1 /* 2 * (C) Copyright 2002 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24 #include <common.h> 25 #include <malloc.h> 26 #include <net.h> 27 #include <asm/io.h> 28 #include <pci.h> 29 #include <miiphy.h> 30 31 #undef DEBUG 32 33 #if defined(CONFIG_CMD_NET) \ 34 && defined(CONFIG_NET_MULTI) && defined(CONFIG_EEPRO100) 35 36 /* Ethernet chip registers. 37 */ 38 #define SCBStatus 0 /* Rx/Command Unit Status *Word* */ 39 #define SCBIntAckByte 1 /* Rx/Command Unit STAT/ACK byte */ 40 #define SCBCmd 2 /* Rx/Command Unit Command *Word* */ 41 #define SCBIntrCtlByte 3 /* Rx/Command Unit Intr.Control Byte */ 42 #define SCBPointer 4 /* General purpose pointer. */ 43 #define SCBPort 8 /* Misc. commands and operands. */ 44 #define SCBflash 12 /* Flash memory control. */ 45 #define SCBeeprom 14 /* EEPROM memory control. */ 46 #define SCBCtrlMDI 16 /* MDI interface control. */ 47 #define SCBEarlyRx 20 /* Early receive byte count. */ 48 #define SCBGenControl 28 /* 82559 General Control Register */ 49 #define SCBGenStatus 29 /* 82559 General Status register */ 50 51 /* 82559 SCB status word defnitions 52 */ 53 #define SCB_STATUS_CX 0x8000 /* CU finished command (transmit) */ 54 #define SCB_STATUS_FR 0x4000 /* frame received */ 55 #define SCB_STATUS_CNA 0x2000 /* CU left active state */ 56 #define SCB_STATUS_RNR 0x1000 /* receiver left ready state */ 57 #define SCB_STATUS_MDI 0x0800 /* MDI read/write cycle done */ 58 #define SCB_STATUS_SWI 0x0400 /* software generated interrupt */ 59 #define SCB_STATUS_FCP 0x0100 /* flow control pause interrupt */ 60 61 #define SCB_INTACK_MASK 0xFD00 /* all the above */ 62 63 #define SCB_INTACK_TX (SCB_STATUS_CX | SCB_STATUS_CNA) 64 #define SCB_INTACK_RX (SCB_STATUS_FR | SCB_STATUS_RNR) 65 66 /* System control block commands 67 */ 68 /* CU Commands */ 69 #define CU_NOP 0x0000 70 #define CU_START 0x0010 71 #define CU_RESUME 0x0020 72 #define CU_STATSADDR 0x0040 /* Load Dump Statistics ctrs addr */ 73 #define CU_SHOWSTATS 0x0050 /* Dump statistics counters. */ 74 #define CU_ADDR_LOAD 0x0060 /* Base address to add to CU commands */ 75 #define CU_DUMPSTATS 0x0070 /* Dump then reset stats counters. */ 76 77 /* RUC Commands */ 78 #define RUC_NOP 0x0000 79 #define RUC_START 0x0001 80 #define RUC_RESUME 0x0002 81 #define RUC_ABORT 0x0004 82 #define RUC_ADDR_LOAD 0x0006 /* (seems not to clear on acceptance) */ 83 #define RUC_RESUMENR 0x0007 84 85 #define CU_CMD_MASK 0x00f0 86 #define RU_CMD_MASK 0x0007 87 88 #define SCB_M 0x0100 /* 0 = enable interrupt, 1 = disable */ 89 #define SCB_SWI 0x0200 /* 1 - cause device to interrupt */ 90 91 #define CU_STATUS_MASK 0x00C0 92 #define RU_STATUS_MASK 0x003C 93 94 #define RU_STATUS_IDLE (0<<2) 95 #define RU_STATUS_SUS (1<<2) 96 #define RU_STATUS_NORES (2<<2) 97 #define RU_STATUS_READY (4<<2) 98 #define RU_STATUS_NO_RBDS_SUS ((1<<2)|(8<<2)) 99 #define RU_STATUS_NO_RBDS_NORES ((2<<2)|(8<<2)) 100 #define RU_STATUS_NO_RBDS_READY ((4<<2)|(8<<2)) 101 102 /* 82559 Port interface commands. 103 */ 104 #define I82559_RESET 0x00000000 /* Software reset */ 105 #define I82559_SELFTEST 0x00000001 /* 82559 Selftest command */ 106 #define I82559_SELECTIVE_RESET 0x00000002 107 #define I82559_DUMP 0x00000003 108 #define I82559_DUMP_WAKEUP 0x00000007 109 110 /* 82559 Eeprom interface. 111 */ 112 #define EE_SHIFT_CLK 0x01 /* EEPROM shift clock. */ 113 #define EE_CS 0x02 /* EEPROM chip select. */ 114 #define EE_DATA_WRITE 0x04 /* EEPROM chip data in. */ 115 #define EE_WRITE_0 0x01 116 #define EE_WRITE_1 0x05 117 #define EE_DATA_READ 0x08 /* EEPROM chip data out. */ 118 #define EE_ENB (0x4800 | EE_CS) 119 #define EE_CMD_BITS 3 120 #define EE_DATA_BITS 16 121 122 /* The EEPROM commands include the alway-set leading bit. 123 */ 124 #define EE_EWENB_CMD (4 << addr_len) 125 #define EE_WRITE_CMD (5 << addr_len) 126 #define EE_READ_CMD (6 << addr_len) 127 #define EE_ERASE_CMD (7 << addr_len) 128 129 /* Receive frame descriptors. 130 */ 131 struct RxFD { 132 volatile u16 status; 133 volatile u16 control; 134 volatile u32 link; /* struct RxFD * */ 135 volatile u32 rx_buf_addr; /* void * */ 136 volatile u32 count; 137 138 volatile u8 data[PKTSIZE_ALIGN]; 139 }; 140 141 #define RFD_STATUS_C 0x8000 /* completion of received frame */ 142 #define RFD_STATUS_OK 0x2000 /* frame received with no errors */ 143 144 #define RFD_CONTROL_EL 0x8000 /* 1=last RFD in RFA */ 145 #define RFD_CONTROL_S 0x4000 /* 1=suspend RU after receiving frame */ 146 #define RFD_CONTROL_H 0x0010 /* 1=RFD is a header RFD */ 147 #define RFD_CONTROL_SF 0x0008 /* 0=simplified, 1=flexible mode */ 148 149 #define RFD_COUNT_MASK 0x3fff 150 #define RFD_COUNT_F 0x4000 151 #define RFD_COUNT_EOF 0x8000 152 153 #define RFD_RX_CRC 0x0800 /* crc error */ 154 #define RFD_RX_ALIGNMENT 0x0400 /* alignment error */ 155 #define RFD_RX_RESOURCE 0x0200 /* out of space, no resources */ 156 #define RFD_RX_DMA_OVER 0x0100 /* DMA overrun */ 157 #define RFD_RX_SHORT 0x0080 /* short frame error */ 158 #define RFD_RX_LENGTH 0x0020 159 #define RFD_RX_ERROR 0x0010 /* receive error */ 160 #define RFD_RX_NO_ADR_MATCH 0x0004 /* no address match */ 161 #define RFD_RX_IA_MATCH 0x0002 /* individual address does not match */ 162 #define RFD_RX_TCO 0x0001 /* TCO indication */ 163 164 /* Transmit frame descriptors 165 */ 166 struct TxFD { /* Transmit frame descriptor set. */ 167 volatile u16 status; 168 volatile u16 command; 169 volatile u32 link; /* void * */ 170 volatile u32 tx_desc_addr; /* Always points to the tx_buf_addr element. */ 171 volatile s32 count; 172 173 volatile u32 tx_buf_addr0; /* void *, frame to be transmitted. */ 174 volatile s32 tx_buf_size0; /* Length of Tx frame. */ 175 volatile u32 tx_buf_addr1; /* void *, frame to be transmitted. */ 176 volatile s32 tx_buf_size1; /* Length of Tx frame. */ 177 }; 178 179 #define TxCB_CMD_TRANSMIT 0x0004 /* transmit command */ 180 #define TxCB_CMD_SF 0x0008 /* 0=simplified, 1=flexible mode */ 181 #define TxCB_CMD_NC 0x0010 /* 0=CRC insert by controller */ 182 #define TxCB_CMD_I 0x2000 /* generate interrupt on completion */ 183 #define TxCB_CMD_S 0x4000 /* suspend on completion */ 184 #define TxCB_CMD_EL 0x8000 /* last command block in CBL */ 185 186 #define TxCB_COUNT_MASK 0x3fff 187 #define TxCB_COUNT_EOF 0x8000 188 189 /* The Speedo3 Rx and Tx frame/buffer descriptors. 190 */ 191 struct descriptor { /* A generic descriptor. */ 192 volatile u16 status; 193 volatile u16 command; 194 volatile u32 link; /* struct descriptor * */ 195 196 unsigned char params[0]; 197 }; 198 199 #define CFG_CMD_EL 0x8000 200 #define CFG_CMD_SUSPEND 0x4000 201 #define CFG_CMD_INT 0x2000 202 #define CFG_CMD_IAS 0x0001 /* individual address setup */ 203 #define CFG_CMD_CONFIGURE 0x0002 /* configure */ 204 205 #define CFG_STATUS_C 0x8000 206 #define CFG_STATUS_OK 0x2000 207 208 /* Misc. 209 */ 210 #define NUM_RX_DESC PKTBUFSRX 211 #define NUM_TX_DESC 1 /* Number of TX descriptors */ 212 213 #define TOUT_LOOP 1000000 214 215 #define ETH_ALEN 6 216 217 static struct RxFD rx_ring[NUM_RX_DESC]; /* RX descriptor ring */ 218 static struct TxFD tx_ring[NUM_TX_DESC]; /* TX descriptor ring */ 219 static int rx_next; /* RX descriptor ring pointer */ 220 static int tx_next; /* TX descriptor ring pointer */ 221 static int tx_threshold; 222 223 /* 224 * The parameters for a CmdConfigure operation. 225 * There are so many options that it would be difficult to document 226 * each bit. We mostly use the default or recommended settings. 227 */ 228 static const char i82557_config_cmd[] = { 229 22, 0x08, 0, 0, 0, 0, 0x32, 0x03, 1, /* 1=Use MII 0=Use AUI */ 230 0, 0x2E, 0, 0x60, 0, 231 0xf2, 0x48, 0, 0x40, 0xf2, 0x80, /* 0x40=Force full-duplex */ 232 0x3f, 0x05, 233 }; 234 static const char i82558_config_cmd[] = { 235 22, 0x08, 0, 1, 0, 0, 0x22, 0x03, 1, /* 1=Use MII 0=Use AUI */ 236 0, 0x2E, 0, 0x60, 0x08, 0x88, 237 0x68, 0, 0x40, 0xf2, 0x84, /* Disable FC */ 238 0x31, 0x05, 239 }; 240 241 static void init_rx_ring (struct eth_device *dev); 242 static void purge_tx_ring (struct eth_device *dev); 243 244 static void read_hw_addr (struct eth_device *dev, bd_t * bis); 245 246 static int eepro100_init (struct eth_device *dev, bd_t * bis); 247 static int eepro100_send (struct eth_device *dev, volatile void *packet, 248 int length); 249 static int eepro100_recv (struct eth_device *dev); 250 static void eepro100_halt (struct eth_device *dev); 251 252 #if defined(CONFIG_E500) || defined(CONFIG_DB64360) || defined(CONFIG_DB64460) 253 #define bus_to_phys(a) (a) 254 #define phys_to_bus(a) (a) 255 #else 256 #define bus_to_phys(a) pci_mem_to_phys((pci_dev_t)dev->priv, a) 257 #define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)dev->priv, a) 258 #endif 259 260 static inline int INW (struct eth_device *dev, u_long addr) 261 { 262 return le16_to_cpu (*(volatile u16 *) (addr + dev->iobase)); 263 } 264 265 static inline void OUTW (struct eth_device *dev, int command, u_long addr) 266 { 267 *(volatile u16 *) ((addr + dev->iobase)) = cpu_to_le16 (command); 268 } 269 270 static inline void OUTL (struct eth_device *dev, int command, u_long addr) 271 { 272 *(volatile u32 *) ((addr + dev->iobase)) = cpu_to_le32 (command); 273 } 274 275 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) 276 static inline int INL (struct eth_device *dev, u_long addr) 277 { 278 return le32_to_cpu (*(volatile u32 *) (addr + dev->iobase)); 279 } 280 281 static int get_phyreg (struct eth_device *dev, unsigned char addr, 282 unsigned char reg, unsigned short *value) 283 { 284 int cmd; 285 int timeout = 50; 286 287 /* read requested data */ 288 cmd = (2 << 26) | ((addr & 0x1f) << 21) | ((reg & 0x1f) << 16); 289 OUTL (dev, cmd, SCBCtrlMDI); 290 291 do { 292 udelay(1000); 293 cmd = INL (dev, SCBCtrlMDI); 294 } while (!(cmd & (1 << 28)) && (--timeout)); 295 296 if (timeout == 0) 297 return -1; 298 299 *value = (unsigned short) (cmd & 0xffff); 300 301 return 0; 302 } 303 304 static int set_phyreg (struct eth_device *dev, unsigned char addr, 305 unsigned char reg, unsigned short value) 306 { 307 int cmd; 308 int timeout = 50; 309 310 /* write requested data */ 311 cmd = (1 << 26) | ((addr & 0x1f) << 21) | ((reg & 0x1f) << 16); 312 OUTL (dev, cmd | value, SCBCtrlMDI); 313 314 while (!(INL (dev, SCBCtrlMDI) & (1 << 28)) && (--timeout)) 315 udelay(1000); 316 317 if (timeout == 0) 318 return -1; 319 320 return 0; 321 } 322 323 /* Check if given phyaddr is valid, i.e. there is a PHY connected. 324 * Do this by checking model value field from ID2 register. 325 */ 326 static struct eth_device* verify_phyaddr (char *devname, unsigned char addr) 327 { 328 struct eth_device *dev; 329 unsigned short value; 330 unsigned char model; 331 332 dev = eth_get_dev_by_name(devname); 333 if (dev == NULL) { 334 printf("%s: no such device\n", devname); 335 return NULL; 336 } 337 338 /* read id2 register */ 339 if (get_phyreg(dev, addr, PHY_PHYIDR2, &value) != 0) { 340 printf("%s: mii read timeout!\n", devname); 341 return NULL; 342 } 343 344 /* get model */ 345 model = (unsigned char)((value >> 4) & 0x003f); 346 347 if (model == 0) { 348 printf("%s: no PHY at address %d\n", devname, addr); 349 return NULL; 350 } 351 352 return dev; 353 } 354 355 static int eepro100_miiphy_read (char *devname, unsigned char addr, 356 unsigned char reg, unsigned short *value) 357 { 358 struct eth_device *dev; 359 360 dev = verify_phyaddr(devname, addr); 361 if (dev == NULL) 362 return -1; 363 364 if (get_phyreg(dev, addr, reg, value) != 0) { 365 printf("%s: mii read timeout!\n", devname); 366 return -1; 367 } 368 369 return 0; 370 } 371 372 static int eepro100_miiphy_write (char *devname, unsigned char addr, 373 unsigned char reg, unsigned short value) 374 { 375 struct eth_device *dev; 376 377 dev = verify_phyaddr(devname, addr); 378 if (dev == NULL) 379 return -1; 380 381 if (set_phyreg(dev, addr, reg, value) != 0) { 382 printf("%s: mii write timeout!\n", devname); 383 return -1; 384 } 385 386 return 0; 387 } 388 389 #endif 390 391 /* Wait for the chip get the command. 392 */ 393 static int wait_for_eepro100 (struct eth_device *dev) 394 { 395 int i; 396 397 for (i = 0; INW (dev, SCBCmd) & (CU_CMD_MASK | RU_CMD_MASK); i++) { 398 if (i >= TOUT_LOOP) { 399 return 0; 400 } 401 } 402 403 return 1; 404 } 405 406 static struct pci_device_id supported[] = { 407 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82557}, 408 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82559}, 409 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82559ER}, 410 {} 411 }; 412 413 int eepro100_initialize (bd_t * bis) 414 { 415 pci_dev_t devno; 416 int card_number = 0; 417 struct eth_device *dev; 418 u32 iobase, status; 419 int idx = 0; 420 421 while (1) { 422 /* Find PCI device 423 */ 424 if ((devno = pci_find_devices (supported, idx++)) < 0) { 425 break; 426 } 427 428 pci_read_config_dword (devno, PCI_BASE_ADDRESS_0, &iobase); 429 iobase &= ~0xf; 430 431 #ifdef DEBUG 432 printf ("eepro100: Intel i82559 PCI EtherExpressPro @0x%x\n", 433 iobase); 434 #endif 435 436 pci_write_config_dword (devno, 437 PCI_COMMAND, 438 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); 439 440 /* Check if I/O accesses and Bus Mastering are enabled. 441 */ 442 pci_read_config_dword (devno, PCI_COMMAND, &status); 443 if (!(status & PCI_COMMAND_MEMORY)) { 444 printf ("Error: Can not enable MEM access.\n"); 445 continue; 446 } 447 448 if (!(status & PCI_COMMAND_MASTER)) { 449 printf ("Error: Can not enable Bus Mastering.\n"); 450 continue; 451 } 452 453 dev = (struct eth_device *) malloc (sizeof *dev); 454 455 sprintf (dev->name, "i82559#%d", card_number); 456 dev->priv = (void *) devno; /* this have to come before bus_to_phys() */ 457 dev->iobase = bus_to_phys (iobase); 458 dev->init = eepro100_init; 459 dev->halt = eepro100_halt; 460 dev->send = eepro100_send; 461 dev->recv = eepro100_recv; 462 463 eth_register (dev); 464 465 #if defined (CONFIG_MII) || defined(CONFIG_CMD_MII) 466 /* register mii command access routines */ 467 miiphy_register(dev->name, 468 eepro100_miiphy_read, eepro100_miiphy_write); 469 #endif 470 471 card_number++; 472 473 /* Set the latency timer for value. 474 */ 475 pci_write_config_byte (devno, PCI_LATENCY_TIMER, 0x20); 476 477 udelay (10 * 1000); 478 479 read_hw_addr (dev, bis); 480 } 481 482 return card_number; 483 } 484 485 486 static int eepro100_init (struct eth_device *dev, bd_t * bis) 487 { 488 int i, status = 0; 489 int tx_cur; 490 struct descriptor *ias_cmd, *cfg_cmd; 491 492 /* Reset the ethernet controller 493 */ 494 OUTL (dev, I82559_SELECTIVE_RESET, SCBPort); 495 udelay (20); 496 497 OUTL (dev, I82559_RESET, SCBPort); 498 udelay (20); 499 500 if (!wait_for_eepro100 (dev)) { 501 printf ("Error: Can not reset ethernet controller.\n"); 502 goto Done; 503 } 504 OUTL (dev, 0, SCBPointer); 505 OUTW (dev, SCB_M | RUC_ADDR_LOAD, SCBCmd); 506 507 if (!wait_for_eepro100 (dev)) { 508 printf ("Error: Can not reset ethernet controller.\n"); 509 goto Done; 510 } 511 OUTL (dev, 0, SCBPointer); 512 OUTW (dev, SCB_M | CU_ADDR_LOAD, SCBCmd); 513 514 /* Initialize Rx and Tx rings. 515 */ 516 init_rx_ring (dev); 517 purge_tx_ring (dev); 518 519 /* Tell the adapter where the RX ring is located. 520 */ 521 if (!wait_for_eepro100 (dev)) { 522 printf ("Error: Can not reset ethernet controller.\n"); 523 goto Done; 524 } 525 526 OUTL (dev, phys_to_bus ((u32) & rx_ring[rx_next]), SCBPointer); 527 OUTW (dev, SCB_M | RUC_START, SCBCmd); 528 529 /* Send the Configure frame */ 530 tx_cur = tx_next; 531 tx_next = ((tx_next + 1) % NUM_TX_DESC); 532 533 cfg_cmd = (struct descriptor *) &tx_ring[tx_cur]; 534 cfg_cmd->command = cpu_to_le16 ((CFG_CMD_SUSPEND | CFG_CMD_CONFIGURE)); 535 cfg_cmd->status = 0; 536 cfg_cmd->link = cpu_to_le32 (phys_to_bus ((u32) & tx_ring[tx_next])); 537 538 memcpy (cfg_cmd->params, i82558_config_cmd, 539 sizeof (i82558_config_cmd)); 540 541 if (!wait_for_eepro100 (dev)) { 542 printf ("Error---CFG_CMD_CONFIGURE: Can not reset ethernet controller.\n"); 543 goto Done; 544 } 545 546 OUTL (dev, phys_to_bus ((u32) & tx_ring[tx_cur]), SCBPointer); 547 OUTW (dev, SCB_M | CU_START, SCBCmd); 548 549 for (i = 0; 550 !(le16_to_cpu (tx_ring[tx_cur].status) & CFG_STATUS_C); 551 i++) { 552 if (i >= TOUT_LOOP) { 553 printf ("%s: Tx error buffer not ready\n", dev->name); 554 goto Done; 555 } 556 } 557 558 if (!(le16_to_cpu (tx_ring[tx_cur].status) & CFG_STATUS_OK)) { 559 printf ("TX error status = 0x%08X\n", 560 le16_to_cpu (tx_ring[tx_cur].status)); 561 goto Done; 562 } 563 564 /* Send the Individual Address Setup frame 565 */ 566 tx_cur = tx_next; 567 tx_next = ((tx_next + 1) % NUM_TX_DESC); 568 569 ias_cmd = (struct descriptor *) &tx_ring[tx_cur]; 570 ias_cmd->command = cpu_to_le16 ((CFG_CMD_SUSPEND | CFG_CMD_IAS)); 571 ias_cmd->status = 0; 572 ias_cmd->link = cpu_to_le32 (phys_to_bus ((u32) & tx_ring[tx_next])); 573 574 memcpy (ias_cmd->params, dev->enetaddr, 6); 575 576 /* Tell the adapter where the TX ring is located. 577 */ 578 if (!wait_for_eepro100 (dev)) { 579 printf ("Error: Can not reset ethernet controller.\n"); 580 goto Done; 581 } 582 583 OUTL (dev, phys_to_bus ((u32) & tx_ring[tx_cur]), SCBPointer); 584 OUTW (dev, SCB_M | CU_START, SCBCmd); 585 586 for (i = 0; !(le16_to_cpu (tx_ring[tx_cur].status) & CFG_STATUS_C); 587 i++) { 588 if (i >= TOUT_LOOP) { 589 printf ("%s: Tx error buffer not ready\n", 590 dev->name); 591 goto Done; 592 } 593 } 594 595 if (!(le16_to_cpu (tx_ring[tx_cur].status) & CFG_STATUS_OK)) { 596 printf ("TX error status = 0x%08X\n", 597 le16_to_cpu (tx_ring[tx_cur].status)); 598 goto Done; 599 } 600 601 status = 1; 602 603 Done: 604 return status; 605 } 606 607 static int eepro100_send (struct eth_device *dev, volatile void *packet, int length) 608 { 609 int i, status = -1; 610 int tx_cur; 611 612 if (length <= 0) { 613 printf ("%s: bad packet size: %d\n", dev->name, length); 614 goto Done; 615 } 616 617 tx_cur = tx_next; 618 tx_next = (tx_next + 1) % NUM_TX_DESC; 619 620 tx_ring[tx_cur].command = cpu_to_le16 ( TxCB_CMD_TRANSMIT | 621 TxCB_CMD_SF | 622 TxCB_CMD_S | 623 TxCB_CMD_EL ); 624 tx_ring[tx_cur].status = 0; 625 tx_ring[tx_cur].count = cpu_to_le32 (tx_threshold); 626 tx_ring[tx_cur].link = 627 cpu_to_le32 (phys_to_bus ((u32) & tx_ring[tx_next])); 628 tx_ring[tx_cur].tx_desc_addr = 629 cpu_to_le32 (phys_to_bus ((u32) & tx_ring[tx_cur].tx_buf_addr0)); 630 tx_ring[tx_cur].tx_buf_addr0 = 631 cpu_to_le32 (phys_to_bus ((u_long) packet)); 632 tx_ring[tx_cur].tx_buf_size0 = cpu_to_le32 (length); 633 634 if (!wait_for_eepro100 (dev)) { 635 printf ("%s: Tx error ethernet controller not ready.\n", 636 dev->name); 637 goto Done; 638 } 639 640 /* Send the packet. 641 */ 642 OUTL (dev, phys_to_bus ((u32) & tx_ring[tx_cur]), SCBPointer); 643 OUTW (dev, SCB_M | CU_START, SCBCmd); 644 645 for (i = 0; !(le16_to_cpu (tx_ring[tx_cur].status) & CFG_STATUS_C); 646 i++) { 647 if (i >= TOUT_LOOP) { 648 printf ("%s: Tx error buffer not ready\n", dev->name); 649 goto Done; 650 } 651 } 652 653 if (!(le16_to_cpu (tx_ring[tx_cur].status) & CFG_STATUS_OK)) { 654 printf ("TX error status = 0x%08X\n", 655 le16_to_cpu (tx_ring[tx_cur].status)); 656 goto Done; 657 } 658 659 status = length; 660 661 Done: 662 return status; 663 } 664 665 static int eepro100_recv (struct eth_device *dev) 666 { 667 u16 status, stat; 668 int rx_prev, length = 0; 669 670 stat = INW (dev, SCBStatus); 671 OUTW (dev, stat & SCB_STATUS_RNR, SCBStatus); 672 673 for (;;) { 674 status = le16_to_cpu (rx_ring[rx_next].status); 675 676 if (!(status & RFD_STATUS_C)) { 677 break; 678 } 679 680 /* Valid frame status. 681 */ 682 if ((status & RFD_STATUS_OK)) { 683 /* A valid frame received. 684 */ 685 length = le32_to_cpu (rx_ring[rx_next].count) & 0x3fff; 686 687 /* Pass the packet up to the protocol 688 * layers. 689 */ 690 NetReceive (rx_ring[rx_next].data, length); 691 } else { 692 /* There was an error. 693 */ 694 printf ("RX error status = 0x%08X\n", status); 695 } 696 697 rx_ring[rx_next].control = cpu_to_le16 (RFD_CONTROL_S); 698 rx_ring[rx_next].status = 0; 699 rx_ring[rx_next].count = cpu_to_le32 (PKTSIZE_ALIGN << 16); 700 701 rx_prev = (rx_next + NUM_RX_DESC - 1) % NUM_RX_DESC; 702 rx_ring[rx_prev].control = 0; 703 704 /* Update entry information. 705 */ 706 rx_next = (rx_next + 1) % NUM_RX_DESC; 707 } 708 709 if (stat & SCB_STATUS_RNR) { 710 711 printf ("%s: Receiver is not ready, restart it !\n", dev->name); 712 713 /* Reinitialize Rx ring. 714 */ 715 init_rx_ring (dev); 716 717 if (!wait_for_eepro100 (dev)) { 718 printf ("Error: Can not restart ethernet controller.\n"); 719 goto Done; 720 } 721 722 OUTL (dev, phys_to_bus ((u32) & rx_ring[rx_next]), SCBPointer); 723 OUTW (dev, SCB_M | RUC_START, SCBCmd); 724 } 725 726 Done: 727 return length; 728 } 729 730 static void eepro100_halt (struct eth_device *dev) 731 { 732 /* Reset the ethernet controller 733 */ 734 OUTL (dev, I82559_SELECTIVE_RESET, SCBPort); 735 udelay (20); 736 737 OUTL (dev, I82559_RESET, SCBPort); 738 udelay (20); 739 740 if (!wait_for_eepro100 (dev)) { 741 printf ("Error: Can not reset ethernet controller.\n"); 742 goto Done; 743 } 744 OUTL (dev, 0, SCBPointer); 745 OUTW (dev, SCB_M | RUC_ADDR_LOAD, SCBCmd); 746 747 if (!wait_for_eepro100 (dev)) { 748 printf ("Error: Can not reset ethernet controller.\n"); 749 goto Done; 750 } 751 OUTL (dev, 0, SCBPointer); 752 OUTW (dev, SCB_M | CU_ADDR_LOAD, SCBCmd); 753 754 Done: 755 return; 756 } 757 758 /* SROM Read. 759 */ 760 static int read_eeprom (struct eth_device *dev, int location, int addr_len) 761 { 762 unsigned short retval = 0; 763 int read_cmd = location | EE_READ_CMD; 764 int i; 765 766 OUTW (dev, EE_ENB & ~EE_CS, SCBeeprom); 767 OUTW (dev, EE_ENB, SCBeeprom); 768 769 /* Shift the read command bits out. */ 770 for (i = 12; i >= 0; i--) { 771 short dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0; 772 773 OUTW (dev, EE_ENB | dataval, SCBeeprom); 774 udelay (1); 775 OUTW (dev, EE_ENB | dataval | EE_SHIFT_CLK, SCBeeprom); 776 udelay (1); 777 } 778 OUTW (dev, EE_ENB, SCBeeprom); 779 780 for (i = 15; i >= 0; i--) { 781 OUTW (dev, EE_ENB | EE_SHIFT_CLK, SCBeeprom); 782 udelay (1); 783 retval = (retval << 1) | 784 ((INW (dev, SCBeeprom) & EE_DATA_READ) ? 1 : 0); 785 OUTW (dev, EE_ENB, SCBeeprom); 786 udelay (1); 787 } 788 789 /* Terminate the EEPROM access. */ 790 OUTW (dev, EE_ENB & ~EE_CS, SCBeeprom); 791 return retval; 792 } 793 794 #ifdef CONFIG_EEPRO100_SROM_WRITE 795 int eepro100_write_eeprom (struct eth_device* dev, int location, int addr_len, unsigned short data) 796 { 797 unsigned short dataval; 798 int enable_cmd = 0x3f | EE_EWENB_CMD; 799 int write_cmd = location | EE_WRITE_CMD; 800 int i; 801 unsigned long datalong, tmplong; 802 803 OUTW(dev, EE_ENB & ~EE_CS, SCBeeprom); 804 udelay(1); 805 OUTW(dev, EE_ENB, SCBeeprom); 806 807 /* Shift the enable command bits out. */ 808 for (i = (addr_len+EE_CMD_BITS-1); i >= 0; i--) 809 { 810 dataval = (enable_cmd & (1 << i)) ? EE_DATA_WRITE : 0; 811 OUTW(dev, EE_ENB | dataval, SCBeeprom); 812 udelay(1); 813 OUTW(dev, EE_ENB | dataval | EE_SHIFT_CLK, SCBeeprom); 814 udelay(1); 815 } 816 817 OUTW(dev, EE_ENB, SCBeeprom); 818 udelay(1); 819 OUTW(dev, EE_ENB & ~EE_CS, SCBeeprom); 820 udelay(1); 821 OUTW(dev, EE_ENB, SCBeeprom); 822 823 824 /* Shift the write command bits out. */ 825 for (i = (addr_len+EE_CMD_BITS-1); i >= 0; i--) 826 { 827 dataval = (write_cmd & (1 << i)) ? EE_DATA_WRITE : 0; 828 OUTW(dev, EE_ENB | dataval, SCBeeprom); 829 udelay(1); 830 OUTW(dev, EE_ENB | dataval | EE_SHIFT_CLK, SCBeeprom); 831 udelay(1); 832 } 833 834 /* Write the data */ 835 datalong= (unsigned long) ((((data) & 0x00ff) << 8) | ( (data) >> 8)); 836 837 for (i = 0; i< EE_DATA_BITS; i++) 838 { 839 /* Extract and move data bit to bit DI */ 840 dataval = ((datalong & 0x8000)>>13) ? EE_DATA_WRITE : 0; 841 842 OUTW(dev, EE_ENB | dataval, SCBeeprom); 843 udelay(1); 844 OUTW(dev, EE_ENB | dataval | EE_SHIFT_CLK, SCBeeprom); 845 udelay(1); 846 OUTW(dev, EE_ENB | dataval, SCBeeprom); 847 udelay(1); 848 849 datalong = datalong << 1; /* Adjust significant data bit*/ 850 } 851 852 /* Finish up command (toggle CS) */ 853 OUTW(dev, EE_ENB & ~EE_CS, SCBeeprom); 854 udelay(1); /* delay for more than 250 ns */ 855 OUTW(dev, EE_ENB, SCBeeprom); 856 857 /* Wait for programming ready (D0 = 1) */ 858 tmplong = 10; 859 do 860 { 861 dataval = INW(dev, SCBeeprom); 862 if (dataval & EE_DATA_READ) 863 break; 864 udelay(10000); 865 } 866 while (-- tmplong); 867 868 if (tmplong == 0) 869 { 870 printf ("Write i82559 eeprom timed out (100 ms waiting for data ready.\n"); 871 return -1; 872 } 873 874 /* Terminate the EEPROM access. */ 875 OUTW(dev, EE_ENB & ~EE_CS, SCBeeprom); 876 877 return 0; 878 } 879 #endif 880 881 static void init_rx_ring (struct eth_device *dev) 882 { 883 int i; 884 885 for (i = 0; i < NUM_RX_DESC; i++) { 886 rx_ring[i].status = 0; 887 rx_ring[i].control = 888 (i == NUM_RX_DESC - 1) ? cpu_to_le16 (RFD_CONTROL_S) : 0; 889 rx_ring[i].link = 890 cpu_to_le32 (phys_to_bus 891 ((u32) & rx_ring[(i + 1) % NUM_RX_DESC])); 892 rx_ring[i].rx_buf_addr = 0xffffffff; 893 rx_ring[i].count = cpu_to_le32 (PKTSIZE_ALIGN << 16); 894 } 895 896 rx_next = 0; 897 } 898 899 static void purge_tx_ring (struct eth_device *dev) 900 { 901 int i; 902 903 tx_next = 0; 904 tx_threshold = 0x01208000; 905 906 for (i = 0; i < NUM_TX_DESC; i++) { 907 tx_ring[i].status = 0; 908 tx_ring[i].command = 0; 909 tx_ring[i].link = 0; 910 tx_ring[i].tx_desc_addr = 0; 911 tx_ring[i].count = 0; 912 913 tx_ring[i].tx_buf_addr0 = 0; 914 tx_ring[i].tx_buf_size0 = 0; 915 tx_ring[i].tx_buf_addr1 = 0; 916 tx_ring[i].tx_buf_size1 = 0; 917 } 918 } 919 920 static void read_hw_addr (struct eth_device *dev, bd_t * bis) 921 { 922 u16 eeprom[0x40]; 923 u16 sum = 0; 924 int i, j; 925 int addr_len = read_eeprom (dev, 0, 6) == 0xffff ? 8 : 6; 926 927 for (j = 0, i = 0; i < 0x40; i++) { 928 u16 value = read_eeprom (dev, i, addr_len); 929 930 eeprom[i] = value; 931 sum += value; 932 if (i < 3) { 933 dev->enetaddr[j++] = value; 934 dev->enetaddr[j++] = value >> 8; 935 } 936 } 937 938 if (sum != 0xBABA) { 939 memset (dev->enetaddr, 0, ETH_ALEN); 940 #ifdef DEBUG 941 printf ("%s: Invalid EEPROM checksum %#4.4x, " 942 "check settings before activating this device!\n", 943 dev->name, sum); 944 #endif 945 } 946 } 947 948 #endif 949