1 /* 2 * (C) Copyright 2002 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24 #include <common.h> 25 #include <malloc.h> 26 #include <net.h> 27 #include <asm/io.h> 28 #include <pci.h> 29 #include <miiphy.h> 30 31 #undef DEBUG 32 33 /* Ethernet chip registers. 34 */ 35 #define SCBStatus 0 /* Rx/Command Unit Status *Word* */ 36 #define SCBIntAckByte 1 /* Rx/Command Unit STAT/ACK byte */ 37 #define SCBCmd 2 /* Rx/Command Unit Command *Word* */ 38 #define SCBIntrCtlByte 3 /* Rx/Command Unit Intr.Control Byte */ 39 #define SCBPointer 4 /* General purpose pointer. */ 40 #define SCBPort 8 /* Misc. commands and operands. */ 41 #define SCBflash 12 /* Flash memory control. */ 42 #define SCBeeprom 14 /* EEPROM memory control. */ 43 #define SCBCtrlMDI 16 /* MDI interface control. */ 44 #define SCBEarlyRx 20 /* Early receive byte count. */ 45 #define SCBGenControl 28 /* 82559 General Control Register */ 46 #define SCBGenStatus 29 /* 82559 General Status register */ 47 48 /* 82559 SCB status word defnitions 49 */ 50 #define SCB_STATUS_CX 0x8000 /* CU finished command (transmit) */ 51 #define SCB_STATUS_FR 0x4000 /* frame received */ 52 #define SCB_STATUS_CNA 0x2000 /* CU left active state */ 53 #define SCB_STATUS_RNR 0x1000 /* receiver left ready state */ 54 #define SCB_STATUS_MDI 0x0800 /* MDI read/write cycle done */ 55 #define SCB_STATUS_SWI 0x0400 /* software generated interrupt */ 56 #define SCB_STATUS_FCP 0x0100 /* flow control pause interrupt */ 57 58 #define SCB_INTACK_MASK 0xFD00 /* all the above */ 59 60 #define SCB_INTACK_TX (SCB_STATUS_CX | SCB_STATUS_CNA) 61 #define SCB_INTACK_RX (SCB_STATUS_FR | SCB_STATUS_RNR) 62 63 /* System control block commands 64 */ 65 /* CU Commands */ 66 #define CU_NOP 0x0000 67 #define CU_START 0x0010 68 #define CU_RESUME 0x0020 69 #define CU_STATSADDR 0x0040 /* Load Dump Statistics ctrs addr */ 70 #define CU_SHOWSTATS 0x0050 /* Dump statistics counters. */ 71 #define CU_ADDR_LOAD 0x0060 /* Base address to add to CU commands */ 72 #define CU_DUMPSTATS 0x0070 /* Dump then reset stats counters. */ 73 74 /* RUC Commands */ 75 #define RUC_NOP 0x0000 76 #define RUC_START 0x0001 77 #define RUC_RESUME 0x0002 78 #define RUC_ABORT 0x0004 79 #define RUC_ADDR_LOAD 0x0006 /* (seems not to clear on acceptance) */ 80 #define RUC_RESUMENR 0x0007 81 82 #define CU_CMD_MASK 0x00f0 83 #define RU_CMD_MASK 0x0007 84 85 #define SCB_M 0x0100 /* 0 = enable interrupt, 1 = disable */ 86 #define SCB_SWI 0x0200 /* 1 - cause device to interrupt */ 87 88 #define CU_STATUS_MASK 0x00C0 89 #define RU_STATUS_MASK 0x003C 90 91 #define RU_STATUS_IDLE (0<<2) 92 #define RU_STATUS_SUS (1<<2) 93 #define RU_STATUS_NORES (2<<2) 94 #define RU_STATUS_READY (4<<2) 95 #define RU_STATUS_NO_RBDS_SUS ((1<<2)|(8<<2)) 96 #define RU_STATUS_NO_RBDS_NORES ((2<<2)|(8<<2)) 97 #define RU_STATUS_NO_RBDS_READY ((4<<2)|(8<<2)) 98 99 /* 82559 Port interface commands. 100 */ 101 #define I82559_RESET 0x00000000 /* Software reset */ 102 #define I82559_SELFTEST 0x00000001 /* 82559 Selftest command */ 103 #define I82559_SELECTIVE_RESET 0x00000002 104 #define I82559_DUMP 0x00000003 105 #define I82559_DUMP_WAKEUP 0x00000007 106 107 /* 82559 Eeprom interface. 108 */ 109 #define EE_SHIFT_CLK 0x01 /* EEPROM shift clock. */ 110 #define EE_CS 0x02 /* EEPROM chip select. */ 111 #define EE_DATA_WRITE 0x04 /* EEPROM chip data in. */ 112 #define EE_WRITE_0 0x01 113 #define EE_WRITE_1 0x05 114 #define EE_DATA_READ 0x08 /* EEPROM chip data out. */ 115 #define EE_ENB (0x4800 | EE_CS) 116 #define EE_CMD_BITS 3 117 #define EE_DATA_BITS 16 118 119 /* The EEPROM commands include the alway-set leading bit. 120 */ 121 #define EE_EWENB_CMD (4 << addr_len) 122 #define EE_WRITE_CMD (5 << addr_len) 123 #define EE_READ_CMD (6 << addr_len) 124 #define EE_ERASE_CMD (7 << addr_len) 125 126 /* Receive frame descriptors. 127 */ 128 struct RxFD { 129 volatile u16 status; 130 volatile u16 control; 131 volatile u32 link; /* struct RxFD * */ 132 volatile u32 rx_buf_addr; /* void * */ 133 volatile u32 count; 134 135 volatile u8 data[PKTSIZE_ALIGN]; 136 }; 137 138 #define RFD_STATUS_C 0x8000 /* completion of received frame */ 139 #define RFD_STATUS_OK 0x2000 /* frame received with no errors */ 140 141 #define RFD_CONTROL_EL 0x8000 /* 1=last RFD in RFA */ 142 #define RFD_CONTROL_S 0x4000 /* 1=suspend RU after receiving frame */ 143 #define RFD_CONTROL_H 0x0010 /* 1=RFD is a header RFD */ 144 #define RFD_CONTROL_SF 0x0008 /* 0=simplified, 1=flexible mode */ 145 146 #define RFD_COUNT_MASK 0x3fff 147 #define RFD_COUNT_F 0x4000 148 #define RFD_COUNT_EOF 0x8000 149 150 #define RFD_RX_CRC 0x0800 /* crc error */ 151 #define RFD_RX_ALIGNMENT 0x0400 /* alignment error */ 152 #define RFD_RX_RESOURCE 0x0200 /* out of space, no resources */ 153 #define RFD_RX_DMA_OVER 0x0100 /* DMA overrun */ 154 #define RFD_RX_SHORT 0x0080 /* short frame error */ 155 #define RFD_RX_LENGTH 0x0020 156 #define RFD_RX_ERROR 0x0010 /* receive error */ 157 #define RFD_RX_NO_ADR_MATCH 0x0004 /* no address match */ 158 #define RFD_RX_IA_MATCH 0x0002 /* individual address does not match */ 159 #define RFD_RX_TCO 0x0001 /* TCO indication */ 160 161 /* Transmit frame descriptors 162 */ 163 struct TxFD { /* Transmit frame descriptor set. */ 164 volatile u16 status; 165 volatile u16 command; 166 volatile u32 link; /* void * */ 167 volatile u32 tx_desc_addr; /* Always points to the tx_buf_addr element. */ 168 volatile s32 count; 169 170 volatile u32 tx_buf_addr0; /* void *, frame to be transmitted. */ 171 volatile s32 tx_buf_size0; /* Length of Tx frame. */ 172 volatile u32 tx_buf_addr1; /* void *, frame to be transmitted. */ 173 volatile s32 tx_buf_size1; /* Length of Tx frame. */ 174 }; 175 176 #define TxCB_CMD_TRANSMIT 0x0004 /* transmit command */ 177 #define TxCB_CMD_SF 0x0008 /* 0=simplified, 1=flexible mode */ 178 #define TxCB_CMD_NC 0x0010 /* 0=CRC insert by controller */ 179 #define TxCB_CMD_I 0x2000 /* generate interrupt on completion */ 180 #define TxCB_CMD_S 0x4000 /* suspend on completion */ 181 #define TxCB_CMD_EL 0x8000 /* last command block in CBL */ 182 183 #define TxCB_COUNT_MASK 0x3fff 184 #define TxCB_COUNT_EOF 0x8000 185 186 /* The Speedo3 Rx and Tx frame/buffer descriptors. 187 */ 188 struct descriptor { /* A generic descriptor. */ 189 volatile u16 status; 190 volatile u16 command; 191 volatile u32 link; /* struct descriptor * */ 192 193 unsigned char params[0]; 194 }; 195 196 #define CFG_CMD_EL 0x8000 197 #define CFG_CMD_SUSPEND 0x4000 198 #define CFG_CMD_INT 0x2000 199 #define CFG_CMD_IAS 0x0001 /* individual address setup */ 200 #define CFG_CMD_CONFIGURE 0x0002 /* configure */ 201 202 #define CFG_STATUS_C 0x8000 203 #define CFG_STATUS_OK 0x2000 204 205 /* Misc. 206 */ 207 #define NUM_RX_DESC PKTBUFSRX 208 #define NUM_TX_DESC 1 /* Number of TX descriptors */ 209 210 #define TOUT_LOOP 1000000 211 212 #define ETH_ALEN 6 213 214 static struct RxFD rx_ring[NUM_RX_DESC]; /* RX descriptor ring */ 215 static struct TxFD tx_ring[NUM_TX_DESC]; /* TX descriptor ring */ 216 static int rx_next; /* RX descriptor ring pointer */ 217 static int tx_next; /* TX descriptor ring pointer */ 218 static int tx_threshold; 219 220 /* 221 * The parameters for a CmdConfigure operation. 222 * There are so many options that it would be difficult to document 223 * each bit. We mostly use the default or recommended settings. 224 */ 225 static const char i82557_config_cmd[] = { 226 22, 0x08, 0, 0, 0, 0, 0x32, 0x03, 1, /* 1=Use MII 0=Use AUI */ 227 0, 0x2E, 0, 0x60, 0, 228 0xf2, 0x48, 0, 0x40, 0xf2, 0x80, /* 0x40=Force full-duplex */ 229 0x3f, 0x05, 230 }; 231 static const char i82558_config_cmd[] = { 232 22, 0x08, 0, 1, 0, 0, 0x22, 0x03, 1, /* 1=Use MII 0=Use AUI */ 233 0, 0x2E, 0, 0x60, 0x08, 0x88, 234 0x68, 0, 0x40, 0xf2, 0x84, /* Disable FC */ 235 0x31, 0x05, 236 }; 237 238 static void init_rx_ring (struct eth_device *dev); 239 static void purge_tx_ring (struct eth_device *dev); 240 241 static void read_hw_addr (struct eth_device *dev, bd_t * bis); 242 243 static int eepro100_init (struct eth_device *dev, bd_t * bis); 244 static int eepro100_send (struct eth_device *dev, volatile void *packet, 245 int length); 246 static int eepro100_recv (struct eth_device *dev); 247 static void eepro100_halt (struct eth_device *dev); 248 249 #if defined(CONFIG_E500) || defined(CONFIG_DB64360) || defined(CONFIG_DB64460) 250 #define bus_to_phys(a) (a) 251 #define phys_to_bus(a) (a) 252 #else 253 #define bus_to_phys(a) pci_mem_to_phys((pci_dev_t)dev->priv, a) 254 #define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)dev->priv, a) 255 #endif 256 257 static inline int INW (struct eth_device *dev, u_long addr) 258 { 259 return le16_to_cpu (*(volatile u16 *) (addr + dev->iobase)); 260 } 261 262 static inline void OUTW (struct eth_device *dev, int command, u_long addr) 263 { 264 *(volatile u16 *) ((addr + dev->iobase)) = cpu_to_le16 (command); 265 } 266 267 static inline void OUTL (struct eth_device *dev, int command, u_long addr) 268 { 269 *(volatile u32 *) ((addr + dev->iobase)) = cpu_to_le32 (command); 270 } 271 272 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) 273 static inline int INL (struct eth_device *dev, u_long addr) 274 { 275 return le32_to_cpu (*(volatile u32 *) (addr + dev->iobase)); 276 } 277 278 static int get_phyreg (struct eth_device *dev, unsigned char addr, 279 unsigned char reg, unsigned short *value) 280 { 281 int cmd; 282 int timeout = 50; 283 284 /* read requested data */ 285 cmd = (2 << 26) | ((addr & 0x1f) << 21) | ((reg & 0x1f) << 16); 286 OUTL (dev, cmd, SCBCtrlMDI); 287 288 do { 289 udelay(1000); 290 cmd = INL (dev, SCBCtrlMDI); 291 } while (!(cmd & (1 << 28)) && (--timeout)); 292 293 if (timeout == 0) 294 return -1; 295 296 *value = (unsigned short) (cmd & 0xffff); 297 298 return 0; 299 } 300 301 static int set_phyreg (struct eth_device *dev, unsigned char addr, 302 unsigned char reg, unsigned short value) 303 { 304 int cmd; 305 int timeout = 50; 306 307 /* write requested data */ 308 cmd = (1 << 26) | ((addr & 0x1f) << 21) | ((reg & 0x1f) << 16); 309 OUTL (dev, cmd | value, SCBCtrlMDI); 310 311 while (!(INL (dev, SCBCtrlMDI) & (1 << 28)) && (--timeout)) 312 udelay(1000); 313 314 if (timeout == 0) 315 return -1; 316 317 return 0; 318 } 319 320 /* Check if given phyaddr is valid, i.e. there is a PHY connected. 321 * Do this by checking model value field from ID2 register. 322 */ 323 static struct eth_device* verify_phyaddr (char *devname, unsigned char addr) 324 { 325 struct eth_device *dev; 326 unsigned short value; 327 unsigned char model; 328 329 dev = eth_get_dev_by_name(devname); 330 if (dev == NULL) { 331 printf("%s: no such device\n", devname); 332 return NULL; 333 } 334 335 /* read id2 register */ 336 if (get_phyreg(dev, addr, PHY_PHYIDR2, &value) != 0) { 337 printf("%s: mii read timeout!\n", devname); 338 return NULL; 339 } 340 341 /* get model */ 342 model = (unsigned char)((value >> 4) & 0x003f); 343 344 if (model == 0) { 345 printf("%s: no PHY at address %d\n", devname, addr); 346 return NULL; 347 } 348 349 return dev; 350 } 351 352 static int eepro100_miiphy_read (char *devname, unsigned char addr, 353 unsigned char reg, unsigned short *value) 354 { 355 struct eth_device *dev; 356 357 dev = verify_phyaddr(devname, addr); 358 if (dev == NULL) 359 return -1; 360 361 if (get_phyreg(dev, addr, reg, value) != 0) { 362 printf("%s: mii read timeout!\n", devname); 363 return -1; 364 } 365 366 return 0; 367 } 368 369 static int eepro100_miiphy_write (char *devname, unsigned char addr, 370 unsigned char reg, unsigned short value) 371 { 372 struct eth_device *dev; 373 374 dev = verify_phyaddr(devname, addr); 375 if (dev == NULL) 376 return -1; 377 378 if (set_phyreg(dev, addr, reg, value) != 0) { 379 printf("%s: mii write timeout!\n", devname); 380 return -1; 381 } 382 383 return 0; 384 } 385 386 #endif 387 388 /* Wait for the chip get the command. 389 */ 390 static int wait_for_eepro100 (struct eth_device *dev) 391 { 392 int i; 393 394 for (i = 0; INW (dev, SCBCmd) & (CU_CMD_MASK | RU_CMD_MASK); i++) { 395 if (i >= TOUT_LOOP) { 396 return 0; 397 } 398 } 399 400 return 1; 401 } 402 403 static struct pci_device_id supported[] = { 404 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82557}, 405 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82559}, 406 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82559ER}, 407 {} 408 }; 409 410 int eepro100_initialize (bd_t * bis) 411 { 412 pci_dev_t devno; 413 int card_number = 0; 414 struct eth_device *dev; 415 u32 iobase, status; 416 int idx = 0; 417 418 while (1) { 419 /* Find PCI device 420 */ 421 if ((devno = pci_find_devices (supported, idx++)) < 0) { 422 break; 423 } 424 425 pci_read_config_dword (devno, PCI_BASE_ADDRESS_0, &iobase); 426 iobase &= ~0xf; 427 428 #ifdef DEBUG 429 printf ("eepro100: Intel i82559 PCI EtherExpressPro @0x%x\n", 430 iobase); 431 #endif 432 433 pci_write_config_dword (devno, 434 PCI_COMMAND, 435 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); 436 437 /* Check if I/O accesses and Bus Mastering are enabled. 438 */ 439 pci_read_config_dword (devno, PCI_COMMAND, &status); 440 if (!(status & PCI_COMMAND_MEMORY)) { 441 printf ("Error: Can not enable MEM access.\n"); 442 continue; 443 } 444 445 if (!(status & PCI_COMMAND_MASTER)) { 446 printf ("Error: Can not enable Bus Mastering.\n"); 447 continue; 448 } 449 450 dev = (struct eth_device *) malloc (sizeof *dev); 451 452 sprintf (dev->name, "i82559#%d", card_number); 453 dev->priv = (void *) devno; /* this have to come before bus_to_phys() */ 454 dev->iobase = bus_to_phys (iobase); 455 dev->init = eepro100_init; 456 dev->halt = eepro100_halt; 457 dev->send = eepro100_send; 458 dev->recv = eepro100_recv; 459 460 eth_register (dev); 461 462 #if defined (CONFIG_MII) || defined(CONFIG_CMD_MII) 463 /* register mii command access routines */ 464 miiphy_register(dev->name, 465 eepro100_miiphy_read, eepro100_miiphy_write); 466 #endif 467 468 card_number++; 469 470 /* Set the latency timer for value. 471 */ 472 pci_write_config_byte (devno, PCI_LATENCY_TIMER, 0x20); 473 474 udelay (10 * 1000); 475 476 read_hw_addr (dev, bis); 477 } 478 479 return card_number; 480 } 481 482 483 static int eepro100_init (struct eth_device *dev, bd_t * bis) 484 { 485 int i, status = -1; 486 int tx_cur; 487 struct descriptor *ias_cmd, *cfg_cmd; 488 489 /* Reset the ethernet controller 490 */ 491 OUTL (dev, I82559_SELECTIVE_RESET, SCBPort); 492 udelay (20); 493 494 OUTL (dev, I82559_RESET, SCBPort); 495 udelay (20); 496 497 if (!wait_for_eepro100 (dev)) { 498 printf ("Error: Can not reset ethernet controller.\n"); 499 goto Done; 500 } 501 OUTL (dev, 0, SCBPointer); 502 OUTW (dev, SCB_M | RUC_ADDR_LOAD, SCBCmd); 503 504 if (!wait_for_eepro100 (dev)) { 505 printf ("Error: Can not reset ethernet controller.\n"); 506 goto Done; 507 } 508 OUTL (dev, 0, SCBPointer); 509 OUTW (dev, SCB_M | CU_ADDR_LOAD, SCBCmd); 510 511 /* Initialize Rx and Tx rings. 512 */ 513 init_rx_ring (dev); 514 purge_tx_ring (dev); 515 516 /* Tell the adapter where the RX ring is located. 517 */ 518 if (!wait_for_eepro100 (dev)) { 519 printf ("Error: Can not reset ethernet controller.\n"); 520 goto Done; 521 } 522 523 OUTL (dev, phys_to_bus ((u32) & rx_ring[rx_next]), SCBPointer); 524 OUTW (dev, SCB_M | RUC_START, SCBCmd); 525 526 /* Send the Configure frame */ 527 tx_cur = tx_next; 528 tx_next = ((tx_next + 1) % NUM_TX_DESC); 529 530 cfg_cmd = (struct descriptor *) &tx_ring[tx_cur]; 531 cfg_cmd->command = cpu_to_le16 ((CFG_CMD_SUSPEND | CFG_CMD_CONFIGURE)); 532 cfg_cmd->status = 0; 533 cfg_cmd->link = cpu_to_le32 (phys_to_bus ((u32) & tx_ring[tx_next])); 534 535 memcpy (cfg_cmd->params, i82558_config_cmd, 536 sizeof (i82558_config_cmd)); 537 538 if (!wait_for_eepro100 (dev)) { 539 printf ("Error---CFG_CMD_CONFIGURE: Can not reset ethernet controller.\n"); 540 goto Done; 541 } 542 543 OUTL (dev, phys_to_bus ((u32) & tx_ring[tx_cur]), SCBPointer); 544 OUTW (dev, SCB_M | CU_START, SCBCmd); 545 546 for (i = 0; 547 !(le16_to_cpu (tx_ring[tx_cur].status) & CFG_STATUS_C); 548 i++) { 549 if (i >= TOUT_LOOP) { 550 printf ("%s: Tx error buffer not ready\n", dev->name); 551 goto Done; 552 } 553 } 554 555 if (!(le16_to_cpu (tx_ring[tx_cur].status) & CFG_STATUS_OK)) { 556 printf ("TX error status = 0x%08X\n", 557 le16_to_cpu (tx_ring[tx_cur].status)); 558 goto Done; 559 } 560 561 /* Send the Individual Address Setup frame 562 */ 563 tx_cur = tx_next; 564 tx_next = ((tx_next + 1) % NUM_TX_DESC); 565 566 ias_cmd = (struct descriptor *) &tx_ring[tx_cur]; 567 ias_cmd->command = cpu_to_le16 ((CFG_CMD_SUSPEND | CFG_CMD_IAS)); 568 ias_cmd->status = 0; 569 ias_cmd->link = cpu_to_le32 (phys_to_bus ((u32) & tx_ring[tx_next])); 570 571 memcpy (ias_cmd->params, dev->enetaddr, 6); 572 573 /* Tell the adapter where the TX ring is located. 574 */ 575 if (!wait_for_eepro100 (dev)) { 576 printf ("Error: Can not reset ethernet controller.\n"); 577 goto Done; 578 } 579 580 OUTL (dev, phys_to_bus ((u32) & tx_ring[tx_cur]), SCBPointer); 581 OUTW (dev, SCB_M | CU_START, SCBCmd); 582 583 for (i = 0; !(le16_to_cpu (tx_ring[tx_cur].status) & CFG_STATUS_C); 584 i++) { 585 if (i >= TOUT_LOOP) { 586 printf ("%s: Tx error buffer not ready\n", 587 dev->name); 588 goto Done; 589 } 590 } 591 592 if (!(le16_to_cpu (tx_ring[tx_cur].status) & CFG_STATUS_OK)) { 593 printf ("TX error status = 0x%08X\n", 594 le16_to_cpu (tx_ring[tx_cur].status)); 595 goto Done; 596 } 597 598 status = 0; 599 600 Done: 601 return status; 602 } 603 604 static int eepro100_send (struct eth_device *dev, volatile void *packet, int length) 605 { 606 int i, status = -1; 607 int tx_cur; 608 609 if (length <= 0) { 610 printf ("%s: bad packet size: %d\n", dev->name, length); 611 goto Done; 612 } 613 614 tx_cur = tx_next; 615 tx_next = (tx_next + 1) % NUM_TX_DESC; 616 617 tx_ring[tx_cur].command = cpu_to_le16 ( TxCB_CMD_TRANSMIT | 618 TxCB_CMD_SF | 619 TxCB_CMD_S | 620 TxCB_CMD_EL ); 621 tx_ring[tx_cur].status = 0; 622 tx_ring[tx_cur].count = cpu_to_le32 (tx_threshold); 623 tx_ring[tx_cur].link = 624 cpu_to_le32 (phys_to_bus ((u32) & tx_ring[tx_next])); 625 tx_ring[tx_cur].tx_desc_addr = 626 cpu_to_le32 (phys_to_bus ((u32) & tx_ring[tx_cur].tx_buf_addr0)); 627 tx_ring[tx_cur].tx_buf_addr0 = 628 cpu_to_le32 (phys_to_bus ((u_long) packet)); 629 tx_ring[tx_cur].tx_buf_size0 = cpu_to_le32 (length); 630 631 if (!wait_for_eepro100 (dev)) { 632 printf ("%s: Tx error ethernet controller not ready.\n", 633 dev->name); 634 goto Done; 635 } 636 637 /* Send the packet. 638 */ 639 OUTL (dev, phys_to_bus ((u32) & tx_ring[tx_cur]), SCBPointer); 640 OUTW (dev, SCB_M | CU_START, SCBCmd); 641 642 for (i = 0; !(le16_to_cpu (tx_ring[tx_cur].status) & CFG_STATUS_C); 643 i++) { 644 if (i >= TOUT_LOOP) { 645 printf ("%s: Tx error buffer not ready\n", dev->name); 646 goto Done; 647 } 648 } 649 650 if (!(le16_to_cpu (tx_ring[tx_cur].status) & CFG_STATUS_OK)) { 651 printf ("TX error status = 0x%08X\n", 652 le16_to_cpu (tx_ring[tx_cur].status)); 653 goto Done; 654 } 655 656 status = length; 657 658 Done: 659 return status; 660 } 661 662 static int eepro100_recv (struct eth_device *dev) 663 { 664 u16 status, stat; 665 int rx_prev, length = 0; 666 667 stat = INW (dev, SCBStatus); 668 OUTW (dev, stat & SCB_STATUS_RNR, SCBStatus); 669 670 for (;;) { 671 status = le16_to_cpu (rx_ring[rx_next].status); 672 673 if (!(status & RFD_STATUS_C)) { 674 break; 675 } 676 677 /* Valid frame status. 678 */ 679 if ((status & RFD_STATUS_OK)) { 680 /* A valid frame received. 681 */ 682 length = le32_to_cpu (rx_ring[rx_next].count) & 0x3fff; 683 684 /* Pass the packet up to the protocol 685 * layers. 686 */ 687 NetReceive (rx_ring[rx_next].data, length); 688 } else { 689 /* There was an error. 690 */ 691 printf ("RX error status = 0x%08X\n", status); 692 } 693 694 rx_ring[rx_next].control = cpu_to_le16 (RFD_CONTROL_S); 695 rx_ring[rx_next].status = 0; 696 rx_ring[rx_next].count = cpu_to_le32 (PKTSIZE_ALIGN << 16); 697 698 rx_prev = (rx_next + NUM_RX_DESC - 1) % NUM_RX_DESC; 699 rx_ring[rx_prev].control = 0; 700 701 /* Update entry information. 702 */ 703 rx_next = (rx_next + 1) % NUM_RX_DESC; 704 } 705 706 if (stat & SCB_STATUS_RNR) { 707 708 printf ("%s: Receiver is not ready, restart it !\n", dev->name); 709 710 /* Reinitialize Rx ring. 711 */ 712 init_rx_ring (dev); 713 714 if (!wait_for_eepro100 (dev)) { 715 printf ("Error: Can not restart ethernet controller.\n"); 716 goto Done; 717 } 718 719 OUTL (dev, phys_to_bus ((u32) & rx_ring[rx_next]), SCBPointer); 720 OUTW (dev, SCB_M | RUC_START, SCBCmd); 721 } 722 723 Done: 724 return length; 725 } 726 727 static void eepro100_halt (struct eth_device *dev) 728 { 729 /* Reset the ethernet controller 730 */ 731 OUTL (dev, I82559_SELECTIVE_RESET, SCBPort); 732 udelay (20); 733 734 OUTL (dev, I82559_RESET, SCBPort); 735 udelay (20); 736 737 if (!wait_for_eepro100 (dev)) { 738 printf ("Error: Can not reset ethernet controller.\n"); 739 goto Done; 740 } 741 OUTL (dev, 0, SCBPointer); 742 OUTW (dev, SCB_M | RUC_ADDR_LOAD, SCBCmd); 743 744 if (!wait_for_eepro100 (dev)) { 745 printf ("Error: Can not reset ethernet controller.\n"); 746 goto Done; 747 } 748 OUTL (dev, 0, SCBPointer); 749 OUTW (dev, SCB_M | CU_ADDR_LOAD, SCBCmd); 750 751 Done: 752 return; 753 } 754 755 /* SROM Read. 756 */ 757 static int read_eeprom (struct eth_device *dev, int location, int addr_len) 758 { 759 unsigned short retval = 0; 760 int read_cmd = location | EE_READ_CMD; 761 int i; 762 763 OUTW (dev, EE_ENB & ~EE_CS, SCBeeprom); 764 OUTW (dev, EE_ENB, SCBeeprom); 765 766 /* Shift the read command bits out. */ 767 for (i = 12; i >= 0; i--) { 768 short dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0; 769 770 OUTW (dev, EE_ENB | dataval, SCBeeprom); 771 udelay (1); 772 OUTW (dev, EE_ENB | dataval | EE_SHIFT_CLK, SCBeeprom); 773 udelay (1); 774 } 775 OUTW (dev, EE_ENB, SCBeeprom); 776 777 for (i = 15; i >= 0; i--) { 778 OUTW (dev, EE_ENB | EE_SHIFT_CLK, SCBeeprom); 779 udelay (1); 780 retval = (retval << 1) | 781 ((INW (dev, SCBeeprom) & EE_DATA_READ) ? 1 : 0); 782 OUTW (dev, EE_ENB, SCBeeprom); 783 udelay (1); 784 } 785 786 /* Terminate the EEPROM access. */ 787 OUTW (dev, EE_ENB & ~EE_CS, SCBeeprom); 788 return retval; 789 } 790 791 #ifdef CONFIG_EEPRO100_SROM_WRITE 792 int eepro100_write_eeprom (struct eth_device* dev, int location, int addr_len, unsigned short data) 793 { 794 unsigned short dataval; 795 int enable_cmd = 0x3f | EE_EWENB_CMD; 796 int write_cmd = location | EE_WRITE_CMD; 797 int i; 798 unsigned long datalong, tmplong; 799 800 OUTW(dev, EE_ENB & ~EE_CS, SCBeeprom); 801 udelay(1); 802 OUTW(dev, EE_ENB, SCBeeprom); 803 804 /* Shift the enable command bits out. */ 805 for (i = (addr_len+EE_CMD_BITS-1); i >= 0; i--) 806 { 807 dataval = (enable_cmd & (1 << i)) ? EE_DATA_WRITE : 0; 808 OUTW(dev, EE_ENB | dataval, SCBeeprom); 809 udelay(1); 810 OUTW(dev, EE_ENB | dataval | EE_SHIFT_CLK, SCBeeprom); 811 udelay(1); 812 } 813 814 OUTW(dev, EE_ENB, SCBeeprom); 815 udelay(1); 816 OUTW(dev, EE_ENB & ~EE_CS, SCBeeprom); 817 udelay(1); 818 OUTW(dev, EE_ENB, SCBeeprom); 819 820 821 /* Shift the write command bits out. */ 822 for (i = (addr_len+EE_CMD_BITS-1); i >= 0; i--) 823 { 824 dataval = (write_cmd & (1 << i)) ? EE_DATA_WRITE : 0; 825 OUTW(dev, EE_ENB | dataval, SCBeeprom); 826 udelay(1); 827 OUTW(dev, EE_ENB | dataval | EE_SHIFT_CLK, SCBeeprom); 828 udelay(1); 829 } 830 831 /* Write the data */ 832 datalong= (unsigned long) ((((data) & 0x00ff) << 8) | ( (data) >> 8)); 833 834 for (i = 0; i< EE_DATA_BITS; i++) 835 { 836 /* Extract and move data bit to bit DI */ 837 dataval = ((datalong & 0x8000)>>13) ? EE_DATA_WRITE : 0; 838 839 OUTW(dev, EE_ENB | dataval, SCBeeprom); 840 udelay(1); 841 OUTW(dev, EE_ENB | dataval | EE_SHIFT_CLK, SCBeeprom); 842 udelay(1); 843 OUTW(dev, EE_ENB | dataval, SCBeeprom); 844 udelay(1); 845 846 datalong = datalong << 1; /* Adjust significant data bit*/ 847 } 848 849 /* Finish up command (toggle CS) */ 850 OUTW(dev, EE_ENB & ~EE_CS, SCBeeprom); 851 udelay(1); /* delay for more than 250 ns */ 852 OUTW(dev, EE_ENB, SCBeeprom); 853 854 /* Wait for programming ready (D0 = 1) */ 855 tmplong = 10; 856 do 857 { 858 dataval = INW(dev, SCBeeprom); 859 if (dataval & EE_DATA_READ) 860 break; 861 udelay(10000); 862 } 863 while (-- tmplong); 864 865 if (tmplong == 0) 866 { 867 printf ("Write i82559 eeprom timed out (100 ms waiting for data ready.\n"); 868 return -1; 869 } 870 871 /* Terminate the EEPROM access. */ 872 OUTW(dev, EE_ENB & ~EE_CS, SCBeeprom); 873 874 return 0; 875 } 876 #endif 877 878 static void init_rx_ring (struct eth_device *dev) 879 { 880 int i; 881 882 for (i = 0; i < NUM_RX_DESC; i++) { 883 rx_ring[i].status = 0; 884 rx_ring[i].control = 885 (i == NUM_RX_DESC - 1) ? cpu_to_le16 (RFD_CONTROL_S) : 0; 886 rx_ring[i].link = 887 cpu_to_le32 (phys_to_bus 888 ((u32) & rx_ring[(i + 1) % NUM_RX_DESC])); 889 rx_ring[i].rx_buf_addr = 0xffffffff; 890 rx_ring[i].count = cpu_to_le32 (PKTSIZE_ALIGN << 16); 891 } 892 893 rx_next = 0; 894 } 895 896 static void purge_tx_ring (struct eth_device *dev) 897 { 898 int i; 899 900 tx_next = 0; 901 tx_threshold = 0x01208000; 902 903 for (i = 0; i < NUM_TX_DESC; i++) { 904 tx_ring[i].status = 0; 905 tx_ring[i].command = 0; 906 tx_ring[i].link = 0; 907 tx_ring[i].tx_desc_addr = 0; 908 tx_ring[i].count = 0; 909 910 tx_ring[i].tx_buf_addr0 = 0; 911 tx_ring[i].tx_buf_size0 = 0; 912 tx_ring[i].tx_buf_addr1 = 0; 913 tx_ring[i].tx_buf_size1 = 0; 914 } 915 } 916 917 static void read_hw_addr (struct eth_device *dev, bd_t * bis) 918 { 919 u16 eeprom[0x40]; 920 u16 sum = 0; 921 int i, j; 922 int addr_len = read_eeprom (dev, 0, 6) == 0xffff ? 8 : 6; 923 924 for (j = 0, i = 0; i < 0x40; i++) { 925 u16 value = read_eeprom (dev, i, addr_len); 926 927 eeprom[i] = value; 928 sum += value; 929 if (i < 3) { 930 dev->enetaddr[j++] = value; 931 dev->enetaddr[j++] = value >> 8; 932 } 933 } 934 935 if (sum != 0xBABA) { 936 memset (dev->enetaddr, 0, ETH_ALEN); 937 #ifdef DEBUG 938 printf ("%s: Invalid EEPROM checksum %#4.4x, " 939 "check settings before activating this device!\n", 940 dev->name, sum); 941 #endif 942 } 943 } 944