1 /* 2 * (C) Copyright 2002 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <malloc.h> 10 #include <net.h> 11 #include <netdev.h> 12 #include <asm/io.h> 13 #include <pci.h> 14 #include <miiphy.h> 15 16 #undef DEBUG 17 18 /* Ethernet chip registers. 19 */ 20 #define SCBStatus 0 /* Rx/Command Unit Status *Word* */ 21 #define SCBIntAckByte 1 /* Rx/Command Unit STAT/ACK byte */ 22 #define SCBCmd 2 /* Rx/Command Unit Command *Word* */ 23 #define SCBIntrCtlByte 3 /* Rx/Command Unit Intr.Control Byte */ 24 #define SCBPointer 4 /* General purpose pointer. */ 25 #define SCBPort 8 /* Misc. commands and operands. */ 26 #define SCBflash 12 /* Flash memory control. */ 27 #define SCBeeprom 14 /* EEPROM memory control. */ 28 #define SCBCtrlMDI 16 /* MDI interface control. */ 29 #define SCBEarlyRx 20 /* Early receive byte count. */ 30 #define SCBGenControl 28 /* 82559 General Control Register */ 31 #define SCBGenStatus 29 /* 82559 General Status register */ 32 33 /* 82559 SCB status word defnitions 34 */ 35 #define SCB_STATUS_CX 0x8000 /* CU finished command (transmit) */ 36 #define SCB_STATUS_FR 0x4000 /* frame received */ 37 #define SCB_STATUS_CNA 0x2000 /* CU left active state */ 38 #define SCB_STATUS_RNR 0x1000 /* receiver left ready state */ 39 #define SCB_STATUS_MDI 0x0800 /* MDI read/write cycle done */ 40 #define SCB_STATUS_SWI 0x0400 /* software generated interrupt */ 41 #define SCB_STATUS_FCP 0x0100 /* flow control pause interrupt */ 42 43 #define SCB_INTACK_MASK 0xFD00 /* all the above */ 44 45 #define SCB_INTACK_TX (SCB_STATUS_CX | SCB_STATUS_CNA) 46 #define SCB_INTACK_RX (SCB_STATUS_FR | SCB_STATUS_RNR) 47 48 /* System control block commands 49 */ 50 /* CU Commands */ 51 #define CU_NOP 0x0000 52 #define CU_START 0x0010 53 #define CU_RESUME 0x0020 54 #define CU_STATSADDR 0x0040 /* Load Dump Statistics ctrs addr */ 55 #define CU_SHOWSTATS 0x0050 /* Dump statistics counters. */ 56 #define CU_ADDR_LOAD 0x0060 /* Base address to add to CU commands */ 57 #define CU_DUMPSTATS 0x0070 /* Dump then reset stats counters. */ 58 59 /* RUC Commands */ 60 #define RUC_NOP 0x0000 61 #define RUC_START 0x0001 62 #define RUC_RESUME 0x0002 63 #define RUC_ABORT 0x0004 64 #define RUC_ADDR_LOAD 0x0006 /* (seems not to clear on acceptance) */ 65 #define RUC_RESUMENR 0x0007 66 67 #define CU_CMD_MASK 0x00f0 68 #define RU_CMD_MASK 0x0007 69 70 #define SCB_M 0x0100 /* 0 = enable interrupt, 1 = disable */ 71 #define SCB_SWI 0x0200 /* 1 - cause device to interrupt */ 72 73 #define CU_STATUS_MASK 0x00C0 74 #define RU_STATUS_MASK 0x003C 75 76 #define RU_STATUS_IDLE (0<<2) 77 #define RU_STATUS_SUS (1<<2) 78 #define RU_STATUS_NORES (2<<2) 79 #define RU_STATUS_READY (4<<2) 80 #define RU_STATUS_NO_RBDS_SUS ((1<<2)|(8<<2)) 81 #define RU_STATUS_NO_RBDS_NORES ((2<<2)|(8<<2)) 82 #define RU_STATUS_NO_RBDS_READY ((4<<2)|(8<<2)) 83 84 /* 82559 Port interface commands. 85 */ 86 #define I82559_RESET 0x00000000 /* Software reset */ 87 #define I82559_SELFTEST 0x00000001 /* 82559 Selftest command */ 88 #define I82559_SELECTIVE_RESET 0x00000002 89 #define I82559_DUMP 0x00000003 90 #define I82559_DUMP_WAKEUP 0x00000007 91 92 /* 82559 Eeprom interface. 93 */ 94 #define EE_SHIFT_CLK 0x01 /* EEPROM shift clock. */ 95 #define EE_CS 0x02 /* EEPROM chip select. */ 96 #define EE_DATA_WRITE 0x04 /* EEPROM chip data in. */ 97 #define EE_WRITE_0 0x01 98 #define EE_WRITE_1 0x05 99 #define EE_DATA_READ 0x08 /* EEPROM chip data out. */ 100 #define EE_ENB (0x4800 | EE_CS) 101 #define EE_CMD_BITS 3 102 #define EE_DATA_BITS 16 103 104 /* The EEPROM commands include the alway-set leading bit. 105 */ 106 #define EE_EWENB_CMD (4 << addr_len) 107 #define EE_WRITE_CMD (5 << addr_len) 108 #define EE_READ_CMD (6 << addr_len) 109 #define EE_ERASE_CMD (7 << addr_len) 110 111 /* Receive frame descriptors. 112 */ 113 struct RxFD { 114 volatile u16 status; 115 volatile u16 control; 116 volatile u32 link; /* struct RxFD * */ 117 volatile u32 rx_buf_addr; /* void * */ 118 volatile u32 count; 119 120 volatile u8 data[PKTSIZE_ALIGN]; 121 }; 122 123 #define RFD_STATUS_C 0x8000 /* completion of received frame */ 124 #define RFD_STATUS_OK 0x2000 /* frame received with no errors */ 125 126 #define RFD_CONTROL_EL 0x8000 /* 1=last RFD in RFA */ 127 #define RFD_CONTROL_S 0x4000 /* 1=suspend RU after receiving frame */ 128 #define RFD_CONTROL_H 0x0010 /* 1=RFD is a header RFD */ 129 #define RFD_CONTROL_SF 0x0008 /* 0=simplified, 1=flexible mode */ 130 131 #define RFD_COUNT_MASK 0x3fff 132 #define RFD_COUNT_F 0x4000 133 #define RFD_COUNT_EOF 0x8000 134 135 #define RFD_RX_CRC 0x0800 /* crc error */ 136 #define RFD_RX_ALIGNMENT 0x0400 /* alignment error */ 137 #define RFD_RX_RESOURCE 0x0200 /* out of space, no resources */ 138 #define RFD_RX_DMA_OVER 0x0100 /* DMA overrun */ 139 #define RFD_RX_SHORT 0x0080 /* short frame error */ 140 #define RFD_RX_LENGTH 0x0020 141 #define RFD_RX_ERROR 0x0010 /* receive error */ 142 #define RFD_RX_NO_ADR_MATCH 0x0004 /* no address match */ 143 #define RFD_RX_IA_MATCH 0x0002 /* individual address does not match */ 144 #define RFD_RX_TCO 0x0001 /* TCO indication */ 145 146 /* Transmit frame descriptors 147 */ 148 struct TxFD { /* Transmit frame descriptor set. */ 149 volatile u16 status; 150 volatile u16 command; 151 volatile u32 link; /* void * */ 152 volatile u32 tx_desc_addr; /* Always points to the tx_buf_addr element. */ 153 volatile s32 count; 154 155 volatile u32 tx_buf_addr0; /* void *, frame to be transmitted. */ 156 volatile s32 tx_buf_size0; /* Length of Tx frame. */ 157 volatile u32 tx_buf_addr1; /* void *, frame to be transmitted. */ 158 volatile s32 tx_buf_size1; /* Length of Tx frame. */ 159 }; 160 161 #define TxCB_CMD_TRANSMIT 0x0004 /* transmit command */ 162 #define TxCB_CMD_SF 0x0008 /* 0=simplified, 1=flexible mode */ 163 #define TxCB_CMD_NC 0x0010 /* 0=CRC insert by controller */ 164 #define TxCB_CMD_I 0x2000 /* generate interrupt on completion */ 165 #define TxCB_CMD_S 0x4000 /* suspend on completion */ 166 #define TxCB_CMD_EL 0x8000 /* last command block in CBL */ 167 168 #define TxCB_COUNT_MASK 0x3fff 169 #define TxCB_COUNT_EOF 0x8000 170 171 /* The Speedo3 Rx and Tx frame/buffer descriptors. 172 */ 173 struct descriptor { /* A generic descriptor. */ 174 volatile u16 status; 175 volatile u16 command; 176 volatile u32 link; /* struct descriptor * */ 177 178 unsigned char params[0]; 179 }; 180 181 #define CONFIG_SYS_CMD_EL 0x8000 182 #define CONFIG_SYS_CMD_SUSPEND 0x4000 183 #define CONFIG_SYS_CMD_INT 0x2000 184 #define CONFIG_SYS_CMD_IAS 0x0001 /* individual address setup */ 185 #define CONFIG_SYS_CMD_CONFIGURE 0x0002 /* configure */ 186 187 #define CONFIG_SYS_STATUS_C 0x8000 188 #define CONFIG_SYS_STATUS_OK 0x2000 189 190 /* Misc. 191 */ 192 #define NUM_RX_DESC PKTBUFSRX 193 #define NUM_TX_DESC 1 /* Number of TX descriptors */ 194 195 #define TOUT_LOOP 1000000 196 197 #define ETH_ALEN 6 198 199 static struct RxFD rx_ring[NUM_RX_DESC]; /* RX descriptor ring */ 200 static struct TxFD tx_ring[NUM_TX_DESC]; /* TX descriptor ring */ 201 static int rx_next; /* RX descriptor ring pointer */ 202 static int tx_next; /* TX descriptor ring pointer */ 203 static int tx_threshold; 204 205 /* 206 * The parameters for a CmdConfigure operation. 207 * There are so many options that it would be difficult to document 208 * each bit. We mostly use the default or recommended settings. 209 */ 210 static const char i82557_config_cmd[] = { 211 22, 0x08, 0, 0, 0, 0, 0x32, 0x03, 1, /* 1=Use MII 0=Use AUI */ 212 0, 0x2E, 0, 0x60, 0, 213 0xf2, 0x48, 0, 0x40, 0xf2, 0x80, /* 0x40=Force full-duplex */ 214 0x3f, 0x05, 215 }; 216 static const char i82558_config_cmd[] = { 217 22, 0x08, 0, 1, 0, 0, 0x22, 0x03, 1, /* 1=Use MII 0=Use AUI */ 218 0, 0x2E, 0, 0x60, 0x08, 0x88, 219 0x68, 0, 0x40, 0xf2, 0x84, /* Disable FC */ 220 0x31, 0x05, 221 }; 222 223 static void init_rx_ring (struct eth_device *dev); 224 static void purge_tx_ring (struct eth_device *dev); 225 226 static void read_hw_addr (struct eth_device *dev, bd_t * bis); 227 228 static int eepro100_init (struct eth_device *dev, bd_t * bis); 229 static int eepro100_send(struct eth_device *dev, void *packet, int length); 230 static int eepro100_recv (struct eth_device *dev); 231 static void eepro100_halt (struct eth_device *dev); 232 233 #if defined(CONFIG_E500) 234 #define bus_to_phys(a) (a) 235 #define phys_to_bus(a) (a) 236 #else 237 #define bus_to_phys(a) pci_mem_to_phys((pci_dev_t)dev->priv, a) 238 #define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)dev->priv, a) 239 #endif 240 241 static inline int INW (struct eth_device *dev, u_long addr) 242 { 243 return le16_to_cpu(*(volatile u16 *)(addr + (u_long)dev->iobase)); 244 } 245 246 static inline void OUTW (struct eth_device *dev, int command, u_long addr) 247 { 248 *(volatile u16 *)((addr + (u_long)dev->iobase)) = cpu_to_le16(command); 249 } 250 251 static inline void OUTL (struct eth_device *dev, int command, u_long addr) 252 { 253 *(volatile u32 *)((addr + (u_long)dev->iobase)) = cpu_to_le32(command); 254 } 255 256 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) 257 static inline int INL (struct eth_device *dev, u_long addr) 258 { 259 return le32_to_cpu(*(volatile u32 *)(addr + (u_long)dev->iobase)); 260 } 261 262 static int get_phyreg (struct eth_device *dev, unsigned char addr, 263 unsigned char reg, unsigned short *value) 264 { 265 int cmd; 266 int timeout = 50; 267 268 /* read requested data */ 269 cmd = (2 << 26) | ((addr & 0x1f) << 21) | ((reg & 0x1f) << 16); 270 OUTL (dev, cmd, SCBCtrlMDI); 271 272 do { 273 udelay(1000); 274 cmd = INL (dev, SCBCtrlMDI); 275 } while (!(cmd & (1 << 28)) && (--timeout)); 276 277 if (timeout == 0) 278 return -1; 279 280 *value = (unsigned short) (cmd & 0xffff); 281 282 return 0; 283 } 284 285 static int set_phyreg (struct eth_device *dev, unsigned char addr, 286 unsigned char reg, unsigned short value) 287 { 288 int cmd; 289 int timeout = 50; 290 291 /* write requested data */ 292 cmd = (1 << 26) | ((addr & 0x1f) << 21) | ((reg & 0x1f) << 16); 293 OUTL (dev, cmd | value, SCBCtrlMDI); 294 295 while (!(INL (dev, SCBCtrlMDI) & (1 << 28)) && (--timeout)) 296 udelay(1000); 297 298 if (timeout == 0) 299 return -1; 300 301 return 0; 302 } 303 304 /* Check if given phyaddr is valid, i.e. there is a PHY connected. 305 * Do this by checking model value field from ID2 register. 306 */ 307 static struct eth_device* verify_phyaddr (const char *devname, 308 unsigned char addr) 309 { 310 struct eth_device *dev; 311 unsigned short value; 312 unsigned char model; 313 314 dev = eth_get_dev_by_name(devname); 315 if (dev == NULL) { 316 printf("%s: no such device\n", devname); 317 return NULL; 318 } 319 320 /* read id2 register */ 321 if (get_phyreg(dev, addr, MII_PHYSID2, &value) != 0) { 322 printf("%s: mii read timeout!\n", devname); 323 return NULL; 324 } 325 326 /* get model */ 327 model = (unsigned char)((value >> 4) & 0x003f); 328 329 if (model == 0) { 330 printf("%s: no PHY at address %d\n", devname, addr); 331 return NULL; 332 } 333 334 return dev; 335 } 336 337 static int eepro100_miiphy_read(struct mii_dev *bus, int addr, int devad, 338 int reg) 339 { 340 unsigned short value = 0; 341 struct eth_device *dev; 342 343 dev = verify_phyaddr(bus->name, addr); 344 if (dev == NULL) 345 return -1; 346 347 if (get_phyreg(dev, addr, reg, &value) != 0) { 348 printf("%s: mii read timeout!\n", bus->name); 349 return -1; 350 } 351 352 return value; 353 } 354 355 static int eepro100_miiphy_write(struct mii_dev *bus, int addr, int devad, 356 int reg, u16 value) 357 { 358 struct eth_device *dev; 359 360 dev = verify_phyaddr(bus->name, addr); 361 if (dev == NULL) 362 return -1; 363 364 if (set_phyreg(dev, addr, reg, value) != 0) { 365 printf("%s: mii write timeout!\n", bus->name); 366 return -1; 367 } 368 369 return 0; 370 } 371 372 #endif 373 374 /* Wait for the chip get the command. 375 */ 376 static int wait_for_eepro100 (struct eth_device *dev) 377 { 378 int i; 379 380 for (i = 0; INW (dev, SCBCmd) & (CU_CMD_MASK | RU_CMD_MASK); i++) { 381 if (i >= TOUT_LOOP) { 382 return 0; 383 } 384 } 385 386 return 1; 387 } 388 389 static struct pci_device_id supported[] = { 390 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82557}, 391 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82559}, 392 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82559ER}, 393 {} 394 }; 395 396 int eepro100_initialize (bd_t * bis) 397 { 398 pci_dev_t devno; 399 int card_number = 0; 400 struct eth_device *dev; 401 u32 iobase, status; 402 int idx = 0; 403 404 while (1) { 405 /* Find PCI device 406 */ 407 if ((devno = pci_find_devices (supported, idx++)) < 0) { 408 break; 409 } 410 411 pci_read_config_dword (devno, PCI_BASE_ADDRESS_0, &iobase); 412 iobase &= ~0xf; 413 414 #ifdef DEBUG 415 printf ("eepro100: Intel i82559 PCI EtherExpressPro @0x%x\n", 416 iobase); 417 #endif 418 419 pci_write_config_dword (devno, 420 PCI_COMMAND, 421 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); 422 423 /* Check if I/O accesses and Bus Mastering are enabled. 424 */ 425 pci_read_config_dword (devno, PCI_COMMAND, &status); 426 if (!(status & PCI_COMMAND_MEMORY)) { 427 printf ("Error: Can not enable MEM access.\n"); 428 continue; 429 } 430 431 if (!(status & PCI_COMMAND_MASTER)) { 432 printf ("Error: Can not enable Bus Mastering.\n"); 433 continue; 434 } 435 436 dev = (struct eth_device *) malloc (sizeof *dev); 437 if (!dev) { 438 printf("eepro100: Can not allocate memory\n"); 439 break; 440 } 441 memset(dev, 0, sizeof(*dev)); 442 443 sprintf (dev->name, "i82559#%d", card_number); 444 dev->priv = (void *) devno; /* this have to come before bus_to_phys() */ 445 dev->iobase = bus_to_phys (iobase); 446 dev->init = eepro100_init; 447 dev->halt = eepro100_halt; 448 dev->send = eepro100_send; 449 dev->recv = eepro100_recv; 450 451 eth_register (dev); 452 453 #if defined (CONFIG_MII) || defined(CONFIG_CMD_MII) 454 /* register mii command access routines */ 455 int retval; 456 struct mii_dev *mdiodev = mdio_alloc(); 457 if (!mdiodev) 458 return -ENOMEM; 459 strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN); 460 mdiodev->read = eepro100_miiphy_read; 461 mdiodev->write = eepro100_miiphy_write; 462 463 retval = mdio_register(mdiodev); 464 if (retval < 0) 465 return retval; 466 #endif 467 468 card_number++; 469 470 /* Set the latency timer for value. 471 */ 472 pci_write_config_byte (devno, PCI_LATENCY_TIMER, 0x20); 473 474 udelay (10 * 1000); 475 476 read_hw_addr (dev, bis); 477 } 478 479 return card_number; 480 } 481 482 483 static int eepro100_init (struct eth_device *dev, bd_t * bis) 484 { 485 int i, status = -1; 486 int tx_cur; 487 struct descriptor *ias_cmd, *cfg_cmd; 488 489 /* Reset the ethernet controller 490 */ 491 OUTL (dev, I82559_SELECTIVE_RESET, SCBPort); 492 udelay (20); 493 494 OUTL (dev, I82559_RESET, SCBPort); 495 udelay (20); 496 497 if (!wait_for_eepro100 (dev)) { 498 printf ("Error: Can not reset ethernet controller.\n"); 499 goto Done; 500 } 501 OUTL (dev, 0, SCBPointer); 502 OUTW (dev, SCB_M | RUC_ADDR_LOAD, SCBCmd); 503 504 if (!wait_for_eepro100 (dev)) { 505 printf ("Error: Can not reset ethernet controller.\n"); 506 goto Done; 507 } 508 OUTL (dev, 0, SCBPointer); 509 OUTW (dev, SCB_M | CU_ADDR_LOAD, SCBCmd); 510 511 /* Initialize Rx and Tx rings. 512 */ 513 init_rx_ring (dev); 514 purge_tx_ring (dev); 515 516 /* Tell the adapter where the RX ring is located. 517 */ 518 if (!wait_for_eepro100 (dev)) { 519 printf ("Error: Can not reset ethernet controller.\n"); 520 goto Done; 521 } 522 523 OUTL (dev, phys_to_bus ((u32) & rx_ring[rx_next]), SCBPointer); 524 OUTW (dev, SCB_M | RUC_START, SCBCmd); 525 526 /* Send the Configure frame */ 527 tx_cur = tx_next; 528 tx_next = ((tx_next + 1) % NUM_TX_DESC); 529 530 cfg_cmd = (struct descriptor *) &tx_ring[tx_cur]; 531 cfg_cmd->command = cpu_to_le16 ((CONFIG_SYS_CMD_SUSPEND | CONFIG_SYS_CMD_CONFIGURE)); 532 cfg_cmd->status = 0; 533 cfg_cmd->link = cpu_to_le32 (phys_to_bus ((u32) & tx_ring[tx_next])); 534 535 memcpy (cfg_cmd->params, i82558_config_cmd, 536 sizeof (i82558_config_cmd)); 537 538 if (!wait_for_eepro100 (dev)) { 539 printf ("Error---CONFIG_SYS_CMD_CONFIGURE: Can not reset ethernet controller.\n"); 540 goto Done; 541 } 542 543 OUTL (dev, phys_to_bus ((u32) & tx_ring[tx_cur]), SCBPointer); 544 OUTW (dev, SCB_M | CU_START, SCBCmd); 545 546 for (i = 0; 547 !(le16_to_cpu (tx_ring[tx_cur].status) & CONFIG_SYS_STATUS_C); 548 i++) { 549 if (i >= TOUT_LOOP) { 550 printf ("%s: Tx error buffer not ready\n", dev->name); 551 goto Done; 552 } 553 } 554 555 if (!(le16_to_cpu (tx_ring[tx_cur].status) & CONFIG_SYS_STATUS_OK)) { 556 printf ("TX error status = 0x%08X\n", 557 le16_to_cpu (tx_ring[tx_cur].status)); 558 goto Done; 559 } 560 561 /* Send the Individual Address Setup frame 562 */ 563 tx_cur = tx_next; 564 tx_next = ((tx_next + 1) % NUM_TX_DESC); 565 566 ias_cmd = (struct descriptor *) &tx_ring[tx_cur]; 567 ias_cmd->command = cpu_to_le16 ((CONFIG_SYS_CMD_SUSPEND | CONFIG_SYS_CMD_IAS)); 568 ias_cmd->status = 0; 569 ias_cmd->link = cpu_to_le32 (phys_to_bus ((u32) & tx_ring[tx_next])); 570 571 memcpy (ias_cmd->params, dev->enetaddr, 6); 572 573 /* Tell the adapter where the TX ring is located. 574 */ 575 if (!wait_for_eepro100 (dev)) { 576 printf ("Error: Can not reset ethernet controller.\n"); 577 goto Done; 578 } 579 580 OUTL (dev, phys_to_bus ((u32) & tx_ring[tx_cur]), SCBPointer); 581 OUTW (dev, SCB_M | CU_START, SCBCmd); 582 583 for (i = 0; !(le16_to_cpu (tx_ring[tx_cur].status) & CONFIG_SYS_STATUS_C); 584 i++) { 585 if (i >= TOUT_LOOP) { 586 printf ("%s: Tx error buffer not ready\n", 587 dev->name); 588 goto Done; 589 } 590 } 591 592 if (!(le16_to_cpu (tx_ring[tx_cur].status) & CONFIG_SYS_STATUS_OK)) { 593 printf ("TX error status = 0x%08X\n", 594 le16_to_cpu (tx_ring[tx_cur].status)); 595 goto Done; 596 } 597 598 status = 0; 599 600 Done: 601 return status; 602 } 603 604 static int eepro100_send(struct eth_device *dev, void *packet, int length) 605 { 606 int i, status = -1; 607 int tx_cur; 608 609 if (length <= 0) { 610 printf ("%s: bad packet size: %d\n", dev->name, length); 611 goto Done; 612 } 613 614 tx_cur = tx_next; 615 tx_next = (tx_next + 1) % NUM_TX_DESC; 616 617 tx_ring[tx_cur].command = cpu_to_le16 ( TxCB_CMD_TRANSMIT | 618 TxCB_CMD_SF | 619 TxCB_CMD_S | 620 TxCB_CMD_EL ); 621 tx_ring[tx_cur].status = 0; 622 tx_ring[tx_cur].count = cpu_to_le32 (tx_threshold); 623 tx_ring[tx_cur].link = 624 cpu_to_le32 (phys_to_bus ((u32) & tx_ring[tx_next])); 625 tx_ring[tx_cur].tx_desc_addr = 626 cpu_to_le32 (phys_to_bus ((u32) & tx_ring[tx_cur].tx_buf_addr0)); 627 tx_ring[tx_cur].tx_buf_addr0 = 628 cpu_to_le32 (phys_to_bus ((u_long) packet)); 629 tx_ring[tx_cur].tx_buf_size0 = cpu_to_le32 (length); 630 631 if (!wait_for_eepro100 (dev)) { 632 printf ("%s: Tx error ethernet controller not ready.\n", 633 dev->name); 634 goto Done; 635 } 636 637 /* Send the packet. 638 */ 639 OUTL (dev, phys_to_bus ((u32) & tx_ring[tx_cur]), SCBPointer); 640 OUTW (dev, SCB_M | CU_START, SCBCmd); 641 642 for (i = 0; !(le16_to_cpu (tx_ring[tx_cur].status) & CONFIG_SYS_STATUS_C); 643 i++) { 644 if (i >= TOUT_LOOP) { 645 printf ("%s: Tx error buffer not ready\n", dev->name); 646 goto Done; 647 } 648 } 649 650 if (!(le16_to_cpu (tx_ring[tx_cur].status) & CONFIG_SYS_STATUS_OK)) { 651 printf ("TX error status = 0x%08X\n", 652 le16_to_cpu (tx_ring[tx_cur].status)); 653 goto Done; 654 } 655 656 status = length; 657 658 Done: 659 return status; 660 } 661 662 static int eepro100_recv (struct eth_device *dev) 663 { 664 u16 status, stat; 665 int rx_prev, length = 0; 666 667 stat = INW (dev, SCBStatus); 668 OUTW (dev, stat & SCB_STATUS_RNR, SCBStatus); 669 670 for (;;) { 671 status = le16_to_cpu (rx_ring[rx_next].status); 672 673 if (!(status & RFD_STATUS_C)) { 674 break; 675 } 676 677 /* Valid frame status. 678 */ 679 if ((status & RFD_STATUS_OK)) { 680 /* A valid frame received. 681 */ 682 length = le32_to_cpu (rx_ring[rx_next].count) & 0x3fff; 683 684 /* Pass the packet up to the protocol 685 * layers. 686 */ 687 net_process_received_packet((u8 *)rx_ring[rx_next].data, 688 length); 689 } else { 690 /* There was an error. 691 */ 692 printf ("RX error status = 0x%08X\n", status); 693 } 694 695 rx_ring[rx_next].control = cpu_to_le16 (RFD_CONTROL_S); 696 rx_ring[rx_next].status = 0; 697 rx_ring[rx_next].count = cpu_to_le32 (PKTSIZE_ALIGN << 16); 698 699 rx_prev = (rx_next + NUM_RX_DESC - 1) % NUM_RX_DESC; 700 rx_ring[rx_prev].control = 0; 701 702 /* Update entry information. 703 */ 704 rx_next = (rx_next + 1) % NUM_RX_DESC; 705 } 706 707 if (stat & SCB_STATUS_RNR) { 708 709 printf ("%s: Receiver is not ready, restart it !\n", dev->name); 710 711 /* Reinitialize Rx ring. 712 */ 713 init_rx_ring (dev); 714 715 if (!wait_for_eepro100 (dev)) { 716 printf ("Error: Can not restart ethernet controller.\n"); 717 goto Done; 718 } 719 720 OUTL (dev, phys_to_bus ((u32) & rx_ring[rx_next]), SCBPointer); 721 OUTW (dev, SCB_M | RUC_START, SCBCmd); 722 } 723 724 Done: 725 return length; 726 } 727 728 static void eepro100_halt (struct eth_device *dev) 729 { 730 /* Reset the ethernet controller 731 */ 732 OUTL (dev, I82559_SELECTIVE_RESET, SCBPort); 733 udelay (20); 734 735 OUTL (dev, I82559_RESET, SCBPort); 736 udelay (20); 737 738 if (!wait_for_eepro100 (dev)) { 739 printf ("Error: Can not reset ethernet controller.\n"); 740 goto Done; 741 } 742 OUTL (dev, 0, SCBPointer); 743 OUTW (dev, SCB_M | RUC_ADDR_LOAD, SCBCmd); 744 745 if (!wait_for_eepro100 (dev)) { 746 printf ("Error: Can not reset ethernet controller.\n"); 747 goto Done; 748 } 749 OUTL (dev, 0, SCBPointer); 750 OUTW (dev, SCB_M | CU_ADDR_LOAD, SCBCmd); 751 752 Done: 753 return; 754 } 755 756 /* SROM Read. 757 */ 758 static int read_eeprom (struct eth_device *dev, int location, int addr_len) 759 { 760 unsigned short retval = 0; 761 int read_cmd = location | EE_READ_CMD; 762 int i; 763 764 OUTW (dev, EE_ENB & ~EE_CS, SCBeeprom); 765 OUTW (dev, EE_ENB, SCBeeprom); 766 767 /* Shift the read command bits out. */ 768 for (i = 12; i >= 0; i--) { 769 short dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0; 770 771 OUTW (dev, EE_ENB | dataval, SCBeeprom); 772 udelay (1); 773 OUTW (dev, EE_ENB | dataval | EE_SHIFT_CLK, SCBeeprom); 774 udelay (1); 775 } 776 OUTW (dev, EE_ENB, SCBeeprom); 777 778 for (i = 15; i >= 0; i--) { 779 OUTW (dev, EE_ENB | EE_SHIFT_CLK, SCBeeprom); 780 udelay (1); 781 retval = (retval << 1) | 782 ((INW (dev, SCBeeprom) & EE_DATA_READ) ? 1 : 0); 783 OUTW (dev, EE_ENB, SCBeeprom); 784 udelay (1); 785 } 786 787 /* Terminate the EEPROM access. */ 788 OUTW (dev, EE_ENB & ~EE_CS, SCBeeprom); 789 return retval; 790 } 791 792 #ifdef CONFIG_EEPRO100_SROM_WRITE 793 int eepro100_write_eeprom (struct eth_device* dev, int location, int addr_len, unsigned short data) 794 { 795 unsigned short dataval; 796 int enable_cmd = 0x3f | EE_EWENB_CMD; 797 int write_cmd = location | EE_WRITE_CMD; 798 int i; 799 unsigned long datalong, tmplong; 800 801 OUTW(dev, EE_ENB & ~EE_CS, SCBeeprom); 802 udelay(1); 803 OUTW(dev, EE_ENB, SCBeeprom); 804 805 /* Shift the enable command bits out. */ 806 for (i = (addr_len+EE_CMD_BITS-1); i >= 0; i--) 807 { 808 dataval = (enable_cmd & (1 << i)) ? EE_DATA_WRITE : 0; 809 OUTW(dev, EE_ENB | dataval, SCBeeprom); 810 udelay(1); 811 OUTW(dev, EE_ENB | dataval | EE_SHIFT_CLK, SCBeeprom); 812 udelay(1); 813 } 814 815 OUTW(dev, EE_ENB, SCBeeprom); 816 udelay(1); 817 OUTW(dev, EE_ENB & ~EE_CS, SCBeeprom); 818 udelay(1); 819 OUTW(dev, EE_ENB, SCBeeprom); 820 821 822 /* Shift the write command bits out. */ 823 for (i = (addr_len+EE_CMD_BITS-1); i >= 0; i--) 824 { 825 dataval = (write_cmd & (1 << i)) ? EE_DATA_WRITE : 0; 826 OUTW(dev, EE_ENB | dataval, SCBeeprom); 827 udelay(1); 828 OUTW(dev, EE_ENB | dataval | EE_SHIFT_CLK, SCBeeprom); 829 udelay(1); 830 } 831 832 /* Write the data */ 833 datalong= (unsigned long) ((((data) & 0x00ff) << 8) | ( (data) >> 8)); 834 835 for (i = 0; i< EE_DATA_BITS; i++) 836 { 837 /* Extract and move data bit to bit DI */ 838 dataval = ((datalong & 0x8000)>>13) ? EE_DATA_WRITE : 0; 839 840 OUTW(dev, EE_ENB | dataval, SCBeeprom); 841 udelay(1); 842 OUTW(dev, EE_ENB | dataval | EE_SHIFT_CLK, SCBeeprom); 843 udelay(1); 844 OUTW(dev, EE_ENB | dataval, SCBeeprom); 845 udelay(1); 846 847 datalong = datalong << 1; /* Adjust significant data bit*/ 848 } 849 850 /* Finish up command (toggle CS) */ 851 OUTW(dev, EE_ENB & ~EE_CS, SCBeeprom); 852 udelay(1); /* delay for more than 250 ns */ 853 OUTW(dev, EE_ENB, SCBeeprom); 854 855 /* Wait for programming ready (D0 = 1) */ 856 tmplong = 10; 857 do 858 { 859 dataval = INW(dev, SCBeeprom); 860 if (dataval & EE_DATA_READ) 861 break; 862 udelay(10000); 863 } 864 while (-- tmplong); 865 866 if (tmplong == 0) 867 { 868 printf ("Write i82559 eeprom timed out (100 ms waiting for data ready.\n"); 869 return -1; 870 } 871 872 /* Terminate the EEPROM access. */ 873 OUTW(dev, EE_ENB & ~EE_CS, SCBeeprom); 874 875 return 0; 876 } 877 #endif 878 879 static void init_rx_ring (struct eth_device *dev) 880 { 881 int i; 882 883 for (i = 0; i < NUM_RX_DESC; i++) { 884 rx_ring[i].status = 0; 885 rx_ring[i].control = 886 (i == NUM_RX_DESC - 1) ? cpu_to_le16 (RFD_CONTROL_S) : 0; 887 rx_ring[i].link = 888 cpu_to_le32 (phys_to_bus 889 ((u32) & rx_ring[(i + 1) % NUM_RX_DESC])); 890 rx_ring[i].rx_buf_addr = 0xffffffff; 891 rx_ring[i].count = cpu_to_le32 (PKTSIZE_ALIGN << 16); 892 } 893 894 rx_next = 0; 895 } 896 897 static void purge_tx_ring (struct eth_device *dev) 898 { 899 int i; 900 901 tx_next = 0; 902 tx_threshold = 0x01208000; 903 904 for (i = 0; i < NUM_TX_DESC; i++) { 905 tx_ring[i].status = 0; 906 tx_ring[i].command = 0; 907 tx_ring[i].link = 0; 908 tx_ring[i].tx_desc_addr = 0; 909 tx_ring[i].count = 0; 910 911 tx_ring[i].tx_buf_addr0 = 0; 912 tx_ring[i].tx_buf_size0 = 0; 913 tx_ring[i].tx_buf_addr1 = 0; 914 tx_ring[i].tx_buf_size1 = 0; 915 } 916 } 917 918 static void read_hw_addr (struct eth_device *dev, bd_t * bis) 919 { 920 u16 sum = 0; 921 int i, j; 922 int addr_len = read_eeprom (dev, 0, 6) == 0xffff ? 8 : 6; 923 924 for (j = 0, i = 0; i < 0x40; i++) { 925 u16 value = read_eeprom (dev, i, addr_len); 926 927 sum += value; 928 if (i < 3) { 929 dev->enetaddr[j++] = value; 930 dev->enetaddr[j++] = value >> 8; 931 } 932 } 933 934 if (sum != 0xBABA) { 935 memset (dev->enetaddr, 0, ETH_ALEN); 936 #ifdef DEBUG 937 printf ("%s: Invalid EEPROM checksum %#4.4x, " 938 "check settings before activating this device!\n", 939 dev->name, sum); 940 #endif 941 } 942 } 943