1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+
22439e4bfSJean-Christophe PLAGNIOL-VILLARD /*
32439e4bfSJean-Christophe PLAGNIOL-VILLARD * (C) Copyright 2002
42439e4bfSJean-Christophe PLAGNIOL-VILLARD * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
52439e4bfSJean-Christophe PLAGNIOL-VILLARD */
62439e4bfSJean-Christophe PLAGNIOL-VILLARD
72439e4bfSJean-Christophe PLAGNIOL-VILLARD #include <common.h>
82439e4bfSJean-Christophe PLAGNIOL-VILLARD #include <malloc.h>
92439e4bfSJean-Christophe PLAGNIOL-VILLARD #include <net.h>
1010efa024SBen Warren #include <netdev.h>
112439e4bfSJean-Christophe PLAGNIOL-VILLARD #include <asm/io.h>
122439e4bfSJean-Christophe PLAGNIOL-VILLARD #include <pci.h>
132439e4bfSJean-Christophe PLAGNIOL-VILLARD #include <miiphy.h>
142439e4bfSJean-Christophe PLAGNIOL-VILLARD
152439e4bfSJean-Christophe PLAGNIOL-VILLARD #undef DEBUG
162439e4bfSJean-Christophe PLAGNIOL-VILLARD
172439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Ethernet chip registers.
182439e4bfSJean-Christophe PLAGNIOL-VILLARD */
192439e4bfSJean-Christophe PLAGNIOL-VILLARD #define SCBStatus 0 /* Rx/Command Unit Status *Word* */
202439e4bfSJean-Christophe PLAGNIOL-VILLARD #define SCBIntAckByte 1 /* Rx/Command Unit STAT/ACK byte */
212439e4bfSJean-Christophe PLAGNIOL-VILLARD #define SCBCmd 2 /* Rx/Command Unit Command *Word* */
222439e4bfSJean-Christophe PLAGNIOL-VILLARD #define SCBIntrCtlByte 3 /* Rx/Command Unit Intr.Control Byte */
232439e4bfSJean-Christophe PLAGNIOL-VILLARD #define SCBPointer 4 /* General purpose pointer. */
242439e4bfSJean-Christophe PLAGNIOL-VILLARD #define SCBPort 8 /* Misc. commands and operands. */
252439e4bfSJean-Christophe PLAGNIOL-VILLARD #define SCBflash 12 /* Flash memory control. */
262439e4bfSJean-Christophe PLAGNIOL-VILLARD #define SCBeeprom 14 /* EEPROM memory control. */
272439e4bfSJean-Christophe PLAGNIOL-VILLARD #define SCBCtrlMDI 16 /* MDI interface control. */
282439e4bfSJean-Christophe PLAGNIOL-VILLARD #define SCBEarlyRx 20 /* Early receive byte count. */
292439e4bfSJean-Christophe PLAGNIOL-VILLARD #define SCBGenControl 28 /* 82559 General Control Register */
302439e4bfSJean-Christophe PLAGNIOL-VILLARD #define SCBGenStatus 29 /* 82559 General Status register */
312439e4bfSJean-Christophe PLAGNIOL-VILLARD
322439e4bfSJean-Christophe PLAGNIOL-VILLARD /* 82559 SCB status word defnitions
332439e4bfSJean-Christophe PLAGNIOL-VILLARD */
342439e4bfSJean-Christophe PLAGNIOL-VILLARD #define SCB_STATUS_CX 0x8000 /* CU finished command (transmit) */
352439e4bfSJean-Christophe PLAGNIOL-VILLARD #define SCB_STATUS_FR 0x4000 /* frame received */
362439e4bfSJean-Christophe PLAGNIOL-VILLARD #define SCB_STATUS_CNA 0x2000 /* CU left active state */
372439e4bfSJean-Christophe PLAGNIOL-VILLARD #define SCB_STATUS_RNR 0x1000 /* receiver left ready state */
382439e4bfSJean-Christophe PLAGNIOL-VILLARD #define SCB_STATUS_MDI 0x0800 /* MDI read/write cycle done */
392439e4bfSJean-Christophe PLAGNIOL-VILLARD #define SCB_STATUS_SWI 0x0400 /* software generated interrupt */
402439e4bfSJean-Christophe PLAGNIOL-VILLARD #define SCB_STATUS_FCP 0x0100 /* flow control pause interrupt */
412439e4bfSJean-Christophe PLAGNIOL-VILLARD
422439e4bfSJean-Christophe PLAGNIOL-VILLARD #define SCB_INTACK_MASK 0xFD00 /* all the above */
432439e4bfSJean-Christophe PLAGNIOL-VILLARD
442439e4bfSJean-Christophe PLAGNIOL-VILLARD #define SCB_INTACK_TX (SCB_STATUS_CX | SCB_STATUS_CNA)
452439e4bfSJean-Christophe PLAGNIOL-VILLARD #define SCB_INTACK_RX (SCB_STATUS_FR | SCB_STATUS_RNR)
462439e4bfSJean-Christophe PLAGNIOL-VILLARD
472439e4bfSJean-Christophe PLAGNIOL-VILLARD /* System control block commands
482439e4bfSJean-Christophe PLAGNIOL-VILLARD */
492439e4bfSJean-Christophe PLAGNIOL-VILLARD /* CU Commands */
502439e4bfSJean-Christophe PLAGNIOL-VILLARD #define CU_NOP 0x0000
512439e4bfSJean-Christophe PLAGNIOL-VILLARD #define CU_START 0x0010
522439e4bfSJean-Christophe PLAGNIOL-VILLARD #define CU_RESUME 0x0020
532439e4bfSJean-Christophe PLAGNIOL-VILLARD #define CU_STATSADDR 0x0040 /* Load Dump Statistics ctrs addr */
542439e4bfSJean-Christophe PLAGNIOL-VILLARD #define CU_SHOWSTATS 0x0050 /* Dump statistics counters. */
552439e4bfSJean-Christophe PLAGNIOL-VILLARD #define CU_ADDR_LOAD 0x0060 /* Base address to add to CU commands */
562439e4bfSJean-Christophe PLAGNIOL-VILLARD #define CU_DUMPSTATS 0x0070 /* Dump then reset stats counters. */
572439e4bfSJean-Christophe PLAGNIOL-VILLARD
582439e4bfSJean-Christophe PLAGNIOL-VILLARD /* RUC Commands */
592439e4bfSJean-Christophe PLAGNIOL-VILLARD #define RUC_NOP 0x0000
602439e4bfSJean-Christophe PLAGNIOL-VILLARD #define RUC_START 0x0001
612439e4bfSJean-Christophe PLAGNIOL-VILLARD #define RUC_RESUME 0x0002
622439e4bfSJean-Christophe PLAGNIOL-VILLARD #define RUC_ABORT 0x0004
632439e4bfSJean-Christophe PLAGNIOL-VILLARD #define RUC_ADDR_LOAD 0x0006 /* (seems not to clear on acceptance) */
642439e4bfSJean-Christophe PLAGNIOL-VILLARD #define RUC_RESUMENR 0x0007
652439e4bfSJean-Christophe PLAGNIOL-VILLARD
662439e4bfSJean-Christophe PLAGNIOL-VILLARD #define CU_CMD_MASK 0x00f0
672439e4bfSJean-Christophe PLAGNIOL-VILLARD #define RU_CMD_MASK 0x0007
682439e4bfSJean-Christophe PLAGNIOL-VILLARD
692439e4bfSJean-Christophe PLAGNIOL-VILLARD #define SCB_M 0x0100 /* 0 = enable interrupt, 1 = disable */
702439e4bfSJean-Christophe PLAGNIOL-VILLARD #define SCB_SWI 0x0200 /* 1 - cause device to interrupt */
712439e4bfSJean-Christophe PLAGNIOL-VILLARD
722439e4bfSJean-Christophe PLAGNIOL-VILLARD #define CU_STATUS_MASK 0x00C0
732439e4bfSJean-Christophe PLAGNIOL-VILLARD #define RU_STATUS_MASK 0x003C
742439e4bfSJean-Christophe PLAGNIOL-VILLARD
752439e4bfSJean-Christophe PLAGNIOL-VILLARD #define RU_STATUS_IDLE (0<<2)
762439e4bfSJean-Christophe PLAGNIOL-VILLARD #define RU_STATUS_SUS (1<<2)
772439e4bfSJean-Christophe PLAGNIOL-VILLARD #define RU_STATUS_NORES (2<<2)
782439e4bfSJean-Christophe PLAGNIOL-VILLARD #define RU_STATUS_READY (4<<2)
792439e4bfSJean-Christophe PLAGNIOL-VILLARD #define RU_STATUS_NO_RBDS_SUS ((1<<2)|(8<<2))
802439e4bfSJean-Christophe PLAGNIOL-VILLARD #define RU_STATUS_NO_RBDS_NORES ((2<<2)|(8<<2))
812439e4bfSJean-Christophe PLAGNIOL-VILLARD #define RU_STATUS_NO_RBDS_READY ((4<<2)|(8<<2))
822439e4bfSJean-Christophe PLAGNIOL-VILLARD
832439e4bfSJean-Christophe PLAGNIOL-VILLARD /* 82559 Port interface commands.
842439e4bfSJean-Christophe PLAGNIOL-VILLARD */
852439e4bfSJean-Christophe PLAGNIOL-VILLARD #define I82559_RESET 0x00000000 /* Software reset */
862439e4bfSJean-Christophe PLAGNIOL-VILLARD #define I82559_SELFTEST 0x00000001 /* 82559 Selftest command */
872439e4bfSJean-Christophe PLAGNIOL-VILLARD #define I82559_SELECTIVE_RESET 0x00000002
882439e4bfSJean-Christophe PLAGNIOL-VILLARD #define I82559_DUMP 0x00000003
892439e4bfSJean-Christophe PLAGNIOL-VILLARD #define I82559_DUMP_WAKEUP 0x00000007
902439e4bfSJean-Christophe PLAGNIOL-VILLARD
912439e4bfSJean-Christophe PLAGNIOL-VILLARD /* 82559 Eeprom interface.
922439e4bfSJean-Christophe PLAGNIOL-VILLARD */
932439e4bfSJean-Christophe PLAGNIOL-VILLARD #define EE_SHIFT_CLK 0x01 /* EEPROM shift clock. */
942439e4bfSJean-Christophe PLAGNIOL-VILLARD #define EE_CS 0x02 /* EEPROM chip select. */
952439e4bfSJean-Christophe PLAGNIOL-VILLARD #define EE_DATA_WRITE 0x04 /* EEPROM chip data in. */
962439e4bfSJean-Christophe PLAGNIOL-VILLARD #define EE_WRITE_0 0x01
972439e4bfSJean-Christophe PLAGNIOL-VILLARD #define EE_WRITE_1 0x05
982439e4bfSJean-Christophe PLAGNIOL-VILLARD #define EE_DATA_READ 0x08 /* EEPROM chip data out. */
992439e4bfSJean-Christophe PLAGNIOL-VILLARD #define EE_ENB (0x4800 | EE_CS)
1002439e4bfSJean-Christophe PLAGNIOL-VILLARD #define EE_CMD_BITS 3
1012439e4bfSJean-Christophe PLAGNIOL-VILLARD #define EE_DATA_BITS 16
1022439e4bfSJean-Christophe PLAGNIOL-VILLARD
1032439e4bfSJean-Christophe PLAGNIOL-VILLARD /* The EEPROM commands include the alway-set leading bit.
1042439e4bfSJean-Christophe PLAGNIOL-VILLARD */
1052439e4bfSJean-Christophe PLAGNIOL-VILLARD #define EE_EWENB_CMD (4 << addr_len)
1062439e4bfSJean-Christophe PLAGNIOL-VILLARD #define EE_WRITE_CMD (5 << addr_len)
1072439e4bfSJean-Christophe PLAGNIOL-VILLARD #define EE_READ_CMD (6 << addr_len)
1082439e4bfSJean-Christophe PLAGNIOL-VILLARD #define EE_ERASE_CMD (7 << addr_len)
1092439e4bfSJean-Christophe PLAGNIOL-VILLARD
1102439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Receive frame descriptors.
1112439e4bfSJean-Christophe PLAGNIOL-VILLARD */
1122439e4bfSJean-Christophe PLAGNIOL-VILLARD struct RxFD {
1132439e4bfSJean-Christophe PLAGNIOL-VILLARD volatile u16 status;
1142439e4bfSJean-Christophe PLAGNIOL-VILLARD volatile u16 control;
1152439e4bfSJean-Christophe PLAGNIOL-VILLARD volatile u32 link; /* struct RxFD * */
1162439e4bfSJean-Christophe PLAGNIOL-VILLARD volatile u32 rx_buf_addr; /* void * */
1172439e4bfSJean-Christophe PLAGNIOL-VILLARD volatile u32 count;
1182439e4bfSJean-Christophe PLAGNIOL-VILLARD
1192439e4bfSJean-Christophe PLAGNIOL-VILLARD volatile u8 data[PKTSIZE_ALIGN];
1202439e4bfSJean-Christophe PLAGNIOL-VILLARD };
1212439e4bfSJean-Christophe PLAGNIOL-VILLARD
1222439e4bfSJean-Christophe PLAGNIOL-VILLARD #define RFD_STATUS_C 0x8000 /* completion of received frame */
1232439e4bfSJean-Christophe PLAGNIOL-VILLARD #define RFD_STATUS_OK 0x2000 /* frame received with no errors */
1242439e4bfSJean-Christophe PLAGNIOL-VILLARD
1252439e4bfSJean-Christophe PLAGNIOL-VILLARD #define RFD_CONTROL_EL 0x8000 /* 1=last RFD in RFA */
1262439e4bfSJean-Christophe PLAGNIOL-VILLARD #define RFD_CONTROL_S 0x4000 /* 1=suspend RU after receiving frame */
1272439e4bfSJean-Christophe PLAGNIOL-VILLARD #define RFD_CONTROL_H 0x0010 /* 1=RFD is a header RFD */
1282439e4bfSJean-Christophe PLAGNIOL-VILLARD #define RFD_CONTROL_SF 0x0008 /* 0=simplified, 1=flexible mode */
1292439e4bfSJean-Christophe PLAGNIOL-VILLARD
1302439e4bfSJean-Christophe PLAGNIOL-VILLARD #define RFD_COUNT_MASK 0x3fff
1312439e4bfSJean-Christophe PLAGNIOL-VILLARD #define RFD_COUNT_F 0x4000
1322439e4bfSJean-Christophe PLAGNIOL-VILLARD #define RFD_COUNT_EOF 0x8000
1332439e4bfSJean-Christophe PLAGNIOL-VILLARD
1342439e4bfSJean-Christophe PLAGNIOL-VILLARD #define RFD_RX_CRC 0x0800 /* crc error */
1352439e4bfSJean-Christophe PLAGNIOL-VILLARD #define RFD_RX_ALIGNMENT 0x0400 /* alignment error */
1362439e4bfSJean-Christophe PLAGNIOL-VILLARD #define RFD_RX_RESOURCE 0x0200 /* out of space, no resources */
1372439e4bfSJean-Christophe PLAGNIOL-VILLARD #define RFD_RX_DMA_OVER 0x0100 /* DMA overrun */
1382439e4bfSJean-Christophe PLAGNIOL-VILLARD #define RFD_RX_SHORT 0x0080 /* short frame error */
1392439e4bfSJean-Christophe PLAGNIOL-VILLARD #define RFD_RX_LENGTH 0x0020
1402439e4bfSJean-Christophe PLAGNIOL-VILLARD #define RFD_RX_ERROR 0x0010 /* receive error */
1412439e4bfSJean-Christophe PLAGNIOL-VILLARD #define RFD_RX_NO_ADR_MATCH 0x0004 /* no address match */
1422439e4bfSJean-Christophe PLAGNIOL-VILLARD #define RFD_RX_IA_MATCH 0x0002 /* individual address does not match */
1432439e4bfSJean-Christophe PLAGNIOL-VILLARD #define RFD_RX_TCO 0x0001 /* TCO indication */
1442439e4bfSJean-Christophe PLAGNIOL-VILLARD
1452439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Transmit frame descriptors
1462439e4bfSJean-Christophe PLAGNIOL-VILLARD */
1472439e4bfSJean-Christophe PLAGNIOL-VILLARD struct TxFD { /* Transmit frame descriptor set. */
1482439e4bfSJean-Christophe PLAGNIOL-VILLARD volatile u16 status;
1492439e4bfSJean-Christophe PLAGNIOL-VILLARD volatile u16 command;
1502439e4bfSJean-Christophe PLAGNIOL-VILLARD volatile u32 link; /* void * */
1512439e4bfSJean-Christophe PLAGNIOL-VILLARD volatile u32 tx_desc_addr; /* Always points to the tx_buf_addr element. */
1522439e4bfSJean-Christophe PLAGNIOL-VILLARD volatile s32 count;
1532439e4bfSJean-Christophe PLAGNIOL-VILLARD
1542439e4bfSJean-Christophe PLAGNIOL-VILLARD volatile u32 tx_buf_addr0; /* void *, frame to be transmitted. */
1552439e4bfSJean-Christophe PLAGNIOL-VILLARD volatile s32 tx_buf_size0; /* Length of Tx frame. */
1562439e4bfSJean-Christophe PLAGNIOL-VILLARD volatile u32 tx_buf_addr1; /* void *, frame to be transmitted. */
1572439e4bfSJean-Christophe PLAGNIOL-VILLARD volatile s32 tx_buf_size1; /* Length of Tx frame. */
1582439e4bfSJean-Christophe PLAGNIOL-VILLARD };
1592439e4bfSJean-Christophe PLAGNIOL-VILLARD
1602439e4bfSJean-Christophe PLAGNIOL-VILLARD #define TxCB_CMD_TRANSMIT 0x0004 /* transmit command */
1612439e4bfSJean-Christophe PLAGNIOL-VILLARD #define TxCB_CMD_SF 0x0008 /* 0=simplified, 1=flexible mode */
1622439e4bfSJean-Christophe PLAGNIOL-VILLARD #define TxCB_CMD_NC 0x0010 /* 0=CRC insert by controller */
1632439e4bfSJean-Christophe PLAGNIOL-VILLARD #define TxCB_CMD_I 0x2000 /* generate interrupt on completion */
1642439e4bfSJean-Christophe PLAGNIOL-VILLARD #define TxCB_CMD_S 0x4000 /* suspend on completion */
1652439e4bfSJean-Christophe PLAGNIOL-VILLARD #define TxCB_CMD_EL 0x8000 /* last command block in CBL */
1662439e4bfSJean-Christophe PLAGNIOL-VILLARD
1672439e4bfSJean-Christophe PLAGNIOL-VILLARD #define TxCB_COUNT_MASK 0x3fff
1682439e4bfSJean-Christophe PLAGNIOL-VILLARD #define TxCB_COUNT_EOF 0x8000
1692439e4bfSJean-Christophe PLAGNIOL-VILLARD
1702439e4bfSJean-Christophe PLAGNIOL-VILLARD /* The Speedo3 Rx and Tx frame/buffer descriptors.
1712439e4bfSJean-Christophe PLAGNIOL-VILLARD */
1722439e4bfSJean-Christophe PLAGNIOL-VILLARD struct descriptor { /* A generic descriptor. */
1732439e4bfSJean-Christophe PLAGNIOL-VILLARD volatile u16 status;
1742439e4bfSJean-Christophe PLAGNIOL-VILLARD volatile u16 command;
1752439e4bfSJean-Christophe PLAGNIOL-VILLARD volatile u32 link; /* struct descriptor * */
1762439e4bfSJean-Christophe PLAGNIOL-VILLARD
1772439e4bfSJean-Christophe PLAGNIOL-VILLARD unsigned char params[0];
1782439e4bfSJean-Christophe PLAGNIOL-VILLARD };
1792439e4bfSJean-Christophe PLAGNIOL-VILLARD
1806d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_CMD_EL 0x8000
1816d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_CMD_SUSPEND 0x4000
1826d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_CMD_INT 0x2000
1836d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_CMD_IAS 0x0001 /* individual address setup */
1846d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_CMD_CONFIGURE 0x0002 /* configure */
1852439e4bfSJean-Christophe PLAGNIOL-VILLARD
1866d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_STATUS_C 0x8000
1876d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_STATUS_OK 0x2000
1882439e4bfSJean-Christophe PLAGNIOL-VILLARD
1892439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Misc.
1902439e4bfSJean-Christophe PLAGNIOL-VILLARD */
1912439e4bfSJean-Christophe PLAGNIOL-VILLARD #define NUM_RX_DESC PKTBUFSRX
1922439e4bfSJean-Christophe PLAGNIOL-VILLARD #define NUM_TX_DESC 1 /* Number of TX descriptors */
1932439e4bfSJean-Christophe PLAGNIOL-VILLARD
1942439e4bfSJean-Christophe PLAGNIOL-VILLARD #define TOUT_LOOP 1000000
1952439e4bfSJean-Christophe PLAGNIOL-VILLARD
1962439e4bfSJean-Christophe PLAGNIOL-VILLARD static struct RxFD rx_ring[NUM_RX_DESC]; /* RX descriptor ring */
1972439e4bfSJean-Christophe PLAGNIOL-VILLARD static struct TxFD tx_ring[NUM_TX_DESC]; /* TX descriptor ring */
1982439e4bfSJean-Christophe PLAGNIOL-VILLARD static int rx_next; /* RX descriptor ring pointer */
1992439e4bfSJean-Christophe PLAGNIOL-VILLARD static int tx_next; /* TX descriptor ring pointer */
2002439e4bfSJean-Christophe PLAGNIOL-VILLARD static int tx_threshold;
2012439e4bfSJean-Christophe PLAGNIOL-VILLARD
2022439e4bfSJean-Christophe PLAGNIOL-VILLARD /*
2032439e4bfSJean-Christophe PLAGNIOL-VILLARD * The parameters for a CmdConfigure operation.
2042439e4bfSJean-Christophe PLAGNIOL-VILLARD * There are so many options that it would be difficult to document
2052439e4bfSJean-Christophe PLAGNIOL-VILLARD * each bit. We mostly use the default or recommended settings.
2062439e4bfSJean-Christophe PLAGNIOL-VILLARD */
2072439e4bfSJean-Christophe PLAGNIOL-VILLARD static const char i82558_config_cmd[] = {
2082439e4bfSJean-Christophe PLAGNIOL-VILLARD 22, 0x08, 0, 1, 0, 0, 0x22, 0x03, 1, /* 1=Use MII 0=Use AUI */
2092439e4bfSJean-Christophe PLAGNIOL-VILLARD 0, 0x2E, 0, 0x60, 0x08, 0x88,
2102439e4bfSJean-Christophe PLAGNIOL-VILLARD 0x68, 0, 0x40, 0xf2, 0x84, /* Disable FC */
2112439e4bfSJean-Christophe PLAGNIOL-VILLARD 0x31, 0x05,
2122439e4bfSJean-Christophe PLAGNIOL-VILLARD };
2132439e4bfSJean-Christophe PLAGNIOL-VILLARD
2142439e4bfSJean-Christophe PLAGNIOL-VILLARD static void init_rx_ring (struct eth_device *dev);
2152439e4bfSJean-Christophe PLAGNIOL-VILLARD static void purge_tx_ring (struct eth_device *dev);
2162439e4bfSJean-Christophe PLAGNIOL-VILLARD
2172439e4bfSJean-Christophe PLAGNIOL-VILLARD static void read_hw_addr (struct eth_device *dev, bd_t * bis);
2182439e4bfSJean-Christophe PLAGNIOL-VILLARD
2192439e4bfSJean-Christophe PLAGNIOL-VILLARD static int eepro100_init (struct eth_device *dev, bd_t * bis);
220bccbe619SJoe Hershberger static int eepro100_send(struct eth_device *dev, void *packet, int length);
2212439e4bfSJean-Christophe PLAGNIOL-VILLARD static int eepro100_recv (struct eth_device *dev);
2222439e4bfSJean-Christophe PLAGNIOL-VILLARD static void eepro100_halt (struct eth_device *dev);
2232439e4bfSJean-Christophe PLAGNIOL-VILLARD
22403b00407SWolfgang Denk #if defined(CONFIG_E500)
2252439e4bfSJean-Christophe PLAGNIOL-VILLARD #define bus_to_phys(a) (a)
2262439e4bfSJean-Christophe PLAGNIOL-VILLARD #define phys_to_bus(a) (a)
2272439e4bfSJean-Christophe PLAGNIOL-VILLARD #else
2282439e4bfSJean-Christophe PLAGNIOL-VILLARD #define bus_to_phys(a) pci_mem_to_phys((pci_dev_t)dev->priv, a)
2292439e4bfSJean-Christophe PLAGNIOL-VILLARD #define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)dev->priv, a)
2302439e4bfSJean-Christophe PLAGNIOL-VILLARD #endif
2312439e4bfSJean-Christophe PLAGNIOL-VILLARD
INW(struct eth_device * dev,u_long addr)2322439e4bfSJean-Christophe PLAGNIOL-VILLARD static inline int INW (struct eth_device *dev, u_long addr)
2332439e4bfSJean-Christophe PLAGNIOL-VILLARD {
234e6655d7cSBin Meng return le16_to_cpu(*(volatile u16 *)(addr + (u_long)dev->iobase));
2352439e4bfSJean-Christophe PLAGNIOL-VILLARD }
2362439e4bfSJean-Christophe PLAGNIOL-VILLARD
OUTW(struct eth_device * dev,int command,u_long addr)2372439e4bfSJean-Christophe PLAGNIOL-VILLARD static inline void OUTW (struct eth_device *dev, int command, u_long addr)
2382439e4bfSJean-Christophe PLAGNIOL-VILLARD {
239e6655d7cSBin Meng *(volatile u16 *)((addr + (u_long)dev->iobase)) = cpu_to_le16(command);
2402439e4bfSJean-Christophe PLAGNIOL-VILLARD }
2412439e4bfSJean-Christophe PLAGNIOL-VILLARD
OUTL(struct eth_device * dev,int command,u_long addr)2422439e4bfSJean-Christophe PLAGNIOL-VILLARD static inline void OUTL (struct eth_device *dev, int command, u_long addr)
2432439e4bfSJean-Christophe PLAGNIOL-VILLARD {
244e6655d7cSBin Meng *(volatile u32 *)((addr + (u_long)dev->iobase)) = cpu_to_le32(command);
2452439e4bfSJean-Christophe PLAGNIOL-VILLARD }
2462439e4bfSJean-Christophe PLAGNIOL-VILLARD
2472439e4bfSJean-Christophe PLAGNIOL-VILLARD #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
INL(struct eth_device * dev,u_long addr)2482439e4bfSJean-Christophe PLAGNIOL-VILLARD static inline int INL (struct eth_device *dev, u_long addr)
2492439e4bfSJean-Christophe PLAGNIOL-VILLARD {
250e6655d7cSBin Meng return le32_to_cpu(*(volatile u32 *)(addr + (u_long)dev->iobase));
2512439e4bfSJean-Christophe PLAGNIOL-VILLARD }
2522439e4bfSJean-Christophe PLAGNIOL-VILLARD
get_phyreg(struct eth_device * dev,unsigned char addr,unsigned char reg,unsigned short * value)2532439e4bfSJean-Christophe PLAGNIOL-VILLARD static int get_phyreg (struct eth_device *dev, unsigned char addr,
2542439e4bfSJean-Christophe PLAGNIOL-VILLARD unsigned char reg, unsigned short *value)
2552439e4bfSJean-Christophe PLAGNIOL-VILLARD {
2562439e4bfSJean-Christophe PLAGNIOL-VILLARD int cmd;
2572439e4bfSJean-Christophe PLAGNIOL-VILLARD int timeout = 50;
2582439e4bfSJean-Christophe PLAGNIOL-VILLARD
2592439e4bfSJean-Christophe PLAGNIOL-VILLARD /* read requested data */
2602439e4bfSJean-Christophe PLAGNIOL-VILLARD cmd = (2 << 26) | ((addr & 0x1f) << 21) | ((reg & 0x1f) << 16);
2612439e4bfSJean-Christophe PLAGNIOL-VILLARD OUTL (dev, cmd, SCBCtrlMDI);
2622439e4bfSJean-Christophe PLAGNIOL-VILLARD
2632439e4bfSJean-Christophe PLAGNIOL-VILLARD do {
2642439e4bfSJean-Christophe PLAGNIOL-VILLARD udelay(1000);
2652439e4bfSJean-Christophe PLAGNIOL-VILLARD cmd = INL (dev, SCBCtrlMDI);
2662439e4bfSJean-Christophe PLAGNIOL-VILLARD } while (!(cmd & (1 << 28)) && (--timeout));
2672439e4bfSJean-Christophe PLAGNIOL-VILLARD
2682439e4bfSJean-Christophe PLAGNIOL-VILLARD if (timeout == 0)
2692439e4bfSJean-Christophe PLAGNIOL-VILLARD return -1;
2702439e4bfSJean-Christophe PLAGNIOL-VILLARD
2712439e4bfSJean-Christophe PLAGNIOL-VILLARD *value = (unsigned short) (cmd & 0xffff);
2722439e4bfSJean-Christophe PLAGNIOL-VILLARD
2732439e4bfSJean-Christophe PLAGNIOL-VILLARD return 0;
2742439e4bfSJean-Christophe PLAGNIOL-VILLARD }
2752439e4bfSJean-Christophe PLAGNIOL-VILLARD
set_phyreg(struct eth_device * dev,unsigned char addr,unsigned char reg,unsigned short value)2762439e4bfSJean-Christophe PLAGNIOL-VILLARD static int set_phyreg (struct eth_device *dev, unsigned char addr,
2772439e4bfSJean-Christophe PLAGNIOL-VILLARD unsigned char reg, unsigned short value)
2782439e4bfSJean-Christophe PLAGNIOL-VILLARD {
2792439e4bfSJean-Christophe PLAGNIOL-VILLARD int cmd;
2802439e4bfSJean-Christophe PLAGNIOL-VILLARD int timeout = 50;
2812439e4bfSJean-Christophe PLAGNIOL-VILLARD
2822439e4bfSJean-Christophe PLAGNIOL-VILLARD /* write requested data */
2832439e4bfSJean-Christophe PLAGNIOL-VILLARD cmd = (1 << 26) | ((addr & 0x1f) << 21) | ((reg & 0x1f) << 16);
2842439e4bfSJean-Christophe PLAGNIOL-VILLARD OUTL (dev, cmd | value, SCBCtrlMDI);
2852439e4bfSJean-Christophe PLAGNIOL-VILLARD
2862439e4bfSJean-Christophe PLAGNIOL-VILLARD while (!(INL (dev, SCBCtrlMDI) & (1 << 28)) && (--timeout))
2872439e4bfSJean-Christophe PLAGNIOL-VILLARD udelay(1000);
2882439e4bfSJean-Christophe PLAGNIOL-VILLARD
2892439e4bfSJean-Christophe PLAGNIOL-VILLARD if (timeout == 0)
2902439e4bfSJean-Christophe PLAGNIOL-VILLARD return -1;
2912439e4bfSJean-Christophe PLAGNIOL-VILLARD
2922439e4bfSJean-Christophe PLAGNIOL-VILLARD return 0;
2932439e4bfSJean-Christophe PLAGNIOL-VILLARD }
2942439e4bfSJean-Christophe PLAGNIOL-VILLARD
2952439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Check if given phyaddr is valid, i.e. there is a PHY connected.
2962439e4bfSJean-Christophe PLAGNIOL-VILLARD * Do this by checking model value field from ID2 register.
2972439e4bfSJean-Christophe PLAGNIOL-VILLARD */
verify_phyaddr(const char * devname,unsigned char addr)298d7fb9bcfSBen Warren static struct eth_device* verify_phyaddr (const char *devname,
299d7fb9bcfSBen Warren unsigned char addr)
3002439e4bfSJean-Christophe PLAGNIOL-VILLARD {
3012439e4bfSJean-Christophe PLAGNIOL-VILLARD struct eth_device *dev;
3022439e4bfSJean-Christophe PLAGNIOL-VILLARD unsigned short value;
3032439e4bfSJean-Christophe PLAGNIOL-VILLARD unsigned char model;
3042439e4bfSJean-Christophe PLAGNIOL-VILLARD
3052439e4bfSJean-Christophe PLAGNIOL-VILLARD dev = eth_get_dev_by_name(devname);
3062439e4bfSJean-Christophe PLAGNIOL-VILLARD if (dev == NULL) {
3072439e4bfSJean-Christophe PLAGNIOL-VILLARD printf("%s: no such device\n", devname);
3082439e4bfSJean-Christophe PLAGNIOL-VILLARD return NULL;
3092439e4bfSJean-Christophe PLAGNIOL-VILLARD }
3102439e4bfSJean-Christophe PLAGNIOL-VILLARD
3112439e4bfSJean-Christophe PLAGNIOL-VILLARD /* read id2 register */
3128ef583a0SMike Frysinger if (get_phyreg(dev, addr, MII_PHYSID2, &value) != 0) {
3132439e4bfSJean-Christophe PLAGNIOL-VILLARD printf("%s: mii read timeout!\n", devname);
3142439e4bfSJean-Christophe PLAGNIOL-VILLARD return NULL;
3152439e4bfSJean-Christophe PLAGNIOL-VILLARD }
3162439e4bfSJean-Christophe PLAGNIOL-VILLARD
3172439e4bfSJean-Christophe PLAGNIOL-VILLARD /* get model */
3182439e4bfSJean-Christophe PLAGNIOL-VILLARD model = (unsigned char)((value >> 4) & 0x003f);
3192439e4bfSJean-Christophe PLAGNIOL-VILLARD
3202439e4bfSJean-Christophe PLAGNIOL-VILLARD if (model == 0) {
3212439e4bfSJean-Christophe PLAGNIOL-VILLARD printf("%s: no PHY at address %d\n", devname, addr);
3222439e4bfSJean-Christophe PLAGNIOL-VILLARD return NULL;
3232439e4bfSJean-Christophe PLAGNIOL-VILLARD }
3242439e4bfSJean-Christophe PLAGNIOL-VILLARD
3252439e4bfSJean-Christophe PLAGNIOL-VILLARD return dev;
3262439e4bfSJean-Christophe PLAGNIOL-VILLARD }
3272439e4bfSJean-Christophe PLAGNIOL-VILLARD
eepro100_miiphy_read(struct mii_dev * bus,int addr,int devad,int reg)3285a49f174SJoe Hershberger static int eepro100_miiphy_read(struct mii_dev *bus, int addr, int devad,
3295a49f174SJoe Hershberger int reg)
3302439e4bfSJean-Christophe PLAGNIOL-VILLARD {
3315a49f174SJoe Hershberger unsigned short value = 0;
3322439e4bfSJean-Christophe PLAGNIOL-VILLARD struct eth_device *dev;
3332439e4bfSJean-Christophe PLAGNIOL-VILLARD
3345a49f174SJoe Hershberger dev = verify_phyaddr(bus->name, addr);
3352439e4bfSJean-Christophe PLAGNIOL-VILLARD if (dev == NULL)
3362439e4bfSJean-Christophe PLAGNIOL-VILLARD return -1;
3372439e4bfSJean-Christophe PLAGNIOL-VILLARD
3385a49f174SJoe Hershberger if (get_phyreg(dev, addr, reg, &value) != 0) {
3395a49f174SJoe Hershberger printf("%s: mii read timeout!\n", bus->name);
3402439e4bfSJean-Christophe PLAGNIOL-VILLARD return -1;
3412439e4bfSJean-Christophe PLAGNIOL-VILLARD }
3422439e4bfSJean-Christophe PLAGNIOL-VILLARD
3435a49f174SJoe Hershberger return value;
3442439e4bfSJean-Christophe PLAGNIOL-VILLARD }
3452439e4bfSJean-Christophe PLAGNIOL-VILLARD
eepro100_miiphy_write(struct mii_dev * bus,int addr,int devad,int reg,u16 value)3465a49f174SJoe Hershberger static int eepro100_miiphy_write(struct mii_dev *bus, int addr, int devad,
3475a49f174SJoe Hershberger int reg, u16 value)
3482439e4bfSJean-Christophe PLAGNIOL-VILLARD {
3492439e4bfSJean-Christophe PLAGNIOL-VILLARD struct eth_device *dev;
3502439e4bfSJean-Christophe PLAGNIOL-VILLARD
3515a49f174SJoe Hershberger dev = verify_phyaddr(bus->name, addr);
3522439e4bfSJean-Christophe PLAGNIOL-VILLARD if (dev == NULL)
3532439e4bfSJean-Christophe PLAGNIOL-VILLARD return -1;
3542439e4bfSJean-Christophe PLAGNIOL-VILLARD
3552439e4bfSJean-Christophe PLAGNIOL-VILLARD if (set_phyreg(dev, addr, reg, value) != 0) {
3565a49f174SJoe Hershberger printf("%s: mii write timeout!\n", bus->name);
3572439e4bfSJean-Christophe PLAGNIOL-VILLARD return -1;
3582439e4bfSJean-Christophe PLAGNIOL-VILLARD }
3592439e4bfSJean-Christophe PLAGNIOL-VILLARD
3602439e4bfSJean-Christophe PLAGNIOL-VILLARD return 0;
3612439e4bfSJean-Christophe PLAGNIOL-VILLARD }
3622439e4bfSJean-Christophe PLAGNIOL-VILLARD
3632439e4bfSJean-Christophe PLAGNIOL-VILLARD #endif
3642439e4bfSJean-Christophe PLAGNIOL-VILLARD
3652439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Wait for the chip get the command.
3662439e4bfSJean-Christophe PLAGNIOL-VILLARD */
wait_for_eepro100(struct eth_device * dev)3672439e4bfSJean-Christophe PLAGNIOL-VILLARD static int wait_for_eepro100 (struct eth_device *dev)
3682439e4bfSJean-Christophe PLAGNIOL-VILLARD {
3692439e4bfSJean-Christophe PLAGNIOL-VILLARD int i;
3702439e4bfSJean-Christophe PLAGNIOL-VILLARD
3712439e4bfSJean-Christophe PLAGNIOL-VILLARD for (i = 0; INW (dev, SCBCmd) & (CU_CMD_MASK | RU_CMD_MASK); i++) {
3722439e4bfSJean-Christophe PLAGNIOL-VILLARD if (i >= TOUT_LOOP) {
3732439e4bfSJean-Christophe PLAGNIOL-VILLARD return 0;
3742439e4bfSJean-Christophe PLAGNIOL-VILLARD }
3752439e4bfSJean-Christophe PLAGNIOL-VILLARD }
3762439e4bfSJean-Christophe PLAGNIOL-VILLARD
3772439e4bfSJean-Christophe PLAGNIOL-VILLARD return 1;
3782439e4bfSJean-Christophe PLAGNIOL-VILLARD }
3792439e4bfSJean-Christophe PLAGNIOL-VILLARD
3802439e4bfSJean-Christophe PLAGNIOL-VILLARD static struct pci_device_id supported[] = {
3812439e4bfSJean-Christophe PLAGNIOL-VILLARD {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82557},
3822439e4bfSJean-Christophe PLAGNIOL-VILLARD {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82559},
3832439e4bfSJean-Christophe PLAGNIOL-VILLARD {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82559ER},
3842439e4bfSJean-Christophe PLAGNIOL-VILLARD {}
3852439e4bfSJean-Christophe PLAGNIOL-VILLARD };
3862439e4bfSJean-Christophe PLAGNIOL-VILLARD
eepro100_initialize(bd_t * bis)3872439e4bfSJean-Christophe PLAGNIOL-VILLARD int eepro100_initialize (bd_t * bis)
3882439e4bfSJean-Christophe PLAGNIOL-VILLARD {
3892439e4bfSJean-Christophe PLAGNIOL-VILLARD pci_dev_t devno;
3902439e4bfSJean-Christophe PLAGNIOL-VILLARD int card_number = 0;
3912439e4bfSJean-Christophe PLAGNIOL-VILLARD struct eth_device *dev;
3922439e4bfSJean-Christophe PLAGNIOL-VILLARD u32 iobase, status;
3932439e4bfSJean-Christophe PLAGNIOL-VILLARD int idx = 0;
3942439e4bfSJean-Christophe PLAGNIOL-VILLARD
3952439e4bfSJean-Christophe PLAGNIOL-VILLARD while (1) {
3962439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Find PCI device
3972439e4bfSJean-Christophe PLAGNIOL-VILLARD */
3982439e4bfSJean-Christophe PLAGNIOL-VILLARD if ((devno = pci_find_devices (supported, idx++)) < 0) {
3992439e4bfSJean-Christophe PLAGNIOL-VILLARD break;
4002439e4bfSJean-Christophe PLAGNIOL-VILLARD }
4012439e4bfSJean-Christophe PLAGNIOL-VILLARD
4022439e4bfSJean-Christophe PLAGNIOL-VILLARD pci_read_config_dword (devno, PCI_BASE_ADDRESS_0, &iobase);
4032439e4bfSJean-Christophe PLAGNIOL-VILLARD iobase &= ~0xf;
4042439e4bfSJean-Christophe PLAGNIOL-VILLARD
4052439e4bfSJean-Christophe PLAGNIOL-VILLARD #ifdef DEBUG
4062439e4bfSJean-Christophe PLAGNIOL-VILLARD printf ("eepro100: Intel i82559 PCI EtherExpressPro @0x%x\n",
4072439e4bfSJean-Christophe PLAGNIOL-VILLARD iobase);
4082439e4bfSJean-Christophe PLAGNIOL-VILLARD #endif
4092439e4bfSJean-Christophe PLAGNIOL-VILLARD
4102439e4bfSJean-Christophe PLAGNIOL-VILLARD pci_write_config_dword (devno,
4112439e4bfSJean-Christophe PLAGNIOL-VILLARD PCI_COMMAND,
4122439e4bfSJean-Christophe PLAGNIOL-VILLARD PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
4132439e4bfSJean-Christophe PLAGNIOL-VILLARD
4142439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Check if I/O accesses and Bus Mastering are enabled.
4152439e4bfSJean-Christophe PLAGNIOL-VILLARD */
4162439e4bfSJean-Christophe PLAGNIOL-VILLARD pci_read_config_dword (devno, PCI_COMMAND, &status);
4172439e4bfSJean-Christophe PLAGNIOL-VILLARD if (!(status & PCI_COMMAND_MEMORY)) {
4182439e4bfSJean-Christophe PLAGNIOL-VILLARD printf ("Error: Can not enable MEM access.\n");
4192439e4bfSJean-Christophe PLAGNIOL-VILLARD continue;
4202439e4bfSJean-Christophe PLAGNIOL-VILLARD }
4212439e4bfSJean-Christophe PLAGNIOL-VILLARD
4222439e4bfSJean-Christophe PLAGNIOL-VILLARD if (!(status & PCI_COMMAND_MASTER)) {
4232439e4bfSJean-Christophe PLAGNIOL-VILLARD printf ("Error: Can not enable Bus Mastering.\n");
4242439e4bfSJean-Christophe PLAGNIOL-VILLARD continue;
4252439e4bfSJean-Christophe PLAGNIOL-VILLARD }
4262439e4bfSJean-Christophe PLAGNIOL-VILLARD
4272439e4bfSJean-Christophe PLAGNIOL-VILLARD dev = (struct eth_device *) malloc (sizeof *dev);
42872c4c33eSNobuhiro Iwamatsu if (!dev) {
42972c4c33eSNobuhiro Iwamatsu printf("eepro100: Can not allocate memory\n");
43072c4c33eSNobuhiro Iwamatsu break;
43172c4c33eSNobuhiro Iwamatsu }
43272c4c33eSNobuhiro Iwamatsu memset(dev, 0, sizeof(*dev));
4332439e4bfSJean-Christophe PLAGNIOL-VILLARD
4342439e4bfSJean-Christophe PLAGNIOL-VILLARD sprintf (dev->name, "i82559#%d", card_number);
4352439e4bfSJean-Christophe PLAGNIOL-VILLARD dev->priv = (void *) devno; /* this have to come before bus_to_phys() */
4362439e4bfSJean-Christophe PLAGNIOL-VILLARD dev->iobase = bus_to_phys (iobase);
4372439e4bfSJean-Christophe PLAGNIOL-VILLARD dev->init = eepro100_init;
4382439e4bfSJean-Christophe PLAGNIOL-VILLARD dev->halt = eepro100_halt;
4392439e4bfSJean-Christophe PLAGNIOL-VILLARD dev->send = eepro100_send;
4402439e4bfSJean-Christophe PLAGNIOL-VILLARD dev->recv = eepro100_recv;
4412439e4bfSJean-Christophe PLAGNIOL-VILLARD
4422439e4bfSJean-Christophe PLAGNIOL-VILLARD eth_register (dev);
4432439e4bfSJean-Christophe PLAGNIOL-VILLARD
4442439e4bfSJean-Christophe PLAGNIOL-VILLARD #if defined (CONFIG_MII) || defined(CONFIG_CMD_MII)
4452439e4bfSJean-Christophe PLAGNIOL-VILLARD /* register mii command access routines */
4465a49f174SJoe Hershberger int retval;
4475a49f174SJoe Hershberger struct mii_dev *mdiodev = mdio_alloc();
4485a49f174SJoe Hershberger if (!mdiodev)
4495a49f174SJoe Hershberger return -ENOMEM;
4505a49f174SJoe Hershberger strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
4515a49f174SJoe Hershberger mdiodev->read = eepro100_miiphy_read;
4525a49f174SJoe Hershberger mdiodev->write = eepro100_miiphy_write;
4535a49f174SJoe Hershberger
4545a49f174SJoe Hershberger retval = mdio_register(mdiodev);
4555a49f174SJoe Hershberger if (retval < 0)
4565a49f174SJoe Hershberger return retval;
4572439e4bfSJean-Christophe PLAGNIOL-VILLARD #endif
4582439e4bfSJean-Christophe PLAGNIOL-VILLARD
4592439e4bfSJean-Christophe PLAGNIOL-VILLARD card_number++;
4602439e4bfSJean-Christophe PLAGNIOL-VILLARD
4612439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Set the latency timer for value.
4622439e4bfSJean-Christophe PLAGNIOL-VILLARD */
4632439e4bfSJean-Christophe PLAGNIOL-VILLARD pci_write_config_byte (devno, PCI_LATENCY_TIMER, 0x20);
4642439e4bfSJean-Christophe PLAGNIOL-VILLARD
4652439e4bfSJean-Christophe PLAGNIOL-VILLARD udelay (10 * 1000);
4662439e4bfSJean-Christophe PLAGNIOL-VILLARD
4672439e4bfSJean-Christophe PLAGNIOL-VILLARD read_hw_addr (dev, bis);
4682439e4bfSJean-Christophe PLAGNIOL-VILLARD }
4692439e4bfSJean-Christophe PLAGNIOL-VILLARD
4702439e4bfSJean-Christophe PLAGNIOL-VILLARD return card_number;
4712439e4bfSJean-Christophe PLAGNIOL-VILLARD }
4722439e4bfSJean-Christophe PLAGNIOL-VILLARD
4732439e4bfSJean-Christophe PLAGNIOL-VILLARD
eepro100_init(struct eth_device * dev,bd_t * bis)4742439e4bfSJean-Christophe PLAGNIOL-VILLARD static int eepro100_init (struct eth_device *dev, bd_t * bis)
4752439e4bfSJean-Christophe PLAGNIOL-VILLARD {
476422b1a01SBen Warren int i, status = -1;
4772439e4bfSJean-Christophe PLAGNIOL-VILLARD int tx_cur;
4782439e4bfSJean-Christophe PLAGNIOL-VILLARD struct descriptor *ias_cmd, *cfg_cmd;
4792439e4bfSJean-Christophe PLAGNIOL-VILLARD
4802439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Reset the ethernet controller
4812439e4bfSJean-Christophe PLAGNIOL-VILLARD */
4822439e4bfSJean-Christophe PLAGNIOL-VILLARD OUTL (dev, I82559_SELECTIVE_RESET, SCBPort);
4832439e4bfSJean-Christophe PLAGNIOL-VILLARD udelay (20);
4842439e4bfSJean-Christophe PLAGNIOL-VILLARD
4852439e4bfSJean-Christophe PLAGNIOL-VILLARD OUTL (dev, I82559_RESET, SCBPort);
4862439e4bfSJean-Christophe PLAGNIOL-VILLARD udelay (20);
4872439e4bfSJean-Christophe PLAGNIOL-VILLARD
4882439e4bfSJean-Christophe PLAGNIOL-VILLARD if (!wait_for_eepro100 (dev)) {
4892439e4bfSJean-Christophe PLAGNIOL-VILLARD printf ("Error: Can not reset ethernet controller.\n");
4902439e4bfSJean-Christophe PLAGNIOL-VILLARD goto Done;
4912439e4bfSJean-Christophe PLAGNIOL-VILLARD }
4922439e4bfSJean-Christophe PLAGNIOL-VILLARD OUTL (dev, 0, SCBPointer);
4932439e4bfSJean-Christophe PLAGNIOL-VILLARD OUTW (dev, SCB_M | RUC_ADDR_LOAD, SCBCmd);
4942439e4bfSJean-Christophe PLAGNIOL-VILLARD
4952439e4bfSJean-Christophe PLAGNIOL-VILLARD if (!wait_for_eepro100 (dev)) {
4962439e4bfSJean-Christophe PLAGNIOL-VILLARD printf ("Error: Can not reset ethernet controller.\n");
4972439e4bfSJean-Christophe PLAGNIOL-VILLARD goto Done;
4982439e4bfSJean-Christophe PLAGNIOL-VILLARD }
4992439e4bfSJean-Christophe PLAGNIOL-VILLARD OUTL (dev, 0, SCBPointer);
5002439e4bfSJean-Christophe PLAGNIOL-VILLARD OUTW (dev, SCB_M | CU_ADDR_LOAD, SCBCmd);
5012439e4bfSJean-Christophe PLAGNIOL-VILLARD
5022439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Initialize Rx and Tx rings.
5032439e4bfSJean-Christophe PLAGNIOL-VILLARD */
5042439e4bfSJean-Christophe PLAGNIOL-VILLARD init_rx_ring (dev);
5052439e4bfSJean-Christophe PLAGNIOL-VILLARD purge_tx_ring (dev);
5062439e4bfSJean-Christophe PLAGNIOL-VILLARD
5072439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Tell the adapter where the RX ring is located.
5082439e4bfSJean-Christophe PLAGNIOL-VILLARD */
5092439e4bfSJean-Christophe PLAGNIOL-VILLARD if (!wait_for_eepro100 (dev)) {
5102439e4bfSJean-Christophe PLAGNIOL-VILLARD printf ("Error: Can not reset ethernet controller.\n");
5112439e4bfSJean-Christophe PLAGNIOL-VILLARD goto Done;
5122439e4bfSJean-Christophe PLAGNIOL-VILLARD }
5132439e4bfSJean-Christophe PLAGNIOL-VILLARD
5142439e4bfSJean-Christophe PLAGNIOL-VILLARD OUTL (dev, phys_to_bus ((u32) & rx_ring[rx_next]), SCBPointer);
5152439e4bfSJean-Christophe PLAGNIOL-VILLARD OUTW (dev, SCB_M | RUC_START, SCBCmd);
5162439e4bfSJean-Christophe PLAGNIOL-VILLARD
5172439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Send the Configure frame */
5182439e4bfSJean-Christophe PLAGNIOL-VILLARD tx_cur = tx_next;
5192439e4bfSJean-Christophe PLAGNIOL-VILLARD tx_next = ((tx_next + 1) % NUM_TX_DESC);
5202439e4bfSJean-Christophe PLAGNIOL-VILLARD
5212439e4bfSJean-Christophe PLAGNIOL-VILLARD cfg_cmd = (struct descriptor *) &tx_ring[tx_cur];
5226d0f6bcfSJean-Christophe PLAGNIOL-VILLARD cfg_cmd->command = cpu_to_le16 ((CONFIG_SYS_CMD_SUSPEND | CONFIG_SYS_CMD_CONFIGURE));
5232439e4bfSJean-Christophe PLAGNIOL-VILLARD cfg_cmd->status = 0;
5242439e4bfSJean-Christophe PLAGNIOL-VILLARD cfg_cmd->link = cpu_to_le32 (phys_to_bus ((u32) & tx_ring[tx_next]));
5252439e4bfSJean-Christophe PLAGNIOL-VILLARD
5262439e4bfSJean-Christophe PLAGNIOL-VILLARD memcpy (cfg_cmd->params, i82558_config_cmd,
5272439e4bfSJean-Christophe PLAGNIOL-VILLARD sizeof (i82558_config_cmd));
5282439e4bfSJean-Christophe PLAGNIOL-VILLARD
5292439e4bfSJean-Christophe PLAGNIOL-VILLARD if (!wait_for_eepro100 (dev)) {
5306d0f6bcfSJean-Christophe PLAGNIOL-VILLARD printf ("Error---CONFIG_SYS_CMD_CONFIGURE: Can not reset ethernet controller.\n");
5312439e4bfSJean-Christophe PLAGNIOL-VILLARD goto Done;
5322439e4bfSJean-Christophe PLAGNIOL-VILLARD }
5332439e4bfSJean-Christophe PLAGNIOL-VILLARD
5342439e4bfSJean-Christophe PLAGNIOL-VILLARD OUTL (dev, phys_to_bus ((u32) & tx_ring[tx_cur]), SCBPointer);
5352439e4bfSJean-Christophe PLAGNIOL-VILLARD OUTW (dev, SCB_M | CU_START, SCBCmd);
5362439e4bfSJean-Christophe PLAGNIOL-VILLARD
5372439e4bfSJean-Christophe PLAGNIOL-VILLARD for (i = 0;
5386d0f6bcfSJean-Christophe PLAGNIOL-VILLARD !(le16_to_cpu (tx_ring[tx_cur].status) & CONFIG_SYS_STATUS_C);
5392439e4bfSJean-Christophe PLAGNIOL-VILLARD i++) {
5402439e4bfSJean-Christophe PLAGNIOL-VILLARD if (i >= TOUT_LOOP) {
5412439e4bfSJean-Christophe PLAGNIOL-VILLARD printf ("%s: Tx error buffer not ready\n", dev->name);
5422439e4bfSJean-Christophe PLAGNIOL-VILLARD goto Done;
5432439e4bfSJean-Christophe PLAGNIOL-VILLARD }
5442439e4bfSJean-Christophe PLAGNIOL-VILLARD }
5452439e4bfSJean-Christophe PLAGNIOL-VILLARD
5466d0f6bcfSJean-Christophe PLAGNIOL-VILLARD if (!(le16_to_cpu (tx_ring[tx_cur].status) & CONFIG_SYS_STATUS_OK)) {
5472439e4bfSJean-Christophe PLAGNIOL-VILLARD printf ("TX error status = 0x%08X\n",
5482439e4bfSJean-Christophe PLAGNIOL-VILLARD le16_to_cpu (tx_ring[tx_cur].status));
5492439e4bfSJean-Christophe PLAGNIOL-VILLARD goto Done;
5502439e4bfSJean-Christophe PLAGNIOL-VILLARD }
5512439e4bfSJean-Christophe PLAGNIOL-VILLARD
5522439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Send the Individual Address Setup frame
5532439e4bfSJean-Christophe PLAGNIOL-VILLARD */
5542439e4bfSJean-Christophe PLAGNIOL-VILLARD tx_cur = tx_next;
5552439e4bfSJean-Christophe PLAGNIOL-VILLARD tx_next = ((tx_next + 1) % NUM_TX_DESC);
5562439e4bfSJean-Christophe PLAGNIOL-VILLARD
5572439e4bfSJean-Christophe PLAGNIOL-VILLARD ias_cmd = (struct descriptor *) &tx_ring[tx_cur];
5586d0f6bcfSJean-Christophe PLAGNIOL-VILLARD ias_cmd->command = cpu_to_le16 ((CONFIG_SYS_CMD_SUSPEND | CONFIG_SYS_CMD_IAS));
5592439e4bfSJean-Christophe PLAGNIOL-VILLARD ias_cmd->status = 0;
5602439e4bfSJean-Christophe PLAGNIOL-VILLARD ias_cmd->link = cpu_to_le32 (phys_to_bus ((u32) & tx_ring[tx_next]));
5612439e4bfSJean-Christophe PLAGNIOL-VILLARD
5622439e4bfSJean-Christophe PLAGNIOL-VILLARD memcpy (ias_cmd->params, dev->enetaddr, 6);
5632439e4bfSJean-Christophe PLAGNIOL-VILLARD
5642439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Tell the adapter where the TX ring is located.
5652439e4bfSJean-Christophe PLAGNIOL-VILLARD */
5662439e4bfSJean-Christophe PLAGNIOL-VILLARD if (!wait_for_eepro100 (dev)) {
5672439e4bfSJean-Christophe PLAGNIOL-VILLARD printf ("Error: Can not reset ethernet controller.\n");
5682439e4bfSJean-Christophe PLAGNIOL-VILLARD goto Done;
5692439e4bfSJean-Christophe PLAGNIOL-VILLARD }
5702439e4bfSJean-Christophe PLAGNIOL-VILLARD
5712439e4bfSJean-Christophe PLAGNIOL-VILLARD OUTL (dev, phys_to_bus ((u32) & tx_ring[tx_cur]), SCBPointer);
5722439e4bfSJean-Christophe PLAGNIOL-VILLARD OUTW (dev, SCB_M | CU_START, SCBCmd);
5732439e4bfSJean-Christophe PLAGNIOL-VILLARD
5746d0f6bcfSJean-Christophe PLAGNIOL-VILLARD for (i = 0; !(le16_to_cpu (tx_ring[tx_cur].status) & CONFIG_SYS_STATUS_C);
5752439e4bfSJean-Christophe PLAGNIOL-VILLARD i++) {
5762439e4bfSJean-Christophe PLAGNIOL-VILLARD if (i >= TOUT_LOOP) {
5772439e4bfSJean-Christophe PLAGNIOL-VILLARD printf ("%s: Tx error buffer not ready\n",
5782439e4bfSJean-Christophe PLAGNIOL-VILLARD dev->name);
5792439e4bfSJean-Christophe PLAGNIOL-VILLARD goto Done;
5802439e4bfSJean-Christophe PLAGNIOL-VILLARD }
5812439e4bfSJean-Christophe PLAGNIOL-VILLARD }
5822439e4bfSJean-Christophe PLAGNIOL-VILLARD
5836d0f6bcfSJean-Christophe PLAGNIOL-VILLARD if (!(le16_to_cpu (tx_ring[tx_cur].status) & CONFIG_SYS_STATUS_OK)) {
5842439e4bfSJean-Christophe PLAGNIOL-VILLARD printf ("TX error status = 0x%08X\n",
5852439e4bfSJean-Christophe PLAGNIOL-VILLARD le16_to_cpu (tx_ring[tx_cur].status));
5862439e4bfSJean-Christophe PLAGNIOL-VILLARD goto Done;
5872439e4bfSJean-Christophe PLAGNIOL-VILLARD }
5882439e4bfSJean-Christophe PLAGNIOL-VILLARD
589422b1a01SBen Warren status = 0;
5902439e4bfSJean-Christophe PLAGNIOL-VILLARD
5912439e4bfSJean-Christophe PLAGNIOL-VILLARD Done:
5922439e4bfSJean-Christophe PLAGNIOL-VILLARD return status;
5932439e4bfSJean-Christophe PLAGNIOL-VILLARD }
5942439e4bfSJean-Christophe PLAGNIOL-VILLARD
eepro100_send(struct eth_device * dev,void * packet,int length)595bccbe619SJoe Hershberger static int eepro100_send(struct eth_device *dev, void *packet, int length)
5962439e4bfSJean-Christophe PLAGNIOL-VILLARD {
5972439e4bfSJean-Christophe PLAGNIOL-VILLARD int i, status = -1;
5982439e4bfSJean-Christophe PLAGNIOL-VILLARD int tx_cur;
5992439e4bfSJean-Christophe PLAGNIOL-VILLARD
6002439e4bfSJean-Christophe PLAGNIOL-VILLARD if (length <= 0) {
6012439e4bfSJean-Christophe PLAGNIOL-VILLARD printf ("%s: bad packet size: %d\n", dev->name, length);
6022439e4bfSJean-Christophe PLAGNIOL-VILLARD goto Done;
6032439e4bfSJean-Christophe PLAGNIOL-VILLARD }
6042439e4bfSJean-Christophe PLAGNIOL-VILLARD
6052439e4bfSJean-Christophe PLAGNIOL-VILLARD tx_cur = tx_next;
6062439e4bfSJean-Christophe PLAGNIOL-VILLARD tx_next = (tx_next + 1) % NUM_TX_DESC;
6072439e4bfSJean-Christophe PLAGNIOL-VILLARD
6082439e4bfSJean-Christophe PLAGNIOL-VILLARD tx_ring[tx_cur].command = cpu_to_le16 ( TxCB_CMD_TRANSMIT |
6092439e4bfSJean-Christophe PLAGNIOL-VILLARD TxCB_CMD_SF |
6102439e4bfSJean-Christophe PLAGNIOL-VILLARD TxCB_CMD_S |
6112439e4bfSJean-Christophe PLAGNIOL-VILLARD TxCB_CMD_EL );
6122439e4bfSJean-Christophe PLAGNIOL-VILLARD tx_ring[tx_cur].status = 0;
6132439e4bfSJean-Christophe PLAGNIOL-VILLARD tx_ring[tx_cur].count = cpu_to_le32 (tx_threshold);
6142439e4bfSJean-Christophe PLAGNIOL-VILLARD tx_ring[tx_cur].link =
6152439e4bfSJean-Christophe PLAGNIOL-VILLARD cpu_to_le32 (phys_to_bus ((u32) & tx_ring[tx_next]));
6162439e4bfSJean-Christophe PLAGNIOL-VILLARD tx_ring[tx_cur].tx_desc_addr =
6172439e4bfSJean-Christophe PLAGNIOL-VILLARD cpu_to_le32 (phys_to_bus ((u32) & tx_ring[tx_cur].tx_buf_addr0));
6182439e4bfSJean-Christophe PLAGNIOL-VILLARD tx_ring[tx_cur].tx_buf_addr0 =
6192439e4bfSJean-Christophe PLAGNIOL-VILLARD cpu_to_le32 (phys_to_bus ((u_long) packet));
6202439e4bfSJean-Christophe PLAGNIOL-VILLARD tx_ring[tx_cur].tx_buf_size0 = cpu_to_le32 (length);
6212439e4bfSJean-Christophe PLAGNIOL-VILLARD
6222439e4bfSJean-Christophe PLAGNIOL-VILLARD if (!wait_for_eepro100 (dev)) {
6232439e4bfSJean-Christophe PLAGNIOL-VILLARD printf ("%s: Tx error ethernet controller not ready.\n",
6242439e4bfSJean-Christophe PLAGNIOL-VILLARD dev->name);
6252439e4bfSJean-Christophe PLAGNIOL-VILLARD goto Done;
6262439e4bfSJean-Christophe PLAGNIOL-VILLARD }
6272439e4bfSJean-Christophe PLAGNIOL-VILLARD
6282439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Send the packet.
6292439e4bfSJean-Christophe PLAGNIOL-VILLARD */
6302439e4bfSJean-Christophe PLAGNIOL-VILLARD OUTL (dev, phys_to_bus ((u32) & tx_ring[tx_cur]), SCBPointer);
6312439e4bfSJean-Christophe PLAGNIOL-VILLARD OUTW (dev, SCB_M | CU_START, SCBCmd);
6322439e4bfSJean-Christophe PLAGNIOL-VILLARD
6336d0f6bcfSJean-Christophe PLAGNIOL-VILLARD for (i = 0; !(le16_to_cpu (tx_ring[tx_cur].status) & CONFIG_SYS_STATUS_C);
6342439e4bfSJean-Christophe PLAGNIOL-VILLARD i++) {
6352439e4bfSJean-Christophe PLAGNIOL-VILLARD if (i >= TOUT_LOOP) {
6362439e4bfSJean-Christophe PLAGNIOL-VILLARD printf ("%s: Tx error buffer not ready\n", dev->name);
6372439e4bfSJean-Christophe PLAGNIOL-VILLARD goto Done;
6382439e4bfSJean-Christophe PLAGNIOL-VILLARD }
6392439e4bfSJean-Christophe PLAGNIOL-VILLARD }
6402439e4bfSJean-Christophe PLAGNIOL-VILLARD
6416d0f6bcfSJean-Christophe PLAGNIOL-VILLARD if (!(le16_to_cpu (tx_ring[tx_cur].status) & CONFIG_SYS_STATUS_OK)) {
6422439e4bfSJean-Christophe PLAGNIOL-VILLARD printf ("TX error status = 0x%08X\n",
6432439e4bfSJean-Christophe PLAGNIOL-VILLARD le16_to_cpu (tx_ring[tx_cur].status));
6442439e4bfSJean-Christophe PLAGNIOL-VILLARD goto Done;
6452439e4bfSJean-Christophe PLAGNIOL-VILLARD }
6462439e4bfSJean-Christophe PLAGNIOL-VILLARD
6472439e4bfSJean-Christophe PLAGNIOL-VILLARD status = length;
6482439e4bfSJean-Christophe PLAGNIOL-VILLARD
6492439e4bfSJean-Christophe PLAGNIOL-VILLARD Done:
6502439e4bfSJean-Christophe PLAGNIOL-VILLARD return status;
6512439e4bfSJean-Christophe PLAGNIOL-VILLARD }
6522439e4bfSJean-Christophe PLAGNIOL-VILLARD
eepro100_recv(struct eth_device * dev)6532439e4bfSJean-Christophe PLAGNIOL-VILLARD static int eepro100_recv (struct eth_device *dev)
6542439e4bfSJean-Christophe PLAGNIOL-VILLARD {
6552439e4bfSJean-Christophe PLAGNIOL-VILLARD u16 status, stat;
6562439e4bfSJean-Christophe PLAGNIOL-VILLARD int rx_prev, length = 0;
6572439e4bfSJean-Christophe PLAGNIOL-VILLARD
6582439e4bfSJean-Christophe PLAGNIOL-VILLARD stat = INW (dev, SCBStatus);
6592439e4bfSJean-Christophe PLAGNIOL-VILLARD OUTW (dev, stat & SCB_STATUS_RNR, SCBStatus);
6602439e4bfSJean-Christophe PLAGNIOL-VILLARD
6612439e4bfSJean-Christophe PLAGNIOL-VILLARD for (;;) {
6622439e4bfSJean-Christophe PLAGNIOL-VILLARD status = le16_to_cpu (rx_ring[rx_next].status);
6632439e4bfSJean-Christophe PLAGNIOL-VILLARD
6642439e4bfSJean-Christophe PLAGNIOL-VILLARD if (!(status & RFD_STATUS_C)) {
6652439e4bfSJean-Christophe PLAGNIOL-VILLARD break;
6662439e4bfSJean-Christophe PLAGNIOL-VILLARD }
6672439e4bfSJean-Christophe PLAGNIOL-VILLARD
6682439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Valid frame status.
6692439e4bfSJean-Christophe PLAGNIOL-VILLARD */
6702439e4bfSJean-Christophe PLAGNIOL-VILLARD if ((status & RFD_STATUS_OK)) {
6712439e4bfSJean-Christophe PLAGNIOL-VILLARD /* A valid frame received.
6722439e4bfSJean-Christophe PLAGNIOL-VILLARD */
6732439e4bfSJean-Christophe PLAGNIOL-VILLARD length = le32_to_cpu (rx_ring[rx_next].count) & 0x3fff;
6742439e4bfSJean-Christophe PLAGNIOL-VILLARD
6752439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Pass the packet up to the protocol
6762439e4bfSJean-Christophe PLAGNIOL-VILLARD * layers.
6772439e4bfSJean-Christophe PLAGNIOL-VILLARD */
6781fd92db8SJoe Hershberger net_process_received_packet((u8 *)rx_ring[rx_next].data,
6791fd92db8SJoe Hershberger length);
6802439e4bfSJean-Christophe PLAGNIOL-VILLARD } else {
6812439e4bfSJean-Christophe PLAGNIOL-VILLARD /* There was an error.
6822439e4bfSJean-Christophe PLAGNIOL-VILLARD */
6832439e4bfSJean-Christophe PLAGNIOL-VILLARD printf ("RX error status = 0x%08X\n", status);
6842439e4bfSJean-Christophe PLAGNIOL-VILLARD }
6852439e4bfSJean-Christophe PLAGNIOL-VILLARD
6862439e4bfSJean-Christophe PLAGNIOL-VILLARD rx_ring[rx_next].control = cpu_to_le16 (RFD_CONTROL_S);
6872439e4bfSJean-Christophe PLAGNIOL-VILLARD rx_ring[rx_next].status = 0;
6882439e4bfSJean-Christophe PLAGNIOL-VILLARD rx_ring[rx_next].count = cpu_to_le32 (PKTSIZE_ALIGN << 16);
6892439e4bfSJean-Christophe PLAGNIOL-VILLARD
6902439e4bfSJean-Christophe PLAGNIOL-VILLARD rx_prev = (rx_next + NUM_RX_DESC - 1) % NUM_RX_DESC;
6912439e4bfSJean-Christophe PLAGNIOL-VILLARD rx_ring[rx_prev].control = 0;
6922439e4bfSJean-Christophe PLAGNIOL-VILLARD
6932439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Update entry information.
6942439e4bfSJean-Christophe PLAGNIOL-VILLARD */
6952439e4bfSJean-Christophe PLAGNIOL-VILLARD rx_next = (rx_next + 1) % NUM_RX_DESC;
6962439e4bfSJean-Christophe PLAGNIOL-VILLARD }
6972439e4bfSJean-Christophe PLAGNIOL-VILLARD
6982439e4bfSJean-Christophe PLAGNIOL-VILLARD if (stat & SCB_STATUS_RNR) {
6992439e4bfSJean-Christophe PLAGNIOL-VILLARD
7002439e4bfSJean-Christophe PLAGNIOL-VILLARD printf ("%s: Receiver is not ready, restart it !\n", dev->name);
7012439e4bfSJean-Christophe PLAGNIOL-VILLARD
7022439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Reinitialize Rx ring.
7032439e4bfSJean-Christophe PLAGNIOL-VILLARD */
7042439e4bfSJean-Christophe PLAGNIOL-VILLARD init_rx_ring (dev);
7052439e4bfSJean-Christophe PLAGNIOL-VILLARD
7062439e4bfSJean-Christophe PLAGNIOL-VILLARD if (!wait_for_eepro100 (dev)) {
7072439e4bfSJean-Christophe PLAGNIOL-VILLARD printf ("Error: Can not restart ethernet controller.\n");
7082439e4bfSJean-Christophe PLAGNIOL-VILLARD goto Done;
7092439e4bfSJean-Christophe PLAGNIOL-VILLARD }
7102439e4bfSJean-Christophe PLAGNIOL-VILLARD
7112439e4bfSJean-Christophe PLAGNIOL-VILLARD OUTL (dev, phys_to_bus ((u32) & rx_ring[rx_next]), SCBPointer);
7122439e4bfSJean-Christophe PLAGNIOL-VILLARD OUTW (dev, SCB_M | RUC_START, SCBCmd);
7132439e4bfSJean-Christophe PLAGNIOL-VILLARD }
7142439e4bfSJean-Christophe PLAGNIOL-VILLARD
7152439e4bfSJean-Christophe PLAGNIOL-VILLARD Done:
7162439e4bfSJean-Christophe PLAGNIOL-VILLARD return length;
7172439e4bfSJean-Christophe PLAGNIOL-VILLARD }
7182439e4bfSJean-Christophe PLAGNIOL-VILLARD
eepro100_halt(struct eth_device * dev)7192439e4bfSJean-Christophe PLAGNIOL-VILLARD static void eepro100_halt (struct eth_device *dev)
7202439e4bfSJean-Christophe PLAGNIOL-VILLARD {
7212439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Reset the ethernet controller
7222439e4bfSJean-Christophe PLAGNIOL-VILLARD */
7232439e4bfSJean-Christophe PLAGNIOL-VILLARD OUTL (dev, I82559_SELECTIVE_RESET, SCBPort);
7242439e4bfSJean-Christophe PLAGNIOL-VILLARD udelay (20);
7252439e4bfSJean-Christophe PLAGNIOL-VILLARD
7262439e4bfSJean-Christophe PLAGNIOL-VILLARD OUTL (dev, I82559_RESET, SCBPort);
7272439e4bfSJean-Christophe PLAGNIOL-VILLARD udelay (20);
7282439e4bfSJean-Christophe PLAGNIOL-VILLARD
7292439e4bfSJean-Christophe PLAGNIOL-VILLARD if (!wait_for_eepro100 (dev)) {
7302439e4bfSJean-Christophe PLAGNIOL-VILLARD printf ("Error: Can not reset ethernet controller.\n");
7312439e4bfSJean-Christophe PLAGNIOL-VILLARD goto Done;
7322439e4bfSJean-Christophe PLAGNIOL-VILLARD }
7332439e4bfSJean-Christophe PLAGNIOL-VILLARD OUTL (dev, 0, SCBPointer);
7342439e4bfSJean-Christophe PLAGNIOL-VILLARD OUTW (dev, SCB_M | RUC_ADDR_LOAD, SCBCmd);
7352439e4bfSJean-Christophe PLAGNIOL-VILLARD
7362439e4bfSJean-Christophe PLAGNIOL-VILLARD if (!wait_for_eepro100 (dev)) {
7372439e4bfSJean-Christophe PLAGNIOL-VILLARD printf ("Error: Can not reset ethernet controller.\n");
7382439e4bfSJean-Christophe PLAGNIOL-VILLARD goto Done;
7392439e4bfSJean-Christophe PLAGNIOL-VILLARD }
7402439e4bfSJean-Christophe PLAGNIOL-VILLARD OUTL (dev, 0, SCBPointer);
7412439e4bfSJean-Christophe PLAGNIOL-VILLARD OUTW (dev, SCB_M | CU_ADDR_LOAD, SCBCmd);
7422439e4bfSJean-Christophe PLAGNIOL-VILLARD
7432439e4bfSJean-Christophe PLAGNIOL-VILLARD Done:
7442439e4bfSJean-Christophe PLAGNIOL-VILLARD return;
7452439e4bfSJean-Christophe PLAGNIOL-VILLARD }
7462439e4bfSJean-Christophe PLAGNIOL-VILLARD
7472439e4bfSJean-Christophe PLAGNIOL-VILLARD /* SROM Read.
7482439e4bfSJean-Christophe PLAGNIOL-VILLARD */
read_eeprom(struct eth_device * dev,int location,int addr_len)7492439e4bfSJean-Christophe PLAGNIOL-VILLARD static int read_eeprom (struct eth_device *dev, int location, int addr_len)
7502439e4bfSJean-Christophe PLAGNIOL-VILLARD {
7512439e4bfSJean-Christophe PLAGNIOL-VILLARD unsigned short retval = 0;
7522439e4bfSJean-Christophe PLAGNIOL-VILLARD int read_cmd = location | EE_READ_CMD;
7532439e4bfSJean-Christophe PLAGNIOL-VILLARD int i;
7542439e4bfSJean-Christophe PLAGNIOL-VILLARD
7552439e4bfSJean-Christophe PLAGNIOL-VILLARD OUTW (dev, EE_ENB & ~EE_CS, SCBeeprom);
7562439e4bfSJean-Christophe PLAGNIOL-VILLARD OUTW (dev, EE_ENB, SCBeeprom);
7572439e4bfSJean-Christophe PLAGNIOL-VILLARD
7582439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Shift the read command bits out. */
7592439e4bfSJean-Christophe PLAGNIOL-VILLARD for (i = 12; i >= 0; i--) {
7602439e4bfSJean-Christophe PLAGNIOL-VILLARD short dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
7612439e4bfSJean-Christophe PLAGNIOL-VILLARD
7622439e4bfSJean-Christophe PLAGNIOL-VILLARD OUTW (dev, EE_ENB | dataval, SCBeeprom);
7632439e4bfSJean-Christophe PLAGNIOL-VILLARD udelay (1);
7642439e4bfSJean-Christophe PLAGNIOL-VILLARD OUTW (dev, EE_ENB | dataval | EE_SHIFT_CLK, SCBeeprom);
7652439e4bfSJean-Christophe PLAGNIOL-VILLARD udelay (1);
7662439e4bfSJean-Christophe PLAGNIOL-VILLARD }
7672439e4bfSJean-Christophe PLAGNIOL-VILLARD OUTW (dev, EE_ENB, SCBeeprom);
7682439e4bfSJean-Christophe PLAGNIOL-VILLARD
7692439e4bfSJean-Christophe PLAGNIOL-VILLARD for (i = 15; i >= 0; i--) {
7702439e4bfSJean-Christophe PLAGNIOL-VILLARD OUTW (dev, EE_ENB | EE_SHIFT_CLK, SCBeeprom);
7712439e4bfSJean-Christophe PLAGNIOL-VILLARD udelay (1);
7722439e4bfSJean-Christophe PLAGNIOL-VILLARD retval = (retval << 1) |
7732439e4bfSJean-Christophe PLAGNIOL-VILLARD ((INW (dev, SCBeeprom) & EE_DATA_READ) ? 1 : 0);
7742439e4bfSJean-Christophe PLAGNIOL-VILLARD OUTW (dev, EE_ENB, SCBeeprom);
7752439e4bfSJean-Christophe PLAGNIOL-VILLARD udelay (1);
7762439e4bfSJean-Christophe PLAGNIOL-VILLARD }
7772439e4bfSJean-Christophe PLAGNIOL-VILLARD
7782439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Terminate the EEPROM access. */
7792439e4bfSJean-Christophe PLAGNIOL-VILLARD OUTW (dev, EE_ENB & ~EE_CS, SCBeeprom);
7802439e4bfSJean-Christophe PLAGNIOL-VILLARD return retval;
7812439e4bfSJean-Christophe PLAGNIOL-VILLARD }
7822439e4bfSJean-Christophe PLAGNIOL-VILLARD
7832439e4bfSJean-Christophe PLAGNIOL-VILLARD #ifdef CONFIG_EEPRO100_SROM_WRITE
eepro100_write_eeprom(struct eth_device * dev,int location,int addr_len,unsigned short data)7842439e4bfSJean-Christophe PLAGNIOL-VILLARD int eepro100_write_eeprom (struct eth_device* dev, int location, int addr_len, unsigned short data)
7852439e4bfSJean-Christophe PLAGNIOL-VILLARD {
7862439e4bfSJean-Christophe PLAGNIOL-VILLARD unsigned short dataval;
7872439e4bfSJean-Christophe PLAGNIOL-VILLARD int enable_cmd = 0x3f | EE_EWENB_CMD;
7882439e4bfSJean-Christophe PLAGNIOL-VILLARD int write_cmd = location | EE_WRITE_CMD;
7892439e4bfSJean-Christophe PLAGNIOL-VILLARD int i;
7902439e4bfSJean-Christophe PLAGNIOL-VILLARD unsigned long datalong, tmplong;
7912439e4bfSJean-Christophe PLAGNIOL-VILLARD
7922439e4bfSJean-Christophe PLAGNIOL-VILLARD OUTW(dev, EE_ENB & ~EE_CS, SCBeeprom);
7932439e4bfSJean-Christophe PLAGNIOL-VILLARD udelay(1);
7942439e4bfSJean-Christophe PLAGNIOL-VILLARD OUTW(dev, EE_ENB, SCBeeprom);
7952439e4bfSJean-Christophe PLAGNIOL-VILLARD
7962439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Shift the enable command bits out. */
7972439e4bfSJean-Christophe PLAGNIOL-VILLARD for (i = (addr_len+EE_CMD_BITS-1); i >= 0; i--)
7982439e4bfSJean-Christophe PLAGNIOL-VILLARD {
7992439e4bfSJean-Christophe PLAGNIOL-VILLARD dataval = (enable_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
8002439e4bfSJean-Christophe PLAGNIOL-VILLARD OUTW(dev, EE_ENB | dataval, SCBeeprom);
8012439e4bfSJean-Christophe PLAGNIOL-VILLARD udelay(1);
8022439e4bfSJean-Christophe PLAGNIOL-VILLARD OUTW(dev, EE_ENB | dataval | EE_SHIFT_CLK, SCBeeprom);
8032439e4bfSJean-Christophe PLAGNIOL-VILLARD udelay(1);
8042439e4bfSJean-Christophe PLAGNIOL-VILLARD }
8052439e4bfSJean-Christophe PLAGNIOL-VILLARD
8062439e4bfSJean-Christophe PLAGNIOL-VILLARD OUTW(dev, EE_ENB, SCBeeprom);
8072439e4bfSJean-Christophe PLAGNIOL-VILLARD udelay(1);
8082439e4bfSJean-Christophe PLAGNIOL-VILLARD OUTW(dev, EE_ENB & ~EE_CS, SCBeeprom);
8092439e4bfSJean-Christophe PLAGNIOL-VILLARD udelay(1);
8102439e4bfSJean-Christophe PLAGNIOL-VILLARD OUTW(dev, EE_ENB, SCBeeprom);
8112439e4bfSJean-Christophe PLAGNIOL-VILLARD
8122439e4bfSJean-Christophe PLAGNIOL-VILLARD
8132439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Shift the write command bits out. */
8142439e4bfSJean-Christophe PLAGNIOL-VILLARD for (i = (addr_len+EE_CMD_BITS-1); i >= 0; i--)
8152439e4bfSJean-Christophe PLAGNIOL-VILLARD {
8162439e4bfSJean-Christophe PLAGNIOL-VILLARD dataval = (write_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
8172439e4bfSJean-Christophe PLAGNIOL-VILLARD OUTW(dev, EE_ENB | dataval, SCBeeprom);
8182439e4bfSJean-Christophe PLAGNIOL-VILLARD udelay(1);
8192439e4bfSJean-Christophe PLAGNIOL-VILLARD OUTW(dev, EE_ENB | dataval | EE_SHIFT_CLK, SCBeeprom);
8202439e4bfSJean-Christophe PLAGNIOL-VILLARD udelay(1);
8212439e4bfSJean-Christophe PLAGNIOL-VILLARD }
8222439e4bfSJean-Christophe PLAGNIOL-VILLARD
8232439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Write the data */
8242439e4bfSJean-Christophe PLAGNIOL-VILLARD datalong= (unsigned long) ((((data) & 0x00ff) << 8) | ( (data) >> 8));
8252439e4bfSJean-Christophe PLAGNIOL-VILLARD
8262439e4bfSJean-Christophe PLAGNIOL-VILLARD for (i = 0; i< EE_DATA_BITS; i++)
8272439e4bfSJean-Christophe PLAGNIOL-VILLARD {
8282439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Extract and move data bit to bit DI */
8292439e4bfSJean-Christophe PLAGNIOL-VILLARD dataval = ((datalong & 0x8000)>>13) ? EE_DATA_WRITE : 0;
8302439e4bfSJean-Christophe PLAGNIOL-VILLARD
8312439e4bfSJean-Christophe PLAGNIOL-VILLARD OUTW(dev, EE_ENB | dataval, SCBeeprom);
8322439e4bfSJean-Christophe PLAGNIOL-VILLARD udelay(1);
8332439e4bfSJean-Christophe PLAGNIOL-VILLARD OUTW(dev, EE_ENB | dataval | EE_SHIFT_CLK, SCBeeprom);
8342439e4bfSJean-Christophe PLAGNIOL-VILLARD udelay(1);
8352439e4bfSJean-Christophe PLAGNIOL-VILLARD OUTW(dev, EE_ENB | dataval, SCBeeprom);
8362439e4bfSJean-Christophe PLAGNIOL-VILLARD udelay(1);
8372439e4bfSJean-Christophe PLAGNIOL-VILLARD
8382439e4bfSJean-Christophe PLAGNIOL-VILLARD datalong = datalong << 1; /* Adjust significant data bit*/
8392439e4bfSJean-Christophe PLAGNIOL-VILLARD }
8402439e4bfSJean-Christophe PLAGNIOL-VILLARD
8412439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Finish up command (toggle CS) */
8422439e4bfSJean-Christophe PLAGNIOL-VILLARD OUTW(dev, EE_ENB & ~EE_CS, SCBeeprom);
8432439e4bfSJean-Christophe PLAGNIOL-VILLARD udelay(1); /* delay for more than 250 ns */
8442439e4bfSJean-Christophe PLAGNIOL-VILLARD OUTW(dev, EE_ENB, SCBeeprom);
8452439e4bfSJean-Christophe PLAGNIOL-VILLARD
8462439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Wait for programming ready (D0 = 1) */
8472439e4bfSJean-Christophe PLAGNIOL-VILLARD tmplong = 10;
8482439e4bfSJean-Christophe PLAGNIOL-VILLARD do
8492439e4bfSJean-Christophe PLAGNIOL-VILLARD {
8502439e4bfSJean-Christophe PLAGNIOL-VILLARD dataval = INW(dev, SCBeeprom);
8512439e4bfSJean-Christophe PLAGNIOL-VILLARD if (dataval & EE_DATA_READ)
8522439e4bfSJean-Christophe PLAGNIOL-VILLARD break;
8532439e4bfSJean-Christophe PLAGNIOL-VILLARD udelay(10000);
8542439e4bfSJean-Christophe PLAGNIOL-VILLARD }
8552439e4bfSJean-Christophe PLAGNIOL-VILLARD while (-- tmplong);
8562439e4bfSJean-Christophe PLAGNIOL-VILLARD
8572439e4bfSJean-Christophe PLAGNIOL-VILLARD if (tmplong == 0)
8582439e4bfSJean-Christophe PLAGNIOL-VILLARD {
8592439e4bfSJean-Christophe PLAGNIOL-VILLARD printf ("Write i82559 eeprom timed out (100 ms waiting for data ready.\n");
8602439e4bfSJean-Christophe PLAGNIOL-VILLARD return -1;
8612439e4bfSJean-Christophe PLAGNIOL-VILLARD }
8622439e4bfSJean-Christophe PLAGNIOL-VILLARD
8632439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Terminate the EEPROM access. */
8642439e4bfSJean-Christophe PLAGNIOL-VILLARD OUTW(dev, EE_ENB & ~EE_CS, SCBeeprom);
8652439e4bfSJean-Christophe PLAGNIOL-VILLARD
8662439e4bfSJean-Christophe PLAGNIOL-VILLARD return 0;
8672439e4bfSJean-Christophe PLAGNIOL-VILLARD }
8682439e4bfSJean-Christophe PLAGNIOL-VILLARD #endif
8692439e4bfSJean-Christophe PLAGNIOL-VILLARD
init_rx_ring(struct eth_device * dev)8702439e4bfSJean-Christophe PLAGNIOL-VILLARD static void init_rx_ring (struct eth_device *dev)
8712439e4bfSJean-Christophe PLAGNIOL-VILLARD {
8722439e4bfSJean-Christophe PLAGNIOL-VILLARD int i;
8732439e4bfSJean-Christophe PLAGNIOL-VILLARD
8742439e4bfSJean-Christophe PLAGNIOL-VILLARD for (i = 0; i < NUM_RX_DESC; i++) {
8752439e4bfSJean-Christophe PLAGNIOL-VILLARD rx_ring[i].status = 0;
8762439e4bfSJean-Christophe PLAGNIOL-VILLARD rx_ring[i].control =
8772439e4bfSJean-Christophe PLAGNIOL-VILLARD (i == NUM_RX_DESC - 1) ? cpu_to_le16 (RFD_CONTROL_S) : 0;
8782439e4bfSJean-Christophe PLAGNIOL-VILLARD rx_ring[i].link =
8792439e4bfSJean-Christophe PLAGNIOL-VILLARD cpu_to_le32 (phys_to_bus
8802439e4bfSJean-Christophe PLAGNIOL-VILLARD ((u32) & rx_ring[(i + 1) % NUM_RX_DESC]));
8812439e4bfSJean-Christophe PLAGNIOL-VILLARD rx_ring[i].rx_buf_addr = 0xffffffff;
8822439e4bfSJean-Christophe PLAGNIOL-VILLARD rx_ring[i].count = cpu_to_le32 (PKTSIZE_ALIGN << 16);
8832439e4bfSJean-Christophe PLAGNIOL-VILLARD }
8842439e4bfSJean-Christophe PLAGNIOL-VILLARD
8852439e4bfSJean-Christophe PLAGNIOL-VILLARD rx_next = 0;
8862439e4bfSJean-Christophe PLAGNIOL-VILLARD }
8872439e4bfSJean-Christophe PLAGNIOL-VILLARD
purge_tx_ring(struct eth_device * dev)8882439e4bfSJean-Christophe PLAGNIOL-VILLARD static void purge_tx_ring (struct eth_device *dev)
8892439e4bfSJean-Christophe PLAGNIOL-VILLARD {
8902439e4bfSJean-Christophe PLAGNIOL-VILLARD int i;
8912439e4bfSJean-Christophe PLAGNIOL-VILLARD
8922439e4bfSJean-Christophe PLAGNIOL-VILLARD tx_next = 0;
8932439e4bfSJean-Christophe PLAGNIOL-VILLARD tx_threshold = 0x01208000;
8942439e4bfSJean-Christophe PLAGNIOL-VILLARD
8952439e4bfSJean-Christophe PLAGNIOL-VILLARD for (i = 0; i < NUM_TX_DESC; i++) {
8962439e4bfSJean-Christophe PLAGNIOL-VILLARD tx_ring[i].status = 0;
8972439e4bfSJean-Christophe PLAGNIOL-VILLARD tx_ring[i].command = 0;
8982439e4bfSJean-Christophe PLAGNIOL-VILLARD tx_ring[i].link = 0;
8992439e4bfSJean-Christophe PLAGNIOL-VILLARD tx_ring[i].tx_desc_addr = 0;
9002439e4bfSJean-Christophe PLAGNIOL-VILLARD tx_ring[i].count = 0;
9012439e4bfSJean-Christophe PLAGNIOL-VILLARD
9022439e4bfSJean-Christophe PLAGNIOL-VILLARD tx_ring[i].tx_buf_addr0 = 0;
9032439e4bfSJean-Christophe PLAGNIOL-VILLARD tx_ring[i].tx_buf_size0 = 0;
9042439e4bfSJean-Christophe PLAGNIOL-VILLARD tx_ring[i].tx_buf_addr1 = 0;
9052439e4bfSJean-Christophe PLAGNIOL-VILLARD tx_ring[i].tx_buf_size1 = 0;
9062439e4bfSJean-Christophe PLAGNIOL-VILLARD }
9072439e4bfSJean-Christophe PLAGNIOL-VILLARD }
9082439e4bfSJean-Christophe PLAGNIOL-VILLARD
read_hw_addr(struct eth_device * dev,bd_t * bis)9092439e4bfSJean-Christophe PLAGNIOL-VILLARD static void read_hw_addr (struct eth_device *dev, bd_t * bis)
9102439e4bfSJean-Christophe PLAGNIOL-VILLARD {
9112439e4bfSJean-Christophe PLAGNIOL-VILLARD u16 sum = 0;
9122439e4bfSJean-Christophe PLAGNIOL-VILLARD int i, j;
9132439e4bfSJean-Christophe PLAGNIOL-VILLARD int addr_len = read_eeprom (dev, 0, 6) == 0xffff ? 8 : 6;
9142439e4bfSJean-Christophe PLAGNIOL-VILLARD
9152439e4bfSJean-Christophe PLAGNIOL-VILLARD for (j = 0, i = 0; i < 0x40; i++) {
9162439e4bfSJean-Christophe PLAGNIOL-VILLARD u16 value = read_eeprom (dev, i, addr_len);
9172439e4bfSJean-Christophe PLAGNIOL-VILLARD
9182439e4bfSJean-Christophe PLAGNIOL-VILLARD sum += value;
9192439e4bfSJean-Christophe PLAGNIOL-VILLARD if (i < 3) {
9202439e4bfSJean-Christophe PLAGNIOL-VILLARD dev->enetaddr[j++] = value;
9212439e4bfSJean-Christophe PLAGNIOL-VILLARD dev->enetaddr[j++] = value >> 8;
9222439e4bfSJean-Christophe PLAGNIOL-VILLARD }
9232439e4bfSJean-Christophe PLAGNIOL-VILLARD }
9242439e4bfSJean-Christophe PLAGNIOL-VILLARD
9252439e4bfSJean-Christophe PLAGNIOL-VILLARD if (sum != 0xBABA) {
9262439e4bfSJean-Christophe PLAGNIOL-VILLARD memset (dev->enetaddr, 0, ETH_ALEN);
9272439e4bfSJean-Christophe PLAGNIOL-VILLARD #ifdef DEBUG
9282439e4bfSJean-Christophe PLAGNIOL-VILLARD printf ("%s: Invalid EEPROM checksum %#4.4x, "
9292439e4bfSJean-Christophe PLAGNIOL-VILLARD "check settings before activating this device!\n",
9302439e4bfSJean-Christophe PLAGNIOL-VILLARD dev->name, sum);
9312439e4bfSJean-Christophe PLAGNIOL-VILLARD #endif
9322439e4bfSJean-Christophe PLAGNIOL-VILLARD }
9332439e4bfSJean-Christophe PLAGNIOL-VILLARD }
934