1 /******************************************************************************* 2 3 4 Copyright(c) 1999 - 2002 Intel Corporation. All rights reserved. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms of the GNU General Public License as published by the Free 8 Software Foundation; either version 2 of the License, or (at your option) 9 any later version. 10 11 This program is distributed in the hope that it will be useful, but WITHOUT 12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 more details. 15 16 You should have received a copy of the GNU General Public License along with 17 this program; if not, write to the Free Software Foundation, Inc., 59 18 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 19 20 The full GNU General Public License is included in this distribution in the 21 file called LICENSE. 22 23 Contact Information: 24 Linux NICS <linux.nics@intel.com> 25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 26 27 *******************************************************************************/ 28 29 /* e1000_hw.h 30 * Structures, enums, and macros for the MAC 31 */ 32 33 #ifndef _E1000_HW_H_ 34 #define _E1000_HW_H_ 35 36 #include <common.h> 37 #include <malloc.h> 38 #include <net.h> 39 #include <asm/io.h> 40 #include <pci.h> 41 42 #define E1000_ERR(args...) printf("e1000: " args) 43 44 #ifdef E1000_DEBUG 45 #define E1000_DBG(args...) printf("e1000: " args) 46 #define DEBUGOUT(fmt,args...) printf(fmt ,##args) 47 #define DEBUGFUNC() printf("%s\n", __FUNCTION__); 48 #else 49 #define E1000_DBG(args...) 50 #define DEBUGFUNC() 51 #define DEBUGOUT(fmt,args...) 52 #endif 53 54 /* Forward declarations of structures used by the shared code */ 55 struct e1000_hw; 56 struct e1000_hw_stats; 57 58 typedef enum { 59 FALSE = 0, 60 TRUE = 1 61 } boolean_t; 62 63 /* Enumerated types specific to the e1000 hardware */ 64 /* Media Access Controlers */ 65 typedef enum { 66 e1000_undefined = 0, 67 e1000_82542_rev2_0, 68 e1000_82542_rev2_1, 69 e1000_82543, 70 e1000_82544, 71 e1000_82540, 72 e1000_82545, 73 e1000_82546, 74 e1000_82541, 75 e1000_82541_rev_2, 76 e1000_num_macs 77 } e1000_mac_type; 78 79 /* Media Types */ 80 typedef enum { 81 e1000_media_type_copper = 0, 82 e1000_media_type_fiber = 1, 83 e1000_num_media_types 84 } e1000_media_type; 85 86 typedef enum { 87 e1000_10_half = 0, 88 e1000_10_full = 1, 89 e1000_100_half = 2, 90 e1000_100_full = 3 91 } e1000_speed_duplex_type; 92 93 typedef enum { 94 e1000_lan_a = 0, 95 e1000_lan_b = 1 96 } e1000_lan_loc; 97 98 /* Flow Control Settings */ 99 typedef enum { 100 e1000_fc_none = 0, 101 e1000_fc_rx_pause = 1, 102 e1000_fc_tx_pause = 2, 103 e1000_fc_full = 3, 104 e1000_fc_default = 0xFF 105 } e1000_fc_type; 106 107 /* PCI bus types */ 108 typedef enum { 109 e1000_bus_type_unknown = 0, 110 e1000_bus_type_pci, 111 e1000_bus_type_pcix 112 } e1000_bus_type; 113 114 /* PCI bus speeds */ 115 typedef enum { 116 e1000_bus_speed_unknown = 0, 117 e1000_bus_speed_33, 118 e1000_bus_speed_66, 119 e1000_bus_speed_100, 120 e1000_bus_speed_133, 121 e1000_bus_speed_reserved 122 } e1000_bus_speed; 123 124 /* PCI bus widths */ 125 typedef enum { 126 e1000_bus_width_unknown = 0, 127 e1000_bus_width_32, 128 e1000_bus_width_64 129 } e1000_bus_width; 130 131 /* PHY status info structure and supporting enums */ 132 typedef enum { 133 e1000_cable_length_50 = 0, 134 e1000_cable_length_50_80, 135 e1000_cable_length_80_110, 136 e1000_cable_length_110_140, 137 e1000_cable_length_140, 138 e1000_cable_length_undefined = 0xFF 139 } e1000_cable_length; 140 141 typedef enum { 142 e1000_10bt_ext_dist_enable_normal = 0, 143 e1000_10bt_ext_dist_enable_lower, 144 e1000_10bt_ext_dist_enable_undefined = 0xFF 145 } e1000_10bt_ext_dist_enable; 146 147 typedef enum { 148 e1000_rev_polarity_normal = 0, 149 e1000_rev_polarity_reversed, 150 e1000_rev_polarity_undefined = 0xFF 151 } e1000_rev_polarity; 152 153 typedef enum { 154 e1000_polarity_reversal_enabled = 0, 155 e1000_polarity_reversal_disabled, 156 e1000_polarity_reversal_undefined = 0xFF 157 } e1000_polarity_reversal; 158 159 typedef enum { 160 e1000_auto_x_mode_manual_mdi = 0, 161 e1000_auto_x_mode_manual_mdix, 162 e1000_auto_x_mode_auto1, 163 e1000_auto_x_mode_auto2, 164 e1000_auto_x_mode_undefined = 0xFF 165 } e1000_auto_x_mode; 166 167 typedef enum { 168 e1000_1000t_rx_status_not_ok = 0, 169 e1000_1000t_rx_status_ok, 170 e1000_1000t_rx_status_undefined = 0xFF 171 } e1000_1000t_rx_status; 172 173 typedef enum { 174 e1000_phy_m88 = 0, 175 e1000_phy_igp, 176 e1000_phy_igp_2, 177 e1000_phy_undefined = 0xFF 178 } e1000_phy_type; 179 180 struct e1000_phy_info { 181 e1000_cable_length cable_length; 182 e1000_10bt_ext_dist_enable extended_10bt_distance; 183 e1000_rev_polarity cable_polarity; 184 e1000_polarity_reversal polarity_correction; 185 e1000_auto_x_mode mdix_mode; 186 e1000_1000t_rx_status local_rx; 187 e1000_1000t_rx_status remote_rx; 188 }; 189 190 struct e1000_phy_stats { 191 uint32_t idle_errors; 192 uint32_t receive_errors; 193 }; 194 195 /* Error Codes */ 196 #define E1000_SUCCESS 0 197 #define E1000_ERR_EEPROM 1 198 #define E1000_ERR_PHY 2 199 #define E1000_ERR_CONFIG 3 200 #define E1000_ERR_PARAM 4 201 #define E1000_ERR_MAC_TYPE 5 202 #define E1000_ERR_PHY_TYPE 6 203 #define E1000_ERR_NOLINK 7 204 #define E1000_ERR_TIMEOUT 8 205 #define E1000_ERR_RESET 9 206 #define E1000_ERR_MASTER_REQUESTS_PENDING 10 207 #define E1000_ERR_HOST_INTERFACE_COMMAND 11 208 #define E1000_BLK_PHY_RESET 12 209 210 /* PCI Device IDs */ 211 #define E1000_DEV_ID_82542 0x1000 212 #define E1000_DEV_ID_82543GC_FIBER 0x1001 213 #define E1000_DEV_ID_82543GC_COPPER 0x1004 214 #define E1000_DEV_ID_82544EI_COPPER 0x1008 215 #define E1000_DEV_ID_82544EI_FIBER 0x1009 216 #define E1000_DEV_ID_82544GC_COPPER 0x100C 217 #define E1000_DEV_ID_82544GC_LOM 0x100D 218 #define E1000_DEV_ID_82540EM 0x100E 219 #define E1000_DEV_ID_82540EM_LOM 0x1015 220 #define E1000_DEV_ID_82545GM_COPPER 0x1026 221 #define E1000_DEV_ID_82545EM_COPPER 0x100F 222 #define E1000_DEV_ID_82545EM_FIBER 0x1011 223 #define E1000_DEV_ID_82546EB_COPPER 0x1010 224 #define E1000_DEV_ID_82546EB_FIBER 0x1012 225 #define E1000_DEV_ID_82541ER 0x1078 226 #define E1000_DEV_ID_82541GI_LF 0x107C 227 #define NUM_DEV_IDS 16 228 229 #define NODE_ADDRESS_SIZE 6 230 #define ETH_LENGTH_OF_ADDRESS 6 231 232 /* MAC decode size is 128K - This is the size of BAR0 */ 233 #define MAC_DECODE_SIZE (128 * 1024) 234 235 #define E1000_82542_2_0_REV_ID 2 236 #define E1000_82542_2_1_REV_ID 3 237 238 #define SPEED_10 10 239 #define SPEED_100 100 240 #define SPEED_1000 1000 241 #define HALF_DUPLEX 1 242 #define FULL_DUPLEX 2 243 244 /* The sizes (in bytes) of a ethernet packet */ 245 #define ENET_HEADER_SIZE 14 246 #define MAXIMUM_ETHERNET_FRAME_SIZE 1518 /* With FCS */ 247 #define MINIMUM_ETHERNET_FRAME_SIZE 64 /* With FCS */ 248 #define ETHERNET_FCS_SIZE 4 249 #define MAXIMUM_ETHERNET_PACKET_SIZE \ 250 (MAXIMUM_ETHERNET_FRAME_SIZE - ETHERNET_FCS_SIZE) 251 #define MINIMUM_ETHERNET_PACKET_SIZE \ 252 (MINIMUM_ETHERNET_FRAME_SIZE - ETHERNET_FCS_SIZE) 253 #define CRC_LENGTH ETHERNET_FCS_SIZE 254 #define MAX_JUMBO_FRAME_SIZE 0x3F00 255 256 /* 802.1q VLAN Packet Sizes */ 257 #define VLAN_TAG_SIZE 4 /* 802.3ac tag (not DMAed) */ 258 259 /* Ethertype field values */ 260 #define ETHERNET_IEEE_VLAN_TYPE 0x8100 /* 802.3ac packet */ 261 #define ETHERNET_IP_TYPE 0x0800 /* IP packets */ 262 #define ETHERNET_ARP_TYPE 0x0806 /* Address Resolution Protocol (ARP) */ 263 264 /* Packet Header defines */ 265 #define IP_PROTOCOL_TCP 6 266 #define IP_PROTOCOL_UDP 0x11 267 268 /* This defines the bits that are set in the Interrupt Mask 269 * Set/Read Register. Each bit is documented below: 270 * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0) 271 * o RXSEQ = Receive Sequence Error 272 */ 273 #define POLL_IMS_ENABLE_MASK ( \ 274 E1000_IMS_RXDMT0 | \ 275 E1000_IMS_RXSEQ) 276 277 /* This defines the bits that are set in the Interrupt Mask 278 * Set/Read Register. Each bit is documented below: 279 * o RXT0 = Receiver Timer Interrupt (ring 0) 280 * o TXDW = Transmit Descriptor Written Back 281 * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0) 282 * o RXSEQ = Receive Sequence Error 283 * o LSC = Link Status Change 284 */ 285 #define IMS_ENABLE_MASK ( \ 286 E1000_IMS_RXT0 | \ 287 E1000_IMS_TXDW | \ 288 E1000_IMS_RXDMT0 | \ 289 E1000_IMS_RXSEQ | \ 290 E1000_IMS_LSC) 291 292 /* The number of high/low register pairs in the RAR. The RAR (Receive Address 293 * Registers) holds the directed and multicast addresses that we monitor. We 294 * reserve one of these spots for our directed address, allowing us room for 295 * E1000_RAR_ENTRIES - 1 multicast addresses. 296 */ 297 #define E1000_RAR_ENTRIES 16 298 299 #define MIN_NUMBER_OF_DESCRIPTORS 8 300 #define MAX_NUMBER_OF_DESCRIPTORS 0xFFF8 301 302 /* Receive Descriptor */ 303 struct e1000_rx_desc { 304 uint64_t buffer_addr; /* Address of the descriptor's data buffer */ 305 uint16_t length; /* Length of data DMAed into data buffer */ 306 uint16_t csum; /* Packet checksum */ 307 uint8_t status; /* Descriptor status */ 308 uint8_t errors; /* Descriptor Errors */ 309 uint16_t special; 310 }; 311 312 /* Receive Decriptor bit definitions */ 313 #define E1000_RXD_STAT_DD 0x01 /* Descriptor Done */ 314 #define E1000_RXD_STAT_EOP 0x02 /* End of Packet */ 315 #define E1000_RXD_STAT_IXSM 0x04 /* Ignore checksum */ 316 #define E1000_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */ 317 #define E1000_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */ 318 #define E1000_RXD_STAT_IPCS 0x40 /* IP xsum calculated */ 319 #define E1000_RXD_STAT_PIF 0x80 /* passed in-exact filter */ 320 #define E1000_RXD_ERR_CE 0x01 /* CRC Error */ 321 #define E1000_RXD_ERR_SE 0x02 /* Symbol Error */ 322 #define E1000_RXD_ERR_SEQ 0x04 /* Sequence Error */ 323 #define E1000_RXD_ERR_CXE 0x10 /* Carrier Extension Error */ 324 #define E1000_RXD_ERR_TCPE 0x20 /* TCP/UDP Checksum Error */ 325 #define E1000_RXD_ERR_IPE 0x40 /* IP Checksum Error */ 326 #define E1000_RXD_ERR_RXE 0x80 /* Rx Data Error */ 327 #define E1000_RXD_SPC_VLAN_MASK 0x0FFF /* VLAN ID is in lower 12 bits */ 328 #define E1000_RXD_SPC_PRI_MASK 0xE000 /* Priority is in upper 3 bits */ 329 #define E1000_RXD_SPC_PRI_SHIFT 0x000D /* Priority is in upper 3 of 16 */ 330 #define E1000_RXD_SPC_CFI_MASK 0x1000 /* CFI is bit 12 */ 331 #define E1000_RXD_SPC_CFI_SHIFT 0x000C /* CFI is bit 12 */ 332 333 /* mask to determine if packets should be dropped due to frame errors */ 334 #define E1000_RXD_ERR_FRAME_ERR_MASK ( \ 335 E1000_RXD_ERR_CE | \ 336 E1000_RXD_ERR_SE | \ 337 E1000_RXD_ERR_SEQ | \ 338 E1000_RXD_ERR_CXE | \ 339 E1000_RXD_ERR_RXE) 340 341 /* Transmit Descriptor */ 342 struct e1000_tx_desc { 343 uint64_t buffer_addr; /* Address of the descriptor's data buffer */ 344 union { 345 uint32_t data; 346 struct { 347 uint16_t length; /* Data buffer length */ 348 uint8_t cso; /* Checksum offset */ 349 uint8_t cmd; /* Descriptor control */ 350 } flags; 351 } lower; 352 union { 353 uint32_t data; 354 struct { 355 uint8_t status; /* Descriptor status */ 356 uint8_t css; /* Checksum start */ 357 uint16_t special; 358 } fields; 359 } upper; 360 }; 361 362 /* Transmit Descriptor bit definitions */ 363 #define E1000_TXD_DTYP_D 0x00100000 /* Data Descriptor */ 364 #define E1000_TXD_DTYP_C 0x00000000 /* Context Descriptor */ 365 #define E1000_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */ 366 #define E1000_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */ 367 #define E1000_TXD_CMD_EOP 0x01000000 /* End of Packet */ 368 #define E1000_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */ 369 #define E1000_TXD_CMD_IC 0x04000000 /* Insert Checksum */ 370 #define E1000_TXD_CMD_RS 0x08000000 /* Report Status */ 371 #define E1000_TXD_CMD_RPS 0x10000000 /* Report Packet Sent */ 372 #define E1000_TXD_CMD_DEXT 0x20000000 /* Descriptor extension (0 = legacy) */ 373 #define E1000_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */ 374 #define E1000_TXD_CMD_IDE 0x80000000 /* Enable Tidv register */ 375 #define E1000_TXD_STAT_DD 0x00000001 /* Descriptor Done */ 376 #define E1000_TXD_STAT_EC 0x00000002 /* Excess Collisions */ 377 #define E1000_TXD_STAT_LC 0x00000004 /* Late Collisions */ 378 #define E1000_TXD_STAT_TU 0x00000008 /* Transmit underrun */ 379 #define E1000_TXD_CMD_TCP 0x01000000 /* TCP packet */ 380 #define E1000_TXD_CMD_IP 0x02000000 /* IP packet */ 381 #define E1000_TXD_CMD_TSE 0x04000000 /* TCP Seg enable */ 382 #define E1000_TXD_STAT_TC 0x00000004 /* Tx Underrun */ 383 384 /* Offload Context Descriptor */ 385 struct e1000_context_desc { 386 union { 387 uint32_t ip_config; 388 struct { 389 uint8_t ipcss; /* IP checksum start */ 390 uint8_t ipcso; /* IP checksum offset */ 391 uint16_t ipcse; /* IP checksum end */ 392 } ip_fields; 393 } lower_setup; 394 union { 395 uint32_t tcp_config; 396 struct { 397 uint8_t tucss; /* TCP checksum start */ 398 uint8_t tucso; /* TCP checksum offset */ 399 uint16_t tucse; /* TCP checksum end */ 400 } tcp_fields; 401 } upper_setup; 402 uint32_t cmd_and_length; /* */ 403 union { 404 uint32_t data; 405 struct { 406 uint8_t status; /* Descriptor status */ 407 uint8_t hdr_len; /* Header length */ 408 uint16_t mss; /* Maximum segment size */ 409 } fields; 410 } tcp_seg_setup; 411 }; 412 413 /* Offload data descriptor */ 414 struct e1000_data_desc { 415 uint64_t buffer_addr; /* Address of the descriptor's buffer address */ 416 union { 417 uint32_t data; 418 struct { 419 uint16_t length; /* Data buffer length */ 420 uint8_t typ_len_ext; /* */ 421 uint8_t cmd; /* */ 422 } flags; 423 } lower; 424 union { 425 uint32_t data; 426 struct { 427 uint8_t status; /* Descriptor status */ 428 uint8_t popts; /* Packet Options */ 429 uint16_t special; /* */ 430 } fields; 431 } upper; 432 }; 433 434 /* Filters */ 435 #define E1000_NUM_UNICAST 16 /* Unicast filter entries */ 436 #define E1000_MC_TBL_SIZE 128 /* Multicast Filter Table (4096 bits) */ 437 #define E1000_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) */ 438 439 /* Receive Address Register */ 440 struct e1000_rar { 441 volatile uint32_t low; /* receive address low */ 442 volatile uint32_t high; /* receive address high */ 443 }; 444 445 /* The number of entries in the Multicast Table Array (MTA). */ 446 #define E1000_NUM_MTA_REGISTERS 128 447 448 /* IPv4 Address Table Entry */ 449 struct e1000_ipv4_at_entry { 450 volatile uint32_t ipv4_addr; /* IP Address (RW) */ 451 volatile uint32_t reserved; 452 }; 453 454 /* Four wakeup IP addresses are supported */ 455 #define E1000_WAKEUP_IP_ADDRESS_COUNT_MAX 4 456 #define E1000_IP4AT_SIZE E1000_WAKEUP_IP_ADDRESS_COUNT_MAX 457 #define E1000_IP6AT_SIZE 1 458 459 /* IPv6 Address Table Entry */ 460 struct e1000_ipv6_at_entry { 461 volatile uint8_t ipv6_addr[16]; 462 }; 463 464 /* Flexible Filter Length Table Entry */ 465 struct e1000_fflt_entry { 466 volatile uint32_t length; /* Flexible Filter Length (RW) */ 467 volatile uint32_t reserved; 468 }; 469 470 /* Flexible Filter Mask Table Entry */ 471 struct e1000_ffmt_entry { 472 volatile uint32_t mask; /* Flexible Filter Mask (RW) */ 473 volatile uint32_t reserved; 474 }; 475 476 /* Flexible Filter Value Table Entry */ 477 struct e1000_ffvt_entry { 478 volatile uint32_t value; /* Flexible Filter Value (RW) */ 479 volatile uint32_t reserved; 480 }; 481 482 /* Four Flexible Filters are supported */ 483 #define E1000_FLEXIBLE_FILTER_COUNT_MAX 4 484 485 /* Each Flexible Filter is at most 128 (0x80) bytes in length */ 486 #define E1000_FLEXIBLE_FILTER_SIZE_MAX 128 487 488 #define E1000_FFLT_SIZE E1000_FLEXIBLE_FILTER_COUNT_MAX 489 #define E1000_FFMT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX 490 #define E1000_FFVT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX 491 492 /* Register Set. (82543, 82544) 493 * 494 * Registers are defined to be 32 bits and should be accessed as 32 bit values. 495 * These registers are physically located on the NIC, but are mapped into the 496 * host memory address space. 497 * 498 * RW - register is both readable and writable 499 * RO - register is read only 500 * WO - register is write only 501 * R/clr - register is read only and is cleared when read 502 * A - register array 503 */ 504 #define E1000_CTRL 0x00000 /* Device Control - RW */ 505 #define E1000_STATUS 0x00008 /* Device Status - RO */ 506 #define E1000_EECD 0x00010 /* EEPROM/Flash Control - RW */ 507 #define E1000_EERD 0x00014 /* EEPROM Read - RW */ 508 #define E1000_CTRL_EXT 0x00018 /* Extended Device Control - RW */ 509 #define E1000_MDIC 0x00020 /* MDI Control - RW */ 510 #define E1000_FCAL 0x00028 /* Flow Control Address Low - RW */ 511 #define E1000_FCAH 0x0002C /* Flow Control Address High -RW */ 512 #define E1000_FCT 0x00030 /* Flow Control Type - RW */ 513 #define E1000_VET 0x00038 /* VLAN Ether Type - RW */ 514 #define E1000_ICR 0x000C0 /* Interrupt Cause Read - R/clr */ 515 #define E1000_ITR 0x000C4 /* Interrupt Throttling Rate - RW */ 516 #define E1000_ICS 0x000C8 /* Interrupt Cause Set - WO */ 517 #define E1000_IMS 0x000D0 /* Interrupt Mask Set - RW */ 518 #define E1000_IMC 0x000D8 /* Interrupt Mask Clear - WO */ 519 #define E1000_RCTL 0x00100 /* RX Control - RW */ 520 #define E1000_FCTTV 0x00170 /* Flow Control Transmit Timer Value - RW */ 521 #define E1000_TXCW 0x00178 /* TX Configuration Word - RW */ 522 #define E1000_RXCW 0x00180 /* RX Configuration Word - RO */ 523 #define E1000_TCTL 0x00400 /* TX Control - RW */ 524 #define E1000_TIPG 0x00410 /* TX Inter-packet gap -RW */ 525 #define E1000_TBT 0x00448 /* TX Burst Timer - RW */ 526 #define E1000_AIT 0x00458 /* Adaptive Interframe Spacing Throttle - RW */ 527 #define E1000_LEDCTL 0x00E00 /* LED Control - RW */ 528 #define E1000_PBA 0x01000 /* Packet Buffer Allocation - RW */ 529 #define E1000_FCRTL 0x02160 /* Flow Control Receive Threshold Low - RW */ 530 #define E1000_FCRTH 0x02168 /* Flow Control Receive Threshold High - RW */ 531 #define E1000_RDBAL 0x02800 /* RX Descriptor Base Address Low - RW */ 532 #define E1000_RDBAH 0x02804 /* RX Descriptor Base Address High - RW */ 533 #define E1000_RDLEN 0x02808 /* RX Descriptor Length - RW */ 534 #define E1000_RDH 0x02810 /* RX Descriptor Head - RW */ 535 #define E1000_RDT 0x02818 /* RX Descriptor Tail - RW */ 536 #define E1000_RDTR 0x02820 /* RX Delay Timer - RW */ 537 #define E1000_RXDCTL 0x02828 /* RX Descriptor Control - RW */ 538 #define E1000_RADV 0x0282C /* RX Interrupt Absolute Delay Timer - RW */ 539 #define E1000_RSRPD 0x02C00 /* RX Small Packet Detect - RW */ 540 #define E1000_TXDMAC 0x03000 /* TX DMA Control - RW */ 541 #define E1000_TDBAL 0x03800 /* TX Descriptor Base Address Low - RW */ 542 #define E1000_TDBAH 0x03804 /* TX Descriptor Base Address High - RW */ 543 #define E1000_TDLEN 0x03808 /* TX Descriptor Length - RW */ 544 #define E1000_TDH 0x03810 /* TX Descriptor Head - RW */ 545 #define E1000_TDT 0x03818 /* TX Descripotr Tail - RW */ 546 #define E1000_TIDV 0x03820 /* TX Interrupt Delay Value - RW */ 547 #define E1000_TXDCTL 0x03828 /* TX Descriptor Control - RW */ 548 #define E1000_TADV 0x0382C /* TX Interrupt Absolute Delay Val - RW */ 549 #define E1000_TSPMT 0x03830 /* TCP Segmentation PAD & Min Threshold - RW */ 550 #define E1000_CRCERRS 0x04000 /* CRC Error Count - R/clr */ 551 #define E1000_ALGNERRC 0x04004 /* Alignment Error Count - R/clr */ 552 #define E1000_SYMERRS 0x04008 /* Symbol Error Count - R/clr */ 553 #define E1000_RXERRC 0x0400C /* Receive Error Count - R/clr */ 554 #define E1000_MPC 0x04010 /* Missed Packet Count - R/clr */ 555 #define E1000_SCC 0x04014 /* Single Collision Count - R/clr */ 556 #define E1000_ECOL 0x04018 /* Excessive Collision Count - R/clr */ 557 #define E1000_MCC 0x0401C /* Multiple Collision Count - R/clr */ 558 #define E1000_LATECOL 0x04020 /* Late Collision Count - R/clr */ 559 #define E1000_COLC 0x04028 /* Collision Count - R/clr */ 560 #define E1000_DC 0x04030 /* Defer Count - R/clr */ 561 #define E1000_TNCRS 0x04034 /* TX-No CRS - R/clr */ 562 #define E1000_SEC 0x04038 /* Sequence Error Count - R/clr */ 563 #define E1000_CEXTERR 0x0403C /* Carrier Extension Error Count - R/clr */ 564 #define E1000_RLEC 0x04040 /* Receive Length Error Count - R/clr */ 565 #define E1000_XONRXC 0x04048 /* XON RX Count - R/clr */ 566 #define E1000_XONTXC 0x0404C /* XON TX Count - R/clr */ 567 #define E1000_XOFFRXC 0x04050 /* XOFF RX Count - R/clr */ 568 #define E1000_XOFFTXC 0x04054 /* XOFF TX Count - R/clr */ 569 #define E1000_FCRUC 0x04058 /* Flow Control RX Unsupported Count- R/clr */ 570 #define E1000_PRC64 0x0405C /* Packets RX (64 bytes) - R/clr */ 571 #define E1000_PRC127 0x04060 /* Packets RX (65-127 bytes) - R/clr */ 572 #define E1000_PRC255 0x04064 /* Packets RX (128-255 bytes) - R/clr */ 573 #define E1000_PRC511 0x04068 /* Packets RX (255-511 bytes) - R/clr */ 574 #define E1000_PRC1023 0x0406C /* Packets RX (512-1023 bytes) - R/clr */ 575 #define E1000_PRC1522 0x04070 /* Packets RX (1024-1522 bytes) - R/clr */ 576 #define E1000_GPRC 0x04074 /* Good Packets RX Count - R/clr */ 577 #define E1000_BPRC 0x04078 /* Broadcast Packets RX Count - R/clr */ 578 #define E1000_MPRC 0x0407C /* Multicast Packets RX Count - R/clr */ 579 #define E1000_GPTC 0x04080 /* Good Packets TX Count - R/clr */ 580 #define E1000_GORCL 0x04088 /* Good Octets RX Count Low - R/clr */ 581 #define E1000_GORCH 0x0408C /* Good Octets RX Count High - R/clr */ 582 #define E1000_GOTCL 0x04090 /* Good Octets TX Count Low - R/clr */ 583 #define E1000_GOTCH 0x04094 /* Good Octets TX Count High - R/clr */ 584 #define E1000_RNBC 0x040A0 /* RX No Buffers Count - R/clr */ 585 #define E1000_RUC 0x040A4 /* RX Undersize Count - R/clr */ 586 #define E1000_RFC 0x040A8 /* RX Fragment Count - R/clr */ 587 #define E1000_ROC 0x040AC /* RX Oversize Count - R/clr */ 588 #define E1000_RJC 0x040B0 /* RX Jabber Count - R/clr */ 589 #define E1000_MGTPRC 0x040B4 /* Management Packets RX Count - R/clr */ 590 #define E1000_MGTPDC 0x040B8 /* Management Packets Dropped Count - R/clr */ 591 #define E1000_MGTPTC 0x040BC /* Management Packets TX Count - R/clr */ 592 #define E1000_TORL 0x040C0 /* Total Octets RX Low - R/clr */ 593 #define E1000_TORH 0x040C4 /* Total Octets RX High - R/clr */ 594 #define E1000_TOTL 0x040C8 /* Total Octets TX Low - R/clr */ 595 #define E1000_TOTH 0x040CC /* Total Octets TX High - R/clr */ 596 #define E1000_TPR 0x040D0 /* Total Packets RX - R/clr */ 597 #define E1000_TPT 0x040D4 /* Total Packets TX - R/clr */ 598 #define E1000_PTC64 0x040D8 /* Packets TX (64 bytes) - R/clr */ 599 #define E1000_PTC127 0x040DC /* Packets TX (65-127 bytes) - R/clr */ 600 #define E1000_PTC255 0x040E0 /* Packets TX (128-255 bytes) - R/clr */ 601 #define E1000_PTC511 0x040E4 /* Packets TX (256-511 bytes) - R/clr */ 602 #define E1000_PTC1023 0x040E8 /* Packets TX (512-1023 bytes) - R/clr */ 603 #define E1000_PTC1522 0x040EC /* Packets TX (1024-1522 Bytes) - R/clr */ 604 #define E1000_MPTC 0x040F0 /* Multicast Packets TX Count - R/clr */ 605 #define E1000_BPTC 0x040F4 /* Broadcast Packets TX Count - R/clr */ 606 #define E1000_TSCTC 0x040F8 /* TCP Segmentation Context TX - R/clr */ 607 #define E1000_TSCTFC 0x040FC /* TCP Segmentation Context TX Fail - R/clr */ 608 #define E1000_RXCSUM 0x05000 /* RX Checksum Control - RW */ 609 #define E1000_MTA 0x05200 /* Multicast Table Array - RW Array */ 610 #define E1000_RA 0x05400 /* Receive Address - RW Array */ 611 #define E1000_VFTA 0x05600 /* VLAN Filter Table Array - RW Array */ 612 #define E1000_WUC 0x05800 /* Wakeup Control - RW */ 613 #define E1000_WUFC 0x05808 /* Wakeup Filter Control - RW */ 614 #define E1000_WUS 0x05810 /* Wakeup Status - RO */ 615 #define E1000_MANC 0x05820 /* Management Control - RW */ 616 #define E1000_IPAV 0x05838 /* IP Address Valid - RW */ 617 #define E1000_IP4AT 0x05840 /* IPv4 Address Table - RW Array */ 618 #define E1000_IP6AT 0x05880 /* IPv6 Address Table - RW Array */ 619 #define E1000_WUPL 0x05900 /* Wakeup Packet Length - RW */ 620 #define E1000_WUPM 0x05A00 /* Wakeup Packet Memory - RO A */ 621 #define E1000_FFLT 0x05F00 /* Flexible Filter Length Table - RW Array */ 622 #define E1000_FFMT 0x09000 /* Flexible Filter Mask Table - RW Array */ 623 #define E1000_FFVT 0x09800 /* Flexible Filter Value Table - RW Array */ 624 625 /* Register Set (82542) 626 * 627 * Some of the 82542 registers are located at different offsets than they are 628 * in more current versions of the 8254x. Despite the difference in location, 629 * the registers function in the same manner. 630 */ 631 #define E1000_82542_CTRL E1000_CTRL 632 #define E1000_82542_STATUS E1000_STATUS 633 #define E1000_82542_EECD E1000_EECD 634 #define E1000_82542_EERD E1000_EERD 635 #define E1000_82542_CTRL_EXT E1000_CTRL_EXT 636 #define E1000_82542_MDIC E1000_MDIC 637 #define E1000_82542_FCAL E1000_FCAL 638 #define E1000_82542_FCAH E1000_FCAH 639 #define E1000_82542_FCT E1000_FCT 640 #define E1000_82542_VET E1000_VET 641 #define E1000_82542_RA 0x00040 642 #define E1000_82542_ICR E1000_ICR 643 #define E1000_82542_ITR E1000_ITR 644 #define E1000_82542_ICS E1000_ICS 645 #define E1000_82542_IMS E1000_IMS 646 #define E1000_82542_IMC E1000_IMC 647 #define E1000_82542_RCTL E1000_RCTL 648 #define E1000_82542_RDTR 0x00108 649 #define E1000_82542_RDBAL 0x00110 650 #define E1000_82542_RDBAH 0x00114 651 #define E1000_82542_RDLEN 0x00118 652 #define E1000_82542_RDH 0x00120 653 #define E1000_82542_RDT 0x00128 654 #define E1000_82542_FCRTH 0x00160 655 #define E1000_82542_FCRTL 0x00168 656 #define E1000_82542_FCTTV E1000_FCTTV 657 #define E1000_82542_TXCW E1000_TXCW 658 #define E1000_82542_RXCW E1000_RXCW 659 #define E1000_82542_MTA 0x00200 660 #define E1000_82542_TCTL E1000_TCTL 661 #define E1000_82542_TIPG E1000_TIPG 662 #define E1000_82542_TDBAL 0x00420 663 #define E1000_82542_TDBAH 0x00424 664 #define E1000_82542_TDLEN 0x00428 665 #define E1000_82542_TDH 0x00430 666 #define E1000_82542_TDT 0x00438 667 #define E1000_82542_TIDV 0x00440 668 #define E1000_82542_TBT E1000_TBT 669 #define E1000_82542_AIT E1000_AIT 670 #define E1000_82542_VFTA 0x00600 671 #define E1000_82542_LEDCTL E1000_LEDCTL 672 #define E1000_82542_PBA E1000_PBA 673 #define E1000_82542_RXDCTL E1000_RXDCTL 674 #define E1000_82542_RADV E1000_RADV 675 #define E1000_82542_RSRPD E1000_RSRPD 676 #define E1000_82542_TXDMAC E1000_TXDMAC 677 #define E1000_82542_TXDCTL E1000_TXDCTL 678 #define E1000_82542_TADV E1000_TADV 679 #define E1000_82542_TSPMT E1000_TSPMT 680 #define E1000_82542_CRCERRS E1000_CRCERRS 681 #define E1000_82542_ALGNERRC E1000_ALGNERRC 682 #define E1000_82542_SYMERRS E1000_SYMERRS 683 #define E1000_82542_RXERRC E1000_RXERRC 684 #define E1000_82542_MPC E1000_MPC 685 #define E1000_82542_SCC E1000_SCC 686 #define E1000_82542_ECOL E1000_ECOL 687 #define E1000_82542_MCC E1000_MCC 688 #define E1000_82542_LATECOL E1000_LATECOL 689 #define E1000_82542_COLC E1000_COLC 690 #define E1000_82542_DC E1000_DC 691 #define E1000_82542_TNCRS E1000_TNCRS 692 #define E1000_82542_SEC E1000_SEC 693 #define E1000_82542_CEXTERR E1000_CEXTERR 694 #define E1000_82542_RLEC E1000_RLEC 695 #define E1000_82542_XONRXC E1000_XONRXC 696 #define E1000_82542_XONTXC E1000_XONTXC 697 #define E1000_82542_XOFFRXC E1000_XOFFRXC 698 #define E1000_82542_XOFFTXC E1000_XOFFTXC 699 #define E1000_82542_FCRUC E1000_FCRUC 700 #define E1000_82542_PRC64 E1000_PRC64 701 #define E1000_82542_PRC127 E1000_PRC127 702 #define E1000_82542_PRC255 E1000_PRC255 703 #define E1000_82542_PRC511 E1000_PRC511 704 #define E1000_82542_PRC1023 E1000_PRC1023 705 #define E1000_82542_PRC1522 E1000_PRC1522 706 #define E1000_82542_GPRC E1000_GPRC 707 #define E1000_82542_BPRC E1000_BPRC 708 #define E1000_82542_MPRC E1000_MPRC 709 #define E1000_82542_GPTC E1000_GPTC 710 #define E1000_82542_GORCL E1000_GORCL 711 #define E1000_82542_GORCH E1000_GORCH 712 #define E1000_82542_GOTCL E1000_GOTCL 713 #define E1000_82542_GOTCH E1000_GOTCH 714 #define E1000_82542_RNBC E1000_RNBC 715 #define E1000_82542_RUC E1000_RUC 716 #define E1000_82542_RFC E1000_RFC 717 #define E1000_82542_ROC E1000_ROC 718 #define E1000_82542_RJC E1000_RJC 719 #define E1000_82542_MGTPRC E1000_MGTPRC 720 #define E1000_82542_MGTPDC E1000_MGTPDC 721 #define E1000_82542_MGTPTC E1000_MGTPTC 722 #define E1000_82542_TORL E1000_TORL 723 #define E1000_82542_TORH E1000_TORH 724 #define E1000_82542_TOTL E1000_TOTL 725 #define E1000_82542_TOTH E1000_TOTH 726 #define E1000_82542_TPR E1000_TPR 727 #define E1000_82542_TPT E1000_TPT 728 #define E1000_82542_PTC64 E1000_PTC64 729 #define E1000_82542_PTC127 E1000_PTC127 730 #define E1000_82542_PTC255 E1000_PTC255 731 #define E1000_82542_PTC511 E1000_PTC511 732 #define E1000_82542_PTC1023 E1000_PTC1023 733 #define E1000_82542_PTC1522 E1000_PTC1522 734 #define E1000_82542_MPTC E1000_MPTC 735 #define E1000_82542_BPTC E1000_BPTC 736 #define E1000_82542_TSCTC E1000_TSCTC 737 #define E1000_82542_TSCTFC E1000_TSCTFC 738 #define E1000_82542_RXCSUM E1000_RXCSUM 739 #define E1000_82542_WUC E1000_WUC 740 #define E1000_82542_WUFC E1000_WUFC 741 #define E1000_82542_WUS E1000_WUS 742 #define E1000_82542_MANC E1000_MANC 743 #define E1000_82542_IPAV E1000_IPAV 744 #define E1000_82542_IP4AT E1000_IP4AT 745 #define E1000_82542_IP6AT E1000_IP6AT 746 #define E1000_82542_WUPL E1000_WUPL 747 #define E1000_82542_WUPM E1000_WUPM 748 #define E1000_82542_FFLT E1000_FFLT 749 #define E1000_82542_FFMT E1000_FFMT 750 #define E1000_82542_FFVT E1000_FFVT 751 752 /* Statistics counters collected by the MAC */ 753 struct e1000_hw_stats { 754 uint64_t crcerrs; 755 uint64_t algnerrc; 756 uint64_t symerrs; 757 uint64_t rxerrc; 758 uint64_t mpc; 759 uint64_t scc; 760 uint64_t ecol; 761 uint64_t mcc; 762 uint64_t latecol; 763 uint64_t colc; 764 uint64_t dc; 765 uint64_t tncrs; 766 uint64_t sec; 767 uint64_t cexterr; 768 uint64_t rlec; 769 uint64_t xonrxc; 770 uint64_t xontxc; 771 uint64_t xoffrxc; 772 uint64_t xofftxc; 773 uint64_t fcruc; 774 uint64_t prc64; 775 uint64_t prc127; 776 uint64_t prc255; 777 uint64_t prc511; 778 uint64_t prc1023; 779 uint64_t prc1522; 780 uint64_t gprc; 781 uint64_t bprc; 782 uint64_t mprc; 783 uint64_t gptc; 784 uint64_t gorcl; 785 uint64_t gorch; 786 uint64_t gotcl; 787 uint64_t gotch; 788 uint64_t rnbc; 789 uint64_t ruc; 790 uint64_t rfc; 791 uint64_t roc; 792 uint64_t rjc; 793 uint64_t mgprc; 794 uint64_t mgpdc; 795 uint64_t mgptc; 796 uint64_t torl; 797 uint64_t torh; 798 uint64_t totl; 799 uint64_t toth; 800 uint64_t tpr; 801 uint64_t tpt; 802 uint64_t ptc64; 803 uint64_t ptc127; 804 uint64_t ptc255; 805 uint64_t ptc511; 806 uint64_t ptc1023; 807 uint64_t ptc1522; 808 uint64_t mptc; 809 uint64_t bptc; 810 uint64_t tsctc; 811 uint64_t tsctfc; 812 }; 813 814 /* Structure containing variables used by the shared code (e1000_hw.c) */ 815 struct e1000_hw { 816 pci_dev_t pdev; 817 uint8_t *hw_addr; 818 e1000_mac_type mac_type; 819 e1000_phy_type phy_type; 820 uint32_t phy_init_script; 821 e1000_media_type media_type; 822 e1000_lan_loc lan_loc; 823 e1000_fc_type fc; 824 #if 0 825 e1000_bus_speed bus_speed; 826 e1000_bus_width bus_width; 827 e1000_bus_type bus_type; 828 uint32_t io_base; 829 #endif 830 uint32_t phy_id; 831 uint32_t phy_addr; 832 uint32_t original_fc; 833 uint32_t txcw; 834 uint32_t autoneg_failed; 835 #if 0 836 uint32_t max_frame_size; 837 uint32_t min_frame_size; 838 uint32_t mc_filter_type; 839 uint32_t num_mc_addrs; 840 uint32_t collision_delta; 841 uint32_t tx_packet_delta; 842 uint32_t ledctl_default; 843 uint32_t ledctl_mode1; 844 uint32_t ledctl_mode2; 845 #endif 846 uint16_t autoneg_advertised; 847 uint16_t pci_cmd_word; 848 uint16_t fc_high_water; 849 uint16_t fc_low_water; 850 uint16_t fc_pause_time; 851 #if 0 852 uint16_t current_ifs_val; 853 uint16_t ifs_min_val; 854 uint16_t ifs_max_val; 855 uint16_t ifs_step_size; 856 uint16_t ifs_ratio; 857 #endif 858 uint16_t device_id; 859 uint16_t vendor_id; 860 uint16_t subsystem_id; 861 uint16_t subsystem_vendor_id; 862 uint8_t revision_id; 863 #if 0 864 uint8_t autoneg; 865 uint8_t mdix; 866 uint8_t forced_speed_duplex; 867 uint8_t wait_autoneg_complete; 868 uint8_t dma_fairness; 869 #endif 870 #if 0 871 uint8_t perm_mac_addr[NODE_ADDRESS_SIZE]; 872 boolean_t disable_polarity_correction; 873 #endif 874 boolean_t get_link_status; 875 boolean_t tbi_compatibility_en; 876 boolean_t tbi_compatibility_on; 877 boolean_t fc_send_xon; 878 boolean_t report_tx_early; 879 #if 0 880 boolean_t adaptive_ifs; 881 boolean_t ifs_params_forced; 882 boolean_t in_ifs_mode; 883 #endif 884 }; 885 886 #define E1000_EEPROM_SWDPIN0 0x0001 /* SWDPIN 0 EEPROM Value */ 887 #define E1000_EEPROM_LED_LOGIC 0x0020 /* Led Logic Word */ 888 889 /* Register Bit Masks */ 890 /* Device Control */ 891 #define E1000_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */ 892 #define E1000_CTRL_BEM 0x00000002 /* Endian Mode.0=little,1=big */ 893 #define E1000_CTRL_PRIOR 0x00000004 /* Priority on PCI. 0=rx,1=fair */ 894 #define E1000_CTRL_LRST 0x00000008 /* Link reset. 0=normal,1=reset */ 895 #define E1000_CTRL_TME 0x00000010 /* Test mode. 0=normal,1=test */ 896 #define E1000_CTRL_SLE 0x00000020 /* Serial Link on 0=dis,1=en */ 897 #define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */ 898 #define E1000_CTRL_SLU 0x00000040 /* Set link up (Force Link) */ 899 #define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */ 900 #define E1000_CTRL_SPD_SEL 0x00000300 /* Speed Select Mask */ 901 #define E1000_CTRL_SPD_10 0x00000000 /* Force 10Mb */ 902 #define E1000_CTRL_SPD_100 0x00000100 /* Force 100Mb */ 903 #define E1000_CTRL_SPD_1000 0x00000200 /* Force 1Gb */ 904 #define E1000_CTRL_BEM32 0x00000400 /* Big Endian 32 mode */ 905 #define E1000_CTRL_FRCSPD 0x00000800 /* Force Speed */ 906 #define E1000_CTRL_FRCDPX 0x00001000 /* Force Duplex */ 907 #define E1000_CTRL_SWDPIN0 0x00040000 /* SWDPIN 0 value */ 908 #define E1000_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */ 909 #define E1000_CTRL_SWDPIN2 0x00100000 /* SWDPIN 2 value */ 910 #define E1000_CTRL_SWDPIN3 0x00200000 /* SWDPIN 3 value */ 911 #define E1000_CTRL_SWDPIO0 0x00400000 /* SWDPIN 0 Input or output */ 912 #define E1000_CTRL_SWDPIO1 0x00800000 /* SWDPIN 1 input or output */ 913 #define E1000_CTRL_SWDPIO2 0x01000000 /* SWDPIN 2 input or output */ 914 #define E1000_CTRL_SWDPIO3 0x02000000 /* SWDPIN 3 input or output */ 915 #define E1000_CTRL_RST 0x04000000 /* Global reset */ 916 #define E1000_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */ 917 #define E1000_CTRL_TFCE 0x10000000 /* Transmit flow control enable */ 918 #define E1000_CTRL_RTE 0x20000000 /* Routing tag enable */ 919 #define E1000_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */ 920 #define E1000_CTRL_PHY_RST 0x80000000 /* PHY Reset */ 921 922 /* Device Status */ 923 #define E1000_STATUS_FD 0x00000001 /* Full duplex.0=half,1=full */ 924 #define E1000_STATUS_LU 0x00000002 /* Link up.0=no,1=link */ 925 #define E1000_STATUS_FUNC_MASK 0x0000000C /* PCI Function Mask */ 926 #define E1000_STATUS_FUNC_0 0x00000000 /* Function 0 */ 927 #define E1000_STATUS_FUNC_1 0x00000004 /* Function 1 */ 928 #define E1000_STATUS_TXOFF 0x00000010 /* transmission paused */ 929 #define E1000_STATUS_TBIMODE 0x00000020 /* TBI mode */ 930 #define E1000_STATUS_SPEED_MASK 0x000000C0 931 #define E1000_STATUS_SPEED_10 0x00000000 /* Speed 10Mb/s */ 932 #define E1000_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */ 933 #define E1000_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */ 934 #define E1000_STATUS_ASDV 0x00000300 /* Auto speed detect value */ 935 #define E1000_STATUS_MTXCKOK 0x00000400 /* MTX clock running OK */ 936 #define E1000_STATUS_PCI66 0x00000800 /* In 66Mhz slot */ 937 #define E1000_STATUS_BUS64 0x00001000 /* In 64 bit slot */ 938 #define E1000_STATUS_PCIX_MODE 0x00002000 /* PCI-X mode */ 939 #define E1000_STATUS_PCIX_SPEED 0x0000C000 /* PCI-X bus speed */ 940 941 /* Constants used to intrepret the masked PCI-X bus speed. */ 942 #define E1000_STATUS_PCIX_SPEED_66 0x00000000 /* PCI-X bus speed 50-66 MHz */ 943 #define E1000_STATUS_PCIX_SPEED_100 0x00004000 /* PCI-X bus speed 66-100 MHz */ 944 #define E1000_STATUS_PCIX_SPEED_133 0x00008000 /* PCI-X bus speed 100-133 MHz */ 945 946 /* EEPROM/Flash Control */ 947 #define E1000_EECD_SK 0x00000001 /* EEPROM Clock */ 948 #define E1000_EECD_CS 0x00000002 /* EEPROM Chip Select */ 949 #define E1000_EECD_DI 0x00000004 /* EEPROM Data In */ 950 #define E1000_EECD_DO 0x00000008 /* EEPROM Data Out */ 951 #define E1000_EECD_FWE_MASK 0x00000030 952 #define E1000_EECD_FWE_DIS 0x00000010 /* Disable FLASH writes */ 953 #define E1000_EECD_FWE_EN 0x00000020 /* Enable FLASH writes */ 954 #define E1000_EECD_FWE_SHIFT 4 955 #define E1000_EECD_SIZE 0x00000200 /* EEPROM Size (0=64 word 1=256 word) */ 956 #define E1000_EECD_REQ 0x00000040 /* EEPROM Access Request */ 957 #define E1000_EECD_GNT 0x00000080 /* EEPROM Access Grant */ 958 #define E1000_EECD_PRES 0x00000100 /* EEPROM Present */ 959 960 /* EEPROM Read */ 961 #define E1000_EERD_START 0x00000001 /* Start Read */ 962 #define E1000_EERD_DONE 0x00000010 /* Read Done */ 963 #define E1000_EERD_ADDR_SHIFT 8 964 #define E1000_EERD_ADDR_MASK 0x0000FF00 /* Read Address */ 965 #define E1000_EERD_DATA_SHIFT 16 966 #define E1000_EERD_DATA_MASK 0xFFFF0000 /* Read Data */ 967 968 /* Extended Device Control */ 969 #define E1000_CTRL_EXT_GPI0_EN 0x00000001 /* Maps SDP4 to GPI0 */ 970 #define E1000_CTRL_EXT_GPI1_EN 0x00000002 /* Maps SDP5 to GPI1 */ 971 #define E1000_CTRL_EXT_PHYINT_EN E1000_CTRL_EXT_GPI1_EN 972 #define E1000_CTRL_EXT_GPI2_EN 0x00000004 /* Maps SDP6 to GPI2 */ 973 #define E1000_CTRL_EXT_GPI3_EN 0x00000008 /* Maps SDP7 to GPI3 */ 974 #define E1000_CTRL_EXT_SDP4_DATA 0x00000010 /* Value of SW Defineable Pin 4 */ 975 #define E1000_CTRL_EXT_SDP5_DATA 0x00000020 /* Value of SW Defineable Pin 5 */ 976 #define E1000_CTRL_EXT_PHY_INT E1000_CTRL_EXT_SDP5_DATA 977 #define E1000_CTRL_EXT_SDP6_DATA 0x00000040 /* Value of SW Defineable Pin 6 */ 978 #define E1000_CTRL_EXT_SWDPIN6 0x00000040 /* SWDPIN 6 value */ 979 #define E1000_CTRL_EXT_SDP7_DATA 0x00000080 /* Value of SW Defineable Pin 7 */ 980 #define E1000_CTRL_EXT_SWDPIN7 0x00000080 /* SWDPIN 7 value */ 981 #define E1000_CTRL_EXT_SDP4_DIR 0x00000100 /* Direction of SDP4 0=in 1=out */ 982 #define E1000_CTRL_EXT_SDP5_DIR 0x00000200 /* Direction of SDP5 0=in 1=out */ 983 #define E1000_CTRL_EXT_SDP6_DIR 0x00000400 /* Direction of SDP6 0=in 1=out */ 984 #define E1000_CTRL_EXT_SWDPIO6 0x00000400 /* SWDPIN 6 Input or output */ 985 #define E1000_CTRL_EXT_SDP7_DIR 0x00000800 /* Direction of SDP7 0=in 1=out */ 986 #define E1000_CTRL_EXT_SWDPIO7 0x00000800 /* SWDPIN 7 Input or output */ 987 #define E1000_CTRL_EXT_ASDCHK 0x00001000 /* Initiate an ASD sequence */ 988 #define E1000_CTRL_EXT_EE_RST 0x00002000 /* Reinitialize from EEPROM */ 989 #define E1000_CTRL_EXT_IPS 0x00004000 /* Invert Power State */ 990 #define E1000_CTRL_EXT_SPD_BYPS 0x00008000 /* Speed Select Bypass */ 991 #define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000 992 #define E1000_CTRL_EXT_LINK_MODE_GMII 0x00000000 993 #define E1000_CTRL_EXT_LINK_MODE_TBI 0x00C00000 994 #define E1000_CTRL_EXT_WR_WMARK_MASK 0x03000000 995 #define E1000_CTRL_EXT_WR_WMARK_256 0x00000000 996 #define E1000_CTRL_EXT_WR_WMARK_320 0x01000000 997 #define E1000_CTRL_EXT_WR_WMARK_384 0x02000000 998 #define E1000_CTRL_EXT_WR_WMARK_448 0x03000000 999 1000 /* MDI Control */ 1001 #define E1000_MDIC_DATA_MASK 0x0000FFFF 1002 #define E1000_MDIC_REG_MASK 0x001F0000 1003 #define E1000_MDIC_REG_SHIFT 16 1004 #define E1000_MDIC_PHY_MASK 0x03E00000 1005 #define E1000_MDIC_PHY_SHIFT 21 1006 #define E1000_MDIC_OP_WRITE 0x04000000 1007 #define E1000_MDIC_OP_READ 0x08000000 1008 #define E1000_MDIC_READY 0x10000000 1009 #define E1000_MDIC_INT_EN 0x20000000 1010 #define E1000_MDIC_ERROR 0x40000000 1011 1012 /* LED Control */ 1013 #define E1000_LEDCTL_LED0_MODE_MASK 0x0000000F 1014 #define E1000_LEDCTL_LED0_MODE_SHIFT 0 1015 #define E1000_LEDCTL_LED0_IVRT 0x00000040 1016 #define E1000_LEDCTL_LED0_BLINK 0x00000080 1017 #define E1000_LEDCTL_LED1_MODE_MASK 0x00000F00 1018 #define E1000_LEDCTL_LED1_MODE_SHIFT 8 1019 #define E1000_LEDCTL_LED1_IVRT 0x00004000 1020 #define E1000_LEDCTL_LED1_BLINK 0x00008000 1021 #define E1000_LEDCTL_LED2_MODE_MASK 0x000F0000 1022 #define E1000_LEDCTL_LED2_MODE_SHIFT 16 1023 #define E1000_LEDCTL_LED2_IVRT 0x00400000 1024 #define E1000_LEDCTL_LED2_BLINK 0x00800000 1025 #define E1000_LEDCTL_LED3_MODE_MASK 0x0F000000 1026 #define E1000_LEDCTL_LED3_MODE_SHIFT 24 1027 #define E1000_LEDCTL_LED3_IVRT 0x40000000 1028 #define E1000_LEDCTL_LED3_BLINK 0x80000000 1029 1030 #define E1000_LEDCTL_MODE_LINK_10_1000 0x0 1031 #define E1000_LEDCTL_MODE_LINK_100_1000 0x1 1032 #define E1000_LEDCTL_MODE_LINK_UP 0x2 1033 #define E1000_LEDCTL_MODE_ACTIVITY 0x3 1034 #define E1000_LEDCTL_MODE_LINK_ACTIVITY 0x4 1035 #define E1000_LEDCTL_MODE_LINK_10 0x5 1036 #define E1000_LEDCTL_MODE_LINK_100 0x6 1037 #define E1000_LEDCTL_MODE_LINK_1000 0x7 1038 #define E1000_LEDCTL_MODE_PCIX_MODE 0x8 1039 #define E1000_LEDCTL_MODE_FULL_DUPLEX 0x9 1040 #define E1000_LEDCTL_MODE_COLLISION 0xA 1041 #define E1000_LEDCTL_MODE_BUS_SPEED 0xB 1042 #define E1000_LEDCTL_MODE_BUS_SIZE 0xC 1043 #define E1000_LEDCTL_MODE_PAUSED 0xD 1044 #define E1000_LEDCTL_MODE_LED_ON 0xE 1045 #define E1000_LEDCTL_MODE_LED_OFF 0xF 1046 1047 /* Receive Address */ 1048 #define E1000_RAH_AV 0x80000000 /* Receive descriptor valid */ 1049 1050 /* Interrupt Cause Read */ 1051 #define E1000_ICR_TXDW 0x00000001 /* Transmit desc written back */ 1052 #define E1000_ICR_TXQE 0x00000002 /* Transmit Queue empty */ 1053 #define E1000_ICR_LSC 0x00000004 /* Link Status Change */ 1054 #define E1000_ICR_RXSEQ 0x00000008 /* rx sequence error */ 1055 #define E1000_ICR_RXDMT0 0x00000010 /* rx desc min. threshold (0) */ 1056 #define E1000_ICR_RXO 0x00000040 /* rx overrun */ 1057 #define E1000_ICR_RXT0 0x00000080 /* rx timer intr (ring 0) */ 1058 #define E1000_ICR_MDAC 0x00000200 /* MDIO access complete */ 1059 #define E1000_ICR_RXCFG 0x00000400 /* RX /c/ ordered set */ 1060 #define E1000_ICR_GPI_EN0 0x00000800 /* GP Int 0 */ 1061 #define E1000_ICR_GPI_EN1 0x00001000 /* GP Int 1 */ 1062 #define E1000_ICR_GPI_EN2 0x00002000 /* GP Int 2 */ 1063 #define E1000_ICR_GPI_EN3 0x00004000 /* GP Int 3 */ 1064 #define E1000_ICR_TXD_LOW 0x00008000 1065 #define E1000_ICR_SRPD 0x00010000 1066 1067 /* Interrupt Cause Set */ 1068 #define E1000_ICS_TXDW E1000_ICR_TXDW /* Transmit desc written back */ 1069 #define E1000_ICS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */ 1070 #define E1000_ICS_LSC E1000_ICR_LSC /* Link Status Change */ 1071 #define E1000_ICS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */ 1072 #define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */ 1073 #define E1000_ICS_RXO E1000_ICR_RXO /* rx overrun */ 1074 #define E1000_ICS_RXT0 E1000_ICR_RXT0 /* rx timer intr */ 1075 #define E1000_ICS_MDAC E1000_ICR_MDAC /* MDIO access complete */ 1076 #define E1000_ICS_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */ 1077 #define E1000_ICS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */ 1078 #define E1000_ICS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */ 1079 #define E1000_ICS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */ 1080 #define E1000_ICS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */ 1081 #define E1000_ICS_TXD_LOW E1000_ICR_TXD_LOW 1082 #define E1000_ICS_SRPD E1000_ICR_SRPD 1083 1084 /* Interrupt Mask Set */ 1085 #define E1000_IMS_TXDW E1000_ICR_TXDW /* Transmit desc written back */ 1086 #define E1000_IMS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */ 1087 #define E1000_IMS_LSC E1000_ICR_LSC /* Link Status Change */ 1088 #define E1000_IMS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */ 1089 #define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */ 1090 #define E1000_IMS_RXO E1000_ICR_RXO /* rx overrun */ 1091 #define E1000_IMS_RXT0 E1000_ICR_RXT0 /* rx timer intr */ 1092 #define E1000_IMS_MDAC E1000_ICR_MDAC /* MDIO access complete */ 1093 #define E1000_IMS_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */ 1094 #define E1000_IMS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */ 1095 #define E1000_IMS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */ 1096 #define E1000_IMS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */ 1097 #define E1000_IMS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */ 1098 #define E1000_IMS_TXD_LOW E1000_ICR_TXD_LOW 1099 #define E1000_IMS_SRPD E1000_ICR_SRPD 1100 1101 /* Interrupt Mask Clear */ 1102 #define E1000_IMC_TXDW E1000_ICR_TXDW /* Transmit desc written back */ 1103 #define E1000_IMC_TXQE E1000_ICR_TXQE /* Transmit Queue empty */ 1104 #define E1000_IMC_LSC E1000_ICR_LSC /* Link Status Change */ 1105 #define E1000_IMC_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */ 1106 #define E1000_IMC_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */ 1107 #define E1000_IMC_RXO E1000_ICR_RXO /* rx overrun */ 1108 #define E1000_IMC_RXT0 E1000_ICR_RXT0 /* rx timer intr */ 1109 #define E1000_IMC_MDAC E1000_ICR_MDAC /* MDIO access complete */ 1110 #define E1000_IMC_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */ 1111 #define E1000_IMC_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */ 1112 #define E1000_IMC_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */ 1113 #define E1000_IMC_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */ 1114 #define E1000_IMC_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */ 1115 #define E1000_IMC_TXD_LOW E1000_ICR_TXD_LOW 1116 #define E1000_IMC_SRPD E1000_ICR_SRPD 1117 1118 /* Receive Control */ 1119 #define E1000_RCTL_RST 0x00000001 /* Software reset */ 1120 #define E1000_RCTL_EN 0x00000002 /* enable */ 1121 #define E1000_RCTL_SBP 0x00000004 /* store bad packet */ 1122 #define E1000_RCTL_UPE 0x00000008 /* unicast promiscuous enable */ 1123 #define E1000_RCTL_MPE 0x00000010 /* multicast promiscuous enab */ 1124 #define E1000_RCTL_LPE 0x00000020 /* long packet enable */ 1125 #define E1000_RCTL_LBM_NO 0x00000000 /* no loopback mode */ 1126 #define E1000_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */ 1127 #define E1000_RCTL_LBM_SLP 0x00000080 /* serial link loopback mode */ 1128 #define E1000_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */ 1129 #define E1000_RCTL_RDMTS_HALF 0x00000000 /* rx desc min threshold size */ 1130 #define E1000_RCTL_RDMTS_QUAT 0x00000100 /* rx desc min threshold size */ 1131 #define E1000_RCTL_RDMTS_EIGTH 0x00000200 /* rx desc min threshold size */ 1132 #define E1000_RCTL_MO_SHIFT 12 /* multicast offset shift */ 1133 #define E1000_RCTL_MO_0 0x00000000 /* multicast offset 11:0 */ 1134 #define E1000_RCTL_MO_1 0x00001000 /* multicast offset 12:1 */ 1135 #define E1000_RCTL_MO_2 0x00002000 /* multicast offset 13:2 */ 1136 #define E1000_RCTL_MO_3 0x00003000 /* multicast offset 15:4 */ 1137 #define E1000_RCTL_MDR 0x00004000 /* multicast desc ring 0 */ 1138 #define E1000_RCTL_BAM 0x00008000 /* broadcast enable */ 1139 /* these buffer sizes are valid if E1000_RCTL_BSEX is 0 */ 1140 #define E1000_RCTL_SZ_2048 0x00000000 /* rx buffer size 2048 */ 1141 #define E1000_RCTL_SZ_1024 0x00010000 /* rx buffer size 1024 */ 1142 #define E1000_RCTL_SZ_512 0x00020000 /* rx buffer size 512 */ 1143 #define E1000_RCTL_SZ_256 0x00030000 /* rx buffer size 256 */ 1144 /* these buffer sizes are valid if E1000_RCTL_BSEX is 1 */ 1145 #define E1000_RCTL_SZ_16384 0x00010000 /* rx buffer size 16384 */ 1146 #define E1000_RCTL_SZ_8192 0x00020000 /* rx buffer size 8192 */ 1147 #define E1000_RCTL_SZ_4096 0x00030000 /* rx buffer size 4096 */ 1148 #define E1000_RCTL_VFE 0x00040000 /* vlan filter enable */ 1149 #define E1000_RCTL_CFIEN 0x00080000 /* canonical form enable */ 1150 #define E1000_RCTL_CFI 0x00100000 /* canonical form indicator */ 1151 #define E1000_RCTL_DPF 0x00400000 /* discard pause frames */ 1152 #define E1000_RCTL_PMCF 0x00800000 /* pass MAC control frames */ 1153 #define E1000_RCTL_BSEX 0x02000000 /* Buffer size extension */ 1154 1155 /* Receive Descriptor */ 1156 #define E1000_RDT_DELAY 0x0000ffff /* Delay timer (1=1024us) */ 1157 #define E1000_RDT_FPDB 0x80000000 /* Flush descriptor block */ 1158 #define E1000_RDLEN_LEN 0x0007ff80 /* descriptor length */ 1159 #define E1000_RDH_RDH 0x0000ffff /* receive descriptor head */ 1160 #define E1000_RDT_RDT 0x0000ffff /* receive descriptor tail */ 1161 1162 /* Flow Control */ 1163 #define E1000_FCRTH_RTH 0x0000FFF8 /* Mask Bits[15:3] for RTH */ 1164 #define E1000_FCRTH_XFCE 0x80000000 /* External Flow Control Enable */ 1165 #define E1000_FCRTL_RTL 0x0000FFF8 /* Mask Bits[15:3] for RTL */ 1166 #define E1000_FCRTL_XONE 0x80000000 /* Enable XON frame transmission */ 1167 1168 /* Receive Descriptor Control */ 1169 #define E1000_RXDCTL_PTHRESH 0x0000003F /* RXDCTL Prefetch Threshold */ 1170 #define E1000_RXDCTL_HTHRESH 0x00003F00 /* RXDCTL Host Threshold */ 1171 #define E1000_RXDCTL_WTHRESH 0x003F0000 /* RXDCTL Writeback Threshold */ 1172 #define E1000_RXDCTL_GRAN 0x01000000 /* RXDCTL Granularity */ 1173 1174 /* Transmit Descriptor Control */ 1175 #define E1000_TXDCTL_PTHRESH 0x000000FF /* TXDCTL Prefetch Threshold */ 1176 #define E1000_TXDCTL_HTHRESH 0x0000FF00 /* TXDCTL Host Threshold */ 1177 #define E1000_TXDCTL_WTHRESH 0x00FF0000 /* TXDCTL Writeback Threshold */ 1178 #define E1000_TXDCTL_GRAN 0x01000000 /* TXDCTL Granularity */ 1179 #define E1000_TXDCTL_LWTHRESH 0xFE000000 /* TXDCTL Low Threshold */ 1180 #define E1000_TXDCTL_FULL_TX_DESC_WB 0x01010000 /* GRAN=1, WTHRESH=1 */ 1181 1182 /* Transmit Configuration Word */ 1183 #define E1000_TXCW_FD 0x00000020 /* TXCW full duplex */ 1184 #define E1000_TXCW_HD 0x00000040 /* TXCW half duplex */ 1185 #define E1000_TXCW_PAUSE 0x00000080 /* TXCW sym pause request */ 1186 #define E1000_TXCW_ASM_DIR 0x00000100 /* TXCW astm pause direction */ 1187 #define E1000_TXCW_PAUSE_MASK 0x00000180 /* TXCW pause request mask */ 1188 #define E1000_TXCW_RF 0x00003000 /* TXCW remote fault */ 1189 #define E1000_TXCW_NP 0x00008000 /* TXCW next page */ 1190 #define E1000_TXCW_CW 0x0000ffff /* TxConfigWord mask */ 1191 #define E1000_TXCW_TXC 0x40000000 /* Transmit Config control */ 1192 #define E1000_TXCW_ANE 0x80000000 /* Auto-neg enable */ 1193 1194 /* Receive Configuration Word */ 1195 #define E1000_RXCW_CW 0x0000ffff /* RxConfigWord mask */ 1196 #define E1000_RXCW_NC 0x04000000 /* Receive config no carrier */ 1197 #define E1000_RXCW_IV 0x08000000 /* Receive config invalid */ 1198 #define E1000_RXCW_CC 0x10000000 /* Receive config change */ 1199 #define E1000_RXCW_C 0x20000000 /* Receive config */ 1200 #define E1000_RXCW_SYNCH 0x40000000 /* Receive config synch */ 1201 #define E1000_RXCW_ANC 0x80000000 /* Auto-neg complete */ 1202 1203 /* Transmit Control */ 1204 #define E1000_TCTL_RST 0x00000001 /* software reset */ 1205 #define E1000_TCTL_EN 0x00000002 /* enable tx */ 1206 #define E1000_TCTL_BCE 0x00000004 /* busy check enable */ 1207 #define E1000_TCTL_PSP 0x00000008 /* pad short packets */ 1208 #define E1000_TCTL_CT 0x00000ff0 /* collision threshold */ 1209 #define E1000_TCTL_COLD 0x003ff000 /* collision distance */ 1210 #define E1000_TCTL_SWXOFF 0x00400000 /* SW Xoff transmission */ 1211 #define E1000_TCTL_PBE 0x00800000 /* Packet Burst Enable */ 1212 #define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */ 1213 #define E1000_TCTL_NRTU 0x02000000 /* No Re-transmit on underrun */ 1214 1215 /* Receive Checksum Control */ 1216 #define E1000_RXCSUM_PCSS_MASK 0x000000FF /* Packet Checksum Start */ 1217 #define E1000_RXCSUM_IPOFL 0x00000100 /* IPv4 checksum offload */ 1218 #define E1000_RXCSUM_TUOFL 0x00000200 /* TCP / UDP checksum offload */ 1219 #define E1000_RXCSUM_IPV6OFL 0x00000400 /* IPv6 checksum offload */ 1220 1221 /* Definitions for power management and wakeup registers */ 1222 /* Wake Up Control */ 1223 #define E1000_WUC_APME 0x00000001 /* APM Enable */ 1224 #define E1000_WUC_PME_EN 0x00000002 /* PME Enable */ 1225 #define E1000_WUC_PME_STATUS 0x00000004 /* PME Status */ 1226 #define E1000_WUC_APMPME 0x00000008 /* Assert PME on APM Wakeup */ 1227 1228 /* Wake Up Filter Control */ 1229 #define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */ 1230 #define E1000_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */ 1231 #define E1000_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */ 1232 #define E1000_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */ 1233 #define E1000_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */ 1234 #define E1000_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */ 1235 #define E1000_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */ 1236 #define E1000_WUFC_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Enable */ 1237 #define E1000_WUFC_FLX0 0x00010000 /* Flexible Filter 0 Enable */ 1238 #define E1000_WUFC_FLX1 0x00020000 /* Flexible Filter 1 Enable */ 1239 #define E1000_WUFC_FLX2 0x00040000 /* Flexible Filter 2 Enable */ 1240 #define E1000_WUFC_FLX3 0x00080000 /* Flexible Filter 3 Enable */ 1241 #define E1000_WUFC_ALL_FILTERS 0x000F00FF /* Mask for all wakeup filters */ 1242 #define E1000_WUFC_FLX_OFFSET 16 /* Offset to the Flexible Filters bits */ 1243 #define E1000_WUFC_FLX_FILTERS 0x000F0000 /* Mask for the 4 flexible filters */ 1244 1245 /* Wake Up Status */ 1246 #define E1000_WUS_LNKC 0x00000001 /* Link Status Changed */ 1247 #define E1000_WUS_MAG 0x00000002 /* Magic Packet Received */ 1248 #define E1000_WUS_EX 0x00000004 /* Directed Exact Received */ 1249 #define E1000_WUS_MC 0x00000008 /* Directed Multicast Received */ 1250 #define E1000_WUS_BC 0x00000010 /* Broadcast Received */ 1251 #define E1000_WUS_ARP 0x00000020 /* ARP Request Packet Received */ 1252 #define E1000_WUS_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Received */ 1253 #define E1000_WUS_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Received */ 1254 #define E1000_WUS_FLX0 0x00010000 /* Flexible Filter 0 Match */ 1255 #define E1000_WUS_FLX1 0x00020000 /* Flexible Filter 1 Match */ 1256 #define E1000_WUS_FLX2 0x00040000 /* Flexible Filter 2 Match */ 1257 #define E1000_WUS_FLX3 0x00080000 /* Flexible Filter 3 Match */ 1258 #define E1000_WUS_FLX_FILTERS 0x000F0000 /* Mask for the 4 flexible filters */ 1259 1260 /* Management Control */ 1261 #define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */ 1262 #define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */ 1263 #define E1000_MANC_R_ON_FORCE 0x00000004 /* Reset on Force TCO - RO */ 1264 #define E1000_MANC_RMCP_EN 0x00000100 /* Enable RCMP 026Fh Filtering */ 1265 #define E1000_MANC_0298_EN 0x00000200 /* Enable RCMP 0298h Filtering */ 1266 #define E1000_MANC_IPV4_EN 0x00000400 /* Enable IPv4 */ 1267 #define E1000_MANC_IPV6_EN 0x00000800 /* Enable IPv6 */ 1268 #define E1000_MANC_SNAP_EN 0x00001000 /* Accept LLC/SNAP */ 1269 #define E1000_MANC_ARP_EN 0x00002000 /* Enable ARP Request Filtering */ 1270 #define E1000_MANC_NEIGHBOR_EN 0x00004000 /* Enable Neighbor Discovery 1271 * Filtering */ 1272 #define E1000_MANC_TCO_RESET 0x00010000 /* TCO Reset Occurred */ 1273 #define E1000_MANC_RCV_TCO_EN 0x00020000 /* Receive TCO Packets Enabled */ 1274 #define E1000_MANC_REPORT_STATUS 0x00040000 /* Status Reporting Enabled */ 1275 #define E1000_MANC_SMB_REQ 0x01000000 /* SMBus Request */ 1276 #define E1000_MANC_SMB_GNT 0x02000000 /* SMBus Grant */ 1277 #define E1000_MANC_SMB_CLK_IN 0x04000000 /* SMBus Clock In */ 1278 #define E1000_MANC_SMB_DATA_IN 0x08000000 /* SMBus Data In */ 1279 #define E1000_MANC_SMB_DATA_OUT 0x10000000 /* SMBus Data Out */ 1280 #define E1000_MANC_SMB_CLK_OUT 0x20000000 /* SMBus Clock Out */ 1281 1282 #define E1000_MANC_SMB_DATA_OUT_SHIFT 28 /* SMBus Data Out Shift */ 1283 #define E1000_MANC_SMB_CLK_OUT_SHIFT 29 /* SMBus Clock Out Shift */ 1284 1285 /* Wake Up Packet Length */ 1286 #define E1000_WUPL_LENGTH_MASK 0x0FFF /* Only the lower 12 bits are valid */ 1287 1288 #define E1000_MDALIGN 4096 1289 1290 /* EEPROM Commands */ 1291 #define EEPROM_READ_OPCODE 0x6 /* EERPOM read opcode */ 1292 #define EEPROM_WRITE_OPCODE 0x5 /* EERPOM write opcode */ 1293 #define EEPROM_ERASE_OPCODE 0x7 /* EERPOM erase opcode */ 1294 #define EEPROM_EWEN_OPCODE 0x13 /* EERPOM erase/write enable */ 1295 #define EEPROM_EWDS_OPCODE 0x10 /* EERPOM erast/write disable */ 1296 1297 /* EEPROM Word Offsets */ 1298 #define EEPROM_COMPAT 0x0003 1299 #define EEPROM_ID_LED_SETTINGS 0x0004 1300 #define EEPROM_INIT_CONTROL1_REG 0x000A 1301 #define EEPROM_INIT_CONTROL2_REG 0x000F 1302 #define EEPROM_FLASH_VERSION 0x0032 1303 #define EEPROM_CHECKSUM_REG 0x003F 1304 1305 /* Word definitions for ID LED Settings */ 1306 #define ID_LED_RESERVED_0000 0x0000 1307 #define ID_LED_RESERVED_FFFF 0xFFFF 1308 #define ID_LED_DEFAULT ((ID_LED_OFF1_ON2 << 12) | \ 1309 (ID_LED_OFF1_OFF2 << 8) | \ 1310 (ID_LED_DEF1_DEF2 << 4) | \ 1311 (ID_LED_DEF1_DEF2)) 1312 #define ID_LED_DEF1_DEF2 0x1 1313 #define ID_LED_DEF1_ON2 0x2 1314 #define ID_LED_DEF1_OFF2 0x3 1315 #define ID_LED_ON1_DEF2 0x4 1316 #define ID_LED_ON1_ON2 0x5 1317 #define ID_LED_ON1_OFF2 0x6 1318 #define ID_LED_OFF1_DEF2 0x7 1319 #define ID_LED_OFF1_ON2 0x8 1320 #define ID_LED_OFF1_OFF2 0x9 1321 1322 /* Mask bits for fields in Word 0x03 of the EEPROM */ 1323 #define EEPROM_COMPAT_SERVER 0x0400 1324 #define EEPROM_COMPAT_CLIENT 0x0200 1325 1326 /* Mask bits for fields in Word 0x0a of the EEPROM */ 1327 #define EEPROM_WORD0A_ILOS 0x0010 1328 #define EEPROM_WORD0A_SWDPIO 0x01E0 1329 #define EEPROM_WORD0A_LRST 0x0200 1330 #define EEPROM_WORD0A_FD 0x0400 1331 #define EEPROM_WORD0A_66MHZ 0x0800 1332 1333 /* Mask bits for fields in Word 0x0f of the EEPROM */ 1334 #define EEPROM_WORD0F_PAUSE_MASK 0x3000 1335 #define EEPROM_WORD0F_PAUSE 0x1000 1336 #define EEPROM_WORD0F_ASM_DIR 0x2000 1337 #define EEPROM_WORD0F_ANE 0x0800 1338 #define EEPROM_WORD0F_SWPDIO_EXT 0x00F0 1339 1340 /* For checksumming, the sum of all words in the EEPROM should equal 0xBABA. */ 1341 #define EEPROM_SUM 0xBABA 1342 1343 /* EEPROM Map defines (WORD OFFSETS)*/ 1344 #define EEPROM_NODE_ADDRESS_BYTE_0 0 1345 #define EEPROM_PBA_BYTE_1 8 1346 1347 /* EEPROM Map Sizes (Byte Counts) */ 1348 #define PBA_SIZE 4 1349 1350 /* Collision related configuration parameters */ 1351 #define E1000_COLLISION_THRESHOLD 16 1352 #define E1000_CT_SHIFT 4 1353 #define E1000_COLLISION_DISTANCE 64 1354 #define E1000_FDX_COLLISION_DISTANCE E1000_COLLISION_DISTANCE 1355 #define E1000_HDX_COLLISION_DISTANCE E1000_COLLISION_DISTANCE 1356 #define E1000_GB_HDX_COLLISION_DISTANCE 512 1357 #define E1000_COLD_SHIFT 12 1358 1359 /* The number of Transmit and Receive Descriptors must be a multiple of 8 */ 1360 #define REQ_TX_DESCRIPTOR_MULTIPLE 8 1361 #define REQ_RX_DESCRIPTOR_MULTIPLE 8 1362 1363 /* Default values for the transmit IPG register */ 1364 #define DEFAULT_82542_TIPG_IPGT 10 1365 #define DEFAULT_82543_TIPG_IPGT_FIBER 9 1366 #define DEFAULT_82543_TIPG_IPGT_COPPER 8 1367 1368 #define E1000_TIPG_IPGT_MASK 0x000003FF 1369 #define E1000_TIPG_IPGR1_MASK 0x000FFC00 1370 #define E1000_TIPG_IPGR2_MASK 0x3FF00000 1371 1372 #define DEFAULT_82542_TIPG_IPGR1 2 1373 #define DEFAULT_82543_TIPG_IPGR1 8 1374 #define E1000_TIPG_IPGR1_SHIFT 10 1375 1376 #define DEFAULT_82542_TIPG_IPGR2 10 1377 #define DEFAULT_82543_TIPG_IPGR2 6 1378 #define E1000_TIPG_IPGR2_SHIFT 20 1379 1380 #define E1000_TXDMAC_DPP 0x00000001 1381 1382 /* Adaptive IFS defines */ 1383 #define TX_THRESHOLD_START 8 1384 #define TX_THRESHOLD_INCREMENT 10 1385 #define TX_THRESHOLD_DECREMENT 1 1386 #define TX_THRESHOLD_STOP 190 1387 #define TX_THRESHOLD_DISABLE 0 1388 #define TX_THRESHOLD_TIMER_MS 10000 1389 #define MIN_NUM_XMITS 1000 1390 #define IFS_MAX 80 1391 #define IFS_STEP 10 1392 #define IFS_MIN 40 1393 #define IFS_RATIO 4 1394 1395 /* PBA constants */ 1396 #define E1000_PBA_16K 0x0010 /* 16KB, default TX allocation */ 1397 #define E1000_PBA_24K 0x0018 1398 #define E1000_PBA_40K 0x0028 1399 #define E1000_PBA_48K 0x0030 /* 48KB, default RX allocation */ 1400 1401 /* Flow Control Constants */ 1402 #define FLOW_CONTROL_ADDRESS_LOW 0x00C28001 1403 #define FLOW_CONTROL_ADDRESS_HIGH 0x00000100 1404 #define FLOW_CONTROL_TYPE 0x8808 1405 1406 /* The historical defaults for the flow control values are given below. */ 1407 #define FC_DEFAULT_HI_THRESH (0x8000) /* 32KB */ 1408 #define FC_DEFAULT_LO_THRESH (0x4000) /* 16KB */ 1409 #define FC_DEFAULT_TX_TIMER (0x100) /* ~130 us */ 1410 1411 /* Flow Control High-Watermark: 43464 bytes */ 1412 #define E1000_FC_HIGH_THRESH 0xA9C8 1413 /* Flow Control Low-Watermark: 43456 bytes */ 1414 #define E1000_FC_LOW_THRESH 0xA9C0 1415 /* Flow Control Pause Time: 858 usec */ 1416 #define E1000_FC_PAUSE_TIME 0x0680 1417 1418 /* PCIX Config space */ 1419 #define PCIX_COMMAND_REGISTER 0xE6 1420 #define PCIX_STATUS_REGISTER_LO 0xE8 1421 #define PCIX_STATUS_REGISTER_HI 0xEA 1422 1423 #define PCIX_COMMAND_MMRBC_MASK 0x000C 1424 #define PCIX_COMMAND_MMRBC_SHIFT 0x2 1425 #define PCIX_STATUS_HI_MMRBC_MASK 0x0060 1426 #define PCIX_STATUS_HI_MMRBC_SHIFT 0x5 1427 #define PCIX_STATUS_HI_MMRBC_4K 0x3 1428 #define PCIX_STATUS_HI_MMRBC_2K 0x2 1429 1430 /* The number of bits that we need to shift right to move the "pause" 1431 * bits from the EEPROM (bits 13:12) to the "pause" (bits 8:7) field 1432 * in the TXCW register 1433 */ 1434 #define PAUSE_SHIFT 5 1435 1436 /* The number of bits that we need to shift left to move the "SWDPIO" 1437 * bits from the EEPROM (bits 8:5) to the "SWDPIO" (bits 25:22) field 1438 * in the CTRL register 1439 */ 1440 #define SWDPIO_SHIFT 17 1441 1442 /* The number of bits that we need to shift left to move the "SWDPIO_EXT" 1443 * bits from the EEPROM word F (bits 7:4) to the bits 11:8 of The 1444 * Extended CTRL register. 1445 * in the CTRL register 1446 */ 1447 #define SWDPIO__EXT_SHIFT 4 1448 1449 /* The number of bits that we need to shift left to move the "ILOS" 1450 * bit from the EEPROM (bit 4) to the "ILOS" (bit 7) field 1451 * in the CTRL register 1452 */ 1453 #define ILOS_SHIFT 3 1454 1455 #define RECEIVE_BUFFER_ALIGN_SIZE (256) 1456 1457 /* The number of milliseconds we wait for auto-negotiation to complete */ 1458 #define LINK_UP_TIMEOUT 500 1459 1460 #define E1000_TX_BUFFER_SIZE ((uint32_t)1514) 1461 1462 /* The carrier extension symbol, as received by the NIC. */ 1463 #define CARRIER_EXTENSION 0x0F 1464 1465 /* TBI_ACCEPT macro definition: 1466 * 1467 * This macro requires: 1468 * adapter = a pointer to struct e1000_hw 1469 * status = the 8 bit status field of the RX descriptor with EOP set 1470 * error = the 8 bit error field of the RX descriptor with EOP set 1471 * length = the sum of all the length fields of the RX descriptors that 1472 * make up the current frame 1473 * last_byte = the last byte of the frame DMAed by the hardware 1474 * max_frame_length = the maximum frame length we want to accept. 1475 * min_frame_length = the minimum frame length we want to accept. 1476 * 1477 * This macro is a conditional that should be used in the interrupt 1478 * handler's Rx processing routine when RxErrors have been detected. 1479 * 1480 * Typical use: 1481 * ... 1482 * if (TBI_ACCEPT) { 1483 * accept_frame = TRUE; 1484 * e1000_tbi_adjust_stats(adapter, MacAddress); 1485 * frame_length--; 1486 * } else { 1487 * accept_frame = FALSE; 1488 * } 1489 * ... 1490 */ 1491 1492 #define TBI_ACCEPT(adapter, status, errors, length, last_byte) \ 1493 ((adapter)->tbi_compatibility_on && \ 1494 (((errors) & E1000_RXD_ERR_FRAME_ERR_MASK) == E1000_RXD_ERR_CE) && \ 1495 ((last_byte) == CARRIER_EXTENSION) && \ 1496 (((status) & E1000_RXD_STAT_VP) ? \ 1497 (((length) > ((adapter)->min_frame_size - VLAN_TAG_SIZE)) && \ 1498 ((length) <= ((adapter)->max_frame_size + 1))) : \ 1499 (((length) > (adapter)->min_frame_size) && \ 1500 ((length) <= ((adapter)->max_frame_size + VLAN_TAG_SIZE + 1))))) 1501 1502 /* Structures, enums, and macros for the PHY */ 1503 1504 /* Bit definitions for the Management Data IO (MDIO) and Management Data 1505 * Clock (MDC) pins in the Device Control Register. 1506 */ 1507 #define E1000_CTRL_PHY_RESET_DIR E1000_CTRL_SWDPIO0 1508 #define E1000_CTRL_PHY_RESET E1000_CTRL_SWDPIN0 1509 #define E1000_CTRL_MDIO_DIR E1000_CTRL_SWDPIO2 1510 #define E1000_CTRL_MDIO E1000_CTRL_SWDPIN2 1511 #define E1000_CTRL_MDC_DIR E1000_CTRL_SWDPIO3 1512 #define E1000_CTRL_MDC E1000_CTRL_SWDPIN3 1513 #define E1000_CTRL_PHY_RESET_DIR4 E1000_CTRL_EXT_SDP4_DIR 1514 #define E1000_CTRL_PHY_RESET4 E1000_CTRL_EXT_SDP4_DATA 1515 1516 /* PHY 1000 MII Register/Bit Definitions */ 1517 /* PHY Registers defined by IEEE */ 1518 #define PHY_CTRL 0x00 /* Control Register */ 1519 #define PHY_STATUS 0x01 /* Status Regiser */ 1520 #define PHY_ID1 0x02 /* Phy Id Reg (word 1) */ 1521 #define PHY_ID2 0x03 /* Phy Id Reg (word 2) */ 1522 #define PHY_AUTONEG_ADV 0x04 /* Autoneg Advertisement */ 1523 #define PHY_LP_ABILITY 0x05 /* Link Partner Ability (Base Page) */ 1524 #define PHY_AUTONEG_EXP 0x06 /* Autoneg Expansion Reg */ 1525 #define PHY_NEXT_PAGE_TX 0x07 /* Next Page TX */ 1526 #define PHY_LP_NEXT_PAGE 0x08 /* Link Partner Next Page */ 1527 #define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */ 1528 #define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */ 1529 #define PHY_EXT_STATUS 0x0F /* Extended Status Reg */ 1530 1531 /* M88E1000 Specific Registers */ 1532 #define M88E1000_PHY_SPEC_CTRL 0x10 /* PHY Specific Control Register */ 1533 #define M88E1000_PHY_SPEC_STATUS 0x11 /* PHY Specific Status Register */ 1534 #define M88E1000_INT_ENABLE 0x12 /* Interrupt Enable Register */ 1535 #define M88E1000_INT_STATUS 0x13 /* Interrupt Status Register */ 1536 #define M88E1000_EXT_PHY_SPEC_CTRL 0x14 /* Extended PHY Specific Control */ 1537 #define M88E1000_RX_ERR_CNTR 0x15 /* Receive Error Counter */ 1538 1539 #define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */ 1540 1541 /* IGP01E1000 specifics */ 1542 #define IGP01E1000_IEEE_REGS_PAGE 0x0000 1543 #define IGP01E1000_IEEE_RESTART_AUTONEG 0x3300 1544 #define IGP01E1000_IEEE_FORCE_GIGA 0x0140 1545 1546 /* IGP01E1000 Specific Registers */ 1547 #define IGP01E1000_PHY_PORT_CONFIG 0x10 /* PHY Specific Port Config Register */ 1548 #define IGP01E1000_PHY_PORT_STATUS 0x11 /* PHY Specific Status Register */ 1549 #define IGP01E1000_PHY_PORT_CTRL 0x12 /* PHY Specific Control Register */ 1550 #define IGP01E1000_PHY_LINK_HEALTH 0x13 /* PHY Link Health Register */ 1551 #define IGP01E1000_GMII_FIFO 0x14 /* GMII FIFO Register */ 1552 #define IGP01E1000_PHY_CHANNEL_QUALITY 0x15 /* PHY Channel Quality Register */ 1553 #define IGP02E1000_PHY_POWER_MGMT 0x19 1554 #define IGP01E1000_PHY_PAGE_SELECT 0x1F /* PHY Page Select Core Register */ 1555 1556 /* PHY Control Register */ 1557 #define MII_CR_SPEED_SELECT_MSB 0x0040 /* bits 6,13: 10=1000, 01=100, 00=10 */ 1558 #define MII_CR_COLL_TEST_ENABLE 0x0080 /* Collision test enable */ 1559 #define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */ 1560 #define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */ 1561 #define MII_CR_ISOLATE 0x0400 /* Isolate PHY from MII */ 1562 #define MII_CR_POWER_DOWN 0x0800 /* Power down */ 1563 #define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */ 1564 #define MII_CR_SPEED_SELECT_LSB 0x2000 /* bits 6,13: 10=1000, 01=100, 00=10 */ 1565 #define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */ 1566 #define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */ 1567 1568 /* PHY Status Register */ 1569 #define MII_SR_EXTENDED_CAPS 0x0001 /* Extended register capabilities */ 1570 #define MII_SR_JABBER_DETECT 0x0002 /* Jabber Detected */ 1571 #define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */ 1572 #define MII_SR_AUTONEG_CAPS 0x0008 /* Auto Neg Capable */ 1573 #define MII_SR_REMOTE_FAULT 0x0010 /* Remote Fault Detect */ 1574 #define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */ 1575 #define MII_SR_PREAMBLE_SUPPRESS 0x0040 /* Preamble may be suppressed */ 1576 #define MII_SR_EXTENDED_STATUS 0x0100 /* Ext. status info in Reg 0x0F */ 1577 #define MII_SR_100T2_HD_CAPS 0x0200 /* 100T2 Half Duplex Capable */ 1578 #define MII_SR_100T2_FD_CAPS 0x0400 /* 100T2 Full Duplex Capable */ 1579 #define MII_SR_10T_HD_CAPS 0x0800 /* 10T Half Duplex Capable */ 1580 #define MII_SR_10T_FD_CAPS 0x1000 /* 10T Full Duplex Capable */ 1581 #define MII_SR_100X_HD_CAPS 0x2000 /* 100X Half Duplex Capable */ 1582 #define MII_SR_100X_FD_CAPS 0x4000 /* 100X Full Duplex Capable */ 1583 #define MII_SR_100T4_CAPS 0x8000 /* 100T4 Capable */ 1584 1585 /* Autoneg Advertisement Register */ 1586 #define NWAY_AR_SELECTOR_FIELD 0x0001 /* indicates IEEE 802.3 CSMA/CD */ 1587 #define NWAY_AR_10T_HD_CAPS 0x0020 /* 10T Half Duplex Capable */ 1588 #define NWAY_AR_10T_FD_CAPS 0x0040 /* 10T Full Duplex Capable */ 1589 #define NWAY_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */ 1590 #define NWAY_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */ 1591 #define NWAY_AR_100T4_CAPS 0x0200 /* 100T4 Capable */ 1592 #define NWAY_AR_PAUSE 0x0400 /* Pause operation desired */ 1593 #define NWAY_AR_ASM_DIR 0x0800 /* Asymmetric Pause Direction bit */ 1594 #define NWAY_AR_REMOTE_FAULT 0x2000 /* Remote Fault detected */ 1595 #define NWAY_AR_NEXT_PAGE 0x8000 /* Next Page ability supported */ 1596 1597 /* Link Partner Ability Register (Base Page) */ 1598 #define NWAY_LPAR_SELECTOR_FIELD 0x0000 /* LP protocol selector field */ 1599 #define NWAY_LPAR_10T_HD_CAPS 0x0020 /* LP is 10T Half Duplex Capable */ 1600 #define NWAY_LPAR_10T_FD_CAPS 0x0040 /* LP is 10T Full Duplex Capable */ 1601 #define NWAY_LPAR_100TX_HD_CAPS 0x0080 /* LP is 100TX Half Duplex Capable */ 1602 #define NWAY_LPAR_100TX_FD_CAPS 0x0100 /* LP is 100TX Full Duplex Capable */ 1603 #define NWAY_LPAR_100T4_CAPS 0x0200 /* LP is 100T4 Capable */ 1604 #define NWAY_LPAR_PAUSE 0x0400 /* LP Pause operation desired */ 1605 #define NWAY_LPAR_ASM_DIR 0x0800 /* LP Asymmetric Pause Direction bit */ 1606 #define NWAY_LPAR_REMOTE_FAULT 0x2000 /* LP has detected Remote Fault */ 1607 #define NWAY_LPAR_ACKNOWLEDGE 0x4000 /* LP has rx'd link code word */ 1608 #define NWAY_LPAR_NEXT_PAGE 0x8000 /* Next Page ability supported */ 1609 1610 /* Autoneg Expansion Register */ 1611 #define NWAY_ER_LP_NWAY_CAPS 0x0001 /* LP has Auto Neg Capability */ 1612 #define NWAY_ER_PAGE_RXD 0x0002 /* LP is 10T Half Duplex Capable */ 1613 #define NWAY_ER_NEXT_PAGE_CAPS 0x0004 /* LP is 10T Full Duplex Capable */ 1614 #define NWAY_ER_LP_NEXT_PAGE_CAPS 0x0008 /* LP is 100TX Half Duplex Capable */ 1615 #define NWAY_ER_PAR_DETECT_FAULT 0x0100 /* LP is 100TX Full Duplex Capable */ 1616 1617 /* Next Page TX Register */ 1618 #define NPTX_MSG_CODE_FIELD 0x0001 /* NP msg code or unformatted data */ 1619 #define NPTX_TOGGLE 0x0800 /* Toggles between exchanges 1620 * of different NP 1621 */ 1622 #define NPTX_ACKNOWLDGE2 0x1000 /* 1 = will comply with msg 1623 * 0 = cannot comply with msg 1624 */ 1625 #define NPTX_MSG_PAGE 0x2000 /* formatted(1)/unformatted(0) pg */ 1626 #define NPTX_NEXT_PAGE 0x8000 /* 1 = addition NP will follow 1627 * 0 = sending last NP 1628 */ 1629 1630 /* Link Partner Next Page Register */ 1631 #define LP_RNPR_MSG_CODE_FIELD 0x0001 /* NP msg code or unformatted data */ 1632 #define LP_RNPR_TOGGLE 0x0800 /* Toggles between exchanges 1633 * of different NP 1634 */ 1635 #define LP_RNPR_ACKNOWLDGE2 0x1000 /* 1 = will comply with msg 1636 * 0 = cannot comply with msg 1637 */ 1638 #define LP_RNPR_MSG_PAGE 0x2000 /* formatted(1)/unformatted(0) pg */ 1639 #define LP_RNPR_ACKNOWLDGE 0x4000 /* 1 = ACK / 0 = NO ACK */ 1640 #define LP_RNPR_NEXT_PAGE 0x8000 /* 1 = addition NP will follow 1641 * 0 = sending last NP 1642 */ 1643 1644 /* 1000BASE-T Control Register */ 1645 #define CR_1000T_ASYM_PAUSE 0x0080 /* Advertise asymmetric pause bit */ 1646 #define CR_1000T_HD_CAPS 0x0100 /* Advertise 1000T HD capability */ 1647 #define CR_1000T_FD_CAPS 0x0200 /* Advertise 1000T FD capability */ 1648 #define CR_1000T_REPEATER_DTE 0x0400 /* 1=Repeater/switch device port */ 1649 /* 0=DTE device */ 1650 #define CR_1000T_MS_VALUE 0x0800 /* 1=Configure PHY as Master */ 1651 /* 0=Configure PHY as Slave */ 1652 #define CR_1000T_MS_ENABLE 0x1000 /* 1=Master/Slave manual config value */ 1653 /* 0=Automatic Master/Slave config */ 1654 #define CR_1000T_TEST_MODE_NORMAL 0x0000 /* Normal Operation */ 1655 #define CR_1000T_TEST_MODE_1 0x2000 /* Transmit Waveform test */ 1656 #define CR_1000T_TEST_MODE_2 0x4000 /* Master Transmit Jitter test */ 1657 #define CR_1000T_TEST_MODE_3 0x6000 /* Slave Transmit Jitter test */ 1658 #define CR_1000T_TEST_MODE_4 0x8000 /* Transmitter Distortion test */ 1659 1660 /* 1000BASE-T Status Register */ 1661 #define SR_1000T_IDLE_ERROR_CNT 0x00FF /* Num idle errors since last read */ 1662 #define SR_1000T_ASYM_PAUSE_DIR 0x0100 /* LP asymmetric pause direction bit */ 1663 #define SR_1000T_LP_HD_CAPS 0x0400 /* LP is 1000T HD capable */ 1664 #define SR_1000T_LP_FD_CAPS 0x0800 /* LP is 1000T FD capable */ 1665 #define SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */ 1666 #define SR_1000T_LOCAL_RX_STATUS 0x2000 /* Local receiver OK */ 1667 #define SR_1000T_MS_CONFIG_RES 0x4000 /* 1=Local TX is Master, 0=Slave */ 1668 #define SR_1000T_MS_CONFIG_FAULT 0x8000 /* Master/Slave config fault */ 1669 #define SR_1000T_REMOTE_RX_STATUS_SHIFT 12 1670 #define SR_1000T_LOCAL_RX_STATUS_SHIFT 13 1671 1672 /* Extended Status Register */ 1673 #define IEEE_ESR_1000T_HD_CAPS 0x1000 /* 1000T HD capable */ 1674 #define IEEE_ESR_1000T_FD_CAPS 0x2000 /* 1000T FD capable */ 1675 #define IEEE_ESR_1000X_HD_CAPS 0x4000 /* 1000X HD capable */ 1676 #define IEEE_ESR_1000X_FD_CAPS 0x8000 /* 1000X FD capable */ 1677 1678 #define PHY_TX_POLARITY_MASK 0x0100 /* register 10h bit 8 (polarity bit) */ 1679 #define PHY_TX_NORMAL_POLARITY 0 /* register 10h bit 8 (normal polarity) */ 1680 1681 #define AUTO_POLARITY_DISABLE 0x0010 /* register 11h bit 4 */ 1682 /* (0=enable, 1=disable) */ 1683 1684 /* M88E1000 PHY Specific Control Register */ 1685 #define M88E1000_PSCR_JABBER_DISABLE 0x0001 /* 1=Jabber Function disabled */ 1686 #define M88E1000_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reversal enabled */ 1687 #define M88E1000_PSCR_SQE_TEST 0x0004 /* 1=SQE Test enabled */ 1688 #define M88E1000_PSCR_CLK125_DISABLE 0x0010 /* 1=CLK125 low, 1689 * 0=CLK125 toggling 1690 */ 1691 #define M88E1000_PSCR_MDI_MANUAL_MODE 0x0000 /* MDI Crossover Mode bits 6:5 */ 1692 /* Manual MDI configuration */ 1693 #define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020 /* Manual MDIX configuration */ 1694 #define M88E1000_PSCR_AUTO_X_1000T 0x0040 /* 1000BASE-T: Auto crossover, 1695 * 100BASE-TX/10BASE-T: 1696 * MDI Mode 1697 */ 1698 #define M88E1000_PSCR_AUTO_X_MODE 0x0060 /* Auto crossover enabled 1699 * all speeds. 1700 */ 1701 #define M88E1000_PSCR_10BT_EXT_DIST_ENABLE 0x0080 1702 /* 1=Enable Extended 10BASE-T distance 1703 * (Lower 10BASE-T RX Threshold) 1704 * 0=Normal 10BASE-T RX Threshold */ 1705 #define M88E1000_PSCR_MII_5BIT_ENABLE 0x0100 1706 /* 1=5-Bit interface in 100BASE-TX 1707 * 0=MII interface in 100BASE-TX */ 1708 #define M88E1000_PSCR_SCRAMBLER_DISABLE 0x0200 /* 1=Scrambler disable */ 1709 #define M88E1000_PSCR_FORCE_LINK_GOOD 0x0400 /* 1=Force link good */ 1710 #define M88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Transmit */ 1711 1712 #define M88E1000_PSCR_POLARITY_REVERSAL_SHIFT 1 1713 #define M88E1000_PSCR_AUTO_X_MODE_SHIFT 5 1714 #define M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT 7 1715 1716 /* M88E1000 PHY Specific Status Register */ 1717 #define M88E1000_PSSR_JABBER 0x0001 /* 1=Jabber */ 1718 #define M88E1000_PSSR_REV_POLARITY 0x0002 /* 1=Polarity reversed */ 1719 #define M88E1000_PSSR_MDIX 0x0040 /* 1=MDIX; 0=MDI */ 1720 #define M88E1000_PSSR_CABLE_LENGTH 0x0380 /* 0=<50M;1=50-80M;2=80-110M; 1721 * 3=110-140M;4=>140M */ 1722 #define M88E1000_PSSR_LINK 0x0400 /* 1=Link up, 0=Link down */ 1723 #define M88E1000_PSSR_SPD_DPLX_RESOLVED 0x0800 /* 1=Speed & Duplex resolved */ 1724 #define M88E1000_PSSR_PAGE_RCVD 0x1000 /* 1=Page received */ 1725 #define M88E1000_PSSR_DPLX 0x2000 /* 1=Duplex 0=Half Duplex */ 1726 #define M88E1000_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */ 1727 #define M88E1000_PSSR_10MBS 0x0000 /* 00=10Mbs */ 1728 #define M88E1000_PSSR_100MBS 0x4000 /* 01=100Mbs */ 1729 #define M88E1000_PSSR_1000MBS 0x8000 /* 10=1000Mbs */ 1730 1731 #define M88E1000_PSSR_REV_POLARITY_SHIFT 1 1732 #define M88E1000_PSSR_MDIX_SHIFT 6 1733 #define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7 1734 1735 /* M88E1000 Extended PHY Specific Control Register */ 1736 #define M88E1000_EPSCR_FIBER_LOOPBACK 0x4000 /* 1=Fiber loopback */ 1737 #define M88E1000_EPSCR_DOWN_NO_IDLE 0x8000 /* 1=Lost lock detect enabled. 1738 * Will assert lost lock and bring 1739 * link down if idle not seen 1740 * within 1ms in 1000BASE-T 1741 */ 1742 /* Number of times we will attempt to autonegotiate before downshifting if we 1743 * are the master */ 1744 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00 1745 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X 0x0000 1746 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_2X 0x0400 1747 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_3X 0x0800 1748 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_4X 0x0C00 1749 /* Number of times we will attempt to autonegotiate before downshifting if we 1750 * are the slave */ 1751 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK 0x0300 1752 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_DIS 0x0000 1753 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X 0x0100 1754 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_2X 0x0200 1755 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_3X 0x0300 1756 #define M88E1000_EPSCR_TX_CLK_2_5 0x0060 /* 2.5 MHz TX_CLK */ 1757 #define M88E1000_EPSCR_TX_CLK_25 0x0070 /* 25 MHz TX_CLK */ 1758 #define M88E1000_EPSCR_TX_CLK_0 0x0000 /* NO TX_CLK */ 1759 1760 /* Bit definitions for valid PHY IDs. */ 1761 #define M88E1000_E_PHY_ID 0x01410C50 1762 #define M88E1000_I_PHY_ID 0x01410C30 1763 #define M88E1011_I_PHY_ID 0x01410C20 1764 #define M88E1000_12_PHY_ID M88E1000_E_PHY_ID 1765 #define M88E1000_14_PHY_ID M88E1000_E_PHY_ID 1766 #define IGP01E1000_I_PHY_ID 0x02A80380 1767 1768 /* Miscellaneous PHY bit definitions. */ 1769 #define PHY_PREAMBLE 0xFFFFFFFF 1770 #define PHY_SOF 0x01 1771 #define PHY_OP_READ 0x02 1772 #define PHY_OP_WRITE 0x01 1773 #define PHY_TURNAROUND 0x02 1774 #define PHY_PREAMBLE_SIZE 32 1775 #define MII_CR_SPEED_1000 0x0040 1776 #define MII_CR_SPEED_100 0x2000 1777 #define MII_CR_SPEED_10 0x0000 1778 #define E1000_PHY_ADDRESS 0x01 1779 #define PHY_AUTO_NEG_TIME 45 /* 4.5 Seconds */ 1780 #define PHY_FORCE_TIME 20 /* 2.0 Seconds */ 1781 #define PHY_REVISION_MASK 0xFFFFFFF0 1782 #define DEVICE_SPEED_MASK 0x00000300 /* Device Ctrl Reg Speed Mask */ 1783 #define REG4_SPEED_MASK 0x01E0 1784 #define REG9_SPEED_MASK 0x0300 1785 #define ADVERTISE_10_HALF 0x0001 1786 #define ADVERTISE_10_FULL 0x0002 1787 #define ADVERTISE_100_HALF 0x0004 1788 #define ADVERTISE_100_FULL 0x0008 1789 #define ADVERTISE_1000_HALF 0x0010 1790 #define ADVERTISE_1000_FULL 0x0020 1791 #define AUTONEG_ADVERTISE_SPEED_DEFAULT 0x002F /* Everything but 1000-Half */ 1792 1793 #endif /* _E1000_HW_H_ */ 1794