1 /************************************************************************** 2 Intel Pro 1000 for ppcboot/das-u-boot 3 Drivers are port from Intel's Linux driver e1000-4.3.15 4 and from Etherboot pro 1000 driver by mrakes at vivato dot net 5 tested on both gig copper and gig fiber boards 6 ***************************************************************************/ 7 /******************************************************************************* 8 9 10 Copyright(c) 1999 - 2002 Intel Corporation. All rights reserved. 11 12 * SPDX-License-Identifier: GPL-2.0+ 13 14 Contact Information: 15 Linux NICS <linux.nics@intel.com> 16 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 17 18 *******************************************************************************/ 19 /* 20 * Copyright (C) Archway Digital Solutions. 21 * 22 * written by Chrsitopher Li <cli at arcyway dot com> or <chrisl at gnuchina dot org> 23 * 2/9/2002 24 * 25 * Copyright (C) Linux Networx. 26 * Massive upgrade to work with the new intel gigabit NICs. 27 * <ebiederman at lnxi dot com> 28 * 29 * Copyright 2011 Freescale Semiconductor, Inc. 30 */ 31 32 #include "e1000.h" 33 34 #define TOUT_LOOP 100000 35 36 #define virt_to_bus(devno, v) pci_virt_to_mem(devno, (void *) (v)) 37 #define bus_to_phys(devno, a) pci_mem_to_phys(devno, a) 38 39 #define E1000_DEFAULT_PCI_PBA 0x00000030 40 #define E1000_DEFAULT_PCIE_PBA 0x000a0026 41 42 /* NIC specific static variables go here */ 43 44 static char tx_pool[128 + 16]; 45 static char rx_pool[128 + 16]; 46 static char packet[2096]; 47 48 static struct e1000_tx_desc *tx_base; 49 static struct e1000_rx_desc *rx_base; 50 51 static int tx_tail; 52 static int rx_tail, rx_last; 53 54 static struct pci_device_id e1000_supported[] = { 55 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82542}, 56 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82543GC_FIBER}, 57 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82543GC_COPPER}, 58 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544EI_COPPER}, 59 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544EI_FIBER}, 60 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544GC_COPPER}, 61 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544GC_LOM}, 62 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82540EM}, 63 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545EM_COPPER}, 64 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545GM_COPPER}, 65 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_COPPER}, 66 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545EM_FIBER}, 67 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_FIBER}, 68 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546GB_COPPER}, 69 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82540EM_LOM}, 70 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82541ER}, 71 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82541GI_LF}, 72 /* E1000 PCIe card */ 73 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_COPPER}, 74 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_FIBER }, 75 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES }, 76 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_COPPER}, 77 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571PT_QUAD_COPPER}, 78 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_FIBER}, 79 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_COPPER_LOWPROFILE}, 80 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES_DUAL}, 81 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES_QUAD}, 82 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_COPPER}, 83 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_FIBER}, 84 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_SERDES}, 85 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI}, 86 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573E}, 87 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573E_IAMT}, 88 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573L}, 89 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82574L}, 90 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546GB_QUAD_COPPER_KSP3}, 91 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_COPPER_DPT}, 92 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_SERDES_DPT}, 93 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_COPPER_SPT}, 94 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_SERDES_SPT}, 95 {} 96 }; 97 98 /* Function forward declarations */ 99 static int e1000_setup_link(struct eth_device *nic); 100 static int e1000_setup_fiber_link(struct eth_device *nic); 101 static int e1000_setup_copper_link(struct eth_device *nic); 102 static int e1000_phy_setup_autoneg(struct e1000_hw *hw); 103 static void e1000_config_collision_dist(struct e1000_hw *hw); 104 static int e1000_config_mac_to_phy(struct e1000_hw *hw); 105 static int e1000_config_fc_after_link_up(struct e1000_hw *hw); 106 static int e1000_check_for_link(struct eth_device *nic); 107 static int e1000_wait_autoneg(struct e1000_hw *hw); 108 static int e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t * speed, 109 uint16_t * duplex); 110 static int e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, 111 uint16_t * phy_data); 112 static int e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, 113 uint16_t phy_data); 114 static int32_t e1000_phy_hw_reset(struct e1000_hw *hw); 115 static int e1000_phy_reset(struct e1000_hw *hw); 116 static int e1000_detect_gig_phy(struct e1000_hw *hw); 117 static void e1000_set_media_type(struct e1000_hw *hw); 118 119 static int32_t e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask); 120 static int32_t e1000_check_phy_reset_block(struct e1000_hw *hw); 121 122 #ifndef CONFIG_E1000_NO_NVM 123 static void e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw); 124 static int32_t e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset, 125 uint16_t words, 126 uint16_t *data); 127 /****************************************************************************** 128 * Raises the EEPROM's clock input. 129 * 130 * hw - Struct containing variables accessed by shared code 131 * eecd - EECD's current value 132 *****************************************************************************/ 133 void e1000_raise_ee_clk(struct e1000_hw *hw, uint32_t * eecd) 134 { 135 /* Raise the clock input to the EEPROM (by setting the SK bit), and then 136 * wait 50 microseconds. 137 */ 138 *eecd = *eecd | E1000_EECD_SK; 139 E1000_WRITE_REG(hw, EECD, *eecd); 140 E1000_WRITE_FLUSH(hw); 141 udelay(50); 142 } 143 144 /****************************************************************************** 145 * Lowers the EEPROM's clock input. 146 * 147 * hw - Struct containing variables accessed by shared code 148 * eecd - EECD's current value 149 *****************************************************************************/ 150 void e1000_lower_ee_clk(struct e1000_hw *hw, uint32_t * eecd) 151 { 152 /* Lower the clock input to the EEPROM (by clearing the SK bit), and then 153 * wait 50 microseconds. 154 */ 155 *eecd = *eecd & ~E1000_EECD_SK; 156 E1000_WRITE_REG(hw, EECD, *eecd); 157 E1000_WRITE_FLUSH(hw); 158 udelay(50); 159 } 160 161 /****************************************************************************** 162 * Shift data bits out to the EEPROM. 163 * 164 * hw - Struct containing variables accessed by shared code 165 * data - data to send to the EEPROM 166 * count - number of bits to shift out 167 *****************************************************************************/ 168 static void 169 e1000_shift_out_ee_bits(struct e1000_hw *hw, uint16_t data, uint16_t count) 170 { 171 uint32_t eecd; 172 uint32_t mask; 173 174 /* We need to shift "count" bits out to the EEPROM. So, value in the 175 * "data" parameter will be shifted out to the EEPROM one bit at a time. 176 * In order to do this, "data" must be broken down into bits. 177 */ 178 mask = 0x01 << (count - 1); 179 eecd = E1000_READ_REG(hw, EECD); 180 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI); 181 do { 182 /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1", 183 * and then raising and then lowering the clock (the SK bit controls 184 * the clock input to the EEPROM). A "0" is shifted out to the EEPROM 185 * by setting "DI" to "0" and then raising and then lowering the clock. 186 */ 187 eecd &= ~E1000_EECD_DI; 188 189 if (data & mask) 190 eecd |= E1000_EECD_DI; 191 192 E1000_WRITE_REG(hw, EECD, eecd); 193 E1000_WRITE_FLUSH(hw); 194 195 udelay(50); 196 197 e1000_raise_ee_clk(hw, &eecd); 198 e1000_lower_ee_clk(hw, &eecd); 199 200 mask = mask >> 1; 201 202 } while (mask); 203 204 /* We leave the "DI" bit set to "0" when we leave this routine. */ 205 eecd &= ~E1000_EECD_DI; 206 E1000_WRITE_REG(hw, EECD, eecd); 207 } 208 209 /****************************************************************************** 210 * Shift data bits in from the EEPROM 211 * 212 * hw - Struct containing variables accessed by shared code 213 *****************************************************************************/ 214 static uint16_t 215 e1000_shift_in_ee_bits(struct e1000_hw *hw, uint16_t count) 216 { 217 uint32_t eecd; 218 uint32_t i; 219 uint16_t data; 220 221 /* In order to read a register from the EEPROM, we need to shift 'count' 222 * bits in from the EEPROM. Bits are "shifted in" by raising the clock 223 * input to the EEPROM (setting the SK bit), and then reading the 224 * value of the "DO" bit. During this "shifting in" process the 225 * "DI" bit should always be clear. 226 */ 227 228 eecd = E1000_READ_REG(hw, EECD); 229 230 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI); 231 data = 0; 232 233 for (i = 0; i < count; i++) { 234 data = data << 1; 235 e1000_raise_ee_clk(hw, &eecd); 236 237 eecd = E1000_READ_REG(hw, EECD); 238 239 eecd &= ~(E1000_EECD_DI); 240 if (eecd & E1000_EECD_DO) 241 data |= 1; 242 243 e1000_lower_ee_clk(hw, &eecd); 244 } 245 246 return data; 247 } 248 249 /****************************************************************************** 250 * Returns EEPROM to a "standby" state 251 * 252 * hw - Struct containing variables accessed by shared code 253 *****************************************************************************/ 254 void e1000_standby_eeprom(struct e1000_hw *hw) 255 { 256 struct e1000_eeprom_info *eeprom = &hw->eeprom; 257 uint32_t eecd; 258 259 eecd = E1000_READ_REG(hw, EECD); 260 261 if (eeprom->type == e1000_eeprom_microwire) { 262 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); 263 E1000_WRITE_REG(hw, EECD, eecd); 264 E1000_WRITE_FLUSH(hw); 265 udelay(eeprom->delay_usec); 266 267 /* Clock high */ 268 eecd |= E1000_EECD_SK; 269 E1000_WRITE_REG(hw, EECD, eecd); 270 E1000_WRITE_FLUSH(hw); 271 udelay(eeprom->delay_usec); 272 273 /* Select EEPROM */ 274 eecd |= E1000_EECD_CS; 275 E1000_WRITE_REG(hw, EECD, eecd); 276 E1000_WRITE_FLUSH(hw); 277 udelay(eeprom->delay_usec); 278 279 /* Clock low */ 280 eecd &= ~E1000_EECD_SK; 281 E1000_WRITE_REG(hw, EECD, eecd); 282 E1000_WRITE_FLUSH(hw); 283 udelay(eeprom->delay_usec); 284 } else if (eeprom->type == e1000_eeprom_spi) { 285 /* Toggle CS to flush commands */ 286 eecd |= E1000_EECD_CS; 287 E1000_WRITE_REG(hw, EECD, eecd); 288 E1000_WRITE_FLUSH(hw); 289 udelay(eeprom->delay_usec); 290 eecd &= ~E1000_EECD_CS; 291 E1000_WRITE_REG(hw, EECD, eecd); 292 E1000_WRITE_FLUSH(hw); 293 udelay(eeprom->delay_usec); 294 } 295 } 296 297 /*************************************************************************** 298 * Description: Determines if the onboard NVM is FLASH or EEPROM. 299 * 300 * hw - Struct containing variables accessed by shared code 301 ****************************************************************************/ 302 static bool e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw) 303 { 304 uint32_t eecd = 0; 305 306 DEBUGFUNC(); 307 308 if (hw->mac_type == e1000_ich8lan) 309 return false; 310 311 if (hw->mac_type == e1000_82573 || hw->mac_type == e1000_82574) { 312 eecd = E1000_READ_REG(hw, EECD); 313 314 /* Isolate bits 15 & 16 */ 315 eecd = ((eecd >> 15) & 0x03); 316 317 /* If both bits are set, device is Flash type */ 318 if (eecd == 0x03) 319 return false; 320 } 321 return true; 322 } 323 324 /****************************************************************************** 325 * Prepares EEPROM for access 326 * 327 * hw - Struct containing variables accessed by shared code 328 * 329 * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This 330 * function should be called before issuing a command to the EEPROM. 331 *****************************************************************************/ 332 int32_t e1000_acquire_eeprom(struct e1000_hw *hw) 333 { 334 struct e1000_eeprom_info *eeprom = &hw->eeprom; 335 uint32_t eecd, i = 0; 336 337 DEBUGFUNC(); 338 339 if (e1000_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM)) 340 return -E1000_ERR_SWFW_SYNC; 341 eecd = E1000_READ_REG(hw, EECD); 342 343 if (hw->mac_type != e1000_82573 || hw->mac_type != e1000_82574) { 344 /* Request EEPROM Access */ 345 if (hw->mac_type > e1000_82544) { 346 eecd |= E1000_EECD_REQ; 347 E1000_WRITE_REG(hw, EECD, eecd); 348 eecd = E1000_READ_REG(hw, EECD); 349 while ((!(eecd & E1000_EECD_GNT)) && 350 (i < E1000_EEPROM_GRANT_ATTEMPTS)) { 351 i++; 352 udelay(5); 353 eecd = E1000_READ_REG(hw, EECD); 354 } 355 if (!(eecd & E1000_EECD_GNT)) { 356 eecd &= ~E1000_EECD_REQ; 357 E1000_WRITE_REG(hw, EECD, eecd); 358 DEBUGOUT("Could not acquire EEPROM grant\n"); 359 return -E1000_ERR_EEPROM; 360 } 361 } 362 } 363 364 /* Setup EEPROM for Read/Write */ 365 366 if (eeprom->type == e1000_eeprom_microwire) { 367 /* Clear SK and DI */ 368 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK); 369 E1000_WRITE_REG(hw, EECD, eecd); 370 371 /* Set CS */ 372 eecd |= E1000_EECD_CS; 373 E1000_WRITE_REG(hw, EECD, eecd); 374 } else if (eeprom->type == e1000_eeprom_spi) { 375 /* Clear SK and CS */ 376 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); 377 E1000_WRITE_REG(hw, EECD, eecd); 378 udelay(1); 379 } 380 381 return E1000_SUCCESS; 382 } 383 384 /****************************************************************************** 385 * Sets up eeprom variables in the hw struct. Must be called after mac_type 386 * is configured. Additionally, if this is ICH8, the flash controller GbE 387 * registers must be mapped, or this will crash. 388 * 389 * hw - Struct containing variables accessed by shared code 390 *****************************************************************************/ 391 static int32_t e1000_init_eeprom_params(struct e1000_hw *hw) 392 { 393 struct e1000_eeprom_info *eeprom = &hw->eeprom; 394 uint32_t eecd = E1000_READ_REG(hw, EECD); 395 int32_t ret_val = E1000_SUCCESS; 396 uint16_t eeprom_size; 397 398 DEBUGFUNC(); 399 400 switch (hw->mac_type) { 401 case e1000_82542_rev2_0: 402 case e1000_82542_rev2_1: 403 case e1000_82543: 404 case e1000_82544: 405 eeprom->type = e1000_eeprom_microwire; 406 eeprom->word_size = 64; 407 eeprom->opcode_bits = 3; 408 eeprom->address_bits = 6; 409 eeprom->delay_usec = 50; 410 eeprom->use_eerd = false; 411 eeprom->use_eewr = false; 412 break; 413 case e1000_82540: 414 case e1000_82545: 415 case e1000_82545_rev_3: 416 case e1000_82546: 417 case e1000_82546_rev_3: 418 eeprom->type = e1000_eeprom_microwire; 419 eeprom->opcode_bits = 3; 420 eeprom->delay_usec = 50; 421 if (eecd & E1000_EECD_SIZE) { 422 eeprom->word_size = 256; 423 eeprom->address_bits = 8; 424 } else { 425 eeprom->word_size = 64; 426 eeprom->address_bits = 6; 427 } 428 eeprom->use_eerd = false; 429 eeprom->use_eewr = false; 430 break; 431 case e1000_82541: 432 case e1000_82541_rev_2: 433 case e1000_82547: 434 case e1000_82547_rev_2: 435 if (eecd & E1000_EECD_TYPE) { 436 eeprom->type = e1000_eeprom_spi; 437 eeprom->opcode_bits = 8; 438 eeprom->delay_usec = 1; 439 if (eecd & E1000_EECD_ADDR_BITS) { 440 eeprom->page_size = 32; 441 eeprom->address_bits = 16; 442 } else { 443 eeprom->page_size = 8; 444 eeprom->address_bits = 8; 445 } 446 } else { 447 eeprom->type = e1000_eeprom_microwire; 448 eeprom->opcode_bits = 3; 449 eeprom->delay_usec = 50; 450 if (eecd & E1000_EECD_ADDR_BITS) { 451 eeprom->word_size = 256; 452 eeprom->address_bits = 8; 453 } else { 454 eeprom->word_size = 64; 455 eeprom->address_bits = 6; 456 } 457 } 458 eeprom->use_eerd = false; 459 eeprom->use_eewr = false; 460 break; 461 case e1000_82571: 462 case e1000_82572: 463 eeprom->type = e1000_eeprom_spi; 464 eeprom->opcode_bits = 8; 465 eeprom->delay_usec = 1; 466 if (eecd & E1000_EECD_ADDR_BITS) { 467 eeprom->page_size = 32; 468 eeprom->address_bits = 16; 469 } else { 470 eeprom->page_size = 8; 471 eeprom->address_bits = 8; 472 } 473 eeprom->use_eerd = false; 474 eeprom->use_eewr = false; 475 break; 476 case e1000_82573: 477 case e1000_82574: 478 eeprom->type = e1000_eeprom_spi; 479 eeprom->opcode_bits = 8; 480 eeprom->delay_usec = 1; 481 if (eecd & E1000_EECD_ADDR_BITS) { 482 eeprom->page_size = 32; 483 eeprom->address_bits = 16; 484 } else { 485 eeprom->page_size = 8; 486 eeprom->address_bits = 8; 487 } 488 eeprom->use_eerd = true; 489 eeprom->use_eewr = true; 490 if (e1000_is_onboard_nvm_eeprom(hw) == false) { 491 eeprom->type = e1000_eeprom_flash; 492 eeprom->word_size = 2048; 493 494 /* Ensure that the Autonomous FLASH update bit is cleared due to 495 * Flash update issue on parts which use a FLASH for NVM. */ 496 eecd &= ~E1000_EECD_AUPDEN; 497 E1000_WRITE_REG(hw, EECD, eecd); 498 } 499 break; 500 case e1000_80003es2lan: 501 eeprom->type = e1000_eeprom_spi; 502 eeprom->opcode_bits = 8; 503 eeprom->delay_usec = 1; 504 if (eecd & E1000_EECD_ADDR_BITS) { 505 eeprom->page_size = 32; 506 eeprom->address_bits = 16; 507 } else { 508 eeprom->page_size = 8; 509 eeprom->address_bits = 8; 510 } 511 eeprom->use_eerd = true; 512 eeprom->use_eewr = false; 513 break; 514 515 /* ich8lan does not support currently. if needed, please 516 * add corresponding code and functions. 517 */ 518 #if 0 519 case e1000_ich8lan: 520 { 521 int32_t i = 0; 522 523 eeprom->type = e1000_eeprom_ich8; 524 eeprom->use_eerd = false; 525 eeprom->use_eewr = false; 526 eeprom->word_size = E1000_SHADOW_RAM_WORDS; 527 uint32_t flash_size = E1000_READ_ICH_FLASH_REG(hw, 528 ICH_FLASH_GFPREG); 529 /* Zero the shadow RAM structure. But don't load it from NVM 530 * so as to save time for driver init */ 531 if (hw->eeprom_shadow_ram != NULL) { 532 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) { 533 hw->eeprom_shadow_ram[i].modified = false; 534 hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF; 535 } 536 } 537 538 hw->flash_base_addr = (flash_size & ICH_GFPREG_BASE_MASK) * 539 ICH_FLASH_SECTOR_SIZE; 540 541 hw->flash_bank_size = ((flash_size >> 16) 542 & ICH_GFPREG_BASE_MASK) + 1; 543 hw->flash_bank_size -= (flash_size & ICH_GFPREG_BASE_MASK); 544 545 hw->flash_bank_size *= ICH_FLASH_SECTOR_SIZE; 546 547 hw->flash_bank_size /= 2 * sizeof(uint16_t); 548 break; 549 } 550 #endif 551 default: 552 break; 553 } 554 555 if (eeprom->type == e1000_eeprom_spi) { 556 /* eeprom_size will be an enum [0..8] that maps 557 * to eeprom sizes 128B to 558 * 32KB (incremented by powers of 2). 559 */ 560 if (hw->mac_type <= e1000_82547_rev_2) { 561 /* Set to default value for initial eeprom read. */ 562 eeprom->word_size = 64; 563 ret_val = e1000_read_eeprom(hw, EEPROM_CFG, 1, 564 &eeprom_size); 565 if (ret_val) 566 return ret_val; 567 eeprom_size = (eeprom_size & EEPROM_SIZE_MASK) 568 >> EEPROM_SIZE_SHIFT; 569 /* 256B eeprom size was not supported in earlier 570 * hardware, so we bump eeprom_size up one to 571 * ensure that "1" (which maps to 256B) is never 572 * the result used in the shifting logic below. */ 573 if (eeprom_size) 574 eeprom_size++; 575 } else { 576 eeprom_size = (uint16_t)((eecd & 577 E1000_EECD_SIZE_EX_MASK) >> 578 E1000_EECD_SIZE_EX_SHIFT); 579 } 580 581 eeprom->word_size = 1 << (eeprom_size + EEPROM_WORD_SIZE_SHIFT); 582 } 583 return ret_val; 584 } 585 586 /****************************************************************************** 587 * Polls the status bit (bit 1) of the EERD to determine when the read is done. 588 * 589 * hw - Struct containing variables accessed by shared code 590 *****************************************************************************/ 591 static int32_t 592 e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd) 593 { 594 uint32_t attempts = 100000; 595 uint32_t i, reg = 0; 596 int32_t done = E1000_ERR_EEPROM; 597 598 for (i = 0; i < attempts; i++) { 599 if (eerd == E1000_EEPROM_POLL_READ) 600 reg = E1000_READ_REG(hw, EERD); 601 else 602 reg = E1000_READ_REG(hw, EEWR); 603 604 if (reg & E1000_EEPROM_RW_REG_DONE) { 605 done = E1000_SUCCESS; 606 break; 607 } 608 udelay(5); 609 } 610 611 return done; 612 } 613 614 /****************************************************************************** 615 * Reads a 16 bit word from the EEPROM using the EERD register. 616 * 617 * hw - Struct containing variables accessed by shared code 618 * offset - offset of word in the EEPROM to read 619 * data - word read from the EEPROM 620 * words - number of words to read 621 *****************************************************************************/ 622 static int32_t 623 e1000_read_eeprom_eerd(struct e1000_hw *hw, 624 uint16_t offset, 625 uint16_t words, 626 uint16_t *data) 627 { 628 uint32_t i, eerd = 0; 629 int32_t error = 0; 630 631 for (i = 0; i < words; i++) { 632 eerd = ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) + 633 E1000_EEPROM_RW_REG_START; 634 635 E1000_WRITE_REG(hw, EERD, eerd); 636 error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_READ); 637 638 if (error) 639 break; 640 data[i] = (E1000_READ_REG(hw, EERD) >> 641 E1000_EEPROM_RW_REG_DATA); 642 643 } 644 645 return error; 646 } 647 648 void e1000_release_eeprom(struct e1000_hw *hw) 649 { 650 uint32_t eecd; 651 652 DEBUGFUNC(); 653 654 eecd = E1000_READ_REG(hw, EECD); 655 656 if (hw->eeprom.type == e1000_eeprom_spi) { 657 eecd |= E1000_EECD_CS; /* Pull CS high */ 658 eecd &= ~E1000_EECD_SK; /* Lower SCK */ 659 660 E1000_WRITE_REG(hw, EECD, eecd); 661 662 udelay(hw->eeprom.delay_usec); 663 } else if (hw->eeprom.type == e1000_eeprom_microwire) { 664 /* cleanup eeprom */ 665 666 /* CS on Microwire is active-high */ 667 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI); 668 669 E1000_WRITE_REG(hw, EECD, eecd); 670 671 /* Rising edge of clock */ 672 eecd |= E1000_EECD_SK; 673 E1000_WRITE_REG(hw, EECD, eecd); 674 E1000_WRITE_FLUSH(hw); 675 udelay(hw->eeprom.delay_usec); 676 677 /* Falling edge of clock */ 678 eecd &= ~E1000_EECD_SK; 679 E1000_WRITE_REG(hw, EECD, eecd); 680 E1000_WRITE_FLUSH(hw); 681 udelay(hw->eeprom.delay_usec); 682 } 683 684 /* Stop requesting EEPROM access */ 685 if (hw->mac_type > e1000_82544) { 686 eecd &= ~E1000_EECD_REQ; 687 E1000_WRITE_REG(hw, EECD, eecd); 688 } 689 } 690 /****************************************************************************** 691 * Reads a 16 bit word from the EEPROM. 692 * 693 * hw - Struct containing variables accessed by shared code 694 *****************************************************************************/ 695 static int32_t 696 e1000_spi_eeprom_ready(struct e1000_hw *hw) 697 { 698 uint16_t retry_count = 0; 699 uint8_t spi_stat_reg; 700 701 DEBUGFUNC(); 702 703 /* Read "Status Register" repeatedly until the LSB is cleared. The 704 * EEPROM will signal that the command has been completed by clearing 705 * bit 0 of the internal status register. If it's not cleared within 706 * 5 milliseconds, then error out. 707 */ 708 retry_count = 0; 709 do { 710 e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI, 711 hw->eeprom.opcode_bits); 712 spi_stat_reg = (uint8_t)e1000_shift_in_ee_bits(hw, 8); 713 if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI)) 714 break; 715 716 udelay(5); 717 retry_count += 5; 718 719 e1000_standby_eeprom(hw); 720 } while (retry_count < EEPROM_MAX_RETRY_SPI); 721 722 /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and 723 * only 0-5mSec on 5V devices) 724 */ 725 if (retry_count >= EEPROM_MAX_RETRY_SPI) { 726 DEBUGOUT("SPI EEPROM Status error\n"); 727 return -E1000_ERR_EEPROM; 728 } 729 730 return E1000_SUCCESS; 731 } 732 733 /****************************************************************************** 734 * Reads a 16 bit word from the EEPROM. 735 * 736 * hw - Struct containing variables accessed by shared code 737 * offset - offset of word in the EEPROM to read 738 * data - word read from the EEPROM 739 *****************************************************************************/ 740 static int32_t 741 e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset, 742 uint16_t words, uint16_t *data) 743 { 744 struct e1000_eeprom_info *eeprom = &hw->eeprom; 745 uint32_t i = 0; 746 747 DEBUGFUNC(); 748 749 /* If eeprom is not yet detected, do so now */ 750 if (eeprom->word_size == 0) 751 e1000_init_eeprom_params(hw); 752 753 /* A check for invalid values: offset too large, too many words, 754 * and not enough words. 755 */ 756 if ((offset >= eeprom->word_size) || 757 (words > eeprom->word_size - offset) || 758 (words == 0)) { 759 DEBUGOUT("\"words\" parameter out of bounds." 760 "Words = %d, size = %d\n", offset, eeprom->word_size); 761 return -E1000_ERR_EEPROM; 762 } 763 764 /* EEPROM's that don't use EERD to read require us to bit-bang the SPI 765 * directly. In this case, we need to acquire the EEPROM so that 766 * FW or other port software does not interrupt. 767 */ 768 if (e1000_is_onboard_nvm_eeprom(hw) == true && 769 hw->eeprom.use_eerd == false) { 770 771 /* Prepare the EEPROM for bit-bang reading */ 772 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS) 773 return -E1000_ERR_EEPROM; 774 } 775 776 /* Eerd register EEPROM access requires no eeprom aquire/release */ 777 if (eeprom->use_eerd == true) 778 return e1000_read_eeprom_eerd(hw, offset, words, data); 779 780 /* ich8lan does not support currently. if needed, please 781 * add corresponding code and functions. 782 */ 783 #if 0 784 /* ICH EEPROM access is done via the ICH flash controller */ 785 if (eeprom->type == e1000_eeprom_ich8) 786 return e1000_read_eeprom_ich8(hw, offset, words, data); 787 #endif 788 /* Set up the SPI or Microwire EEPROM for bit-bang reading. We have 789 * acquired the EEPROM at this point, so any returns should relase it */ 790 if (eeprom->type == e1000_eeprom_spi) { 791 uint16_t word_in; 792 uint8_t read_opcode = EEPROM_READ_OPCODE_SPI; 793 794 if (e1000_spi_eeprom_ready(hw)) { 795 e1000_release_eeprom(hw); 796 return -E1000_ERR_EEPROM; 797 } 798 799 e1000_standby_eeprom(hw); 800 801 /* Some SPI eeproms use the 8th address bit embedded in 802 * the opcode */ 803 if ((eeprom->address_bits == 8) && (offset >= 128)) 804 read_opcode |= EEPROM_A8_OPCODE_SPI; 805 806 /* Send the READ command (opcode + addr) */ 807 e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits); 808 e1000_shift_out_ee_bits(hw, (uint16_t)(offset*2), 809 eeprom->address_bits); 810 811 /* Read the data. The address of the eeprom internally 812 * increments with each byte (spi) being read, saving on the 813 * overhead of eeprom setup and tear-down. The address 814 * counter will roll over if reading beyond the size of 815 * the eeprom, thus allowing the entire memory to be read 816 * starting from any offset. */ 817 for (i = 0; i < words; i++) { 818 word_in = e1000_shift_in_ee_bits(hw, 16); 819 data[i] = (word_in >> 8) | (word_in << 8); 820 } 821 } else if (eeprom->type == e1000_eeprom_microwire) { 822 for (i = 0; i < words; i++) { 823 /* Send the READ command (opcode + addr) */ 824 e1000_shift_out_ee_bits(hw, 825 EEPROM_READ_OPCODE_MICROWIRE, 826 eeprom->opcode_bits); 827 e1000_shift_out_ee_bits(hw, (uint16_t)(offset + i), 828 eeprom->address_bits); 829 830 /* Read the data. For microwire, each word requires 831 * the overhead of eeprom setup and tear-down. */ 832 data[i] = e1000_shift_in_ee_bits(hw, 16); 833 e1000_standby_eeprom(hw); 834 } 835 } 836 837 /* End this read operation */ 838 e1000_release_eeprom(hw); 839 840 return E1000_SUCCESS; 841 } 842 843 /****************************************************************************** 844 * Verifies that the EEPROM has a valid checksum 845 * 846 * hw - Struct containing variables accessed by shared code 847 * 848 * Reads the first 64 16 bit words of the EEPROM and sums the values read. 849 * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is 850 * valid. 851 *****************************************************************************/ 852 static int e1000_validate_eeprom_checksum(struct e1000_hw *hw) 853 { 854 uint16_t i, checksum, checksum_reg, *buf; 855 856 DEBUGFUNC(); 857 858 /* Allocate a temporary buffer */ 859 buf = malloc(sizeof(buf[0]) * (EEPROM_CHECKSUM_REG + 1)); 860 if (!buf) { 861 E1000_ERR(hw->nic, "Unable to allocate EEPROM buffer!\n"); 862 return -E1000_ERR_EEPROM; 863 } 864 865 /* Read the EEPROM */ 866 if (e1000_read_eeprom(hw, 0, EEPROM_CHECKSUM_REG + 1, buf) < 0) { 867 E1000_ERR(hw->nic, "Unable to read EEPROM!\n"); 868 return -E1000_ERR_EEPROM; 869 } 870 871 /* Compute the checksum */ 872 checksum = 0; 873 for (i = 0; i < EEPROM_CHECKSUM_REG; i++) 874 checksum += buf[i]; 875 checksum = ((uint16_t)EEPROM_SUM) - checksum; 876 checksum_reg = buf[i]; 877 878 /* Verify it! */ 879 if (checksum == checksum_reg) 880 return 0; 881 882 /* Hrm, verification failed, print an error */ 883 E1000_ERR(hw->nic, "EEPROM checksum is incorrect!\n"); 884 E1000_ERR(hw->nic, " ...register was 0x%04hx, calculated 0x%04hx\n", 885 checksum_reg, checksum); 886 887 return -E1000_ERR_EEPROM; 888 } 889 #endif /* CONFIG_E1000_NO_NVM */ 890 891 /***************************************************************************** 892 * Set PHY to class A mode 893 * Assumes the following operations will follow to enable the new class mode. 894 * 1. Do a PHY soft reset 895 * 2. Restart auto-negotiation or force link. 896 * 897 * hw - Struct containing variables accessed by shared code 898 ****************************************************************************/ 899 static int32_t 900 e1000_set_phy_mode(struct e1000_hw *hw) 901 { 902 #ifndef CONFIG_E1000_NO_NVM 903 int32_t ret_val; 904 uint16_t eeprom_data; 905 906 DEBUGFUNC(); 907 908 if ((hw->mac_type == e1000_82545_rev_3) && 909 (hw->media_type == e1000_media_type_copper)) { 910 ret_val = e1000_read_eeprom(hw, EEPROM_PHY_CLASS_WORD, 911 1, &eeprom_data); 912 if (ret_val) 913 return ret_val; 914 915 if ((eeprom_data != EEPROM_RESERVED_WORD) && 916 (eeprom_data & EEPROM_PHY_CLASS_A)) { 917 ret_val = e1000_write_phy_reg(hw, 918 M88E1000_PHY_PAGE_SELECT, 0x000B); 919 if (ret_val) 920 return ret_val; 921 ret_val = e1000_write_phy_reg(hw, 922 M88E1000_PHY_GEN_CONTROL, 0x8104); 923 if (ret_val) 924 return ret_val; 925 926 hw->phy_reset_disable = false; 927 } 928 } 929 #endif 930 return E1000_SUCCESS; 931 } 932 933 #ifndef CONFIG_E1000_NO_NVM 934 /*************************************************************************** 935 * 936 * Obtaining software semaphore bit (SMBI) before resetting PHY. 937 * 938 * hw: Struct containing variables accessed by shared code 939 * 940 * returns: - E1000_ERR_RESET if fail to obtain semaphore. 941 * E1000_SUCCESS at any other case. 942 * 943 ***************************************************************************/ 944 static int32_t 945 e1000_get_software_semaphore(struct e1000_hw *hw) 946 { 947 int32_t timeout = hw->eeprom.word_size + 1; 948 uint32_t swsm; 949 950 DEBUGFUNC(); 951 952 if (hw->mac_type != e1000_80003es2lan) 953 return E1000_SUCCESS; 954 955 while (timeout) { 956 swsm = E1000_READ_REG(hw, SWSM); 957 /* If SMBI bit cleared, it is now set and we hold 958 * the semaphore */ 959 if (!(swsm & E1000_SWSM_SMBI)) 960 break; 961 mdelay(1); 962 timeout--; 963 } 964 965 if (!timeout) { 966 DEBUGOUT("Driver can't access device - SMBI bit is set.\n"); 967 return -E1000_ERR_RESET; 968 } 969 970 return E1000_SUCCESS; 971 } 972 #endif 973 974 /*************************************************************************** 975 * This function clears HW semaphore bits. 976 * 977 * hw: Struct containing variables accessed by shared code 978 * 979 * returns: - None. 980 * 981 ***************************************************************************/ 982 static void 983 e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw) 984 { 985 #ifndef CONFIG_E1000_NO_NVM 986 uint32_t swsm; 987 988 DEBUGFUNC(); 989 990 if (!hw->eeprom_semaphore_present) 991 return; 992 993 swsm = E1000_READ_REG(hw, SWSM); 994 if (hw->mac_type == e1000_80003es2lan) { 995 /* Release both semaphores. */ 996 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI); 997 } else 998 swsm &= ~(E1000_SWSM_SWESMBI); 999 E1000_WRITE_REG(hw, SWSM, swsm); 1000 #endif 1001 } 1002 1003 /*************************************************************************** 1004 * 1005 * Using the combination of SMBI and SWESMBI semaphore bits when resetting 1006 * adapter or Eeprom access. 1007 * 1008 * hw: Struct containing variables accessed by shared code 1009 * 1010 * returns: - E1000_ERR_EEPROM if fail to access EEPROM. 1011 * E1000_SUCCESS at any other case. 1012 * 1013 ***************************************************************************/ 1014 static int32_t 1015 e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw) 1016 { 1017 #ifndef CONFIG_E1000_NO_NVM 1018 int32_t timeout; 1019 uint32_t swsm; 1020 1021 DEBUGFUNC(); 1022 1023 if (!hw->eeprom_semaphore_present) 1024 return E1000_SUCCESS; 1025 1026 if (hw->mac_type == e1000_80003es2lan) { 1027 /* Get the SW semaphore. */ 1028 if (e1000_get_software_semaphore(hw) != E1000_SUCCESS) 1029 return -E1000_ERR_EEPROM; 1030 } 1031 1032 /* Get the FW semaphore. */ 1033 timeout = hw->eeprom.word_size + 1; 1034 while (timeout) { 1035 swsm = E1000_READ_REG(hw, SWSM); 1036 swsm |= E1000_SWSM_SWESMBI; 1037 E1000_WRITE_REG(hw, SWSM, swsm); 1038 /* if we managed to set the bit we got the semaphore. */ 1039 swsm = E1000_READ_REG(hw, SWSM); 1040 if (swsm & E1000_SWSM_SWESMBI) 1041 break; 1042 1043 udelay(50); 1044 timeout--; 1045 } 1046 1047 if (!timeout) { 1048 /* Release semaphores */ 1049 e1000_put_hw_eeprom_semaphore(hw); 1050 DEBUGOUT("Driver can't access the Eeprom - " 1051 "SWESMBI bit is set.\n"); 1052 return -E1000_ERR_EEPROM; 1053 } 1054 #endif 1055 return E1000_SUCCESS; 1056 } 1057 1058 static int32_t 1059 e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask) 1060 { 1061 uint32_t swfw_sync = 0; 1062 uint32_t swmask = mask; 1063 uint32_t fwmask = mask << 16; 1064 int32_t timeout = 200; 1065 1066 DEBUGFUNC(); 1067 while (timeout) { 1068 if (e1000_get_hw_eeprom_semaphore(hw)) 1069 return -E1000_ERR_SWFW_SYNC; 1070 1071 swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC); 1072 if (!(swfw_sync & (fwmask | swmask))) 1073 break; 1074 1075 /* firmware currently using resource (fwmask) */ 1076 /* or other software thread currently using resource (swmask) */ 1077 e1000_put_hw_eeprom_semaphore(hw); 1078 mdelay(5); 1079 timeout--; 1080 } 1081 1082 if (!timeout) { 1083 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n"); 1084 return -E1000_ERR_SWFW_SYNC; 1085 } 1086 1087 swfw_sync |= swmask; 1088 E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync); 1089 1090 e1000_put_hw_eeprom_semaphore(hw); 1091 return E1000_SUCCESS; 1092 } 1093 1094 static bool e1000_is_second_port(struct e1000_hw *hw) 1095 { 1096 switch (hw->mac_type) { 1097 case e1000_80003es2lan: 1098 case e1000_82546: 1099 case e1000_82571: 1100 if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1) 1101 return true; 1102 /* Fallthrough */ 1103 default: 1104 return false; 1105 } 1106 } 1107 1108 #ifndef CONFIG_E1000_NO_NVM 1109 /****************************************************************************** 1110 * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the 1111 * second function of dual function devices 1112 * 1113 * nic - Struct containing variables accessed by shared code 1114 *****************************************************************************/ 1115 static int 1116 e1000_read_mac_addr(struct eth_device *nic) 1117 { 1118 struct e1000_hw *hw = nic->priv; 1119 uint16_t offset; 1120 uint16_t eeprom_data; 1121 int i; 1122 1123 DEBUGFUNC(); 1124 1125 for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) { 1126 offset = i >> 1; 1127 if (e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) { 1128 DEBUGOUT("EEPROM Read Error\n"); 1129 return -E1000_ERR_EEPROM; 1130 } 1131 nic->enetaddr[i] = eeprom_data & 0xff; 1132 nic->enetaddr[i + 1] = (eeprom_data >> 8) & 0xff; 1133 } 1134 1135 /* Invert the last bit if this is the second device */ 1136 if (e1000_is_second_port(hw)) 1137 nic->enetaddr[5] ^= 1; 1138 1139 #ifdef CONFIG_E1000_FALLBACK_MAC 1140 if (!is_valid_ether_addr(nic->enetaddr)) { 1141 unsigned char fb_mac[NODE_ADDRESS_SIZE] = CONFIG_E1000_FALLBACK_MAC; 1142 1143 memcpy (nic->enetaddr, fb_mac, NODE_ADDRESS_SIZE); 1144 } 1145 #endif 1146 return 0; 1147 } 1148 #endif 1149 1150 /****************************************************************************** 1151 * Initializes receive address filters. 1152 * 1153 * hw - Struct containing variables accessed by shared code 1154 * 1155 * Places the MAC address in receive address register 0 and clears the rest 1156 * of the receive addresss registers. Clears the multicast table. Assumes 1157 * the receiver is in reset when the routine is called. 1158 *****************************************************************************/ 1159 static void 1160 e1000_init_rx_addrs(struct eth_device *nic) 1161 { 1162 struct e1000_hw *hw = nic->priv; 1163 uint32_t i; 1164 uint32_t addr_low; 1165 uint32_t addr_high; 1166 1167 DEBUGFUNC(); 1168 1169 /* Setup the receive address. */ 1170 DEBUGOUT("Programming MAC Address into RAR[0]\n"); 1171 addr_low = (nic->enetaddr[0] | 1172 (nic->enetaddr[1] << 8) | 1173 (nic->enetaddr[2] << 16) | (nic->enetaddr[3] << 24)); 1174 1175 addr_high = (nic->enetaddr[4] | (nic->enetaddr[5] << 8) | E1000_RAH_AV); 1176 1177 E1000_WRITE_REG_ARRAY(hw, RA, 0, addr_low); 1178 E1000_WRITE_REG_ARRAY(hw, RA, 1, addr_high); 1179 1180 /* Zero out the other 15 receive addresses. */ 1181 DEBUGOUT("Clearing RAR[1-15]\n"); 1182 for (i = 1; i < E1000_RAR_ENTRIES; i++) { 1183 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0); 1184 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0); 1185 } 1186 } 1187 1188 /****************************************************************************** 1189 * Clears the VLAN filer table 1190 * 1191 * hw - Struct containing variables accessed by shared code 1192 *****************************************************************************/ 1193 static void 1194 e1000_clear_vfta(struct e1000_hw *hw) 1195 { 1196 uint32_t offset; 1197 1198 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) 1199 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, 0); 1200 } 1201 1202 /****************************************************************************** 1203 * Set the mac type member in the hw struct. 1204 * 1205 * hw - Struct containing variables accessed by shared code 1206 *****************************************************************************/ 1207 int32_t 1208 e1000_set_mac_type(struct e1000_hw *hw) 1209 { 1210 DEBUGFUNC(); 1211 1212 switch (hw->device_id) { 1213 case E1000_DEV_ID_82542: 1214 switch (hw->revision_id) { 1215 case E1000_82542_2_0_REV_ID: 1216 hw->mac_type = e1000_82542_rev2_0; 1217 break; 1218 case E1000_82542_2_1_REV_ID: 1219 hw->mac_type = e1000_82542_rev2_1; 1220 break; 1221 default: 1222 /* Invalid 82542 revision ID */ 1223 return -E1000_ERR_MAC_TYPE; 1224 } 1225 break; 1226 case E1000_DEV_ID_82543GC_FIBER: 1227 case E1000_DEV_ID_82543GC_COPPER: 1228 hw->mac_type = e1000_82543; 1229 break; 1230 case E1000_DEV_ID_82544EI_COPPER: 1231 case E1000_DEV_ID_82544EI_FIBER: 1232 case E1000_DEV_ID_82544GC_COPPER: 1233 case E1000_DEV_ID_82544GC_LOM: 1234 hw->mac_type = e1000_82544; 1235 break; 1236 case E1000_DEV_ID_82540EM: 1237 case E1000_DEV_ID_82540EM_LOM: 1238 case E1000_DEV_ID_82540EP: 1239 case E1000_DEV_ID_82540EP_LOM: 1240 case E1000_DEV_ID_82540EP_LP: 1241 hw->mac_type = e1000_82540; 1242 break; 1243 case E1000_DEV_ID_82545EM_COPPER: 1244 case E1000_DEV_ID_82545EM_FIBER: 1245 hw->mac_type = e1000_82545; 1246 break; 1247 case E1000_DEV_ID_82545GM_COPPER: 1248 case E1000_DEV_ID_82545GM_FIBER: 1249 case E1000_DEV_ID_82545GM_SERDES: 1250 hw->mac_type = e1000_82545_rev_3; 1251 break; 1252 case E1000_DEV_ID_82546EB_COPPER: 1253 case E1000_DEV_ID_82546EB_FIBER: 1254 case E1000_DEV_ID_82546EB_QUAD_COPPER: 1255 hw->mac_type = e1000_82546; 1256 break; 1257 case E1000_DEV_ID_82546GB_COPPER: 1258 case E1000_DEV_ID_82546GB_FIBER: 1259 case E1000_DEV_ID_82546GB_SERDES: 1260 case E1000_DEV_ID_82546GB_PCIE: 1261 case E1000_DEV_ID_82546GB_QUAD_COPPER: 1262 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3: 1263 hw->mac_type = e1000_82546_rev_3; 1264 break; 1265 case E1000_DEV_ID_82541EI: 1266 case E1000_DEV_ID_82541EI_MOBILE: 1267 case E1000_DEV_ID_82541ER_LOM: 1268 hw->mac_type = e1000_82541; 1269 break; 1270 case E1000_DEV_ID_82541ER: 1271 case E1000_DEV_ID_82541GI: 1272 case E1000_DEV_ID_82541GI_LF: 1273 case E1000_DEV_ID_82541GI_MOBILE: 1274 hw->mac_type = e1000_82541_rev_2; 1275 break; 1276 case E1000_DEV_ID_82547EI: 1277 case E1000_DEV_ID_82547EI_MOBILE: 1278 hw->mac_type = e1000_82547; 1279 break; 1280 case E1000_DEV_ID_82547GI: 1281 hw->mac_type = e1000_82547_rev_2; 1282 break; 1283 case E1000_DEV_ID_82571EB_COPPER: 1284 case E1000_DEV_ID_82571EB_FIBER: 1285 case E1000_DEV_ID_82571EB_SERDES: 1286 case E1000_DEV_ID_82571EB_SERDES_DUAL: 1287 case E1000_DEV_ID_82571EB_SERDES_QUAD: 1288 case E1000_DEV_ID_82571EB_QUAD_COPPER: 1289 case E1000_DEV_ID_82571PT_QUAD_COPPER: 1290 case E1000_DEV_ID_82571EB_QUAD_FIBER: 1291 case E1000_DEV_ID_82571EB_QUAD_COPPER_LOWPROFILE: 1292 hw->mac_type = e1000_82571; 1293 break; 1294 case E1000_DEV_ID_82572EI_COPPER: 1295 case E1000_DEV_ID_82572EI_FIBER: 1296 case E1000_DEV_ID_82572EI_SERDES: 1297 case E1000_DEV_ID_82572EI: 1298 hw->mac_type = e1000_82572; 1299 break; 1300 case E1000_DEV_ID_82573E: 1301 case E1000_DEV_ID_82573E_IAMT: 1302 case E1000_DEV_ID_82573L: 1303 hw->mac_type = e1000_82573; 1304 break; 1305 case E1000_DEV_ID_82574L: 1306 hw->mac_type = e1000_82574; 1307 break; 1308 case E1000_DEV_ID_80003ES2LAN_COPPER_SPT: 1309 case E1000_DEV_ID_80003ES2LAN_SERDES_SPT: 1310 case E1000_DEV_ID_80003ES2LAN_COPPER_DPT: 1311 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT: 1312 hw->mac_type = e1000_80003es2lan; 1313 break; 1314 case E1000_DEV_ID_ICH8_IGP_M_AMT: 1315 case E1000_DEV_ID_ICH8_IGP_AMT: 1316 case E1000_DEV_ID_ICH8_IGP_C: 1317 case E1000_DEV_ID_ICH8_IFE: 1318 case E1000_DEV_ID_ICH8_IFE_GT: 1319 case E1000_DEV_ID_ICH8_IFE_G: 1320 case E1000_DEV_ID_ICH8_IGP_M: 1321 hw->mac_type = e1000_ich8lan; 1322 break; 1323 default: 1324 /* Should never have loaded on this device */ 1325 return -E1000_ERR_MAC_TYPE; 1326 } 1327 return E1000_SUCCESS; 1328 } 1329 1330 /****************************************************************************** 1331 * Reset the transmit and receive units; mask and clear all interrupts. 1332 * 1333 * hw - Struct containing variables accessed by shared code 1334 *****************************************************************************/ 1335 void 1336 e1000_reset_hw(struct e1000_hw *hw) 1337 { 1338 uint32_t ctrl; 1339 uint32_t ctrl_ext; 1340 uint32_t manc; 1341 uint32_t pba = 0; 1342 1343 DEBUGFUNC(); 1344 1345 /* get the correct pba value for both PCI and PCIe*/ 1346 if (hw->mac_type < e1000_82571) 1347 pba = E1000_DEFAULT_PCI_PBA; 1348 else 1349 pba = E1000_DEFAULT_PCIE_PBA; 1350 1351 /* For 82542 (rev 2.0), disable MWI before issuing a device reset */ 1352 if (hw->mac_type == e1000_82542_rev2_0) { 1353 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n"); 1354 pci_write_config_word(hw->pdev, PCI_COMMAND, 1355 hw->pci_cmd_word & ~PCI_COMMAND_INVALIDATE); 1356 } 1357 1358 /* Clear interrupt mask to stop board from generating interrupts */ 1359 DEBUGOUT("Masking off all interrupts\n"); 1360 E1000_WRITE_REG(hw, IMC, 0xffffffff); 1361 1362 /* Disable the Transmit and Receive units. Then delay to allow 1363 * any pending transactions to complete before we hit the MAC with 1364 * the global reset. 1365 */ 1366 E1000_WRITE_REG(hw, RCTL, 0); 1367 E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP); 1368 E1000_WRITE_FLUSH(hw); 1369 1370 /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */ 1371 hw->tbi_compatibility_on = false; 1372 1373 /* Delay to allow any outstanding PCI transactions to complete before 1374 * resetting the device 1375 */ 1376 mdelay(10); 1377 1378 /* Issue a global reset to the MAC. This will reset the chip's 1379 * transmit, receive, DMA, and link units. It will not effect 1380 * the current PCI configuration. The global reset bit is self- 1381 * clearing, and should clear within a microsecond. 1382 */ 1383 DEBUGOUT("Issuing a global reset to MAC\n"); 1384 ctrl = E1000_READ_REG(hw, CTRL); 1385 1386 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST)); 1387 1388 /* Force a reload from the EEPROM if necessary */ 1389 if (hw->mac_type < e1000_82540) { 1390 /* Wait for reset to complete */ 1391 udelay(10); 1392 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 1393 ctrl_ext |= E1000_CTRL_EXT_EE_RST; 1394 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 1395 E1000_WRITE_FLUSH(hw); 1396 /* Wait for EEPROM reload */ 1397 mdelay(2); 1398 } else { 1399 /* Wait for EEPROM reload (it happens automatically) */ 1400 mdelay(4); 1401 /* Dissable HW ARPs on ASF enabled adapters */ 1402 manc = E1000_READ_REG(hw, MANC); 1403 manc &= ~(E1000_MANC_ARP_EN); 1404 E1000_WRITE_REG(hw, MANC, manc); 1405 } 1406 1407 /* Clear interrupt mask to stop board from generating interrupts */ 1408 DEBUGOUT("Masking off all interrupts\n"); 1409 E1000_WRITE_REG(hw, IMC, 0xffffffff); 1410 1411 /* Clear any pending interrupt events. */ 1412 E1000_READ_REG(hw, ICR); 1413 1414 /* If MWI was previously enabled, reenable it. */ 1415 if (hw->mac_type == e1000_82542_rev2_0) { 1416 pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word); 1417 } 1418 E1000_WRITE_REG(hw, PBA, pba); 1419 } 1420 1421 /****************************************************************************** 1422 * 1423 * Initialize a number of hardware-dependent bits 1424 * 1425 * hw: Struct containing variables accessed by shared code 1426 * 1427 * This function contains hardware limitation workarounds for PCI-E adapters 1428 * 1429 *****************************************************************************/ 1430 static void 1431 e1000_initialize_hardware_bits(struct e1000_hw *hw) 1432 { 1433 if ((hw->mac_type >= e1000_82571) && 1434 (!hw->initialize_hw_bits_disable)) { 1435 /* Settings common to all PCI-express silicon */ 1436 uint32_t reg_ctrl, reg_ctrl_ext; 1437 uint32_t reg_tarc0, reg_tarc1; 1438 uint32_t reg_tctl; 1439 uint32_t reg_txdctl, reg_txdctl1; 1440 1441 /* link autonegotiation/sync workarounds */ 1442 reg_tarc0 = E1000_READ_REG(hw, TARC0); 1443 reg_tarc0 &= ~((1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)); 1444 1445 /* Enable not-done TX descriptor counting */ 1446 reg_txdctl = E1000_READ_REG(hw, TXDCTL); 1447 reg_txdctl |= E1000_TXDCTL_COUNT_DESC; 1448 E1000_WRITE_REG(hw, TXDCTL, reg_txdctl); 1449 1450 reg_txdctl1 = E1000_READ_REG(hw, TXDCTL1); 1451 reg_txdctl1 |= E1000_TXDCTL_COUNT_DESC; 1452 E1000_WRITE_REG(hw, TXDCTL1, reg_txdctl1); 1453 1454 switch (hw->mac_type) { 1455 case e1000_82571: 1456 case e1000_82572: 1457 /* Clear PHY TX compatible mode bits */ 1458 reg_tarc1 = E1000_READ_REG(hw, TARC1); 1459 reg_tarc1 &= ~((1 << 30)|(1 << 29)); 1460 1461 /* link autonegotiation/sync workarounds */ 1462 reg_tarc0 |= ((1 << 26)|(1 << 25)|(1 << 24)|(1 << 23)); 1463 1464 /* TX ring control fixes */ 1465 reg_tarc1 |= ((1 << 26)|(1 << 25)|(1 << 24)); 1466 1467 /* Multiple read bit is reversed polarity */ 1468 reg_tctl = E1000_READ_REG(hw, TCTL); 1469 if (reg_tctl & E1000_TCTL_MULR) 1470 reg_tarc1 &= ~(1 << 28); 1471 else 1472 reg_tarc1 |= (1 << 28); 1473 1474 E1000_WRITE_REG(hw, TARC1, reg_tarc1); 1475 break; 1476 case e1000_82573: 1477 case e1000_82574: 1478 reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 1479 reg_ctrl_ext &= ~(1 << 23); 1480 reg_ctrl_ext |= (1 << 22); 1481 1482 /* TX byte count fix */ 1483 reg_ctrl = E1000_READ_REG(hw, CTRL); 1484 reg_ctrl &= ~(1 << 29); 1485 1486 E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext); 1487 E1000_WRITE_REG(hw, CTRL, reg_ctrl); 1488 break; 1489 case e1000_80003es2lan: 1490 /* improve small packet performace for fiber/serdes */ 1491 if ((hw->media_type == e1000_media_type_fiber) 1492 || (hw->media_type == 1493 e1000_media_type_internal_serdes)) { 1494 reg_tarc0 &= ~(1 << 20); 1495 } 1496 1497 /* Multiple read bit is reversed polarity */ 1498 reg_tctl = E1000_READ_REG(hw, TCTL); 1499 reg_tarc1 = E1000_READ_REG(hw, TARC1); 1500 if (reg_tctl & E1000_TCTL_MULR) 1501 reg_tarc1 &= ~(1 << 28); 1502 else 1503 reg_tarc1 |= (1 << 28); 1504 1505 E1000_WRITE_REG(hw, TARC1, reg_tarc1); 1506 break; 1507 case e1000_ich8lan: 1508 /* Reduce concurrent DMA requests to 3 from 4 */ 1509 if ((hw->revision_id < 3) || 1510 ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) && 1511 (hw->device_id != E1000_DEV_ID_ICH8_IGP_M))) 1512 reg_tarc0 |= ((1 << 29)|(1 << 28)); 1513 1514 reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 1515 reg_ctrl_ext |= (1 << 22); 1516 E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext); 1517 1518 /* workaround TX hang with TSO=on */ 1519 reg_tarc0 |= ((1 << 27)|(1 << 26)|(1 << 24)|(1 << 23)); 1520 1521 /* Multiple read bit is reversed polarity */ 1522 reg_tctl = E1000_READ_REG(hw, TCTL); 1523 reg_tarc1 = E1000_READ_REG(hw, TARC1); 1524 if (reg_tctl & E1000_TCTL_MULR) 1525 reg_tarc1 &= ~(1 << 28); 1526 else 1527 reg_tarc1 |= (1 << 28); 1528 1529 /* workaround TX hang with TSO=on */ 1530 reg_tarc1 |= ((1 << 30)|(1 << 26)|(1 << 24)); 1531 1532 E1000_WRITE_REG(hw, TARC1, reg_tarc1); 1533 break; 1534 default: 1535 break; 1536 } 1537 1538 E1000_WRITE_REG(hw, TARC0, reg_tarc0); 1539 } 1540 } 1541 1542 /****************************************************************************** 1543 * Performs basic configuration of the adapter. 1544 * 1545 * hw - Struct containing variables accessed by shared code 1546 * 1547 * Assumes that the controller has previously been reset and is in a 1548 * post-reset uninitialized state. Initializes the receive address registers, 1549 * multicast table, and VLAN filter table. Calls routines to setup link 1550 * configuration and flow control settings. Clears all on-chip counters. Leaves 1551 * the transmit and receive units disabled and uninitialized. 1552 *****************************************************************************/ 1553 static int 1554 e1000_init_hw(struct eth_device *nic) 1555 { 1556 struct e1000_hw *hw = nic->priv; 1557 uint32_t ctrl; 1558 uint32_t i; 1559 int32_t ret_val; 1560 uint16_t pcix_cmd_word; 1561 uint16_t pcix_stat_hi_word; 1562 uint16_t cmd_mmrbc; 1563 uint16_t stat_mmrbc; 1564 uint32_t mta_size; 1565 uint32_t reg_data; 1566 uint32_t ctrl_ext; 1567 DEBUGFUNC(); 1568 /* force full DMA clock frequency for 10/100 on ICH8 A0-B0 */ 1569 if ((hw->mac_type == e1000_ich8lan) && 1570 ((hw->revision_id < 3) || 1571 ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) && 1572 (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))) { 1573 reg_data = E1000_READ_REG(hw, STATUS); 1574 reg_data &= ~0x80000000; 1575 E1000_WRITE_REG(hw, STATUS, reg_data); 1576 } 1577 /* Do not need initialize Identification LED */ 1578 1579 /* Set the media type and TBI compatibility */ 1580 e1000_set_media_type(hw); 1581 1582 /* Must be called after e1000_set_media_type 1583 * because media_type is used */ 1584 e1000_initialize_hardware_bits(hw); 1585 1586 /* Disabling VLAN filtering. */ 1587 DEBUGOUT("Initializing the IEEE VLAN\n"); 1588 /* VET hardcoded to standard value and VFTA removed in ICH8 LAN */ 1589 if (hw->mac_type != e1000_ich8lan) { 1590 if (hw->mac_type < e1000_82545_rev_3) 1591 E1000_WRITE_REG(hw, VET, 0); 1592 e1000_clear_vfta(hw); 1593 } 1594 1595 /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */ 1596 if (hw->mac_type == e1000_82542_rev2_0) { 1597 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n"); 1598 pci_write_config_word(hw->pdev, PCI_COMMAND, 1599 hw-> 1600 pci_cmd_word & ~PCI_COMMAND_INVALIDATE); 1601 E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST); 1602 E1000_WRITE_FLUSH(hw); 1603 mdelay(5); 1604 } 1605 1606 /* Setup the receive address. This involves initializing all of the Receive 1607 * Address Registers (RARs 0 - 15). 1608 */ 1609 e1000_init_rx_addrs(nic); 1610 1611 /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */ 1612 if (hw->mac_type == e1000_82542_rev2_0) { 1613 E1000_WRITE_REG(hw, RCTL, 0); 1614 E1000_WRITE_FLUSH(hw); 1615 mdelay(1); 1616 pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word); 1617 } 1618 1619 /* Zero out the Multicast HASH table */ 1620 DEBUGOUT("Zeroing the MTA\n"); 1621 mta_size = E1000_MC_TBL_SIZE; 1622 if (hw->mac_type == e1000_ich8lan) 1623 mta_size = E1000_MC_TBL_SIZE_ICH8LAN; 1624 for (i = 0; i < mta_size; i++) { 1625 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0); 1626 /* use write flush to prevent Memory Write Block (MWB) from 1627 * occuring when accessing our register space */ 1628 E1000_WRITE_FLUSH(hw); 1629 } 1630 #if 0 1631 /* Set the PCI priority bit correctly in the CTRL register. This 1632 * determines if the adapter gives priority to receives, or if it 1633 * gives equal priority to transmits and receives. Valid only on 1634 * 82542 and 82543 silicon. 1635 */ 1636 if (hw->dma_fairness && hw->mac_type <= e1000_82543) { 1637 ctrl = E1000_READ_REG(hw, CTRL); 1638 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR); 1639 } 1640 #endif 1641 switch (hw->mac_type) { 1642 case e1000_82545_rev_3: 1643 case e1000_82546_rev_3: 1644 break; 1645 default: 1646 /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */ 1647 if (hw->bus_type == e1000_bus_type_pcix) { 1648 pci_read_config_word(hw->pdev, PCIX_COMMAND_REGISTER, 1649 &pcix_cmd_word); 1650 pci_read_config_word(hw->pdev, PCIX_STATUS_REGISTER_HI, 1651 &pcix_stat_hi_word); 1652 cmd_mmrbc = 1653 (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) >> 1654 PCIX_COMMAND_MMRBC_SHIFT; 1655 stat_mmrbc = 1656 (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >> 1657 PCIX_STATUS_HI_MMRBC_SHIFT; 1658 if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K) 1659 stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K; 1660 if (cmd_mmrbc > stat_mmrbc) { 1661 pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK; 1662 pcix_cmd_word |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT; 1663 pci_write_config_word(hw->pdev, PCIX_COMMAND_REGISTER, 1664 pcix_cmd_word); 1665 } 1666 } 1667 break; 1668 } 1669 1670 /* More time needed for PHY to initialize */ 1671 if (hw->mac_type == e1000_ich8lan) 1672 mdelay(15); 1673 1674 /* Call a subroutine to configure the link and setup flow control. */ 1675 ret_val = e1000_setup_link(nic); 1676 1677 /* Set the transmit descriptor write-back policy */ 1678 if (hw->mac_type > e1000_82544) { 1679 ctrl = E1000_READ_REG(hw, TXDCTL); 1680 ctrl = 1681 (ctrl & ~E1000_TXDCTL_WTHRESH) | 1682 E1000_TXDCTL_FULL_TX_DESC_WB; 1683 E1000_WRITE_REG(hw, TXDCTL, ctrl); 1684 } 1685 1686 /* Set the receive descriptor write back policy */ 1687 1688 if (hw->mac_type >= e1000_82571) { 1689 ctrl = E1000_READ_REG(hw, RXDCTL); 1690 ctrl = 1691 (ctrl & ~E1000_RXDCTL_WTHRESH) | 1692 E1000_RXDCTL_FULL_RX_DESC_WB; 1693 E1000_WRITE_REG(hw, RXDCTL, ctrl); 1694 } 1695 1696 switch (hw->mac_type) { 1697 default: 1698 break; 1699 case e1000_80003es2lan: 1700 /* Enable retransmit on late collisions */ 1701 reg_data = E1000_READ_REG(hw, TCTL); 1702 reg_data |= E1000_TCTL_RTLC; 1703 E1000_WRITE_REG(hw, TCTL, reg_data); 1704 1705 /* Configure Gigabit Carry Extend Padding */ 1706 reg_data = E1000_READ_REG(hw, TCTL_EXT); 1707 reg_data &= ~E1000_TCTL_EXT_GCEX_MASK; 1708 reg_data |= DEFAULT_80003ES2LAN_TCTL_EXT_GCEX; 1709 E1000_WRITE_REG(hw, TCTL_EXT, reg_data); 1710 1711 /* Configure Transmit Inter-Packet Gap */ 1712 reg_data = E1000_READ_REG(hw, TIPG); 1713 reg_data &= ~E1000_TIPG_IPGT_MASK; 1714 reg_data |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000; 1715 E1000_WRITE_REG(hw, TIPG, reg_data); 1716 1717 reg_data = E1000_READ_REG_ARRAY(hw, FFLT, 0x0001); 1718 reg_data &= ~0x00100000; 1719 E1000_WRITE_REG_ARRAY(hw, FFLT, 0x0001, reg_data); 1720 /* Fall through */ 1721 case e1000_82571: 1722 case e1000_82572: 1723 case e1000_ich8lan: 1724 ctrl = E1000_READ_REG(hw, TXDCTL1); 1725 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) 1726 | E1000_TXDCTL_FULL_TX_DESC_WB; 1727 E1000_WRITE_REG(hw, TXDCTL1, ctrl); 1728 break; 1729 case e1000_82573: 1730 case e1000_82574: 1731 reg_data = E1000_READ_REG(hw, GCR); 1732 reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX; 1733 E1000_WRITE_REG(hw, GCR, reg_data); 1734 } 1735 1736 #if 0 1737 /* Clear all of the statistics registers (clear on read). It is 1738 * important that we do this after we have tried to establish link 1739 * because the symbol error count will increment wildly if there 1740 * is no link. 1741 */ 1742 e1000_clear_hw_cntrs(hw); 1743 1744 /* ICH8 No-snoop bits are opposite polarity. 1745 * Set to snoop by default after reset. */ 1746 if (hw->mac_type == e1000_ich8lan) 1747 e1000_set_pci_ex_no_snoop(hw, PCI_EX_82566_SNOOP_ALL); 1748 #endif 1749 1750 if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER || 1751 hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) { 1752 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 1753 /* Relaxed ordering must be disabled to avoid a parity 1754 * error crash in a PCI slot. */ 1755 ctrl_ext |= E1000_CTRL_EXT_RO_DIS; 1756 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 1757 } 1758 1759 return ret_val; 1760 } 1761 1762 /****************************************************************************** 1763 * Configures flow control and link settings. 1764 * 1765 * hw - Struct containing variables accessed by shared code 1766 * 1767 * Determines which flow control settings to use. Calls the apropriate media- 1768 * specific link configuration function. Configures the flow control settings. 1769 * Assuming the adapter has a valid link partner, a valid link should be 1770 * established. Assumes the hardware has previously been reset and the 1771 * transmitter and receiver are not enabled. 1772 *****************************************************************************/ 1773 static int 1774 e1000_setup_link(struct eth_device *nic) 1775 { 1776 struct e1000_hw *hw = nic->priv; 1777 int32_t ret_val; 1778 #ifndef CONFIG_E1000_NO_NVM 1779 uint32_t ctrl_ext; 1780 uint16_t eeprom_data; 1781 #endif 1782 1783 DEBUGFUNC(); 1784 1785 /* In the case of the phy reset being blocked, we already have a link. 1786 * We do not have to set it up again. */ 1787 if (e1000_check_phy_reset_block(hw)) 1788 return E1000_SUCCESS; 1789 1790 #ifndef CONFIG_E1000_NO_NVM 1791 /* Read and store word 0x0F of the EEPROM. This word contains bits 1792 * that determine the hardware's default PAUSE (flow control) mode, 1793 * a bit that determines whether the HW defaults to enabling or 1794 * disabling auto-negotiation, and the direction of the 1795 * SW defined pins. If there is no SW over-ride of the flow 1796 * control setting, then the variable hw->fc will 1797 * be initialized based on a value in the EEPROM. 1798 */ 1799 if (e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, 1, 1800 &eeprom_data) < 0) { 1801 DEBUGOUT("EEPROM Read Error\n"); 1802 return -E1000_ERR_EEPROM; 1803 } 1804 #endif 1805 if (hw->fc == e1000_fc_default) { 1806 switch (hw->mac_type) { 1807 case e1000_ich8lan: 1808 case e1000_82573: 1809 case e1000_82574: 1810 hw->fc = e1000_fc_full; 1811 break; 1812 default: 1813 #ifndef CONFIG_E1000_NO_NVM 1814 ret_val = e1000_read_eeprom(hw, 1815 EEPROM_INIT_CONTROL2_REG, 1, &eeprom_data); 1816 if (ret_val) { 1817 DEBUGOUT("EEPROM Read Error\n"); 1818 return -E1000_ERR_EEPROM; 1819 } 1820 if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0) 1821 hw->fc = e1000_fc_none; 1822 else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 1823 EEPROM_WORD0F_ASM_DIR) 1824 hw->fc = e1000_fc_tx_pause; 1825 else 1826 #endif 1827 hw->fc = e1000_fc_full; 1828 break; 1829 } 1830 } 1831 1832 /* We want to save off the original Flow Control configuration just 1833 * in case we get disconnected and then reconnected into a different 1834 * hub or switch with different Flow Control capabilities. 1835 */ 1836 if (hw->mac_type == e1000_82542_rev2_0) 1837 hw->fc &= (~e1000_fc_tx_pause); 1838 1839 if ((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1)) 1840 hw->fc &= (~e1000_fc_rx_pause); 1841 1842 hw->original_fc = hw->fc; 1843 1844 DEBUGOUT("After fix-ups FlowControl is now = %x\n", hw->fc); 1845 1846 #ifndef CONFIG_E1000_NO_NVM 1847 /* Take the 4 bits from EEPROM word 0x0F that determine the initial 1848 * polarity value for the SW controlled pins, and setup the 1849 * Extended Device Control reg with that info. 1850 * This is needed because one of the SW controlled pins is used for 1851 * signal detection. So this should be done before e1000_setup_pcs_link() 1852 * or e1000_phy_setup() is called. 1853 */ 1854 if (hw->mac_type == e1000_82543) { 1855 ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) << 1856 SWDPIO__EXT_SHIFT); 1857 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 1858 } 1859 #endif 1860 1861 /* Call the necessary subroutine to configure the link. */ 1862 ret_val = (hw->media_type == e1000_media_type_fiber) ? 1863 e1000_setup_fiber_link(nic) : e1000_setup_copper_link(nic); 1864 if (ret_val < 0) { 1865 return ret_val; 1866 } 1867 1868 /* Initialize the flow control address, type, and PAUSE timer 1869 * registers to their default values. This is done even if flow 1870 * control is disabled, because it does not hurt anything to 1871 * initialize these registers. 1872 */ 1873 DEBUGOUT("Initializing the Flow Control address, type" 1874 "and timer regs\n"); 1875 1876 /* FCAL/H and FCT are hardcoded to standard values in e1000_ich8lan. */ 1877 if (hw->mac_type != e1000_ich8lan) { 1878 E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE); 1879 E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH); 1880 E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW); 1881 } 1882 1883 E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time); 1884 1885 /* Set the flow control receive threshold registers. Normally, 1886 * these registers will be set to a default threshold that may be 1887 * adjusted later by the driver's runtime code. However, if the 1888 * ability to transmit pause frames in not enabled, then these 1889 * registers will be set to 0. 1890 */ 1891 if (!(hw->fc & e1000_fc_tx_pause)) { 1892 E1000_WRITE_REG(hw, FCRTL, 0); 1893 E1000_WRITE_REG(hw, FCRTH, 0); 1894 } else { 1895 /* We need to set up the Receive Threshold high and low water marks 1896 * as well as (optionally) enabling the transmission of XON frames. 1897 */ 1898 if (hw->fc_send_xon) { 1899 E1000_WRITE_REG(hw, FCRTL, 1900 (hw->fc_low_water | E1000_FCRTL_XONE)); 1901 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water); 1902 } else { 1903 E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water); 1904 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water); 1905 } 1906 } 1907 return ret_val; 1908 } 1909 1910 /****************************************************************************** 1911 * Sets up link for a fiber based adapter 1912 * 1913 * hw - Struct containing variables accessed by shared code 1914 * 1915 * Manipulates Physical Coding Sublayer functions in order to configure 1916 * link. Assumes the hardware has been previously reset and the transmitter 1917 * and receiver are not enabled. 1918 *****************************************************************************/ 1919 static int 1920 e1000_setup_fiber_link(struct eth_device *nic) 1921 { 1922 struct e1000_hw *hw = nic->priv; 1923 uint32_t ctrl; 1924 uint32_t status; 1925 uint32_t txcw = 0; 1926 uint32_t i; 1927 uint32_t signal; 1928 int32_t ret_val; 1929 1930 DEBUGFUNC(); 1931 /* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be 1932 * set when the optics detect a signal. On older adapters, it will be 1933 * cleared when there is a signal 1934 */ 1935 ctrl = E1000_READ_REG(hw, CTRL); 1936 if ((hw->mac_type > e1000_82544) && !(ctrl & E1000_CTRL_ILOS)) 1937 signal = E1000_CTRL_SWDPIN1; 1938 else 1939 signal = 0; 1940 1941 printf("signal for %s is %x (ctrl %08x)!!!!\n", nic->name, signal, 1942 ctrl); 1943 /* Take the link out of reset */ 1944 ctrl &= ~(E1000_CTRL_LRST); 1945 1946 e1000_config_collision_dist(hw); 1947 1948 /* Check for a software override of the flow control settings, and setup 1949 * the device accordingly. If auto-negotiation is enabled, then software 1950 * will have to set the "PAUSE" bits to the correct value in the Tranmsit 1951 * Config Word Register (TXCW) and re-start auto-negotiation. However, if 1952 * auto-negotiation is disabled, then software will have to manually 1953 * configure the two flow control enable bits in the CTRL register. 1954 * 1955 * The possible values of the "fc" parameter are: 1956 * 0: Flow control is completely disabled 1957 * 1: Rx flow control is enabled (we can receive pause frames, but 1958 * not send pause frames). 1959 * 2: Tx flow control is enabled (we can send pause frames but we do 1960 * not support receiving pause frames). 1961 * 3: Both Rx and TX flow control (symmetric) are enabled. 1962 */ 1963 switch (hw->fc) { 1964 case e1000_fc_none: 1965 /* Flow control is completely disabled by a software over-ride. */ 1966 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD); 1967 break; 1968 case e1000_fc_rx_pause: 1969 /* RX Flow control is enabled and TX Flow control is disabled by a 1970 * software over-ride. Since there really isn't a way to advertise 1971 * that we are capable of RX Pause ONLY, we will advertise that we 1972 * support both symmetric and asymmetric RX PAUSE. Later, we will 1973 * disable the adapter's ability to send PAUSE frames. 1974 */ 1975 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); 1976 break; 1977 case e1000_fc_tx_pause: 1978 /* TX Flow control is enabled, and RX Flow control is disabled, by a 1979 * software over-ride. 1980 */ 1981 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR); 1982 break; 1983 case e1000_fc_full: 1984 /* Flow control (both RX and TX) is enabled by a software over-ride. */ 1985 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); 1986 break; 1987 default: 1988 DEBUGOUT("Flow control param set incorrectly\n"); 1989 return -E1000_ERR_CONFIG; 1990 break; 1991 } 1992 1993 /* Since auto-negotiation is enabled, take the link out of reset (the link 1994 * will be in reset, because we previously reset the chip). This will 1995 * restart auto-negotiation. If auto-neogtiation is successful then the 1996 * link-up status bit will be set and the flow control enable bits (RFCE 1997 * and TFCE) will be set according to their negotiated value. 1998 */ 1999 DEBUGOUT("Auto-negotiation enabled (%#x)\n", txcw); 2000 2001 E1000_WRITE_REG(hw, TXCW, txcw); 2002 E1000_WRITE_REG(hw, CTRL, ctrl); 2003 E1000_WRITE_FLUSH(hw); 2004 2005 hw->txcw = txcw; 2006 mdelay(1); 2007 2008 /* If we have a signal (the cable is plugged in) then poll for a "Link-Up" 2009 * indication in the Device Status Register. Time-out if a link isn't 2010 * seen in 500 milliseconds seconds (Auto-negotiation should complete in 2011 * less than 500 milliseconds even if the other end is doing it in SW). 2012 */ 2013 if ((E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) { 2014 DEBUGOUT("Looking for Link\n"); 2015 for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) { 2016 mdelay(10); 2017 status = E1000_READ_REG(hw, STATUS); 2018 if (status & E1000_STATUS_LU) 2019 break; 2020 } 2021 if (i == (LINK_UP_TIMEOUT / 10)) { 2022 /* AutoNeg failed to achieve a link, so we'll call 2023 * e1000_check_for_link. This routine will force the link up if we 2024 * detect a signal. This will allow us to communicate with 2025 * non-autonegotiating link partners. 2026 */ 2027 DEBUGOUT("Never got a valid link from auto-neg!!!\n"); 2028 hw->autoneg_failed = 1; 2029 ret_val = e1000_check_for_link(nic); 2030 if (ret_val < 0) { 2031 DEBUGOUT("Error while checking for link\n"); 2032 return ret_val; 2033 } 2034 hw->autoneg_failed = 0; 2035 } else { 2036 hw->autoneg_failed = 0; 2037 DEBUGOUT("Valid Link Found\n"); 2038 } 2039 } else { 2040 DEBUGOUT("No Signal Detected\n"); 2041 return -E1000_ERR_NOLINK; 2042 } 2043 return 0; 2044 } 2045 2046 /****************************************************************************** 2047 * Make sure we have a valid PHY and change PHY mode before link setup. 2048 * 2049 * hw - Struct containing variables accessed by shared code 2050 ******************************************************************************/ 2051 static int32_t 2052 e1000_copper_link_preconfig(struct e1000_hw *hw) 2053 { 2054 uint32_t ctrl; 2055 int32_t ret_val; 2056 uint16_t phy_data; 2057 2058 DEBUGFUNC(); 2059 2060 ctrl = E1000_READ_REG(hw, CTRL); 2061 /* With 82543, we need to force speed and duplex on the MAC equal to what 2062 * the PHY speed and duplex configuration is. In addition, we need to 2063 * perform a hardware reset on the PHY to take it out of reset. 2064 */ 2065 if (hw->mac_type > e1000_82543) { 2066 ctrl |= E1000_CTRL_SLU; 2067 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 2068 E1000_WRITE_REG(hw, CTRL, ctrl); 2069 } else { 2070 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX 2071 | E1000_CTRL_SLU); 2072 E1000_WRITE_REG(hw, CTRL, ctrl); 2073 ret_val = e1000_phy_hw_reset(hw); 2074 if (ret_val) 2075 return ret_val; 2076 } 2077 2078 /* Make sure we have a valid PHY */ 2079 ret_val = e1000_detect_gig_phy(hw); 2080 if (ret_val) { 2081 DEBUGOUT("Error, did not detect valid phy.\n"); 2082 return ret_val; 2083 } 2084 DEBUGOUT("Phy ID = %x \n", hw->phy_id); 2085 2086 /* Set PHY to class A mode (if necessary) */ 2087 ret_val = e1000_set_phy_mode(hw); 2088 if (ret_val) 2089 return ret_val; 2090 if ((hw->mac_type == e1000_82545_rev_3) || 2091 (hw->mac_type == e1000_82546_rev_3)) { 2092 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 2093 &phy_data); 2094 phy_data |= 0x00000008; 2095 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 2096 phy_data); 2097 } 2098 2099 if (hw->mac_type <= e1000_82543 || 2100 hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 || 2101 hw->mac_type == e1000_82541_rev_2 2102 || hw->mac_type == e1000_82547_rev_2) 2103 hw->phy_reset_disable = false; 2104 2105 return E1000_SUCCESS; 2106 } 2107 2108 /***************************************************************************** 2109 * 2110 * This function sets the lplu state according to the active flag. When 2111 * activating lplu this function also disables smart speed and vise versa. 2112 * lplu will not be activated unless the device autonegotiation advertisment 2113 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes. 2114 * hw: Struct containing variables accessed by shared code 2115 * active - true to enable lplu false to disable lplu. 2116 * 2117 * returns: - E1000_ERR_PHY if fail to read/write the PHY 2118 * E1000_SUCCESS at any other case. 2119 * 2120 ****************************************************************************/ 2121 2122 static int32_t 2123 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active) 2124 { 2125 uint32_t phy_ctrl = 0; 2126 int32_t ret_val; 2127 uint16_t phy_data; 2128 DEBUGFUNC(); 2129 2130 if (hw->phy_type != e1000_phy_igp && hw->phy_type != e1000_phy_igp_2 2131 && hw->phy_type != e1000_phy_igp_3) 2132 return E1000_SUCCESS; 2133 2134 /* During driver activity LPLU should not be used or it will attain link 2135 * from the lowest speeds starting from 10Mbps. The capability is used 2136 * for Dx transitions and states */ 2137 if (hw->mac_type == e1000_82541_rev_2 2138 || hw->mac_type == e1000_82547_rev_2) { 2139 ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, 2140 &phy_data); 2141 if (ret_val) 2142 return ret_val; 2143 } else if (hw->mac_type == e1000_ich8lan) { 2144 /* MAC writes into PHY register based on the state transition 2145 * and start auto-negotiation. SW driver can overwrite the 2146 * settings in CSR PHY power control E1000_PHY_CTRL register. */ 2147 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL); 2148 } else { 2149 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, 2150 &phy_data); 2151 if (ret_val) 2152 return ret_val; 2153 } 2154 2155 if (!active) { 2156 if (hw->mac_type == e1000_82541_rev_2 || 2157 hw->mac_type == e1000_82547_rev_2) { 2158 phy_data &= ~IGP01E1000_GMII_FLEX_SPD; 2159 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, 2160 phy_data); 2161 if (ret_val) 2162 return ret_val; 2163 } else { 2164 if (hw->mac_type == e1000_ich8lan) { 2165 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU; 2166 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); 2167 } else { 2168 phy_data &= ~IGP02E1000_PM_D3_LPLU; 2169 ret_val = e1000_write_phy_reg(hw, 2170 IGP02E1000_PHY_POWER_MGMT, phy_data); 2171 if (ret_val) 2172 return ret_val; 2173 } 2174 } 2175 2176 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during 2177 * Dx states where the power conservation is most important. During 2178 * driver activity we should enable SmartSpeed, so performance is 2179 * maintained. */ 2180 if (hw->smart_speed == e1000_smart_speed_on) { 2181 ret_val = e1000_read_phy_reg(hw, 2182 IGP01E1000_PHY_PORT_CONFIG, &phy_data); 2183 if (ret_val) 2184 return ret_val; 2185 2186 phy_data |= IGP01E1000_PSCFR_SMART_SPEED; 2187 ret_val = e1000_write_phy_reg(hw, 2188 IGP01E1000_PHY_PORT_CONFIG, phy_data); 2189 if (ret_val) 2190 return ret_val; 2191 } else if (hw->smart_speed == e1000_smart_speed_off) { 2192 ret_val = e1000_read_phy_reg(hw, 2193 IGP01E1000_PHY_PORT_CONFIG, &phy_data); 2194 if (ret_val) 2195 return ret_val; 2196 2197 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 2198 ret_val = e1000_write_phy_reg(hw, 2199 IGP01E1000_PHY_PORT_CONFIG, phy_data); 2200 if (ret_val) 2201 return ret_val; 2202 } 2203 2204 } else if ((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT) 2205 || (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL) || 2206 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) { 2207 2208 if (hw->mac_type == e1000_82541_rev_2 || 2209 hw->mac_type == e1000_82547_rev_2) { 2210 phy_data |= IGP01E1000_GMII_FLEX_SPD; 2211 ret_val = e1000_write_phy_reg(hw, 2212 IGP01E1000_GMII_FIFO, phy_data); 2213 if (ret_val) 2214 return ret_val; 2215 } else { 2216 if (hw->mac_type == e1000_ich8lan) { 2217 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU; 2218 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); 2219 } else { 2220 phy_data |= IGP02E1000_PM_D3_LPLU; 2221 ret_val = e1000_write_phy_reg(hw, 2222 IGP02E1000_PHY_POWER_MGMT, phy_data); 2223 if (ret_val) 2224 return ret_val; 2225 } 2226 } 2227 2228 /* When LPLU is enabled we should disable SmartSpeed */ 2229 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 2230 &phy_data); 2231 if (ret_val) 2232 return ret_val; 2233 2234 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 2235 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 2236 phy_data); 2237 if (ret_val) 2238 return ret_val; 2239 } 2240 return E1000_SUCCESS; 2241 } 2242 2243 /***************************************************************************** 2244 * 2245 * This function sets the lplu d0 state according to the active flag. When 2246 * activating lplu this function also disables smart speed and vise versa. 2247 * lplu will not be activated unless the device autonegotiation advertisment 2248 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes. 2249 * hw: Struct containing variables accessed by shared code 2250 * active - true to enable lplu false to disable lplu. 2251 * 2252 * returns: - E1000_ERR_PHY if fail to read/write the PHY 2253 * E1000_SUCCESS at any other case. 2254 * 2255 ****************************************************************************/ 2256 2257 static int32_t 2258 e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active) 2259 { 2260 uint32_t phy_ctrl = 0; 2261 int32_t ret_val; 2262 uint16_t phy_data; 2263 DEBUGFUNC(); 2264 2265 if (hw->mac_type <= e1000_82547_rev_2) 2266 return E1000_SUCCESS; 2267 2268 if (hw->mac_type == e1000_ich8lan) { 2269 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL); 2270 } else { 2271 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, 2272 &phy_data); 2273 if (ret_val) 2274 return ret_val; 2275 } 2276 2277 if (!active) { 2278 if (hw->mac_type == e1000_ich8lan) { 2279 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU; 2280 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); 2281 } else { 2282 phy_data &= ~IGP02E1000_PM_D0_LPLU; 2283 ret_val = e1000_write_phy_reg(hw, 2284 IGP02E1000_PHY_POWER_MGMT, phy_data); 2285 if (ret_val) 2286 return ret_val; 2287 } 2288 2289 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during 2290 * Dx states where the power conservation is most important. During 2291 * driver activity we should enable SmartSpeed, so performance is 2292 * maintained. */ 2293 if (hw->smart_speed == e1000_smart_speed_on) { 2294 ret_val = e1000_read_phy_reg(hw, 2295 IGP01E1000_PHY_PORT_CONFIG, &phy_data); 2296 if (ret_val) 2297 return ret_val; 2298 2299 phy_data |= IGP01E1000_PSCFR_SMART_SPEED; 2300 ret_val = e1000_write_phy_reg(hw, 2301 IGP01E1000_PHY_PORT_CONFIG, phy_data); 2302 if (ret_val) 2303 return ret_val; 2304 } else if (hw->smart_speed == e1000_smart_speed_off) { 2305 ret_val = e1000_read_phy_reg(hw, 2306 IGP01E1000_PHY_PORT_CONFIG, &phy_data); 2307 if (ret_val) 2308 return ret_val; 2309 2310 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 2311 ret_val = e1000_write_phy_reg(hw, 2312 IGP01E1000_PHY_PORT_CONFIG, phy_data); 2313 if (ret_val) 2314 return ret_val; 2315 } 2316 2317 2318 } else { 2319 2320 if (hw->mac_type == e1000_ich8lan) { 2321 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU; 2322 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); 2323 } else { 2324 phy_data |= IGP02E1000_PM_D0_LPLU; 2325 ret_val = e1000_write_phy_reg(hw, 2326 IGP02E1000_PHY_POWER_MGMT, phy_data); 2327 if (ret_val) 2328 return ret_val; 2329 } 2330 2331 /* When LPLU is enabled we should disable SmartSpeed */ 2332 ret_val = e1000_read_phy_reg(hw, 2333 IGP01E1000_PHY_PORT_CONFIG, &phy_data); 2334 if (ret_val) 2335 return ret_val; 2336 2337 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 2338 ret_val = e1000_write_phy_reg(hw, 2339 IGP01E1000_PHY_PORT_CONFIG, phy_data); 2340 if (ret_val) 2341 return ret_val; 2342 2343 } 2344 return E1000_SUCCESS; 2345 } 2346 2347 /******************************************************************** 2348 * Copper link setup for e1000_phy_igp series. 2349 * 2350 * hw - Struct containing variables accessed by shared code 2351 *********************************************************************/ 2352 static int32_t 2353 e1000_copper_link_igp_setup(struct e1000_hw *hw) 2354 { 2355 uint32_t led_ctrl; 2356 int32_t ret_val; 2357 uint16_t phy_data; 2358 2359 DEBUGFUNC(); 2360 2361 if (hw->phy_reset_disable) 2362 return E1000_SUCCESS; 2363 2364 ret_val = e1000_phy_reset(hw); 2365 if (ret_val) { 2366 DEBUGOUT("Error Resetting the PHY\n"); 2367 return ret_val; 2368 } 2369 2370 /* Wait 15ms for MAC to configure PHY from eeprom settings */ 2371 mdelay(15); 2372 if (hw->mac_type != e1000_ich8lan) { 2373 /* Configure activity LED after PHY reset */ 2374 led_ctrl = E1000_READ_REG(hw, LEDCTL); 2375 led_ctrl &= IGP_ACTIVITY_LED_MASK; 2376 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); 2377 E1000_WRITE_REG(hw, LEDCTL, led_ctrl); 2378 } 2379 2380 /* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */ 2381 if (hw->phy_type == e1000_phy_igp) { 2382 /* disable lplu d3 during driver init */ 2383 ret_val = e1000_set_d3_lplu_state(hw, false); 2384 if (ret_val) { 2385 DEBUGOUT("Error Disabling LPLU D3\n"); 2386 return ret_val; 2387 } 2388 } 2389 2390 /* disable lplu d0 during driver init */ 2391 ret_val = e1000_set_d0_lplu_state(hw, false); 2392 if (ret_val) { 2393 DEBUGOUT("Error Disabling LPLU D0\n"); 2394 return ret_val; 2395 } 2396 /* Configure mdi-mdix settings */ 2397 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); 2398 if (ret_val) 2399 return ret_val; 2400 2401 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { 2402 hw->dsp_config_state = e1000_dsp_config_disabled; 2403 /* Force MDI for earlier revs of the IGP PHY */ 2404 phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX 2405 | IGP01E1000_PSCR_FORCE_MDI_MDIX); 2406 hw->mdix = 1; 2407 2408 } else { 2409 hw->dsp_config_state = e1000_dsp_config_enabled; 2410 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; 2411 2412 switch (hw->mdix) { 2413 case 1: 2414 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; 2415 break; 2416 case 2: 2417 phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX; 2418 break; 2419 case 0: 2420 default: 2421 phy_data |= IGP01E1000_PSCR_AUTO_MDIX; 2422 break; 2423 } 2424 } 2425 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); 2426 if (ret_val) 2427 return ret_val; 2428 2429 /* set auto-master slave resolution settings */ 2430 if (hw->autoneg) { 2431 e1000_ms_type phy_ms_setting = hw->master_slave; 2432 2433 if (hw->ffe_config_state == e1000_ffe_config_active) 2434 hw->ffe_config_state = e1000_ffe_config_enabled; 2435 2436 if (hw->dsp_config_state == e1000_dsp_config_activated) 2437 hw->dsp_config_state = e1000_dsp_config_enabled; 2438 2439 /* when autonegotiation advertisment is only 1000Mbps then we 2440 * should disable SmartSpeed and enable Auto MasterSlave 2441 * resolution as hardware default. */ 2442 if (hw->autoneg_advertised == ADVERTISE_1000_FULL) { 2443 /* Disable SmartSpeed */ 2444 ret_val = e1000_read_phy_reg(hw, 2445 IGP01E1000_PHY_PORT_CONFIG, &phy_data); 2446 if (ret_val) 2447 return ret_val; 2448 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 2449 ret_val = e1000_write_phy_reg(hw, 2450 IGP01E1000_PHY_PORT_CONFIG, phy_data); 2451 if (ret_val) 2452 return ret_val; 2453 /* Set auto Master/Slave resolution process */ 2454 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, 2455 &phy_data); 2456 if (ret_val) 2457 return ret_val; 2458 phy_data &= ~CR_1000T_MS_ENABLE; 2459 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, 2460 phy_data); 2461 if (ret_val) 2462 return ret_val; 2463 } 2464 2465 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data); 2466 if (ret_val) 2467 return ret_val; 2468 2469 /* load defaults for future use */ 2470 hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ? 2471 ((phy_data & CR_1000T_MS_VALUE) ? 2472 e1000_ms_force_master : 2473 e1000_ms_force_slave) : 2474 e1000_ms_auto; 2475 2476 switch (phy_ms_setting) { 2477 case e1000_ms_force_master: 2478 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE); 2479 break; 2480 case e1000_ms_force_slave: 2481 phy_data |= CR_1000T_MS_ENABLE; 2482 phy_data &= ~(CR_1000T_MS_VALUE); 2483 break; 2484 case e1000_ms_auto: 2485 phy_data &= ~CR_1000T_MS_ENABLE; 2486 default: 2487 break; 2488 } 2489 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data); 2490 if (ret_val) 2491 return ret_val; 2492 } 2493 2494 return E1000_SUCCESS; 2495 } 2496 2497 /***************************************************************************** 2498 * This function checks the mode of the firmware. 2499 * 2500 * returns - true when the mode is IAMT or false. 2501 ****************************************************************************/ 2502 bool 2503 e1000_check_mng_mode(struct e1000_hw *hw) 2504 { 2505 uint32_t fwsm; 2506 DEBUGFUNC(); 2507 2508 fwsm = E1000_READ_REG(hw, FWSM); 2509 2510 if (hw->mac_type == e1000_ich8lan) { 2511 if ((fwsm & E1000_FWSM_MODE_MASK) == 2512 (E1000_MNG_ICH_IAMT_MODE << E1000_FWSM_MODE_SHIFT)) 2513 return true; 2514 } else if ((fwsm & E1000_FWSM_MODE_MASK) == 2515 (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT)) 2516 return true; 2517 2518 return false; 2519 } 2520 2521 static int32_t 2522 e1000_write_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t data) 2523 { 2524 uint16_t swfw = E1000_SWFW_PHY0_SM; 2525 uint32_t reg_val; 2526 DEBUGFUNC(); 2527 2528 if (e1000_is_second_port(hw)) 2529 swfw = E1000_SWFW_PHY1_SM; 2530 2531 if (e1000_swfw_sync_acquire(hw, swfw)) 2532 return -E1000_ERR_SWFW_SYNC; 2533 2534 reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) 2535 & E1000_KUMCTRLSTA_OFFSET) | data; 2536 E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val); 2537 udelay(2); 2538 2539 return E1000_SUCCESS; 2540 } 2541 2542 static int32_t 2543 e1000_read_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *data) 2544 { 2545 uint16_t swfw = E1000_SWFW_PHY0_SM; 2546 uint32_t reg_val; 2547 DEBUGFUNC(); 2548 2549 if (e1000_is_second_port(hw)) 2550 swfw = E1000_SWFW_PHY1_SM; 2551 2552 if (e1000_swfw_sync_acquire(hw, swfw)) 2553 return -E1000_ERR_SWFW_SYNC; 2554 2555 /* Write register address */ 2556 reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) & 2557 E1000_KUMCTRLSTA_OFFSET) | E1000_KUMCTRLSTA_REN; 2558 E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val); 2559 udelay(2); 2560 2561 /* Read the data returned */ 2562 reg_val = E1000_READ_REG(hw, KUMCTRLSTA); 2563 *data = (uint16_t)reg_val; 2564 2565 return E1000_SUCCESS; 2566 } 2567 2568 /******************************************************************** 2569 * Copper link setup for e1000_phy_gg82563 series. 2570 * 2571 * hw - Struct containing variables accessed by shared code 2572 *********************************************************************/ 2573 static int32_t 2574 e1000_copper_link_ggp_setup(struct e1000_hw *hw) 2575 { 2576 int32_t ret_val; 2577 uint16_t phy_data; 2578 uint32_t reg_data; 2579 2580 DEBUGFUNC(); 2581 2582 if (!hw->phy_reset_disable) { 2583 /* Enable CRS on TX for half-duplex operation. */ 2584 ret_val = e1000_read_phy_reg(hw, 2585 GG82563_PHY_MAC_SPEC_CTRL, &phy_data); 2586 if (ret_val) 2587 return ret_val; 2588 2589 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX; 2590 /* Use 25MHz for both link down and 1000BASE-T for Tx clock */ 2591 phy_data |= GG82563_MSCR_TX_CLK_1000MBPS_25MHZ; 2592 2593 ret_val = e1000_write_phy_reg(hw, 2594 GG82563_PHY_MAC_SPEC_CTRL, phy_data); 2595 if (ret_val) 2596 return ret_val; 2597 2598 /* Options: 2599 * MDI/MDI-X = 0 (default) 2600 * 0 - Auto for all speeds 2601 * 1 - MDI mode 2602 * 2 - MDI-X mode 2603 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) 2604 */ 2605 ret_val = e1000_read_phy_reg(hw, 2606 GG82563_PHY_SPEC_CTRL, &phy_data); 2607 if (ret_val) 2608 return ret_val; 2609 2610 phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK; 2611 2612 switch (hw->mdix) { 2613 case 1: 2614 phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDI; 2615 break; 2616 case 2: 2617 phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDIX; 2618 break; 2619 case 0: 2620 default: 2621 phy_data |= GG82563_PSCR_CROSSOVER_MODE_AUTO; 2622 break; 2623 } 2624 2625 /* Options: 2626 * disable_polarity_correction = 0 (default) 2627 * Automatic Correction for Reversed Cable Polarity 2628 * 0 - Disabled 2629 * 1 - Enabled 2630 */ 2631 phy_data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE; 2632 ret_val = e1000_write_phy_reg(hw, 2633 GG82563_PHY_SPEC_CTRL, phy_data); 2634 2635 if (ret_val) 2636 return ret_val; 2637 2638 /* SW Reset the PHY so all changes take effect */ 2639 ret_val = e1000_phy_reset(hw); 2640 if (ret_val) { 2641 DEBUGOUT("Error Resetting the PHY\n"); 2642 return ret_val; 2643 } 2644 } /* phy_reset_disable */ 2645 2646 if (hw->mac_type == e1000_80003es2lan) { 2647 /* Bypass RX and TX FIFO's */ 2648 ret_val = e1000_write_kmrn_reg(hw, 2649 E1000_KUMCTRLSTA_OFFSET_FIFO_CTRL, 2650 E1000_KUMCTRLSTA_FIFO_CTRL_RX_BYPASS 2651 | E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS); 2652 if (ret_val) 2653 return ret_val; 2654 2655 ret_val = e1000_read_phy_reg(hw, 2656 GG82563_PHY_SPEC_CTRL_2, &phy_data); 2657 if (ret_val) 2658 return ret_val; 2659 2660 phy_data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG; 2661 ret_val = e1000_write_phy_reg(hw, 2662 GG82563_PHY_SPEC_CTRL_2, phy_data); 2663 2664 if (ret_val) 2665 return ret_val; 2666 2667 reg_data = E1000_READ_REG(hw, CTRL_EXT); 2668 reg_data &= ~(E1000_CTRL_EXT_LINK_MODE_MASK); 2669 E1000_WRITE_REG(hw, CTRL_EXT, reg_data); 2670 2671 ret_val = e1000_read_phy_reg(hw, 2672 GG82563_PHY_PWR_MGMT_CTRL, &phy_data); 2673 if (ret_val) 2674 return ret_val; 2675 2676 /* Do not init these registers when the HW is in IAMT mode, since the 2677 * firmware will have already initialized them. We only initialize 2678 * them if the HW is not in IAMT mode. 2679 */ 2680 if (e1000_check_mng_mode(hw) == false) { 2681 /* Enable Electrical Idle on the PHY */ 2682 phy_data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE; 2683 ret_val = e1000_write_phy_reg(hw, 2684 GG82563_PHY_PWR_MGMT_CTRL, phy_data); 2685 if (ret_val) 2686 return ret_val; 2687 2688 ret_val = e1000_read_phy_reg(hw, 2689 GG82563_PHY_KMRN_MODE_CTRL, &phy_data); 2690 if (ret_val) 2691 return ret_val; 2692 2693 phy_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; 2694 ret_val = e1000_write_phy_reg(hw, 2695 GG82563_PHY_KMRN_MODE_CTRL, phy_data); 2696 2697 if (ret_val) 2698 return ret_val; 2699 } 2700 2701 /* Workaround: Disable padding in Kumeran interface in the MAC 2702 * and in the PHY to avoid CRC errors. 2703 */ 2704 ret_val = e1000_read_phy_reg(hw, 2705 GG82563_PHY_INBAND_CTRL, &phy_data); 2706 if (ret_val) 2707 return ret_val; 2708 phy_data |= GG82563_ICR_DIS_PADDING; 2709 ret_val = e1000_write_phy_reg(hw, 2710 GG82563_PHY_INBAND_CTRL, phy_data); 2711 if (ret_val) 2712 return ret_val; 2713 } 2714 return E1000_SUCCESS; 2715 } 2716 2717 /******************************************************************** 2718 * Copper link setup for e1000_phy_m88 series. 2719 * 2720 * hw - Struct containing variables accessed by shared code 2721 *********************************************************************/ 2722 static int32_t 2723 e1000_copper_link_mgp_setup(struct e1000_hw *hw) 2724 { 2725 int32_t ret_val; 2726 uint16_t phy_data; 2727 2728 DEBUGFUNC(); 2729 2730 if (hw->phy_reset_disable) 2731 return E1000_SUCCESS; 2732 2733 /* Enable CRS on TX. This must be set for half-duplex operation. */ 2734 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 2735 if (ret_val) 2736 return ret_val; 2737 2738 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; 2739 2740 /* Options: 2741 * MDI/MDI-X = 0 (default) 2742 * 0 - Auto for all speeds 2743 * 1 - MDI mode 2744 * 2 - MDI-X mode 2745 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) 2746 */ 2747 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 2748 2749 switch (hw->mdix) { 2750 case 1: 2751 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; 2752 break; 2753 case 2: 2754 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; 2755 break; 2756 case 3: 2757 phy_data |= M88E1000_PSCR_AUTO_X_1000T; 2758 break; 2759 case 0: 2760 default: 2761 phy_data |= M88E1000_PSCR_AUTO_X_MODE; 2762 break; 2763 } 2764 2765 /* Options: 2766 * disable_polarity_correction = 0 (default) 2767 * Automatic Correction for Reversed Cable Polarity 2768 * 0 - Disabled 2769 * 1 - Enabled 2770 */ 2771 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; 2772 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 2773 if (ret_val) 2774 return ret_val; 2775 2776 if (hw->phy_revision < M88E1011_I_REV_4) { 2777 /* Force TX_CLK in the Extended PHY Specific Control Register 2778 * to 25MHz clock. 2779 */ 2780 ret_val = e1000_read_phy_reg(hw, 2781 M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); 2782 if (ret_val) 2783 return ret_val; 2784 2785 phy_data |= M88E1000_EPSCR_TX_CLK_25; 2786 2787 if ((hw->phy_revision == E1000_REVISION_2) && 2788 (hw->phy_id == M88E1111_I_PHY_ID)) { 2789 /* Vidalia Phy, set the downshift counter to 5x */ 2790 phy_data &= ~(M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK); 2791 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X; 2792 ret_val = e1000_write_phy_reg(hw, 2793 M88E1000_EXT_PHY_SPEC_CTRL, phy_data); 2794 if (ret_val) 2795 return ret_val; 2796 } else { 2797 /* Configure Master and Slave downshift values */ 2798 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 2799 | M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK); 2800 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X 2801 | M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X); 2802 ret_val = e1000_write_phy_reg(hw, 2803 M88E1000_EXT_PHY_SPEC_CTRL, phy_data); 2804 if (ret_val) 2805 return ret_val; 2806 } 2807 } 2808 2809 /* SW Reset the PHY so all changes take effect */ 2810 ret_val = e1000_phy_reset(hw); 2811 if (ret_val) { 2812 DEBUGOUT("Error Resetting the PHY\n"); 2813 return ret_val; 2814 } 2815 2816 return E1000_SUCCESS; 2817 } 2818 2819 /******************************************************************** 2820 * Setup auto-negotiation and flow control advertisements, 2821 * and then perform auto-negotiation. 2822 * 2823 * hw - Struct containing variables accessed by shared code 2824 *********************************************************************/ 2825 static int32_t 2826 e1000_copper_link_autoneg(struct e1000_hw *hw) 2827 { 2828 int32_t ret_val; 2829 uint16_t phy_data; 2830 2831 DEBUGFUNC(); 2832 2833 /* Perform some bounds checking on the hw->autoneg_advertised 2834 * parameter. If this variable is zero, then set it to the default. 2835 */ 2836 hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT; 2837 2838 /* If autoneg_advertised is zero, we assume it was not defaulted 2839 * by the calling code so we set to advertise full capability. 2840 */ 2841 if (hw->autoneg_advertised == 0) 2842 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT; 2843 2844 /* IFE phy only supports 10/100 */ 2845 if (hw->phy_type == e1000_phy_ife) 2846 hw->autoneg_advertised &= AUTONEG_ADVERTISE_10_100_ALL; 2847 2848 DEBUGOUT("Reconfiguring auto-neg advertisement params\n"); 2849 ret_val = e1000_phy_setup_autoneg(hw); 2850 if (ret_val) { 2851 DEBUGOUT("Error Setting up Auto-Negotiation\n"); 2852 return ret_val; 2853 } 2854 DEBUGOUT("Restarting Auto-Neg\n"); 2855 2856 /* Restart auto-negotiation by setting the Auto Neg Enable bit and 2857 * the Auto Neg Restart bit in the PHY control register. 2858 */ 2859 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data); 2860 if (ret_val) 2861 return ret_val; 2862 2863 phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); 2864 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data); 2865 if (ret_val) 2866 return ret_val; 2867 2868 /* Does the user want to wait for Auto-Neg to complete here, or 2869 * check at a later time (for example, callback routine). 2870 */ 2871 /* If we do not wait for autonegtation to complete I 2872 * do not see a valid link status. 2873 * wait_autoneg_complete = 1 . 2874 */ 2875 if (hw->wait_autoneg_complete) { 2876 ret_val = e1000_wait_autoneg(hw); 2877 if (ret_val) { 2878 DEBUGOUT("Error while waiting for autoneg" 2879 "to complete\n"); 2880 return ret_val; 2881 } 2882 } 2883 2884 hw->get_link_status = true; 2885 2886 return E1000_SUCCESS; 2887 } 2888 2889 /****************************************************************************** 2890 * Config the MAC and the PHY after link is up. 2891 * 1) Set up the MAC to the current PHY speed/duplex 2892 * if we are on 82543. If we 2893 * are on newer silicon, we only need to configure 2894 * collision distance in the Transmit Control Register. 2895 * 2) Set up flow control on the MAC to that established with 2896 * the link partner. 2897 * 3) Config DSP to improve Gigabit link quality for some PHY revisions. 2898 * 2899 * hw - Struct containing variables accessed by shared code 2900 ******************************************************************************/ 2901 static int32_t 2902 e1000_copper_link_postconfig(struct e1000_hw *hw) 2903 { 2904 int32_t ret_val; 2905 DEBUGFUNC(); 2906 2907 if (hw->mac_type >= e1000_82544) { 2908 e1000_config_collision_dist(hw); 2909 } else { 2910 ret_val = e1000_config_mac_to_phy(hw); 2911 if (ret_val) { 2912 DEBUGOUT("Error configuring MAC to PHY settings\n"); 2913 return ret_val; 2914 } 2915 } 2916 ret_val = e1000_config_fc_after_link_up(hw); 2917 if (ret_val) { 2918 DEBUGOUT("Error Configuring Flow Control\n"); 2919 return ret_val; 2920 } 2921 return E1000_SUCCESS; 2922 } 2923 2924 /****************************************************************************** 2925 * Detects which PHY is present and setup the speed and duplex 2926 * 2927 * hw - Struct containing variables accessed by shared code 2928 ******************************************************************************/ 2929 static int 2930 e1000_setup_copper_link(struct eth_device *nic) 2931 { 2932 struct e1000_hw *hw = nic->priv; 2933 int32_t ret_val; 2934 uint16_t i; 2935 uint16_t phy_data; 2936 uint16_t reg_data; 2937 2938 DEBUGFUNC(); 2939 2940 switch (hw->mac_type) { 2941 case e1000_80003es2lan: 2942 case e1000_ich8lan: 2943 /* Set the mac to wait the maximum time between each 2944 * iteration and increase the max iterations when 2945 * polling the phy; this fixes erroneous timeouts at 10Mbps. */ 2946 ret_val = e1000_write_kmrn_reg(hw, 2947 GG82563_REG(0x34, 4), 0xFFFF); 2948 if (ret_val) 2949 return ret_val; 2950 ret_val = e1000_read_kmrn_reg(hw, 2951 GG82563_REG(0x34, 9), ®_data); 2952 if (ret_val) 2953 return ret_val; 2954 reg_data |= 0x3F; 2955 ret_val = e1000_write_kmrn_reg(hw, 2956 GG82563_REG(0x34, 9), reg_data); 2957 if (ret_val) 2958 return ret_val; 2959 default: 2960 break; 2961 } 2962 2963 /* Check if it is a valid PHY and set PHY mode if necessary. */ 2964 ret_val = e1000_copper_link_preconfig(hw); 2965 if (ret_val) 2966 return ret_val; 2967 switch (hw->mac_type) { 2968 case e1000_80003es2lan: 2969 /* Kumeran registers are written-only */ 2970 reg_data = 2971 E1000_KUMCTRLSTA_INB_CTRL_LINK_STATUS_TX_TIMEOUT_DEFAULT; 2972 reg_data |= E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING; 2973 ret_val = e1000_write_kmrn_reg(hw, 2974 E1000_KUMCTRLSTA_OFFSET_INB_CTRL, reg_data); 2975 if (ret_val) 2976 return ret_val; 2977 break; 2978 default: 2979 break; 2980 } 2981 2982 if (hw->phy_type == e1000_phy_igp || 2983 hw->phy_type == e1000_phy_igp_3 || 2984 hw->phy_type == e1000_phy_igp_2) { 2985 ret_val = e1000_copper_link_igp_setup(hw); 2986 if (ret_val) 2987 return ret_val; 2988 } else if (hw->phy_type == e1000_phy_m88) { 2989 ret_val = e1000_copper_link_mgp_setup(hw); 2990 if (ret_val) 2991 return ret_val; 2992 } else if (hw->phy_type == e1000_phy_gg82563) { 2993 ret_val = e1000_copper_link_ggp_setup(hw); 2994 if (ret_val) 2995 return ret_val; 2996 } 2997 2998 /* always auto */ 2999 /* Setup autoneg and flow control advertisement 3000 * and perform autonegotiation */ 3001 ret_val = e1000_copper_link_autoneg(hw); 3002 if (ret_val) 3003 return ret_val; 3004 3005 /* Check link status. Wait up to 100 microseconds for link to become 3006 * valid. 3007 */ 3008 for (i = 0; i < 10; i++) { 3009 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); 3010 if (ret_val) 3011 return ret_val; 3012 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); 3013 if (ret_val) 3014 return ret_val; 3015 3016 if (phy_data & MII_SR_LINK_STATUS) { 3017 /* Config the MAC and PHY after link is up */ 3018 ret_val = e1000_copper_link_postconfig(hw); 3019 if (ret_val) 3020 return ret_val; 3021 3022 DEBUGOUT("Valid link established!!!\n"); 3023 return E1000_SUCCESS; 3024 } 3025 udelay(10); 3026 } 3027 3028 DEBUGOUT("Unable to establish link!!!\n"); 3029 return E1000_SUCCESS; 3030 } 3031 3032 /****************************************************************************** 3033 * Configures PHY autoneg and flow control advertisement settings 3034 * 3035 * hw - Struct containing variables accessed by shared code 3036 ******************************************************************************/ 3037 int32_t 3038 e1000_phy_setup_autoneg(struct e1000_hw *hw) 3039 { 3040 int32_t ret_val; 3041 uint16_t mii_autoneg_adv_reg; 3042 uint16_t mii_1000t_ctrl_reg; 3043 3044 DEBUGFUNC(); 3045 3046 /* Read the MII Auto-Neg Advertisement Register (Address 4). */ 3047 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg); 3048 if (ret_val) 3049 return ret_val; 3050 3051 if (hw->phy_type != e1000_phy_ife) { 3052 /* Read the MII 1000Base-T Control Register (Address 9). */ 3053 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, 3054 &mii_1000t_ctrl_reg); 3055 if (ret_val) 3056 return ret_val; 3057 } else 3058 mii_1000t_ctrl_reg = 0; 3059 3060 /* Need to parse both autoneg_advertised and fc and set up 3061 * the appropriate PHY registers. First we will parse for 3062 * autoneg_advertised software override. Since we can advertise 3063 * a plethora of combinations, we need to check each bit 3064 * individually. 3065 */ 3066 3067 /* First we clear all the 10/100 mb speed bits in the Auto-Neg 3068 * Advertisement Register (Address 4) and the 1000 mb speed bits in 3069 * the 1000Base-T Control Register (Address 9). 3070 */ 3071 mii_autoneg_adv_reg &= ~REG4_SPEED_MASK; 3072 mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK; 3073 3074 DEBUGOUT("autoneg_advertised %x\n", hw->autoneg_advertised); 3075 3076 /* Do we want to advertise 10 Mb Half Duplex? */ 3077 if (hw->autoneg_advertised & ADVERTISE_10_HALF) { 3078 DEBUGOUT("Advertise 10mb Half duplex\n"); 3079 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS; 3080 } 3081 3082 /* Do we want to advertise 10 Mb Full Duplex? */ 3083 if (hw->autoneg_advertised & ADVERTISE_10_FULL) { 3084 DEBUGOUT("Advertise 10mb Full duplex\n"); 3085 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS; 3086 } 3087 3088 /* Do we want to advertise 100 Mb Half Duplex? */ 3089 if (hw->autoneg_advertised & ADVERTISE_100_HALF) { 3090 DEBUGOUT("Advertise 100mb Half duplex\n"); 3091 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS; 3092 } 3093 3094 /* Do we want to advertise 100 Mb Full Duplex? */ 3095 if (hw->autoneg_advertised & ADVERTISE_100_FULL) { 3096 DEBUGOUT("Advertise 100mb Full duplex\n"); 3097 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS; 3098 } 3099 3100 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */ 3101 if (hw->autoneg_advertised & ADVERTISE_1000_HALF) { 3102 DEBUGOUT 3103 ("Advertise 1000mb Half duplex requested, request denied!\n"); 3104 } 3105 3106 /* Do we want to advertise 1000 Mb Full Duplex? */ 3107 if (hw->autoneg_advertised & ADVERTISE_1000_FULL) { 3108 DEBUGOUT("Advertise 1000mb Full duplex\n"); 3109 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS; 3110 } 3111 3112 /* Check for a software override of the flow control settings, and 3113 * setup the PHY advertisement registers accordingly. If 3114 * auto-negotiation is enabled, then software will have to set the 3115 * "PAUSE" bits to the correct value in the Auto-Negotiation 3116 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation. 3117 * 3118 * The possible values of the "fc" parameter are: 3119 * 0: Flow control is completely disabled 3120 * 1: Rx flow control is enabled (we can receive pause frames 3121 * but not send pause frames). 3122 * 2: Tx flow control is enabled (we can send pause frames 3123 * but we do not support receiving pause frames). 3124 * 3: Both Rx and TX flow control (symmetric) are enabled. 3125 * other: No software override. The flow control configuration 3126 * in the EEPROM is used. 3127 */ 3128 switch (hw->fc) { 3129 case e1000_fc_none: /* 0 */ 3130 /* Flow control (RX & TX) is completely disabled by a 3131 * software over-ride. 3132 */ 3133 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 3134 break; 3135 case e1000_fc_rx_pause: /* 1 */ 3136 /* RX Flow control is enabled, and TX Flow control is 3137 * disabled, by a software over-ride. 3138 */ 3139 /* Since there really isn't a way to advertise that we are 3140 * capable of RX Pause ONLY, we will advertise that we 3141 * support both symmetric and asymmetric RX PAUSE. Later 3142 * (in e1000_config_fc_after_link_up) we will disable the 3143 *hw's ability to send PAUSE frames. 3144 */ 3145 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 3146 break; 3147 case e1000_fc_tx_pause: /* 2 */ 3148 /* TX Flow control is enabled, and RX Flow control is 3149 * disabled, by a software over-ride. 3150 */ 3151 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR; 3152 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE; 3153 break; 3154 case e1000_fc_full: /* 3 */ 3155 /* Flow control (both RX and TX) is enabled by a software 3156 * over-ride. 3157 */ 3158 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 3159 break; 3160 default: 3161 DEBUGOUT("Flow control param set incorrectly\n"); 3162 return -E1000_ERR_CONFIG; 3163 } 3164 3165 ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg); 3166 if (ret_val) 3167 return ret_val; 3168 3169 DEBUGOUT("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); 3170 3171 if (hw->phy_type != e1000_phy_ife) { 3172 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, 3173 mii_1000t_ctrl_reg); 3174 if (ret_val) 3175 return ret_val; 3176 } 3177 3178 return E1000_SUCCESS; 3179 } 3180 3181 /****************************************************************************** 3182 * Sets the collision distance in the Transmit Control register 3183 * 3184 * hw - Struct containing variables accessed by shared code 3185 * 3186 * Link should have been established previously. Reads the speed and duplex 3187 * information from the Device Status register. 3188 ******************************************************************************/ 3189 static void 3190 e1000_config_collision_dist(struct e1000_hw *hw) 3191 { 3192 uint32_t tctl, coll_dist; 3193 3194 DEBUGFUNC(); 3195 3196 if (hw->mac_type < e1000_82543) 3197 coll_dist = E1000_COLLISION_DISTANCE_82542; 3198 else 3199 coll_dist = E1000_COLLISION_DISTANCE; 3200 3201 tctl = E1000_READ_REG(hw, TCTL); 3202 3203 tctl &= ~E1000_TCTL_COLD; 3204 tctl |= coll_dist << E1000_COLD_SHIFT; 3205 3206 E1000_WRITE_REG(hw, TCTL, tctl); 3207 E1000_WRITE_FLUSH(hw); 3208 } 3209 3210 /****************************************************************************** 3211 * Sets MAC speed and duplex settings to reflect the those in the PHY 3212 * 3213 * hw - Struct containing variables accessed by shared code 3214 * mii_reg - data to write to the MII control register 3215 * 3216 * The contents of the PHY register containing the needed information need to 3217 * be passed in. 3218 ******************************************************************************/ 3219 static int 3220 e1000_config_mac_to_phy(struct e1000_hw *hw) 3221 { 3222 uint32_t ctrl; 3223 uint16_t phy_data; 3224 3225 DEBUGFUNC(); 3226 3227 /* Read the Device Control Register and set the bits to Force Speed 3228 * and Duplex. 3229 */ 3230 ctrl = E1000_READ_REG(hw, CTRL); 3231 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 3232 ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS); 3233 3234 /* Set up duplex in the Device Control and Transmit Control 3235 * registers depending on negotiated values. 3236 */ 3237 if (e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data) < 0) { 3238 DEBUGOUT("PHY Read Error\n"); 3239 return -E1000_ERR_PHY; 3240 } 3241 if (phy_data & M88E1000_PSSR_DPLX) 3242 ctrl |= E1000_CTRL_FD; 3243 else 3244 ctrl &= ~E1000_CTRL_FD; 3245 3246 e1000_config_collision_dist(hw); 3247 3248 /* Set up speed in the Device Control register depending on 3249 * negotiated values. 3250 */ 3251 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) 3252 ctrl |= E1000_CTRL_SPD_1000; 3253 else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS) 3254 ctrl |= E1000_CTRL_SPD_100; 3255 /* Write the configured values back to the Device Control Reg. */ 3256 E1000_WRITE_REG(hw, CTRL, ctrl); 3257 return 0; 3258 } 3259 3260 /****************************************************************************** 3261 * Forces the MAC's flow control settings. 3262 * 3263 * hw - Struct containing variables accessed by shared code 3264 * 3265 * Sets the TFCE and RFCE bits in the device control register to reflect 3266 * the adapter settings. TFCE and RFCE need to be explicitly set by 3267 * software when a Copper PHY is used because autonegotiation is managed 3268 * by the PHY rather than the MAC. Software must also configure these 3269 * bits when link is forced on a fiber connection. 3270 *****************************************************************************/ 3271 static int 3272 e1000_force_mac_fc(struct e1000_hw *hw) 3273 { 3274 uint32_t ctrl; 3275 3276 DEBUGFUNC(); 3277 3278 /* Get the current configuration of the Device Control Register */ 3279 ctrl = E1000_READ_REG(hw, CTRL); 3280 3281 /* Because we didn't get link via the internal auto-negotiation 3282 * mechanism (we either forced link or we got link via PHY 3283 * auto-neg), we have to manually enable/disable transmit an 3284 * receive flow control. 3285 * 3286 * The "Case" statement below enables/disable flow control 3287 * according to the "hw->fc" parameter. 3288 * 3289 * The possible values of the "fc" parameter are: 3290 * 0: Flow control is completely disabled 3291 * 1: Rx flow control is enabled (we can receive pause 3292 * frames but not send pause frames). 3293 * 2: Tx flow control is enabled (we can send pause frames 3294 * frames but we do not receive pause frames). 3295 * 3: Both Rx and TX flow control (symmetric) is enabled. 3296 * other: No other values should be possible at this point. 3297 */ 3298 3299 switch (hw->fc) { 3300 case e1000_fc_none: 3301 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE)); 3302 break; 3303 case e1000_fc_rx_pause: 3304 ctrl &= (~E1000_CTRL_TFCE); 3305 ctrl |= E1000_CTRL_RFCE; 3306 break; 3307 case e1000_fc_tx_pause: 3308 ctrl &= (~E1000_CTRL_RFCE); 3309 ctrl |= E1000_CTRL_TFCE; 3310 break; 3311 case e1000_fc_full: 3312 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE); 3313 break; 3314 default: 3315 DEBUGOUT("Flow control param set incorrectly\n"); 3316 return -E1000_ERR_CONFIG; 3317 } 3318 3319 /* Disable TX Flow Control for 82542 (rev 2.0) */ 3320 if (hw->mac_type == e1000_82542_rev2_0) 3321 ctrl &= (~E1000_CTRL_TFCE); 3322 3323 E1000_WRITE_REG(hw, CTRL, ctrl); 3324 return 0; 3325 } 3326 3327 /****************************************************************************** 3328 * Configures flow control settings after link is established 3329 * 3330 * hw - Struct containing variables accessed by shared code 3331 * 3332 * Should be called immediately after a valid link has been established. 3333 * Forces MAC flow control settings if link was forced. When in MII/GMII mode 3334 * and autonegotiation is enabled, the MAC flow control settings will be set 3335 * based on the flow control negotiated by the PHY. In TBI mode, the TFCE 3336 * and RFCE bits will be automaticaly set to the negotiated flow control mode. 3337 *****************************************************************************/ 3338 static int32_t 3339 e1000_config_fc_after_link_up(struct e1000_hw *hw) 3340 { 3341 int32_t ret_val; 3342 uint16_t mii_status_reg; 3343 uint16_t mii_nway_adv_reg; 3344 uint16_t mii_nway_lp_ability_reg; 3345 uint16_t speed; 3346 uint16_t duplex; 3347 3348 DEBUGFUNC(); 3349 3350 /* Check for the case where we have fiber media and auto-neg failed 3351 * so we had to force link. In this case, we need to force the 3352 * configuration of the MAC to match the "fc" parameter. 3353 */ 3354 if (((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed)) 3355 || ((hw->media_type == e1000_media_type_internal_serdes) 3356 && (hw->autoneg_failed)) 3357 || ((hw->media_type == e1000_media_type_copper) 3358 && (!hw->autoneg))) { 3359 ret_val = e1000_force_mac_fc(hw); 3360 if (ret_val < 0) { 3361 DEBUGOUT("Error forcing flow control settings\n"); 3362 return ret_val; 3363 } 3364 } 3365 3366 /* Check for the case where we have copper media and auto-neg is 3367 * enabled. In this case, we need to check and see if Auto-Neg 3368 * has completed, and if so, how the PHY and link partner has 3369 * flow control configured. 3370 */ 3371 if (hw->media_type == e1000_media_type_copper) { 3372 /* Read the MII Status Register and check to see if AutoNeg 3373 * has completed. We read this twice because this reg has 3374 * some "sticky" (latched) bits. 3375 */ 3376 if (e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) { 3377 DEBUGOUT("PHY Read Error \n"); 3378 return -E1000_ERR_PHY; 3379 } 3380 if (e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) { 3381 DEBUGOUT("PHY Read Error \n"); 3382 return -E1000_ERR_PHY; 3383 } 3384 3385 if (mii_status_reg & MII_SR_AUTONEG_COMPLETE) { 3386 /* The AutoNeg process has completed, so we now need to 3387 * read both the Auto Negotiation Advertisement Register 3388 * (Address 4) and the Auto_Negotiation Base Page Ability 3389 * Register (Address 5) to determine how flow control was 3390 * negotiated. 3391 */ 3392 if (e1000_read_phy_reg 3393 (hw, PHY_AUTONEG_ADV, &mii_nway_adv_reg) < 0) { 3394 DEBUGOUT("PHY Read Error\n"); 3395 return -E1000_ERR_PHY; 3396 } 3397 if (e1000_read_phy_reg 3398 (hw, PHY_LP_ABILITY, 3399 &mii_nway_lp_ability_reg) < 0) { 3400 DEBUGOUT("PHY Read Error\n"); 3401 return -E1000_ERR_PHY; 3402 } 3403 3404 /* Two bits in the Auto Negotiation Advertisement Register 3405 * (Address 4) and two bits in the Auto Negotiation Base 3406 * Page Ability Register (Address 5) determine flow control 3407 * for both the PHY and the link partner. The following 3408 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25, 3409 * 1999, describes these PAUSE resolution bits and how flow 3410 * control is determined based upon these settings. 3411 * NOTE: DC = Don't Care 3412 * 3413 * LOCAL DEVICE | LINK PARTNER 3414 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution 3415 *-------|---------|-------|---------|-------------------- 3416 * 0 | 0 | DC | DC | e1000_fc_none 3417 * 0 | 1 | 0 | DC | e1000_fc_none 3418 * 0 | 1 | 1 | 0 | e1000_fc_none 3419 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 3420 * 1 | 0 | 0 | DC | e1000_fc_none 3421 * 1 | DC | 1 | DC | e1000_fc_full 3422 * 1 | 1 | 0 | 0 | e1000_fc_none 3423 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 3424 * 3425 */ 3426 /* Are both PAUSE bits set to 1? If so, this implies 3427 * Symmetric Flow Control is enabled at both ends. The 3428 * ASM_DIR bits are irrelevant per the spec. 3429 * 3430 * For Symmetric Flow Control: 3431 * 3432 * LOCAL DEVICE | LINK PARTNER 3433 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 3434 *-------|---------|-------|---------|-------------------- 3435 * 1 | DC | 1 | DC | e1000_fc_full 3436 * 3437 */ 3438 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 3439 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) { 3440 /* Now we need to check if the user selected RX ONLY 3441 * of pause frames. In this case, we had to advertise 3442 * FULL flow control because we could not advertise RX 3443 * ONLY. Hence, we must now check to see if we need to 3444 * turn OFF the TRANSMISSION of PAUSE frames. 3445 */ 3446 if (hw->original_fc == e1000_fc_full) { 3447 hw->fc = e1000_fc_full; 3448 DEBUGOUT("Flow Control = FULL.\r\n"); 3449 } else { 3450 hw->fc = e1000_fc_rx_pause; 3451 DEBUGOUT 3452 ("Flow Control = RX PAUSE frames only.\r\n"); 3453 } 3454 } 3455 /* For receiving PAUSE frames ONLY. 3456 * 3457 * LOCAL DEVICE | LINK PARTNER 3458 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 3459 *-------|---------|-------|---------|-------------------- 3460 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 3461 * 3462 */ 3463 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) && 3464 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 3465 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 3466 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) 3467 { 3468 hw->fc = e1000_fc_tx_pause; 3469 DEBUGOUT 3470 ("Flow Control = TX PAUSE frames only.\r\n"); 3471 } 3472 /* For transmitting PAUSE frames ONLY. 3473 * 3474 * LOCAL DEVICE | LINK PARTNER 3475 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 3476 *-------|---------|-------|---------|-------------------- 3477 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 3478 * 3479 */ 3480 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 3481 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 3482 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 3483 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) 3484 { 3485 hw->fc = e1000_fc_rx_pause; 3486 DEBUGOUT 3487 ("Flow Control = RX PAUSE frames only.\r\n"); 3488 } 3489 /* Per the IEEE spec, at this point flow control should be 3490 * disabled. However, we want to consider that we could 3491 * be connected to a legacy switch that doesn't advertise 3492 * desired flow control, but can be forced on the link 3493 * partner. So if we advertised no flow control, that is 3494 * what we will resolve to. If we advertised some kind of 3495 * receive capability (Rx Pause Only or Full Flow Control) 3496 * and the link partner advertised none, we will configure 3497 * ourselves to enable Rx Flow Control only. We can do 3498 * this safely for two reasons: If the link partner really 3499 * didn't want flow control enabled, and we enable Rx, no 3500 * harm done since we won't be receiving any PAUSE frames 3501 * anyway. If the intent on the link partner was to have 3502 * flow control enabled, then by us enabling RX only, we 3503 * can at least receive pause frames and process them. 3504 * This is a good idea because in most cases, since we are 3505 * predominantly a server NIC, more times than not we will 3506 * be asked to delay transmission of packets than asking 3507 * our link partner to pause transmission of frames. 3508 */ 3509 else if (hw->original_fc == e1000_fc_none || 3510 hw->original_fc == e1000_fc_tx_pause) { 3511 hw->fc = e1000_fc_none; 3512 DEBUGOUT("Flow Control = NONE.\r\n"); 3513 } else { 3514 hw->fc = e1000_fc_rx_pause; 3515 DEBUGOUT 3516 ("Flow Control = RX PAUSE frames only.\r\n"); 3517 } 3518 3519 /* Now we need to do one last check... If we auto- 3520 * negotiated to HALF DUPLEX, flow control should not be 3521 * enabled per IEEE 802.3 spec. 3522 */ 3523 e1000_get_speed_and_duplex(hw, &speed, &duplex); 3524 3525 if (duplex == HALF_DUPLEX) 3526 hw->fc = e1000_fc_none; 3527 3528 /* Now we call a subroutine to actually force the MAC 3529 * controller to use the correct flow control settings. 3530 */ 3531 ret_val = e1000_force_mac_fc(hw); 3532 if (ret_val < 0) { 3533 DEBUGOUT 3534 ("Error forcing flow control settings\n"); 3535 return ret_val; 3536 } 3537 } else { 3538 DEBUGOUT 3539 ("Copper PHY and Auto Neg has not completed.\r\n"); 3540 } 3541 } 3542 return E1000_SUCCESS; 3543 } 3544 3545 /****************************************************************************** 3546 * Checks to see if the link status of the hardware has changed. 3547 * 3548 * hw - Struct containing variables accessed by shared code 3549 * 3550 * Called by any function that needs to check the link status of the adapter. 3551 *****************************************************************************/ 3552 static int 3553 e1000_check_for_link(struct eth_device *nic) 3554 { 3555 struct e1000_hw *hw = nic->priv; 3556 uint32_t rxcw; 3557 uint32_t ctrl; 3558 uint32_t status; 3559 uint32_t rctl; 3560 uint32_t signal; 3561 int32_t ret_val; 3562 uint16_t phy_data; 3563 uint16_t lp_capability; 3564 3565 DEBUGFUNC(); 3566 3567 /* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be 3568 * set when the optics detect a signal. On older adapters, it will be 3569 * cleared when there is a signal 3570 */ 3571 ctrl = E1000_READ_REG(hw, CTRL); 3572 if ((hw->mac_type > e1000_82544) && !(ctrl & E1000_CTRL_ILOS)) 3573 signal = E1000_CTRL_SWDPIN1; 3574 else 3575 signal = 0; 3576 3577 status = E1000_READ_REG(hw, STATUS); 3578 rxcw = E1000_READ_REG(hw, RXCW); 3579 DEBUGOUT("ctrl: %#08x status %#08x rxcw %#08x\n", ctrl, status, rxcw); 3580 3581 /* If we have a copper PHY then we only want to go out to the PHY 3582 * registers to see if Auto-Neg has completed and/or if our link 3583 * status has changed. The get_link_status flag will be set if we 3584 * receive a Link Status Change interrupt or we have Rx Sequence 3585 * Errors. 3586 */ 3587 if ((hw->media_type == e1000_media_type_copper) && hw->get_link_status) { 3588 /* First we want to see if the MII Status Register reports 3589 * link. If so, then we want to get the current speed/duplex 3590 * of the PHY. 3591 * Read the register twice since the link bit is sticky. 3592 */ 3593 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) { 3594 DEBUGOUT("PHY Read Error\n"); 3595 return -E1000_ERR_PHY; 3596 } 3597 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) { 3598 DEBUGOUT("PHY Read Error\n"); 3599 return -E1000_ERR_PHY; 3600 } 3601 3602 if (phy_data & MII_SR_LINK_STATUS) { 3603 hw->get_link_status = false; 3604 } else { 3605 /* No link detected */ 3606 return -E1000_ERR_NOLINK; 3607 } 3608 3609 /* We have a M88E1000 PHY and Auto-Neg is enabled. If we 3610 * have Si on board that is 82544 or newer, Auto 3611 * Speed Detection takes care of MAC speed/duplex 3612 * configuration. So we only need to configure Collision 3613 * Distance in the MAC. Otherwise, we need to force 3614 * speed/duplex on the MAC to the current PHY speed/duplex 3615 * settings. 3616 */ 3617 if (hw->mac_type >= e1000_82544) 3618 e1000_config_collision_dist(hw); 3619 else { 3620 ret_val = e1000_config_mac_to_phy(hw); 3621 if (ret_val < 0) { 3622 DEBUGOUT 3623 ("Error configuring MAC to PHY settings\n"); 3624 return ret_val; 3625 } 3626 } 3627 3628 /* Configure Flow Control now that Auto-Neg has completed. First, we 3629 * need to restore the desired flow control settings because we may 3630 * have had to re-autoneg with a different link partner. 3631 */ 3632 ret_val = e1000_config_fc_after_link_up(hw); 3633 if (ret_val < 0) { 3634 DEBUGOUT("Error configuring flow control\n"); 3635 return ret_val; 3636 } 3637 3638 /* At this point we know that we are on copper and we have 3639 * auto-negotiated link. These are conditions for checking the link 3640 * parter capability register. We use the link partner capability to 3641 * determine if TBI Compatibility needs to be turned on or off. If 3642 * the link partner advertises any speed in addition to Gigabit, then 3643 * we assume that they are GMII-based, and TBI compatibility is not 3644 * needed. If no other speeds are advertised, we assume the link 3645 * partner is TBI-based, and we turn on TBI Compatibility. 3646 */ 3647 if (hw->tbi_compatibility_en) { 3648 if (e1000_read_phy_reg 3649 (hw, PHY_LP_ABILITY, &lp_capability) < 0) { 3650 DEBUGOUT("PHY Read Error\n"); 3651 return -E1000_ERR_PHY; 3652 } 3653 if (lp_capability & (NWAY_LPAR_10T_HD_CAPS | 3654 NWAY_LPAR_10T_FD_CAPS | 3655 NWAY_LPAR_100TX_HD_CAPS | 3656 NWAY_LPAR_100TX_FD_CAPS | 3657 NWAY_LPAR_100T4_CAPS)) { 3658 /* If our link partner advertises anything in addition to 3659 * gigabit, we do not need to enable TBI compatibility. 3660 */ 3661 if (hw->tbi_compatibility_on) { 3662 /* If we previously were in the mode, turn it off. */ 3663 rctl = E1000_READ_REG(hw, RCTL); 3664 rctl &= ~E1000_RCTL_SBP; 3665 E1000_WRITE_REG(hw, RCTL, rctl); 3666 hw->tbi_compatibility_on = false; 3667 } 3668 } else { 3669 /* If TBI compatibility is was previously off, turn it on. For 3670 * compatibility with a TBI link partner, we will store bad 3671 * packets. Some frames have an additional byte on the end and 3672 * will look like CRC errors to to the hardware. 3673 */ 3674 if (!hw->tbi_compatibility_on) { 3675 hw->tbi_compatibility_on = true; 3676 rctl = E1000_READ_REG(hw, RCTL); 3677 rctl |= E1000_RCTL_SBP; 3678 E1000_WRITE_REG(hw, RCTL, rctl); 3679 } 3680 } 3681 } 3682 } 3683 /* If we don't have link (auto-negotiation failed or link partner cannot 3684 * auto-negotiate), the cable is plugged in (we have signal), and our 3685 * link partner is not trying to auto-negotiate with us (we are receiving 3686 * idles or data), we need to force link up. We also need to give 3687 * auto-negotiation time to complete, in case the cable was just plugged 3688 * in. The autoneg_failed flag does this. 3689 */ 3690 else if ((hw->media_type == e1000_media_type_fiber) && 3691 (!(status & E1000_STATUS_LU)) && 3692 ((ctrl & E1000_CTRL_SWDPIN1) == signal) && 3693 (!(rxcw & E1000_RXCW_C))) { 3694 if (hw->autoneg_failed == 0) { 3695 hw->autoneg_failed = 1; 3696 return 0; 3697 } 3698 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\r\n"); 3699 3700 /* Disable auto-negotiation in the TXCW register */ 3701 E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE)); 3702 3703 /* Force link-up and also force full-duplex. */ 3704 ctrl = E1000_READ_REG(hw, CTRL); 3705 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 3706 E1000_WRITE_REG(hw, CTRL, ctrl); 3707 3708 /* Configure Flow Control after forcing link up. */ 3709 ret_val = e1000_config_fc_after_link_up(hw); 3710 if (ret_val < 0) { 3711 DEBUGOUT("Error configuring flow control\n"); 3712 return ret_val; 3713 } 3714 } 3715 /* If we are forcing link and we are receiving /C/ ordered sets, re-enable 3716 * auto-negotiation in the TXCW register and disable forced link in the 3717 * Device Control register in an attempt to auto-negotiate with our link 3718 * partner. 3719 */ 3720 else if ((hw->media_type == e1000_media_type_fiber) && 3721 (ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { 3722 DEBUGOUT 3723 ("RXing /C/, enable AutoNeg and stop forcing link.\r\n"); 3724 E1000_WRITE_REG(hw, TXCW, hw->txcw); 3725 E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU)); 3726 } 3727 return 0; 3728 } 3729 3730 /****************************************************************************** 3731 * Configure the MAC-to-PHY interface for 10/100Mbps 3732 * 3733 * hw - Struct containing variables accessed by shared code 3734 ******************************************************************************/ 3735 static int32_t 3736 e1000_configure_kmrn_for_10_100(struct e1000_hw *hw, uint16_t duplex) 3737 { 3738 int32_t ret_val = E1000_SUCCESS; 3739 uint32_t tipg; 3740 uint16_t reg_data; 3741 3742 DEBUGFUNC(); 3743 3744 reg_data = E1000_KUMCTRLSTA_HD_CTRL_10_100_DEFAULT; 3745 ret_val = e1000_write_kmrn_reg(hw, 3746 E1000_KUMCTRLSTA_OFFSET_HD_CTRL, reg_data); 3747 if (ret_val) 3748 return ret_val; 3749 3750 /* Configure Transmit Inter-Packet Gap */ 3751 tipg = E1000_READ_REG(hw, TIPG); 3752 tipg &= ~E1000_TIPG_IPGT_MASK; 3753 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_10_100; 3754 E1000_WRITE_REG(hw, TIPG, tipg); 3755 3756 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data); 3757 3758 if (ret_val) 3759 return ret_val; 3760 3761 if (duplex == HALF_DUPLEX) 3762 reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER; 3763 else 3764 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; 3765 3766 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data); 3767 3768 return ret_val; 3769 } 3770 3771 static int32_t 3772 e1000_configure_kmrn_for_1000(struct e1000_hw *hw) 3773 { 3774 int32_t ret_val = E1000_SUCCESS; 3775 uint16_t reg_data; 3776 uint32_t tipg; 3777 3778 DEBUGFUNC(); 3779 3780 reg_data = E1000_KUMCTRLSTA_HD_CTRL_1000_DEFAULT; 3781 ret_val = e1000_write_kmrn_reg(hw, 3782 E1000_KUMCTRLSTA_OFFSET_HD_CTRL, reg_data); 3783 if (ret_val) 3784 return ret_val; 3785 3786 /* Configure Transmit Inter-Packet Gap */ 3787 tipg = E1000_READ_REG(hw, TIPG); 3788 tipg &= ~E1000_TIPG_IPGT_MASK; 3789 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000; 3790 E1000_WRITE_REG(hw, TIPG, tipg); 3791 3792 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data); 3793 3794 if (ret_val) 3795 return ret_val; 3796 3797 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; 3798 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data); 3799 3800 return ret_val; 3801 } 3802 3803 /****************************************************************************** 3804 * Detects the current speed and duplex settings of the hardware. 3805 * 3806 * hw - Struct containing variables accessed by shared code 3807 * speed - Speed of the connection 3808 * duplex - Duplex setting of the connection 3809 *****************************************************************************/ 3810 static int 3811 e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t *speed, 3812 uint16_t *duplex) 3813 { 3814 uint32_t status; 3815 int32_t ret_val; 3816 uint16_t phy_data; 3817 3818 DEBUGFUNC(); 3819 3820 if (hw->mac_type >= e1000_82543) { 3821 status = E1000_READ_REG(hw, STATUS); 3822 if (status & E1000_STATUS_SPEED_1000) { 3823 *speed = SPEED_1000; 3824 DEBUGOUT("1000 Mbs, "); 3825 } else if (status & E1000_STATUS_SPEED_100) { 3826 *speed = SPEED_100; 3827 DEBUGOUT("100 Mbs, "); 3828 } else { 3829 *speed = SPEED_10; 3830 DEBUGOUT("10 Mbs, "); 3831 } 3832 3833 if (status & E1000_STATUS_FD) { 3834 *duplex = FULL_DUPLEX; 3835 DEBUGOUT("Full Duplex\r\n"); 3836 } else { 3837 *duplex = HALF_DUPLEX; 3838 DEBUGOUT(" Half Duplex\r\n"); 3839 } 3840 } else { 3841 DEBUGOUT("1000 Mbs, Full Duplex\r\n"); 3842 *speed = SPEED_1000; 3843 *duplex = FULL_DUPLEX; 3844 } 3845 3846 /* IGP01 PHY may advertise full duplex operation after speed downgrade 3847 * even if it is operating at half duplex. Here we set the duplex 3848 * settings to match the duplex in the link partner's capabilities. 3849 */ 3850 if (hw->phy_type == e1000_phy_igp && hw->speed_downgraded) { 3851 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data); 3852 if (ret_val) 3853 return ret_val; 3854 3855 if (!(phy_data & NWAY_ER_LP_NWAY_CAPS)) 3856 *duplex = HALF_DUPLEX; 3857 else { 3858 ret_val = e1000_read_phy_reg(hw, 3859 PHY_LP_ABILITY, &phy_data); 3860 if (ret_val) 3861 return ret_val; 3862 if ((*speed == SPEED_100 && 3863 !(phy_data & NWAY_LPAR_100TX_FD_CAPS)) 3864 || (*speed == SPEED_10 3865 && !(phy_data & NWAY_LPAR_10T_FD_CAPS))) 3866 *duplex = HALF_DUPLEX; 3867 } 3868 } 3869 3870 if ((hw->mac_type == e1000_80003es2lan) && 3871 (hw->media_type == e1000_media_type_copper)) { 3872 if (*speed == SPEED_1000) 3873 ret_val = e1000_configure_kmrn_for_1000(hw); 3874 else 3875 ret_val = e1000_configure_kmrn_for_10_100(hw, *duplex); 3876 if (ret_val) 3877 return ret_val; 3878 } 3879 return E1000_SUCCESS; 3880 } 3881 3882 /****************************************************************************** 3883 * Blocks until autoneg completes or times out (~4.5 seconds) 3884 * 3885 * hw - Struct containing variables accessed by shared code 3886 ******************************************************************************/ 3887 static int 3888 e1000_wait_autoneg(struct e1000_hw *hw) 3889 { 3890 uint16_t i; 3891 uint16_t phy_data; 3892 3893 DEBUGFUNC(); 3894 DEBUGOUT("Waiting for Auto-Neg to complete.\n"); 3895 3896 /* We will wait for autoneg to complete or 4.5 seconds to expire. */ 3897 for (i = PHY_AUTO_NEG_TIME; i > 0; i--) { 3898 /* Read the MII Status Register and wait for Auto-Neg 3899 * Complete bit to be set. 3900 */ 3901 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) { 3902 DEBUGOUT("PHY Read Error\n"); 3903 return -E1000_ERR_PHY; 3904 } 3905 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) { 3906 DEBUGOUT("PHY Read Error\n"); 3907 return -E1000_ERR_PHY; 3908 } 3909 if (phy_data & MII_SR_AUTONEG_COMPLETE) { 3910 DEBUGOUT("Auto-Neg complete.\n"); 3911 return 0; 3912 } 3913 mdelay(100); 3914 } 3915 DEBUGOUT("Auto-Neg timedout.\n"); 3916 return -E1000_ERR_TIMEOUT; 3917 } 3918 3919 /****************************************************************************** 3920 * Raises the Management Data Clock 3921 * 3922 * hw - Struct containing variables accessed by shared code 3923 * ctrl - Device control register's current value 3924 ******************************************************************************/ 3925 static void 3926 e1000_raise_mdi_clk(struct e1000_hw *hw, uint32_t * ctrl) 3927 { 3928 /* Raise the clock input to the Management Data Clock (by setting the MDC 3929 * bit), and then delay 2 microseconds. 3930 */ 3931 E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC)); 3932 E1000_WRITE_FLUSH(hw); 3933 udelay(2); 3934 } 3935 3936 /****************************************************************************** 3937 * Lowers the Management Data Clock 3938 * 3939 * hw - Struct containing variables accessed by shared code 3940 * ctrl - Device control register's current value 3941 ******************************************************************************/ 3942 static void 3943 e1000_lower_mdi_clk(struct e1000_hw *hw, uint32_t * ctrl) 3944 { 3945 /* Lower the clock input to the Management Data Clock (by clearing the MDC 3946 * bit), and then delay 2 microseconds. 3947 */ 3948 E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC)); 3949 E1000_WRITE_FLUSH(hw); 3950 udelay(2); 3951 } 3952 3953 /****************************************************************************** 3954 * Shifts data bits out to the PHY 3955 * 3956 * hw - Struct containing variables accessed by shared code 3957 * data - Data to send out to the PHY 3958 * count - Number of bits to shift out 3959 * 3960 * Bits are shifted out in MSB to LSB order. 3961 ******************************************************************************/ 3962 static void 3963 e1000_shift_out_mdi_bits(struct e1000_hw *hw, uint32_t data, uint16_t count) 3964 { 3965 uint32_t ctrl; 3966 uint32_t mask; 3967 3968 /* We need to shift "count" number of bits out to the PHY. So, the value 3969 * in the "data" parameter will be shifted out to the PHY one bit at a 3970 * time. In order to do this, "data" must be broken down into bits. 3971 */ 3972 mask = 0x01; 3973 mask <<= (count - 1); 3974 3975 ctrl = E1000_READ_REG(hw, CTRL); 3976 3977 /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */ 3978 ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR); 3979 3980 while (mask) { 3981 /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and 3982 * then raising and lowering the Management Data Clock. A "0" is 3983 * shifted out to the PHY by setting the MDIO bit to "0" and then 3984 * raising and lowering the clock. 3985 */ 3986 if (data & mask) 3987 ctrl |= E1000_CTRL_MDIO; 3988 else 3989 ctrl &= ~E1000_CTRL_MDIO; 3990 3991 E1000_WRITE_REG(hw, CTRL, ctrl); 3992 E1000_WRITE_FLUSH(hw); 3993 3994 udelay(2); 3995 3996 e1000_raise_mdi_clk(hw, &ctrl); 3997 e1000_lower_mdi_clk(hw, &ctrl); 3998 3999 mask = mask >> 1; 4000 } 4001 } 4002 4003 /****************************************************************************** 4004 * Shifts data bits in from the PHY 4005 * 4006 * hw - Struct containing variables accessed by shared code 4007 * 4008 * Bits are shifted in in MSB to LSB order. 4009 ******************************************************************************/ 4010 static uint16_t 4011 e1000_shift_in_mdi_bits(struct e1000_hw *hw) 4012 { 4013 uint32_t ctrl; 4014 uint16_t data = 0; 4015 uint8_t i; 4016 4017 /* In order to read a register from the PHY, we need to shift in a total 4018 * of 18 bits from the PHY. The first two bit (turnaround) times are used 4019 * to avoid contention on the MDIO pin when a read operation is performed. 4020 * These two bits are ignored by us and thrown away. Bits are "shifted in" 4021 * by raising the input to the Management Data Clock (setting the MDC bit), 4022 * and then reading the value of the MDIO bit. 4023 */ 4024 ctrl = E1000_READ_REG(hw, CTRL); 4025 4026 /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */ 4027 ctrl &= ~E1000_CTRL_MDIO_DIR; 4028 ctrl &= ~E1000_CTRL_MDIO; 4029 4030 E1000_WRITE_REG(hw, CTRL, ctrl); 4031 E1000_WRITE_FLUSH(hw); 4032 4033 /* Raise and Lower the clock before reading in the data. This accounts for 4034 * the turnaround bits. The first clock occurred when we clocked out the 4035 * last bit of the Register Address. 4036 */ 4037 e1000_raise_mdi_clk(hw, &ctrl); 4038 e1000_lower_mdi_clk(hw, &ctrl); 4039 4040 for (data = 0, i = 0; i < 16; i++) { 4041 data = data << 1; 4042 e1000_raise_mdi_clk(hw, &ctrl); 4043 ctrl = E1000_READ_REG(hw, CTRL); 4044 /* Check to see if we shifted in a "1". */ 4045 if (ctrl & E1000_CTRL_MDIO) 4046 data |= 1; 4047 e1000_lower_mdi_clk(hw, &ctrl); 4048 } 4049 4050 e1000_raise_mdi_clk(hw, &ctrl); 4051 e1000_lower_mdi_clk(hw, &ctrl); 4052 4053 return data; 4054 } 4055 4056 /***************************************************************************** 4057 * Reads the value from a PHY register 4058 * 4059 * hw - Struct containing variables accessed by shared code 4060 * reg_addr - address of the PHY register to read 4061 ******************************************************************************/ 4062 static int 4063 e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t * phy_data) 4064 { 4065 uint32_t i; 4066 uint32_t mdic = 0; 4067 const uint32_t phy_addr = 1; 4068 4069 if (reg_addr > MAX_PHY_REG_ADDRESS) { 4070 DEBUGOUT("PHY Address %d is out of range\n", reg_addr); 4071 return -E1000_ERR_PARAM; 4072 } 4073 4074 if (hw->mac_type > e1000_82543) { 4075 /* Set up Op-code, Phy Address, and register address in the MDI 4076 * Control register. The MAC will take care of interfacing with the 4077 * PHY to retrieve the desired data. 4078 */ 4079 mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) | 4080 (phy_addr << E1000_MDIC_PHY_SHIFT) | 4081 (E1000_MDIC_OP_READ)); 4082 4083 E1000_WRITE_REG(hw, MDIC, mdic); 4084 4085 /* Poll the ready bit to see if the MDI read completed */ 4086 for (i = 0; i < 64; i++) { 4087 udelay(10); 4088 mdic = E1000_READ_REG(hw, MDIC); 4089 if (mdic & E1000_MDIC_READY) 4090 break; 4091 } 4092 if (!(mdic & E1000_MDIC_READY)) { 4093 DEBUGOUT("MDI Read did not complete\n"); 4094 return -E1000_ERR_PHY; 4095 } 4096 if (mdic & E1000_MDIC_ERROR) { 4097 DEBUGOUT("MDI Error\n"); 4098 return -E1000_ERR_PHY; 4099 } 4100 *phy_data = (uint16_t) mdic; 4101 } else { 4102 /* We must first send a preamble through the MDIO pin to signal the 4103 * beginning of an MII instruction. This is done by sending 32 4104 * consecutive "1" bits. 4105 */ 4106 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); 4107 4108 /* Now combine the next few fields that are required for a read 4109 * operation. We use this method instead of calling the 4110 * e1000_shift_out_mdi_bits routine five different times. The format of 4111 * a MII read instruction consists of a shift out of 14 bits and is 4112 * defined as follows: 4113 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr> 4114 * followed by a shift in of 18 bits. This first two bits shifted in 4115 * are TurnAround bits used to avoid contention on the MDIO pin when a 4116 * READ operation is performed. These two bits are thrown away 4117 * followed by a shift in of 16 bits which contains the desired data. 4118 */ 4119 mdic = ((reg_addr) | (phy_addr << 5) | 4120 (PHY_OP_READ << 10) | (PHY_SOF << 12)); 4121 4122 e1000_shift_out_mdi_bits(hw, mdic, 14); 4123 4124 /* Now that we've shifted out the read command to the MII, we need to 4125 * "shift in" the 16-bit value (18 total bits) of the requested PHY 4126 * register address. 4127 */ 4128 *phy_data = e1000_shift_in_mdi_bits(hw); 4129 } 4130 return 0; 4131 } 4132 4133 /****************************************************************************** 4134 * Writes a value to a PHY register 4135 * 4136 * hw - Struct containing variables accessed by shared code 4137 * reg_addr - address of the PHY register to write 4138 * data - data to write to the PHY 4139 ******************************************************************************/ 4140 static int 4141 e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t phy_data) 4142 { 4143 uint32_t i; 4144 uint32_t mdic = 0; 4145 const uint32_t phy_addr = 1; 4146 4147 if (reg_addr > MAX_PHY_REG_ADDRESS) { 4148 DEBUGOUT("PHY Address %d is out of range\n", reg_addr); 4149 return -E1000_ERR_PARAM; 4150 } 4151 4152 if (hw->mac_type > e1000_82543) { 4153 /* Set up Op-code, Phy Address, register address, and data intended 4154 * for the PHY register in the MDI Control register. The MAC will take 4155 * care of interfacing with the PHY to send the desired data. 4156 */ 4157 mdic = (((uint32_t) phy_data) | 4158 (reg_addr << E1000_MDIC_REG_SHIFT) | 4159 (phy_addr << E1000_MDIC_PHY_SHIFT) | 4160 (E1000_MDIC_OP_WRITE)); 4161 4162 E1000_WRITE_REG(hw, MDIC, mdic); 4163 4164 /* Poll the ready bit to see if the MDI read completed */ 4165 for (i = 0; i < 64; i++) { 4166 udelay(10); 4167 mdic = E1000_READ_REG(hw, MDIC); 4168 if (mdic & E1000_MDIC_READY) 4169 break; 4170 } 4171 if (!(mdic & E1000_MDIC_READY)) { 4172 DEBUGOUT("MDI Write did not complete\n"); 4173 return -E1000_ERR_PHY; 4174 } 4175 } else { 4176 /* We'll need to use the SW defined pins to shift the write command 4177 * out to the PHY. We first send a preamble to the PHY to signal the 4178 * beginning of the MII instruction. This is done by sending 32 4179 * consecutive "1" bits. 4180 */ 4181 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); 4182 4183 /* Now combine the remaining required fields that will indicate a 4184 * write operation. We use this method instead of calling the 4185 * e1000_shift_out_mdi_bits routine for each field in the command. The 4186 * format of a MII write instruction is as follows: 4187 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>. 4188 */ 4189 mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) | 4190 (PHY_OP_WRITE << 12) | (PHY_SOF << 14)); 4191 mdic <<= 16; 4192 mdic |= (uint32_t) phy_data; 4193 4194 e1000_shift_out_mdi_bits(hw, mdic, 32); 4195 } 4196 return 0; 4197 } 4198 4199 /****************************************************************************** 4200 * Checks if PHY reset is blocked due to SOL/IDER session, for example. 4201 * Returning E1000_BLK_PHY_RESET isn't necessarily an error. But it's up to 4202 * the caller to figure out how to deal with it. 4203 * 4204 * hw - Struct containing variables accessed by shared code 4205 * 4206 * returns: - E1000_BLK_PHY_RESET 4207 * E1000_SUCCESS 4208 * 4209 *****************************************************************************/ 4210 int32_t 4211 e1000_check_phy_reset_block(struct e1000_hw *hw) 4212 { 4213 uint32_t manc = 0; 4214 uint32_t fwsm = 0; 4215 4216 if (hw->mac_type == e1000_ich8lan) { 4217 fwsm = E1000_READ_REG(hw, FWSM); 4218 return (fwsm & E1000_FWSM_RSPCIPHY) ? E1000_SUCCESS 4219 : E1000_BLK_PHY_RESET; 4220 } 4221 4222 if (hw->mac_type > e1000_82547_rev_2) 4223 manc = E1000_READ_REG(hw, MANC); 4224 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ? 4225 E1000_BLK_PHY_RESET : E1000_SUCCESS; 4226 } 4227 4228 /*************************************************************************** 4229 * Checks if the PHY configuration is done 4230 * 4231 * hw: Struct containing variables accessed by shared code 4232 * 4233 * returns: - E1000_ERR_RESET if fail to reset MAC 4234 * E1000_SUCCESS at any other case. 4235 * 4236 ***************************************************************************/ 4237 static int32_t 4238 e1000_get_phy_cfg_done(struct e1000_hw *hw) 4239 { 4240 int32_t timeout = PHY_CFG_TIMEOUT; 4241 uint32_t cfg_mask = E1000_EEPROM_CFG_DONE; 4242 4243 DEBUGFUNC(); 4244 4245 switch (hw->mac_type) { 4246 default: 4247 mdelay(10); 4248 break; 4249 4250 case e1000_80003es2lan: 4251 /* Separate *_CFG_DONE_* bit for each port */ 4252 if (e1000_is_second_port(hw)) 4253 cfg_mask = E1000_EEPROM_CFG_DONE_PORT_1; 4254 /* Fall Through */ 4255 4256 case e1000_82571: 4257 case e1000_82572: 4258 while (timeout) { 4259 if (E1000_READ_REG(hw, EEMNGCTL) & cfg_mask) 4260 break; 4261 else 4262 mdelay(1); 4263 timeout--; 4264 } 4265 if (!timeout) { 4266 DEBUGOUT("MNG configuration cycle has not " 4267 "completed.\n"); 4268 return -E1000_ERR_RESET; 4269 } 4270 break; 4271 } 4272 4273 return E1000_SUCCESS; 4274 } 4275 4276 /****************************************************************************** 4277 * Returns the PHY to the power-on reset state 4278 * 4279 * hw - Struct containing variables accessed by shared code 4280 ******************************************************************************/ 4281 int32_t 4282 e1000_phy_hw_reset(struct e1000_hw *hw) 4283 { 4284 uint16_t swfw = E1000_SWFW_PHY0_SM; 4285 uint32_t ctrl, ctrl_ext; 4286 uint32_t led_ctrl; 4287 int32_t ret_val; 4288 4289 DEBUGFUNC(); 4290 4291 /* In the case of the phy reset being blocked, it's not an error, we 4292 * simply return success without performing the reset. */ 4293 ret_val = e1000_check_phy_reset_block(hw); 4294 if (ret_val) 4295 return E1000_SUCCESS; 4296 4297 DEBUGOUT("Resetting Phy...\n"); 4298 4299 if (hw->mac_type > e1000_82543) { 4300 if (e1000_is_second_port(hw)) 4301 swfw = E1000_SWFW_PHY1_SM; 4302 4303 if (e1000_swfw_sync_acquire(hw, swfw)) { 4304 DEBUGOUT("Unable to acquire swfw sync\n"); 4305 return -E1000_ERR_SWFW_SYNC; 4306 } 4307 4308 /* Read the device control register and assert the E1000_CTRL_PHY_RST 4309 * bit. Then, take it out of reset. 4310 */ 4311 ctrl = E1000_READ_REG(hw, CTRL); 4312 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST); 4313 E1000_WRITE_FLUSH(hw); 4314 4315 if (hw->mac_type < e1000_82571) 4316 udelay(10); 4317 else 4318 udelay(100); 4319 4320 E1000_WRITE_REG(hw, CTRL, ctrl); 4321 E1000_WRITE_FLUSH(hw); 4322 4323 if (hw->mac_type >= e1000_82571) 4324 mdelay(10); 4325 4326 } else { 4327 /* Read the Extended Device Control Register, assert the PHY_RESET_DIR 4328 * bit to put the PHY into reset. Then, take it out of reset. 4329 */ 4330 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 4331 ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR; 4332 ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA; 4333 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 4334 E1000_WRITE_FLUSH(hw); 4335 mdelay(10); 4336 ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA; 4337 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 4338 E1000_WRITE_FLUSH(hw); 4339 } 4340 udelay(150); 4341 4342 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { 4343 /* Configure activity LED after PHY reset */ 4344 led_ctrl = E1000_READ_REG(hw, LEDCTL); 4345 led_ctrl &= IGP_ACTIVITY_LED_MASK; 4346 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); 4347 E1000_WRITE_REG(hw, LEDCTL, led_ctrl); 4348 } 4349 4350 /* Wait for FW to finish PHY configuration. */ 4351 ret_val = e1000_get_phy_cfg_done(hw); 4352 if (ret_val != E1000_SUCCESS) 4353 return ret_val; 4354 4355 return ret_val; 4356 } 4357 4358 /****************************************************************************** 4359 * IGP phy init script - initializes the GbE PHY 4360 * 4361 * hw - Struct containing variables accessed by shared code 4362 *****************************************************************************/ 4363 static void 4364 e1000_phy_init_script(struct e1000_hw *hw) 4365 { 4366 uint32_t ret_val; 4367 uint16_t phy_saved_data; 4368 DEBUGFUNC(); 4369 4370 if (hw->phy_init_script) { 4371 mdelay(20); 4372 4373 /* Save off the current value of register 0x2F5B to be 4374 * restored at the end of this routine. */ 4375 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data); 4376 4377 /* Disabled the PHY transmitter */ 4378 e1000_write_phy_reg(hw, 0x2F5B, 0x0003); 4379 4380 mdelay(20); 4381 4382 e1000_write_phy_reg(hw, 0x0000, 0x0140); 4383 4384 mdelay(5); 4385 4386 switch (hw->mac_type) { 4387 case e1000_82541: 4388 case e1000_82547: 4389 e1000_write_phy_reg(hw, 0x1F95, 0x0001); 4390 4391 e1000_write_phy_reg(hw, 0x1F71, 0xBD21); 4392 4393 e1000_write_phy_reg(hw, 0x1F79, 0x0018); 4394 4395 e1000_write_phy_reg(hw, 0x1F30, 0x1600); 4396 4397 e1000_write_phy_reg(hw, 0x1F31, 0x0014); 4398 4399 e1000_write_phy_reg(hw, 0x1F32, 0x161C); 4400 4401 e1000_write_phy_reg(hw, 0x1F94, 0x0003); 4402 4403 e1000_write_phy_reg(hw, 0x1F96, 0x003F); 4404 4405 e1000_write_phy_reg(hw, 0x2010, 0x0008); 4406 break; 4407 4408 case e1000_82541_rev_2: 4409 case e1000_82547_rev_2: 4410 e1000_write_phy_reg(hw, 0x1F73, 0x0099); 4411 break; 4412 default: 4413 break; 4414 } 4415 4416 e1000_write_phy_reg(hw, 0x0000, 0x3300); 4417 4418 mdelay(20); 4419 4420 /* Now enable the transmitter */ 4421 if (!ret_val) 4422 e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data); 4423 4424 if (hw->mac_type == e1000_82547) { 4425 uint16_t fused, fine, coarse; 4426 4427 /* Move to analog registers page */ 4428 e1000_read_phy_reg(hw, 4429 IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused); 4430 4431 if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) { 4432 e1000_read_phy_reg(hw, 4433 IGP01E1000_ANALOG_FUSE_STATUS, &fused); 4434 4435 fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK; 4436 coarse = fused 4437 & IGP01E1000_ANALOG_FUSE_COARSE_MASK; 4438 4439 if (coarse > 4440 IGP01E1000_ANALOG_FUSE_COARSE_THRESH) { 4441 coarse -= 4442 IGP01E1000_ANALOG_FUSE_COARSE_10; 4443 fine -= IGP01E1000_ANALOG_FUSE_FINE_1; 4444 } else if (coarse 4445 == IGP01E1000_ANALOG_FUSE_COARSE_THRESH) 4446 fine -= IGP01E1000_ANALOG_FUSE_FINE_10; 4447 4448 fused = (fused 4449 & IGP01E1000_ANALOG_FUSE_POLY_MASK) | 4450 (fine 4451 & IGP01E1000_ANALOG_FUSE_FINE_MASK) | 4452 (coarse 4453 & IGP01E1000_ANALOG_FUSE_COARSE_MASK); 4454 4455 e1000_write_phy_reg(hw, 4456 IGP01E1000_ANALOG_FUSE_CONTROL, fused); 4457 e1000_write_phy_reg(hw, 4458 IGP01E1000_ANALOG_FUSE_BYPASS, 4459 IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL); 4460 } 4461 } 4462 } 4463 } 4464 4465 /****************************************************************************** 4466 * Resets the PHY 4467 * 4468 * hw - Struct containing variables accessed by shared code 4469 * 4470 * Sets bit 15 of the MII Control register 4471 ******************************************************************************/ 4472 int32_t 4473 e1000_phy_reset(struct e1000_hw *hw) 4474 { 4475 int32_t ret_val; 4476 uint16_t phy_data; 4477 4478 DEBUGFUNC(); 4479 4480 /* In the case of the phy reset being blocked, it's not an error, we 4481 * simply return success without performing the reset. */ 4482 ret_val = e1000_check_phy_reset_block(hw); 4483 if (ret_val) 4484 return E1000_SUCCESS; 4485 4486 switch (hw->phy_type) { 4487 case e1000_phy_igp: 4488 case e1000_phy_igp_2: 4489 case e1000_phy_igp_3: 4490 case e1000_phy_ife: 4491 ret_val = e1000_phy_hw_reset(hw); 4492 if (ret_val) 4493 return ret_val; 4494 break; 4495 default: 4496 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data); 4497 if (ret_val) 4498 return ret_val; 4499 4500 phy_data |= MII_CR_RESET; 4501 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data); 4502 if (ret_val) 4503 return ret_val; 4504 4505 udelay(1); 4506 break; 4507 } 4508 4509 if (hw->phy_type == e1000_phy_igp || hw->phy_type == e1000_phy_igp_2) 4510 e1000_phy_init_script(hw); 4511 4512 return E1000_SUCCESS; 4513 } 4514 4515 static int e1000_set_phy_type (struct e1000_hw *hw) 4516 { 4517 DEBUGFUNC (); 4518 4519 if (hw->mac_type == e1000_undefined) 4520 return -E1000_ERR_PHY_TYPE; 4521 4522 switch (hw->phy_id) { 4523 case M88E1000_E_PHY_ID: 4524 case M88E1000_I_PHY_ID: 4525 case M88E1011_I_PHY_ID: 4526 case M88E1111_I_PHY_ID: 4527 hw->phy_type = e1000_phy_m88; 4528 break; 4529 case IGP01E1000_I_PHY_ID: 4530 if (hw->mac_type == e1000_82541 || 4531 hw->mac_type == e1000_82541_rev_2 || 4532 hw->mac_type == e1000_82547 || 4533 hw->mac_type == e1000_82547_rev_2) { 4534 hw->phy_type = e1000_phy_igp; 4535 break; 4536 } 4537 case IGP03E1000_E_PHY_ID: 4538 hw->phy_type = e1000_phy_igp_3; 4539 break; 4540 case IFE_E_PHY_ID: 4541 case IFE_PLUS_E_PHY_ID: 4542 case IFE_C_E_PHY_ID: 4543 hw->phy_type = e1000_phy_ife; 4544 break; 4545 case GG82563_E_PHY_ID: 4546 if (hw->mac_type == e1000_80003es2lan) { 4547 hw->phy_type = e1000_phy_gg82563; 4548 break; 4549 } 4550 case BME1000_E_PHY_ID: 4551 hw->phy_type = e1000_phy_bm; 4552 break; 4553 /* Fall Through */ 4554 default: 4555 /* Should never have loaded on this device */ 4556 hw->phy_type = e1000_phy_undefined; 4557 return -E1000_ERR_PHY_TYPE; 4558 } 4559 4560 return E1000_SUCCESS; 4561 } 4562 4563 /****************************************************************************** 4564 * Probes the expected PHY address for known PHY IDs 4565 * 4566 * hw - Struct containing variables accessed by shared code 4567 ******************************************************************************/ 4568 static int32_t 4569 e1000_detect_gig_phy(struct e1000_hw *hw) 4570 { 4571 int32_t phy_init_status, ret_val; 4572 uint16_t phy_id_high, phy_id_low; 4573 bool match = false; 4574 4575 DEBUGFUNC(); 4576 4577 /* The 82571 firmware may still be configuring the PHY. In this 4578 * case, we cannot access the PHY until the configuration is done. So 4579 * we explicitly set the PHY values. */ 4580 if (hw->mac_type == e1000_82571 || 4581 hw->mac_type == e1000_82572) { 4582 hw->phy_id = IGP01E1000_I_PHY_ID; 4583 hw->phy_type = e1000_phy_igp_2; 4584 return E1000_SUCCESS; 4585 } 4586 4587 /* ESB-2 PHY reads require e1000_phy_gg82563 to be set because of a 4588 * work- around that forces PHY page 0 to be set or the reads fail. 4589 * The rest of the code in this routine uses e1000_read_phy_reg to 4590 * read the PHY ID. So for ESB-2 we need to have this set so our 4591 * reads won't fail. If the attached PHY is not a e1000_phy_gg82563, 4592 * the routines below will figure this out as well. */ 4593 if (hw->mac_type == e1000_80003es2lan) 4594 hw->phy_type = e1000_phy_gg82563; 4595 4596 /* Read the PHY ID Registers to identify which PHY is onboard. */ 4597 ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high); 4598 if (ret_val) 4599 return ret_val; 4600 4601 hw->phy_id = (uint32_t) (phy_id_high << 16); 4602 udelay(20); 4603 ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low); 4604 if (ret_val) 4605 return ret_val; 4606 4607 hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK); 4608 hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK; 4609 4610 switch (hw->mac_type) { 4611 case e1000_82543: 4612 if (hw->phy_id == M88E1000_E_PHY_ID) 4613 match = true; 4614 break; 4615 case e1000_82544: 4616 if (hw->phy_id == M88E1000_I_PHY_ID) 4617 match = true; 4618 break; 4619 case e1000_82540: 4620 case e1000_82545: 4621 case e1000_82545_rev_3: 4622 case e1000_82546: 4623 case e1000_82546_rev_3: 4624 if (hw->phy_id == M88E1011_I_PHY_ID) 4625 match = true; 4626 break; 4627 case e1000_82541: 4628 case e1000_82541_rev_2: 4629 case e1000_82547: 4630 case e1000_82547_rev_2: 4631 if(hw->phy_id == IGP01E1000_I_PHY_ID) 4632 match = true; 4633 4634 break; 4635 case e1000_82573: 4636 if (hw->phy_id == M88E1111_I_PHY_ID) 4637 match = true; 4638 break; 4639 case e1000_82574: 4640 if (hw->phy_id == BME1000_E_PHY_ID) 4641 match = true; 4642 break; 4643 case e1000_80003es2lan: 4644 if (hw->phy_id == GG82563_E_PHY_ID) 4645 match = true; 4646 break; 4647 case e1000_ich8lan: 4648 if (hw->phy_id == IGP03E1000_E_PHY_ID) 4649 match = true; 4650 if (hw->phy_id == IFE_E_PHY_ID) 4651 match = true; 4652 if (hw->phy_id == IFE_PLUS_E_PHY_ID) 4653 match = true; 4654 if (hw->phy_id == IFE_C_E_PHY_ID) 4655 match = true; 4656 break; 4657 default: 4658 DEBUGOUT("Invalid MAC type %d\n", hw->mac_type); 4659 return -E1000_ERR_CONFIG; 4660 } 4661 4662 phy_init_status = e1000_set_phy_type(hw); 4663 4664 if ((match) && (phy_init_status == E1000_SUCCESS)) { 4665 DEBUGOUT("PHY ID 0x%X detected\n", hw->phy_id); 4666 return 0; 4667 } 4668 DEBUGOUT("Invalid PHY ID 0x%X\n", hw->phy_id); 4669 return -E1000_ERR_PHY; 4670 } 4671 4672 /***************************************************************************** 4673 * Set media type and TBI compatibility. 4674 * 4675 * hw - Struct containing variables accessed by shared code 4676 * **************************************************************************/ 4677 void 4678 e1000_set_media_type(struct e1000_hw *hw) 4679 { 4680 uint32_t status; 4681 4682 DEBUGFUNC(); 4683 4684 if (hw->mac_type != e1000_82543) { 4685 /* tbi_compatibility is only valid on 82543 */ 4686 hw->tbi_compatibility_en = false; 4687 } 4688 4689 switch (hw->device_id) { 4690 case E1000_DEV_ID_82545GM_SERDES: 4691 case E1000_DEV_ID_82546GB_SERDES: 4692 case E1000_DEV_ID_82571EB_SERDES: 4693 case E1000_DEV_ID_82571EB_SERDES_DUAL: 4694 case E1000_DEV_ID_82571EB_SERDES_QUAD: 4695 case E1000_DEV_ID_82572EI_SERDES: 4696 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT: 4697 hw->media_type = e1000_media_type_internal_serdes; 4698 break; 4699 default: 4700 switch (hw->mac_type) { 4701 case e1000_82542_rev2_0: 4702 case e1000_82542_rev2_1: 4703 hw->media_type = e1000_media_type_fiber; 4704 break; 4705 case e1000_ich8lan: 4706 case e1000_82573: 4707 case e1000_82574: 4708 /* The STATUS_TBIMODE bit is reserved or reused 4709 * for the this device. 4710 */ 4711 hw->media_type = e1000_media_type_copper; 4712 break; 4713 default: 4714 status = E1000_READ_REG(hw, STATUS); 4715 if (status & E1000_STATUS_TBIMODE) { 4716 hw->media_type = e1000_media_type_fiber; 4717 /* tbi_compatibility not valid on fiber */ 4718 hw->tbi_compatibility_en = false; 4719 } else { 4720 hw->media_type = e1000_media_type_copper; 4721 } 4722 break; 4723 } 4724 } 4725 } 4726 4727 /** 4728 * e1000_sw_init - Initialize general software structures (struct e1000_adapter) 4729 * 4730 * e1000_sw_init initializes the Adapter private data structure. 4731 * Fields are initialized based on PCI device information and 4732 * OS network device settings (MTU size). 4733 **/ 4734 4735 static int 4736 e1000_sw_init(struct eth_device *nic) 4737 { 4738 struct e1000_hw *hw = (typeof(hw)) nic->priv; 4739 int result; 4740 4741 /* PCI config space info */ 4742 pci_read_config_word(hw->pdev, PCI_VENDOR_ID, &hw->vendor_id); 4743 pci_read_config_word(hw->pdev, PCI_DEVICE_ID, &hw->device_id); 4744 pci_read_config_word(hw->pdev, PCI_SUBSYSTEM_VENDOR_ID, 4745 &hw->subsystem_vendor_id); 4746 pci_read_config_word(hw->pdev, PCI_SUBSYSTEM_ID, &hw->subsystem_id); 4747 4748 pci_read_config_byte(hw->pdev, PCI_REVISION_ID, &hw->revision_id); 4749 pci_read_config_word(hw->pdev, PCI_COMMAND, &hw->pci_cmd_word); 4750 4751 /* identify the MAC */ 4752 result = e1000_set_mac_type(hw); 4753 if (result) { 4754 E1000_ERR(hw->nic, "Unknown MAC Type\n"); 4755 return result; 4756 } 4757 4758 switch (hw->mac_type) { 4759 default: 4760 break; 4761 case e1000_82541: 4762 case e1000_82547: 4763 case e1000_82541_rev_2: 4764 case e1000_82547_rev_2: 4765 hw->phy_init_script = 1; 4766 break; 4767 } 4768 4769 /* flow control settings */ 4770 hw->fc_high_water = E1000_FC_HIGH_THRESH; 4771 hw->fc_low_water = E1000_FC_LOW_THRESH; 4772 hw->fc_pause_time = E1000_FC_PAUSE_TIME; 4773 hw->fc_send_xon = 1; 4774 4775 /* Media type - copper or fiber */ 4776 e1000_set_media_type(hw); 4777 4778 if (hw->mac_type >= e1000_82543) { 4779 uint32_t status = E1000_READ_REG(hw, STATUS); 4780 4781 if (status & E1000_STATUS_TBIMODE) { 4782 DEBUGOUT("fiber interface\n"); 4783 hw->media_type = e1000_media_type_fiber; 4784 } else { 4785 DEBUGOUT("copper interface\n"); 4786 hw->media_type = e1000_media_type_copper; 4787 } 4788 } else { 4789 hw->media_type = e1000_media_type_fiber; 4790 } 4791 4792 hw->tbi_compatibility_en = true; 4793 hw->wait_autoneg_complete = true; 4794 if (hw->mac_type < e1000_82543) 4795 hw->report_tx_early = 0; 4796 else 4797 hw->report_tx_early = 1; 4798 4799 return E1000_SUCCESS; 4800 } 4801 4802 void 4803 fill_rx(struct e1000_hw *hw) 4804 { 4805 struct e1000_rx_desc *rd; 4806 4807 rx_last = rx_tail; 4808 rd = rx_base + rx_tail; 4809 rx_tail = (rx_tail + 1) % 8; 4810 memset(rd, 0, 16); 4811 rd->buffer_addr = cpu_to_le64((u32) & packet); 4812 E1000_WRITE_REG(hw, RDT, rx_tail); 4813 } 4814 4815 /** 4816 * e1000_configure_tx - Configure 8254x Transmit Unit after Reset 4817 * @adapter: board private structure 4818 * 4819 * Configure the Tx unit of the MAC after a reset. 4820 **/ 4821 4822 static void 4823 e1000_configure_tx(struct e1000_hw *hw) 4824 { 4825 unsigned long ptr; 4826 unsigned long tctl; 4827 unsigned long tipg, tarc; 4828 uint32_t ipgr1, ipgr2; 4829 4830 ptr = (u32) tx_pool; 4831 if (ptr & 0xf) 4832 ptr = (ptr + 0x10) & (~0xf); 4833 4834 tx_base = (typeof(tx_base)) ptr; 4835 4836 E1000_WRITE_REG(hw, TDBAL, (u32) tx_base); 4837 E1000_WRITE_REG(hw, TDBAH, 0); 4838 4839 E1000_WRITE_REG(hw, TDLEN, 128); 4840 4841 /* Setup the HW Tx Head and Tail descriptor pointers */ 4842 E1000_WRITE_REG(hw, TDH, 0); 4843 E1000_WRITE_REG(hw, TDT, 0); 4844 tx_tail = 0; 4845 4846 /* Set the default values for the Tx Inter Packet Gap timer */ 4847 if (hw->mac_type <= e1000_82547_rev_2 && 4848 (hw->media_type == e1000_media_type_fiber || 4849 hw->media_type == e1000_media_type_internal_serdes)) 4850 tipg = DEFAULT_82543_TIPG_IPGT_FIBER; 4851 else 4852 tipg = DEFAULT_82543_TIPG_IPGT_COPPER; 4853 4854 /* Set the default values for the Tx Inter Packet Gap timer */ 4855 switch (hw->mac_type) { 4856 case e1000_82542_rev2_0: 4857 case e1000_82542_rev2_1: 4858 tipg = DEFAULT_82542_TIPG_IPGT; 4859 ipgr1 = DEFAULT_82542_TIPG_IPGR1; 4860 ipgr2 = DEFAULT_82542_TIPG_IPGR2; 4861 break; 4862 case e1000_80003es2lan: 4863 ipgr1 = DEFAULT_82543_TIPG_IPGR1; 4864 ipgr2 = DEFAULT_80003ES2LAN_TIPG_IPGR2; 4865 break; 4866 default: 4867 ipgr1 = DEFAULT_82543_TIPG_IPGR1; 4868 ipgr2 = DEFAULT_82543_TIPG_IPGR2; 4869 break; 4870 } 4871 tipg |= ipgr1 << E1000_TIPG_IPGR1_SHIFT; 4872 tipg |= ipgr2 << E1000_TIPG_IPGR2_SHIFT; 4873 E1000_WRITE_REG(hw, TIPG, tipg); 4874 /* Program the Transmit Control Register */ 4875 tctl = E1000_READ_REG(hw, TCTL); 4876 tctl &= ~E1000_TCTL_CT; 4877 tctl |= E1000_TCTL_EN | E1000_TCTL_PSP | 4878 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); 4879 4880 if (hw->mac_type == e1000_82571 || hw->mac_type == e1000_82572) { 4881 tarc = E1000_READ_REG(hw, TARC0); 4882 /* set the speed mode bit, we'll clear it if we're not at 4883 * gigabit link later */ 4884 /* git bit can be set to 1*/ 4885 } else if (hw->mac_type == e1000_80003es2lan) { 4886 tarc = E1000_READ_REG(hw, TARC0); 4887 tarc |= 1; 4888 E1000_WRITE_REG(hw, TARC0, tarc); 4889 tarc = E1000_READ_REG(hw, TARC1); 4890 tarc |= 1; 4891 E1000_WRITE_REG(hw, TARC1, tarc); 4892 } 4893 4894 4895 e1000_config_collision_dist(hw); 4896 /* Setup Transmit Descriptor Settings for eop descriptor */ 4897 hw->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS; 4898 4899 /* Need to set up RS bit */ 4900 if (hw->mac_type < e1000_82543) 4901 hw->txd_cmd |= E1000_TXD_CMD_RPS; 4902 else 4903 hw->txd_cmd |= E1000_TXD_CMD_RS; 4904 E1000_WRITE_REG(hw, TCTL, tctl); 4905 } 4906 4907 /** 4908 * e1000_setup_rctl - configure the receive control register 4909 * @adapter: Board private structure 4910 **/ 4911 static void 4912 e1000_setup_rctl(struct e1000_hw *hw) 4913 { 4914 uint32_t rctl; 4915 4916 rctl = E1000_READ_REG(hw, RCTL); 4917 4918 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 4919 4920 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO 4921 | E1000_RCTL_RDMTS_HALF; /* | 4922 (hw.mc_filter_type << E1000_RCTL_MO_SHIFT); */ 4923 4924 if (hw->tbi_compatibility_on == 1) 4925 rctl |= E1000_RCTL_SBP; 4926 else 4927 rctl &= ~E1000_RCTL_SBP; 4928 4929 rctl &= ~(E1000_RCTL_SZ_4096); 4930 rctl |= E1000_RCTL_SZ_2048; 4931 rctl &= ~(E1000_RCTL_BSEX | E1000_RCTL_LPE); 4932 E1000_WRITE_REG(hw, RCTL, rctl); 4933 } 4934 4935 /** 4936 * e1000_configure_rx - Configure 8254x Receive Unit after Reset 4937 * @adapter: board private structure 4938 * 4939 * Configure the Rx unit of the MAC after a reset. 4940 **/ 4941 static void 4942 e1000_configure_rx(struct e1000_hw *hw) 4943 { 4944 unsigned long ptr; 4945 unsigned long rctl, ctrl_ext; 4946 rx_tail = 0; 4947 /* make sure receives are disabled while setting up the descriptors */ 4948 rctl = E1000_READ_REG(hw, RCTL); 4949 E1000_WRITE_REG(hw, RCTL, rctl & ~E1000_RCTL_EN); 4950 if (hw->mac_type >= e1000_82540) { 4951 /* Set the interrupt throttling rate. Value is calculated 4952 * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns) */ 4953 #define MAX_INTS_PER_SEC 8000 4954 #define DEFAULT_ITR 1000000000/(MAX_INTS_PER_SEC * 256) 4955 E1000_WRITE_REG(hw, ITR, DEFAULT_ITR); 4956 } 4957 4958 if (hw->mac_type >= e1000_82571) { 4959 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 4960 /* Reset delay timers after every interrupt */ 4961 ctrl_ext |= E1000_CTRL_EXT_INT_TIMER_CLR; 4962 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 4963 E1000_WRITE_FLUSH(hw); 4964 } 4965 /* Setup the Base and Length of the Rx Descriptor Ring */ 4966 ptr = (u32) rx_pool; 4967 if (ptr & 0xf) 4968 ptr = (ptr + 0x10) & (~0xf); 4969 rx_base = (typeof(rx_base)) ptr; 4970 E1000_WRITE_REG(hw, RDBAL, (u32) rx_base); 4971 E1000_WRITE_REG(hw, RDBAH, 0); 4972 4973 E1000_WRITE_REG(hw, RDLEN, 128); 4974 4975 /* Setup the HW Rx Head and Tail Descriptor Pointers */ 4976 E1000_WRITE_REG(hw, RDH, 0); 4977 E1000_WRITE_REG(hw, RDT, 0); 4978 /* Enable Receives */ 4979 4980 E1000_WRITE_REG(hw, RCTL, rctl); 4981 fill_rx(hw); 4982 } 4983 4984 /************************************************************************** 4985 POLL - Wait for a frame 4986 ***************************************************************************/ 4987 static int 4988 e1000_poll(struct eth_device *nic) 4989 { 4990 struct e1000_hw *hw = nic->priv; 4991 struct e1000_rx_desc *rd; 4992 /* return true if there's an ethernet packet ready to read */ 4993 rd = rx_base + rx_last; 4994 if (!(le32_to_cpu(rd->status)) & E1000_RXD_STAT_DD) 4995 return 0; 4996 /*DEBUGOUT("recv: packet len=%d \n", rd->length); */ 4997 NetReceive((uchar *)packet, le32_to_cpu(rd->length)); 4998 fill_rx(hw); 4999 return 1; 5000 } 5001 5002 /************************************************************************** 5003 TRANSMIT - Transmit a frame 5004 ***************************************************************************/ 5005 static int e1000_transmit(struct eth_device *nic, void *packet, int length) 5006 { 5007 void *nv_packet = (void *)packet; 5008 struct e1000_hw *hw = nic->priv; 5009 struct e1000_tx_desc *txp; 5010 int i = 0; 5011 5012 txp = tx_base + tx_tail; 5013 tx_tail = (tx_tail + 1) % 8; 5014 5015 txp->buffer_addr = cpu_to_le64(virt_to_bus(hw->pdev, nv_packet)); 5016 txp->lower.data = cpu_to_le32(hw->txd_cmd | length); 5017 txp->upper.data = 0; 5018 E1000_WRITE_REG(hw, TDT, tx_tail); 5019 5020 E1000_WRITE_FLUSH(hw); 5021 while (!(le32_to_cpu(txp->upper.data) & E1000_TXD_STAT_DD)) { 5022 if (i++ > TOUT_LOOP) { 5023 DEBUGOUT("e1000: tx timeout\n"); 5024 return 0; 5025 } 5026 udelay(10); /* give the nic a chance to write to the register */ 5027 } 5028 return 1; 5029 } 5030 5031 /*reset function*/ 5032 static inline int 5033 e1000_reset(struct eth_device *nic) 5034 { 5035 struct e1000_hw *hw = nic->priv; 5036 5037 e1000_reset_hw(hw); 5038 if (hw->mac_type >= e1000_82544) { 5039 E1000_WRITE_REG(hw, WUC, 0); 5040 } 5041 return e1000_init_hw(nic); 5042 } 5043 5044 /************************************************************************** 5045 DISABLE - Turn off ethernet interface 5046 ***************************************************************************/ 5047 static void 5048 e1000_disable(struct eth_device *nic) 5049 { 5050 struct e1000_hw *hw = nic->priv; 5051 5052 /* Turn off the ethernet interface */ 5053 E1000_WRITE_REG(hw, RCTL, 0); 5054 E1000_WRITE_REG(hw, TCTL, 0); 5055 5056 /* Clear the transmit ring */ 5057 E1000_WRITE_REG(hw, TDH, 0); 5058 E1000_WRITE_REG(hw, TDT, 0); 5059 5060 /* Clear the receive ring */ 5061 E1000_WRITE_REG(hw, RDH, 0); 5062 E1000_WRITE_REG(hw, RDT, 0); 5063 5064 /* put the card in its initial state */ 5065 #if 0 5066 E1000_WRITE_REG(hw, CTRL, E1000_CTRL_RST); 5067 #endif 5068 mdelay(10); 5069 5070 } 5071 5072 /************************************************************************** 5073 INIT - set up ethernet interface(s) 5074 ***************************************************************************/ 5075 static int 5076 e1000_init(struct eth_device *nic, bd_t * bis) 5077 { 5078 struct e1000_hw *hw = nic->priv; 5079 int ret_val = 0; 5080 5081 ret_val = e1000_reset(nic); 5082 if (ret_val < 0) { 5083 if ((ret_val == -E1000_ERR_NOLINK) || 5084 (ret_val == -E1000_ERR_TIMEOUT)) { 5085 E1000_ERR(hw->nic, "Valid Link not detected\n"); 5086 } else { 5087 E1000_ERR(hw->nic, "Hardware Initialization Failed\n"); 5088 } 5089 return 0; 5090 } 5091 e1000_configure_tx(hw); 5092 e1000_setup_rctl(hw); 5093 e1000_configure_rx(hw); 5094 return 1; 5095 } 5096 5097 /****************************************************************************** 5098 * Gets the current PCI bus type of hardware 5099 * 5100 * hw - Struct containing variables accessed by shared code 5101 *****************************************************************************/ 5102 void e1000_get_bus_type(struct e1000_hw *hw) 5103 { 5104 uint32_t status; 5105 5106 switch (hw->mac_type) { 5107 case e1000_82542_rev2_0: 5108 case e1000_82542_rev2_1: 5109 hw->bus_type = e1000_bus_type_pci; 5110 break; 5111 case e1000_82571: 5112 case e1000_82572: 5113 case e1000_82573: 5114 case e1000_82574: 5115 case e1000_80003es2lan: 5116 hw->bus_type = e1000_bus_type_pci_express; 5117 break; 5118 case e1000_ich8lan: 5119 hw->bus_type = e1000_bus_type_pci_express; 5120 break; 5121 default: 5122 status = E1000_READ_REG(hw, STATUS); 5123 hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ? 5124 e1000_bus_type_pcix : e1000_bus_type_pci; 5125 break; 5126 } 5127 } 5128 5129 /* A list of all registered e1000 devices */ 5130 static LIST_HEAD(e1000_hw_list); 5131 5132 /************************************************************************** 5133 PROBE - Look for an adapter, this routine's visible to the outside 5134 You should omit the last argument struct pci_device * for a non-PCI NIC 5135 ***************************************************************************/ 5136 int 5137 e1000_initialize(bd_t * bis) 5138 { 5139 unsigned int i; 5140 pci_dev_t devno; 5141 5142 DEBUGFUNC(); 5143 5144 /* Find and probe all the matching PCI devices */ 5145 for (i = 0; (devno = pci_find_devices(e1000_supported, i)) >= 0; i++) { 5146 u32 val; 5147 5148 /* 5149 * These will never get freed due to errors, this allows us to 5150 * perform SPI EEPROM programming from U-boot, for example. 5151 */ 5152 struct eth_device *nic = malloc(sizeof(*nic)); 5153 struct e1000_hw *hw = malloc(sizeof(*hw)); 5154 if (!nic || !hw) { 5155 printf("e1000#%u: Out of Memory!\n", i); 5156 free(nic); 5157 free(hw); 5158 continue; 5159 } 5160 5161 /* Make sure all of the fields are initially zeroed */ 5162 memset(nic, 0, sizeof(*nic)); 5163 memset(hw, 0, sizeof(*hw)); 5164 5165 /* Assign the passed-in values */ 5166 hw->cardnum = i; 5167 hw->pdev = devno; 5168 hw->nic = nic; 5169 nic->priv = hw; 5170 5171 /* Generate a card name */ 5172 sprintf(nic->name, "e1000#%u", hw->cardnum); 5173 5174 /* Print a debug message with the IO base address */ 5175 pci_read_config_dword(devno, PCI_BASE_ADDRESS_0, &val); 5176 E1000_DBG(nic, "iobase 0x%08x\n", val & 0xfffffff0); 5177 5178 /* Try to enable I/O accesses and bus-mastering */ 5179 val = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; 5180 pci_write_config_dword(devno, PCI_COMMAND, val); 5181 5182 /* Make sure it worked */ 5183 pci_read_config_dword(devno, PCI_COMMAND, &val); 5184 if (!(val & PCI_COMMAND_MEMORY)) { 5185 E1000_ERR(nic, "Can't enable I/O memory\n"); 5186 continue; 5187 } 5188 if (!(val & PCI_COMMAND_MASTER)) { 5189 E1000_ERR(nic, "Can't enable bus-mastering\n"); 5190 continue; 5191 } 5192 5193 /* Are these variables needed? */ 5194 hw->fc = e1000_fc_default; 5195 hw->original_fc = e1000_fc_default; 5196 hw->autoneg_failed = 0; 5197 hw->autoneg = 1; 5198 hw->get_link_status = true; 5199 hw->hw_addr = pci_map_bar(devno, PCI_BASE_ADDRESS_0, 5200 PCI_REGION_MEM); 5201 hw->mac_type = e1000_undefined; 5202 5203 /* MAC and Phy settings */ 5204 if (e1000_sw_init(nic) < 0) { 5205 E1000_ERR(nic, "Software init failed\n"); 5206 continue; 5207 } 5208 if (e1000_check_phy_reset_block(hw)) 5209 E1000_ERR(nic, "PHY Reset is blocked!\n"); 5210 5211 /* Basic init was OK, reset the hardware and allow SPI access */ 5212 e1000_reset_hw(hw); 5213 list_add_tail(&hw->list_node, &e1000_hw_list); 5214 5215 #ifndef CONFIG_E1000_NO_NVM 5216 /* Validate the EEPROM and get chipset information */ 5217 #if !defined(CONFIG_MVBC_1G) 5218 if (e1000_init_eeprom_params(hw)) { 5219 E1000_ERR(nic, "EEPROM is invalid!\n"); 5220 continue; 5221 } 5222 if (e1000_validate_eeprom_checksum(hw)) 5223 continue; 5224 #endif 5225 e1000_read_mac_addr(nic); 5226 #endif 5227 e1000_get_bus_type(hw); 5228 5229 #ifndef CONFIG_E1000_NO_NVM 5230 printf("e1000: %02x:%02x:%02x:%02x:%02x:%02x\n ", 5231 nic->enetaddr[0], nic->enetaddr[1], nic->enetaddr[2], 5232 nic->enetaddr[3], nic->enetaddr[4], nic->enetaddr[5]); 5233 #else 5234 memset(nic->enetaddr, 0, 6); 5235 printf("e1000: no NVM\n"); 5236 #endif 5237 5238 /* Set up the function pointers and register the device */ 5239 nic->init = e1000_init; 5240 nic->recv = e1000_poll; 5241 nic->send = e1000_transmit; 5242 nic->halt = e1000_disable; 5243 eth_register(nic); 5244 } 5245 5246 return i; 5247 } 5248 5249 struct e1000_hw *e1000_find_card(unsigned int cardnum) 5250 { 5251 struct e1000_hw *hw; 5252 5253 list_for_each_entry(hw, &e1000_hw_list, list_node) 5254 if (hw->cardnum == cardnum) 5255 return hw; 5256 5257 return NULL; 5258 } 5259 5260 #ifdef CONFIG_CMD_E1000 5261 static int do_e1000(cmd_tbl_t *cmdtp, int flag, 5262 int argc, char * const argv[]) 5263 { 5264 struct e1000_hw *hw; 5265 5266 if (argc < 3) { 5267 cmd_usage(cmdtp); 5268 return 1; 5269 } 5270 5271 /* Make sure we can find the requested e1000 card */ 5272 hw = e1000_find_card(simple_strtoul(argv[1], NULL, 10)); 5273 if (!hw) { 5274 printf("e1000: ERROR: No such device: e1000#%s\n", argv[1]); 5275 return 1; 5276 } 5277 5278 if (!strcmp(argv[2], "print-mac-address")) { 5279 unsigned char *mac = hw->nic->enetaddr; 5280 printf("%02x:%02x:%02x:%02x:%02x:%02x\n", 5281 mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]); 5282 return 0; 5283 } 5284 5285 #ifdef CONFIG_E1000_SPI 5286 /* Handle the "SPI" subcommand */ 5287 if (!strcmp(argv[2], "spi")) 5288 return do_e1000_spi(cmdtp, hw, argc - 3, argv + 3); 5289 #endif 5290 5291 cmd_usage(cmdtp); 5292 return 1; 5293 } 5294 5295 U_BOOT_CMD( 5296 e1000, 7, 0, do_e1000, 5297 "Intel e1000 controller management", 5298 /* */"<card#> print-mac-address\n" 5299 #ifdef CONFIG_E1000_SPI 5300 "e1000 <card#> spi show [<offset> [<length>]]\n" 5301 "e1000 <card#> spi dump <addr> <offset> <length>\n" 5302 "e1000 <card#> spi program <addr> <offset> <length>\n" 5303 "e1000 <card#> spi checksum [update]\n" 5304 #endif 5305 " - Manage the Intel E1000 PCI device" 5306 ); 5307 #endif /* not CONFIG_CMD_E1000 */ 5308