1 /************************************************************************** 2 Intel Pro 1000 for ppcboot/das-u-boot 3 Drivers are port from Intel's Linux driver e1000-4.3.15 4 and from Etherboot pro 1000 driver by mrakes at vivato dot net 5 tested on both gig copper and gig fiber boards 6 ***************************************************************************/ 7 /******************************************************************************* 8 9 10 Copyright(c) 1999 - 2002 Intel Corporation. All rights reserved. 11 12 This program is free software; you can redistribute it and/or modify it 13 under the terms of the GNU General Public License as published by the Free 14 Software Foundation; either version 2 of the License, or (at your option) 15 any later version. 16 17 This program is distributed in the hope that it will be useful, but WITHOUT 18 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 19 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 20 more details. 21 22 You should have received a copy of the GNU General Public License along with 23 this program; if not, write to the Free Software Foundation, Inc., 59 24 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 25 26 The full GNU General Public License is included in this distribution in the 27 file called LICENSE. 28 29 Contact Information: 30 Linux NICS <linux.nics@intel.com> 31 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 32 33 *******************************************************************************/ 34 /* 35 * Copyright (C) Archway Digital Solutions. 36 * 37 * written by Chrsitopher Li <cli at arcyway dot com> or <chrisl at gnuchina dot org> 38 * 2/9/2002 39 * 40 * Copyright (C) Linux Networx. 41 * Massive upgrade to work with the new intel gigabit NICs. 42 * <ebiederman at lnxi dot com> 43 */ 44 45 #include "e1000.h" 46 47 #define TOUT_LOOP 100000 48 49 #undef virt_to_bus 50 #define virt_to_bus(x) ((unsigned long)x) 51 #define bus_to_phys(devno, a) pci_mem_to_phys(devno, a) 52 #define mdelay(n) udelay((n)*1000) 53 54 #define E1000_DEFAULT_PBA 0x00000030 55 56 /* NIC specific static variables go here */ 57 58 static char tx_pool[128 + 16]; 59 static char rx_pool[128 + 16]; 60 static char packet[2096]; 61 62 static struct e1000_tx_desc *tx_base; 63 static struct e1000_rx_desc *rx_base; 64 65 static int tx_tail; 66 static int rx_tail, rx_last; 67 68 static struct pci_device_id supported[] = { 69 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82542}, 70 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82543GC_FIBER}, 71 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82543GC_COPPER}, 72 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544EI_COPPER}, 73 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544EI_FIBER}, 74 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544GC_COPPER}, 75 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544GC_LOM}, 76 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82540EM}, 77 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545EM_COPPER}, 78 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_COPPER}, 79 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545EM_FIBER}, 80 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_FIBER}, 81 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82540EM_LOM}, 82 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82541ER}, 83 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82541GI_LF}, 84 }; 85 86 /* Function forward declarations */ 87 static int e1000_setup_link(struct eth_device *nic); 88 static int e1000_setup_fiber_link(struct eth_device *nic); 89 static int e1000_setup_copper_link(struct eth_device *nic); 90 static int e1000_phy_setup_autoneg(struct e1000_hw *hw); 91 static void e1000_config_collision_dist(struct e1000_hw *hw); 92 static int e1000_config_mac_to_phy(struct e1000_hw *hw); 93 static int e1000_config_fc_after_link_up(struct e1000_hw *hw); 94 static int e1000_check_for_link(struct eth_device *nic); 95 static int e1000_wait_autoneg(struct e1000_hw *hw); 96 static void e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t * speed, 97 uint16_t * duplex); 98 static int e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, 99 uint16_t * phy_data); 100 static int e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, 101 uint16_t phy_data); 102 static void e1000_phy_hw_reset(struct e1000_hw *hw); 103 static int e1000_phy_reset(struct e1000_hw *hw); 104 static int e1000_detect_gig_phy(struct e1000_hw *hw); 105 106 #define E1000_WRITE_REG(a, reg, value) (writel((value), ((a)->hw_addr + E1000_##reg))) 107 #define E1000_READ_REG(a, reg) (readl((a)->hw_addr + E1000_##reg)) 108 #define E1000_WRITE_REG_ARRAY(a, reg, offset, value) (\ 109 writel((value), ((a)->hw_addr + E1000_##reg + ((offset) << 2)))) 110 #define E1000_READ_REG_ARRAY(a, reg, offset) ( \ 111 readl((a)->hw_addr + E1000_##reg + ((offset) << 2))) 112 #define E1000_WRITE_FLUSH(a) {uint32_t x; x = E1000_READ_REG(a, STATUS);} 113 114 #ifndef CONFIG_AP1000 /* remove for warnings */ 115 /****************************************************************************** 116 * Raises the EEPROM's clock input. 117 * 118 * hw - Struct containing variables accessed by shared code 119 * eecd - EECD's current value 120 *****************************************************************************/ 121 static void 122 e1000_raise_ee_clk(struct e1000_hw *hw, uint32_t * eecd) 123 { 124 /* Raise the clock input to the EEPROM (by setting the SK bit), and then 125 * wait 50 microseconds. 126 */ 127 *eecd = *eecd | E1000_EECD_SK; 128 E1000_WRITE_REG(hw, EECD, *eecd); 129 E1000_WRITE_FLUSH(hw); 130 udelay(50); 131 } 132 133 /****************************************************************************** 134 * Lowers the EEPROM's clock input. 135 * 136 * hw - Struct containing variables accessed by shared code 137 * eecd - EECD's current value 138 *****************************************************************************/ 139 static void 140 e1000_lower_ee_clk(struct e1000_hw *hw, uint32_t * eecd) 141 { 142 /* Lower the clock input to the EEPROM (by clearing the SK bit), and then 143 * wait 50 microseconds. 144 */ 145 *eecd = *eecd & ~E1000_EECD_SK; 146 E1000_WRITE_REG(hw, EECD, *eecd); 147 E1000_WRITE_FLUSH(hw); 148 udelay(50); 149 } 150 151 /****************************************************************************** 152 * Shift data bits out to the EEPROM. 153 * 154 * hw - Struct containing variables accessed by shared code 155 * data - data to send to the EEPROM 156 * count - number of bits to shift out 157 *****************************************************************************/ 158 static void 159 e1000_shift_out_ee_bits(struct e1000_hw *hw, uint16_t data, uint16_t count) 160 { 161 uint32_t eecd; 162 uint32_t mask; 163 164 /* We need to shift "count" bits out to the EEPROM. So, value in the 165 * "data" parameter will be shifted out to the EEPROM one bit at a time. 166 * In order to do this, "data" must be broken down into bits. 167 */ 168 mask = 0x01 << (count - 1); 169 eecd = E1000_READ_REG(hw, EECD); 170 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI); 171 do { 172 /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1", 173 * and then raising and then lowering the clock (the SK bit controls 174 * the clock input to the EEPROM). A "0" is shifted out to the EEPROM 175 * by setting "DI" to "0" and then raising and then lowering the clock. 176 */ 177 eecd &= ~E1000_EECD_DI; 178 179 if (data & mask) 180 eecd |= E1000_EECD_DI; 181 182 E1000_WRITE_REG(hw, EECD, eecd); 183 E1000_WRITE_FLUSH(hw); 184 185 udelay(50); 186 187 e1000_raise_ee_clk(hw, &eecd); 188 e1000_lower_ee_clk(hw, &eecd); 189 190 mask = mask >> 1; 191 192 } while (mask); 193 194 /* We leave the "DI" bit set to "0" when we leave this routine. */ 195 eecd &= ~E1000_EECD_DI; 196 E1000_WRITE_REG(hw, EECD, eecd); 197 } 198 199 /****************************************************************************** 200 * Shift data bits in from the EEPROM 201 * 202 * hw - Struct containing variables accessed by shared code 203 *****************************************************************************/ 204 static uint16_t 205 e1000_shift_in_ee_bits(struct e1000_hw *hw) 206 { 207 uint32_t eecd; 208 uint32_t i; 209 uint16_t data; 210 211 /* In order to read a register from the EEPROM, we need to shift 16 bits 212 * in from the EEPROM. Bits are "shifted in" by raising the clock input to 213 * the EEPROM (setting the SK bit), and then reading the value of the "DO" 214 * bit. During this "shifting in" process the "DI" bit should always be 215 * clear.. 216 */ 217 218 eecd = E1000_READ_REG(hw, EECD); 219 220 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI); 221 data = 0; 222 223 for (i = 0; i < 16; i++) { 224 data = data << 1; 225 e1000_raise_ee_clk(hw, &eecd); 226 227 eecd = E1000_READ_REG(hw, EECD); 228 229 eecd &= ~(E1000_EECD_DI); 230 if (eecd & E1000_EECD_DO) 231 data |= 1; 232 233 e1000_lower_ee_clk(hw, &eecd); 234 } 235 236 return data; 237 } 238 239 /****************************************************************************** 240 * Prepares EEPROM for access 241 * 242 * hw - Struct containing variables accessed by shared code 243 * 244 * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This 245 * function should be called before issuing a command to the EEPROM. 246 *****************************************************************************/ 247 static void 248 e1000_setup_eeprom(struct e1000_hw *hw) 249 { 250 uint32_t eecd; 251 252 eecd = E1000_READ_REG(hw, EECD); 253 254 /* Clear SK and DI */ 255 eecd &= ~(E1000_EECD_SK | E1000_EECD_DI); 256 E1000_WRITE_REG(hw, EECD, eecd); 257 258 /* Set CS */ 259 eecd |= E1000_EECD_CS; 260 E1000_WRITE_REG(hw, EECD, eecd); 261 } 262 263 /****************************************************************************** 264 * Returns EEPROM to a "standby" state 265 * 266 * hw - Struct containing variables accessed by shared code 267 *****************************************************************************/ 268 static void 269 e1000_standby_eeprom(struct e1000_hw *hw) 270 { 271 uint32_t eecd; 272 273 eecd = E1000_READ_REG(hw, EECD); 274 275 /* Deselct EEPROM */ 276 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); 277 E1000_WRITE_REG(hw, EECD, eecd); 278 E1000_WRITE_FLUSH(hw); 279 udelay(50); 280 281 /* Clock high */ 282 eecd |= E1000_EECD_SK; 283 E1000_WRITE_REG(hw, EECD, eecd); 284 E1000_WRITE_FLUSH(hw); 285 udelay(50); 286 287 /* Select EEPROM */ 288 eecd |= E1000_EECD_CS; 289 E1000_WRITE_REG(hw, EECD, eecd); 290 E1000_WRITE_FLUSH(hw); 291 udelay(50); 292 293 /* Clock low */ 294 eecd &= ~E1000_EECD_SK; 295 E1000_WRITE_REG(hw, EECD, eecd); 296 E1000_WRITE_FLUSH(hw); 297 udelay(50); 298 } 299 300 /****************************************************************************** 301 * Reads a 16 bit word from the EEPROM. 302 * 303 * hw - Struct containing variables accessed by shared code 304 * offset - offset of word in the EEPROM to read 305 * data - word read from the EEPROM 306 *****************************************************************************/ 307 static int 308 e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset, uint16_t * data) 309 { 310 uint32_t eecd; 311 uint32_t i = 0; 312 int large_eeprom = FALSE; 313 314 /* Request EEPROM Access */ 315 if (hw->mac_type > e1000_82544) { 316 eecd = E1000_READ_REG(hw, EECD); 317 if (eecd & E1000_EECD_SIZE) 318 large_eeprom = TRUE; 319 eecd |= E1000_EECD_REQ; 320 E1000_WRITE_REG(hw, EECD, eecd); 321 eecd = E1000_READ_REG(hw, EECD); 322 while ((!(eecd & E1000_EECD_GNT)) && (i < 100)) { 323 i++; 324 udelay(10); 325 eecd = E1000_READ_REG(hw, EECD); 326 } 327 if (!(eecd & E1000_EECD_GNT)) { 328 eecd &= ~E1000_EECD_REQ; 329 E1000_WRITE_REG(hw, EECD, eecd); 330 DEBUGOUT("Could not acquire EEPROM grant\n"); 331 return -E1000_ERR_EEPROM; 332 } 333 } 334 335 /* Prepare the EEPROM for reading */ 336 e1000_setup_eeprom(hw); 337 338 /* Send the READ command (opcode + addr) */ 339 e1000_shift_out_ee_bits(hw, EEPROM_READ_OPCODE, 3); 340 e1000_shift_out_ee_bits(hw, offset, (large_eeprom) ? 8 : 6); 341 342 /* Read the data */ 343 *data = e1000_shift_in_ee_bits(hw); 344 345 /* End this read operation */ 346 e1000_standby_eeprom(hw); 347 348 /* Stop requesting EEPROM access */ 349 if (hw->mac_type > e1000_82544) { 350 eecd = E1000_READ_REG(hw, EECD); 351 eecd &= ~E1000_EECD_REQ; 352 E1000_WRITE_REG(hw, EECD, eecd); 353 } 354 355 return 0; 356 } 357 358 #if 0 359 static void 360 e1000_eeprom_cleanup(struct e1000_hw *hw) 361 { 362 uint32_t eecd; 363 364 eecd = E1000_READ_REG(hw, EECD); 365 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI); 366 E1000_WRITE_REG(hw, EECD, eecd); 367 e1000_raise_ee_clk(hw, &eecd); 368 e1000_lower_ee_clk(hw, &eecd); 369 } 370 371 static uint16_t 372 e1000_wait_eeprom_done(struct e1000_hw *hw) 373 { 374 uint32_t eecd; 375 uint32_t i; 376 377 e1000_standby_eeprom(hw); 378 for (i = 0; i < 200; i++) { 379 eecd = E1000_READ_REG(hw, EECD); 380 if (eecd & E1000_EECD_DO) 381 return (TRUE); 382 udelay(5); 383 } 384 return (FALSE); 385 } 386 387 static int 388 e1000_write_eeprom(struct e1000_hw *hw, uint16_t Reg, uint16_t Data) 389 { 390 uint32_t eecd; 391 int large_eeprom = FALSE; 392 int i = 0; 393 394 /* Request EEPROM Access */ 395 if (hw->mac_type > e1000_82544) { 396 eecd = E1000_READ_REG(hw, EECD); 397 if (eecd & E1000_EECD_SIZE) 398 large_eeprom = TRUE; 399 eecd |= E1000_EECD_REQ; 400 E1000_WRITE_REG(hw, EECD, eecd); 401 eecd = E1000_READ_REG(hw, EECD); 402 while ((!(eecd & E1000_EECD_GNT)) && (i < 100)) { 403 i++; 404 udelay(5); 405 eecd = E1000_READ_REG(hw, EECD); 406 } 407 if (!(eecd & E1000_EECD_GNT)) { 408 eecd &= ~E1000_EECD_REQ; 409 E1000_WRITE_REG(hw, EECD, eecd); 410 DEBUGOUT("Could not acquire EEPROM grant\n"); 411 return FALSE; 412 } 413 } 414 e1000_setup_eeprom(hw); 415 e1000_shift_out_ee_bits(hw, EEPROM_EWEN_OPCODE, 5); 416 e1000_shift_out_ee_bits(hw, Reg, (large_eeprom) ? 6 : 4); 417 e1000_standby_eeprom(hw); 418 e1000_shift_out_ee_bits(hw, EEPROM_WRITE_OPCODE, 3); 419 e1000_shift_out_ee_bits(hw, Reg, (large_eeprom) ? 8 : 6); 420 e1000_shift_out_ee_bits(hw, Data, 16); 421 if (!e1000_wait_eeprom_done(hw)) { 422 return FALSE; 423 } 424 e1000_shift_out_ee_bits(hw, EEPROM_EWDS_OPCODE, 5); 425 e1000_shift_out_ee_bits(hw, Reg, (large_eeprom) ? 6 : 4); 426 e1000_eeprom_cleanup(hw); 427 428 /* Stop requesting EEPROM access */ 429 if (hw->mac_type > e1000_82544) { 430 eecd = E1000_READ_REG(hw, EECD); 431 eecd &= ~E1000_EECD_REQ; 432 E1000_WRITE_REG(hw, EECD, eecd); 433 } 434 i = 0; 435 eecd = E1000_READ_REG(hw, EECD); 436 while (((eecd & E1000_EECD_GNT)) && (i < 500)) { 437 i++; 438 udelay(10); 439 eecd = E1000_READ_REG(hw, EECD); 440 } 441 if ((eecd & E1000_EECD_GNT)) { 442 DEBUGOUT("Could not release EEPROM grant\n"); 443 } 444 return TRUE; 445 } 446 #endif 447 448 /****************************************************************************** 449 * Verifies that the EEPROM has a valid checksum 450 * 451 * hw - Struct containing variables accessed by shared code 452 * 453 * Reads the first 64 16 bit words of the EEPROM and sums the values read. 454 * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is 455 * valid. 456 *****************************************************************************/ 457 static int 458 e1000_validate_eeprom_checksum(struct eth_device *nic) 459 { 460 struct e1000_hw *hw = nic->priv; 461 uint16_t checksum = 0; 462 uint16_t i, eeprom_data; 463 464 DEBUGFUNC(); 465 466 for (i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) { 467 if (e1000_read_eeprom(hw, i, &eeprom_data) < 0) { 468 DEBUGOUT("EEPROM Read Error\n"); 469 return -E1000_ERR_EEPROM; 470 } 471 checksum += eeprom_data; 472 } 473 474 if (checksum == (uint16_t) EEPROM_SUM) { 475 return 0; 476 } else { 477 DEBUGOUT("EEPROM Checksum Invalid\n"); 478 return -E1000_ERR_EEPROM; 479 } 480 } 481 #endif /* #ifndef CONFIG_AP1000 */ 482 483 /****************************************************************************** 484 * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the 485 * second function of dual function devices 486 * 487 * nic - Struct containing variables accessed by shared code 488 *****************************************************************************/ 489 static int 490 e1000_read_mac_addr(struct eth_device *nic) 491 { 492 #ifndef CONFIG_AP1000 493 struct e1000_hw *hw = nic->priv; 494 uint16_t offset; 495 uint16_t eeprom_data; 496 int i; 497 498 DEBUGFUNC(); 499 500 for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) { 501 offset = i >> 1; 502 if (e1000_read_eeprom(hw, offset, &eeprom_data) < 0) { 503 DEBUGOUT("EEPROM Read Error\n"); 504 return -E1000_ERR_EEPROM; 505 } 506 nic->enetaddr[i] = eeprom_data & 0xff; 507 nic->enetaddr[i + 1] = (eeprom_data >> 8) & 0xff; 508 } 509 if ((hw->mac_type == e1000_82546) && 510 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) { 511 /* Invert the last bit if this is the second device */ 512 nic->enetaddr[5] += 1; 513 } 514 #ifdef CONFIG_E1000_FALLBACK_MAC 515 if ( *(u32*)(nic->enetaddr) == 0 || *(u32*)(nic->enetaddr) == ~0 ) 516 for ( i=0; i < NODE_ADDRESS_SIZE; i++ ) 517 nic->enetaddr[i] = (CONFIG_E1000_FALLBACK_MAC >> (8*(5-i))) & 0xff; 518 #endif 519 #else 520 /* 521 * The AP1000's e1000 has no eeprom; the MAC address is stored in the 522 * environment variables. Currently this does not support the addition 523 * of a PMC e1000 card, which is certainly a possibility, so this should 524 * be updated to properly use the env variable only for the onboard e1000 525 */ 526 527 int ii; 528 char *s, *e; 529 530 DEBUGFUNC(); 531 532 s = getenv ("ethaddr"); 533 if (s == NULL){ 534 return -E1000_ERR_EEPROM; 535 } 536 else{ 537 for(ii = 0; ii < 6; ii++) { 538 nic->enetaddr[ii] = s ? simple_strtoul (s, &e, 16) : 0; 539 if (s){ 540 s = (*e) ? e + 1 : e; 541 } 542 } 543 } 544 #endif 545 return 0; 546 } 547 548 /****************************************************************************** 549 * Initializes receive address filters. 550 * 551 * hw - Struct containing variables accessed by shared code 552 * 553 * Places the MAC address in receive address register 0 and clears the rest 554 * of the receive addresss registers. Clears the multicast table. Assumes 555 * the receiver is in reset when the routine is called. 556 *****************************************************************************/ 557 static void 558 e1000_init_rx_addrs(struct eth_device *nic) 559 { 560 struct e1000_hw *hw = nic->priv; 561 uint32_t i; 562 uint32_t addr_low; 563 uint32_t addr_high; 564 565 DEBUGFUNC(); 566 567 /* Setup the receive address. */ 568 DEBUGOUT("Programming MAC Address into RAR[0]\n"); 569 addr_low = (nic->enetaddr[0] | 570 (nic->enetaddr[1] << 8) | 571 (nic->enetaddr[2] << 16) | (nic->enetaddr[3] << 24)); 572 573 addr_high = (nic->enetaddr[4] | (nic->enetaddr[5] << 8) | E1000_RAH_AV); 574 575 E1000_WRITE_REG_ARRAY(hw, RA, 0, addr_low); 576 E1000_WRITE_REG_ARRAY(hw, RA, 1, addr_high); 577 578 /* Zero out the other 15 receive addresses. */ 579 DEBUGOUT("Clearing RAR[1-15]\n"); 580 for (i = 1; i < E1000_RAR_ENTRIES; i++) { 581 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0); 582 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0); 583 } 584 } 585 586 /****************************************************************************** 587 * Clears the VLAN filer table 588 * 589 * hw - Struct containing variables accessed by shared code 590 *****************************************************************************/ 591 static void 592 e1000_clear_vfta(struct e1000_hw *hw) 593 { 594 uint32_t offset; 595 596 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) 597 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, 0); 598 } 599 600 /****************************************************************************** 601 * Set the mac type member in the hw struct. 602 * 603 * hw - Struct containing variables accessed by shared code 604 *****************************************************************************/ 605 static int 606 e1000_set_mac_type(struct e1000_hw *hw) 607 { 608 DEBUGFUNC(); 609 610 switch (hw->device_id) { 611 case E1000_DEV_ID_82542: 612 switch (hw->revision_id) { 613 case E1000_82542_2_0_REV_ID: 614 hw->mac_type = e1000_82542_rev2_0; 615 break; 616 case E1000_82542_2_1_REV_ID: 617 hw->mac_type = e1000_82542_rev2_1; 618 break; 619 default: 620 /* Invalid 82542 revision ID */ 621 return -E1000_ERR_MAC_TYPE; 622 } 623 break; 624 case E1000_DEV_ID_82543GC_FIBER: 625 case E1000_DEV_ID_82543GC_COPPER: 626 hw->mac_type = e1000_82543; 627 break; 628 case E1000_DEV_ID_82544EI_COPPER: 629 case E1000_DEV_ID_82544EI_FIBER: 630 case E1000_DEV_ID_82544GC_COPPER: 631 case E1000_DEV_ID_82544GC_LOM: 632 hw->mac_type = e1000_82544; 633 break; 634 case E1000_DEV_ID_82540EM: 635 case E1000_DEV_ID_82540EM_LOM: 636 hw->mac_type = e1000_82540; 637 break; 638 case E1000_DEV_ID_82545EM_COPPER: 639 case E1000_DEV_ID_82545EM_FIBER: 640 hw->mac_type = e1000_82545; 641 break; 642 case E1000_DEV_ID_82546EB_COPPER: 643 case E1000_DEV_ID_82546EB_FIBER: 644 hw->mac_type = e1000_82546; 645 break; 646 case E1000_DEV_ID_82541ER: 647 case E1000_DEV_ID_82541GI_LF: 648 hw->mac_type = e1000_82541_rev_2; 649 break; 650 default: 651 /* Should never have loaded on this device */ 652 return -E1000_ERR_MAC_TYPE; 653 } 654 return E1000_SUCCESS; 655 } 656 657 /****************************************************************************** 658 * Reset the transmit and receive units; mask and clear all interrupts. 659 * 660 * hw - Struct containing variables accessed by shared code 661 *****************************************************************************/ 662 void 663 e1000_reset_hw(struct e1000_hw *hw) 664 { 665 uint32_t ctrl; 666 uint32_t ctrl_ext; 667 uint32_t icr; 668 uint32_t manc; 669 670 DEBUGFUNC(); 671 672 /* For 82542 (rev 2.0), disable MWI before issuing a device reset */ 673 if (hw->mac_type == e1000_82542_rev2_0) { 674 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n"); 675 pci_write_config_word(hw->pdev, PCI_COMMAND, 676 hw-> 677 pci_cmd_word & ~PCI_COMMAND_INVALIDATE); 678 } 679 680 /* Clear interrupt mask to stop board from generating interrupts */ 681 DEBUGOUT("Masking off all interrupts\n"); 682 E1000_WRITE_REG(hw, IMC, 0xffffffff); 683 684 /* Disable the Transmit and Receive units. Then delay to allow 685 * any pending transactions to complete before we hit the MAC with 686 * the global reset. 687 */ 688 E1000_WRITE_REG(hw, RCTL, 0); 689 E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP); 690 E1000_WRITE_FLUSH(hw); 691 692 /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */ 693 hw->tbi_compatibility_on = FALSE; 694 695 /* Delay to allow any outstanding PCI transactions to complete before 696 * resetting the device 697 */ 698 mdelay(10); 699 700 /* Issue a global reset to the MAC. This will reset the chip's 701 * transmit, receive, DMA, and link units. It will not effect 702 * the current PCI configuration. The global reset bit is self- 703 * clearing, and should clear within a microsecond. 704 */ 705 DEBUGOUT("Issuing a global reset to MAC\n"); 706 ctrl = E1000_READ_REG(hw, CTRL); 707 708 #if 0 709 if (hw->mac_type > e1000_82543) 710 E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST)); 711 else 712 #endif 713 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST)); 714 715 /* Force a reload from the EEPROM if necessary */ 716 if (hw->mac_type < e1000_82540) { 717 /* Wait for reset to complete */ 718 udelay(10); 719 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 720 ctrl_ext |= E1000_CTRL_EXT_EE_RST; 721 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 722 E1000_WRITE_FLUSH(hw); 723 /* Wait for EEPROM reload */ 724 mdelay(2); 725 } else { 726 /* Wait for EEPROM reload (it happens automatically) */ 727 mdelay(4); 728 /* Dissable HW ARPs on ASF enabled adapters */ 729 manc = E1000_READ_REG(hw, MANC); 730 manc &= ~(E1000_MANC_ARP_EN); 731 E1000_WRITE_REG(hw, MANC, manc); 732 } 733 734 /* Clear interrupt mask to stop board from generating interrupts */ 735 DEBUGOUT("Masking off all interrupts\n"); 736 E1000_WRITE_REG(hw, IMC, 0xffffffff); 737 738 /* Clear any pending interrupt events. */ 739 icr = E1000_READ_REG(hw, ICR); 740 741 /* If MWI was previously enabled, reenable it. */ 742 if (hw->mac_type == e1000_82542_rev2_0) { 743 pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word); 744 } 745 } 746 747 /****************************************************************************** 748 * Performs basic configuration of the adapter. 749 * 750 * hw - Struct containing variables accessed by shared code 751 * 752 * Assumes that the controller has previously been reset and is in a 753 * post-reset uninitialized state. Initializes the receive address registers, 754 * multicast table, and VLAN filter table. Calls routines to setup link 755 * configuration and flow control settings. Clears all on-chip counters. Leaves 756 * the transmit and receive units disabled and uninitialized. 757 *****************************************************************************/ 758 static int 759 e1000_init_hw(struct eth_device *nic) 760 { 761 struct e1000_hw *hw = nic->priv; 762 uint32_t ctrl, status; 763 uint32_t i; 764 int32_t ret_val; 765 uint16_t pcix_cmd_word; 766 uint16_t pcix_stat_hi_word; 767 uint16_t cmd_mmrbc; 768 uint16_t stat_mmrbc; 769 e1000_bus_type bus_type = e1000_bus_type_unknown; 770 771 DEBUGFUNC(); 772 #if 0 773 /* Initialize Identification LED */ 774 ret_val = e1000_id_led_init(hw); 775 if (ret_val < 0) { 776 DEBUGOUT("Error Initializing Identification LED\n"); 777 return ret_val; 778 } 779 #endif 780 /* Set the Media Type and exit with error if it is not valid. */ 781 if (hw->mac_type != e1000_82543) { 782 /* tbi_compatibility is only valid on 82543 */ 783 hw->tbi_compatibility_en = FALSE; 784 } 785 786 if (hw->mac_type >= e1000_82543) { 787 status = E1000_READ_REG(hw, STATUS); 788 if (status & E1000_STATUS_TBIMODE) { 789 hw->media_type = e1000_media_type_fiber; 790 /* tbi_compatibility not valid on fiber */ 791 hw->tbi_compatibility_en = FALSE; 792 } else { 793 hw->media_type = e1000_media_type_copper; 794 } 795 } else { 796 /* This is an 82542 (fiber only) */ 797 hw->media_type = e1000_media_type_fiber; 798 } 799 800 /* Disabling VLAN filtering. */ 801 DEBUGOUT("Initializing the IEEE VLAN\n"); 802 E1000_WRITE_REG(hw, VET, 0); 803 804 e1000_clear_vfta(hw); 805 806 /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */ 807 if (hw->mac_type == e1000_82542_rev2_0) { 808 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n"); 809 pci_write_config_word(hw->pdev, PCI_COMMAND, 810 hw-> 811 pci_cmd_word & ~PCI_COMMAND_INVALIDATE); 812 E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST); 813 E1000_WRITE_FLUSH(hw); 814 mdelay(5); 815 } 816 817 /* Setup the receive address. This involves initializing all of the Receive 818 * Address Registers (RARs 0 - 15). 819 */ 820 e1000_init_rx_addrs(nic); 821 822 /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */ 823 if (hw->mac_type == e1000_82542_rev2_0) { 824 E1000_WRITE_REG(hw, RCTL, 0); 825 E1000_WRITE_FLUSH(hw); 826 mdelay(1); 827 pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word); 828 } 829 830 /* Zero out the Multicast HASH table */ 831 DEBUGOUT("Zeroing the MTA\n"); 832 for (i = 0; i < E1000_MC_TBL_SIZE; i++) 833 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0); 834 835 #if 0 836 /* Set the PCI priority bit correctly in the CTRL register. This 837 * determines if the adapter gives priority to receives, or if it 838 * gives equal priority to transmits and receives. 839 */ 840 if (hw->dma_fairness) { 841 ctrl = E1000_READ_REG(hw, CTRL); 842 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR); 843 } 844 #endif 845 if (hw->mac_type >= e1000_82543) { 846 status = E1000_READ_REG(hw, STATUS); 847 bus_type = (status & E1000_STATUS_PCIX_MODE) ? 848 e1000_bus_type_pcix : e1000_bus_type_pci; 849 } 850 /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */ 851 if (bus_type == e1000_bus_type_pcix) { 852 pci_read_config_word(hw->pdev, PCIX_COMMAND_REGISTER, 853 &pcix_cmd_word); 854 pci_read_config_word(hw->pdev, PCIX_STATUS_REGISTER_HI, 855 &pcix_stat_hi_word); 856 cmd_mmrbc = 857 (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) >> 858 PCIX_COMMAND_MMRBC_SHIFT; 859 stat_mmrbc = 860 (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >> 861 PCIX_STATUS_HI_MMRBC_SHIFT; 862 if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K) 863 stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K; 864 if (cmd_mmrbc > stat_mmrbc) { 865 pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK; 866 pcix_cmd_word |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT; 867 pci_write_config_word(hw->pdev, PCIX_COMMAND_REGISTER, 868 pcix_cmd_word); 869 } 870 } 871 872 /* Call a subroutine to configure the link and setup flow control. */ 873 ret_val = e1000_setup_link(nic); 874 875 /* Set the transmit descriptor write-back policy */ 876 if (hw->mac_type > e1000_82544) { 877 ctrl = E1000_READ_REG(hw, TXDCTL); 878 ctrl = 879 (ctrl & ~E1000_TXDCTL_WTHRESH) | 880 E1000_TXDCTL_FULL_TX_DESC_WB; 881 E1000_WRITE_REG(hw, TXDCTL, ctrl); 882 } 883 #if 0 884 /* Clear all of the statistics registers (clear on read). It is 885 * important that we do this after we have tried to establish link 886 * because the symbol error count will increment wildly if there 887 * is no link. 888 */ 889 e1000_clear_hw_cntrs(hw); 890 #endif 891 892 return ret_val; 893 } 894 895 /****************************************************************************** 896 * Configures flow control and link settings. 897 * 898 * hw - Struct containing variables accessed by shared code 899 * 900 * Determines which flow control settings to use. Calls the apropriate media- 901 * specific link configuration function. Configures the flow control settings. 902 * Assuming the adapter has a valid link partner, a valid link should be 903 * established. Assumes the hardware has previously been reset and the 904 * transmitter and receiver are not enabled. 905 *****************************************************************************/ 906 static int 907 e1000_setup_link(struct eth_device *nic) 908 { 909 struct e1000_hw *hw = nic->priv; 910 uint32_t ctrl_ext; 911 int32_t ret_val; 912 uint16_t eeprom_data; 913 914 DEBUGFUNC(); 915 916 #ifndef CONFIG_AP1000 917 /* Read and store word 0x0F of the EEPROM. This word contains bits 918 * that determine the hardware's default PAUSE (flow control) mode, 919 * a bit that determines whether the HW defaults to enabling or 920 * disabling auto-negotiation, and the direction of the 921 * SW defined pins. If there is no SW over-ride of the flow 922 * control setting, then the variable hw->fc will 923 * be initialized based on a value in the EEPROM. 924 */ 925 if (e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, &eeprom_data) < 0) { 926 DEBUGOUT("EEPROM Read Error\n"); 927 return -E1000_ERR_EEPROM; 928 } 929 #else 930 /* we have to hardcode the proper value for our hardware. */ 931 /* this value is for the 82540EM pci card used for prototyping, and it works. */ 932 eeprom_data = 0xb220; 933 #endif 934 935 if (hw->fc == e1000_fc_default) { 936 if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0) 937 hw->fc = e1000_fc_none; 938 else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 939 EEPROM_WORD0F_ASM_DIR) 940 hw->fc = e1000_fc_tx_pause; 941 else 942 hw->fc = e1000_fc_full; 943 } 944 945 /* We want to save off the original Flow Control configuration just 946 * in case we get disconnected and then reconnected into a different 947 * hub or switch with different Flow Control capabilities. 948 */ 949 if (hw->mac_type == e1000_82542_rev2_0) 950 hw->fc &= (~e1000_fc_tx_pause); 951 952 if ((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1)) 953 hw->fc &= (~e1000_fc_rx_pause); 954 955 hw->original_fc = hw->fc; 956 957 DEBUGOUT("After fix-ups FlowControl is now = %x\n", hw->fc); 958 959 /* Take the 4 bits from EEPROM word 0x0F that determine the initial 960 * polarity value for the SW controlled pins, and setup the 961 * Extended Device Control reg with that info. 962 * This is needed because one of the SW controlled pins is used for 963 * signal detection. So this should be done before e1000_setup_pcs_link() 964 * or e1000_phy_setup() is called. 965 */ 966 if (hw->mac_type == e1000_82543) { 967 ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) << 968 SWDPIO__EXT_SHIFT); 969 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 970 } 971 972 /* Call the necessary subroutine to configure the link. */ 973 ret_val = (hw->media_type == e1000_media_type_fiber) ? 974 e1000_setup_fiber_link(nic) : e1000_setup_copper_link(nic); 975 if (ret_val < 0) { 976 return ret_val; 977 } 978 979 /* Initialize the flow control address, type, and PAUSE timer 980 * registers to their default values. This is done even if flow 981 * control is disabled, because it does not hurt anything to 982 * initialize these registers. 983 */ 984 DEBUGOUT 985 ("Initializing the Flow Control address, type and timer regs\n"); 986 987 E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW); 988 E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH); 989 E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE); 990 E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time); 991 992 /* Set the flow control receive threshold registers. Normally, 993 * these registers will be set to a default threshold that may be 994 * adjusted later by the driver's runtime code. However, if the 995 * ability to transmit pause frames in not enabled, then these 996 * registers will be set to 0. 997 */ 998 if (!(hw->fc & e1000_fc_tx_pause)) { 999 E1000_WRITE_REG(hw, FCRTL, 0); 1000 E1000_WRITE_REG(hw, FCRTH, 0); 1001 } else { 1002 /* We need to set up the Receive Threshold high and low water marks 1003 * as well as (optionally) enabling the transmission of XON frames. 1004 */ 1005 if (hw->fc_send_xon) { 1006 E1000_WRITE_REG(hw, FCRTL, 1007 (hw->fc_low_water | E1000_FCRTL_XONE)); 1008 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water); 1009 } else { 1010 E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water); 1011 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water); 1012 } 1013 } 1014 return ret_val; 1015 } 1016 1017 /****************************************************************************** 1018 * Sets up link for a fiber based adapter 1019 * 1020 * hw - Struct containing variables accessed by shared code 1021 * 1022 * Manipulates Physical Coding Sublayer functions in order to configure 1023 * link. Assumes the hardware has been previously reset and the transmitter 1024 * and receiver are not enabled. 1025 *****************************************************************************/ 1026 static int 1027 e1000_setup_fiber_link(struct eth_device *nic) 1028 { 1029 struct e1000_hw *hw = nic->priv; 1030 uint32_t ctrl; 1031 uint32_t status; 1032 uint32_t txcw = 0; 1033 uint32_t i; 1034 uint32_t signal; 1035 int32_t ret_val; 1036 1037 DEBUGFUNC(); 1038 /* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be 1039 * set when the optics detect a signal. On older adapters, it will be 1040 * cleared when there is a signal 1041 */ 1042 ctrl = E1000_READ_REG(hw, CTRL); 1043 if ((hw->mac_type > e1000_82544) && !(ctrl & E1000_CTRL_ILOS)) 1044 signal = E1000_CTRL_SWDPIN1; 1045 else 1046 signal = 0; 1047 1048 printf("signal for %s is %x (ctrl %08x)!!!!\n", nic->name, signal, 1049 ctrl); 1050 /* Take the link out of reset */ 1051 ctrl &= ~(E1000_CTRL_LRST); 1052 1053 e1000_config_collision_dist(hw); 1054 1055 /* Check for a software override of the flow control settings, and setup 1056 * the device accordingly. If auto-negotiation is enabled, then software 1057 * will have to set the "PAUSE" bits to the correct value in the Tranmsit 1058 * Config Word Register (TXCW) and re-start auto-negotiation. However, if 1059 * auto-negotiation is disabled, then software will have to manually 1060 * configure the two flow control enable bits in the CTRL register. 1061 * 1062 * The possible values of the "fc" parameter are: 1063 * 0: Flow control is completely disabled 1064 * 1: Rx flow control is enabled (we can receive pause frames, but 1065 * not send pause frames). 1066 * 2: Tx flow control is enabled (we can send pause frames but we do 1067 * not support receiving pause frames). 1068 * 3: Both Rx and TX flow control (symmetric) are enabled. 1069 */ 1070 switch (hw->fc) { 1071 case e1000_fc_none: 1072 /* Flow control is completely disabled by a software over-ride. */ 1073 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD); 1074 break; 1075 case e1000_fc_rx_pause: 1076 /* RX Flow control is enabled and TX Flow control is disabled by a 1077 * software over-ride. Since there really isn't a way to advertise 1078 * that we are capable of RX Pause ONLY, we will advertise that we 1079 * support both symmetric and asymmetric RX PAUSE. Later, we will 1080 * disable the adapter's ability to send PAUSE frames. 1081 */ 1082 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); 1083 break; 1084 case e1000_fc_tx_pause: 1085 /* TX Flow control is enabled, and RX Flow control is disabled, by a 1086 * software over-ride. 1087 */ 1088 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR); 1089 break; 1090 case e1000_fc_full: 1091 /* Flow control (both RX and TX) is enabled by a software over-ride. */ 1092 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); 1093 break; 1094 default: 1095 DEBUGOUT("Flow control param set incorrectly\n"); 1096 return -E1000_ERR_CONFIG; 1097 break; 1098 } 1099 1100 /* Since auto-negotiation is enabled, take the link out of reset (the link 1101 * will be in reset, because we previously reset the chip). This will 1102 * restart auto-negotiation. If auto-neogtiation is successful then the 1103 * link-up status bit will be set and the flow control enable bits (RFCE 1104 * and TFCE) will be set according to their negotiated value. 1105 */ 1106 DEBUGOUT("Auto-negotiation enabled (%#x)\n", txcw); 1107 1108 E1000_WRITE_REG(hw, TXCW, txcw); 1109 E1000_WRITE_REG(hw, CTRL, ctrl); 1110 E1000_WRITE_FLUSH(hw); 1111 1112 hw->txcw = txcw; 1113 mdelay(1); 1114 1115 /* If we have a signal (the cable is plugged in) then poll for a "Link-Up" 1116 * indication in the Device Status Register. Time-out if a link isn't 1117 * seen in 500 milliseconds seconds (Auto-negotiation should complete in 1118 * less than 500 milliseconds even if the other end is doing it in SW). 1119 */ 1120 if ((E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) { 1121 DEBUGOUT("Looking for Link\n"); 1122 for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) { 1123 mdelay(10); 1124 status = E1000_READ_REG(hw, STATUS); 1125 if (status & E1000_STATUS_LU) 1126 break; 1127 } 1128 if (i == (LINK_UP_TIMEOUT / 10)) { 1129 /* AutoNeg failed to achieve a link, so we'll call 1130 * e1000_check_for_link. This routine will force the link up if we 1131 * detect a signal. This will allow us to communicate with 1132 * non-autonegotiating link partners. 1133 */ 1134 DEBUGOUT("Never got a valid link from auto-neg!!!\n"); 1135 hw->autoneg_failed = 1; 1136 ret_val = e1000_check_for_link(nic); 1137 if (ret_val < 0) { 1138 DEBUGOUT("Error while checking for link\n"); 1139 return ret_val; 1140 } 1141 hw->autoneg_failed = 0; 1142 } else { 1143 hw->autoneg_failed = 0; 1144 DEBUGOUT("Valid Link Found\n"); 1145 } 1146 } else { 1147 DEBUGOUT("No Signal Detected\n"); 1148 return -E1000_ERR_NOLINK; 1149 } 1150 return 0; 1151 } 1152 1153 /****************************************************************************** 1154 * Detects which PHY is present and the speed and duplex 1155 * 1156 * hw - Struct containing variables accessed by shared code 1157 ******************************************************************************/ 1158 static int 1159 e1000_setup_copper_link(struct eth_device *nic) 1160 { 1161 struct e1000_hw *hw = nic->priv; 1162 uint32_t ctrl; 1163 int32_t ret_val; 1164 uint16_t i; 1165 uint16_t phy_data; 1166 1167 DEBUGFUNC(); 1168 1169 ctrl = E1000_READ_REG(hw, CTRL); 1170 /* With 82543, we need to force speed and duplex on the MAC equal to what 1171 * the PHY speed and duplex configuration is. In addition, we need to 1172 * perform a hardware reset on the PHY to take it out of reset. 1173 */ 1174 if (hw->mac_type > e1000_82543) { 1175 ctrl |= E1000_CTRL_SLU; 1176 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1177 E1000_WRITE_REG(hw, CTRL, ctrl); 1178 } else { 1179 ctrl |= 1180 (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU); 1181 E1000_WRITE_REG(hw, CTRL, ctrl); 1182 e1000_phy_hw_reset(hw); 1183 } 1184 1185 /* Make sure we have a valid PHY */ 1186 ret_val = e1000_detect_gig_phy(hw); 1187 if (ret_val < 0) { 1188 DEBUGOUT("Error, did not detect valid phy.\n"); 1189 return ret_val; 1190 } 1191 DEBUGOUT("Phy ID = %x \n", hw->phy_id); 1192 1193 /* Enable CRS on TX. This must be set for half-duplex operation. */ 1194 if (e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data) < 0) { 1195 DEBUGOUT("PHY Read Error\n"); 1196 return -E1000_ERR_PHY; 1197 } 1198 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; 1199 1200 #if 0 1201 /* Options: 1202 * MDI/MDI-X = 0 (default) 1203 * 0 - Auto for all speeds 1204 * 1 - MDI mode 1205 * 2 - MDI-X mode 1206 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) 1207 */ 1208 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 1209 switch (hw->mdix) { 1210 case 1: 1211 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; 1212 break; 1213 case 2: 1214 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; 1215 break; 1216 case 3: 1217 phy_data |= M88E1000_PSCR_AUTO_X_1000T; 1218 break; 1219 case 0: 1220 default: 1221 phy_data |= M88E1000_PSCR_AUTO_X_MODE; 1222 break; 1223 } 1224 #else 1225 phy_data |= M88E1000_PSCR_AUTO_X_MODE; 1226 #endif 1227 1228 #if 0 1229 /* Options: 1230 * disable_polarity_correction = 0 (default) 1231 * Automatic Correction for Reversed Cable Polarity 1232 * 0 - Disabled 1233 * 1 - Enabled 1234 */ 1235 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; 1236 if (hw->disable_polarity_correction == 1) 1237 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL; 1238 #else 1239 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; 1240 #endif 1241 if (e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data) < 0) { 1242 DEBUGOUT("PHY Write Error\n"); 1243 return -E1000_ERR_PHY; 1244 } 1245 1246 /* Force TX_CLK in the Extended PHY Specific Control Register 1247 * to 25MHz clock. 1248 */ 1249 if (e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data) < 0) { 1250 DEBUGOUT("PHY Read Error\n"); 1251 return -E1000_ERR_PHY; 1252 } 1253 phy_data |= M88E1000_EPSCR_TX_CLK_25; 1254 /* Configure Master and Slave downshift values */ 1255 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK | 1256 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK); 1257 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X | 1258 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X); 1259 if (e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data) < 0) { 1260 DEBUGOUT("PHY Write Error\n"); 1261 return -E1000_ERR_PHY; 1262 } 1263 1264 /* SW Reset the PHY so all changes take effect */ 1265 ret_val = e1000_phy_reset(hw); 1266 if (ret_val < 0) { 1267 DEBUGOUT("Error Resetting the PHY\n"); 1268 return ret_val; 1269 } 1270 1271 /* Options: 1272 * autoneg = 1 (default) 1273 * PHY will advertise value(s) parsed from 1274 * autoneg_advertised and fc 1275 * autoneg = 0 1276 * PHY will be set to 10H, 10F, 100H, or 100F 1277 * depending on value parsed from forced_speed_duplex. 1278 */ 1279 1280 /* Is autoneg enabled? This is enabled by default or by software override. 1281 * If so, call e1000_phy_setup_autoneg routine to parse the 1282 * autoneg_advertised and fc options. If autoneg is NOT enabled, then the 1283 * user should have provided a speed/duplex override. If so, then call 1284 * e1000_phy_force_speed_duplex to parse and set this up. 1285 */ 1286 /* Perform some bounds checking on the hw->autoneg_advertised 1287 * parameter. If this variable is zero, then set it to the default. 1288 */ 1289 hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT; 1290 1291 /* If autoneg_advertised is zero, we assume it was not defaulted 1292 * by the calling code so we set to advertise full capability. 1293 */ 1294 if (hw->autoneg_advertised == 0) 1295 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT; 1296 1297 DEBUGOUT("Reconfiguring auto-neg advertisement params\n"); 1298 ret_val = e1000_phy_setup_autoneg(hw); 1299 if (ret_val < 0) { 1300 DEBUGOUT("Error Setting up Auto-Negotiation\n"); 1301 return ret_val; 1302 } 1303 DEBUGOUT("Restarting Auto-Neg\n"); 1304 1305 /* Restart auto-negotiation by setting the Auto Neg Enable bit and 1306 * the Auto Neg Restart bit in the PHY control register. 1307 */ 1308 if (e1000_read_phy_reg(hw, PHY_CTRL, &phy_data) < 0) { 1309 DEBUGOUT("PHY Read Error\n"); 1310 return -E1000_ERR_PHY; 1311 } 1312 phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); 1313 if (e1000_write_phy_reg(hw, PHY_CTRL, phy_data) < 0) { 1314 DEBUGOUT("PHY Write Error\n"); 1315 return -E1000_ERR_PHY; 1316 } 1317 #if 0 1318 /* Does the user want to wait for Auto-Neg to complete here, or 1319 * check at a later time (for example, callback routine). 1320 */ 1321 if (hw->wait_autoneg_complete) { 1322 ret_val = e1000_wait_autoneg(hw); 1323 if (ret_val < 0) { 1324 DEBUGOUT 1325 ("Error while waiting for autoneg to complete\n"); 1326 return ret_val; 1327 } 1328 } 1329 #else 1330 /* If we do not wait for autonegtation to complete I 1331 * do not see a valid link status. 1332 */ 1333 ret_val = e1000_wait_autoneg(hw); 1334 if (ret_val < 0) { 1335 DEBUGOUT("Error while waiting for autoneg to complete\n"); 1336 return ret_val; 1337 } 1338 #endif 1339 1340 /* Check link status. Wait up to 100 microseconds for link to become 1341 * valid. 1342 */ 1343 for (i = 0; i < 10; i++) { 1344 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) { 1345 DEBUGOUT("PHY Read Error\n"); 1346 return -E1000_ERR_PHY; 1347 } 1348 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) { 1349 DEBUGOUT("PHY Read Error\n"); 1350 return -E1000_ERR_PHY; 1351 } 1352 if (phy_data & MII_SR_LINK_STATUS) { 1353 /* We have link, so we need to finish the config process: 1354 * 1) Set up the MAC to the current PHY speed/duplex 1355 * if we are on 82543. If we 1356 * are on newer silicon, we only need to configure 1357 * collision distance in the Transmit Control Register. 1358 * 2) Set up flow control on the MAC to that established with 1359 * the link partner. 1360 */ 1361 if (hw->mac_type >= e1000_82544) { 1362 e1000_config_collision_dist(hw); 1363 } else { 1364 ret_val = e1000_config_mac_to_phy(hw); 1365 if (ret_val < 0) { 1366 DEBUGOUT 1367 ("Error configuring MAC to PHY settings\n"); 1368 return ret_val; 1369 } 1370 } 1371 ret_val = e1000_config_fc_after_link_up(hw); 1372 if (ret_val < 0) { 1373 DEBUGOUT("Error Configuring Flow Control\n"); 1374 return ret_val; 1375 } 1376 DEBUGOUT("Valid link established!!!\n"); 1377 return 0; 1378 } 1379 udelay(10); 1380 } 1381 1382 DEBUGOUT("Unable to establish link!!!\n"); 1383 return -E1000_ERR_NOLINK; 1384 } 1385 1386 /****************************************************************************** 1387 * Configures PHY autoneg and flow control advertisement settings 1388 * 1389 * hw - Struct containing variables accessed by shared code 1390 ******************************************************************************/ 1391 static int 1392 e1000_phy_setup_autoneg(struct e1000_hw *hw) 1393 { 1394 uint16_t mii_autoneg_adv_reg; 1395 uint16_t mii_1000t_ctrl_reg; 1396 1397 DEBUGFUNC(); 1398 1399 /* Read the MII Auto-Neg Advertisement Register (Address 4). */ 1400 if (e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg) < 0) { 1401 DEBUGOUT("PHY Read Error\n"); 1402 return -E1000_ERR_PHY; 1403 } 1404 1405 /* Read the MII 1000Base-T Control Register (Address 9). */ 1406 if (e1000_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg) < 0) { 1407 DEBUGOUT("PHY Read Error\n"); 1408 return -E1000_ERR_PHY; 1409 } 1410 1411 /* Need to parse both autoneg_advertised and fc and set up 1412 * the appropriate PHY registers. First we will parse for 1413 * autoneg_advertised software override. Since we can advertise 1414 * a plethora of combinations, we need to check each bit 1415 * individually. 1416 */ 1417 1418 /* First we clear all the 10/100 mb speed bits in the Auto-Neg 1419 * Advertisement Register (Address 4) and the 1000 mb speed bits in 1420 * the 1000Base-T Control Register (Address 9). 1421 */ 1422 mii_autoneg_adv_reg &= ~REG4_SPEED_MASK; 1423 mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK; 1424 1425 DEBUGOUT("autoneg_advertised %x\n", hw->autoneg_advertised); 1426 1427 /* Do we want to advertise 10 Mb Half Duplex? */ 1428 if (hw->autoneg_advertised & ADVERTISE_10_HALF) { 1429 DEBUGOUT("Advertise 10mb Half duplex\n"); 1430 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS; 1431 } 1432 1433 /* Do we want to advertise 10 Mb Full Duplex? */ 1434 if (hw->autoneg_advertised & ADVERTISE_10_FULL) { 1435 DEBUGOUT("Advertise 10mb Full duplex\n"); 1436 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS; 1437 } 1438 1439 /* Do we want to advertise 100 Mb Half Duplex? */ 1440 if (hw->autoneg_advertised & ADVERTISE_100_HALF) { 1441 DEBUGOUT("Advertise 100mb Half duplex\n"); 1442 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS; 1443 } 1444 1445 /* Do we want to advertise 100 Mb Full Duplex? */ 1446 if (hw->autoneg_advertised & ADVERTISE_100_FULL) { 1447 DEBUGOUT("Advertise 100mb Full duplex\n"); 1448 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS; 1449 } 1450 1451 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */ 1452 if (hw->autoneg_advertised & ADVERTISE_1000_HALF) { 1453 DEBUGOUT 1454 ("Advertise 1000mb Half duplex requested, request denied!\n"); 1455 } 1456 1457 /* Do we want to advertise 1000 Mb Full Duplex? */ 1458 if (hw->autoneg_advertised & ADVERTISE_1000_FULL) { 1459 DEBUGOUT("Advertise 1000mb Full duplex\n"); 1460 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS; 1461 } 1462 1463 /* Check for a software override of the flow control settings, and 1464 * setup the PHY advertisement registers accordingly. If 1465 * auto-negotiation is enabled, then software will have to set the 1466 * "PAUSE" bits to the correct value in the Auto-Negotiation 1467 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation. 1468 * 1469 * The possible values of the "fc" parameter are: 1470 * 0: Flow control is completely disabled 1471 * 1: Rx flow control is enabled (we can receive pause frames 1472 * but not send pause frames). 1473 * 2: Tx flow control is enabled (we can send pause frames 1474 * but we do not support receiving pause frames). 1475 * 3: Both Rx and TX flow control (symmetric) are enabled. 1476 * other: No software override. The flow control configuration 1477 * in the EEPROM is used. 1478 */ 1479 switch (hw->fc) { 1480 case e1000_fc_none: /* 0 */ 1481 /* Flow control (RX & TX) is completely disabled by a 1482 * software over-ride. 1483 */ 1484 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 1485 break; 1486 case e1000_fc_rx_pause: /* 1 */ 1487 /* RX Flow control is enabled, and TX Flow control is 1488 * disabled, by a software over-ride. 1489 */ 1490 /* Since there really isn't a way to advertise that we are 1491 * capable of RX Pause ONLY, we will advertise that we 1492 * support both symmetric and asymmetric RX PAUSE. Later 1493 * (in e1000_config_fc_after_link_up) we will disable the 1494 *hw's ability to send PAUSE frames. 1495 */ 1496 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 1497 break; 1498 case e1000_fc_tx_pause: /* 2 */ 1499 /* TX Flow control is enabled, and RX Flow control is 1500 * disabled, by a software over-ride. 1501 */ 1502 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR; 1503 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE; 1504 break; 1505 case e1000_fc_full: /* 3 */ 1506 /* Flow control (both RX and TX) is enabled by a software 1507 * over-ride. 1508 */ 1509 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 1510 break; 1511 default: 1512 DEBUGOUT("Flow control param set incorrectly\n"); 1513 return -E1000_ERR_CONFIG; 1514 } 1515 1516 if (e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg) < 0) { 1517 DEBUGOUT("PHY Write Error\n"); 1518 return -E1000_ERR_PHY; 1519 } 1520 1521 DEBUGOUT("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); 1522 1523 if (e1000_write_phy_reg(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg) < 0) { 1524 DEBUGOUT("PHY Write Error\n"); 1525 return -E1000_ERR_PHY; 1526 } 1527 return 0; 1528 } 1529 1530 /****************************************************************************** 1531 * Sets the collision distance in the Transmit Control register 1532 * 1533 * hw - Struct containing variables accessed by shared code 1534 * 1535 * Link should have been established previously. Reads the speed and duplex 1536 * information from the Device Status register. 1537 ******************************************************************************/ 1538 static void 1539 e1000_config_collision_dist(struct e1000_hw *hw) 1540 { 1541 uint32_t tctl; 1542 1543 tctl = E1000_READ_REG(hw, TCTL); 1544 1545 tctl &= ~E1000_TCTL_COLD; 1546 tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT; 1547 1548 E1000_WRITE_REG(hw, TCTL, tctl); 1549 E1000_WRITE_FLUSH(hw); 1550 } 1551 1552 /****************************************************************************** 1553 * Sets MAC speed and duplex settings to reflect the those in the PHY 1554 * 1555 * hw - Struct containing variables accessed by shared code 1556 * mii_reg - data to write to the MII control register 1557 * 1558 * The contents of the PHY register containing the needed information need to 1559 * be passed in. 1560 ******************************************************************************/ 1561 static int 1562 e1000_config_mac_to_phy(struct e1000_hw *hw) 1563 { 1564 uint32_t ctrl; 1565 uint16_t phy_data; 1566 1567 DEBUGFUNC(); 1568 1569 /* Read the Device Control Register and set the bits to Force Speed 1570 * and Duplex. 1571 */ 1572 ctrl = E1000_READ_REG(hw, CTRL); 1573 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1574 ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS); 1575 1576 /* Set up duplex in the Device Control and Transmit Control 1577 * registers depending on negotiated values. 1578 */ 1579 if (e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data) < 0) { 1580 DEBUGOUT("PHY Read Error\n"); 1581 return -E1000_ERR_PHY; 1582 } 1583 if (phy_data & M88E1000_PSSR_DPLX) 1584 ctrl |= E1000_CTRL_FD; 1585 else 1586 ctrl &= ~E1000_CTRL_FD; 1587 1588 e1000_config_collision_dist(hw); 1589 1590 /* Set up speed in the Device Control register depending on 1591 * negotiated values. 1592 */ 1593 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) 1594 ctrl |= E1000_CTRL_SPD_1000; 1595 else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS) 1596 ctrl |= E1000_CTRL_SPD_100; 1597 /* Write the configured values back to the Device Control Reg. */ 1598 E1000_WRITE_REG(hw, CTRL, ctrl); 1599 return 0; 1600 } 1601 1602 /****************************************************************************** 1603 * Forces the MAC's flow control settings. 1604 * 1605 * hw - Struct containing variables accessed by shared code 1606 * 1607 * Sets the TFCE and RFCE bits in the device control register to reflect 1608 * the adapter settings. TFCE and RFCE need to be explicitly set by 1609 * software when a Copper PHY is used because autonegotiation is managed 1610 * by the PHY rather than the MAC. Software must also configure these 1611 * bits when link is forced on a fiber connection. 1612 *****************************************************************************/ 1613 static int 1614 e1000_force_mac_fc(struct e1000_hw *hw) 1615 { 1616 uint32_t ctrl; 1617 1618 DEBUGFUNC(); 1619 1620 /* Get the current configuration of the Device Control Register */ 1621 ctrl = E1000_READ_REG(hw, CTRL); 1622 1623 /* Because we didn't get link via the internal auto-negotiation 1624 * mechanism (we either forced link or we got link via PHY 1625 * auto-neg), we have to manually enable/disable transmit an 1626 * receive flow control. 1627 * 1628 * The "Case" statement below enables/disable flow control 1629 * according to the "hw->fc" parameter. 1630 * 1631 * The possible values of the "fc" parameter are: 1632 * 0: Flow control is completely disabled 1633 * 1: Rx flow control is enabled (we can receive pause 1634 * frames but not send pause frames). 1635 * 2: Tx flow control is enabled (we can send pause frames 1636 * frames but we do not receive pause frames). 1637 * 3: Both Rx and TX flow control (symmetric) is enabled. 1638 * other: No other values should be possible at this point. 1639 */ 1640 1641 switch (hw->fc) { 1642 case e1000_fc_none: 1643 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE)); 1644 break; 1645 case e1000_fc_rx_pause: 1646 ctrl &= (~E1000_CTRL_TFCE); 1647 ctrl |= E1000_CTRL_RFCE; 1648 break; 1649 case e1000_fc_tx_pause: 1650 ctrl &= (~E1000_CTRL_RFCE); 1651 ctrl |= E1000_CTRL_TFCE; 1652 break; 1653 case e1000_fc_full: 1654 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE); 1655 break; 1656 default: 1657 DEBUGOUT("Flow control param set incorrectly\n"); 1658 return -E1000_ERR_CONFIG; 1659 } 1660 1661 /* Disable TX Flow Control for 82542 (rev 2.0) */ 1662 if (hw->mac_type == e1000_82542_rev2_0) 1663 ctrl &= (~E1000_CTRL_TFCE); 1664 1665 E1000_WRITE_REG(hw, CTRL, ctrl); 1666 return 0; 1667 } 1668 1669 /****************************************************************************** 1670 * Configures flow control settings after link is established 1671 * 1672 * hw - Struct containing variables accessed by shared code 1673 * 1674 * Should be called immediately after a valid link has been established. 1675 * Forces MAC flow control settings if link was forced. When in MII/GMII mode 1676 * and autonegotiation is enabled, the MAC flow control settings will be set 1677 * based on the flow control negotiated by the PHY. In TBI mode, the TFCE 1678 * and RFCE bits will be automaticaly set to the negotiated flow control mode. 1679 *****************************************************************************/ 1680 static int 1681 e1000_config_fc_after_link_up(struct e1000_hw *hw) 1682 { 1683 int32_t ret_val; 1684 uint16_t mii_status_reg; 1685 uint16_t mii_nway_adv_reg; 1686 uint16_t mii_nway_lp_ability_reg; 1687 uint16_t speed; 1688 uint16_t duplex; 1689 1690 DEBUGFUNC(); 1691 1692 /* Check for the case where we have fiber media and auto-neg failed 1693 * so we had to force link. In this case, we need to force the 1694 * configuration of the MAC to match the "fc" parameter. 1695 */ 1696 if ((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed)) { 1697 ret_val = e1000_force_mac_fc(hw); 1698 if (ret_val < 0) { 1699 DEBUGOUT("Error forcing flow control settings\n"); 1700 return ret_val; 1701 } 1702 } 1703 1704 /* Check for the case where we have copper media and auto-neg is 1705 * enabled. In this case, we need to check and see if Auto-Neg 1706 * has completed, and if so, how the PHY and link partner has 1707 * flow control configured. 1708 */ 1709 if (hw->media_type == e1000_media_type_copper) { 1710 /* Read the MII Status Register and check to see if AutoNeg 1711 * has completed. We read this twice because this reg has 1712 * some "sticky" (latched) bits. 1713 */ 1714 if (e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) { 1715 DEBUGOUT("PHY Read Error \n"); 1716 return -E1000_ERR_PHY; 1717 } 1718 if (e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) { 1719 DEBUGOUT("PHY Read Error \n"); 1720 return -E1000_ERR_PHY; 1721 } 1722 1723 if (mii_status_reg & MII_SR_AUTONEG_COMPLETE) { 1724 /* The AutoNeg process has completed, so we now need to 1725 * read both the Auto Negotiation Advertisement Register 1726 * (Address 4) and the Auto_Negotiation Base Page Ability 1727 * Register (Address 5) to determine how flow control was 1728 * negotiated. 1729 */ 1730 if (e1000_read_phy_reg 1731 (hw, PHY_AUTONEG_ADV, &mii_nway_adv_reg) < 0) { 1732 DEBUGOUT("PHY Read Error\n"); 1733 return -E1000_ERR_PHY; 1734 } 1735 if (e1000_read_phy_reg 1736 (hw, PHY_LP_ABILITY, 1737 &mii_nway_lp_ability_reg) < 0) { 1738 DEBUGOUT("PHY Read Error\n"); 1739 return -E1000_ERR_PHY; 1740 } 1741 1742 /* Two bits in the Auto Negotiation Advertisement Register 1743 * (Address 4) and two bits in the Auto Negotiation Base 1744 * Page Ability Register (Address 5) determine flow control 1745 * for both the PHY and the link partner. The following 1746 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25, 1747 * 1999, describes these PAUSE resolution bits and how flow 1748 * control is determined based upon these settings. 1749 * NOTE: DC = Don't Care 1750 * 1751 * LOCAL DEVICE | LINK PARTNER 1752 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution 1753 *-------|---------|-------|---------|-------------------- 1754 * 0 | 0 | DC | DC | e1000_fc_none 1755 * 0 | 1 | 0 | DC | e1000_fc_none 1756 * 0 | 1 | 1 | 0 | e1000_fc_none 1757 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 1758 * 1 | 0 | 0 | DC | e1000_fc_none 1759 * 1 | DC | 1 | DC | e1000_fc_full 1760 * 1 | 1 | 0 | 0 | e1000_fc_none 1761 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 1762 * 1763 */ 1764 /* Are both PAUSE bits set to 1? If so, this implies 1765 * Symmetric Flow Control is enabled at both ends. The 1766 * ASM_DIR bits are irrelevant per the spec. 1767 * 1768 * For Symmetric Flow Control: 1769 * 1770 * LOCAL DEVICE | LINK PARTNER 1771 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1772 *-------|---------|-------|---------|-------------------- 1773 * 1 | DC | 1 | DC | e1000_fc_full 1774 * 1775 */ 1776 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 1777 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) { 1778 /* Now we need to check if the user selected RX ONLY 1779 * of pause frames. In this case, we had to advertise 1780 * FULL flow control because we could not advertise RX 1781 * ONLY. Hence, we must now check to see if we need to 1782 * turn OFF the TRANSMISSION of PAUSE frames. 1783 */ 1784 if (hw->original_fc == e1000_fc_full) { 1785 hw->fc = e1000_fc_full; 1786 DEBUGOUT("Flow Control = FULL.\r\n"); 1787 } else { 1788 hw->fc = e1000_fc_rx_pause; 1789 DEBUGOUT 1790 ("Flow Control = RX PAUSE frames only.\r\n"); 1791 } 1792 } 1793 /* For receiving PAUSE frames ONLY. 1794 * 1795 * LOCAL DEVICE | LINK PARTNER 1796 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1797 *-------|---------|-------|---------|-------------------- 1798 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 1799 * 1800 */ 1801 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) && 1802 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 1803 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 1804 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) 1805 { 1806 hw->fc = e1000_fc_tx_pause; 1807 DEBUGOUT 1808 ("Flow Control = TX PAUSE frames only.\r\n"); 1809 } 1810 /* For transmitting PAUSE frames ONLY. 1811 * 1812 * LOCAL DEVICE | LINK PARTNER 1813 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1814 *-------|---------|-------|---------|-------------------- 1815 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 1816 * 1817 */ 1818 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 1819 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 1820 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 1821 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) 1822 { 1823 hw->fc = e1000_fc_rx_pause; 1824 DEBUGOUT 1825 ("Flow Control = RX PAUSE frames only.\r\n"); 1826 } 1827 /* Per the IEEE spec, at this point flow control should be 1828 * disabled. However, we want to consider that we could 1829 * be connected to a legacy switch that doesn't advertise 1830 * desired flow control, but can be forced on the link 1831 * partner. So if we advertised no flow control, that is 1832 * what we will resolve to. If we advertised some kind of 1833 * receive capability (Rx Pause Only or Full Flow Control) 1834 * and the link partner advertised none, we will configure 1835 * ourselves to enable Rx Flow Control only. We can do 1836 * this safely for two reasons: If the link partner really 1837 * didn't want flow control enabled, and we enable Rx, no 1838 * harm done since we won't be receiving any PAUSE frames 1839 * anyway. If the intent on the link partner was to have 1840 * flow control enabled, then by us enabling RX only, we 1841 * can at least receive pause frames and process them. 1842 * This is a good idea because in most cases, since we are 1843 * predominantly a server NIC, more times than not we will 1844 * be asked to delay transmission of packets than asking 1845 * our link partner to pause transmission of frames. 1846 */ 1847 else if (hw->original_fc == e1000_fc_none || 1848 hw->original_fc == e1000_fc_tx_pause) { 1849 hw->fc = e1000_fc_none; 1850 DEBUGOUT("Flow Control = NONE.\r\n"); 1851 } else { 1852 hw->fc = e1000_fc_rx_pause; 1853 DEBUGOUT 1854 ("Flow Control = RX PAUSE frames only.\r\n"); 1855 } 1856 1857 /* Now we need to do one last check... If we auto- 1858 * negotiated to HALF DUPLEX, flow control should not be 1859 * enabled per IEEE 802.3 spec. 1860 */ 1861 e1000_get_speed_and_duplex(hw, &speed, &duplex); 1862 1863 if (duplex == HALF_DUPLEX) 1864 hw->fc = e1000_fc_none; 1865 1866 /* Now we call a subroutine to actually force the MAC 1867 * controller to use the correct flow control settings. 1868 */ 1869 ret_val = e1000_force_mac_fc(hw); 1870 if (ret_val < 0) { 1871 DEBUGOUT 1872 ("Error forcing flow control settings\n"); 1873 return ret_val; 1874 } 1875 } else { 1876 DEBUGOUT 1877 ("Copper PHY and Auto Neg has not completed.\r\n"); 1878 } 1879 } 1880 return 0; 1881 } 1882 1883 /****************************************************************************** 1884 * Checks to see if the link status of the hardware has changed. 1885 * 1886 * hw - Struct containing variables accessed by shared code 1887 * 1888 * Called by any function that needs to check the link status of the adapter. 1889 *****************************************************************************/ 1890 static int 1891 e1000_check_for_link(struct eth_device *nic) 1892 { 1893 struct e1000_hw *hw = nic->priv; 1894 uint32_t rxcw; 1895 uint32_t ctrl; 1896 uint32_t status; 1897 uint32_t rctl; 1898 uint32_t signal; 1899 int32_t ret_val; 1900 uint16_t phy_data; 1901 uint16_t lp_capability; 1902 1903 DEBUGFUNC(); 1904 1905 /* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be 1906 * set when the optics detect a signal. On older adapters, it will be 1907 * cleared when there is a signal 1908 */ 1909 ctrl = E1000_READ_REG(hw, CTRL); 1910 if ((hw->mac_type > e1000_82544) && !(ctrl & E1000_CTRL_ILOS)) 1911 signal = E1000_CTRL_SWDPIN1; 1912 else 1913 signal = 0; 1914 1915 status = E1000_READ_REG(hw, STATUS); 1916 rxcw = E1000_READ_REG(hw, RXCW); 1917 DEBUGOUT("ctrl: %#08x status %#08x rxcw %#08x\n", ctrl, status, rxcw); 1918 1919 /* If we have a copper PHY then we only want to go out to the PHY 1920 * registers to see if Auto-Neg has completed and/or if our link 1921 * status has changed. The get_link_status flag will be set if we 1922 * receive a Link Status Change interrupt or we have Rx Sequence 1923 * Errors. 1924 */ 1925 if ((hw->media_type == e1000_media_type_copper) && hw->get_link_status) { 1926 /* First we want to see if the MII Status Register reports 1927 * link. If so, then we want to get the current speed/duplex 1928 * of the PHY. 1929 * Read the register twice since the link bit is sticky. 1930 */ 1931 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) { 1932 DEBUGOUT("PHY Read Error\n"); 1933 return -E1000_ERR_PHY; 1934 } 1935 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) { 1936 DEBUGOUT("PHY Read Error\n"); 1937 return -E1000_ERR_PHY; 1938 } 1939 1940 if (phy_data & MII_SR_LINK_STATUS) { 1941 hw->get_link_status = FALSE; 1942 } else { 1943 /* No link detected */ 1944 return -E1000_ERR_NOLINK; 1945 } 1946 1947 /* We have a M88E1000 PHY and Auto-Neg is enabled. If we 1948 * have Si on board that is 82544 or newer, Auto 1949 * Speed Detection takes care of MAC speed/duplex 1950 * configuration. So we only need to configure Collision 1951 * Distance in the MAC. Otherwise, we need to force 1952 * speed/duplex on the MAC to the current PHY speed/duplex 1953 * settings. 1954 */ 1955 if (hw->mac_type >= e1000_82544) 1956 e1000_config_collision_dist(hw); 1957 else { 1958 ret_val = e1000_config_mac_to_phy(hw); 1959 if (ret_val < 0) { 1960 DEBUGOUT 1961 ("Error configuring MAC to PHY settings\n"); 1962 return ret_val; 1963 } 1964 } 1965 1966 /* Configure Flow Control now that Auto-Neg has completed. First, we 1967 * need to restore the desired flow control settings because we may 1968 * have had to re-autoneg with a different link partner. 1969 */ 1970 ret_val = e1000_config_fc_after_link_up(hw); 1971 if (ret_val < 0) { 1972 DEBUGOUT("Error configuring flow control\n"); 1973 return ret_val; 1974 } 1975 1976 /* At this point we know that we are on copper and we have 1977 * auto-negotiated link. These are conditions for checking the link 1978 * parter capability register. We use the link partner capability to 1979 * determine if TBI Compatibility needs to be turned on or off. If 1980 * the link partner advertises any speed in addition to Gigabit, then 1981 * we assume that they are GMII-based, and TBI compatibility is not 1982 * needed. If no other speeds are advertised, we assume the link 1983 * partner is TBI-based, and we turn on TBI Compatibility. 1984 */ 1985 if (hw->tbi_compatibility_en) { 1986 if (e1000_read_phy_reg 1987 (hw, PHY_LP_ABILITY, &lp_capability) < 0) { 1988 DEBUGOUT("PHY Read Error\n"); 1989 return -E1000_ERR_PHY; 1990 } 1991 if (lp_capability & (NWAY_LPAR_10T_HD_CAPS | 1992 NWAY_LPAR_10T_FD_CAPS | 1993 NWAY_LPAR_100TX_HD_CAPS | 1994 NWAY_LPAR_100TX_FD_CAPS | 1995 NWAY_LPAR_100T4_CAPS)) { 1996 /* If our link partner advertises anything in addition to 1997 * gigabit, we do not need to enable TBI compatibility. 1998 */ 1999 if (hw->tbi_compatibility_on) { 2000 /* If we previously were in the mode, turn it off. */ 2001 rctl = E1000_READ_REG(hw, RCTL); 2002 rctl &= ~E1000_RCTL_SBP; 2003 E1000_WRITE_REG(hw, RCTL, rctl); 2004 hw->tbi_compatibility_on = FALSE; 2005 } 2006 } else { 2007 /* If TBI compatibility is was previously off, turn it on. For 2008 * compatibility with a TBI link partner, we will store bad 2009 * packets. Some frames have an additional byte on the end and 2010 * will look like CRC errors to to the hardware. 2011 */ 2012 if (!hw->tbi_compatibility_on) { 2013 hw->tbi_compatibility_on = TRUE; 2014 rctl = E1000_READ_REG(hw, RCTL); 2015 rctl |= E1000_RCTL_SBP; 2016 E1000_WRITE_REG(hw, RCTL, rctl); 2017 } 2018 } 2019 } 2020 } 2021 /* If we don't have link (auto-negotiation failed or link partner cannot 2022 * auto-negotiate), the cable is plugged in (we have signal), and our 2023 * link partner is not trying to auto-negotiate with us (we are receiving 2024 * idles or data), we need to force link up. We also need to give 2025 * auto-negotiation time to complete, in case the cable was just plugged 2026 * in. The autoneg_failed flag does this. 2027 */ 2028 else if ((hw->media_type == e1000_media_type_fiber) && 2029 (!(status & E1000_STATUS_LU)) && 2030 ((ctrl & E1000_CTRL_SWDPIN1) == signal) && 2031 (!(rxcw & E1000_RXCW_C))) { 2032 if (hw->autoneg_failed == 0) { 2033 hw->autoneg_failed = 1; 2034 return 0; 2035 } 2036 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\r\n"); 2037 2038 /* Disable auto-negotiation in the TXCW register */ 2039 E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE)); 2040 2041 /* Force link-up and also force full-duplex. */ 2042 ctrl = E1000_READ_REG(hw, CTRL); 2043 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 2044 E1000_WRITE_REG(hw, CTRL, ctrl); 2045 2046 /* Configure Flow Control after forcing link up. */ 2047 ret_val = e1000_config_fc_after_link_up(hw); 2048 if (ret_val < 0) { 2049 DEBUGOUT("Error configuring flow control\n"); 2050 return ret_val; 2051 } 2052 } 2053 /* If we are forcing link and we are receiving /C/ ordered sets, re-enable 2054 * auto-negotiation in the TXCW register and disable forced link in the 2055 * Device Control register in an attempt to auto-negotiate with our link 2056 * partner. 2057 */ 2058 else if ((hw->media_type == e1000_media_type_fiber) && 2059 (ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { 2060 DEBUGOUT 2061 ("RXing /C/, enable AutoNeg and stop forcing link.\r\n"); 2062 E1000_WRITE_REG(hw, TXCW, hw->txcw); 2063 E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU)); 2064 } 2065 return 0; 2066 } 2067 2068 /****************************************************************************** 2069 * Detects the current speed and duplex settings of the hardware. 2070 * 2071 * hw - Struct containing variables accessed by shared code 2072 * speed - Speed of the connection 2073 * duplex - Duplex setting of the connection 2074 *****************************************************************************/ 2075 static void 2076 e1000_get_speed_and_duplex(struct e1000_hw *hw, 2077 uint16_t * speed, uint16_t * duplex) 2078 { 2079 uint32_t status; 2080 2081 DEBUGFUNC(); 2082 2083 if (hw->mac_type >= e1000_82543) { 2084 status = E1000_READ_REG(hw, STATUS); 2085 if (status & E1000_STATUS_SPEED_1000) { 2086 *speed = SPEED_1000; 2087 DEBUGOUT("1000 Mbs, "); 2088 } else if (status & E1000_STATUS_SPEED_100) { 2089 *speed = SPEED_100; 2090 DEBUGOUT("100 Mbs, "); 2091 } else { 2092 *speed = SPEED_10; 2093 DEBUGOUT("10 Mbs, "); 2094 } 2095 2096 if (status & E1000_STATUS_FD) { 2097 *duplex = FULL_DUPLEX; 2098 DEBUGOUT("Full Duplex\r\n"); 2099 } else { 2100 *duplex = HALF_DUPLEX; 2101 DEBUGOUT(" Half Duplex\r\n"); 2102 } 2103 } else { 2104 DEBUGOUT("1000 Mbs, Full Duplex\r\n"); 2105 *speed = SPEED_1000; 2106 *duplex = FULL_DUPLEX; 2107 } 2108 } 2109 2110 /****************************************************************************** 2111 * Blocks until autoneg completes or times out (~4.5 seconds) 2112 * 2113 * hw - Struct containing variables accessed by shared code 2114 ******************************************************************************/ 2115 static int 2116 e1000_wait_autoneg(struct e1000_hw *hw) 2117 { 2118 uint16_t i; 2119 uint16_t phy_data; 2120 2121 DEBUGFUNC(); 2122 DEBUGOUT("Waiting for Auto-Neg to complete.\n"); 2123 2124 /* We will wait for autoneg to complete or 4.5 seconds to expire. */ 2125 for (i = PHY_AUTO_NEG_TIME; i > 0; i--) { 2126 /* Read the MII Status Register and wait for Auto-Neg 2127 * Complete bit to be set. 2128 */ 2129 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) { 2130 DEBUGOUT("PHY Read Error\n"); 2131 return -E1000_ERR_PHY; 2132 } 2133 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) { 2134 DEBUGOUT("PHY Read Error\n"); 2135 return -E1000_ERR_PHY; 2136 } 2137 if (phy_data & MII_SR_AUTONEG_COMPLETE) { 2138 DEBUGOUT("Auto-Neg complete.\n"); 2139 return 0; 2140 } 2141 mdelay(100); 2142 } 2143 DEBUGOUT("Auto-Neg timedout.\n"); 2144 return -E1000_ERR_TIMEOUT; 2145 } 2146 2147 /****************************************************************************** 2148 * Raises the Management Data Clock 2149 * 2150 * hw - Struct containing variables accessed by shared code 2151 * ctrl - Device control register's current value 2152 ******************************************************************************/ 2153 static void 2154 e1000_raise_mdi_clk(struct e1000_hw *hw, uint32_t * ctrl) 2155 { 2156 /* Raise the clock input to the Management Data Clock (by setting the MDC 2157 * bit), and then delay 2 microseconds. 2158 */ 2159 E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC)); 2160 E1000_WRITE_FLUSH(hw); 2161 udelay(2); 2162 } 2163 2164 /****************************************************************************** 2165 * Lowers the Management Data Clock 2166 * 2167 * hw - Struct containing variables accessed by shared code 2168 * ctrl - Device control register's current value 2169 ******************************************************************************/ 2170 static void 2171 e1000_lower_mdi_clk(struct e1000_hw *hw, uint32_t * ctrl) 2172 { 2173 /* Lower the clock input to the Management Data Clock (by clearing the MDC 2174 * bit), and then delay 2 microseconds. 2175 */ 2176 E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC)); 2177 E1000_WRITE_FLUSH(hw); 2178 udelay(2); 2179 } 2180 2181 /****************************************************************************** 2182 * Shifts data bits out to the PHY 2183 * 2184 * hw - Struct containing variables accessed by shared code 2185 * data - Data to send out to the PHY 2186 * count - Number of bits to shift out 2187 * 2188 * Bits are shifted out in MSB to LSB order. 2189 ******************************************************************************/ 2190 static void 2191 e1000_shift_out_mdi_bits(struct e1000_hw *hw, uint32_t data, uint16_t count) 2192 { 2193 uint32_t ctrl; 2194 uint32_t mask; 2195 2196 /* We need to shift "count" number of bits out to the PHY. So, the value 2197 * in the "data" parameter will be shifted out to the PHY one bit at a 2198 * time. In order to do this, "data" must be broken down into bits. 2199 */ 2200 mask = 0x01; 2201 mask <<= (count - 1); 2202 2203 ctrl = E1000_READ_REG(hw, CTRL); 2204 2205 /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */ 2206 ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR); 2207 2208 while (mask) { 2209 /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and 2210 * then raising and lowering the Management Data Clock. A "0" is 2211 * shifted out to the PHY by setting the MDIO bit to "0" and then 2212 * raising and lowering the clock. 2213 */ 2214 if (data & mask) 2215 ctrl |= E1000_CTRL_MDIO; 2216 else 2217 ctrl &= ~E1000_CTRL_MDIO; 2218 2219 E1000_WRITE_REG(hw, CTRL, ctrl); 2220 E1000_WRITE_FLUSH(hw); 2221 2222 udelay(2); 2223 2224 e1000_raise_mdi_clk(hw, &ctrl); 2225 e1000_lower_mdi_clk(hw, &ctrl); 2226 2227 mask = mask >> 1; 2228 } 2229 } 2230 2231 /****************************************************************************** 2232 * Shifts data bits in from the PHY 2233 * 2234 * hw - Struct containing variables accessed by shared code 2235 * 2236 * Bits are shifted in in MSB to LSB order. 2237 ******************************************************************************/ 2238 static uint16_t 2239 e1000_shift_in_mdi_bits(struct e1000_hw *hw) 2240 { 2241 uint32_t ctrl; 2242 uint16_t data = 0; 2243 uint8_t i; 2244 2245 /* In order to read a register from the PHY, we need to shift in a total 2246 * of 18 bits from the PHY. The first two bit (turnaround) times are used 2247 * to avoid contention on the MDIO pin when a read operation is performed. 2248 * These two bits are ignored by us and thrown away. Bits are "shifted in" 2249 * by raising the input to the Management Data Clock (setting the MDC bit), 2250 * and then reading the value of the MDIO bit. 2251 */ 2252 ctrl = E1000_READ_REG(hw, CTRL); 2253 2254 /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */ 2255 ctrl &= ~E1000_CTRL_MDIO_DIR; 2256 ctrl &= ~E1000_CTRL_MDIO; 2257 2258 E1000_WRITE_REG(hw, CTRL, ctrl); 2259 E1000_WRITE_FLUSH(hw); 2260 2261 /* Raise and Lower the clock before reading in the data. This accounts for 2262 * the turnaround bits. The first clock occurred when we clocked out the 2263 * last bit of the Register Address. 2264 */ 2265 e1000_raise_mdi_clk(hw, &ctrl); 2266 e1000_lower_mdi_clk(hw, &ctrl); 2267 2268 for (data = 0, i = 0; i < 16; i++) { 2269 data = data << 1; 2270 e1000_raise_mdi_clk(hw, &ctrl); 2271 ctrl = E1000_READ_REG(hw, CTRL); 2272 /* Check to see if we shifted in a "1". */ 2273 if (ctrl & E1000_CTRL_MDIO) 2274 data |= 1; 2275 e1000_lower_mdi_clk(hw, &ctrl); 2276 } 2277 2278 e1000_raise_mdi_clk(hw, &ctrl); 2279 e1000_lower_mdi_clk(hw, &ctrl); 2280 2281 return data; 2282 } 2283 2284 /***************************************************************************** 2285 * Reads the value from a PHY register 2286 * 2287 * hw - Struct containing variables accessed by shared code 2288 * reg_addr - address of the PHY register to read 2289 ******************************************************************************/ 2290 static int 2291 e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t * phy_data) 2292 { 2293 uint32_t i; 2294 uint32_t mdic = 0; 2295 const uint32_t phy_addr = 1; 2296 2297 if (reg_addr > MAX_PHY_REG_ADDRESS) { 2298 DEBUGOUT("PHY Address %d is out of range\n", reg_addr); 2299 return -E1000_ERR_PARAM; 2300 } 2301 2302 if (hw->mac_type > e1000_82543) { 2303 /* Set up Op-code, Phy Address, and register address in the MDI 2304 * Control register. The MAC will take care of interfacing with the 2305 * PHY to retrieve the desired data. 2306 */ 2307 mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) | 2308 (phy_addr << E1000_MDIC_PHY_SHIFT) | 2309 (E1000_MDIC_OP_READ)); 2310 2311 E1000_WRITE_REG(hw, MDIC, mdic); 2312 2313 /* Poll the ready bit to see if the MDI read completed */ 2314 for (i = 0; i < 64; i++) { 2315 udelay(10); 2316 mdic = E1000_READ_REG(hw, MDIC); 2317 if (mdic & E1000_MDIC_READY) 2318 break; 2319 } 2320 if (!(mdic & E1000_MDIC_READY)) { 2321 DEBUGOUT("MDI Read did not complete\n"); 2322 return -E1000_ERR_PHY; 2323 } 2324 if (mdic & E1000_MDIC_ERROR) { 2325 DEBUGOUT("MDI Error\n"); 2326 return -E1000_ERR_PHY; 2327 } 2328 *phy_data = (uint16_t) mdic; 2329 } else { 2330 /* We must first send a preamble through the MDIO pin to signal the 2331 * beginning of an MII instruction. This is done by sending 32 2332 * consecutive "1" bits. 2333 */ 2334 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); 2335 2336 /* Now combine the next few fields that are required for a read 2337 * operation. We use this method instead of calling the 2338 * e1000_shift_out_mdi_bits routine five different times. The format of 2339 * a MII read instruction consists of a shift out of 14 bits and is 2340 * defined as follows: 2341 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr> 2342 * followed by a shift in of 18 bits. This first two bits shifted in 2343 * are TurnAround bits used to avoid contention on the MDIO pin when a 2344 * READ operation is performed. These two bits are thrown away 2345 * followed by a shift in of 16 bits which contains the desired data. 2346 */ 2347 mdic = ((reg_addr) | (phy_addr << 5) | 2348 (PHY_OP_READ << 10) | (PHY_SOF << 12)); 2349 2350 e1000_shift_out_mdi_bits(hw, mdic, 14); 2351 2352 /* Now that we've shifted out the read command to the MII, we need to 2353 * "shift in" the 16-bit value (18 total bits) of the requested PHY 2354 * register address. 2355 */ 2356 *phy_data = e1000_shift_in_mdi_bits(hw); 2357 } 2358 return 0; 2359 } 2360 2361 /****************************************************************************** 2362 * Writes a value to a PHY register 2363 * 2364 * hw - Struct containing variables accessed by shared code 2365 * reg_addr - address of the PHY register to write 2366 * data - data to write to the PHY 2367 ******************************************************************************/ 2368 static int 2369 e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t phy_data) 2370 { 2371 uint32_t i; 2372 uint32_t mdic = 0; 2373 const uint32_t phy_addr = 1; 2374 2375 if (reg_addr > MAX_PHY_REG_ADDRESS) { 2376 DEBUGOUT("PHY Address %d is out of range\n", reg_addr); 2377 return -E1000_ERR_PARAM; 2378 } 2379 2380 if (hw->mac_type > e1000_82543) { 2381 /* Set up Op-code, Phy Address, register address, and data intended 2382 * for the PHY register in the MDI Control register. The MAC will take 2383 * care of interfacing with the PHY to send the desired data. 2384 */ 2385 mdic = (((uint32_t) phy_data) | 2386 (reg_addr << E1000_MDIC_REG_SHIFT) | 2387 (phy_addr << E1000_MDIC_PHY_SHIFT) | 2388 (E1000_MDIC_OP_WRITE)); 2389 2390 E1000_WRITE_REG(hw, MDIC, mdic); 2391 2392 /* Poll the ready bit to see if the MDI read completed */ 2393 for (i = 0; i < 64; i++) { 2394 udelay(10); 2395 mdic = E1000_READ_REG(hw, MDIC); 2396 if (mdic & E1000_MDIC_READY) 2397 break; 2398 } 2399 if (!(mdic & E1000_MDIC_READY)) { 2400 DEBUGOUT("MDI Write did not complete\n"); 2401 return -E1000_ERR_PHY; 2402 } 2403 } else { 2404 /* We'll need to use the SW defined pins to shift the write command 2405 * out to the PHY. We first send a preamble to the PHY to signal the 2406 * beginning of the MII instruction. This is done by sending 32 2407 * consecutive "1" bits. 2408 */ 2409 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); 2410 2411 /* Now combine the remaining required fields that will indicate a 2412 * write operation. We use this method instead of calling the 2413 * e1000_shift_out_mdi_bits routine for each field in the command. The 2414 * format of a MII write instruction is as follows: 2415 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>. 2416 */ 2417 mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) | 2418 (PHY_OP_WRITE << 12) | (PHY_SOF << 14)); 2419 mdic <<= 16; 2420 mdic |= (uint32_t) phy_data; 2421 2422 e1000_shift_out_mdi_bits(hw, mdic, 32); 2423 } 2424 return 0; 2425 } 2426 2427 /****************************************************************************** 2428 * Returns the PHY to the power-on reset state 2429 * 2430 * hw - Struct containing variables accessed by shared code 2431 ******************************************************************************/ 2432 static void 2433 e1000_phy_hw_reset(struct e1000_hw *hw) 2434 { 2435 uint32_t ctrl; 2436 uint32_t ctrl_ext; 2437 2438 DEBUGFUNC(); 2439 2440 DEBUGOUT("Resetting Phy...\n"); 2441 2442 if (hw->mac_type > e1000_82543) { 2443 /* Read the device control register and assert the E1000_CTRL_PHY_RST 2444 * bit. Then, take it out of reset. 2445 */ 2446 ctrl = E1000_READ_REG(hw, CTRL); 2447 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST); 2448 E1000_WRITE_FLUSH(hw); 2449 mdelay(10); 2450 E1000_WRITE_REG(hw, CTRL, ctrl); 2451 E1000_WRITE_FLUSH(hw); 2452 } else { 2453 /* Read the Extended Device Control Register, assert the PHY_RESET_DIR 2454 * bit to put the PHY into reset. Then, take it out of reset. 2455 */ 2456 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 2457 ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR; 2458 ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA; 2459 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 2460 E1000_WRITE_FLUSH(hw); 2461 mdelay(10); 2462 ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA; 2463 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 2464 E1000_WRITE_FLUSH(hw); 2465 } 2466 udelay(150); 2467 } 2468 2469 /****************************************************************************** 2470 * Resets the PHY 2471 * 2472 * hw - Struct containing variables accessed by shared code 2473 * 2474 * Sets bit 15 of the MII Control regiser 2475 ******************************************************************************/ 2476 static int 2477 e1000_phy_reset(struct e1000_hw *hw) 2478 { 2479 uint16_t phy_data; 2480 2481 DEBUGFUNC(); 2482 2483 if (e1000_read_phy_reg(hw, PHY_CTRL, &phy_data) < 0) { 2484 DEBUGOUT("PHY Read Error\n"); 2485 return -E1000_ERR_PHY; 2486 } 2487 phy_data |= MII_CR_RESET; 2488 if (e1000_write_phy_reg(hw, PHY_CTRL, phy_data) < 0) { 2489 DEBUGOUT("PHY Write Error\n"); 2490 return -E1000_ERR_PHY; 2491 } 2492 udelay(1); 2493 return 0; 2494 } 2495 2496 static int e1000_set_phy_type (struct e1000_hw *hw) 2497 { 2498 DEBUGFUNC (); 2499 2500 if (hw->mac_type == e1000_undefined) 2501 return -E1000_ERR_PHY_TYPE; 2502 2503 switch (hw->phy_id) { 2504 case M88E1000_E_PHY_ID: 2505 case M88E1000_I_PHY_ID: 2506 case M88E1011_I_PHY_ID: 2507 hw->phy_type = e1000_phy_m88; 2508 break; 2509 case IGP01E1000_I_PHY_ID: 2510 if (hw->mac_type == e1000_82541 || 2511 hw->mac_type == e1000_82541_rev_2) { 2512 hw->phy_type = e1000_phy_igp; 2513 break; 2514 } 2515 /* Fall Through */ 2516 default: 2517 /* Should never have loaded on this device */ 2518 hw->phy_type = e1000_phy_undefined; 2519 return -E1000_ERR_PHY_TYPE; 2520 } 2521 2522 return E1000_SUCCESS; 2523 } 2524 2525 /****************************************************************************** 2526 * Probes the expected PHY address for known PHY IDs 2527 * 2528 * hw - Struct containing variables accessed by shared code 2529 ******************************************************************************/ 2530 static int 2531 e1000_detect_gig_phy(struct e1000_hw *hw) 2532 { 2533 int32_t phy_init_status; 2534 uint16_t phy_id_high, phy_id_low; 2535 int match = FALSE; 2536 2537 DEBUGFUNC(); 2538 2539 /* Read the PHY ID Registers to identify which PHY is onboard. */ 2540 if (e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high) < 0) { 2541 DEBUGOUT("PHY Read Error\n"); 2542 return -E1000_ERR_PHY; 2543 } 2544 hw->phy_id = (uint32_t) (phy_id_high << 16); 2545 udelay(2); 2546 if (e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low) < 0) { 2547 DEBUGOUT("PHY Read Error\n"); 2548 return -E1000_ERR_PHY; 2549 } 2550 hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK); 2551 2552 switch (hw->mac_type) { 2553 case e1000_82543: 2554 if (hw->phy_id == M88E1000_E_PHY_ID) 2555 match = TRUE; 2556 break; 2557 case e1000_82544: 2558 if (hw->phy_id == M88E1000_I_PHY_ID) 2559 match = TRUE; 2560 break; 2561 case e1000_82540: 2562 case e1000_82545: 2563 case e1000_82546: 2564 if (hw->phy_id == M88E1011_I_PHY_ID) 2565 match = TRUE; 2566 break; 2567 case e1000_82541_rev_2: 2568 if(hw->phy_id == IGP01E1000_I_PHY_ID) 2569 match = TRUE; 2570 2571 break; 2572 default: 2573 DEBUGOUT("Invalid MAC type %d\n", hw->mac_type); 2574 return -E1000_ERR_CONFIG; 2575 } 2576 2577 phy_init_status = e1000_set_phy_type(hw); 2578 2579 if ((match) && (phy_init_status == E1000_SUCCESS)) { 2580 DEBUGOUT("PHY ID 0x%X detected\n", hw->phy_id); 2581 return 0; 2582 } 2583 DEBUGOUT("Invalid PHY ID 0x%X\n", hw->phy_id); 2584 return -E1000_ERR_PHY; 2585 } 2586 2587 /** 2588 * e1000_sw_init - Initialize general software structures (struct e1000_adapter) 2589 * 2590 * e1000_sw_init initializes the Adapter private data structure. 2591 * Fields are initialized based on PCI device information and 2592 * OS network device settings (MTU size). 2593 **/ 2594 2595 static int 2596 e1000_sw_init(struct eth_device *nic, int cardnum) 2597 { 2598 struct e1000_hw *hw = (typeof(hw)) nic->priv; 2599 int result; 2600 2601 /* PCI config space info */ 2602 pci_read_config_word(hw->pdev, PCI_VENDOR_ID, &hw->vendor_id); 2603 pci_read_config_word(hw->pdev, PCI_DEVICE_ID, &hw->device_id); 2604 pci_read_config_word(hw->pdev, PCI_SUBSYSTEM_VENDOR_ID, 2605 &hw->subsystem_vendor_id); 2606 pci_read_config_word(hw->pdev, PCI_SUBSYSTEM_ID, &hw->subsystem_id); 2607 2608 pci_read_config_byte(hw->pdev, PCI_REVISION_ID, &hw->revision_id); 2609 pci_read_config_word(hw->pdev, PCI_COMMAND, &hw->pci_cmd_word); 2610 2611 /* identify the MAC */ 2612 result = e1000_set_mac_type(hw); 2613 if (result) { 2614 E1000_ERR("Unknown MAC Type\n"); 2615 return result; 2616 } 2617 2618 /* lan a vs. lan b settings */ 2619 if (hw->mac_type == e1000_82546) 2620 /*this also works w/ multiple 82546 cards */ 2621 /*but not if they're intermingled /w other e1000s */ 2622 hw->lan_loc = (cardnum % 2) ? e1000_lan_b : e1000_lan_a; 2623 else 2624 hw->lan_loc = e1000_lan_a; 2625 2626 /* flow control settings */ 2627 hw->fc_high_water = E1000_FC_HIGH_THRESH; 2628 hw->fc_low_water = E1000_FC_LOW_THRESH; 2629 hw->fc_pause_time = E1000_FC_PAUSE_TIME; 2630 hw->fc_send_xon = 1; 2631 2632 /* Media type - copper or fiber */ 2633 2634 if (hw->mac_type >= e1000_82543) { 2635 uint32_t status = E1000_READ_REG(hw, STATUS); 2636 2637 if (status & E1000_STATUS_TBIMODE) { 2638 DEBUGOUT("fiber interface\n"); 2639 hw->media_type = e1000_media_type_fiber; 2640 } else { 2641 DEBUGOUT("copper interface\n"); 2642 hw->media_type = e1000_media_type_copper; 2643 } 2644 } else { 2645 hw->media_type = e1000_media_type_fiber; 2646 } 2647 2648 if (hw->mac_type < e1000_82543) 2649 hw->report_tx_early = 0; 2650 else 2651 hw->report_tx_early = 1; 2652 2653 hw->tbi_compatibility_en = TRUE; 2654 #if 0 2655 hw->wait_autoneg_complete = FALSE; 2656 hw->adaptive_ifs = TRUE; 2657 2658 /* Copper options */ 2659 if (hw->media_type == e1000_media_type_copper) { 2660 hw->mdix = AUTO_ALL_MODES; 2661 hw->disable_polarity_correction = FALSE; 2662 } 2663 #endif 2664 return E1000_SUCCESS; 2665 } 2666 2667 void 2668 fill_rx(struct e1000_hw *hw) 2669 { 2670 struct e1000_rx_desc *rd; 2671 2672 rx_last = rx_tail; 2673 rd = rx_base + rx_tail; 2674 rx_tail = (rx_tail + 1) % 8; 2675 memset(rd, 0, 16); 2676 rd->buffer_addr = cpu_to_le64((u32) & packet); 2677 E1000_WRITE_REG(hw, RDT, rx_tail); 2678 } 2679 2680 /** 2681 * e1000_configure_tx - Configure 8254x Transmit Unit after Reset 2682 * @adapter: board private structure 2683 * 2684 * Configure the Tx unit of the MAC after a reset. 2685 **/ 2686 2687 static void 2688 e1000_configure_tx(struct e1000_hw *hw) 2689 { 2690 unsigned long ptr; 2691 unsigned long tctl; 2692 unsigned long tipg; 2693 2694 ptr = (u32) tx_pool; 2695 if (ptr & 0xf) 2696 ptr = (ptr + 0x10) & (~0xf); 2697 2698 tx_base = (typeof(tx_base)) ptr; 2699 2700 E1000_WRITE_REG(hw, TDBAL, (u32) tx_base); 2701 E1000_WRITE_REG(hw, TDBAH, 0); 2702 2703 E1000_WRITE_REG(hw, TDLEN, 128); 2704 2705 /* Setup the HW Tx Head and Tail descriptor pointers */ 2706 E1000_WRITE_REG(hw, TDH, 0); 2707 E1000_WRITE_REG(hw, TDT, 0); 2708 tx_tail = 0; 2709 2710 /* Set the default values for the Tx Inter Packet Gap timer */ 2711 switch (hw->mac_type) { 2712 case e1000_82542_rev2_0: 2713 case e1000_82542_rev2_1: 2714 tipg = DEFAULT_82542_TIPG_IPGT; 2715 tipg |= DEFAULT_82542_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 2716 tipg |= DEFAULT_82542_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 2717 break; 2718 default: 2719 if (hw->media_type == e1000_media_type_fiber) 2720 tipg = DEFAULT_82543_TIPG_IPGT_FIBER; 2721 else 2722 tipg = DEFAULT_82543_TIPG_IPGT_COPPER; 2723 tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 2724 tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 2725 } 2726 E1000_WRITE_REG(hw, TIPG, tipg); 2727 #if 0 2728 /* Set the Tx Interrupt Delay register */ 2729 E1000_WRITE_REG(hw, TIDV, adapter->tx_int_delay); 2730 if (hw->mac_type >= e1000_82540) 2731 E1000_WRITE_REG(hw, TADV, adapter->tx_abs_int_delay); 2732 #endif 2733 /* Program the Transmit Control Register */ 2734 tctl = E1000_READ_REG(hw, TCTL); 2735 tctl &= ~E1000_TCTL_CT; 2736 tctl |= E1000_TCTL_EN | E1000_TCTL_PSP | 2737 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); 2738 E1000_WRITE_REG(hw, TCTL, tctl); 2739 2740 e1000_config_collision_dist(hw); 2741 #if 0 2742 /* Setup Transmit Descriptor Settings for this adapter */ 2743 adapter->txd_cmd = E1000_TXD_CMD_IFCS | E1000_TXD_CMD_IDE; 2744 2745 if (adapter->hw.report_tx_early == 1) 2746 adapter->txd_cmd |= E1000_TXD_CMD_RS; 2747 else 2748 adapter->txd_cmd |= E1000_TXD_CMD_RPS; 2749 #endif 2750 } 2751 2752 /** 2753 * e1000_setup_rctl - configure the receive control register 2754 * @adapter: Board private structure 2755 **/ 2756 static void 2757 e1000_setup_rctl(struct e1000_hw *hw) 2758 { 2759 uint32_t rctl; 2760 2761 rctl = E1000_READ_REG(hw, RCTL); 2762 2763 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 2764 2765 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF; /* | 2766 (hw.mc_filter_type << E1000_RCTL_MO_SHIFT); */ 2767 2768 if (hw->tbi_compatibility_on == 1) 2769 rctl |= E1000_RCTL_SBP; 2770 else 2771 rctl &= ~E1000_RCTL_SBP; 2772 2773 rctl &= ~(E1000_RCTL_SZ_4096); 2774 #if 0 2775 switch (adapter->rx_buffer_len) { 2776 case E1000_RXBUFFER_2048: 2777 default: 2778 #endif 2779 rctl |= E1000_RCTL_SZ_2048; 2780 rctl &= ~(E1000_RCTL_BSEX | E1000_RCTL_LPE); 2781 #if 0 2782 break; 2783 case E1000_RXBUFFER_4096: 2784 rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX | E1000_RCTL_LPE; 2785 break; 2786 case E1000_RXBUFFER_8192: 2787 rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX | E1000_RCTL_LPE; 2788 break; 2789 case E1000_RXBUFFER_16384: 2790 rctl |= E1000_RCTL_SZ_16384 | E1000_RCTL_BSEX | E1000_RCTL_LPE; 2791 break; 2792 } 2793 #endif 2794 E1000_WRITE_REG(hw, RCTL, rctl); 2795 } 2796 2797 /** 2798 * e1000_configure_rx - Configure 8254x Receive Unit after Reset 2799 * @adapter: board private structure 2800 * 2801 * Configure the Rx unit of the MAC after a reset. 2802 **/ 2803 static void 2804 e1000_configure_rx(struct e1000_hw *hw) 2805 { 2806 unsigned long ptr; 2807 unsigned long rctl; 2808 #if 0 2809 unsigned long rxcsum; 2810 #endif 2811 rx_tail = 0; 2812 /* make sure receives are disabled while setting up the descriptors */ 2813 rctl = E1000_READ_REG(hw, RCTL); 2814 E1000_WRITE_REG(hw, RCTL, rctl & ~E1000_RCTL_EN); 2815 #if 0 2816 /* set the Receive Delay Timer Register */ 2817 2818 E1000_WRITE_REG(hw, RDTR, adapter->rx_int_delay); 2819 #endif 2820 if (hw->mac_type >= e1000_82540) { 2821 #if 0 2822 E1000_WRITE_REG(hw, RADV, adapter->rx_abs_int_delay); 2823 #endif 2824 /* Set the interrupt throttling rate. Value is calculated 2825 * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns) */ 2826 #define MAX_INTS_PER_SEC 8000 2827 #define DEFAULT_ITR 1000000000/(MAX_INTS_PER_SEC * 256) 2828 E1000_WRITE_REG(hw, ITR, DEFAULT_ITR); 2829 } 2830 2831 /* Setup the Base and Length of the Rx Descriptor Ring */ 2832 ptr = (u32) rx_pool; 2833 if (ptr & 0xf) 2834 ptr = (ptr + 0x10) & (~0xf); 2835 rx_base = (typeof(rx_base)) ptr; 2836 E1000_WRITE_REG(hw, RDBAL, (u32) rx_base); 2837 E1000_WRITE_REG(hw, RDBAH, 0); 2838 2839 E1000_WRITE_REG(hw, RDLEN, 128); 2840 2841 /* Setup the HW Rx Head and Tail Descriptor Pointers */ 2842 E1000_WRITE_REG(hw, RDH, 0); 2843 E1000_WRITE_REG(hw, RDT, 0); 2844 #if 0 2845 /* Enable 82543 Receive Checksum Offload for TCP and UDP */ 2846 if ((adapter->hw.mac_type >= e1000_82543) && (adapter->rx_csum == TRUE)) { 2847 rxcsum = E1000_READ_REG(hw, RXCSUM); 2848 rxcsum |= E1000_RXCSUM_TUOFL; 2849 E1000_WRITE_REG(hw, RXCSUM, rxcsum); 2850 } 2851 #endif 2852 /* Enable Receives */ 2853 2854 E1000_WRITE_REG(hw, RCTL, rctl); 2855 fill_rx(hw); 2856 } 2857 2858 /************************************************************************** 2859 POLL - Wait for a frame 2860 ***************************************************************************/ 2861 static int 2862 e1000_poll(struct eth_device *nic) 2863 { 2864 struct e1000_hw *hw = nic->priv; 2865 struct e1000_rx_desc *rd; 2866 /* return true if there's an ethernet packet ready to read */ 2867 rd = rx_base + rx_last; 2868 if (!(le32_to_cpu(rd->status)) & E1000_RXD_STAT_DD) 2869 return 0; 2870 /*DEBUGOUT("recv: packet len=%d \n", rd->length); */ 2871 NetReceive((uchar *)packet, le32_to_cpu(rd->length)); 2872 fill_rx(hw); 2873 return 1; 2874 } 2875 2876 /************************************************************************** 2877 TRANSMIT - Transmit a frame 2878 ***************************************************************************/ 2879 static int 2880 e1000_transmit(struct eth_device *nic, volatile void *packet, int length) 2881 { 2882 struct e1000_hw *hw = nic->priv; 2883 struct e1000_tx_desc *txp; 2884 int i = 0; 2885 2886 txp = tx_base + tx_tail; 2887 tx_tail = (tx_tail + 1) % 8; 2888 2889 txp->buffer_addr = cpu_to_le64(virt_to_bus(packet)); 2890 txp->lower.data = cpu_to_le32(E1000_TXD_CMD_RPS | E1000_TXD_CMD_EOP | 2891 E1000_TXD_CMD_IFCS | length); 2892 txp->upper.data = 0; 2893 E1000_WRITE_REG(hw, TDT, tx_tail); 2894 2895 while (!(le32_to_cpu(txp->upper.data) & E1000_TXD_STAT_DD)) { 2896 if (i++ > TOUT_LOOP) { 2897 DEBUGOUT("e1000: tx timeout\n"); 2898 return 0; 2899 } 2900 udelay(10); /* give the nic a chance to write to the register */ 2901 } 2902 return 1; 2903 } 2904 2905 /*reset function*/ 2906 static inline int 2907 e1000_reset(struct eth_device *nic) 2908 { 2909 struct e1000_hw *hw = nic->priv; 2910 2911 e1000_reset_hw(hw); 2912 if (hw->mac_type >= e1000_82544) { 2913 E1000_WRITE_REG(hw, WUC, 0); 2914 } 2915 return e1000_init_hw(nic); 2916 } 2917 2918 /************************************************************************** 2919 DISABLE - Turn off ethernet interface 2920 ***************************************************************************/ 2921 static void 2922 e1000_disable(struct eth_device *nic) 2923 { 2924 struct e1000_hw *hw = nic->priv; 2925 2926 /* Turn off the ethernet interface */ 2927 E1000_WRITE_REG(hw, RCTL, 0); 2928 E1000_WRITE_REG(hw, TCTL, 0); 2929 2930 /* Clear the transmit ring */ 2931 E1000_WRITE_REG(hw, TDH, 0); 2932 E1000_WRITE_REG(hw, TDT, 0); 2933 2934 /* Clear the receive ring */ 2935 E1000_WRITE_REG(hw, RDH, 0); 2936 E1000_WRITE_REG(hw, RDT, 0); 2937 2938 /* put the card in its initial state */ 2939 #if 0 2940 E1000_WRITE_REG(hw, CTRL, E1000_CTRL_RST); 2941 #endif 2942 mdelay(10); 2943 2944 } 2945 2946 /************************************************************************** 2947 INIT - set up ethernet interface(s) 2948 ***************************************************************************/ 2949 static int 2950 e1000_init(struct eth_device *nic, bd_t * bis) 2951 { 2952 struct e1000_hw *hw = nic->priv; 2953 int ret_val = 0; 2954 2955 ret_val = e1000_reset(nic); 2956 if (ret_val < 0) { 2957 if ((ret_val == -E1000_ERR_NOLINK) || 2958 (ret_val == -E1000_ERR_TIMEOUT)) { 2959 E1000_ERR("Valid Link not detected\n"); 2960 } else { 2961 E1000_ERR("Hardware Initialization Failed\n"); 2962 } 2963 return 0; 2964 } 2965 e1000_configure_tx(hw); 2966 e1000_setup_rctl(hw); 2967 e1000_configure_rx(hw); 2968 return 1; 2969 } 2970 2971 /************************************************************************** 2972 PROBE - Look for an adapter, this routine's visible to the outside 2973 You should omit the last argument struct pci_device * for a non-PCI NIC 2974 ***************************************************************************/ 2975 int 2976 e1000_initialize(bd_t * bis) 2977 { 2978 pci_dev_t devno; 2979 int card_number = 0; 2980 struct eth_device *nic = NULL; 2981 struct e1000_hw *hw = NULL; 2982 u32 iobase; 2983 int idx = 0; 2984 u32 PciCommandWord; 2985 2986 while (1) { /* Find PCI device(s) */ 2987 if ((devno = pci_find_devices(supported, idx++)) < 0) { 2988 break; 2989 } 2990 2991 pci_read_config_dword(devno, PCI_BASE_ADDRESS_0, &iobase); 2992 iobase &= ~0xf; /* Mask the bits that say "this is an io addr" */ 2993 DEBUGOUT("e1000#%d: iobase 0x%08x\n", card_number, iobase); 2994 2995 pci_write_config_dword(devno, PCI_COMMAND, 2996 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); 2997 /* Check if I/O accesses and Bus Mastering are enabled. */ 2998 pci_read_config_dword(devno, PCI_COMMAND, &PciCommandWord); 2999 if (!(PciCommandWord & PCI_COMMAND_MEMORY)) { 3000 printf("Error: Can not enable MEM access.\n"); 3001 continue; 3002 } else if (!(PciCommandWord & PCI_COMMAND_MASTER)) { 3003 printf("Error: Can not enable Bus Mastering.\n"); 3004 continue; 3005 } 3006 3007 nic = (struct eth_device *) malloc(sizeof (*nic)); 3008 hw = (struct e1000_hw *) malloc(sizeof (*hw)); 3009 hw->pdev = devno; 3010 nic->priv = hw; 3011 nic->iobase = bus_to_phys(devno, iobase); 3012 3013 sprintf(nic->name, "e1000#%d", card_number); 3014 3015 /* Are these variables needed? */ 3016 #if 0 3017 hw->fc = e1000_fc_none; 3018 hw->original_fc = e1000_fc_none; 3019 #else 3020 hw->fc = e1000_fc_default; 3021 hw->original_fc = e1000_fc_default; 3022 #endif 3023 hw->autoneg_failed = 0; 3024 hw->get_link_status = TRUE; 3025 hw->hw_addr = (typeof(hw->hw_addr)) iobase; 3026 hw->mac_type = e1000_undefined; 3027 3028 /* MAC and Phy settings */ 3029 if (e1000_sw_init(nic, card_number) < 0) { 3030 free(hw); 3031 free(nic); 3032 return 0; 3033 } 3034 #if !(defined(CONFIG_AP1000) || defined(CONFIG_MVBC_1G)) 3035 if (e1000_validate_eeprom_checksum(nic) < 0) { 3036 printf("The EEPROM Checksum Is Not Valid\n"); 3037 free(hw); 3038 free(nic); 3039 return 0; 3040 } 3041 #endif 3042 e1000_read_mac_addr(nic); 3043 3044 E1000_WRITE_REG(hw, PBA, E1000_DEFAULT_PBA); 3045 3046 printf("e1000: %02x:%02x:%02x:%02x:%02x:%02x\n", 3047 nic->enetaddr[0], nic->enetaddr[1], nic->enetaddr[2], 3048 nic->enetaddr[3], nic->enetaddr[4], nic->enetaddr[5]); 3049 3050 nic->init = e1000_init; 3051 nic->recv = e1000_poll; 3052 nic->send = e1000_transmit; 3053 nic->halt = e1000_disable; 3054 3055 eth_register(nic); 3056 3057 card_number++; 3058 } 3059 return 1; 3060 } 3061