1 /************************************************************************** 2 Inter Pro 1000 for ppcboot/das-u-boot 3 Drivers are port from Intel's Linux driver e1000-4.3.15 4 and from Etherboot pro 1000 driver by mrakes at vivato dot net 5 tested on both gig copper and gig fiber boards 6 ***************************************************************************/ 7 /******************************************************************************* 8 9 10 Copyright(c) 1999 - 2002 Intel Corporation. All rights reserved. 11 12 This program is free software; you can redistribute it and/or modify it 13 under the terms of the GNU General Public License as published by the Free 14 Software Foundation; either version 2 of the License, or (at your option) 15 any later version. 16 17 This program is distributed in the hope that it will be useful, but WITHOUT 18 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 19 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 20 more details. 21 22 You should have received a copy of the GNU General Public License along with 23 this program; if not, write to the Free Software Foundation, Inc., 59 24 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 25 26 The full GNU General Public License is included in this distribution in the 27 file called LICENSE. 28 29 Contact Information: 30 Linux NICS <linux.nics@intel.com> 31 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 32 33 *******************************************************************************/ 34 /* 35 * Copyright (C) Archway Digital Solutions. 36 * 37 * written by Chrsitopher Li <cli at arcyway dot com> or <chrisl at gnuchina dot org> 38 * 2/9/2002 39 * 40 * Copyright (C) Linux Networx. 41 * Massive upgrade to work with the new intel gigabit NICs. 42 * <ebiederman at lnxi dot com> 43 */ 44 45 #include "e1000.h" 46 47 #if defined(CONFIG_CMD_NET) \ 48 && defined(CONFIG_NET_MULTI) && defined(CONFIG_E1000) 49 50 #define TOUT_LOOP 100000 51 52 #undef virt_to_bus 53 #define virt_to_bus(x) ((unsigned long)x) 54 #define bus_to_phys(devno, a) pci_mem_to_phys(devno, a) 55 #define mdelay(n) udelay((n)*1000) 56 57 #define E1000_DEFAULT_PBA 0x00000030 58 59 /* NIC specific static variables go here */ 60 61 static char tx_pool[128 + 16]; 62 static char rx_pool[128 + 16]; 63 static char packet[2096]; 64 65 static struct e1000_tx_desc *tx_base; 66 static struct e1000_rx_desc *rx_base; 67 68 static int tx_tail; 69 static int rx_tail, rx_last; 70 71 static struct pci_device_id supported[] = { 72 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82542}, 73 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82543GC_FIBER}, 74 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82543GC_COPPER}, 75 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544EI_COPPER}, 76 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544EI_FIBER}, 77 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544GC_COPPER}, 78 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544GC_LOM}, 79 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82540EM}, 80 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545EM_COPPER}, 81 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_COPPER}, 82 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545EM_FIBER}, 83 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_FIBER}, 84 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82540EM_LOM}, 85 }; 86 87 /* Function forward declarations */ 88 static int e1000_setup_link(struct eth_device *nic); 89 static int e1000_setup_fiber_link(struct eth_device *nic); 90 static int e1000_setup_copper_link(struct eth_device *nic); 91 static int e1000_phy_setup_autoneg(struct e1000_hw *hw); 92 static void e1000_config_collision_dist(struct e1000_hw *hw); 93 static int e1000_config_mac_to_phy(struct e1000_hw *hw); 94 static int e1000_config_fc_after_link_up(struct e1000_hw *hw); 95 static int e1000_check_for_link(struct eth_device *nic); 96 static int e1000_wait_autoneg(struct e1000_hw *hw); 97 static void e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t * speed, 98 uint16_t * duplex); 99 static int e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, 100 uint16_t * phy_data); 101 static int e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, 102 uint16_t phy_data); 103 static void e1000_phy_hw_reset(struct e1000_hw *hw); 104 static int e1000_phy_reset(struct e1000_hw *hw); 105 static int e1000_detect_gig_phy(struct e1000_hw *hw); 106 107 #define E1000_WRITE_REG(a, reg, value) (writel((value), ((a)->hw_addr + E1000_##reg))) 108 #define E1000_READ_REG(a, reg) (readl((a)->hw_addr + E1000_##reg)) 109 #define E1000_WRITE_REG_ARRAY(a, reg, offset, value) (\ 110 writel((value), ((a)->hw_addr + E1000_##reg + ((offset) << 2)))) 111 #define E1000_READ_REG_ARRAY(a, reg, offset) ( \ 112 readl((a)->hw_addr + E1000_##reg + ((offset) << 2))) 113 #define E1000_WRITE_FLUSH(a) {uint32_t x; x = E1000_READ_REG(a, STATUS);} 114 115 #ifndef CONFIG_AP1000 /* remove for warnings */ 116 /****************************************************************************** 117 * Raises the EEPROM's clock input. 118 * 119 * hw - Struct containing variables accessed by shared code 120 * eecd - EECD's current value 121 *****************************************************************************/ 122 static void 123 e1000_raise_ee_clk(struct e1000_hw *hw, uint32_t * eecd) 124 { 125 /* Raise the clock input to the EEPROM (by setting the SK bit), and then 126 * wait 50 microseconds. 127 */ 128 *eecd = *eecd | E1000_EECD_SK; 129 E1000_WRITE_REG(hw, EECD, *eecd); 130 E1000_WRITE_FLUSH(hw); 131 udelay(50); 132 } 133 134 /****************************************************************************** 135 * Lowers the EEPROM's clock input. 136 * 137 * hw - Struct containing variables accessed by shared code 138 * eecd - EECD's current value 139 *****************************************************************************/ 140 static void 141 e1000_lower_ee_clk(struct e1000_hw *hw, uint32_t * eecd) 142 { 143 /* Lower the clock input to the EEPROM (by clearing the SK bit), and then 144 * wait 50 microseconds. 145 */ 146 *eecd = *eecd & ~E1000_EECD_SK; 147 E1000_WRITE_REG(hw, EECD, *eecd); 148 E1000_WRITE_FLUSH(hw); 149 udelay(50); 150 } 151 152 /****************************************************************************** 153 * Shift data bits out to the EEPROM. 154 * 155 * hw - Struct containing variables accessed by shared code 156 * data - data to send to the EEPROM 157 * count - number of bits to shift out 158 *****************************************************************************/ 159 static void 160 e1000_shift_out_ee_bits(struct e1000_hw *hw, uint16_t data, uint16_t count) 161 { 162 uint32_t eecd; 163 uint32_t mask; 164 165 /* We need to shift "count" bits out to the EEPROM. So, value in the 166 * "data" parameter will be shifted out to the EEPROM one bit at a time. 167 * In order to do this, "data" must be broken down into bits. 168 */ 169 mask = 0x01 << (count - 1); 170 eecd = E1000_READ_REG(hw, EECD); 171 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI); 172 do { 173 /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1", 174 * and then raising and then lowering the clock (the SK bit controls 175 * the clock input to the EEPROM). A "0" is shifted out to the EEPROM 176 * by setting "DI" to "0" and then raising and then lowering the clock. 177 */ 178 eecd &= ~E1000_EECD_DI; 179 180 if (data & mask) 181 eecd |= E1000_EECD_DI; 182 183 E1000_WRITE_REG(hw, EECD, eecd); 184 E1000_WRITE_FLUSH(hw); 185 186 udelay(50); 187 188 e1000_raise_ee_clk(hw, &eecd); 189 e1000_lower_ee_clk(hw, &eecd); 190 191 mask = mask >> 1; 192 193 } while (mask); 194 195 /* We leave the "DI" bit set to "0" when we leave this routine. */ 196 eecd &= ~E1000_EECD_DI; 197 E1000_WRITE_REG(hw, EECD, eecd); 198 } 199 200 /****************************************************************************** 201 * Shift data bits in from the EEPROM 202 * 203 * hw - Struct containing variables accessed by shared code 204 *****************************************************************************/ 205 static uint16_t 206 e1000_shift_in_ee_bits(struct e1000_hw *hw) 207 { 208 uint32_t eecd; 209 uint32_t i; 210 uint16_t data; 211 212 /* In order to read a register from the EEPROM, we need to shift 16 bits 213 * in from the EEPROM. Bits are "shifted in" by raising the clock input to 214 * the EEPROM (setting the SK bit), and then reading the value of the "DO" 215 * bit. During this "shifting in" process the "DI" bit should always be 216 * clear.. 217 */ 218 219 eecd = E1000_READ_REG(hw, EECD); 220 221 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI); 222 data = 0; 223 224 for (i = 0; i < 16; i++) { 225 data = data << 1; 226 e1000_raise_ee_clk(hw, &eecd); 227 228 eecd = E1000_READ_REG(hw, EECD); 229 230 eecd &= ~(E1000_EECD_DI); 231 if (eecd & E1000_EECD_DO) 232 data |= 1; 233 234 e1000_lower_ee_clk(hw, &eecd); 235 } 236 237 return data; 238 } 239 240 /****************************************************************************** 241 * Prepares EEPROM for access 242 * 243 * hw - Struct containing variables accessed by shared code 244 * 245 * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This 246 * function should be called before issuing a command to the EEPROM. 247 *****************************************************************************/ 248 static void 249 e1000_setup_eeprom(struct e1000_hw *hw) 250 { 251 uint32_t eecd; 252 253 eecd = E1000_READ_REG(hw, EECD); 254 255 /* Clear SK and DI */ 256 eecd &= ~(E1000_EECD_SK | E1000_EECD_DI); 257 E1000_WRITE_REG(hw, EECD, eecd); 258 259 /* Set CS */ 260 eecd |= E1000_EECD_CS; 261 E1000_WRITE_REG(hw, EECD, eecd); 262 } 263 264 /****************************************************************************** 265 * Returns EEPROM to a "standby" state 266 * 267 * hw - Struct containing variables accessed by shared code 268 *****************************************************************************/ 269 static void 270 e1000_standby_eeprom(struct e1000_hw *hw) 271 { 272 uint32_t eecd; 273 274 eecd = E1000_READ_REG(hw, EECD); 275 276 /* Deselct EEPROM */ 277 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); 278 E1000_WRITE_REG(hw, EECD, eecd); 279 E1000_WRITE_FLUSH(hw); 280 udelay(50); 281 282 /* Clock high */ 283 eecd |= E1000_EECD_SK; 284 E1000_WRITE_REG(hw, EECD, eecd); 285 E1000_WRITE_FLUSH(hw); 286 udelay(50); 287 288 /* Select EEPROM */ 289 eecd |= E1000_EECD_CS; 290 E1000_WRITE_REG(hw, EECD, eecd); 291 E1000_WRITE_FLUSH(hw); 292 udelay(50); 293 294 /* Clock low */ 295 eecd &= ~E1000_EECD_SK; 296 E1000_WRITE_REG(hw, EECD, eecd); 297 E1000_WRITE_FLUSH(hw); 298 udelay(50); 299 } 300 301 /****************************************************************************** 302 * Reads a 16 bit word from the EEPROM. 303 * 304 * hw - Struct containing variables accessed by shared code 305 * offset - offset of word in the EEPROM to read 306 * data - word read from the EEPROM 307 *****************************************************************************/ 308 static int 309 e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset, uint16_t * data) 310 { 311 uint32_t eecd; 312 uint32_t i = 0; 313 int large_eeprom = FALSE; 314 315 /* Request EEPROM Access */ 316 if (hw->mac_type > e1000_82544) { 317 eecd = E1000_READ_REG(hw, EECD); 318 if (eecd & E1000_EECD_SIZE) 319 large_eeprom = TRUE; 320 eecd |= E1000_EECD_REQ; 321 E1000_WRITE_REG(hw, EECD, eecd); 322 eecd = E1000_READ_REG(hw, EECD); 323 while ((!(eecd & E1000_EECD_GNT)) && (i < 100)) { 324 i++; 325 udelay(10); 326 eecd = E1000_READ_REG(hw, EECD); 327 } 328 if (!(eecd & E1000_EECD_GNT)) { 329 eecd &= ~E1000_EECD_REQ; 330 E1000_WRITE_REG(hw, EECD, eecd); 331 DEBUGOUT("Could not acquire EEPROM grant\n"); 332 return -E1000_ERR_EEPROM; 333 } 334 } 335 336 /* Prepare the EEPROM for reading */ 337 e1000_setup_eeprom(hw); 338 339 /* Send the READ command (opcode + addr) */ 340 e1000_shift_out_ee_bits(hw, EEPROM_READ_OPCODE, 3); 341 e1000_shift_out_ee_bits(hw, offset, (large_eeprom) ? 8 : 6); 342 343 /* Read the data */ 344 *data = e1000_shift_in_ee_bits(hw); 345 346 /* End this read operation */ 347 e1000_standby_eeprom(hw); 348 349 /* Stop requesting EEPROM access */ 350 if (hw->mac_type > e1000_82544) { 351 eecd = E1000_READ_REG(hw, EECD); 352 eecd &= ~E1000_EECD_REQ; 353 E1000_WRITE_REG(hw, EECD, eecd); 354 } 355 356 return 0; 357 } 358 359 #if 0 360 static void 361 e1000_eeprom_cleanup(struct e1000_hw *hw) 362 { 363 uint32_t eecd; 364 365 eecd = E1000_READ_REG(hw, EECD); 366 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI); 367 E1000_WRITE_REG(hw, EECD, eecd); 368 e1000_raise_ee_clk(hw, &eecd); 369 e1000_lower_ee_clk(hw, &eecd); 370 } 371 372 static uint16_t 373 e1000_wait_eeprom_done(struct e1000_hw *hw) 374 { 375 uint32_t eecd; 376 uint32_t i; 377 378 e1000_standby_eeprom(hw); 379 for (i = 0; i < 200; i++) { 380 eecd = E1000_READ_REG(hw, EECD); 381 if (eecd & E1000_EECD_DO) 382 return (TRUE); 383 udelay(5); 384 } 385 return (FALSE); 386 } 387 388 static int 389 e1000_write_eeprom(struct e1000_hw *hw, uint16_t Reg, uint16_t Data) 390 { 391 uint32_t eecd; 392 int large_eeprom = FALSE; 393 int i = 0; 394 395 /* Request EEPROM Access */ 396 if (hw->mac_type > e1000_82544) { 397 eecd = E1000_READ_REG(hw, EECD); 398 if (eecd & E1000_EECD_SIZE) 399 large_eeprom = TRUE; 400 eecd |= E1000_EECD_REQ; 401 E1000_WRITE_REG(hw, EECD, eecd); 402 eecd = E1000_READ_REG(hw, EECD); 403 while ((!(eecd & E1000_EECD_GNT)) && (i < 100)) { 404 i++; 405 udelay(5); 406 eecd = E1000_READ_REG(hw, EECD); 407 } 408 if (!(eecd & E1000_EECD_GNT)) { 409 eecd &= ~E1000_EECD_REQ; 410 E1000_WRITE_REG(hw, EECD, eecd); 411 DEBUGOUT("Could not acquire EEPROM grant\n"); 412 return FALSE; 413 } 414 } 415 e1000_setup_eeprom(hw); 416 e1000_shift_out_ee_bits(hw, EEPROM_EWEN_OPCODE, 5); 417 e1000_shift_out_ee_bits(hw, Reg, (large_eeprom) ? 6 : 4); 418 e1000_standby_eeprom(hw); 419 e1000_shift_out_ee_bits(hw, EEPROM_WRITE_OPCODE, 3); 420 e1000_shift_out_ee_bits(hw, Reg, (large_eeprom) ? 8 : 6); 421 e1000_shift_out_ee_bits(hw, Data, 16); 422 if (!e1000_wait_eeprom_done(hw)) { 423 return FALSE; 424 } 425 e1000_shift_out_ee_bits(hw, EEPROM_EWDS_OPCODE, 5); 426 e1000_shift_out_ee_bits(hw, Reg, (large_eeprom) ? 6 : 4); 427 e1000_eeprom_cleanup(hw); 428 429 /* Stop requesting EEPROM access */ 430 if (hw->mac_type > e1000_82544) { 431 eecd = E1000_READ_REG(hw, EECD); 432 eecd &= ~E1000_EECD_REQ; 433 E1000_WRITE_REG(hw, EECD, eecd); 434 } 435 i = 0; 436 eecd = E1000_READ_REG(hw, EECD); 437 while (((eecd & E1000_EECD_GNT)) && (i < 500)) { 438 i++; 439 udelay(10); 440 eecd = E1000_READ_REG(hw, EECD); 441 } 442 if ((eecd & E1000_EECD_GNT)) { 443 DEBUGOUT("Could not release EEPROM grant\n"); 444 } 445 return TRUE; 446 } 447 #endif 448 449 /****************************************************************************** 450 * Verifies that the EEPROM has a valid checksum 451 * 452 * hw - Struct containing variables accessed by shared code 453 * 454 * Reads the first 64 16 bit words of the EEPROM and sums the values read. 455 * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is 456 * valid. 457 *****************************************************************************/ 458 static int 459 e1000_validate_eeprom_checksum(struct eth_device *nic) 460 { 461 struct e1000_hw *hw = nic->priv; 462 uint16_t checksum = 0; 463 uint16_t i, eeprom_data; 464 465 DEBUGFUNC(); 466 467 for (i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) { 468 if (e1000_read_eeprom(hw, i, &eeprom_data) < 0) { 469 DEBUGOUT("EEPROM Read Error\n"); 470 return -E1000_ERR_EEPROM; 471 } 472 checksum += eeprom_data; 473 } 474 475 if (checksum == (uint16_t) EEPROM_SUM) { 476 return 0; 477 } else { 478 DEBUGOUT("EEPROM Checksum Invalid\n"); 479 return -E1000_ERR_EEPROM; 480 } 481 } 482 #endif /* #ifndef CONFIG_AP1000 */ 483 484 /****************************************************************************** 485 * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the 486 * second function of dual function devices 487 * 488 * nic - Struct containing variables accessed by shared code 489 *****************************************************************************/ 490 static int 491 e1000_read_mac_addr(struct eth_device *nic) 492 { 493 #ifndef CONFIG_AP1000 494 struct e1000_hw *hw = nic->priv; 495 uint16_t offset; 496 uint16_t eeprom_data; 497 int i; 498 499 DEBUGFUNC(); 500 501 for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) { 502 offset = i >> 1; 503 if (e1000_read_eeprom(hw, offset, &eeprom_data) < 0) { 504 DEBUGOUT("EEPROM Read Error\n"); 505 return -E1000_ERR_EEPROM; 506 } 507 nic->enetaddr[i] = eeprom_data & 0xff; 508 nic->enetaddr[i + 1] = (eeprom_data >> 8) & 0xff; 509 } 510 if ((hw->mac_type == e1000_82546) && 511 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) { 512 /* Invert the last bit if this is the second device */ 513 nic->enetaddr[5] += 1; 514 } 515 #else 516 /* 517 * The AP1000's e1000 has no eeprom; the MAC address is stored in the 518 * environment variables. Currently this does not support the addition 519 * of a PMC e1000 card, which is certainly a possibility, so this should 520 * be updated to properly use the env variable only for the onboard e1000 521 */ 522 523 int ii; 524 char *s, *e; 525 526 DEBUGFUNC(); 527 528 s = getenv ("ethaddr"); 529 if (s == NULL){ 530 return -E1000_ERR_EEPROM; 531 } 532 else{ 533 for(ii = 0; ii < 6; ii++) { 534 nic->enetaddr[ii] = s ? simple_strtoul (s, &e, 16) : 0; 535 if (s){ 536 s = (*e) ? e + 1 : e; 537 } 538 } 539 } 540 #endif 541 return 0; 542 } 543 544 /****************************************************************************** 545 * Initializes receive address filters. 546 * 547 * hw - Struct containing variables accessed by shared code 548 * 549 * Places the MAC address in receive address register 0 and clears the rest 550 * of the receive addresss registers. Clears the multicast table. Assumes 551 * the receiver is in reset when the routine is called. 552 *****************************************************************************/ 553 static void 554 e1000_init_rx_addrs(struct eth_device *nic) 555 { 556 struct e1000_hw *hw = nic->priv; 557 uint32_t i; 558 uint32_t addr_low; 559 uint32_t addr_high; 560 561 DEBUGFUNC(); 562 563 /* Setup the receive address. */ 564 DEBUGOUT("Programming MAC Address into RAR[0]\n"); 565 addr_low = (nic->enetaddr[0] | 566 (nic->enetaddr[1] << 8) | 567 (nic->enetaddr[2] << 16) | (nic->enetaddr[3] << 24)); 568 569 addr_high = (nic->enetaddr[4] | (nic->enetaddr[5] << 8) | E1000_RAH_AV); 570 571 E1000_WRITE_REG_ARRAY(hw, RA, 0, addr_low); 572 E1000_WRITE_REG_ARRAY(hw, RA, 1, addr_high); 573 574 /* Zero out the other 15 receive addresses. */ 575 DEBUGOUT("Clearing RAR[1-15]\n"); 576 for (i = 1; i < E1000_RAR_ENTRIES; i++) { 577 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0); 578 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0); 579 } 580 } 581 582 /****************************************************************************** 583 * Clears the VLAN filer table 584 * 585 * hw - Struct containing variables accessed by shared code 586 *****************************************************************************/ 587 static void 588 e1000_clear_vfta(struct e1000_hw *hw) 589 { 590 uint32_t offset; 591 592 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) 593 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, 0); 594 } 595 596 /****************************************************************************** 597 * Set the mac type member in the hw struct. 598 * 599 * hw - Struct containing variables accessed by shared code 600 *****************************************************************************/ 601 static int 602 e1000_set_mac_type(struct e1000_hw *hw) 603 { 604 DEBUGFUNC(); 605 606 switch (hw->device_id) { 607 case E1000_DEV_ID_82542: 608 switch (hw->revision_id) { 609 case E1000_82542_2_0_REV_ID: 610 hw->mac_type = e1000_82542_rev2_0; 611 break; 612 case E1000_82542_2_1_REV_ID: 613 hw->mac_type = e1000_82542_rev2_1; 614 break; 615 default: 616 /* Invalid 82542 revision ID */ 617 return -E1000_ERR_MAC_TYPE; 618 } 619 break; 620 case E1000_DEV_ID_82543GC_FIBER: 621 case E1000_DEV_ID_82543GC_COPPER: 622 hw->mac_type = e1000_82543; 623 break; 624 case E1000_DEV_ID_82544EI_COPPER: 625 case E1000_DEV_ID_82544EI_FIBER: 626 case E1000_DEV_ID_82544GC_COPPER: 627 case E1000_DEV_ID_82544GC_LOM: 628 hw->mac_type = e1000_82544; 629 break; 630 case E1000_DEV_ID_82540EM: 631 case E1000_DEV_ID_82540EM_LOM: 632 hw->mac_type = e1000_82540; 633 break; 634 case E1000_DEV_ID_82545EM_COPPER: 635 case E1000_DEV_ID_82545EM_FIBER: 636 hw->mac_type = e1000_82545; 637 break; 638 case E1000_DEV_ID_82546EB_COPPER: 639 case E1000_DEV_ID_82546EB_FIBER: 640 hw->mac_type = e1000_82546; 641 break; 642 default: 643 /* Should never have loaded on this device */ 644 return -E1000_ERR_MAC_TYPE; 645 } 646 return E1000_SUCCESS; 647 } 648 649 /****************************************************************************** 650 * Reset the transmit and receive units; mask and clear all interrupts. 651 * 652 * hw - Struct containing variables accessed by shared code 653 *****************************************************************************/ 654 void 655 e1000_reset_hw(struct e1000_hw *hw) 656 { 657 uint32_t ctrl; 658 uint32_t ctrl_ext; 659 uint32_t icr; 660 uint32_t manc; 661 662 DEBUGFUNC(); 663 664 /* For 82542 (rev 2.0), disable MWI before issuing a device reset */ 665 if (hw->mac_type == e1000_82542_rev2_0) { 666 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n"); 667 pci_write_config_word(hw->pdev, PCI_COMMAND, 668 hw-> 669 pci_cmd_word & ~PCI_COMMAND_INVALIDATE); 670 } 671 672 /* Clear interrupt mask to stop board from generating interrupts */ 673 DEBUGOUT("Masking off all interrupts\n"); 674 E1000_WRITE_REG(hw, IMC, 0xffffffff); 675 676 /* Disable the Transmit and Receive units. Then delay to allow 677 * any pending transactions to complete before we hit the MAC with 678 * the global reset. 679 */ 680 E1000_WRITE_REG(hw, RCTL, 0); 681 E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP); 682 E1000_WRITE_FLUSH(hw); 683 684 /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */ 685 hw->tbi_compatibility_on = FALSE; 686 687 /* Delay to allow any outstanding PCI transactions to complete before 688 * resetting the device 689 */ 690 mdelay(10); 691 692 /* Issue a global reset to the MAC. This will reset the chip's 693 * transmit, receive, DMA, and link units. It will not effect 694 * the current PCI configuration. The global reset bit is self- 695 * clearing, and should clear within a microsecond. 696 */ 697 DEBUGOUT("Issuing a global reset to MAC\n"); 698 ctrl = E1000_READ_REG(hw, CTRL); 699 700 #if 0 701 if (hw->mac_type > e1000_82543) 702 E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST)); 703 else 704 #endif 705 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST)); 706 707 /* Force a reload from the EEPROM if necessary */ 708 if (hw->mac_type < e1000_82540) { 709 /* Wait for reset to complete */ 710 udelay(10); 711 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 712 ctrl_ext |= E1000_CTRL_EXT_EE_RST; 713 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 714 E1000_WRITE_FLUSH(hw); 715 /* Wait for EEPROM reload */ 716 mdelay(2); 717 } else { 718 /* Wait for EEPROM reload (it happens automatically) */ 719 mdelay(4); 720 /* Dissable HW ARPs on ASF enabled adapters */ 721 manc = E1000_READ_REG(hw, MANC); 722 manc &= ~(E1000_MANC_ARP_EN); 723 E1000_WRITE_REG(hw, MANC, manc); 724 } 725 726 /* Clear interrupt mask to stop board from generating interrupts */ 727 DEBUGOUT("Masking off all interrupts\n"); 728 E1000_WRITE_REG(hw, IMC, 0xffffffff); 729 730 /* Clear any pending interrupt events. */ 731 icr = E1000_READ_REG(hw, ICR); 732 733 /* If MWI was previously enabled, reenable it. */ 734 if (hw->mac_type == e1000_82542_rev2_0) { 735 pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word); 736 } 737 } 738 739 /****************************************************************************** 740 * Performs basic configuration of the adapter. 741 * 742 * hw - Struct containing variables accessed by shared code 743 * 744 * Assumes that the controller has previously been reset and is in a 745 * post-reset uninitialized state. Initializes the receive address registers, 746 * multicast table, and VLAN filter table. Calls routines to setup link 747 * configuration and flow control settings. Clears all on-chip counters. Leaves 748 * the transmit and receive units disabled and uninitialized. 749 *****************************************************************************/ 750 static int 751 e1000_init_hw(struct eth_device *nic) 752 { 753 struct e1000_hw *hw = nic->priv; 754 uint32_t ctrl, status; 755 uint32_t i; 756 int32_t ret_val; 757 uint16_t pcix_cmd_word; 758 uint16_t pcix_stat_hi_word; 759 uint16_t cmd_mmrbc; 760 uint16_t stat_mmrbc; 761 e1000_bus_type bus_type = e1000_bus_type_unknown; 762 763 DEBUGFUNC(); 764 #if 0 765 /* Initialize Identification LED */ 766 ret_val = e1000_id_led_init(hw); 767 if (ret_val < 0) { 768 DEBUGOUT("Error Initializing Identification LED\n"); 769 return ret_val; 770 } 771 #endif 772 /* Set the Media Type and exit with error if it is not valid. */ 773 if (hw->mac_type != e1000_82543) { 774 /* tbi_compatibility is only valid on 82543 */ 775 hw->tbi_compatibility_en = FALSE; 776 } 777 778 if (hw->mac_type >= e1000_82543) { 779 status = E1000_READ_REG(hw, STATUS); 780 if (status & E1000_STATUS_TBIMODE) { 781 hw->media_type = e1000_media_type_fiber; 782 /* tbi_compatibility not valid on fiber */ 783 hw->tbi_compatibility_en = FALSE; 784 } else { 785 hw->media_type = e1000_media_type_copper; 786 } 787 } else { 788 /* This is an 82542 (fiber only) */ 789 hw->media_type = e1000_media_type_fiber; 790 } 791 792 /* Disabling VLAN filtering. */ 793 DEBUGOUT("Initializing the IEEE VLAN\n"); 794 E1000_WRITE_REG(hw, VET, 0); 795 796 e1000_clear_vfta(hw); 797 798 /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */ 799 if (hw->mac_type == e1000_82542_rev2_0) { 800 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n"); 801 pci_write_config_word(hw->pdev, PCI_COMMAND, 802 hw-> 803 pci_cmd_word & ~PCI_COMMAND_INVALIDATE); 804 E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST); 805 E1000_WRITE_FLUSH(hw); 806 mdelay(5); 807 } 808 809 /* Setup the receive address. This involves initializing all of the Receive 810 * Address Registers (RARs 0 - 15). 811 */ 812 e1000_init_rx_addrs(nic); 813 814 /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */ 815 if (hw->mac_type == e1000_82542_rev2_0) { 816 E1000_WRITE_REG(hw, RCTL, 0); 817 E1000_WRITE_FLUSH(hw); 818 mdelay(1); 819 pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word); 820 } 821 822 /* Zero out the Multicast HASH table */ 823 DEBUGOUT("Zeroing the MTA\n"); 824 for (i = 0; i < E1000_MC_TBL_SIZE; i++) 825 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0); 826 827 #if 0 828 /* Set the PCI priority bit correctly in the CTRL register. This 829 * determines if the adapter gives priority to receives, or if it 830 * gives equal priority to transmits and receives. 831 */ 832 if (hw->dma_fairness) { 833 ctrl = E1000_READ_REG(hw, CTRL); 834 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR); 835 } 836 #endif 837 if (hw->mac_type >= e1000_82543) { 838 status = E1000_READ_REG(hw, STATUS); 839 bus_type = (status & E1000_STATUS_PCIX_MODE) ? 840 e1000_bus_type_pcix : e1000_bus_type_pci; 841 } 842 /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */ 843 if (bus_type == e1000_bus_type_pcix) { 844 pci_read_config_word(hw->pdev, PCIX_COMMAND_REGISTER, 845 &pcix_cmd_word); 846 pci_read_config_word(hw->pdev, PCIX_STATUS_REGISTER_HI, 847 &pcix_stat_hi_word); 848 cmd_mmrbc = 849 (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) >> 850 PCIX_COMMAND_MMRBC_SHIFT; 851 stat_mmrbc = 852 (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >> 853 PCIX_STATUS_HI_MMRBC_SHIFT; 854 if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K) 855 stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K; 856 if (cmd_mmrbc > stat_mmrbc) { 857 pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK; 858 pcix_cmd_word |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT; 859 pci_write_config_word(hw->pdev, PCIX_COMMAND_REGISTER, 860 pcix_cmd_word); 861 } 862 } 863 864 /* Call a subroutine to configure the link and setup flow control. */ 865 ret_val = e1000_setup_link(nic); 866 867 /* Set the transmit descriptor write-back policy */ 868 if (hw->mac_type > e1000_82544) { 869 ctrl = E1000_READ_REG(hw, TXDCTL); 870 ctrl = 871 (ctrl & ~E1000_TXDCTL_WTHRESH) | 872 E1000_TXDCTL_FULL_TX_DESC_WB; 873 E1000_WRITE_REG(hw, TXDCTL, ctrl); 874 } 875 #if 0 876 /* Clear all of the statistics registers (clear on read). It is 877 * important that we do this after we have tried to establish link 878 * because the symbol error count will increment wildly if there 879 * is no link. 880 */ 881 e1000_clear_hw_cntrs(hw); 882 #endif 883 884 return ret_val; 885 } 886 887 /****************************************************************************** 888 * Configures flow control and link settings. 889 * 890 * hw - Struct containing variables accessed by shared code 891 * 892 * Determines which flow control settings to use. Calls the apropriate media- 893 * specific link configuration function. Configures the flow control settings. 894 * Assuming the adapter has a valid link partner, a valid link should be 895 * established. Assumes the hardware has previously been reset and the 896 * transmitter and receiver are not enabled. 897 *****************************************************************************/ 898 static int 899 e1000_setup_link(struct eth_device *nic) 900 { 901 struct e1000_hw *hw = nic->priv; 902 uint32_t ctrl_ext; 903 int32_t ret_val; 904 uint16_t eeprom_data; 905 906 DEBUGFUNC(); 907 908 #ifndef CONFIG_AP1000 909 /* Read and store word 0x0F of the EEPROM. This word contains bits 910 * that determine the hardware's default PAUSE (flow control) mode, 911 * a bit that determines whether the HW defaults to enabling or 912 * disabling auto-negotiation, and the direction of the 913 * SW defined pins. If there is no SW over-ride of the flow 914 * control setting, then the variable hw->fc will 915 * be initialized based on a value in the EEPROM. 916 */ 917 if (e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, &eeprom_data) < 0) { 918 DEBUGOUT("EEPROM Read Error\n"); 919 return -E1000_ERR_EEPROM; 920 } 921 #else 922 /* we have to hardcode the proper value for our hardware. */ 923 /* this value is for the 82540EM pci card used for prototyping, and it works. */ 924 eeprom_data = 0xb220; 925 #endif 926 927 if (hw->fc == e1000_fc_default) { 928 if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0) 929 hw->fc = e1000_fc_none; 930 else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 931 EEPROM_WORD0F_ASM_DIR) 932 hw->fc = e1000_fc_tx_pause; 933 else 934 hw->fc = e1000_fc_full; 935 } 936 937 /* We want to save off the original Flow Control configuration just 938 * in case we get disconnected and then reconnected into a different 939 * hub or switch with different Flow Control capabilities. 940 */ 941 if (hw->mac_type == e1000_82542_rev2_0) 942 hw->fc &= (~e1000_fc_tx_pause); 943 944 if ((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1)) 945 hw->fc &= (~e1000_fc_rx_pause); 946 947 hw->original_fc = hw->fc; 948 949 DEBUGOUT("After fix-ups FlowControl is now = %x\n", hw->fc); 950 951 /* Take the 4 bits from EEPROM word 0x0F that determine the initial 952 * polarity value for the SW controlled pins, and setup the 953 * Extended Device Control reg with that info. 954 * This is needed because one of the SW controlled pins is used for 955 * signal detection. So this should be done before e1000_setup_pcs_link() 956 * or e1000_phy_setup() is called. 957 */ 958 if (hw->mac_type == e1000_82543) { 959 ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) << 960 SWDPIO__EXT_SHIFT); 961 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 962 } 963 964 /* Call the necessary subroutine to configure the link. */ 965 ret_val = (hw->media_type == e1000_media_type_fiber) ? 966 e1000_setup_fiber_link(nic) : e1000_setup_copper_link(nic); 967 if (ret_val < 0) { 968 return ret_val; 969 } 970 971 /* Initialize the flow control address, type, and PAUSE timer 972 * registers to their default values. This is done even if flow 973 * control is disabled, because it does not hurt anything to 974 * initialize these registers. 975 */ 976 DEBUGOUT 977 ("Initializing the Flow Control address, type and timer regs\n"); 978 979 E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW); 980 E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH); 981 E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE); 982 E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time); 983 984 /* Set the flow control receive threshold registers. Normally, 985 * these registers will be set to a default threshold that may be 986 * adjusted later by the driver's runtime code. However, if the 987 * ability to transmit pause frames in not enabled, then these 988 * registers will be set to 0. 989 */ 990 if (!(hw->fc & e1000_fc_tx_pause)) { 991 E1000_WRITE_REG(hw, FCRTL, 0); 992 E1000_WRITE_REG(hw, FCRTH, 0); 993 } else { 994 /* We need to set up the Receive Threshold high and low water marks 995 * as well as (optionally) enabling the transmission of XON frames. 996 */ 997 if (hw->fc_send_xon) { 998 E1000_WRITE_REG(hw, FCRTL, 999 (hw->fc_low_water | E1000_FCRTL_XONE)); 1000 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water); 1001 } else { 1002 E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water); 1003 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water); 1004 } 1005 } 1006 return ret_val; 1007 } 1008 1009 /****************************************************************************** 1010 * Sets up link for a fiber based adapter 1011 * 1012 * hw - Struct containing variables accessed by shared code 1013 * 1014 * Manipulates Physical Coding Sublayer functions in order to configure 1015 * link. Assumes the hardware has been previously reset and the transmitter 1016 * and receiver are not enabled. 1017 *****************************************************************************/ 1018 static int 1019 e1000_setup_fiber_link(struct eth_device *nic) 1020 { 1021 struct e1000_hw *hw = nic->priv; 1022 uint32_t ctrl; 1023 uint32_t status; 1024 uint32_t txcw = 0; 1025 uint32_t i; 1026 uint32_t signal; 1027 int32_t ret_val; 1028 1029 DEBUGFUNC(); 1030 /* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be 1031 * set when the optics detect a signal. On older adapters, it will be 1032 * cleared when there is a signal 1033 */ 1034 ctrl = E1000_READ_REG(hw, CTRL); 1035 if ((hw->mac_type > e1000_82544) && !(ctrl & E1000_CTRL_ILOS)) 1036 signal = E1000_CTRL_SWDPIN1; 1037 else 1038 signal = 0; 1039 1040 printf("signal for %s is %x (ctrl %08x)!!!!\n", nic->name, signal, 1041 ctrl); 1042 /* Take the link out of reset */ 1043 ctrl &= ~(E1000_CTRL_LRST); 1044 1045 e1000_config_collision_dist(hw); 1046 1047 /* Check for a software override of the flow control settings, and setup 1048 * the device accordingly. If auto-negotiation is enabled, then software 1049 * will have to set the "PAUSE" bits to the correct value in the Tranmsit 1050 * Config Word Register (TXCW) and re-start auto-negotiation. However, if 1051 * auto-negotiation is disabled, then software will have to manually 1052 * configure the two flow control enable bits in the CTRL register. 1053 * 1054 * The possible values of the "fc" parameter are: 1055 * 0: Flow control is completely disabled 1056 * 1: Rx flow control is enabled (we can receive pause frames, but 1057 * not send pause frames). 1058 * 2: Tx flow control is enabled (we can send pause frames but we do 1059 * not support receiving pause frames). 1060 * 3: Both Rx and TX flow control (symmetric) are enabled. 1061 */ 1062 switch (hw->fc) { 1063 case e1000_fc_none: 1064 /* Flow control is completely disabled by a software over-ride. */ 1065 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD); 1066 break; 1067 case e1000_fc_rx_pause: 1068 /* RX Flow control is enabled and TX Flow control is disabled by a 1069 * software over-ride. Since there really isn't a way to advertise 1070 * that we are capable of RX Pause ONLY, we will advertise that we 1071 * support both symmetric and asymmetric RX PAUSE. Later, we will 1072 * disable the adapter's ability to send PAUSE frames. 1073 */ 1074 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); 1075 break; 1076 case e1000_fc_tx_pause: 1077 /* TX Flow control is enabled, and RX Flow control is disabled, by a 1078 * software over-ride. 1079 */ 1080 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR); 1081 break; 1082 case e1000_fc_full: 1083 /* Flow control (both RX and TX) is enabled by a software over-ride. */ 1084 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); 1085 break; 1086 default: 1087 DEBUGOUT("Flow control param set incorrectly\n"); 1088 return -E1000_ERR_CONFIG; 1089 break; 1090 } 1091 1092 /* Since auto-negotiation is enabled, take the link out of reset (the link 1093 * will be in reset, because we previously reset the chip). This will 1094 * restart auto-negotiation. If auto-neogtiation is successful then the 1095 * link-up status bit will be set and the flow control enable bits (RFCE 1096 * and TFCE) will be set according to their negotiated value. 1097 */ 1098 DEBUGOUT("Auto-negotiation enabled (%#x)\n", txcw); 1099 1100 E1000_WRITE_REG(hw, TXCW, txcw); 1101 E1000_WRITE_REG(hw, CTRL, ctrl); 1102 E1000_WRITE_FLUSH(hw); 1103 1104 hw->txcw = txcw; 1105 mdelay(1); 1106 1107 /* If we have a signal (the cable is plugged in) then poll for a "Link-Up" 1108 * indication in the Device Status Register. Time-out if a link isn't 1109 * seen in 500 milliseconds seconds (Auto-negotiation should complete in 1110 * less than 500 milliseconds even if the other end is doing it in SW). 1111 */ 1112 if ((E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) { 1113 DEBUGOUT("Looking for Link\n"); 1114 for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) { 1115 mdelay(10); 1116 status = E1000_READ_REG(hw, STATUS); 1117 if (status & E1000_STATUS_LU) 1118 break; 1119 } 1120 if (i == (LINK_UP_TIMEOUT / 10)) { 1121 /* AutoNeg failed to achieve a link, so we'll call 1122 * e1000_check_for_link. This routine will force the link up if we 1123 * detect a signal. This will allow us to communicate with 1124 * non-autonegotiating link partners. 1125 */ 1126 DEBUGOUT("Never got a valid link from auto-neg!!!\n"); 1127 hw->autoneg_failed = 1; 1128 ret_val = e1000_check_for_link(nic); 1129 if (ret_val < 0) { 1130 DEBUGOUT("Error while checking for link\n"); 1131 return ret_val; 1132 } 1133 hw->autoneg_failed = 0; 1134 } else { 1135 hw->autoneg_failed = 0; 1136 DEBUGOUT("Valid Link Found\n"); 1137 } 1138 } else { 1139 DEBUGOUT("No Signal Detected\n"); 1140 return -E1000_ERR_NOLINK; 1141 } 1142 return 0; 1143 } 1144 1145 /****************************************************************************** 1146 * Detects which PHY is present and the speed and duplex 1147 * 1148 * hw - Struct containing variables accessed by shared code 1149 ******************************************************************************/ 1150 static int 1151 e1000_setup_copper_link(struct eth_device *nic) 1152 { 1153 struct e1000_hw *hw = nic->priv; 1154 uint32_t ctrl; 1155 int32_t ret_val; 1156 uint16_t i; 1157 uint16_t phy_data; 1158 1159 DEBUGFUNC(); 1160 1161 ctrl = E1000_READ_REG(hw, CTRL); 1162 /* With 82543, we need to force speed and duplex on the MAC equal to what 1163 * the PHY speed and duplex configuration is. In addition, we need to 1164 * perform a hardware reset on the PHY to take it out of reset. 1165 */ 1166 if (hw->mac_type > e1000_82543) { 1167 ctrl |= E1000_CTRL_SLU; 1168 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1169 E1000_WRITE_REG(hw, CTRL, ctrl); 1170 } else { 1171 ctrl |= 1172 (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU); 1173 E1000_WRITE_REG(hw, CTRL, ctrl); 1174 e1000_phy_hw_reset(hw); 1175 } 1176 1177 /* Make sure we have a valid PHY */ 1178 ret_val = e1000_detect_gig_phy(hw); 1179 if (ret_val < 0) { 1180 DEBUGOUT("Error, did not detect valid phy.\n"); 1181 return ret_val; 1182 } 1183 DEBUGOUT("Phy ID = %x \n", hw->phy_id); 1184 1185 /* Enable CRS on TX. This must be set for half-duplex operation. */ 1186 if (e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data) < 0) { 1187 DEBUGOUT("PHY Read Error\n"); 1188 return -E1000_ERR_PHY; 1189 } 1190 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; 1191 1192 #if 0 1193 /* Options: 1194 * MDI/MDI-X = 0 (default) 1195 * 0 - Auto for all speeds 1196 * 1 - MDI mode 1197 * 2 - MDI-X mode 1198 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) 1199 */ 1200 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 1201 switch (hw->mdix) { 1202 case 1: 1203 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; 1204 break; 1205 case 2: 1206 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; 1207 break; 1208 case 3: 1209 phy_data |= M88E1000_PSCR_AUTO_X_1000T; 1210 break; 1211 case 0: 1212 default: 1213 phy_data |= M88E1000_PSCR_AUTO_X_MODE; 1214 break; 1215 } 1216 #else 1217 phy_data |= M88E1000_PSCR_AUTO_X_MODE; 1218 #endif 1219 1220 #if 0 1221 /* Options: 1222 * disable_polarity_correction = 0 (default) 1223 * Automatic Correction for Reversed Cable Polarity 1224 * 0 - Disabled 1225 * 1 - Enabled 1226 */ 1227 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; 1228 if (hw->disable_polarity_correction == 1) 1229 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL; 1230 #else 1231 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; 1232 #endif 1233 if (e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data) < 0) { 1234 DEBUGOUT("PHY Write Error\n"); 1235 return -E1000_ERR_PHY; 1236 } 1237 1238 /* Force TX_CLK in the Extended PHY Specific Control Register 1239 * to 25MHz clock. 1240 */ 1241 if (e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data) < 0) { 1242 DEBUGOUT("PHY Read Error\n"); 1243 return -E1000_ERR_PHY; 1244 } 1245 phy_data |= M88E1000_EPSCR_TX_CLK_25; 1246 /* Configure Master and Slave downshift values */ 1247 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK | 1248 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK); 1249 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X | 1250 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X); 1251 if (e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data) < 0) { 1252 DEBUGOUT("PHY Write Error\n"); 1253 return -E1000_ERR_PHY; 1254 } 1255 1256 /* SW Reset the PHY so all changes take effect */ 1257 ret_val = e1000_phy_reset(hw); 1258 if (ret_val < 0) { 1259 DEBUGOUT("Error Resetting the PHY\n"); 1260 return ret_val; 1261 } 1262 1263 /* Options: 1264 * autoneg = 1 (default) 1265 * PHY will advertise value(s) parsed from 1266 * autoneg_advertised and fc 1267 * autoneg = 0 1268 * PHY will be set to 10H, 10F, 100H, or 100F 1269 * depending on value parsed from forced_speed_duplex. 1270 */ 1271 1272 /* Is autoneg enabled? This is enabled by default or by software override. 1273 * If so, call e1000_phy_setup_autoneg routine to parse the 1274 * autoneg_advertised and fc options. If autoneg is NOT enabled, then the 1275 * user should have provided a speed/duplex override. If so, then call 1276 * e1000_phy_force_speed_duplex to parse and set this up. 1277 */ 1278 /* Perform some bounds checking on the hw->autoneg_advertised 1279 * parameter. If this variable is zero, then set it to the default. 1280 */ 1281 hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT; 1282 1283 /* If autoneg_advertised is zero, we assume it was not defaulted 1284 * by the calling code so we set to advertise full capability. 1285 */ 1286 if (hw->autoneg_advertised == 0) 1287 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT; 1288 1289 DEBUGOUT("Reconfiguring auto-neg advertisement params\n"); 1290 ret_val = e1000_phy_setup_autoneg(hw); 1291 if (ret_val < 0) { 1292 DEBUGOUT("Error Setting up Auto-Negotiation\n"); 1293 return ret_val; 1294 } 1295 DEBUGOUT("Restarting Auto-Neg\n"); 1296 1297 /* Restart auto-negotiation by setting the Auto Neg Enable bit and 1298 * the Auto Neg Restart bit in the PHY control register. 1299 */ 1300 if (e1000_read_phy_reg(hw, PHY_CTRL, &phy_data) < 0) { 1301 DEBUGOUT("PHY Read Error\n"); 1302 return -E1000_ERR_PHY; 1303 } 1304 phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); 1305 if (e1000_write_phy_reg(hw, PHY_CTRL, phy_data) < 0) { 1306 DEBUGOUT("PHY Write Error\n"); 1307 return -E1000_ERR_PHY; 1308 } 1309 #if 0 1310 /* Does the user want to wait for Auto-Neg to complete here, or 1311 * check at a later time (for example, callback routine). 1312 */ 1313 if (hw->wait_autoneg_complete) { 1314 ret_val = e1000_wait_autoneg(hw); 1315 if (ret_val < 0) { 1316 DEBUGOUT 1317 ("Error while waiting for autoneg to complete\n"); 1318 return ret_val; 1319 } 1320 } 1321 #else 1322 /* If we do not wait for autonegtation to complete I 1323 * do not see a valid link status. 1324 */ 1325 ret_val = e1000_wait_autoneg(hw); 1326 if (ret_val < 0) { 1327 DEBUGOUT("Error while waiting for autoneg to complete\n"); 1328 return ret_val; 1329 } 1330 #endif 1331 1332 /* Check link status. Wait up to 100 microseconds for link to become 1333 * valid. 1334 */ 1335 for (i = 0; i < 10; i++) { 1336 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) { 1337 DEBUGOUT("PHY Read Error\n"); 1338 return -E1000_ERR_PHY; 1339 } 1340 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) { 1341 DEBUGOUT("PHY Read Error\n"); 1342 return -E1000_ERR_PHY; 1343 } 1344 if (phy_data & MII_SR_LINK_STATUS) { 1345 /* We have link, so we need to finish the config process: 1346 * 1) Set up the MAC to the current PHY speed/duplex 1347 * if we are on 82543. If we 1348 * are on newer silicon, we only need to configure 1349 * collision distance in the Transmit Control Register. 1350 * 2) Set up flow control on the MAC to that established with 1351 * the link partner. 1352 */ 1353 if (hw->mac_type >= e1000_82544) { 1354 e1000_config_collision_dist(hw); 1355 } else { 1356 ret_val = e1000_config_mac_to_phy(hw); 1357 if (ret_val < 0) { 1358 DEBUGOUT 1359 ("Error configuring MAC to PHY settings\n"); 1360 return ret_val; 1361 } 1362 } 1363 ret_val = e1000_config_fc_after_link_up(hw); 1364 if (ret_val < 0) { 1365 DEBUGOUT("Error Configuring Flow Control\n"); 1366 return ret_val; 1367 } 1368 DEBUGOUT("Valid link established!!!\n"); 1369 return 0; 1370 } 1371 udelay(10); 1372 } 1373 1374 DEBUGOUT("Unable to establish link!!!\n"); 1375 return -E1000_ERR_NOLINK; 1376 } 1377 1378 /****************************************************************************** 1379 * Configures PHY autoneg and flow control advertisement settings 1380 * 1381 * hw - Struct containing variables accessed by shared code 1382 ******************************************************************************/ 1383 static int 1384 e1000_phy_setup_autoneg(struct e1000_hw *hw) 1385 { 1386 uint16_t mii_autoneg_adv_reg; 1387 uint16_t mii_1000t_ctrl_reg; 1388 1389 DEBUGFUNC(); 1390 1391 /* Read the MII Auto-Neg Advertisement Register (Address 4). */ 1392 if (e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg) < 0) { 1393 DEBUGOUT("PHY Read Error\n"); 1394 return -E1000_ERR_PHY; 1395 } 1396 1397 /* Read the MII 1000Base-T Control Register (Address 9). */ 1398 if (e1000_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg) < 0) { 1399 DEBUGOUT("PHY Read Error\n"); 1400 return -E1000_ERR_PHY; 1401 } 1402 1403 /* Need to parse both autoneg_advertised and fc and set up 1404 * the appropriate PHY registers. First we will parse for 1405 * autoneg_advertised software override. Since we can advertise 1406 * a plethora of combinations, we need to check each bit 1407 * individually. 1408 */ 1409 1410 /* First we clear all the 10/100 mb speed bits in the Auto-Neg 1411 * Advertisement Register (Address 4) and the 1000 mb speed bits in 1412 * the 1000Base-T Control Register (Address 9). 1413 */ 1414 mii_autoneg_adv_reg &= ~REG4_SPEED_MASK; 1415 mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK; 1416 1417 DEBUGOUT("autoneg_advertised %x\n", hw->autoneg_advertised); 1418 1419 /* Do we want to advertise 10 Mb Half Duplex? */ 1420 if (hw->autoneg_advertised & ADVERTISE_10_HALF) { 1421 DEBUGOUT("Advertise 10mb Half duplex\n"); 1422 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS; 1423 } 1424 1425 /* Do we want to advertise 10 Mb Full Duplex? */ 1426 if (hw->autoneg_advertised & ADVERTISE_10_FULL) { 1427 DEBUGOUT("Advertise 10mb Full duplex\n"); 1428 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS; 1429 } 1430 1431 /* Do we want to advertise 100 Mb Half Duplex? */ 1432 if (hw->autoneg_advertised & ADVERTISE_100_HALF) { 1433 DEBUGOUT("Advertise 100mb Half duplex\n"); 1434 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS; 1435 } 1436 1437 /* Do we want to advertise 100 Mb Full Duplex? */ 1438 if (hw->autoneg_advertised & ADVERTISE_100_FULL) { 1439 DEBUGOUT("Advertise 100mb Full duplex\n"); 1440 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS; 1441 } 1442 1443 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */ 1444 if (hw->autoneg_advertised & ADVERTISE_1000_HALF) { 1445 DEBUGOUT 1446 ("Advertise 1000mb Half duplex requested, request denied!\n"); 1447 } 1448 1449 /* Do we want to advertise 1000 Mb Full Duplex? */ 1450 if (hw->autoneg_advertised & ADVERTISE_1000_FULL) { 1451 DEBUGOUT("Advertise 1000mb Full duplex\n"); 1452 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS; 1453 } 1454 1455 /* Check for a software override of the flow control settings, and 1456 * setup the PHY advertisement registers accordingly. If 1457 * auto-negotiation is enabled, then software will have to set the 1458 * "PAUSE" bits to the correct value in the Auto-Negotiation 1459 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation. 1460 * 1461 * The possible values of the "fc" parameter are: 1462 * 0: Flow control is completely disabled 1463 * 1: Rx flow control is enabled (we can receive pause frames 1464 * but not send pause frames). 1465 * 2: Tx flow control is enabled (we can send pause frames 1466 * but we do not support receiving pause frames). 1467 * 3: Both Rx and TX flow control (symmetric) are enabled. 1468 * other: No software override. The flow control configuration 1469 * in the EEPROM is used. 1470 */ 1471 switch (hw->fc) { 1472 case e1000_fc_none: /* 0 */ 1473 /* Flow control (RX & TX) is completely disabled by a 1474 * software over-ride. 1475 */ 1476 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 1477 break; 1478 case e1000_fc_rx_pause: /* 1 */ 1479 /* RX Flow control is enabled, and TX Flow control is 1480 * disabled, by a software over-ride. 1481 */ 1482 /* Since there really isn't a way to advertise that we are 1483 * capable of RX Pause ONLY, we will advertise that we 1484 * support both symmetric and asymmetric RX PAUSE. Later 1485 * (in e1000_config_fc_after_link_up) we will disable the 1486 *hw's ability to send PAUSE frames. 1487 */ 1488 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 1489 break; 1490 case e1000_fc_tx_pause: /* 2 */ 1491 /* TX Flow control is enabled, and RX Flow control is 1492 * disabled, by a software over-ride. 1493 */ 1494 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR; 1495 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE; 1496 break; 1497 case e1000_fc_full: /* 3 */ 1498 /* Flow control (both RX and TX) is enabled by a software 1499 * over-ride. 1500 */ 1501 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 1502 break; 1503 default: 1504 DEBUGOUT("Flow control param set incorrectly\n"); 1505 return -E1000_ERR_CONFIG; 1506 } 1507 1508 if (e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg) < 0) { 1509 DEBUGOUT("PHY Write Error\n"); 1510 return -E1000_ERR_PHY; 1511 } 1512 1513 DEBUGOUT("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); 1514 1515 if (e1000_write_phy_reg(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg) < 0) { 1516 DEBUGOUT("PHY Write Error\n"); 1517 return -E1000_ERR_PHY; 1518 } 1519 return 0; 1520 } 1521 1522 /****************************************************************************** 1523 * Sets the collision distance in the Transmit Control register 1524 * 1525 * hw - Struct containing variables accessed by shared code 1526 * 1527 * Link should have been established previously. Reads the speed and duplex 1528 * information from the Device Status register. 1529 ******************************************************************************/ 1530 static void 1531 e1000_config_collision_dist(struct e1000_hw *hw) 1532 { 1533 uint32_t tctl; 1534 1535 tctl = E1000_READ_REG(hw, TCTL); 1536 1537 tctl &= ~E1000_TCTL_COLD; 1538 tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT; 1539 1540 E1000_WRITE_REG(hw, TCTL, tctl); 1541 E1000_WRITE_FLUSH(hw); 1542 } 1543 1544 /****************************************************************************** 1545 * Sets MAC speed and duplex settings to reflect the those in the PHY 1546 * 1547 * hw - Struct containing variables accessed by shared code 1548 * mii_reg - data to write to the MII control register 1549 * 1550 * The contents of the PHY register containing the needed information need to 1551 * be passed in. 1552 ******************************************************************************/ 1553 static int 1554 e1000_config_mac_to_phy(struct e1000_hw *hw) 1555 { 1556 uint32_t ctrl; 1557 uint16_t phy_data; 1558 1559 DEBUGFUNC(); 1560 1561 /* Read the Device Control Register and set the bits to Force Speed 1562 * and Duplex. 1563 */ 1564 ctrl = E1000_READ_REG(hw, CTRL); 1565 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1566 ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS); 1567 1568 /* Set up duplex in the Device Control and Transmit Control 1569 * registers depending on negotiated values. 1570 */ 1571 if (e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data) < 0) { 1572 DEBUGOUT("PHY Read Error\n"); 1573 return -E1000_ERR_PHY; 1574 } 1575 if (phy_data & M88E1000_PSSR_DPLX) 1576 ctrl |= E1000_CTRL_FD; 1577 else 1578 ctrl &= ~E1000_CTRL_FD; 1579 1580 e1000_config_collision_dist(hw); 1581 1582 /* Set up speed in the Device Control register depending on 1583 * negotiated values. 1584 */ 1585 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) 1586 ctrl |= E1000_CTRL_SPD_1000; 1587 else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS) 1588 ctrl |= E1000_CTRL_SPD_100; 1589 /* Write the configured values back to the Device Control Reg. */ 1590 E1000_WRITE_REG(hw, CTRL, ctrl); 1591 return 0; 1592 } 1593 1594 /****************************************************************************** 1595 * Forces the MAC's flow control settings. 1596 * 1597 * hw - Struct containing variables accessed by shared code 1598 * 1599 * Sets the TFCE and RFCE bits in the device control register to reflect 1600 * the adapter settings. TFCE and RFCE need to be explicitly set by 1601 * software when a Copper PHY is used because autonegotiation is managed 1602 * by the PHY rather than the MAC. Software must also configure these 1603 * bits when link is forced on a fiber connection. 1604 *****************************************************************************/ 1605 static int 1606 e1000_force_mac_fc(struct e1000_hw *hw) 1607 { 1608 uint32_t ctrl; 1609 1610 DEBUGFUNC(); 1611 1612 /* Get the current configuration of the Device Control Register */ 1613 ctrl = E1000_READ_REG(hw, CTRL); 1614 1615 /* Because we didn't get link via the internal auto-negotiation 1616 * mechanism (we either forced link or we got link via PHY 1617 * auto-neg), we have to manually enable/disable transmit an 1618 * receive flow control. 1619 * 1620 * The "Case" statement below enables/disable flow control 1621 * according to the "hw->fc" parameter. 1622 * 1623 * The possible values of the "fc" parameter are: 1624 * 0: Flow control is completely disabled 1625 * 1: Rx flow control is enabled (we can receive pause 1626 * frames but not send pause frames). 1627 * 2: Tx flow control is enabled (we can send pause frames 1628 * frames but we do not receive pause frames). 1629 * 3: Both Rx and TX flow control (symmetric) is enabled. 1630 * other: No other values should be possible at this point. 1631 */ 1632 1633 switch (hw->fc) { 1634 case e1000_fc_none: 1635 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE)); 1636 break; 1637 case e1000_fc_rx_pause: 1638 ctrl &= (~E1000_CTRL_TFCE); 1639 ctrl |= E1000_CTRL_RFCE; 1640 break; 1641 case e1000_fc_tx_pause: 1642 ctrl &= (~E1000_CTRL_RFCE); 1643 ctrl |= E1000_CTRL_TFCE; 1644 break; 1645 case e1000_fc_full: 1646 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE); 1647 break; 1648 default: 1649 DEBUGOUT("Flow control param set incorrectly\n"); 1650 return -E1000_ERR_CONFIG; 1651 } 1652 1653 /* Disable TX Flow Control for 82542 (rev 2.0) */ 1654 if (hw->mac_type == e1000_82542_rev2_0) 1655 ctrl &= (~E1000_CTRL_TFCE); 1656 1657 E1000_WRITE_REG(hw, CTRL, ctrl); 1658 return 0; 1659 } 1660 1661 /****************************************************************************** 1662 * Configures flow control settings after link is established 1663 * 1664 * hw - Struct containing variables accessed by shared code 1665 * 1666 * Should be called immediately after a valid link has been established. 1667 * Forces MAC flow control settings if link was forced. When in MII/GMII mode 1668 * and autonegotiation is enabled, the MAC flow control settings will be set 1669 * based on the flow control negotiated by the PHY. In TBI mode, the TFCE 1670 * and RFCE bits will be automaticaly set to the negotiated flow control mode. 1671 *****************************************************************************/ 1672 static int 1673 e1000_config_fc_after_link_up(struct e1000_hw *hw) 1674 { 1675 int32_t ret_val; 1676 uint16_t mii_status_reg; 1677 uint16_t mii_nway_adv_reg; 1678 uint16_t mii_nway_lp_ability_reg; 1679 uint16_t speed; 1680 uint16_t duplex; 1681 1682 DEBUGFUNC(); 1683 1684 /* Check for the case where we have fiber media and auto-neg failed 1685 * so we had to force link. In this case, we need to force the 1686 * configuration of the MAC to match the "fc" parameter. 1687 */ 1688 if ((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed)) { 1689 ret_val = e1000_force_mac_fc(hw); 1690 if (ret_val < 0) { 1691 DEBUGOUT("Error forcing flow control settings\n"); 1692 return ret_val; 1693 } 1694 } 1695 1696 /* Check for the case where we have copper media and auto-neg is 1697 * enabled. In this case, we need to check and see if Auto-Neg 1698 * has completed, and if so, how the PHY and link partner has 1699 * flow control configured. 1700 */ 1701 if (hw->media_type == e1000_media_type_copper) { 1702 /* Read the MII Status Register and check to see if AutoNeg 1703 * has completed. We read this twice because this reg has 1704 * some "sticky" (latched) bits. 1705 */ 1706 if (e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) { 1707 DEBUGOUT("PHY Read Error \n"); 1708 return -E1000_ERR_PHY; 1709 } 1710 if (e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) { 1711 DEBUGOUT("PHY Read Error \n"); 1712 return -E1000_ERR_PHY; 1713 } 1714 1715 if (mii_status_reg & MII_SR_AUTONEG_COMPLETE) { 1716 /* The AutoNeg process has completed, so we now need to 1717 * read both the Auto Negotiation Advertisement Register 1718 * (Address 4) and the Auto_Negotiation Base Page Ability 1719 * Register (Address 5) to determine how flow control was 1720 * negotiated. 1721 */ 1722 if (e1000_read_phy_reg 1723 (hw, PHY_AUTONEG_ADV, &mii_nway_adv_reg) < 0) { 1724 DEBUGOUT("PHY Read Error\n"); 1725 return -E1000_ERR_PHY; 1726 } 1727 if (e1000_read_phy_reg 1728 (hw, PHY_LP_ABILITY, 1729 &mii_nway_lp_ability_reg) < 0) { 1730 DEBUGOUT("PHY Read Error\n"); 1731 return -E1000_ERR_PHY; 1732 } 1733 1734 /* Two bits in the Auto Negotiation Advertisement Register 1735 * (Address 4) and two bits in the Auto Negotiation Base 1736 * Page Ability Register (Address 5) determine flow control 1737 * for both the PHY and the link partner. The following 1738 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25, 1739 * 1999, describes these PAUSE resolution bits and how flow 1740 * control is determined based upon these settings. 1741 * NOTE: DC = Don't Care 1742 * 1743 * LOCAL DEVICE | LINK PARTNER 1744 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution 1745 *-------|---------|-------|---------|-------------------- 1746 * 0 | 0 | DC | DC | e1000_fc_none 1747 * 0 | 1 | 0 | DC | e1000_fc_none 1748 * 0 | 1 | 1 | 0 | e1000_fc_none 1749 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 1750 * 1 | 0 | 0 | DC | e1000_fc_none 1751 * 1 | DC | 1 | DC | e1000_fc_full 1752 * 1 | 1 | 0 | 0 | e1000_fc_none 1753 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 1754 * 1755 */ 1756 /* Are both PAUSE bits set to 1? If so, this implies 1757 * Symmetric Flow Control is enabled at both ends. The 1758 * ASM_DIR bits are irrelevant per the spec. 1759 * 1760 * For Symmetric Flow Control: 1761 * 1762 * LOCAL DEVICE | LINK PARTNER 1763 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1764 *-------|---------|-------|---------|-------------------- 1765 * 1 | DC | 1 | DC | e1000_fc_full 1766 * 1767 */ 1768 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 1769 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) { 1770 /* Now we need to check if the user selected RX ONLY 1771 * of pause frames. In this case, we had to advertise 1772 * FULL flow control because we could not advertise RX 1773 * ONLY. Hence, we must now check to see if we need to 1774 * turn OFF the TRANSMISSION of PAUSE frames. 1775 */ 1776 if (hw->original_fc == e1000_fc_full) { 1777 hw->fc = e1000_fc_full; 1778 DEBUGOUT("Flow Control = FULL.\r\n"); 1779 } else { 1780 hw->fc = e1000_fc_rx_pause; 1781 DEBUGOUT 1782 ("Flow Control = RX PAUSE frames only.\r\n"); 1783 } 1784 } 1785 /* For receiving PAUSE frames ONLY. 1786 * 1787 * LOCAL DEVICE | LINK PARTNER 1788 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1789 *-------|---------|-------|---------|-------------------- 1790 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 1791 * 1792 */ 1793 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) && 1794 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 1795 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 1796 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) 1797 { 1798 hw->fc = e1000_fc_tx_pause; 1799 DEBUGOUT 1800 ("Flow Control = TX PAUSE frames only.\r\n"); 1801 } 1802 /* For transmitting PAUSE frames ONLY. 1803 * 1804 * LOCAL DEVICE | LINK PARTNER 1805 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1806 *-------|---------|-------|---------|-------------------- 1807 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 1808 * 1809 */ 1810 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 1811 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 1812 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 1813 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) 1814 { 1815 hw->fc = e1000_fc_rx_pause; 1816 DEBUGOUT 1817 ("Flow Control = RX PAUSE frames only.\r\n"); 1818 } 1819 /* Per the IEEE spec, at this point flow control should be 1820 * disabled. However, we want to consider that we could 1821 * be connected to a legacy switch that doesn't advertise 1822 * desired flow control, but can be forced on the link 1823 * partner. So if we advertised no flow control, that is 1824 * what we will resolve to. If we advertised some kind of 1825 * receive capability (Rx Pause Only or Full Flow Control) 1826 * and the link partner advertised none, we will configure 1827 * ourselves to enable Rx Flow Control only. We can do 1828 * this safely for two reasons: If the link partner really 1829 * didn't want flow control enabled, and we enable Rx, no 1830 * harm done since we won't be receiving any PAUSE frames 1831 * anyway. If the intent on the link partner was to have 1832 * flow control enabled, then by us enabling RX only, we 1833 * can at least receive pause frames and process them. 1834 * This is a good idea because in most cases, since we are 1835 * predominantly a server NIC, more times than not we will 1836 * be asked to delay transmission of packets than asking 1837 * our link partner to pause transmission of frames. 1838 */ 1839 else if (hw->original_fc == e1000_fc_none || 1840 hw->original_fc == e1000_fc_tx_pause) { 1841 hw->fc = e1000_fc_none; 1842 DEBUGOUT("Flow Control = NONE.\r\n"); 1843 } else { 1844 hw->fc = e1000_fc_rx_pause; 1845 DEBUGOUT 1846 ("Flow Control = RX PAUSE frames only.\r\n"); 1847 } 1848 1849 /* Now we need to do one last check... If we auto- 1850 * negotiated to HALF DUPLEX, flow control should not be 1851 * enabled per IEEE 802.3 spec. 1852 */ 1853 e1000_get_speed_and_duplex(hw, &speed, &duplex); 1854 1855 if (duplex == HALF_DUPLEX) 1856 hw->fc = e1000_fc_none; 1857 1858 /* Now we call a subroutine to actually force the MAC 1859 * controller to use the correct flow control settings. 1860 */ 1861 ret_val = e1000_force_mac_fc(hw); 1862 if (ret_val < 0) { 1863 DEBUGOUT 1864 ("Error forcing flow control settings\n"); 1865 return ret_val; 1866 } 1867 } else { 1868 DEBUGOUT 1869 ("Copper PHY and Auto Neg has not completed.\r\n"); 1870 } 1871 } 1872 return 0; 1873 } 1874 1875 /****************************************************************************** 1876 * Checks to see if the link status of the hardware has changed. 1877 * 1878 * hw - Struct containing variables accessed by shared code 1879 * 1880 * Called by any function that needs to check the link status of the adapter. 1881 *****************************************************************************/ 1882 static int 1883 e1000_check_for_link(struct eth_device *nic) 1884 { 1885 struct e1000_hw *hw = nic->priv; 1886 uint32_t rxcw; 1887 uint32_t ctrl; 1888 uint32_t status; 1889 uint32_t rctl; 1890 uint32_t signal; 1891 int32_t ret_val; 1892 uint16_t phy_data; 1893 uint16_t lp_capability; 1894 1895 DEBUGFUNC(); 1896 1897 /* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be 1898 * set when the optics detect a signal. On older adapters, it will be 1899 * cleared when there is a signal 1900 */ 1901 ctrl = E1000_READ_REG(hw, CTRL); 1902 if ((hw->mac_type > e1000_82544) && !(ctrl & E1000_CTRL_ILOS)) 1903 signal = E1000_CTRL_SWDPIN1; 1904 else 1905 signal = 0; 1906 1907 status = E1000_READ_REG(hw, STATUS); 1908 rxcw = E1000_READ_REG(hw, RXCW); 1909 DEBUGOUT("ctrl: %#08x status %#08x rxcw %#08x\n", ctrl, status, rxcw); 1910 1911 /* If we have a copper PHY then we only want to go out to the PHY 1912 * registers to see if Auto-Neg has completed and/or if our link 1913 * status has changed. The get_link_status flag will be set if we 1914 * receive a Link Status Change interrupt or we have Rx Sequence 1915 * Errors. 1916 */ 1917 if ((hw->media_type == e1000_media_type_copper) && hw->get_link_status) { 1918 /* First we want to see if the MII Status Register reports 1919 * link. If so, then we want to get the current speed/duplex 1920 * of the PHY. 1921 * Read the register twice since the link bit is sticky. 1922 */ 1923 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) { 1924 DEBUGOUT("PHY Read Error\n"); 1925 return -E1000_ERR_PHY; 1926 } 1927 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) { 1928 DEBUGOUT("PHY Read Error\n"); 1929 return -E1000_ERR_PHY; 1930 } 1931 1932 if (phy_data & MII_SR_LINK_STATUS) { 1933 hw->get_link_status = FALSE; 1934 } else { 1935 /* No link detected */ 1936 return -E1000_ERR_NOLINK; 1937 } 1938 1939 /* We have a M88E1000 PHY and Auto-Neg is enabled. If we 1940 * have Si on board that is 82544 or newer, Auto 1941 * Speed Detection takes care of MAC speed/duplex 1942 * configuration. So we only need to configure Collision 1943 * Distance in the MAC. Otherwise, we need to force 1944 * speed/duplex on the MAC to the current PHY speed/duplex 1945 * settings. 1946 */ 1947 if (hw->mac_type >= e1000_82544) 1948 e1000_config_collision_dist(hw); 1949 else { 1950 ret_val = e1000_config_mac_to_phy(hw); 1951 if (ret_val < 0) { 1952 DEBUGOUT 1953 ("Error configuring MAC to PHY settings\n"); 1954 return ret_val; 1955 } 1956 } 1957 1958 /* Configure Flow Control now that Auto-Neg has completed. First, we 1959 * need to restore the desired flow control settings because we may 1960 * have had to re-autoneg with a different link partner. 1961 */ 1962 ret_val = e1000_config_fc_after_link_up(hw); 1963 if (ret_val < 0) { 1964 DEBUGOUT("Error configuring flow control\n"); 1965 return ret_val; 1966 } 1967 1968 /* At this point we know that we are on copper and we have 1969 * auto-negotiated link. These are conditions for checking the link 1970 * parter capability register. We use the link partner capability to 1971 * determine if TBI Compatibility needs to be turned on or off. If 1972 * the link partner advertises any speed in addition to Gigabit, then 1973 * we assume that they are GMII-based, and TBI compatibility is not 1974 * needed. If no other speeds are advertised, we assume the link 1975 * partner is TBI-based, and we turn on TBI Compatibility. 1976 */ 1977 if (hw->tbi_compatibility_en) { 1978 if (e1000_read_phy_reg 1979 (hw, PHY_LP_ABILITY, &lp_capability) < 0) { 1980 DEBUGOUT("PHY Read Error\n"); 1981 return -E1000_ERR_PHY; 1982 } 1983 if (lp_capability & (NWAY_LPAR_10T_HD_CAPS | 1984 NWAY_LPAR_10T_FD_CAPS | 1985 NWAY_LPAR_100TX_HD_CAPS | 1986 NWAY_LPAR_100TX_FD_CAPS | 1987 NWAY_LPAR_100T4_CAPS)) { 1988 /* If our link partner advertises anything in addition to 1989 * gigabit, we do not need to enable TBI compatibility. 1990 */ 1991 if (hw->tbi_compatibility_on) { 1992 /* If we previously were in the mode, turn it off. */ 1993 rctl = E1000_READ_REG(hw, RCTL); 1994 rctl &= ~E1000_RCTL_SBP; 1995 E1000_WRITE_REG(hw, RCTL, rctl); 1996 hw->tbi_compatibility_on = FALSE; 1997 } 1998 } else { 1999 /* If TBI compatibility is was previously off, turn it on. For 2000 * compatibility with a TBI link partner, we will store bad 2001 * packets. Some frames have an additional byte on the end and 2002 * will look like CRC errors to to the hardware. 2003 */ 2004 if (!hw->tbi_compatibility_on) { 2005 hw->tbi_compatibility_on = TRUE; 2006 rctl = E1000_READ_REG(hw, RCTL); 2007 rctl |= E1000_RCTL_SBP; 2008 E1000_WRITE_REG(hw, RCTL, rctl); 2009 } 2010 } 2011 } 2012 } 2013 /* If we don't have link (auto-negotiation failed or link partner cannot 2014 * auto-negotiate), the cable is plugged in (we have signal), and our 2015 * link partner is not trying to auto-negotiate with us (we are receiving 2016 * idles or data), we need to force link up. We also need to give 2017 * auto-negotiation time to complete, in case the cable was just plugged 2018 * in. The autoneg_failed flag does this. 2019 */ 2020 else if ((hw->media_type == e1000_media_type_fiber) && 2021 (!(status & E1000_STATUS_LU)) && 2022 ((ctrl & E1000_CTRL_SWDPIN1) == signal) && 2023 (!(rxcw & E1000_RXCW_C))) { 2024 if (hw->autoneg_failed == 0) { 2025 hw->autoneg_failed = 1; 2026 return 0; 2027 } 2028 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\r\n"); 2029 2030 /* Disable auto-negotiation in the TXCW register */ 2031 E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE)); 2032 2033 /* Force link-up and also force full-duplex. */ 2034 ctrl = E1000_READ_REG(hw, CTRL); 2035 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 2036 E1000_WRITE_REG(hw, CTRL, ctrl); 2037 2038 /* Configure Flow Control after forcing link up. */ 2039 ret_val = e1000_config_fc_after_link_up(hw); 2040 if (ret_val < 0) { 2041 DEBUGOUT("Error configuring flow control\n"); 2042 return ret_val; 2043 } 2044 } 2045 /* If we are forcing link and we are receiving /C/ ordered sets, re-enable 2046 * auto-negotiation in the TXCW register and disable forced link in the 2047 * Device Control register in an attempt to auto-negotiate with our link 2048 * partner. 2049 */ 2050 else if ((hw->media_type == e1000_media_type_fiber) && 2051 (ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { 2052 DEBUGOUT 2053 ("RXing /C/, enable AutoNeg and stop forcing link.\r\n"); 2054 E1000_WRITE_REG(hw, TXCW, hw->txcw); 2055 E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU)); 2056 } 2057 return 0; 2058 } 2059 2060 /****************************************************************************** 2061 * Detects the current speed and duplex settings of the hardware. 2062 * 2063 * hw - Struct containing variables accessed by shared code 2064 * speed - Speed of the connection 2065 * duplex - Duplex setting of the connection 2066 *****************************************************************************/ 2067 static void 2068 e1000_get_speed_and_duplex(struct e1000_hw *hw, 2069 uint16_t * speed, uint16_t * duplex) 2070 { 2071 uint32_t status; 2072 2073 DEBUGFUNC(); 2074 2075 if (hw->mac_type >= e1000_82543) { 2076 status = E1000_READ_REG(hw, STATUS); 2077 if (status & E1000_STATUS_SPEED_1000) { 2078 *speed = SPEED_1000; 2079 DEBUGOUT("1000 Mbs, "); 2080 } else if (status & E1000_STATUS_SPEED_100) { 2081 *speed = SPEED_100; 2082 DEBUGOUT("100 Mbs, "); 2083 } else { 2084 *speed = SPEED_10; 2085 DEBUGOUT("10 Mbs, "); 2086 } 2087 2088 if (status & E1000_STATUS_FD) { 2089 *duplex = FULL_DUPLEX; 2090 DEBUGOUT("Full Duplex\r\n"); 2091 } else { 2092 *duplex = HALF_DUPLEX; 2093 DEBUGOUT(" Half Duplex\r\n"); 2094 } 2095 } else { 2096 DEBUGOUT("1000 Mbs, Full Duplex\r\n"); 2097 *speed = SPEED_1000; 2098 *duplex = FULL_DUPLEX; 2099 } 2100 } 2101 2102 /****************************************************************************** 2103 * Blocks until autoneg completes or times out (~4.5 seconds) 2104 * 2105 * hw - Struct containing variables accessed by shared code 2106 ******************************************************************************/ 2107 static int 2108 e1000_wait_autoneg(struct e1000_hw *hw) 2109 { 2110 uint16_t i; 2111 uint16_t phy_data; 2112 2113 DEBUGFUNC(); 2114 DEBUGOUT("Waiting for Auto-Neg to complete.\n"); 2115 2116 /* We will wait for autoneg to complete or 4.5 seconds to expire. */ 2117 for (i = PHY_AUTO_NEG_TIME; i > 0; i--) { 2118 /* Read the MII Status Register and wait for Auto-Neg 2119 * Complete bit to be set. 2120 */ 2121 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) { 2122 DEBUGOUT("PHY Read Error\n"); 2123 return -E1000_ERR_PHY; 2124 } 2125 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) { 2126 DEBUGOUT("PHY Read Error\n"); 2127 return -E1000_ERR_PHY; 2128 } 2129 if (phy_data & MII_SR_AUTONEG_COMPLETE) { 2130 DEBUGOUT("Auto-Neg complete.\n"); 2131 return 0; 2132 } 2133 mdelay(100); 2134 } 2135 DEBUGOUT("Auto-Neg timedout.\n"); 2136 return -E1000_ERR_TIMEOUT; 2137 } 2138 2139 /****************************************************************************** 2140 * Raises the Management Data Clock 2141 * 2142 * hw - Struct containing variables accessed by shared code 2143 * ctrl - Device control register's current value 2144 ******************************************************************************/ 2145 static void 2146 e1000_raise_mdi_clk(struct e1000_hw *hw, uint32_t * ctrl) 2147 { 2148 /* Raise the clock input to the Management Data Clock (by setting the MDC 2149 * bit), and then delay 2 microseconds. 2150 */ 2151 E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC)); 2152 E1000_WRITE_FLUSH(hw); 2153 udelay(2); 2154 } 2155 2156 /****************************************************************************** 2157 * Lowers the Management Data Clock 2158 * 2159 * hw - Struct containing variables accessed by shared code 2160 * ctrl - Device control register's current value 2161 ******************************************************************************/ 2162 static void 2163 e1000_lower_mdi_clk(struct e1000_hw *hw, uint32_t * ctrl) 2164 { 2165 /* Lower the clock input to the Management Data Clock (by clearing the MDC 2166 * bit), and then delay 2 microseconds. 2167 */ 2168 E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC)); 2169 E1000_WRITE_FLUSH(hw); 2170 udelay(2); 2171 } 2172 2173 /****************************************************************************** 2174 * Shifts data bits out to the PHY 2175 * 2176 * hw - Struct containing variables accessed by shared code 2177 * data - Data to send out to the PHY 2178 * count - Number of bits to shift out 2179 * 2180 * Bits are shifted out in MSB to LSB order. 2181 ******************************************************************************/ 2182 static void 2183 e1000_shift_out_mdi_bits(struct e1000_hw *hw, uint32_t data, uint16_t count) 2184 { 2185 uint32_t ctrl; 2186 uint32_t mask; 2187 2188 /* We need to shift "count" number of bits out to the PHY. So, the value 2189 * in the "data" parameter will be shifted out to the PHY one bit at a 2190 * time. In order to do this, "data" must be broken down into bits. 2191 */ 2192 mask = 0x01; 2193 mask <<= (count - 1); 2194 2195 ctrl = E1000_READ_REG(hw, CTRL); 2196 2197 /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */ 2198 ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR); 2199 2200 while (mask) { 2201 /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and 2202 * then raising and lowering the Management Data Clock. A "0" is 2203 * shifted out to the PHY by setting the MDIO bit to "0" and then 2204 * raising and lowering the clock. 2205 */ 2206 if (data & mask) 2207 ctrl |= E1000_CTRL_MDIO; 2208 else 2209 ctrl &= ~E1000_CTRL_MDIO; 2210 2211 E1000_WRITE_REG(hw, CTRL, ctrl); 2212 E1000_WRITE_FLUSH(hw); 2213 2214 udelay(2); 2215 2216 e1000_raise_mdi_clk(hw, &ctrl); 2217 e1000_lower_mdi_clk(hw, &ctrl); 2218 2219 mask = mask >> 1; 2220 } 2221 } 2222 2223 /****************************************************************************** 2224 * Shifts data bits in from the PHY 2225 * 2226 * hw - Struct containing variables accessed by shared code 2227 * 2228 * Bits are shifted in in MSB to LSB order. 2229 ******************************************************************************/ 2230 static uint16_t 2231 e1000_shift_in_mdi_bits(struct e1000_hw *hw) 2232 { 2233 uint32_t ctrl; 2234 uint16_t data = 0; 2235 uint8_t i; 2236 2237 /* In order to read a register from the PHY, we need to shift in a total 2238 * of 18 bits from the PHY. The first two bit (turnaround) times are used 2239 * to avoid contention on the MDIO pin when a read operation is performed. 2240 * These two bits are ignored by us and thrown away. Bits are "shifted in" 2241 * by raising the input to the Management Data Clock (setting the MDC bit), 2242 * and then reading the value of the MDIO bit. 2243 */ 2244 ctrl = E1000_READ_REG(hw, CTRL); 2245 2246 /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */ 2247 ctrl &= ~E1000_CTRL_MDIO_DIR; 2248 ctrl &= ~E1000_CTRL_MDIO; 2249 2250 E1000_WRITE_REG(hw, CTRL, ctrl); 2251 E1000_WRITE_FLUSH(hw); 2252 2253 /* Raise and Lower the clock before reading in the data. This accounts for 2254 * the turnaround bits. The first clock occurred when we clocked out the 2255 * last bit of the Register Address. 2256 */ 2257 e1000_raise_mdi_clk(hw, &ctrl); 2258 e1000_lower_mdi_clk(hw, &ctrl); 2259 2260 for (data = 0, i = 0; i < 16; i++) { 2261 data = data << 1; 2262 e1000_raise_mdi_clk(hw, &ctrl); 2263 ctrl = E1000_READ_REG(hw, CTRL); 2264 /* Check to see if we shifted in a "1". */ 2265 if (ctrl & E1000_CTRL_MDIO) 2266 data |= 1; 2267 e1000_lower_mdi_clk(hw, &ctrl); 2268 } 2269 2270 e1000_raise_mdi_clk(hw, &ctrl); 2271 e1000_lower_mdi_clk(hw, &ctrl); 2272 2273 return data; 2274 } 2275 2276 /***************************************************************************** 2277 * Reads the value from a PHY register 2278 * 2279 * hw - Struct containing variables accessed by shared code 2280 * reg_addr - address of the PHY register to read 2281 ******************************************************************************/ 2282 static int 2283 e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t * phy_data) 2284 { 2285 uint32_t i; 2286 uint32_t mdic = 0; 2287 const uint32_t phy_addr = 1; 2288 2289 if (reg_addr > MAX_PHY_REG_ADDRESS) { 2290 DEBUGOUT("PHY Address %d is out of range\n", reg_addr); 2291 return -E1000_ERR_PARAM; 2292 } 2293 2294 if (hw->mac_type > e1000_82543) { 2295 /* Set up Op-code, Phy Address, and register address in the MDI 2296 * Control register. The MAC will take care of interfacing with the 2297 * PHY to retrieve the desired data. 2298 */ 2299 mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) | 2300 (phy_addr << E1000_MDIC_PHY_SHIFT) | 2301 (E1000_MDIC_OP_READ)); 2302 2303 E1000_WRITE_REG(hw, MDIC, mdic); 2304 2305 /* Poll the ready bit to see if the MDI read completed */ 2306 for (i = 0; i < 64; i++) { 2307 udelay(10); 2308 mdic = E1000_READ_REG(hw, MDIC); 2309 if (mdic & E1000_MDIC_READY) 2310 break; 2311 } 2312 if (!(mdic & E1000_MDIC_READY)) { 2313 DEBUGOUT("MDI Read did not complete\n"); 2314 return -E1000_ERR_PHY; 2315 } 2316 if (mdic & E1000_MDIC_ERROR) { 2317 DEBUGOUT("MDI Error\n"); 2318 return -E1000_ERR_PHY; 2319 } 2320 *phy_data = (uint16_t) mdic; 2321 } else { 2322 /* We must first send a preamble through the MDIO pin to signal the 2323 * beginning of an MII instruction. This is done by sending 32 2324 * consecutive "1" bits. 2325 */ 2326 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); 2327 2328 /* Now combine the next few fields that are required for a read 2329 * operation. We use this method instead of calling the 2330 * e1000_shift_out_mdi_bits routine five different times. The format of 2331 * a MII read instruction consists of a shift out of 14 bits and is 2332 * defined as follows: 2333 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr> 2334 * followed by a shift in of 18 bits. This first two bits shifted in 2335 * are TurnAround bits used to avoid contention on the MDIO pin when a 2336 * READ operation is performed. These two bits are thrown away 2337 * followed by a shift in of 16 bits which contains the desired data. 2338 */ 2339 mdic = ((reg_addr) | (phy_addr << 5) | 2340 (PHY_OP_READ << 10) | (PHY_SOF << 12)); 2341 2342 e1000_shift_out_mdi_bits(hw, mdic, 14); 2343 2344 /* Now that we've shifted out the read command to the MII, we need to 2345 * "shift in" the 16-bit value (18 total bits) of the requested PHY 2346 * register address. 2347 */ 2348 *phy_data = e1000_shift_in_mdi_bits(hw); 2349 } 2350 return 0; 2351 } 2352 2353 /****************************************************************************** 2354 * Writes a value to a PHY register 2355 * 2356 * hw - Struct containing variables accessed by shared code 2357 * reg_addr - address of the PHY register to write 2358 * data - data to write to the PHY 2359 ******************************************************************************/ 2360 static int 2361 e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t phy_data) 2362 { 2363 uint32_t i; 2364 uint32_t mdic = 0; 2365 const uint32_t phy_addr = 1; 2366 2367 if (reg_addr > MAX_PHY_REG_ADDRESS) { 2368 DEBUGOUT("PHY Address %d is out of range\n", reg_addr); 2369 return -E1000_ERR_PARAM; 2370 } 2371 2372 if (hw->mac_type > e1000_82543) { 2373 /* Set up Op-code, Phy Address, register address, and data intended 2374 * for the PHY register in the MDI Control register. The MAC will take 2375 * care of interfacing with the PHY to send the desired data. 2376 */ 2377 mdic = (((uint32_t) phy_data) | 2378 (reg_addr << E1000_MDIC_REG_SHIFT) | 2379 (phy_addr << E1000_MDIC_PHY_SHIFT) | 2380 (E1000_MDIC_OP_WRITE)); 2381 2382 E1000_WRITE_REG(hw, MDIC, mdic); 2383 2384 /* Poll the ready bit to see if the MDI read completed */ 2385 for (i = 0; i < 64; i++) { 2386 udelay(10); 2387 mdic = E1000_READ_REG(hw, MDIC); 2388 if (mdic & E1000_MDIC_READY) 2389 break; 2390 } 2391 if (!(mdic & E1000_MDIC_READY)) { 2392 DEBUGOUT("MDI Write did not complete\n"); 2393 return -E1000_ERR_PHY; 2394 } 2395 } else { 2396 /* We'll need to use the SW defined pins to shift the write command 2397 * out to the PHY. We first send a preamble to the PHY to signal the 2398 * beginning of the MII instruction. This is done by sending 32 2399 * consecutive "1" bits. 2400 */ 2401 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); 2402 2403 /* Now combine the remaining required fields that will indicate a 2404 * write operation. We use this method instead of calling the 2405 * e1000_shift_out_mdi_bits routine for each field in the command. The 2406 * format of a MII write instruction is as follows: 2407 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>. 2408 */ 2409 mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) | 2410 (PHY_OP_WRITE << 12) | (PHY_SOF << 14)); 2411 mdic <<= 16; 2412 mdic |= (uint32_t) phy_data; 2413 2414 e1000_shift_out_mdi_bits(hw, mdic, 32); 2415 } 2416 return 0; 2417 } 2418 2419 /****************************************************************************** 2420 * Returns the PHY to the power-on reset state 2421 * 2422 * hw - Struct containing variables accessed by shared code 2423 ******************************************************************************/ 2424 static void 2425 e1000_phy_hw_reset(struct e1000_hw *hw) 2426 { 2427 uint32_t ctrl; 2428 uint32_t ctrl_ext; 2429 2430 DEBUGFUNC(); 2431 2432 DEBUGOUT("Resetting Phy...\n"); 2433 2434 if (hw->mac_type > e1000_82543) { 2435 /* Read the device control register and assert the E1000_CTRL_PHY_RST 2436 * bit. Then, take it out of reset. 2437 */ 2438 ctrl = E1000_READ_REG(hw, CTRL); 2439 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST); 2440 E1000_WRITE_FLUSH(hw); 2441 mdelay(10); 2442 E1000_WRITE_REG(hw, CTRL, ctrl); 2443 E1000_WRITE_FLUSH(hw); 2444 } else { 2445 /* Read the Extended Device Control Register, assert the PHY_RESET_DIR 2446 * bit to put the PHY into reset. Then, take it out of reset. 2447 */ 2448 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 2449 ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR; 2450 ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA; 2451 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 2452 E1000_WRITE_FLUSH(hw); 2453 mdelay(10); 2454 ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA; 2455 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 2456 E1000_WRITE_FLUSH(hw); 2457 } 2458 udelay(150); 2459 } 2460 2461 /****************************************************************************** 2462 * Resets the PHY 2463 * 2464 * hw - Struct containing variables accessed by shared code 2465 * 2466 * Sets bit 15 of the MII Control regiser 2467 ******************************************************************************/ 2468 static int 2469 e1000_phy_reset(struct e1000_hw *hw) 2470 { 2471 uint16_t phy_data; 2472 2473 DEBUGFUNC(); 2474 2475 if (e1000_read_phy_reg(hw, PHY_CTRL, &phy_data) < 0) { 2476 DEBUGOUT("PHY Read Error\n"); 2477 return -E1000_ERR_PHY; 2478 } 2479 phy_data |= MII_CR_RESET; 2480 if (e1000_write_phy_reg(hw, PHY_CTRL, phy_data) < 0) { 2481 DEBUGOUT("PHY Write Error\n"); 2482 return -E1000_ERR_PHY; 2483 } 2484 udelay(1); 2485 return 0; 2486 } 2487 2488 /****************************************************************************** 2489 * Probes the expected PHY address for known PHY IDs 2490 * 2491 * hw - Struct containing variables accessed by shared code 2492 ******************************************************************************/ 2493 static int 2494 e1000_detect_gig_phy(struct e1000_hw *hw) 2495 { 2496 uint16_t phy_id_high, phy_id_low; 2497 int match = FALSE; 2498 2499 DEBUGFUNC(); 2500 2501 /* Read the PHY ID Registers to identify which PHY is onboard. */ 2502 if (e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high) < 0) { 2503 DEBUGOUT("PHY Read Error\n"); 2504 return -E1000_ERR_PHY; 2505 } 2506 hw->phy_id = (uint32_t) (phy_id_high << 16); 2507 udelay(2); 2508 if (e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low) < 0) { 2509 DEBUGOUT("PHY Read Error\n"); 2510 return -E1000_ERR_PHY; 2511 } 2512 hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK); 2513 2514 switch (hw->mac_type) { 2515 case e1000_82543: 2516 if (hw->phy_id == M88E1000_E_PHY_ID) 2517 match = TRUE; 2518 break; 2519 case e1000_82544: 2520 if (hw->phy_id == M88E1000_I_PHY_ID) 2521 match = TRUE; 2522 break; 2523 case e1000_82540: 2524 case e1000_82545: 2525 case e1000_82546: 2526 if (hw->phy_id == M88E1011_I_PHY_ID) 2527 match = TRUE; 2528 break; 2529 default: 2530 DEBUGOUT("Invalid MAC type %d\n", hw->mac_type); 2531 return -E1000_ERR_CONFIG; 2532 } 2533 if (match) { 2534 DEBUGOUT("PHY ID 0x%X detected\n", hw->phy_id); 2535 return 0; 2536 } 2537 DEBUGOUT("Invalid PHY ID 0x%X\n", hw->phy_id); 2538 return -E1000_ERR_PHY; 2539 } 2540 2541 /** 2542 * e1000_sw_init - Initialize general software structures (struct e1000_adapter) 2543 * 2544 * e1000_sw_init initializes the Adapter private data structure. 2545 * Fields are initialized based on PCI device information and 2546 * OS network device settings (MTU size). 2547 **/ 2548 2549 static int 2550 e1000_sw_init(struct eth_device *nic, int cardnum) 2551 { 2552 struct e1000_hw *hw = (typeof(hw)) nic->priv; 2553 int result; 2554 2555 /* PCI config space info */ 2556 pci_read_config_word(hw->pdev, PCI_VENDOR_ID, &hw->vendor_id); 2557 pci_read_config_word(hw->pdev, PCI_DEVICE_ID, &hw->device_id); 2558 pci_read_config_word(hw->pdev, PCI_SUBSYSTEM_VENDOR_ID, 2559 &hw->subsystem_vendor_id); 2560 pci_read_config_word(hw->pdev, PCI_SUBSYSTEM_ID, &hw->subsystem_id); 2561 2562 pci_read_config_byte(hw->pdev, PCI_REVISION_ID, &hw->revision_id); 2563 pci_read_config_word(hw->pdev, PCI_COMMAND, &hw->pci_cmd_word); 2564 2565 /* identify the MAC */ 2566 result = e1000_set_mac_type(hw); 2567 if (result) { 2568 E1000_ERR("Unknown MAC Type\n"); 2569 return result; 2570 } 2571 2572 /* lan a vs. lan b settings */ 2573 if (hw->mac_type == e1000_82546) 2574 /*this also works w/ multiple 82546 cards */ 2575 /*but not if they're intermingled /w other e1000s */ 2576 hw->lan_loc = (cardnum % 2) ? e1000_lan_b : e1000_lan_a; 2577 else 2578 hw->lan_loc = e1000_lan_a; 2579 2580 /* flow control settings */ 2581 hw->fc_high_water = E1000_FC_HIGH_THRESH; 2582 hw->fc_low_water = E1000_FC_LOW_THRESH; 2583 hw->fc_pause_time = E1000_FC_PAUSE_TIME; 2584 hw->fc_send_xon = 1; 2585 2586 /* Media type - copper or fiber */ 2587 2588 if (hw->mac_type >= e1000_82543) { 2589 uint32_t status = E1000_READ_REG(hw, STATUS); 2590 2591 if (status & E1000_STATUS_TBIMODE) { 2592 DEBUGOUT("fiber interface\n"); 2593 hw->media_type = e1000_media_type_fiber; 2594 } else { 2595 DEBUGOUT("copper interface\n"); 2596 hw->media_type = e1000_media_type_copper; 2597 } 2598 } else { 2599 hw->media_type = e1000_media_type_fiber; 2600 } 2601 2602 if (hw->mac_type < e1000_82543) 2603 hw->report_tx_early = 0; 2604 else 2605 hw->report_tx_early = 1; 2606 2607 hw->tbi_compatibility_en = TRUE; 2608 #if 0 2609 hw->wait_autoneg_complete = FALSE; 2610 hw->adaptive_ifs = TRUE; 2611 2612 /* Copper options */ 2613 if (hw->media_type == e1000_media_type_copper) { 2614 hw->mdix = AUTO_ALL_MODES; 2615 hw->disable_polarity_correction = FALSE; 2616 } 2617 #endif 2618 return E1000_SUCCESS; 2619 } 2620 2621 void 2622 fill_rx(struct e1000_hw *hw) 2623 { 2624 struct e1000_rx_desc *rd; 2625 2626 rx_last = rx_tail; 2627 rd = rx_base + rx_tail; 2628 rx_tail = (rx_tail + 1) % 8; 2629 memset(rd, 0, 16); 2630 rd->buffer_addr = cpu_to_le64((u32) & packet); 2631 E1000_WRITE_REG(hw, RDT, rx_tail); 2632 } 2633 2634 /** 2635 * e1000_configure_tx - Configure 8254x Transmit Unit after Reset 2636 * @adapter: board private structure 2637 * 2638 * Configure the Tx unit of the MAC after a reset. 2639 **/ 2640 2641 static void 2642 e1000_configure_tx(struct e1000_hw *hw) 2643 { 2644 unsigned long ptr; 2645 unsigned long tctl; 2646 unsigned long tipg; 2647 2648 ptr = (u32) tx_pool; 2649 if (ptr & 0xf) 2650 ptr = (ptr + 0x10) & (~0xf); 2651 2652 tx_base = (typeof(tx_base)) ptr; 2653 2654 E1000_WRITE_REG(hw, TDBAL, (u32) tx_base); 2655 E1000_WRITE_REG(hw, TDBAH, 0); 2656 2657 E1000_WRITE_REG(hw, TDLEN, 128); 2658 2659 /* Setup the HW Tx Head and Tail descriptor pointers */ 2660 E1000_WRITE_REG(hw, TDH, 0); 2661 E1000_WRITE_REG(hw, TDT, 0); 2662 tx_tail = 0; 2663 2664 /* Set the default values for the Tx Inter Packet Gap timer */ 2665 switch (hw->mac_type) { 2666 case e1000_82542_rev2_0: 2667 case e1000_82542_rev2_1: 2668 tipg = DEFAULT_82542_TIPG_IPGT; 2669 tipg |= DEFAULT_82542_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 2670 tipg |= DEFAULT_82542_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 2671 break; 2672 default: 2673 if (hw->media_type == e1000_media_type_fiber) 2674 tipg = DEFAULT_82543_TIPG_IPGT_FIBER; 2675 else 2676 tipg = DEFAULT_82543_TIPG_IPGT_COPPER; 2677 tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 2678 tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 2679 } 2680 E1000_WRITE_REG(hw, TIPG, tipg); 2681 #if 0 2682 /* Set the Tx Interrupt Delay register */ 2683 E1000_WRITE_REG(hw, TIDV, adapter->tx_int_delay); 2684 if (hw->mac_type >= e1000_82540) 2685 E1000_WRITE_REG(hw, TADV, adapter->tx_abs_int_delay); 2686 #endif 2687 /* Program the Transmit Control Register */ 2688 tctl = E1000_READ_REG(hw, TCTL); 2689 tctl &= ~E1000_TCTL_CT; 2690 tctl |= E1000_TCTL_EN | E1000_TCTL_PSP | 2691 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); 2692 E1000_WRITE_REG(hw, TCTL, tctl); 2693 2694 e1000_config_collision_dist(hw); 2695 #if 0 2696 /* Setup Transmit Descriptor Settings for this adapter */ 2697 adapter->txd_cmd = E1000_TXD_CMD_IFCS | E1000_TXD_CMD_IDE; 2698 2699 if (adapter->hw.report_tx_early == 1) 2700 adapter->txd_cmd |= E1000_TXD_CMD_RS; 2701 else 2702 adapter->txd_cmd |= E1000_TXD_CMD_RPS; 2703 #endif 2704 } 2705 2706 /** 2707 * e1000_setup_rctl - configure the receive control register 2708 * @adapter: Board private structure 2709 **/ 2710 static void 2711 e1000_setup_rctl(struct e1000_hw *hw) 2712 { 2713 uint32_t rctl; 2714 2715 rctl = E1000_READ_REG(hw, RCTL); 2716 2717 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 2718 2719 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF; /* | 2720 (hw.mc_filter_type << E1000_RCTL_MO_SHIFT); */ 2721 2722 if (hw->tbi_compatibility_on == 1) 2723 rctl |= E1000_RCTL_SBP; 2724 else 2725 rctl &= ~E1000_RCTL_SBP; 2726 2727 rctl &= ~(E1000_RCTL_SZ_4096); 2728 #if 0 2729 switch (adapter->rx_buffer_len) { 2730 case E1000_RXBUFFER_2048: 2731 default: 2732 #endif 2733 rctl |= E1000_RCTL_SZ_2048; 2734 rctl &= ~(E1000_RCTL_BSEX | E1000_RCTL_LPE); 2735 #if 0 2736 break; 2737 case E1000_RXBUFFER_4096: 2738 rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX | E1000_RCTL_LPE; 2739 break; 2740 case E1000_RXBUFFER_8192: 2741 rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX | E1000_RCTL_LPE; 2742 break; 2743 case E1000_RXBUFFER_16384: 2744 rctl |= E1000_RCTL_SZ_16384 | E1000_RCTL_BSEX | E1000_RCTL_LPE; 2745 break; 2746 } 2747 #endif 2748 E1000_WRITE_REG(hw, RCTL, rctl); 2749 } 2750 2751 /** 2752 * e1000_configure_rx - Configure 8254x Receive Unit after Reset 2753 * @adapter: board private structure 2754 * 2755 * Configure the Rx unit of the MAC after a reset. 2756 **/ 2757 static void 2758 e1000_configure_rx(struct e1000_hw *hw) 2759 { 2760 unsigned long ptr; 2761 unsigned long rctl; 2762 #if 0 2763 unsigned long rxcsum; 2764 #endif 2765 rx_tail = 0; 2766 /* make sure receives are disabled while setting up the descriptors */ 2767 rctl = E1000_READ_REG(hw, RCTL); 2768 E1000_WRITE_REG(hw, RCTL, rctl & ~E1000_RCTL_EN); 2769 #if 0 2770 /* set the Receive Delay Timer Register */ 2771 2772 E1000_WRITE_REG(hw, RDTR, adapter->rx_int_delay); 2773 #endif 2774 if (hw->mac_type >= e1000_82540) { 2775 #if 0 2776 E1000_WRITE_REG(hw, RADV, adapter->rx_abs_int_delay); 2777 #endif 2778 /* Set the interrupt throttling rate. Value is calculated 2779 * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns) */ 2780 #define MAX_INTS_PER_SEC 8000 2781 #define DEFAULT_ITR 1000000000/(MAX_INTS_PER_SEC * 256) 2782 E1000_WRITE_REG(hw, ITR, DEFAULT_ITR); 2783 } 2784 2785 /* Setup the Base and Length of the Rx Descriptor Ring */ 2786 ptr = (u32) rx_pool; 2787 if (ptr & 0xf) 2788 ptr = (ptr + 0x10) & (~0xf); 2789 rx_base = (typeof(rx_base)) ptr; 2790 E1000_WRITE_REG(hw, RDBAL, (u32) rx_base); 2791 E1000_WRITE_REG(hw, RDBAH, 0); 2792 2793 E1000_WRITE_REG(hw, RDLEN, 128); 2794 2795 /* Setup the HW Rx Head and Tail Descriptor Pointers */ 2796 E1000_WRITE_REG(hw, RDH, 0); 2797 E1000_WRITE_REG(hw, RDT, 0); 2798 #if 0 2799 /* Enable 82543 Receive Checksum Offload for TCP and UDP */ 2800 if ((adapter->hw.mac_type >= e1000_82543) && (adapter->rx_csum == TRUE)) { 2801 rxcsum = E1000_READ_REG(hw, RXCSUM); 2802 rxcsum |= E1000_RXCSUM_TUOFL; 2803 E1000_WRITE_REG(hw, RXCSUM, rxcsum); 2804 } 2805 #endif 2806 /* Enable Receives */ 2807 2808 E1000_WRITE_REG(hw, RCTL, rctl); 2809 fill_rx(hw); 2810 } 2811 2812 /************************************************************************** 2813 POLL - Wait for a frame 2814 ***************************************************************************/ 2815 static int 2816 e1000_poll(struct eth_device *nic) 2817 { 2818 struct e1000_hw *hw = nic->priv; 2819 struct e1000_rx_desc *rd; 2820 /* return true if there's an ethernet packet ready to read */ 2821 rd = rx_base + rx_last; 2822 if (!(le32_to_cpu(rd->status)) & E1000_RXD_STAT_DD) 2823 return 0; 2824 /*DEBUGOUT("recv: packet len=%d \n", rd->length); */ 2825 NetReceive((uchar *)packet, le32_to_cpu(rd->length)); 2826 fill_rx(hw); 2827 return 1; 2828 } 2829 2830 /************************************************************************** 2831 TRANSMIT - Transmit a frame 2832 ***************************************************************************/ 2833 static int 2834 e1000_transmit(struct eth_device *nic, volatile void *packet, int length) 2835 { 2836 struct e1000_hw *hw = nic->priv; 2837 struct e1000_tx_desc *txp; 2838 int i = 0; 2839 2840 txp = tx_base + tx_tail; 2841 tx_tail = (tx_tail + 1) % 8; 2842 2843 txp->buffer_addr = cpu_to_le64(virt_to_bus(packet)); 2844 txp->lower.data = cpu_to_le32(E1000_TXD_CMD_RPS | E1000_TXD_CMD_EOP | 2845 E1000_TXD_CMD_IFCS | length); 2846 txp->upper.data = 0; 2847 E1000_WRITE_REG(hw, TDT, tx_tail); 2848 2849 while (!(le32_to_cpu(txp->upper.data) & E1000_TXD_STAT_DD)) { 2850 if (i++ > TOUT_LOOP) { 2851 DEBUGOUT("e1000: tx timeout\n"); 2852 return 0; 2853 } 2854 udelay(10); /* give the nic a chance to write to the register */ 2855 } 2856 return 1; 2857 } 2858 2859 /*reset function*/ 2860 static inline int 2861 e1000_reset(struct eth_device *nic) 2862 { 2863 struct e1000_hw *hw = nic->priv; 2864 2865 e1000_reset_hw(hw); 2866 if (hw->mac_type >= e1000_82544) { 2867 E1000_WRITE_REG(hw, WUC, 0); 2868 } 2869 return e1000_init_hw(nic); 2870 } 2871 2872 /************************************************************************** 2873 DISABLE - Turn off ethernet interface 2874 ***************************************************************************/ 2875 static void 2876 e1000_disable(struct eth_device *nic) 2877 { 2878 struct e1000_hw *hw = nic->priv; 2879 2880 /* Turn off the ethernet interface */ 2881 E1000_WRITE_REG(hw, RCTL, 0); 2882 E1000_WRITE_REG(hw, TCTL, 0); 2883 2884 /* Clear the transmit ring */ 2885 E1000_WRITE_REG(hw, TDH, 0); 2886 E1000_WRITE_REG(hw, TDT, 0); 2887 2888 /* Clear the receive ring */ 2889 E1000_WRITE_REG(hw, RDH, 0); 2890 E1000_WRITE_REG(hw, RDT, 0); 2891 2892 /* put the card in its initial state */ 2893 #if 0 2894 E1000_WRITE_REG(hw, CTRL, E1000_CTRL_RST); 2895 #endif 2896 mdelay(10); 2897 2898 } 2899 2900 /************************************************************************** 2901 INIT - set up ethernet interface(s) 2902 ***************************************************************************/ 2903 static int 2904 e1000_init(struct eth_device *nic, bd_t * bis) 2905 { 2906 struct e1000_hw *hw = nic->priv; 2907 int ret_val = 0; 2908 2909 ret_val = e1000_reset(nic); 2910 if (ret_val < 0) { 2911 if ((ret_val == -E1000_ERR_NOLINK) || 2912 (ret_val == -E1000_ERR_TIMEOUT)) { 2913 E1000_ERR("Valid Link not detected\n"); 2914 } else { 2915 E1000_ERR("Hardware Initialization Failed\n"); 2916 } 2917 return 0; 2918 } 2919 e1000_configure_tx(hw); 2920 e1000_setup_rctl(hw); 2921 e1000_configure_rx(hw); 2922 return 1; 2923 } 2924 2925 /************************************************************************** 2926 PROBE - Look for an adapter, this routine's visible to the outside 2927 You should omit the last argument struct pci_device * for a non-PCI NIC 2928 ***************************************************************************/ 2929 int 2930 e1000_initialize(bd_t * bis) 2931 { 2932 pci_dev_t devno; 2933 int card_number = 0; 2934 struct eth_device *nic = NULL; 2935 struct e1000_hw *hw = NULL; 2936 u32 iobase; 2937 int idx = 0; 2938 u32 PciCommandWord; 2939 2940 while (1) { /* Find PCI device(s) */ 2941 if ((devno = pci_find_devices(supported, idx++)) < 0) { 2942 break; 2943 } 2944 2945 pci_read_config_dword(devno, PCI_BASE_ADDRESS_0, &iobase); 2946 iobase &= ~0xf; /* Mask the bits that say "this is an io addr" */ 2947 DEBUGOUT("e1000#%d: iobase 0x%08x\n", card_number, iobase); 2948 2949 pci_write_config_dword(devno, PCI_COMMAND, 2950 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); 2951 /* Check if I/O accesses and Bus Mastering are enabled. */ 2952 pci_read_config_dword(devno, PCI_COMMAND, &PciCommandWord); 2953 if (!(PciCommandWord & PCI_COMMAND_MEMORY)) { 2954 printf("Error: Can not enable MEM access.\n"); 2955 continue; 2956 } else if (!(PciCommandWord & PCI_COMMAND_MASTER)) { 2957 printf("Error: Can not enable Bus Mastering.\n"); 2958 continue; 2959 } 2960 2961 nic = (struct eth_device *) malloc(sizeof (*nic)); 2962 hw = (struct e1000_hw *) malloc(sizeof (*hw)); 2963 hw->pdev = devno; 2964 nic->priv = hw; 2965 nic->iobase = bus_to_phys(devno, iobase); 2966 2967 sprintf(nic->name, "e1000#%d", card_number); 2968 2969 /* Are these variables needed? */ 2970 #if 0 2971 hw->fc = e1000_fc_none; 2972 hw->original_fc = e1000_fc_none; 2973 #else 2974 hw->fc = e1000_fc_default; 2975 hw->original_fc = e1000_fc_default; 2976 #endif 2977 hw->autoneg_failed = 0; 2978 hw->get_link_status = TRUE; 2979 hw->hw_addr = (typeof(hw->hw_addr)) iobase; 2980 hw->mac_type = e1000_undefined; 2981 2982 /* MAC and Phy settings */ 2983 if (e1000_sw_init(nic, card_number) < 0) { 2984 free(hw); 2985 free(nic); 2986 return 0; 2987 } 2988 #ifndef CONFIG_AP1000 2989 if (e1000_validate_eeprom_checksum(nic) < 0) { 2990 printf("The EEPROM Checksum Is Not Valid\n"); 2991 free(hw); 2992 free(nic); 2993 return 0; 2994 } 2995 #endif 2996 e1000_read_mac_addr(nic); 2997 2998 E1000_WRITE_REG(hw, PBA, E1000_DEFAULT_PBA); 2999 3000 printf("e1000: %02x:%02x:%02x:%02x:%02x:%02x\n", 3001 nic->enetaddr[0], nic->enetaddr[1], nic->enetaddr[2], 3002 nic->enetaddr[3], nic->enetaddr[4], nic->enetaddr[5]); 3003 3004 nic->init = e1000_init; 3005 nic->recv = e1000_poll; 3006 nic->send = e1000_transmit; 3007 nic->halt = e1000_disable; 3008 3009 eth_register(nic); 3010 3011 card_number++; 3012 } 3013 return 1; 3014 } 3015 3016 #endif 3017