1 /************************************************************************** 2 Intel Pro 1000 for ppcboot/das-u-boot 3 Drivers are port from Intel's Linux driver e1000-4.3.15 4 and from Etherboot pro 1000 driver by mrakes at vivato dot net 5 tested on both gig copper and gig fiber boards 6 ***************************************************************************/ 7 /******************************************************************************* 8 9 10 Copyright(c) 1999 - 2002 Intel Corporation. All rights reserved. 11 12 This program is free software; you can redistribute it and/or modify it 13 under the terms of the GNU General Public License as published by the Free 14 Software Foundation; either version 2 of the License, or (at your option) 15 any later version. 16 17 This program is distributed in the hope that it will be useful, but WITHOUT 18 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 19 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 20 more details. 21 22 You should have received a copy of the GNU General Public License along with 23 this program; if not, write to the Free Software Foundation, Inc., 59 24 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 25 26 The full GNU General Public License is included in this distribution in the 27 file called LICENSE. 28 29 Contact Information: 30 Linux NICS <linux.nics@intel.com> 31 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 32 33 *******************************************************************************/ 34 /* 35 * Copyright (C) Archway Digital Solutions. 36 * 37 * written by Chrsitopher Li <cli at arcyway dot com> or <chrisl at gnuchina dot org> 38 * 2/9/2002 39 * 40 * Copyright (C) Linux Networx. 41 * Massive upgrade to work with the new intel gigabit NICs. 42 * <ebiederman at lnxi dot com> 43 */ 44 45 #include "e1000.h" 46 47 #define TOUT_LOOP 100000 48 49 #define virt_to_bus(devno, v) pci_virt_to_mem(devno, (void *) (v)) 50 #define bus_to_phys(devno, a) pci_mem_to_phys(devno, a) 51 #define mdelay(n) udelay((n)*1000) 52 53 #define E1000_DEFAULT_PCI_PBA 0x00000030 54 #define E1000_DEFAULT_PCIE_PBA 0x000a0026 55 56 /* NIC specific static variables go here */ 57 58 static char tx_pool[128 + 16]; 59 static char rx_pool[128 + 16]; 60 static char packet[2096]; 61 62 static struct e1000_tx_desc *tx_base; 63 static struct e1000_rx_desc *rx_base; 64 65 static int tx_tail; 66 static int rx_tail, rx_last; 67 68 static struct pci_device_id supported[] = { 69 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82542}, 70 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82543GC_FIBER}, 71 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82543GC_COPPER}, 72 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544EI_COPPER}, 73 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544EI_FIBER}, 74 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544GC_COPPER}, 75 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544GC_LOM}, 76 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82540EM}, 77 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545EM_COPPER}, 78 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545GM_COPPER}, 79 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_COPPER}, 80 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545EM_FIBER}, 81 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_FIBER}, 82 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546GB_COPPER}, 83 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82540EM_LOM}, 84 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82541ER}, 85 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82541GI_LF}, 86 /* E1000 PCIe card */ 87 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_COPPER}, 88 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_FIBER }, 89 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES }, 90 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_COPPER}, 91 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571PT_QUAD_COPPER}, 92 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_FIBER}, 93 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_COPPER_LOWPROFILE}, 94 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES_DUAL}, 95 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES_QUAD}, 96 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_COPPER}, 97 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_FIBER}, 98 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_SERDES}, 99 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI}, 100 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573E}, 101 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573E_IAMT}, 102 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573L}, 103 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546GB_QUAD_COPPER_KSP3}, 104 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_COPPER_DPT}, 105 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_SERDES_DPT}, 106 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_COPPER_SPT}, 107 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_SERDES_SPT}, 108 {} 109 }; 110 111 /* Function forward declarations */ 112 static int e1000_setup_link(struct eth_device *nic); 113 static int e1000_setup_fiber_link(struct eth_device *nic); 114 static int e1000_setup_copper_link(struct eth_device *nic); 115 static int e1000_phy_setup_autoneg(struct e1000_hw *hw); 116 static void e1000_config_collision_dist(struct e1000_hw *hw); 117 static int e1000_config_mac_to_phy(struct e1000_hw *hw); 118 static int e1000_config_fc_after_link_up(struct e1000_hw *hw); 119 static int e1000_check_for_link(struct eth_device *nic); 120 static int e1000_wait_autoneg(struct e1000_hw *hw); 121 static int e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t * speed, 122 uint16_t * duplex); 123 static int e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, 124 uint16_t * phy_data); 125 static int e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, 126 uint16_t phy_data); 127 static int32_t e1000_phy_hw_reset(struct e1000_hw *hw); 128 static int e1000_phy_reset(struct e1000_hw *hw); 129 static int e1000_detect_gig_phy(struct e1000_hw *hw); 130 static void e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw); 131 static void e1000_set_media_type(struct e1000_hw *hw); 132 133 static int32_t e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask); 134 static int32_t e1000_check_phy_reset_block(struct e1000_hw *hw); 135 #define E1000_WRITE_REG(a, reg, value) (writel((value), ((a)->hw_addr + E1000_##reg))) 136 #define E1000_READ_REG(a, reg) (readl((a)->hw_addr + E1000_##reg)) 137 #define E1000_WRITE_REG_ARRAY(a, reg, offset, value) (\ 138 writel((value), ((a)->hw_addr + E1000_##reg + ((offset) << 2)))) 139 #define E1000_READ_REG_ARRAY(a, reg, offset) ( \ 140 readl((a)->hw_addr + E1000_##reg + ((offset) << 2))) 141 #define E1000_WRITE_FLUSH(a) {uint32_t x; x = E1000_READ_REG(a, STATUS);} 142 143 #ifndef CONFIG_AP1000 /* remove for warnings */ 144 static int32_t e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset, 145 uint16_t words, 146 uint16_t *data); 147 /****************************************************************************** 148 * Raises the EEPROM's clock input. 149 * 150 * hw - Struct containing variables accessed by shared code 151 * eecd - EECD's current value 152 *****************************************************************************/ 153 static void 154 e1000_raise_ee_clk(struct e1000_hw *hw, uint32_t * eecd) 155 { 156 /* Raise the clock input to the EEPROM (by setting the SK bit), and then 157 * wait 50 microseconds. 158 */ 159 *eecd = *eecd | E1000_EECD_SK; 160 E1000_WRITE_REG(hw, EECD, *eecd); 161 E1000_WRITE_FLUSH(hw); 162 udelay(50); 163 } 164 165 /****************************************************************************** 166 * Lowers the EEPROM's clock input. 167 * 168 * hw - Struct containing variables accessed by shared code 169 * eecd - EECD's current value 170 *****************************************************************************/ 171 static void 172 e1000_lower_ee_clk(struct e1000_hw *hw, uint32_t * eecd) 173 { 174 /* Lower the clock input to the EEPROM (by clearing the SK bit), and then 175 * wait 50 microseconds. 176 */ 177 *eecd = *eecd & ~E1000_EECD_SK; 178 E1000_WRITE_REG(hw, EECD, *eecd); 179 E1000_WRITE_FLUSH(hw); 180 udelay(50); 181 } 182 183 /****************************************************************************** 184 * Shift data bits out to the EEPROM. 185 * 186 * hw - Struct containing variables accessed by shared code 187 * data - data to send to the EEPROM 188 * count - number of bits to shift out 189 *****************************************************************************/ 190 static void 191 e1000_shift_out_ee_bits(struct e1000_hw *hw, uint16_t data, uint16_t count) 192 { 193 uint32_t eecd; 194 uint32_t mask; 195 196 /* We need to shift "count" bits out to the EEPROM. So, value in the 197 * "data" parameter will be shifted out to the EEPROM one bit at a time. 198 * In order to do this, "data" must be broken down into bits. 199 */ 200 mask = 0x01 << (count - 1); 201 eecd = E1000_READ_REG(hw, EECD); 202 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI); 203 do { 204 /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1", 205 * and then raising and then lowering the clock (the SK bit controls 206 * the clock input to the EEPROM). A "0" is shifted out to the EEPROM 207 * by setting "DI" to "0" and then raising and then lowering the clock. 208 */ 209 eecd &= ~E1000_EECD_DI; 210 211 if (data & mask) 212 eecd |= E1000_EECD_DI; 213 214 E1000_WRITE_REG(hw, EECD, eecd); 215 E1000_WRITE_FLUSH(hw); 216 217 udelay(50); 218 219 e1000_raise_ee_clk(hw, &eecd); 220 e1000_lower_ee_clk(hw, &eecd); 221 222 mask = mask >> 1; 223 224 } while (mask); 225 226 /* We leave the "DI" bit set to "0" when we leave this routine. */ 227 eecd &= ~E1000_EECD_DI; 228 E1000_WRITE_REG(hw, EECD, eecd); 229 } 230 231 /****************************************************************************** 232 * Shift data bits in from the EEPROM 233 * 234 * hw - Struct containing variables accessed by shared code 235 *****************************************************************************/ 236 static uint16_t 237 e1000_shift_in_ee_bits(struct e1000_hw *hw, uint16_t count) 238 { 239 uint32_t eecd; 240 uint32_t i; 241 uint16_t data; 242 243 /* In order to read a register from the EEPROM, we need to shift 'count' 244 * bits in from the EEPROM. Bits are "shifted in" by raising the clock 245 * input to the EEPROM (setting the SK bit), and then reading the 246 * value of the "DO" bit. During this "shifting in" process the 247 * "DI" bit should always be clear. 248 */ 249 250 eecd = E1000_READ_REG(hw, EECD); 251 252 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI); 253 data = 0; 254 255 for (i = 0; i < count; i++) { 256 data = data << 1; 257 e1000_raise_ee_clk(hw, &eecd); 258 259 eecd = E1000_READ_REG(hw, EECD); 260 261 eecd &= ~(E1000_EECD_DI); 262 if (eecd & E1000_EECD_DO) 263 data |= 1; 264 265 e1000_lower_ee_clk(hw, &eecd); 266 } 267 268 return data; 269 } 270 271 /****************************************************************************** 272 * Returns EEPROM to a "standby" state 273 * 274 * hw - Struct containing variables accessed by shared code 275 *****************************************************************************/ 276 static void 277 e1000_standby_eeprom(struct e1000_hw *hw) 278 { 279 struct e1000_eeprom_info *eeprom = &hw->eeprom; 280 uint32_t eecd; 281 282 eecd = E1000_READ_REG(hw, EECD); 283 284 if (eeprom->type == e1000_eeprom_microwire) { 285 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); 286 E1000_WRITE_REG(hw, EECD, eecd); 287 E1000_WRITE_FLUSH(hw); 288 udelay(eeprom->delay_usec); 289 290 /* Clock high */ 291 eecd |= E1000_EECD_SK; 292 E1000_WRITE_REG(hw, EECD, eecd); 293 E1000_WRITE_FLUSH(hw); 294 udelay(eeprom->delay_usec); 295 296 /* Select EEPROM */ 297 eecd |= E1000_EECD_CS; 298 E1000_WRITE_REG(hw, EECD, eecd); 299 E1000_WRITE_FLUSH(hw); 300 udelay(eeprom->delay_usec); 301 302 /* Clock low */ 303 eecd &= ~E1000_EECD_SK; 304 E1000_WRITE_REG(hw, EECD, eecd); 305 E1000_WRITE_FLUSH(hw); 306 udelay(eeprom->delay_usec); 307 } else if (eeprom->type == e1000_eeprom_spi) { 308 /* Toggle CS to flush commands */ 309 eecd |= E1000_EECD_CS; 310 E1000_WRITE_REG(hw, EECD, eecd); 311 E1000_WRITE_FLUSH(hw); 312 udelay(eeprom->delay_usec); 313 eecd &= ~E1000_EECD_CS; 314 E1000_WRITE_REG(hw, EECD, eecd); 315 E1000_WRITE_FLUSH(hw); 316 udelay(eeprom->delay_usec); 317 } 318 } 319 320 /*************************************************************************** 321 * Description: Determines if the onboard NVM is FLASH or EEPROM. 322 * 323 * hw - Struct containing variables accessed by shared code 324 ****************************************************************************/ 325 static boolean_t e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw) 326 { 327 uint32_t eecd = 0; 328 329 DEBUGFUNC(); 330 331 if (hw->mac_type == e1000_ich8lan) 332 return FALSE; 333 334 if (hw->mac_type == e1000_82573) { 335 eecd = E1000_READ_REG(hw, EECD); 336 337 /* Isolate bits 15 & 16 */ 338 eecd = ((eecd >> 15) & 0x03); 339 340 /* If both bits are set, device is Flash type */ 341 if (eecd == 0x03) 342 return FALSE; 343 } 344 return TRUE; 345 } 346 347 /****************************************************************************** 348 * Prepares EEPROM for access 349 * 350 * hw - Struct containing variables accessed by shared code 351 * 352 * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This 353 * function should be called before issuing a command to the EEPROM. 354 *****************************************************************************/ 355 static int32_t 356 e1000_acquire_eeprom(struct e1000_hw *hw) 357 { 358 struct e1000_eeprom_info *eeprom = &hw->eeprom; 359 uint32_t eecd, i = 0; 360 361 DEBUGFUNC(); 362 363 if (e1000_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM)) 364 return -E1000_ERR_SWFW_SYNC; 365 eecd = E1000_READ_REG(hw, EECD); 366 367 if (hw->mac_type != e1000_82573) { 368 /* Request EEPROM Access */ 369 if (hw->mac_type > e1000_82544) { 370 eecd |= E1000_EECD_REQ; 371 E1000_WRITE_REG(hw, EECD, eecd); 372 eecd = E1000_READ_REG(hw, EECD); 373 while ((!(eecd & E1000_EECD_GNT)) && 374 (i < E1000_EEPROM_GRANT_ATTEMPTS)) { 375 i++; 376 udelay(5); 377 eecd = E1000_READ_REG(hw, EECD); 378 } 379 if (!(eecd & E1000_EECD_GNT)) { 380 eecd &= ~E1000_EECD_REQ; 381 E1000_WRITE_REG(hw, EECD, eecd); 382 DEBUGOUT("Could not acquire EEPROM grant\n"); 383 return -E1000_ERR_EEPROM; 384 } 385 } 386 } 387 388 /* Setup EEPROM for Read/Write */ 389 390 if (eeprom->type == e1000_eeprom_microwire) { 391 /* Clear SK and DI */ 392 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK); 393 E1000_WRITE_REG(hw, EECD, eecd); 394 395 /* Set CS */ 396 eecd |= E1000_EECD_CS; 397 E1000_WRITE_REG(hw, EECD, eecd); 398 } else if (eeprom->type == e1000_eeprom_spi) { 399 /* Clear SK and CS */ 400 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); 401 E1000_WRITE_REG(hw, EECD, eecd); 402 udelay(1); 403 } 404 405 return E1000_SUCCESS; 406 } 407 408 /****************************************************************************** 409 * Sets up eeprom variables in the hw struct. Must be called after mac_type 410 * is configured. Additionally, if this is ICH8, the flash controller GbE 411 * registers must be mapped, or this will crash. 412 * 413 * hw - Struct containing variables accessed by shared code 414 *****************************************************************************/ 415 static int32_t e1000_init_eeprom_params(struct e1000_hw *hw) 416 { 417 struct e1000_eeprom_info *eeprom = &hw->eeprom; 418 uint32_t eecd = E1000_READ_REG(hw, EECD); 419 int32_t ret_val = E1000_SUCCESS; 420 uint16_t eeprom_size; 421 422 DEBUGFUNC(); 423 424 switch (hw->mac_type) { 425 case e1000_82542_rev2_0: 426 case e1000_82542_rev2_1: 427 case e1000_82543: 428 case e1000_82544: 429 eeprom->type = e1000_eeprom_microwire; 430 eeprom->word_size = 64; 431 eeprom->opcode_bits = 3; 432 eeprom->address_bits = 6; 433 eeprom->delay_usec = 50; 434 eeprom->use_eerd = FALSE; 435 eeprom->use_eewr = FALSE; 436 break; 437 case e1000_82540: 438 case e1000_82545: 439 case e1000_82545_rev_3: 440 case e1000_82546: 441 case e1000_82546_rev_3: 442 eeprom->type = e1000_eeprom_microwire; 443 eeprom->opcode_bits = 3; 444 eeprom->delay_usec = 50; 445 if (eecd & E1000_EECD_SIZE) { 446 eeprom->word_size = 256; 447 eeprom->address_bits = 8; 448 } else { 449 eeprom->word_size = 64; 450 eeprom->address_bits = 6; 451 } 452 eeprom->use_eerd = FALSE; 453 eeprom->use_eewr = FALSE; 454 break; 455 case e1000_82541: 456 case e1000_82541_rev_2: 457 case e1000_82547: 458 case e1000_82547_rev_2: 459 if (eecd & E1000_EECD_TYPE) { 460 eeprom->type = e1000_eeprom_spi; 461 eeprom->opcode_bits = 8; 462 eeprom->delay_usec = 1; 463 if (eecd & E1000_EECD_ADDR_BITS) { 464 eeprom->page_size = 32; 465 eeprom->address_bits = 16; 466 } else { 467 eeprom->page_size = 8; 468 eeprom->address_bits = 8; 469 } 470 } else { 471 eeprom->type = e1000_eeprom_microwire; 472 eeprom->opcode_bits = 3; 473 eeprom->delay_usec = 50; 474 if (eecd & E1000_EECD_ADDR_BITS) { 475 eeprom->word_size = 256; 476 eeprom->address_bits = 8; 477 } else { 478 eeprom->word_size = 64; 479 eeprom->address_bits = 6; 480 } 481 } 482 eeprom->use_eerd = FALSE; 483 eeprom->use_eewr = FALSE; 484 break; 485 case e1000_82571: 486 case e1000_82572: 487 eeprom->type = e1000_eeprom_spi; 488 eeprom->opcode_bits = 8; 489 eeprom->delay_usec = 1; 490 if (eecd & E1000_EECD_ADDR_BITS) { 491 eeprom->page_size = 32; 492 eeprom->address_bits = 16; 493 } else { 494 eeprom->page_size = 8; 495 eeprom->address_bits = 8; 496 } 497 eeprom->use_eerd = FALSE; 498 eeprom->use_eewr = FALSE; 499 break; 500 case e1000_82573: 501 eeprom->type = e1000_eeprom_spi; 502 eeprom->opcode_bits = 8; 503 eeprom->delay_usec = 1; 504 if (eecd & E1000_EECD_ADDR_BITS) { 505 eeprom->page_size = 32; 506 eeprom->address_bits = 16; 507 } else { 508 eeprom->page_size = 8; 509 eeprom->address_bits = 8; 510 } 511 eeprom->use_eerd = TRUE; 512 eeprom->use_eewr = TRUE; 513 if (e1000_is_onboard_nvm_eeprom(hw) == FALSE) { 514 eeprom->type = e1000_eeprom_flash; 515 eeprom->word_size = 2048; 516 517 /* Ensure that the Autonomous FLASH update bit is cleared due to 518 * Flash update issue on parts which use a FLASH for NVM. */ 519 eecd &= ~E1000_EECD_AUPDEN; 520 E1000_WRITE_REG(hw, EECD, eecd); 521 } 522 break; 523 case e1000_80003es2lan: 524 eeprom->type = e1000_eeprom_spi; 525 eeprom->opcode_bits = 8; 526 eeprom->delay_usec = 1; 527 if (eecd & E1000_EECD_ADDR_BITS) { 528 eeprom->page_size = 32; 529 eeprom->address_bits = 16; 530 } else { 531 eeprom->page_size = 8; 532 eeprom->address_bits = 8; 533 } 534 eeprom->use_eerd = TRUE; 535 eeprom->use_eewr = FALSE; 536 break; 537 538 /* ich8lan does not support currently. if needed, please 539 * add corresponding code and functions. 540 */ 541 #if 0 542 case e1000_ich8lan: 543 { 544 int32_t i = 0; 545 546 eeprom->type = e1000_eeprom_ich8; 547 eeprom->use_eerd = FALSE; 548 eeprom->use_eewr = FALSE; 549 eeprom->word_size = E1000_SHADOW_RAM_WORDS; 550 uint32_t flash_size = E1000_READ_ICH_FLASH_REG(hw, 551 ICH_FLASH_GFPREG); 552 /* Zero the shadow RAM structure. But don't load it from NVM 553 * so as to save time for driver init */ 554 if (hw->eeprom_shadow_ram != NULL) { 555 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) { 556 hw->eeprom_shadow_ram[i].modified = FALSE; 557 hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF; 558 } 559 } 560 561 hw->flash_base_addr = (flash_size & ICH_GFPREG_BASE_MASK) * 562 ICH_FLASH_SECTOR_SIZE; 563 564 hw->flash_bank_size = ((flash_size >> 16) 565 & ICH_GFPREG_BASE_MASK) + 1; 566 hw->flash_bank_size -= (flash_size & ICH_GFPREG_BASE_MASK); 567 568 hw->flash_bank_size *= ICH_FLASH_SECTOR_SIZE; 569 570 hw->flash_bank_size /= 2 * sizeof(uint16_t); 571 break; 572 } 573 #endif 574 default: 575 break; 576 } 577 578 if (eeprom->type == e1000_eeprom_spi) { 579 /* eeprom_size will be an enum [0..8] that maps 580 * to eeprom sizes 128B to 581 * 32KB (incremented by powers of 2). 582 */ 583 if (hw->mac_type <= e1000_82547_rev_2) { 584 /* Set to default value for initial eeprom read. */ 585 eeprom->word_size = 64; 586 ret_val = e1000_read_eeprom(hw, EEPROM_CFG, 1, 587 &eeprom_size); 588 if (ret_val) 589 return ret_val; 590 eeprom_size = (eeprom_size & EEPROM_SIZE_MASK) 591 >> EEPROM_SIZE_SHIFT; 592 /* 256B eeprom size was not supported in earlier 593 * hardware, so we bump eeprom_size up one to 594 * ensure that "1" (which maps to 256B) is never 595 * the result used in the shifting logic below. */ 596 if (eeprom_size) 597 eeprom_size++; 598 } else { 599 eeprom_size = (uint16_t)((eecd & 600 E1000_EECD_SIZE_EX_MASK) >> 601 E1000_EECD_SIZE_EX_SHIFT); 602 } 603 604 eeprom->word_size = 1 << (eeprom_size + EEPROM_WORD_SIZE_SHIFT); 605 } 606 return ret_val; 607 } 608 609 /****************************************************************************** 610 * Polls the status bit (bit 1) of the EERD to determine when the read is done. 611 * 612 * hw - Struct containing variables accessed by shared code 613 *****************************************************************************/ 614 static int32_t 615 e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd) 616 { 617 uint32_t attempts = 100000; 618 uint32_t i, reg = 0; 619 int32_t done = E1000_ERR_EEPROM; 620 621 for (i = 0; i < attempts; i++) { 622 if (eerd == E1000_EEPROM_POLL_READ) 623 reg = E1000_READ_REG(hw, EERD); 624 else 625 reg = E1000_READ_REG(hw, EEWR); 626 627 if (reg & E1000_EEPROM_RW_REG_DONE) { 628 done = E1000_SUCCESS; 629 break; 630 } 631 udelay(5); 632 } 633 634 return done; 635 } 636 637 /****************************************************************************** 638 * Reads a 16 bit word from the EEPROM using the EERD register. 639 * 640 * hw - Struct containing variables accessed by shared code 641 * offset - offset of word in the EEPROM to read 642 * data - word read from the EEPROM 643 * words - number of words to read 644 *****************************************************************************/ 645 static int32_t 646 e1000_read_eeprom_eerd(struct e1000_hw *hw, 647 uint16_t offset, 648 uint16_t words, 649 uint16_t *data) 650 { 651 uint32_t i, eerd = 0; 652 int32_t error = 0; 653 654 for (i = 0; i < words; i++) { 655 eerd = ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) + 656 E1000_EEPROM_RW_REG_START; 657 658 E1000_WRITE_REG(hw, EERD, eerd); 659 error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_READ); 660 661 if (error) 662 break; 663 data[i] = (E1000_READ_REG(hw, EERD) >> 664 E1000_EEPROM_RW_REG_DATA); 665 666 } 667 668 return error; 669 } 670 671 static void 672 e1000_release_eeprom(struct e1000_hw *hw) 673 { 674 uint32_t eecd; 675 676 DEBUGFUNC(); 677 678 eecd = E1000_READ_REG(hw, EECD); 679 680 if (hw->eeprom.type == e1000_eeprom_spi) { 681 eecd |= E1000_EECD_CS; /* Pull CS high */ 682 eecd &= ~E1000_EECD_SK; /* Lower SCK */ 683 684 E1000_WRITE_REG(hw, EECD, eecd); 685 686 udelay(hw->eeprom.delay_usec); 687 } else if (hw->eeprom.type == e1000_eeprom_microwire) { 688 /* cleanup eeprom */ 689 690 /* CS on Microwire is active-high */ 691 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI); 692 693 E1000_WRITE_REG(hw, EECD, eecd); 694 695 /* Rising edge of clock */ 696 eecd |= E1000_EECD_SK; 697 E1000_WRITE_REG(hw, EECD, eecd); 698 E1000_WRITE_FLUSH(hw); 699 udelay(hw->eeprom.delay_usec); 700 701 /* Falling edge of clock */ 702 eecd &= ~E1000_EECD_SK; 703 E1000_WRITE_REG(hw, EECD, eecd); 704 E1000_WRITE_FLUSH(hw); 705 udelay(hw->eeprom.delay_usec); 706 } 707 708 /* Stop requesting EEPROM access */ 709 if (hw->mac_type > e1000_82544) { 710 eecd &= ~E1000_EECD_REQ; 711 E1000_WRITE_REG(hw, EECD, eecd); 712 } 713 } 714 /****************************************************************************** 715 * Reads a 16 bit word from the EEPROM. 716 * 717 * hw - Struct containing variables accessed by shared code 718 *****************************************************************************/ 719 static int32_t 720 e1000_spi_eeprom_ready(struct e1000_hw *hw) 721 { 722 uint16_t retry_count = 0; 723 uint8_t spi_stat_reg; 724 725 DEBUGFUNC(); 726 727 /* Read "Status Register" repeatedly until the LSB is cleared. The 728 * EEPROM will signal that the command has been completed by clearing 729 * bit 0 of the internal status register. If it's not cleared within 730 * 5 milliseconds, then error out. 731 */ 732 retry_count = 0; 733 do { 734 e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI, 735 hw->eeprom.opcode_bits); 736 spi_stat_reg = (uint8_t)e1000_shift_in_ee_bits(hw, 8); 737 if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI)) 738 break; 739 740 udelay(5); 741 retry_count += 5; 742 743 e1000_standby_eeprom(hw); 744 } while (retry_count < EEPROM_MAX_RETRY_SPI); 745 746 /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and 747 * only 0-5mSec on 5V devices) 748 */ 749 if (retry_count >= EEPROM_MAX_RETRY_SPI) { 750 DEBUGOUT("SPI EEPROM Status error\n"); 751 return -E1000_ERR_EEPROM; 752 } 753 754 return E1000_SUCCESS; 755 } 756 757 /****************************************************************************** 758 * Reads a 16 bit word from the EEPROM. 759 * 760 * hw - Struct containing variables accessed by shared code 761 * offset - offset of word in the EEPROM to read 762 * data - word read from the EEPROM 763 *****************************************************************************/ 764 static int32_t 765 e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset, 766 uint16_t words, uint16_t *data) 767 { 768 struct e1000_eeprom_info *eeprom = &hw->eeprom; 769 uint32_t i = 0; 770 771 DEBUGFUNC(); 772 773 /* If eeprom is not yet detected, do so now */ 774 if (eeprom->word_size == 0) 775 e1000_init_eeprom_params(hw); 776 777 /* A check for invalid values: offset too large, too many words, 778 * and not enough words. 779 */ 780 if ((offset >= eeprom->word_size) || 781 (words > eeprom->word_size - offset) || 782 (words == 0)) { 783 DEBUGOUT("\"words\" parameter out of bounds." 784 "Words = %d, size = %d\n", offset, eeprom->word_size); 785 return -E1000_ERR_EEPROM; 786 } 787 788 /* EEPROM's that don't use EERD to read require us to bit-bang the SPI 789 * directly. In this case, we need to acquire the EEPROM so that 790 * FW or other port software does not interrupt. 791 */ 792 if (e1000_is_onboard_nvm_eeprom(hw) == TRUE && 793 hw->eeprom.use_eerd == FALSE) { 794 795 /* Prepare the EEPROM for bit-bang reading */ 796 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS) 797 return -E1000_ERR_EEPROM; 798 } 799 800 /* Eerd register EEPROM access requires no eeprom aquire/release */ 801 if (eeprom->use_eerd == TRUE) 802 return e1000_read_eeprom_eerd(hw, offset, words, data); 803 804 /* ich8lan does not support currently. if needed, please 805 * add corresponding code and functions. 806 */ 807 #if 0 808 /* ICH EEPROM access is done via the ICH flash controller */ 809 if (eeprom->type == e1000_eeprom_ich8) 810 return e1000_read_eeprom_ich8(hw, offset, words, data); 811 #endif 812 /* Set up the SPI or Microwire EEPROM for bit-bang reading. We have 813 * acquired the EEPROM at this point, so any returns should relase it */ 814 if (eeprom->type == e1000_eeprom_spi) { 815 uint16_t word_in; 816 uint8_t read_opcode = EEPROM_READ_OPCODE_SPI; 817 818 if (e1000_spi_eeprom_ready(hw)) { 819 e1000_release_eeprom(hw); 820 return -E1000_ERR_EEPROM; 821 } 822 823 e1000_standby_eeprom(hw); 824 825 /* Some SPI eeproms use the 8th address bit embedded in 826 * the opcode */ 827 if ((eeprom->address_bits == 8) && (offset >= 128)) 828 read_opcode |= EEPROM_A8_OPCODE_SPI; 829 830 /* Send the READ command (opcode + addr) */ 831 e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits); 832 e1000_shift_out_ee_bits(hw, (uint16_t)(offset*2), 833 eeprom->address_bits); 834 835 /* Read the data. The address of the eeprom internally 836 * increments with each byte (spi) being read, saving on the 837 * overhead of eeprom setup and tear-down. The address 838 * counter will roll over if reading beyond the size of 839 * the eeprom, thus allowing the entire memory to be read 840 * starting from any offset. */ 841 for (i = 0; i < words; i++) { 842 word_in = e1000_shift_in_ee_bits(hw, 16); 843 data[i] = (word_in >> 8) | (word_in << 8); 844 } 845 } else if (eeprom->type == e1000_eeprom_microwire) { 846 for (i = 0; i < words; i++) { 847 /* Send the READ command (opcode + addr) */ 848 e1000_shift_out_ee_bits(hw, 849 EEPROM_READ_OPCODE_MICROWIRE, 850 eeprom->opcode_bits); 851 e1000_shift_out_ee_bits(hw, (uint16_t)(offset + i), 852 eeprom->address_bits); 853 854 /* Read the data. For microwire, each word requires 855 * the overhead of eeprom setup and tear-down. */ 856 data[i] = e1000_shift_in_ee_bits(hw, 16); 857 e1000_standby_eeprom(hw); 858 } 859 } 860 861 /* End this read operation */ 862 e1000_release_eeprom(hw); 863 864 return E1000_SUCCESS; 865 } 866 867 /****************************************************************************** 868 * Verifies that the EEPROM has a valid checksum 869 * 870 * hw - Struct containing variables accessed by shared code 871 * 872 * Reads the first 64 16 bit words of the EEPROM and sums the values read. 873 * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is 874 * valid. 875 *****************************************************************************/ 876 static int 877 e1000_validate_eeprom_checksum(struct eth_device *nic) 878 { 879 struct e1000_hw *hw = nic->priv; 880 uint16_t checksum = 0; 881 uint16_t i, eeprom_data; 882 883 DEBUGFUNC(); 884 885 for (i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) { 886 if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) { 887 DEBUGOUT("EEPROM Read Error\n"); 888 return -E1000_ERR_EEPROM; 889 } 890 checksum += eeprom_data; 891 } 892 893 if (checksum == (uint16_t) EEPROM_SUM) { 894 return 0; 895 } else { 896 DEBUGOUT("EEPROM Checksum Invalid\n"); 897 return -E1000_ERR_EEPROM; 898 } 899 } 900 901 /***************************************************************************** 902 * Set PHY to class A mode 903 * Assumes the following operations will follow to enable the new class mode. 904 * 1. Do a PHY soft reset 905 * 2. Restart auto-negotiation or force link. 906 * 907 * hw - Struct containing variables accessed by shared code 908 ****************************************************************************/ 909 static int32_t 910 e1000_set_phy_mode(struct e1000_hw *hw) 911 { 912 int32_t ret_val; 913 uint16_t eeprom_data; 914 915 DEBUGFUNC(); 916 917 if ((hw->mac_type == e1000_82545_rev_3) && 918 (hw->media_type == e1000_media_type_copper)) { 919 ret_val = e1000_read_eeprom(hw, EEPROM_PHY_CLASS_WORD, 920 1, &eeprom_data); 921 if (ret_val) 922 return ret_val; 923 924 if ((eeprom_data != EEPROM_RESERVED_WORD) && 925 (eeprom_data & EEPROM_PHY_CLASS_A)) { 926 ret_val = e1000_write_phy_reg(hw, 927 M88E1000_PHY_PAGE_SELECT, 0x000B); 928 if (ret_val) 929 return ret_val; 930 ret_val = e1000_write_phy_reg(hw, 931 M88E1000_PHY_GEN_CONTROL, 0x8104); 932 if (ret_val) 933 return ret_val; 934 935 hw->phy_reset_disable = FALSE; 936 } 937 } 938 939 return E1000_SUCCESS; 940 } 941 #endif /* #ifndef CONFIG_AP1000 */ 942 943 /*************************************************************************** 944 * 945 * Obtaining software semaphore bit (SMBI) before resetting PHY. 946 * 947 * hw: Struct containing variables accessed by shared code 948 * 949 * returns: - E1000_ERR_RESET if fail to obtain semaphore. 950 * E1000_SUCCESS at any other case. 951 * 952 ***************************************************************************/ 953 static int32_t 954 e1000_get_software_semaphore(struct e1000_hw *hw) 955 { 956 int32_t timeout = hw->eeprom.word_size + 1; 957 uint32_t swsm; 958 959 DEBUGFUNC(); 960 961 if (hw->mac_type != e1000_80003es2lan) 962 return E1000_SUCCESS; 963 964 while (timeout) { 965 swsm = E1000_READ_REG(hw, SWSM); 966 /* If SMBI bit cleared, it is now set and we hold 967 * the semaphore */ 968 if (!(swsm & E1000_SWSM_SMBI)) 969 break; 970 mdelay(1); 971 timeout--; 972 } 973 974 if (!timeout) { 975 DEBUGOUT("Driver can't access device - SMBI bit is set.\n"); 976 return -E1000_ERR_RESET; 977 } 978 979 return E1000_SUCCESS; 980 } 981 982 /*************************************************************************** 983 * This function clears HW semaphore bits. 984 * 985 * hw: Struct containing variables accessed by shared code 986 * 987 * returns: - None. 988 * 989 ***************************************************************************/ 990 static void 991 e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw) 992 { 993 uint32_t swsm; 994 995 DEBUGFUNC(); 996 997 if (!hw->eeprom_semaphore_present) 998 return; 999 1000 swsm = E1000_READ_REG(hw, SWSM); 1001 if (hw->mac_type == e1000_80003es2lan) { 1002 /* Release both semaphores. */ 1003 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI); 1004 } else 1005 swsm &= ~(E1000_SWSM_SWESMBI); 1006 E1000_WRITE_REG(hw, SWSM, swsm); 1007 } 1008 1009 /*************************************************************************** 1010 * 1011 * Using the combination of SMBI and SWESMBI semaphore bits when resetting 1012 * adapter or Eeprom access. 1013 * 1014 * hw: Struct containing variables accessed by shared code 1015 * 1016 * returns: - E1000_ERR_EEPROM if fail to access EEPROM. 1017 * E1000_SUCCESS at any other case. 1018 * 1019 ***************************************************************************/ 1020 static int32_t 1021 e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw) 1022 { 1023 int32_t timeout; 1024 uint32_t swsm; 1025 1026 DEBUGFUNC(); 1027 1028 if (!hw->eeprom_semaphore_present) 1029 return E1000_SUCCESS; 1030 1031 if (hw->mac_type == e1000_80003es2lan) { 1032 /* Get the SW semaphore. */ 1033 if (e1000_get_software_semaphore(hw) != E1000_SUCCESS) 1034 return -E1000_ERR_EEPROM; 1035 } 1036 1037 /* Get the FW semaphore. */ 1038 timeout = hw->eeprom.word_size + 1; 1039 while (timeout) { 1040 swsm = E1000_READ_REG(hw, SWSM); 1041 swsm |= E1000_SWSM_SWESMBI; 1042 E1000_WRITE_REG(hw, SWSM, swsm); 1043 /* if we managed to set the bit we got the semaphore. */ 1044 swsm = E1000_READ_REG(hw, SWSM); 1045 if (swsm & E1000_SWSM_SWESMBI) 1046 break; 1047 1048 udelay(50); 1049 timeout--; 1050 } 1051 1052 if (!timeout) { 1053 /* Release semaphores */ 1054 e1000_put_hw_eeprom_semaphore(hw); 1055 DEBUGOUT("Driver can't access the Eeprom - " 1056 "SWESMBI bit is set.\n"); 1057 return -E1000_ERR_EEPROM; 1058 } 1059 1060 return E1000_SUCCESS; 1061 } 1062 1063 static int32_t 1064 e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask) 1065 { 1066 uint32_t swfw_sync = 0; 1067 uint32_t swmask = mask; 1068 uint32_t fwmask = mask << 16; 1069 int32_t timeout = 200; 1070 1071 DEBUGFUNC(); 1072 while (timeout) { 1073 if (e1000_get_hw_eeprom_semaphore(hw)) 1074 return -E1000_ERR_SWFW_SYNC; 1075 1076 swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC); 1077 if (!(swfw_sync & (fwmask | swmask))) 1078 break; 1079 1080 /* firmware currently using resource (fwmask) */ 1081 /* or other software thread currently using resource (swmask) */ 1082 e1000_put_hw_eeprom_semaphore(hw); 1083 mdelay(5); 1084 timeout--; 1085 } 1086 1087 if (!timeout) { 1088 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n"); 1089 return -E1000_ERR_SWFW_SYNC; 1090 } 1091 1092 swfw_sync |= swmask; 1093 E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync); 1094 1095 e1000_put_hw_eeprom_semaphore(hw); 1096 return E1000_SUCCESS; 1097 } 1098 1099 /****************************************************************************** 1100 * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the 1101 * second function of dual function devices 1102 * 1103 * nic - Struct containing variables accessed by shared code 1104 *****************************************************************************/ 1105 static int 1106 e1000_read_mac_addr(struct eth_device *nic) 1107 { 1108 #ifndef CONFIG_AP1000 1109 struct e1000_hw *hw = nic->priv; 1110 uint16_t offset; 1111 uint16_t eeprom_data; 1112 int i; 1113 1114 DEBUGFUNC(); 1115 1116 for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) { 1117 offset = i >> 1; 1118 if (e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) { 1119 DEBUGOUT("EEPROM Read Error\n"); 1120 return -E1000_ERR_EEPROM; 1121 } 1122 nic->enetaddr[i] = eeprom_data & 0xff; 1123 nic->enetaddr[i + 1] = (eeprom_data >> 8) & 0xff; 1124 } 1125 if ((hw->mac_type == e1000_82546) && 1126 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) { 1127 /* Invert the last bit if this is the second device */ 1128 nic->enetaddr[5] += 1; 1129 } 1130 #ifdef CONFIG_E1000_FALLBACK_MAC 1131 if ( *(u32*)(nic->enetaddr) == 0 || *(u32*)(nic->enetaddr) == ~0 ) { 1132 unsigned char fb_mac[NODE_ADDRESS_SIZE] = CONFIG_E1000_FALLBACK_MAC; 1133 1134 memcpy (nic->enetaddr, fb_mac, NODE_ADDRESS_SIZE); 1135 } 1136 #endif 1137 #else 1138 /* 1139 * The AP1000's e1000 has no eeprom; the MAC address is stored in the 1140 * environment variables. Currently this does not support the addition 1141 * of a PMC e1000 card, which is certainly a possibility, so this should 1142 * be updated to properly use the env variable only for the onboard e1000 1143 */ 1144 1145 int ii; 1146 char *s, *e; 1147 1148 DEBUGFUNC(); 1149 1150 s = getenv ("ethaddr"); 1151 if (s == NULL) { 1152 return -E1000_ERR_EEPROM; 1153 } else { 1154 for(ii = 0; ii < 6; ii++) { 1155 nic->enetaddr[ii] = s ? simple_strtoul (s, &e, 16) : 0; 1156 if (s){ 1157 s = (*e) ? e + 1 : e; 1158 } 1159 } 1160 } 1161 #endif 1162 return 0; 1163 } 1164 1165 /****************************************************************************** 1166 * Initializes receive address filters. 1167 * 1168 * hw - Struct containing variables accessed by shared code 1169 * 1170 * Places the MAC address in receive address register 0 and clears the rest 1171 * of the receive addresss registers. Clears the multicast table. Assumes 1172 * the receiver is in reset when the routine is called. 1173 *****************************************************************************/ 1174 static void 1175 e1000_init_rx_addrs(struct eth_device *nic) 1176 { 1177 struct e1000_hw *hw = nic->priv; 1178 uint32_t i; 1179 uint32_t addr_low; 1180 uint32_t addr_high; 1181 1182 DEBUGFUNC(); 1183 1184 /* Setup the receive address. */ 1185 DEBUGOUT("Programming MAC Address into RAR[0]\n"); 1186 addr_low = (nic->enetaddr[0] | 1187 (nic->enetaddr[1] << 8) | 1188 (nic->enetaddr[2] << 16) | (nic->enetaddr[3] << 24)); 1189 1190 addr_high = (nic->enetaddr[4] | (nic->enetaddr[5] << 8) | E1000_RAH_AV); 1191 1192 E1000_WRITE_REG_ARRAY(hw, RA, 0, addr_low); 1193 E1000_WRITE_REG_ARRAY(hw, RA, 1, addr_high); 1194 1195 /* Zero out the other 15 receive addresses. */ 1196 DEBUGOUT("Clearing RAR[1-15]\n"); 1197 for (i = 1; i < E1000_RAR_ENTRIES; i++) { 1198 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0); 1199 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0); 1200 } 1201 } 1202 1203 /****************************************************************************** 1204 * Clears the VLAN filer table 1205 * 1206 * hw - Struct containing variables accessed by shared code 1207 *****************************************************************************/ 1208 static void 1209 e1000_clear_vfta(struct e1000_hw *hw) 1210 { 1211 uint32_t offset; 1212 1213 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) 1214 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, 0); 1215 } 1216 1217 /****************************************************************************** 1218 * Set the mac type member in the hw struct. 1219 * 1220 * hw - Struct containing variables accessed by shared code 1221 *****************************************************************************/ 1222 int32_t 1223 e1000_set_mac_type(struct e1000_hw *hw) 1224 { 1225 DEBUGFUNC(); 1226 1227 switch (hw->device_id) { 1228 case E1000_DEV_ID_82542: 1229 switch (hw->revision_id) { 1230 case E1000_82542_2_0_REV_ID: 1231 hw->mac_type = e1000_82542_rev2_0; 1232 break; 1233 case E1000_82542_2_1_REV_ID: 1234 hw->mac_type = e1000_82542_rev2_1; 1235 break; 1236 default: 1237 /* Invalid 82542 revision ID */ 1238 return -E1000_ERR_MAC_TYPE; 1239 } 1240 break; 1241 case E1000_DEV_ID_82543GC_FIBER: 1242 case E1000_DEV_ID_82543GC_COPPER: 1243 hw->mac_type = e1000_82543; 1244 break; 1245 case E1000_DEV_ID_82544EI_COPPER: 1246 case E1000_DEV_ID_82544EI_FIBER: 1247 case E1000_DEV_ID_82544GC_COPPER: 1248 case E1000_DEV_ID_82544GC_LOM: 1249 hw->mac_type = e1000_82544; 1250 break; 1251 case E1000_DEV_ID_82540EM: 1252 case E1000_DEV_ID_82540EM_LOM: 1253 case E1000_DEV_ID_82540EP: 1254 case E1000_DEV_ID_82540EP_LOM: 1255 case E1000_DEV_ID_82540EP_LP: 1256 hw->mac_type = e1000_82540; 1257 break; 1258 case E1000_DEV_ID_82545EM_COPPER: 1259 case E1000_DEV_ID_82545EM_FIBER: 1260 hw->mac_type = e1000_82545; 1261 break; 1262 case E1000_DEV_ID_82545GM_COPPER: 1263 case E1000_DEV_ID_82545GM_FIBER: 1264 case E1000_DEV_ID_82545GM_SERDES: 1265 hw->mac_type = e1000_82545_rev_3; 1266 break; 1267 case E1000_DEV_ID_82546EB_COPPER: 1268 case E1000_DEV_ID_82546EB_FIBER: 1269 case E1000_DEV_ID_82546EB_QUAD_COPPER: 1270 hw->mac_type = e1000_82546; 1271 break; 1272 case E1000_DEV_ID_82546GB_COPPER: 1273 case E1000_DEV_ID_82546GB_FIBER: 1274 case E1000_DEV_ID_82546GB_SERDES: 1275 case E1000_DEV_ID_82546GB_PCIE: 1276 case E1000_DEV_ID_82546GB_QUAD_COPPER: 1277 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3: 1278 hw->mac_type = e1000_82546_rev_3; 1279 break; 1280 case E1000_DEV_ID_82541EI: 1281 case E1000_DEV_ID_82541EI_MOBILE: 1282 case E1000_DEV_ID_82541ER_LOM: 1283 hw->mac_type = e1000_82541; 1284 break; 1285 case E1000_DEV_ID_82541ER: 1286 case E1000_DEV_ID_82541GI: 1287 case E1000_DEV_ID_82541GI_LF: 1288 case E1000_DEV_ID_82541GI_MOBILE: 1289 hw->mac_type = e1000_82541_rev_2; 1290 break; 1291 case E1000_DEV_ID_82547EI: 1292 case E1000_DEV_ID_82547EI_MOBILE: 1293 hw->mac_type = e1000_82547; 1294 break; 1295 case E1000_DEV_ID_82547GI: 1296 hw->mac_type = e1000_82547_rev_2; 1297 break; 1298 case E1000_DEV_ID_82571EB_COPPER: 1299 case E1000_DEV_ID_82571EB_FIBER: 1300 case E1000_DEV_ID_82571EB_SERDES: 1301 case E1000_DEV_ID_82571EB_SERDES_DUAL: 1302 case E1000_DEV_ID_82571EB_SERDES_QUAD: 1303 case E1000_DEV_ID_82571EB_QUAD_COPPER: 1304 case E1000_DEV_ID_82571PT_QUAD_COPPER: 1305 case E1000_DEV_ID_82571EB_QUAD_FIBER: 1306 case E1000_DEV_ID_82571EB_QUAD_COPPER_LOWPROFILE: 1307 hw->mac_type = e1000_82571; 1308 break; 1309 case E1000_DEV_ID_82572EI_COPPER: 1310 case E1000_DEV_ID_82572EI_FIBER: 1311 case E1000_DEV_ID_82572EI_SERDES: 1312 case E1000_DEV_ID_82572EI: 1313 hw->mac_type = e1000_82572; 1314 break; 1315 case E1000_DEV_ID_82573E: 1316 case E1000_DEV_ID_82573E_IAMT: 1317 case E1000_DEV_ID_82573L: 1318 hw->mac_type = e1000_82573; 1319 break; 1320 case E1000_DEV_ID_80003ES2LAN_COPPER_SPT: 1321 case E1000_DEV_ID_80003ES2LAN_SERDES_SPT: 1322 case E1000_DEV_ID_80003ES2LAN_COPPER_DPT: 1323 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT: 1324 hw->mac_type = e1000_80003es2lan; 1325 break; 1326 case E1000_DEV_ID_ICH8_IGP_M_AMT: 1327 case E1000_DEV_ID_ICH8_IGP_AMT: 1328 case E1000_DEV_ID_ICH8_IGP_C: 1329 case E1000_DEV_ID_ICH8_IFE: 1330 case E1000_DEV_ID_ICH8_IFE_GT: 1331 case E1000_DEV_ID_ICH8_IFE_G: 1332 case E1000_DEV_ID_ICH8_IGP_M: 1333 hw->mac_type = e1000_ich8lan; 1334 break; 1335 default: 1336 /* Should never have loaded on this device */ 1337 return -E1000_ERR_MAC_TYPE; 1338 } 1339 return E1000_SUCCESS; 1340 } 1341 1342 /****************************************************************************** 1343 * Reset the transmit and receive units; mask and clear all interrupts. 1344 * 1345 * hw - Struct containing variables accessed by shared code 1346 *****************************************************************************/ 1347 void 1348 e1000_reset_hw(struct e1000_hw *hw) 1349 { 1350 uint32_t ctrl; 1351 uint32_t ctrl_ext; 1352 uint32_t icr; 1353 uint32_t manc; 1354 uint32_t pba = 0; 1355 1356 DEBUGFUNC(); 1357 1358 /* get the correct pba value for both PCI and PCIe*/ 1359 if (hw->mac_type < e1000_82571) 1360 pba = E1000_DEFAULT_PCI_PBA; 1361 else 1362 pba = E1000_DEFAULT_PCIE_PBA; 1363 1364 /* For 82542 (rev 2.0), disable MWI before issuing a device reset */ 1365 if (hw->mac_type == e1000_82542_rev2_0) { 1366 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n"); 1367 pci_write_config_word(hw->pdev, PCI_COMMAND, 1368 hw->pci_cmd_word & ~PCI_COMMAND_INVALIDATE); 1369 } 1370 1371 /* Clear interrupt mask to stop board from generating interrupts */ 1372 DEBUGOUT("Masking off all interrupts\n"); 1373 E1000_WRITE_REG(hw, IMC, 0xffffffff); 1374 1375 /* Disable the Transmit and Receive units. Then delay to allow 1376 * any pending transactions to complete before we hit the MAC with 1377 * the global reset. 1378 */ 1379 E1000_WRITE_REG(hw, RCTL, 0); 1380 E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP); 1381 E1000_WRITE_FLUSH(hw); 1382 1383 /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */ 1384 hw->tbi_compatibility_on = FALSE; 1385 1386 /* Delay to allow any outstanding PCI transactions to complete before 1387 * resetting the device 1388 */ 1389 mdelay(10); 1390 1391 /* Issue a global reset to the MAC. This will reset the chip's 1392 * transmit, receive, DMA, and link units. It will not effect 1393 * the current PCI configuration. The global reset bit is self- 1394 * clearing, and should clear within a microsecond. 1395 */ 1396 DEBUGOUT("Issuing a global reset to MAC\n"); 1397 ctrl = E1000_READ_REG(hw, CTRL); 1398 1399 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST)); 1400 1401 /* Force a reload from the EEPROM if necessary */ 1402 if (hw->mac_type < e1000_82540) { 1403 /* Wait for reset to complete */ 1404 udelay(10); 1405 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 1406 ctrl_ext |= E1000_CTRL_EXT_EE_RST; 1407 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 1408 E1000_WRITE_FLUSH(hw); 1409 /* Wait for EEPROM reload */ 1410 mdelay(2); 1411 } else { 1412 /* Wait for EEPROM reload (it happens automatically) */ 1413 mdelay(4); 1414 /* Dissable HW ARPs on ASF enabled adapters */ 1415 manc = E1000_READ_REG(hw, MANC); 1416 manc &= ~(E1000_MANC_ARP_EN); 1417 E1000_WRITE_REG(hw, MANC, manc); 1418 } 1419 1420 /* Clear interrupt mask to stop board from generating interrupts */ 1421 DEBUGOUT("Masking off all interrupts\n"); 1422 E1000_WRITE_REG(hw, IMC, 0xffffffff); 1423 1424 /* Clear any pending interrupt events. */ 1425 icr = E1000_READ_REG(hw, ICR); 1426 1427 /* If MWI was previously enabled, reenable it. */ 1428 if (hw->mac_type == e1000_82542_rev2_0) { 1429 pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word); 1430 } 1431 E1000_WRITE_REG(hw, PBA, pba); 1432 } 1433 1434 /****************************************************************************** 1435 * 1436 * Initialize a number of hardware-dependent bits 1437 * 1438 * hw: Struct containing variables accessed by shared code 1439 * 1440 * This function contains hardware limitation workarounds for PCI-E adapters 1441 * 1442 *****************************************************************************/ 1443 static void 1444 e1000_initialize_hardware_bits(struct e1000_hw *hw) 1445 { 1446 if ((hw->mac_type >= e1000_82571) && 1447 (!hw->initialize_hw_bits_disable)) { 1448 /* Settings common to all PCI-express silicon */ 1449 uint32_t reg_ctrl, reg_ctrl_ext; 1450 uint32_t reg_tarc0, reg_tarc1; 1451 uint32_t reg_tctl; 1452 uint32_t reg_txdctl, reg_txdctl1; 1453 1454 /* link autonegotiation/sync workarounds */ 1455 reg_tarc0 = E1000_READ_REG(hw, TARC0); 1456 reg_tarc0 &= ~((1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)); 1457 1458 /* Enable not-done TX descriptor counting */ 1459 reg_txdctl = E1000_READ_REG(hw, TXDCTL); 1460 reg_txdctl |= E1000_TXDCTL_COUNT_DESC; 1461 E1000_WRITE_REG(hw, TXDCTL, reg_txdctl); 1462 1463 reg_txdctl1 = E1000_READ_REG(hw, TXDCTL1); 1464 reg_txdctl1 |= E1000_TXDCTL_COUNT_DESC; 1465 E1000_WRITE_REG(hw, TXDCTL1, reg_txdctl1); 1466 1467 switch (hw->mac_type) { 1468 case e1000_82571: 1469 case e1000_82572: 1470 /* Clear PHY TX compatible mode bits */ 1471 reg_tarc1 = E1000_READ_REG(hw, TARC1); 1472 reg_tarc1 &= ~((1 << 30)|(1 << 29)); 1473 1474 /* link autonegotiation/sync workarounds */ 1475 reg_tarc0 |= ((1 << 26)|(1 << 25)|(1 << 24)|(1 << 23)); 1476 1477 /* TX ring control fixes */ 1478 reg_tarc1 |= ((1 << 26)|(1 << 25)|(1 << 24)); 1479 1480 /* Multiple read bit is reversed polarity */ 1481 reg_tctl = E1000_READ_REG(hw, TCTL); 1482 if (reg_tctl & E1000_TCTL_MULR) 1483 reg_tarc1 &= ~(1 << 28); 1484 else 1485 reg_tarc1 |= (1 << 28); 1486 1487 E1000_WRITE_REG(hw, TARC1, reg_tarc1); 1488 break; 1489 case e1000_82573: 1490 reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 1491 reg_ctrl_ext &= ~(1 << 23); 1492 reg_ctrl_ext |= (1 << 22); 1493 1494 /* TX byte count fix */ 1495 reg_ctrl = E1000_READ_REG(hw, CTRL); 1496 reg_ctrl &= ~(1 << 29); 1497 1498 E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext); 1499 E1000_WRITE_REG(hw, CTRL, reg_ctrl); 1500 break; 1501 case e1000_80003es2lan: 1502 /* improve small packet performace for fiber/serdes */ 1503 if ((hw->media_type == e1000_media_type_fiber) 1504 || (hw->media_type == 1505 e1000_media_type_internal_serdes)) { 1506 reg_tarc0 &= ~(1 << 20); 1507 } 1508 1509 /* Multiple read bit is reversed polarity */ 1510 reg_tctl = E1000_READ_REG(hw, TCTL); 1511 reg_tarc1 = E1000_READ_REG(hw, TARC1); 1512 if (reg_tctl & E1000_TCTL_MULR) 1513 reg_tarc1 &= ~(1 << 28); 1514 else 1515 reg_tarc1 |= (1 << 28); 1516 1517 E1000_WRITE_REG(hw, TARC1, reg_tarc1); 1518 break; 1519 case e1000_ich8lan: 1520 /* Reduce concurrent DMA requests to 3 from 4 */ 1521 if ((hw->revision_id < 3) || 1522 ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) && 1523 (hw->device_id != E1000_DEV_ID_ICH8_IGP_M))) 1524 reg_tarc0 |= ((1 << 29)|(1 << 28)); 1525 1526 reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 1527 reg_ctrl_ext |= (1 << 22); 1528 E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext); 1529 1530 /* workaround TX hang with TSO=on */ 1531 reg_tarc0 |= ((1 << 27)|(1 << 26)|(1 << 24)|(1 << 23)); 1532 1533 /* Multiple read bit is reversed polarity */ 1534 reg_tctl = E1000_READ_REG(hw, TCTL); 1535 reg_tarc1 = E1000_READ_REG(hw, TARC1); 1536 if (reg_tctl & E1000_TCTL_MULR) 1537 reg_tarc1 &= ~(1 << 28); 1538 else 1539 reg_tarc1 |= (1 << 28); 1540 1541 /* workaround TX hang with TSO=on */ 1542 reg_tarc1 |= ((1 << 30)|(1 << 26)|(1 << 24)); 1543 1544 E1000_WRITE_REG(hw, TARC1, reg_tarc1); 1545 break; 1546 default: 1547 break; 1548 } 1549 1550 E1000_WRITE_REG(hw, TARC0, reg_tarc0); 1551 } 1552 } 1553 1554 /****************************************************************************** 1555 * Performs basic configuration of the adapter. 1556 * 1557 * hw - Struct containing variables accessed by shared code 1558 * 1559 * Assumes that the controller has previously been reset and is in a 1560 * post-reset uninitialized state. Initializes the receive address registers, 1561 * multicast table, and VLAN filter table. Calls routines to setup link 1562 * configuration and flow control settings. Clears all on-chip counters. Leaves 1563 * the transmit and receive units disabled and uninitialized. 1564 *****************************************************************************/ 1565 static int 1566 e1000_init_hw(struct eth_device *nic) 1567 { 1568 struct e1000_hw *hw = nic->priv; 1569 uint32_t ctrl; 1570 uint32_t i; 1571 int32_t ret_val; 1572 uint16_t pcix_cmd_word; 1573 uint16_t pcix_stat_hi_word; 1574 uint16_t cmd_mmrbc; 1575 uint16_t stat_mmrbc; 1576 uint32_t mta_size; 1577 uint32_t reg_data; 1578 uint32_t ctrl_ext; 1579 DEBUGFUNC(); 1580 /* force full DMA clock frequency for 10/100 on ICH8 A0-B0 */ 1581 if ((hw->mac_type == e1000_ich8lan) && 1582 ((hw->revision_id < 3) || 1583 ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) && 1584 (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))) { 1585 reg_data = E1000_READ_REG(hw, STATUS); 1586 reg_data &= ~0x80000000; 1587 E1000_WRITE_REG(hw, STATUS, reg_data); 1588 } 1589 /* Do not need initialize Identification LED */ 1590 1591 /* Set the media type and TBI compatibility */ 1592 e1000_set_media_type(hw); 1593 1594 /* Must be called after e1000_set_media_type 1595 * because media_type is used */ 1596 e1000_initialize_hardware_bits(hw); 1597 1598 /* Disabling VLAN filtering. */ 1599 DEBUGOUT("Initializing the IEEE VLAN\n"); 1600 /* VET hardcoded to standard value and VFTA removed in ICH8 LAN */ 1601 if (hw->mac_type != e1000_ich8lan) { 1602 if (hw->mac_type < e1000_82545_rev_3) 1603 E1000_WRITE_REG(hw, VET, 0); 1604 e1000_clear_vfta(hw); 1605 } 1606 1607 /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */ 1608 if (hw->mac_type == e1000_82542_rev2_0) { 1609 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n"); 1610 pci_write_config_word(hw->pdev, PCI_COMMAND, 1611 hw-> 1612 pci_cmd_word & ~PCI_COMMAND_INVALIDATE); 1613 E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST); 1614 E1000_WRITE_FLUSH(hw); 1615 mdelay(5); 1616 } 1617 1618 /* Setup the receive address. This involves initializing all of the Receive 1619 * Address Registers (RARs 0 - 15). 1620 */ 1621 e1000_init_rx_addrs(nic); 1622 1623 /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */ 1624 if (hw->mac_type == e1000_82542_rev2_0) { 1625 E1000_WRITE_REG(hw, RCTL, 0); 1626 E1000_WRITE_FLUSH(hw); 1627 mdelay(1); 1628 pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word); 1629 } 1630 1631 /* Zero out the Multicast HASH table */ 1632 DEBUGOUT("Zeroing the MTA\n"); 1633 mta_size = E1000_MC_TBL_SIZE; 1634 if (hw->mac_type == e1000_ich8lan) 1635 mta_size = E1000_MC_TBL_SIZE_ICH8LAN; 1636 for (i = 0; i < mta_size; i++) { 1637 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0); 1638 /* use write flush to prevent Memory Write Block (MWB) from 1639 * occuring when accessing our register space */ 1640 E1000_WRITE_FLUSH(hw); 1641 } 1642 #if 0 1643 /* Set the PCI priority bit correctly in the CTRL register. This 1644 * determines if the adapter gives priority to receives, or if it 1645 * gives equal priority to transmits and receives. Valid only on 1646 * 82542 and 82543 silicon. 1647 */ 1648 if (hw->dma_fairness && hw->mac_type <= e1000_82543) { 1649 ctrl = E1000_READ_REG(hw, CTRL); 1650 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR); 1651 } 1652 #endif 1653 switch (hw->mac_type) { 1654 case e1000_82545_rev_3: 1655 case e1000_82546_rev_3: 1656 break; 1657 default: 1658 /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */ 1659 if (hw->bus_type == e1000_bus_type_pcix) { 1660 pci_read_config_word(hw->pdev, PCIX_COMMAND_REGISTER, 1661 &pcix_cmd_word); 1662 pci_read_config_word(hw->pdev, PCIX_STATUS_REGISTER_HI, 1663 &pcix_stat_hi_word); 1664 cmd_mmrbc = 1665 (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) >> 1666 PCIX_COMMAND_MMRBC_SHIFT; 1667 stat_mmrbc = 1668 (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >> 1669 PCIX_STATUS_HI_MMRBC_SHIFT; 1670 if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K) 1671 stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K; 1672 if (cmd_mmrbc > stat_mmrbc) { 1673 pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK; 1674 pcix_cmd_word |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT; 1675 pci_write_config_word(hw->pdev, PCIX_COMMAND_REGISTER, 1676 pcix_cmd_word); 1677 } 1678 } 1679 break; 1680 } 1681 1682 /* More time needed for PHY to initialize */ 1683 if (hw->mac_type == e1000_ich8lan) 1684 mdelay(15); 1685 1686 /* Call a subroutine to configure the link and setup flow control. */ 1687 ret_val = e1000_setup_link(nic); 1688 1689 /* Set the transmit descriptor write-back policy */ 1690 if (hw->mac_type > e1000_82544) { 1691 ctrl = E1000_READ_REG(hw, TXDCTL); 1692 ctrl = 1693 (ctrl & ~E1000_TXDCTL_WTHRESH) | 1694 E1000_TXDCTL_FULL_TX_DESC_WB; 1695 E1000_WRITE_REG(hw, TXDCTL, ctrl); 1696 } 1697 1698 switch (hw->mac_type) { 1699 default: 1700 break; 1701 case e1000_80003es2lan: 1702 /* Enable retransmit on late collisions */ 1703 reg_data = E1000_READ_REG(hw, TCTL); 1704 reg_data |= E1000_TCTL_RTLC; 1705 E1000_WRITE_REG(hw, TCTL, reg_data); 1706 1707 /* Configure Gigabit Carry Extend Padding */ 1708 reg_data = E1000_READ_REG(hw, TCTL_EXT); 1709 reg_data &= ~E1000_TCTL_EXT_GCEX_MASK; 1710 reg_data |= DEFAULT_80003ES2LAN_TCTL_EXT_GCEX; 1711 E1000_WRITE_REG(hw, TCTL_EXT, reg_data); 1712 1713 /* Configure Transmit Inter-Packet Gap */ 1714 reg_data = E1000_READ_REG(hw, TIPG); 1715 reg_data &= ~E1000_TIPG_IPGT_MASK; 1716 reg_data |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000; 1717 E1000_WRITE_REG(hw, TIPG, reg_data); 1718 1719 reg_data = E1000_READ_REG_ARRAY(hw, FFLT, 0x0001); 1720 reg_data &= ~0x00100000; 1721 E1000_WRITE_REG_ARRAY(hw, FFLT, 0x0001, reg_data); 1722 /* Fall through */ 1723 case e1000_82571: 1724 case e1000_82572: 1725 case e1000_ich8lan: 1726 ctrl = E1000_READ_REG(hw, TXDCTL1); 1727 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) 1728 | E1000_TXDCTL_FULL_TX_DESC_WB; 1729 E1000_WRITE_REG(hw, TXDCTL1, ctrl); 1730 break; 1731 } 1732 1733 if (hw->mac_type == e1000_82573) { 1734 uint32_t gcr = E1000_READ_REG(hw, GCR); 1735 gcr |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX; 1736 E1000_WRITE_REG(hw, GCR, gcr); 1737 } 1738 1739 #if 0 1740 /* Clear all of the statistics registers (clear on read). It is 1741 * important that we do this after we have tried to establish link 1742 * because the symbol error count will increment wildly if there 1743 * is no link. 1744 */ 1745 e1000_clear_hw_cntrs(hw); 1746 1747 /* ICH8 No-snoop bits are opposite polarity. 1748 * Set to snoop by default after reset. */ 1749 if (hw->mac_type == e1000_ich8lan) 1750 e1000_set_pci_ex_no_snoop(hw, PCI_EX_82566_SNOOP_ALL); 1751 #endif 1752 1753 if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER || 1754 hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) { 1755 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 1756 /* Relaxed ordering must be disabled to avoid a parity 1757 * error crash in a PCI slot. */ 1758 ctrl_ext |= E1000_CTRL_EXT_RO_DIS; 1759 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 1760 } 1761 1762 return ret_val; 1763 } 1764 1765 /****************************************************************************** 1766 * Configures flow control and link settings. 1767 * 1768 * hw - Struct containing variables accessed by shared code 1769 * 1770 * Determines which flow control settings to use. Calls the apropriate media- 1771 * specific link configuration function. Configures the flow control settings. 1772 * Assuming the adapter has a valid link partner, a valid link should be 1773 * established. Assumes the hardware has previously been reset and the 1774 * transmitter and receiver are not enabled. 1775 *****************************************************************************/ 1776 static int 1777 e1000_setup_link(struct eth_device *nic) 1778 { 1779 struct e1000_hw *hw = nic->priv; 1780 uint32_t ctrl_ext; 1781 int32_t ret_val; 1782 uint16_t eeprom_data; 1783 1784 DEBUGFUNC(); 1785 1786 /* In the case of the phy reset being blocked, we already have a link. 1787 * We do not have to set it up again. */ 1788 if (e1000_check_phy_reset_block(hw)) 1789 return E1000_SUCCESS; 1790 1791 #ifndef CONFIG_AP1000 1792 /* Read and store word 0x0F of the EEPROM. This word contains bits 1793 * that determine the hardware's default PAUSE (flow control) mode, 1794 * a bit that determines whether the HW defaults to enabling or 1795 * disabling auto-negotiation, and the direction of the 1796 * SW defined pins. If there is no SW over-ride of the flow 1797 * control setting, then the variable hw->fc will 1798 * be initialized based on a value in the EEPROM. 1799 */ 1800 if (e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, 1, 1801 &eeprom_data) < 0) { 1802 DEBUGOUT("EEPROM Read Error\n"); 1803 return -E1000_ERR_EEPROM; 1804 } 1805 #else 1806 /* we have to hardcode the proper value for our hardware. */ 1807 /* this value is for the 82540EM pci card used for prototyping, and it works. */ 1808 eeprom_data = 0xb220; 1809 #endif 1810 1811 if (hw->fc == e1000_fc_default) { 1812 switch (hw->mac_type) { 1813 case e1000_ich8lan: 1814 case e1000_82573: 1815 hw->fc = e1000_fc_full; 1816 break; 1817 default: 1818 #ifndef CONFIG_AP1000 1819 ret_val = e1000_read_eeprom(hw, 1820 EEPROM_INIT_CONTROL2_REG, 1, &eeprom_data); 1821 if (ret_val) { 1822 DEBUGOUT("EEPROM Read Error\n"); 1823 return -E1000_ERR_EEPROM; 1824 } 1825 #else 1826 eeprom_data = 0xb220; 1827 #endif 1828 if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0) 1829 hw->fc = e1000_fc_none; 1830 else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 1831 EEPROM_WORD0F_ASM_DIR) 1832 hw->fc = e1000_fc_tx_pause; 1833 else 1834 hw->fc = e1000_fc_full; 1835 break; 1836 } 1837 } 1838 1839 /* We want to save off the original Flow Control configuration just 1840 * in case we get disconnected and then reconnected into a different 1841 * hub or switch with different Flow Control capabilities. 1842 */ 1843 if (hw->mac_type == e1000_82542_rev2_0) 1844 hw->fc &= (~e1000_fc_tx_pause); 1845 1846 if ((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1)) 1847 hw->fc &= (~e1000_fc_rx_pause); 1848 1849 hw->original_fc = hw->fc; 1850 1851 DEBUGOUT("After fix-ups FlowControl is now = %x\n", hw->fc); 1852 1853 /* Take the 4 bits from EEPROM word 0x0F that determine the initial 1854 * polarity value for the SW controlled pins, and setup the 1855 * Extended Device Control reg with that info. 1856 * This is needed because one of the SW controlled pins is used for 1857 * signal detection. So this should be done before e1000_setup_pcs_link() 1858 * or e1000_phy_setup() is called. 1859 */ 1860 if (hw->mac_type == e1000_82543) { 1861 ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) << 1862 SWDPIO__EXT_SHIFT); 1863 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 1864 } 1865 1866 /* Call the necessary subroutine to configure the link. */ 1867 ret_val = (hw->media_type == e1000_media_type_fiber) ? 1868 e1000_setup_fiber_link(nic) : e1000_setup_copper_link(nic); 1869 if (ret_val < 0) { 1870 return ret_val; 1871 } 1872 1873 /* Initialize the flow control address, type, and PAUSE timer 1874 * registers to their default values. This is done even if flow 1875 * control is disabled, because it does not hurt anything to 1876 * initialize these registers. 1877 */ 1878 DEBUGOUT("Initializing the Flow Control address, type" 1879 "and timer regs\n"); 1880 1881 /* FCAL/H and FCT are hardcoded to standard values in e1000_ich8lan. */ 1882 if (hw->mac_type != e1000_ich8lan) { 1883 E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE); 1884 E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH); 1885 E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW); 1886 } 1887 1888 E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time); 1889 1890 /* Set the flow control receive threshold registers. Normally, 1891 * these registers will be set to a default threshold that may be 1892 * adjusted later by the driver's runtime code. However, if the 1893 * ability to transmit pause frames in not enabled, then these 1894 * registers will be set to 0. 1895 */ 1896 if (!(hw->fc & e1000_fc_tx_pause)) { 1897 E1000_WRITE_REG(hw, FCRTL, 0); 1898 E1000_WRITE_REG(hw, FCRTH, 0); 1899 } else { 1900 /* We need to set up the Receive Threshold high and low water marks 1901 * as well as (optionally) enabling the transmission of XON frames. 1902 */ 1903 if (hw->fc_send_xon) { 1904 E1000_WRITE_REG(hw, FCRTL, 1905 (hw->fc_low_water | E1000_FCRTL_XONE)); 1906 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water); 1907 } else { 1908 E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water); 1909 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water); 1910 } 1911 } 1912 return ret_val; 1913 } 1914 1915 /****************************************************************************** 1916 * Sets up link for a fiber based adapter 1917 * 1918 * hw - Struct containing variables accessed by shared code 1919 * 1920 * Manipulates Physical Coding Sublayer functions in order to configure 1921 * link. Assumes the hardware has been previously reset and the transmitter 1922 * and receiver are not enabled. 1923 *****************************************************************************/ 1924 static int 1925 e1000_setup_fiber_link(struct eth_device *nic) 1926 { 1927 struct e1000_hw *hw = nic->priv; 1928 uint32_t ctrl; 1929 uint32_t status; 1930 uint32_t txcw = 0; 1931 uint32_t i; 1932 uint32_t signal; 1933 int32_t ret_val; 1934 1935 DEBUGFUNC(); 1936 /* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be 1937 * set when the optics detect a signal. On older adapters, it will be 1938 * cleared when there is a signal 1939 */ 1940 ctrl = E1000_READ_REG(hw, CTRL); 1941 if ((hw->mac_type > e1000_82544) && !(ctrl & E1000_CTRL_ILOS)) 1942 signal = E1000_CTRL_SWDPIN1; 1943 else 1944 signal = 0; 1945 1946 printf("signal for %s is %x (ctrl %08x)!!!!\n", nic->name, signal, 1947 ctrl); 1948 /* Take the link out of reset */ 1949 ctrl &= ~(E1000_CTRL_LRST); 1950 1951 e1000_config_collision_dist(hw); 1952 1953 /* Check for a software override of the flow control settings, and setup 1954 * the device accordingly. If auto-negotiation is enabled, then software 1955 * will have to set the "PAUSE" bits to the correct value in the Tranmsit 1956 * Config Word Register (TXCW) and re-start auto-negotiation. However, if 1957 * auto-negotiation is disabled, then software will have to manually 1958 * configure the two flow control enable bits in the CTRL register. 1959 * 1960 * The possible values of the "fc" parameter are: 1961 * 0: Flow control is completely disabled 1962 * 1: Rx flow control is enabled (we can receive pause frames, but 1963 * not send pause frames). 1964 * 2: Tx flow control is enabled (we can send pause frames but we do 1965 * not support receiving pause frames). 1966 * 3: Both Rx and TX flow control (symmetric) are enabled. 1967 */ 1968 switch (hw->fc) { 1969 case e1000_fc_none: 1970 /* Flow control is completely disabled by a software over-ride. */ 1971 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD); 1972 break; 1973 case e1000_fc_rx_pause: 1974 /* RX Flow control is enabled and TX Flow control is disabled by a 1975 * software over-ride. Since there really isn't a way to advertise 1976 * that we are capable of RX Pause ONLY, we will advertise that we 1977 * support both symmetric and asymmetric RX PAUSE. Later, we will 1978 * disable the adapter's ability to send PAUSE frames. 1979 */ 1980 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); 1981 break; 1982 case e1000_fc_tx_pause: 1983 /* TX Flow control is enabled, and RX Flow control is disabled, by a 1984 * software over-ride. 1985 */ 1986 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR); 1987 break; 1988 case e1000_fc_full: 1989 /* Flow control (both RX and TX) is enabled by a software over-ride. */ 1990 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); 1991 break; 1992 default: 1993 DEBUGOUT("Flow control param set incorrectly\n"); 1994 return -E1000_ERR_CONFIG; 1995 break; 1996 } 1997 1998 /* Since auto-negotiation is enabled, take the link out of reset (the link 1999 * will be in reset, because we previously reset the chip). This will 2000 * restart auto-negotiation. If auto-neogtiation is successful then the 2001 * link-up status bit will be set and the flow control enable bits (RFCE 2002 * and TFCE) will be set according to their negotiated value. 2003 */ 2004 DEBUGOUT("Auto-negotiation enabled (%#x)\n", txcw); 2005 2006 E1000_WRITE_REG(hw, TXCW, txcw); 2007 E1000_WRITE_REG(hw, CTRL, ctrl); 2008 E1000_WRITE_FLUSH(hw); 2009 2010 hw->txcw = txcw; 2011 mdelay(1); 2012 2013 /* If we have a signal (the cable is plugged in) then poll for a "Link-Up" 2014 * indication in the Device Status Register. Time-out if a link isn't 2015 * seen in 500 milliseconds seconds (Auto-negotiation should complete in 2016 * less than 500 milliseconds even if the other end is doing it in SW). 2017 */ 2018 if ((E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) { 2019 DEBUGOUT("Looking for Link\n"); 2020 for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) { 2021 mdelay(10); 2022 status = E1000_READ_REG(hw, STATUS); 2023 if (status & E1000_STATUS_LU) 2024 break; 2025 } 2026 if (i == (LINK_UP_TIMEOUT / 10)) { 2027 /* AutoNeg failed to achieve a link, so we'll call 2028 * e1000_check_for_link. This routine will force the link up if we 2029 * detect a signal. This will allow us to communicate with 2030 * non-autonegotiating link partners. 2031 */ 2032 DEBUGOUT("Never got a valid link from auto-neg!!!\n"); 2033 hw->autoneg_failed = 1; 2034 ret_val = e1000_check_for_link(nic); 2035 if (ret_val < 0) { 2036 DEBUGOUT("Error while checking for link\n"); 2037 return ret_val; 2038 } 2039 hw->autoneg_failed = 0; 2040 } else { 2041 hw->autoneg_failed = 0; 2042 DEBUGOUT("Valid Link Found\n"); 2043 } 2044 } else { 2045 DEBUGOUT("No Signal Detected\n"); 2046 return -E1000_ERR_NOLINK; 2047 } 2048 return 0; 2049 } 2050 2051 /****************************************************************************** 2052 * Make sure we have a valid PHY and change PHY mode before link setup. 2053 * 2054 * hw - Struct containing variables accessed by shared code 2055 ******************************************************************************/ 2056 static int32_t 2057 e1000_copper_link_preconfig(struct e1000_hw *hw) 2058 { 2059 uint32_t ctrl; 2060 int32_t ret_val; 2061 uint16_t phy_data; 2062 2063 DEBUGFUNC(); 2064 2065 ctrl = E1000_READ_REG(hw, CTRL); 2066 /* With 82543, we need to force speed and duplex on the MAC equal to what 2067 * the PHY speed and duplex configuration is. In addition, we need to 2068 * perform a hardware reset on the PHY to take it out of reset. 2069 */ 2070 if (hw->mac_type > e1000_82543) { 2071 ctrl |= E1000_CTRL_SLU; 2072 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 2073 E1000_WRITE_REG(hw, CTRL, ctrl); 2074 } else { 2075 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX 2076 | E1000_CTRL_SLU); 2077 E1000_WRITE_REG(hw, CTRL, ctrl); 2078 ret_val = e1000_phy_hw_reset(hw); 2079 if (ret_val) 2080 return ret_val; 2081 } 2082 2083 /* Make sure we have a valid PHY */ 2084 ret_val = e1000_detect_gig_phy(hw); 2085 if (ret_val) { 2086 DEBUGOUT("Error, did not detect valid phy.\n"); 2087 return ret_val; 2088 } 2089 DEBUGOUT("Phy ID = %x \n", hw->phy_id); 2090 2091 #ifndef CONFIG_AP1000 2092 /* Set PHY to class A mode (if necessary) */ 2093 ret_val = e1000_set_phy_mode(hw); 2094 if (ret_val) 2095 return ret_val; 2096 #endif 2097 if ((hw->mac_type == e1000_82545_rev_3) || 2098 (hw->mac_type == e1000_82546_rev_3)) { 2099 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 2100 &phy_data); 2101 phy_data |= 0x00000008; 2102 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 2103 phy_data); 2104 } 2105 2106 if (hw->mac_type <= e1000_82543 || 2107 hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 || 2108 hw->mac_type == e1000_82541_rev_2 2109 || hw->mac_type == e1000_82547_rev_2) 2110 hw->phy_reset_disable = FALSE; 2111 2112 return E1000_SUCCESS; 2113 } 2114 2115 /***************************************************************************** 2116 * 2117 * This function sets the lplu state according to the active flag. When 2118 * activating lplu this function also disables smart speed and vise versa. 2119 * lplu will not be activated unless the device autonegotiation advertisment 2120 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes. 2121 * hw: Struct containing variables accessed by shared code 2122 * active - true to enable lplu false to disable lplu. 2123 * 2124 * returns: - E1000_ERR_PHY if fail to read/write the PHY 2125 * E1000_SUCCESS at any other case. 2126 * 2127 ****************************************************************************/ 2128 2129 static int32_t 2130 e1000_set_d3_lplu_state(struct e1000_hw *hw, boolean_t active) 2131 { 2132 uint32_t phy_ctrl = 0; 2133 int32_t ret_val; 2134 uint16_t phy_data; 2135 DEBUGFUNC(); 2136 2137 if (hw->phy_type != e1000_phy_igp && hw->phy_type != e1000_phy_igp_2 2138 && hw->phy_type != e1000_phy_igp_3) 2139 return E1000_SUCCESS; 2140 2141 /* During driver activity LPLU should not be used or it will attain link 2142 * from the lowest speeds starting from 10Mbps. The capability is used 2143 * for Dx transitions and states */ 2144 if (hw->mac_type == e1000_82541_rev_2 2145 || hw->mac_type == e1000_82547_rev_2) { 2146 ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, 2147 &phy_data); 2148 if (ret_val) 2149 return ret_val; 2150 } else if (hw->mac_type == e1000_ich8lan) { 2151 /* MAC writes into PHY register based on the state transition 2152 * and start auto-negotiation. SW driver can overwrite the 2153 * settings in CSR PHY power control E1000_PHY_CTRL register. */ 2154 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL); 2155 } else { 2156 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, 2157 &phy_data); 2158 if (ret_val) 2159 return ret_val; 2160 } 2161 2162 if (!active) { 2163 if (hw->mac_type == e1000_82541_rev_2 || 2164 hw->mac_type == e1000_82547_rev_2) { 2165 phy_data &= ~IGP01E1000_GMII_FLEX_SPD; 2166 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, 2167 phy_data); 2168 if (ret_val) 2169 return ret_val; 2170 } else { 2171 if (hw->mac_type == e1000_ich8lan) { 2172 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU; 2173 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); 2174 } else { 2175 phy_data &= ~IGP02E1000_PM_D3_LPLU; 2176 ret_val = e1000_write_phy_reg(hw, 2177 IGP02E1000_PHY_POWER_MGMT, phy_data); 2178 if (ret_val) 2179 return ret_val; 2180 } 2181 } 2182 2183 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during 2184 * Dx states where the power conservation is most important. During 2185 * driver activity we should enable SmartSpeed, so performance is 2186 * maintained. */ 2187 if (hw->smart_speed == e1000_smart_speed_on) { 2188 ret_val = e1000_read_phy_reg(hw, 2189 IGP01E1000_PHY_PORT_CONFIG, &phy_data); 2190 if (ret_val) 2191 return ret_val; 2192 2193 phy_data |= IGP01E1000_PSCFR_SMART_SPEED; 2194 ret_val = e1000_write_phy_reg(hw, 2195 IGP01E1000_PHY_PORT_CONFIG, phy_data); 2196 if (ret_val) 2197 return ret_val; 2198 } else if (hw->smart_speed == e1000_smart_speed_off) { 2199 ret_val = e1000_read_phy_reg(hw, 2200 IGP01E1000_PHY_PORT_CONFIG, &phy_data); 2201 if (ret_val) 2202 return ret_val; 2203 2204 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 2205 ret_val = e1000_write_phy_reg(hw, 2206 IGP01E1000_PHY_PORT_CONFIG, phy_data); 2207 if (ret_val) 2208 return ret_val; 2209 } 2210 2211 } else if ((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT) 2212 || (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL) || 2213 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) { 2214 2215 if (hw->mac_type == e1000_82541_rev_2 || 2216 hw->mac_type == e1000_82547_rev_2) { 2217 phy_data |= IGP01E1000_GMII_FLEX_SPD; 2218 ret_val = e1000_write_phy_reg(hw, 2219 IGP01E1000_GMII_FIFO, phy_data); 2220 if (ret_val) 2221 return ret_val; 2222 } else { 2223 if (hw->mac_type == e1000_ich8lan) { 2224 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU; 2225 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); 2226 } else { 2227 phy_data |= IGP02E1000_PM_D3_LPLU; 2228 ret_val = e1000_write_phy_reg(hw, 2229 IGP02E1000_PHY_POWER_MGMT, phy_data); 2230 if (ret_val) 2231 return ret_val; 2232 } 2233 } 2234 2235 /* When LPLU is enabled we should disable SmartSpeed */ 2236 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 2237 &phy_data); 2238 if (ret_val) 2239 return ret_val; 2240 2241 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 2242 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 2243 phy_data); 2244 if (ret_val) 2245 return ret_val; 2246 } 2247 return E1000_SUCCESS; 2248 } 2249 2250 /***************************************************************************** 2251 * 2252 * This function sets the lplu d0 state according to the active flag. When 2253 * activating lplu this function also disables smart speed and vise versa. 2254 * lplu will not be activated unless the device autonegotiation advertisment 2255 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes. 2256 * hw: Struct containing variables accessed by shared code 2257 * active - true to enable lplu false to disable lplu. 2258 * 2259 * returns: - E1000_ERR_PHY if fail to read/write the PHY 2260 * E1000_SUCCESS at any other case. 2261 * 2262 ****************************************************************************/ 2263 2264 static int32_t 2265 e1000_set_d0_lplu_state(struct e1000_hw *hw, boolean_t active) 2266 { 2267 uint32_t phy_ctrl = 0; 2268 int32_t ret_val; 2269 uint16_t phy_data; 2270 DEBUGFUNC(); 2271 2272 if (hw->mac_type <= e1000_82547_rev_2) 2273 return E1000_SUCCESS; 2274 2275 if (hw->mac_type == e1000_ich8lan) { 2276 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL); 2277 } else { 2278 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, 2279 &phy_data); 2280 if (ret_val) 2281 return ret_val; 2282 } 2283 2284 if (!active) { 2285 if (hw->mac_type == e1000_ich8lan) { 2286 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU; 2287 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); 2288 } else { 2289 phy_data &= ~IGP02E1000_PM_D0_LPLU; 2290 ret_val = e1000_write_phy_reg(hw, 2291 IGP02E1000_PHY_POWER_MGMT, phy_data); 2292 if (ret_val) 2293 return ret_val; 2294 } 2295 2296 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during 2297 * Dx states where the power conservation is most important. During 2298 * driver activity we should enable SmartSpeed, so performance is 2299 * maintained. */ 2300 if (hw->smart_speed == e1000_smart_speed_on) { 2301 ret_val = e1000_read_phy_reg(hw, 2302 IGP01E1000_PHY_PORT_CONFIG, &phy_data); 2303 if (ret_val) 2304 return ret_val; 2305 2306 phy_data |= IGP01E1000_PSCFR_SMART_SPEED; 2307 ret_val = e1000_write_phy_reg(hw, 2308 IGP01E1000_PHY_PORT_CONFIG, phy_data); 2309 if (ret_val) 2310 return ret_val; 2311 } else if (hw->smart_speed == e1000_smart_speed_off) { 2312 ret_val = e1000_read_phy_reg(hw, 2313 IGP01E1000_PHY_PORT_CONFIG, &phy_data); 2314 if (ret_val) 2315 return ret_val; 2316 2317 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 2318 ret_val = e1000_write_phy_reg(hw, 2319 IGP01E1000_PHY_PORT_CONFIG, phy_data); 2320 if (ret_val) 2321 return ret_val; 2322 } 2323 2324 2325 } else { 2326 2327 if (hw->mac_type == e1000_ich8lan) { 2328 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU; 2329 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); 2330 } else { 2331 phy_data |= IGP02E1000_PM_D0_LPLU; 2332 ret_val = e1000_write_phy_reg(hw, 2333 IGP02E1000_PHY_POWER_MGMT, phy_data); 2334 if (ret_val) 2335 return ret_val; 2336 } 2337 2338 /* When LPLU is enabled we should disable SmartSpeed */ 2339 ret_val = e1000_read_phy_reg(hw, 2340 IGP01E1000_PHY_PORT_CONFIG, &phy_data); 2341 if (ret_val) 2342 return ret_val; 2343 2344 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 2345 ret_val = e1000_write_phy_reg(hw, 2346 IGP01E1000_PHY_PORT_CONFIG, phy_data); 2347 if (ret_val) 2348 return ret_val; 2349 2350 } 2351 return E1000_SUCCESS; 2352 } 2353 2354 /******************************************************************** 2355 * Copper link setup for e1000_phy_igp series. 2356 * 2357 * hw - Struct containing variables accessed by shared code 2358 *********************************************************************/ 2359 static int32_t 2360 e1000_copper_link_igp_setup(struct e1000_hw *hw) 2361 { 2362 uint32_t led_ctrl; 2363 int32_t ret_val; 2364 uint16_t phy_data; 2365 2366 DEBUGFUNC(); 2367 2368 if (hw->phy_reset_disable) 2369 return E1000_SUCCESS; 2370 2371 ret_val = e1000_phy_reset(hw); 2372 if (ret_val) { 2373 DEBUGOUT("Error Resetting the PHY\n"); 2374 return ret_val; 2375 } 2376 2377 /* Wait 15ms for MAC to configure PHY from eeprom settings */ 2378 mdelay(15); 2379 if (hw->mac_type != e1000_ich8lan) { 2380 /* Configure activity LED after PHY reset */ 2381 led_ctrl = E1000_READ_REG(hw, LEDCTL); 2382 led_ctrl &= IGP_ACTIVITY_LED_MASK; 2383 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); 2384 E1000_WRITE_REG(hw, LEDCTL, led_ctrl); 2385 } 2386 2387 /* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */ 2388 if (hw->phy_type == e1000_phy_igp) { 2389 /* disable lplu d3 during driver init */ 2390 ret_val = e1000_set_d3_lplu_state(hw, FALSE); 2391 if (ret_val) { 2392 DEBUGOUT("Error Disabling LPLU D3\n"); 2393 return ret_val; 2394 } 2395 } 2396 2397 /* disable lplu d0 during driver init */ 2398 ret_val = e1000_set_d0_lplu_state(hw, FALSE); 2399 if (ret_val) { 2400 DEBUGOUT("Error Disabling LPLU D0\n"); 2401 return ret_val; 2402 } 2403 /* Configure mdi-mdix settings */ 2404 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); 2405 if (ret_val) 2406 return ret_val; 2407 2408 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { 2409 hw->dsp_config_state = e1000_dsp_config_disabled; 2410 /* Force MDI for earlier revs of the IGP PHY */ 2411 phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX 2412 | IGP01E1000_PSCR_FORCE_MDI_MDIX); 2413 hw->mdix = 1; 2414 2415 } else { 2416 hw->dsp_config_state = e1000_dsp_config_enabled; 2417 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; 2418 2419 switch (hw->mdix) { 2420 case 1: 2421 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; 2422 break; 2423 case 2: 2424 phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX; 2425 break; 2426 case 0: 2427 default: 2428 phy_data |= IGP01E1000_PSCR_AUTO_MDIX; 2429 break; 2430 } 2431 } 2432 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); 2433 if (ret_val) 2434 return ret_val; 2435 2436 /* set auto-master slave resolution settings */ 2437 if (hw->autoneg) { 2438 e1000_ms_type phy_ms_setting = hw->master_slave; 2439 2440 if (hw->ffe_config_state == e1000_ffe_config_active) 2441 hw->ffe_config_state = e1000_ffe_config_enabled; 2442 2443 if (hw->dsp_config_state == e1000_dsp_config_activated) 2444 hw->dsp_config_state = e1000_dsp_config_enabled; 2445 2446 /* when autonegotiation advertisment is only 1000Mbps then we 2447 * should disable SmartSpeed and enable Auto MasterSlave 2448 * resolution as hardware default. */ 2449 if (hw->autoneg_advertised == ADVERTISE_1000_FULL) { 2450 /* Disable SmartSpeed */ 2451 ret_val = e1000_read_phy_reg(hw, 2452 IGP01E1000_PHY_PORT_CONFIG, &phy_data); 2453 if (ret_val) 2454 return ret_val; 2455 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 2456 ret_val = e1000_write_phy_reg(hw, 2457 IGP01E1000_PHY_PORT_CONFIG, phy_data); 2458 if (ret_val) 2459 return ret_val; 2460 /* Set auto Master/Slave resolution process */ 2461 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, 2462 &phy_data); 2463 if (ret_val) 2464 return ret_val; 2465 phy_data &= ~CR_1000T_MS_ENABLE; 2466 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, 2467 phy_data); 2468 if (ret_val) 2469 return ret_val; 2470 } 2471 2472 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data); 2473 if (ret_val) 2474 return ret_val; 2475 2476 /* load defaults for future use */ 2477 hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ? 2478 ((phy_data & CR_1000T_MS_VALUE) ? 2479 e1000_ms_force_master : 2480 e1000_ms_force_slave) : 2481 e1000_ms_auto; 2482 2483 switch (phy_ms_setting) { 2484 case e1000_ms_force_master: 2485 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE); 2486 break; 2487 case e1000_ms_force_slave: 2488 phy_data |= CR_1000T_MS_ENABLE; 2489 phy_data &= ~(CR_1000T_MS_VALUE); 2490 break; 2491 case e1000_ms_auto: 2492 phy_data &= ~CR_1000T_MS_ENABLE; 2493 default: 2494 break; 2495 } 2496 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data); 2497 if (ret_val) 2498 return ret_val; 2499 } 2500 2501 return E1000_SUCCESS; 2502 } 2503 2504 /***************************************************************************** 2505 * This function checks the mode of the firmware. 2506 * 2507 * returns - TRUE when the mode is IAMT or FALSE. 2508 ****************************************************************************/ 2509 boolean_t 2510 e1000_check_mng_mode(struct e1000_hw *hw) 2511 { 2512 uint32_t fwsm; 2513 DEBUGFUNC(); 2514 2515 fwsm = E1000_READ_REG(hw, FWSM); 2516 2517 if (hw->mac_type == e1000_ich8lan) { 2518 if ((fwsm & E1000_FWSM_MODE_MASK) == 2519 (E1000_MNG_ICH_IAMT_MODE << E1000_FWSM_MODE_SHIFT)) 2520 return TRUE; 2521 } else if ((fwsm & E1000_FWSM_MODE_MASK) == 2522 (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT)) 2523 return TRUE; 2524 2525 return FALSE; 2526 } 2527 2528 static int32_t 2529 e1000_write_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t data) 2530 { 2531 uint32_t reg_val; 2532 uint16_t swfw; 2533 DEBUGFUNC(); 2534 2535 if ((hw->mac_type == e1000_80003es2lan) && 2536 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) { 2537 swfw = E1000_SWFW_PHY1_SM; 2538 } else { 2539 swfw = E1000_SWFW_PHY0_SM; 2540 } 2541 if (e1000_swfw_sync_acquire(hw, swfw)) 2542 return -E1000_ERR_SWFW_SYNC; 2543 2544 reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) 2545 & E1000_KUMCTRLSTA_OFFSET) | data; 2546 E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val); 2547 udelay(2); 2548 2549 return E1000_SUCCESS; 2550 } 2551 2552 static int32_t 2553 e1000_read_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *data) 2554 { 2555 uint32_t reg_val; 2556 uint16_t swfw; 2557 DEBUGFUNC(); 2558 2559 if ((hw->mac_type == e1000_80003es2lan) && 2560 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) { 2561 swfw = E1000_SWFW_PHY1_SM; 2562 } else { 2563 swfw = E1000_SWFW_PHY0_SM; 2564 } 2565 if (e1000_swfw_sync_acquire(hw, swfw)) 2566 return -E1000_ERR_SWFW_SYNC; 2567 2568 /* Write register address */ 2569 reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) & 2570 E1000_KUMCTRLSTA_OFFSET) | E1000_KUMCTRLSTA_REN; 2571 E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val); 2572 udelay(2); 2573 2574 /* Read the data returned */ 2575 reg_val = E1000_READ_REG(hw, KUMCTRLSTA); 2576 *data = (uint16_t)reg_val; 2577 2578 return E1000_SUCCESS; 2579 } 2580 2581 /******************************************************************** 2582 * Copper link setup for e1000_phy_gg82563 series. 2583 * 2584 * hw - Struct containing variables accessed by shared code 2585 *********************************************************************/ 2586 static int32_t 2587 e1000_copper_link_ggp_setup(struct e1000_hw *hw) 2588 { 2589 int32_t ret_val; 2590 uint16_t phy_data; 2591 uint32_t reg_data; 2592 2593 DEBUGFUNC(); 2594 2595 if (!hw->phy_reset_disable) { 2596 /* Enable CRS on TX for half-duplex operation. */ 2597 ret_val = e1000_read_phy_reg(hw, 2598 GG82563_PHY_MAC_SPEC_CTRL, &phy_data); 2599 if (ret_val) 2600 return ret_val; 2601 2602 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX; 2603 /* Use 25MHz for both link down and 1000BASE-T for Tx clock */ 2604 phy_data |= GG82563_MSCR_TX_CLK_1000MBPS_25MHZ; 2605 2606 ret_val = e1000_write_phy_reg(hw, 2607 GG82563_PHY_MAC_SPEC_CTRL, phy_data); 2608 if (ret_val) 2609 return ret_val; 2610 2611 /* Options: 2612 * MDI/MDI-X = 0 (default) 2613 * 0 - Auto for all speeds 2614 * 1 - MDI mode 2615 * 2 - MDI-X mode 2616 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) 2617 */ 2618 ret_val = e1000_read_phy_reg(hw, 2619 GG82563_PHY_SPEC_CTRL, &phy_data); 2620 if (ret_val) 2621 return ret_val; 2622 2623 phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK; 2624 2625 switch (hw->mdix) { 2626 case 1: 2627 phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDI; 2628 break; 2629 case 2: 2630 phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDIX; 2631 break; 2632 case 0: 2633 default: 2634 phy_data |= GG82563_PSCR_CROSSOVER_MODE_AUTO; 2635 break; 2636 } 2637 2638 /* Options: 2639 * disable_polarity_correction = 0 (default) 2640 * Automatic Correction for Reversed Cable Polarity 2641 * 0 - Disabled 2642 * 1 - Enabled 2643 */ 2644 phy_data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE; 2645 ret_val = e1000_write_phy_reg(hw, 2646 GG82563_PHY_SPEC_CTRL, phy_data); 2647 2648 if (ret_val) 2649 return ret_val; 2650 2651 /* SW Reset the PHY so all changes take effect */ 2652 ret_val = e1000_phy_reset(hw); 2653 if (ret_val) { 2654 DEBUGOUT("Error Resetting the PHY\n"); 2655 return ret_val; 2656 } 2657 } /* phy_reset_disable */ 2658 2659 if (hw->mac_type == e1000_80003es2lan) { 2660 /* Bypass RX and TX FIFO's */ 2661 ret_val = e1000_write_kmrn_reg(hw, 2662 E1000_KUMCTRLSTA_OFFSET_FIFO_CTRL, 2663 E1000_KUMCTRLSTA_FIFO_CTRL_RX_BYPASS 2664 | E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS); 2665 if (ret_val) 2666 return ret_val; 2667 2668 ret_val = e1000_read_phy_reg(hw, 2669 GG82563_PHY_SPEC_CTRL_2, &phy_data); 2670 if (ret_val) 2671 return ret_val; 2672 2673 phy_data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG; 2674 ret_val = e1000_write_phy_reg(hw, 2675 GG82563_PHY_SPEC_CTRL_2, phy_data); 2676 2677 if (ret_val) 2678 return ret_val; 2679 2680 reg_data = E1000_READ_REG(hw, CTRL_EXT); 2681 reg_data &= ~(E1000_CTRL_EXT_LINK_MODE_MASK); 2682 E1000_WRITE_REG(hw, CTRL_EXT, reg_data); 2683 2684 ret_val = e1000_read_phy_reg(hw, 2685 GG82563_PHY_PWR_MGMT_CTRL, &phy_data); 2686 if (ret_val) 2687 return ret_val; 2688 2689 /* Do not init these registers when the HW is in IAMT mode, since the 2690 * firmware will have already initialized them. We only initialize 2691 * them if the HW is not in IAMT mode. 2692 */ 2693 if (e1000_check_mng_mode(hw) == FALSE) { 2694 /* Enable Electrical Idle on the PHY */ 2695 phy_data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE; 2696 ret_val = e1000_write_phy_reg(hw, 2697 GG82563_PHY_PWR_MGMT_CTRL, phy_data); 2698 if (ret_val) 2699 return ret_val; 2700 2701 ret_val = e1000_read_phy_reg(hw, 2702 GG82563_PHY_KMRN_MODE_CTRL, &phy_data); 2703 if (ret_val) 2704 return ret_val; 2705 2706 phy_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; 2707 ret_val = e1000_write_phy_reg(hw, 2708 GG82563_PHY_KMRN_MODE_CTRL, phy_data); 2709 2710 if (ret_val) 2711 return ret_val; 2712 } 2713 2714 /* Workaround: Disable padding in Kumeran interface in the MAC 2715 * and in the PHY to avoid CRC errors. 2716 */ 2717 ret_val = e1000_read_phy_reg(hw, 2718 GG82563_PHY_INBAND_CTRL, &phy_data); 2719 if (ret_val) 2720 return ret_val; 2721 phy_data |= GG82563_ICR_DIS_PADDING; 2722 ret_val = e1000_write_phy_reg(hw, 2723 GG82563_PHY_INBAND_CTRL, phy_data); 2724 if (ret_val) 2725 return ret_val; 2726 } 2727 return E1000_SUCCESS; 2728 } 2729 2730 /******************************************************************** 2731 * Copper link setup for e1000_phy_m88 series. 2732 * 2733 * hw - Struct containing variables accessed by shared code 2734 *********************************************************************/ 2735 static int32_t 2736 e1000_copper_link_mgp_setup(struct e1000_hw *hw) 2737 { 2738 int32_t ret_val; 2739 uint16_t phy_data; 2740 2741 DEBUGFUNC(); 2742 2743 if (hw->phy_reset_disable) 2744 return E1000_SUCCESS; 2745 2746 /* Enable CRS on TX. This must be set for half-duplex operation. */ 2747 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 2748 if (ret_val) 2749 return ret_val; 2750 2751 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; 2752 2753 /* Options: 2754 * MDI/MDI-X = 0 (default) 2755 * 0 - Auto for all speeds 2756 * 1 - MDI mode 2757 * 2 - MDI-X mode 2758 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) 2759 */ 2760 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 2761 2762 switch (hw->mdix) { 2763 case 1: 2764 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; 2765 break; 2766 case 2: 2767 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; 2768 break; 2769 case 3: 2770 phy_data |= M88E1000_PSCR_AUTO_X_1000T; 2771 break; 2772 case 0: 2773 default: 2774 phy_data |= M88E1000_PSCR_AUTO_X_MODE; 2775 break; 2776 } 2777 2778 /* Options: 2779 * disable_polarity_correction = 0 (default) 2780 * Automatic Correction for Reversed Cable Polarity 2781 * 0 - Disabled 2782 * 1 - Enabled 2783 */ 2784 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; 2785 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 2786 if (ret_val) 2787 return ret_val; 2788 2789 if (hw->phy_revision < M88E1011_I_REV_4) { 2790 /* Force TX_CLK in the Extended PHY Specific Control Register 2791 * to 25MHz clock. 2792 */ 2793 ret_val = e1000_read_phy_reg(hw, 2794 M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); 2795 if (ret_val) 2796 return ret_val; 2797 2798 phy_data |= M88E1000_EPSCR_TX_CLK_25; 2799 2800 if ((hw->phy_revision == E1000_REVISION_2) && 2801 (hw->phy_id == M88E1111_I_PHY_ID)) { 2802 /* Vidalia Phy, set the downshift counter to 5x */ 2803 phy_data &= ~(M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK); 2804 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X; 2805 ret_val = e1000_write_phy_reg(hw, 2806 M88E1000_EXT_PHY_SPEC_CTRL, phy_data); 2807 if (ret_val) 2808 return ret_val; 2809 } else { 2810 /* Configure Master and Slave downshift values */ 2811 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 2812 | M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK); 2813 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X 2814 | M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X); 2815 ret_val = e1000_write_phy_reg(hw, 2816 M88E1000_EXT_PHY_SPEC_CTRL, phy_data); 2817 if (ret_val) 2818 return ret_val; 2819 } 2820 } 2821 2822 /* SW Reset the PHY so all changes take effect */ 2823 ret_val = e1000_phy_reset(hw); 2824 if (ret_val) { 2825 DEBUGOUT("Error Resetting the PHY\n"); 2826 return ret_val; 2827 } 2828 2829 return E1000_SUCCESS; 2830 } 2831 2832 /******************************************************************** 2833 * Setup auto-negotiation and flow control advertisements, 2834 * and then perform auto-negotiation. 2835 * 2836 * hw - Struct containing variables accessed by shared code 2837 *********************************************************************/ 2838 static int32_t 2839 e1000_copper_link_autoneg(struct e1000_hw *hw) 2840 { 2841 int32_t ret_val; 2842 uint16_t phy_data; 2843 2844 DEBUGFUNC(); 2845 2846 /* Perform some bounds checking on the hw->autoneg_advertised 2847 * parameter. If this variable is zero, then set it to the default. 2848 */ 2849 hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT; 2850 2851 /* If autoneg_advertised is zero, we assume it was not defaulted 2852 * by the calling code so we set to advertise full capability. 2853 */ 2854 if (hw->autoneg_advertised == 0) 2855 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT; 2856 2857 /* IFE phy only supports 10/100 */ 2858 if (hw->phy_type == e1000_phy_ife) 2859 hw->autoneg_advertised &= AUTONEG_ADVERTISE_10_100_ALL; 2860 2861 DEBUGOUT("Reconfiguring auto-neg advertisement params\n"); 2862 ret_val = e1000_phy_setup_autoneg(hw); 2863 if (ret_val) { 2864 DEBUGOUT("Error Setting up Auto-Negotiation\n"); 2865 return ret_val; 2866 } 2867 DEBUGOUT("Restarting Auto-Neg\n"); 2868 2869 /* Restart auto-negotiation by setting the Auto Neg Enable bit and 2870 * the Auto Neg Restart bit in the PHY control register. 2871 */ 2872 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data); 2873 if (ret_val) 2874 return ret_val; 2875 2876 phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); 2877 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data); 2878 if (ret_val) 2879 return ret_val; 2880 2881 /* Does the user want to wait for Auto-Neg to complete here, or 2882 * check at a later time (for example, callback routine). 2883 */ 2884 /* If we do not wait for autonegtation to complete I 2885 * do not see a valid link status. 2886 * wait_autoneg_complete = 1 . 2887 */ 2888 if (hw->wait_autoneg_complete) { 2889 ret_val = e1000_wait_autoneg(hw); 2890 if (ret_val) { 2891 DEBUGOUT("Error while waiting for autoneg" 2892 "to complete\n"); 2893 return ret_val; 2894 } 2895 } 2896 2897 hw->get_link_status = TRUE; 2898 2899 return E1000_SUCCESS; 2900 } 2901 2902 /****************************************************************************** 2903 * Config the MAC and the PHY after link is up. 2904 * 1) Set up the MAC to the current PHY speed/duplex 2905 * if we are on 82543. If we 2906 * are on newer silicon, we only need to configure 2907 * collision distance in the Transmit Control Register. 2908 * 2) Set up flow control on the MAC to that established with 2909 * the link partner. 2910 * 3) Config DSP to improve Gigabit link quality for some PHY revisions. 2911 * 2912 * hw - Struct containing variables accessed by shared code 2913 ******************************************************************************/ 2914 static int32_t 2915 e1000_copper_link_postconfig(struct e1000_hw *hw) 2916 { 2917 int32_t ret_val; 2918 DEBUGFUNC(); 2919 2920 if (hw->mac_type >= e1000_82544) { 2921 e1000_config_collision_dist(hw); 2922 } else { 2923 ret_val = e1000_config_mac_to_phy(hw); 2924 if (ret_val) { 2925 DEBUGOUT("Error configuring MAC to PHY settings\n"); 2926 return ret_val; 2927 } 2928 } 2929 ret_val = e1000_config_fc_after_link_up(hw); 2930 if (ret_val) { 2931 DEBUGOUT("Error Configuring Flow Control\n"); 2932 return ret_val; 2933 } 2934 return E1000_SUCCESS; 2935 } 2936 2937 /****************************************************************************** 2938 * Detects which PHY is present and setup the speed and duplex 2939 * 2940 * hw - Struct containing variables accessed by shared code 2941 ******************************************************************************/ 2942 static int 2943 e1000_setup_copper_link(struct eth_device *nic) 2944 { 2945 struct e1000_hw *hw = nic->priv; 2946 int32_t ret_val; 2947 uint16_t i; 2948 uint16_t phy_data; 2949 uint16_t reg_data; 2950 2951 DEBUGFUNC(); 2952 2953 switch (hw->mac_type) { 2954 case e1000_80003es2lan: 2955 case e1000_ich8lan: 2956 /* Set the mac to wait the maximum time between each 2957 * iteration and increase the max iterations when 2958 * polling the phy; this fixes erroneous timeouts at 10Mbps. */ 2959 ret_val = e1000_write_kmrn_reg(hw, 2960 GG82563_REG(0x34, 4), 0xFFFF); 2961 if (ret_val) 2962 return ret_val; 2963 ret_val = e1000_read_kmrn_reg(hw, 2964 GG82563_REG(0x34, 9), ®_data); 2965 if (ret_val) 2966 return ret_val; 2967 reg_data |= 0x3F; 2968 ret_val = e1000_write_kmrn_reg(hw, 2969 GG82563_REG(0x34, 9), reg_data); 2970 if (ret_val) 2971 return ret_val; 2972 default: 2973 break; 2974 } 2975 2976 /* Check if it is a valid PHY and set PHY mode if necessary. */ 2977 ret_val = e1000_copper_link_preconfig(hw); 2978 if (ret_val) 2979 return ret_val; 2980 switch (hw->mac_type) { 2981 case e1000_80003es2lan: 2982 /* Kumeran registers are written-only */ 2983 reg_data = 2984 E1000_KUMCTRLSTA_INB_CTRL_LINK_STATUS_TX_TIMEOUT_DEFAULT; 2985 reg_data |= E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING; 2986 ret_val = e1000_write_kmrn_reg(hw, 2987 E1000_KUMCTRLSTA_OFFSET_INB_CTRL, reg_data); 2988 if (ret_val) 2989 return ret_val; 2990 break; 2991 default: 2992 break; 2993 } 2994 2995 if (hw->phy_type == e1000_phy_igp || 2996 hw->phy_type == e1000_phy_igp_3 || 2997 hw->phy_type == e1000_phy_igp_2) { 2998 ret_val = e1000_copper_link_igp_setup(hw); 2999 if (ret_val) 3000 return ret_val; 3001 } else if (hw->phy_type == e1000_phy_m88) { 3002 ret_val = e1000_copper_link_mgp_setup(hw); 3003 if (ret_val) 3004 return ret_val; 3005 } else if (hw->phy_type == e1000_phy_gg82563) { 3006 ret_val = e1000_copper_link_ggp_setup(hw); 3007 if (ret_val) 3008 return ret_val; 3009 } 3010 3011 /* always auto */ 3012 /* Setup autoneg and flow control advertisement 3013 * and perform autonegotiation */ 3014 ret_val = e1000_copper_link_autoneg(hw); 3015 if (ret_val) 3016 return ret_val; 3017 3018 /* Check link status. Wait up to 100 microseconds for link to become 3019 * valid. 3020 */ 3021 for (i = 0; i < 10; i++) { 3022 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); 3023 if (ret_val) 3024 return ret_val; 3025 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); 3026 if (ret_val) 3027 return ret_val; 3028 3029 if (phy_data & MII_SR_LINK_STATUS) { 3030 /* Config the MAC and PHY after link is up */ 3031 ret_val = e1000_copper_link_postconfig(hw); 3032 if (ret_val) 3033 return ret_val; 3034 3035 DEBUGOUT("Valid link established!!!\n"); 3036 return E1000_SUCCESS; 3037 } 3038 udelay(10); 3039 } 3040 3041 DEBUGOUT("Unable to establish link!!!\n"); 3042 return E1000_SUCCESS; 3043 } 3044 3045 /****************************************************************************** 3046 * Configures PHY autoneg and flow control advertisement settings 3047 * 3048 * hw - Struct containing variables accessed by shared code 3049 ******************************************************************************/ 3050 int32_t 3051 e1000_phy_setup_autoneg(struct e1000_hw *hw) 3052 { 3053 int32_t ret_val; 3054 uint16_t mii_autoneg_adv_reg; 3055 uint16_t mii_1000t_ctrl_reg; 3056 3057 DEBUGFUNC(); 3058 3059 /* Read the MII Auto-Neg Advertisement Register (Address 4). */ 3060 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg); 3061 if (ret_val) 3062 return ret_val; 3063 3064 if (hw->phy_type != e1000_phy_ife) { 3065 /* Read the MII 1000Base-T Control Register (Address 9). */ 3066 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, 3067 &mii_1000t_ctrl_reg); 3068 if (ret_val) 3069 return ret_val; 3070 } else 3071 mii_1000t_ctrl_reg = 0; 3072 3073 /* Need to parse both autoneg_advertised and fc and set up 3074 * the appropriate PHY registers. First we will parse for 3075 * autoneg_advertised software override. Since we can advertise 3076 * a plethora of combinations, we need to check each bit 3077 * individually. 3078 */ 3079 3080 /* First we clear all the 10/100 mb speed bits in the Auto-Neg 3081 * Advertisement Register (Address 4) and the 1000 mb speed bits in 3082 * the 1000Base-T Control Register (Address 9). 3083 */ 3084 mii_autoneg_adv_reg &= ~REG4_SPEED_MASK; 3085 mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK; 3086 3087 DEBUGOUT("autoneg_advertised %x\n", hw->autoneg_advertised); 3088 3089 /* Do we want to advertise 10 Mb Half Duplex? */ 3090 if (hw->autoneg_advertised & ADVERTISE_10_HALF) { 3091 DEBUGOUT("Advertise 10mb Half duplex\n"); 3092 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS; 3093 } 3094 3095 /* Do we want to advertise 10 Mb Full Duplex? */ 3096 if (hw->autoneg_advertised & ADVERTISE_10_FULL) { 3097 DEBUGOUT("Advertise 10mb Full duplex\n"); 3098 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS; 3099 } 3100 3101 /* Do we want to advertise 100 Mb Half Duplex? */ 3102 if (hw->autoneg_advertised & ADVERTISE_100_HALF) { 3103 DEBUGOUT("Advertise 100mb Half duplex\n"); 3104 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS; 3105 } 3106 3107 /* Do we want to advertise 100 Mb Full Duplex? */ 3108 if (hw->autoneg_advertised & ADVERTISE_100_FULL) { 3109 DEBUGOUT("Advertise 100mb Full duplex\n"); 3110 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS; 3111 } 3112 3113 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */ 3114 if (hw->autoneg_advertised & ADVERTISE_1000_HALF) { 3115 DEBUGOUT 3116 ("Advertise 1000mb Half duplex requested, request denied!\n"); 3117 } 3118 3119 /* Do we want to advertise 1000 Mb Full Duplex? */ 3120 if (hw->autoneg_advertised & ADVERTISE_1000_FULL) { 3121 DEBUGOUT("Advertise 1000mb Full duplex\n"); 3122 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS; 3123 } 3124 3125 /* Check for a software override of the flow control settings, and 3126 * setup the PHY advertisement registers accordingly. If 3127 * auto-negotiation is enabled, then software will have to set the 3128 * "PAUSE" bits to the correct value in the Auto-Negotiation 3129 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation. 3130 * 3131 * The possible values of the "fc" parameter are: 3132 * 0: Flow control is completely disabled 3133 * 1: Rx flow control is enabled (we can receive pause frames 3134 * but not send pause frames). 3135 * 2: Tx flow control is enabled (we can send pause frames 3136 * but we do not support receiving pause frames). 3137 * 3: Both Rx and TX flow control (symmetric) are enabled. 3138 * other: No software override. The flow control configuration 3139 * in the EEPROM is used. 3140 */ 3141 switch (hw->fc) { 3142 case e1000_fc_none: /* 0 */ 3143 /* Flow control (RX & TX) is completely disabled by a 3144 * software over-ride. 3145 */ 3146 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 3147 break; 3148 case e1000_fc_rx_pause: /* 1 */ 3149 /* RX Flow control is enabled, and TX Flow control is 3150 * disabled, by a software over-ride. 3151 */ 3152 /* Since there really isn't a way to advertise that we are 3153 * capable of RX Pause ONLY, we will advertise that we 3154 * support both symmetric and asymmetric RX PAUSE. Later 3155 * (in e1000_config_fc_after_link_up) we will disable the 3156 *hw's ability to send PAUSE frames. 3157 */ 3158 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 3159 break; 3160 case e1000_fc_tx_pause: /* 2 */ 3161 /* TX Flow control is enabled, and RX Flow control is 3162 * disabled, by a software over-ride. 3163 */ 3164 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR; 3165 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE; 3166 break; 3167 case e1000_fc_full: /* 3 */ 3168 /* Flow control (both RX and TX) is enabled by a software 3169 * over-ride. 3170 */ 3171 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 3172 break; 3173 default: 3174 DEBUGOUT("Flow control param set incorrectly\n"); 3175 return -E1000_ERR_CONFIG; 3176 } 3177 3178 ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg); 3179 if (ret_val) 3180 return ret_val; 3181 3182 DEBUGOUT("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); 3183 3184 if (hw->phy_type != e1000_phy_ife) { 3185 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, 3186 mii_1000t_ctrl_reg); 3187 if (ret_val) 3188 return ret_val; 3189 } 3190 3191 return E1000_SUCCESS; 3192 } 3193 3194 /****************************************************************************** 3195 * Sets the collision distance in the Transmit Control register 3196 * 3197 * hw - Struct containing variables accessed by shared code 3198 * 3199 * Link should have been established previously. Reads the speed and duplex 3200 * information from the Device Status register. 3201 ******************************************************************************/ 3202 static void 3203 e1000_config_collision_dist(struct e1000_hw *hw) 3204 { 3205 uint32_t tctl, coll_dist; 3206 3207 DEBUGFUNC(); 3208 3209 if (hw->mac_type < e1000_82543) 3210 coll_dist = E1000_COLLISION_DISTANCE_82542; 3211 else 3212 coll_dist = E1000_COLLISION_DISTANCE; 3213 3214 tctl = E1000_READ_REG(hw, TCTL); 3215 3216 tctl &= ~E1000_TCTL_COLD; 3217 tctl |= coll_dist << E1000_COLD_SHIFT; 3218 3219 E1000_WRITE_REG(hw, TCTL, tctl); 3220 E1000_WRITE_FLUSH(hw); 3221 } 3222 3223 /****************************************************************************** 3224 * Sets MAC speed and duplex settings to reflect the those in the PHY 3225 * 3226 * hw - Struct containing variables accessed by shared code 3227 * mii_reg - data to write to the MII control register 3228 * 3229 * The contents of the PHY register containing the needed information need to 3230 * be passed in. 3231 ******************************************************************************/ 3232 static int 3233 e1000_config_mac_to_phy(struct e1000_hw *hw) 3234 { 3235 uint32_t ctrl; 3236 uint16_t phy_data; 3237 3238 DEBUGFUNC(); 3239 3240 /* Read the Device Control Register and set the bits to Force Speed 3241 * and Duplex. 3242 */ 3243 ctrl = E1000_READ_REG(hw, CTRL); 3244 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 3245 ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS); 3246 3247 /* Set up duplex in the Device Control and Transmit Control 3248 * registers depending on negotiated values. 3249 */ 3250 if (e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data) < 0) { 3251 DEBUGOUT("PHY Read Error\n"); 3252 return -E1000_ERR_PHY; 3253 } 3254 if (phy_data & M88E1000_PSSR_DPLX) 3255 ctrl |= E1000_CTRL_FD; 3256 else 3257 ctrl &= ~E1000_CTRL_FD; 3258 3259 e1000_config_collision_dist(hw); 3260 3261 /* Set up speed in the Device Control register depending on 3262 * negotiated values. 3263 */ 3264 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) 3265 ctrl |= E1000_CTRL_SPD_1000; 3266 else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS) 3267 ctrl |= E1000_CTRL_SPD_100; 3268 /* Write the configured values back to the Device Control Reg. */ 3269 E1000_WRITE_REG(hw, CTRL, ctrl); 3270 return 0; 3271 } 3272 3273 /****************************************************************************** 3274 * Forces the MAC's flow control settings. 3275 * 3276 * hw - Struct containing variables accessed by shared code 3277 * 3278 * Sets the TFCE and RFCE bits in the device control register to reflect 3279 * the adapter settings. TFCE and RFCE need to be explicitly set by 3280 * software when a Copper PHY is used because autonegotiation is managed 3281 * by the PHY rather than the MAC. Software must also configure these 3282 * bits when link is forced on a fiber connection. 3283 *****************************************************************************/ 3284 static int 3285 e1000_force_mac_fc(struct e1000_hw *hw) 3286 { 3287 uint32_t ctrl; 3288 3289 DEBUGFUNC(); 3290 3291 /* Get the current configuration of the Device Control Register */ 3292 ctrl = E1000_READ_REG(hw, CTRL); 3293 3294 /* Because we didn't get link via the internal auto-negotiation 3295 * mechanism (we either forced link or we got link via PHY 3296 * auto-neg), we have to manually enable/disable transmit an 3297 * receive flow control. 3298 * 3299 * The "Case" statement below enables/disable flow control 3300 * according to the "hw->fc" parameter. 3301 * 3302 * The possible values of the "fc" parameter are: 3303 * 0: Flow control is completely disabled 3304 * 1: Rx flow control is enabled (we can receive pause 3305 * frames but not send pause frames). 3306 * 2: Tx flow control is enabled (we can send pause frames 3307 * frames but we do not receive pause frames). 3308 * 3: Both Rx and TX flow control (symmetric) is enabled. 3309 * other: No other values should be possible at this point. 3310 */ 3311 3312 switch (hw->fc) { 3313 case e1000_fc_none: 3314 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE)); 3315 break; 3316 case e1000_fc_rx_pause: 3317 ctrl &= (~E1000_CTRL_TFCE); 3318 ctrl |= E1000_CTRL_RFCE; 3319 break; 3320 case e1000_fc_tx_pause: 3321 ctrl &= (~E1000_CTRL_RFCE); 3322 ctrl |= E1000_CTRL_TFCE; 3323 break; 3324 case e1000_fc_full: 3325 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE); 3326 break; 3327 default: 3328 DEBUGOUT("Flow control param set incorrectly\n"); 3329 return -E1000_ERR_CONFIG; 3330 } 3331 3332 /* Disable TX Flow Control for 82542 (rev 2.0) */ 3333 if (hw->mac_type == e1000_82542_rev2_0) 3334 ctrl &= (~E1000_CTRL_TFCE); 3335 3336 E1000_WRITE_REG(hw, CTRL, ctrl); 3337 return 0; 3338 } 3339 3340 /****************************************************************************** 3341 * Configures flow control settings after link is established 3342 * 3343 * hw - Struct containing variables accessed by shared code 3344 * 3345 * Should be called immediately after a valid link has been established. 3346 * Forces MAC flow control settings if link was forced. When in MII/GMII mode 3347 * and autonegotiation is enabled, the MAC flow control settings will be set 3348 * based on the flow control negotiated by the PHY. In TBI mode, the TFCE 3349 * and RFCE bits will be automaticaly set to the negotiated flow control mode. 3350 *****************************************************************************/ 3351 static int32_t 3352 e1000_config_fc_after_link_up(struct e1000_hw *hw) 3353 { 3354 int32_t ret_val; 3355 uint16_t mii_status_reg; 3356 uint16_t mii_nway_adv_reg; 3357 uint16_t mii_nway_lp_ability_reg; 3358 uint16_t speed; 3359 uint16_t duplex; 3360 3361 DEBUGFUNC(); 3362 3363 /* Check for the case where we have fiber media and auto-neg failed 3364 * so we had to force link. In this case, we need to force the 3365 * configuration of the MAC to match the "fc" parameter. 3366 */ 3367 if (((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed)) 3368 || ((hw->media_type == e1000_media_type_internal_serdes) 3369 && (hw->autoneg_failed)) 3370 || ((hw->media_type == e1000_media_type_copper) 3371 && (!hw->autoneg))) { 3372 ret_val = e1000_force_mac_fc(hw); 3373 if (ret_val < 0) { 3374 DEBUGOUT("Error forcing flow control settings\n"); 3375 return ret_val; 3376 } 3377 } 3378 3379 /* Check for the case where we have copper media and auto-neg is 3380 * enabled. In this case, we need to check and see if Auto-Neg 3381 * has completed, and if so, how the PHY and link partner has 3382 * flow control configured. 3383 */ 3384 if (hw->media_type == e1000_media_type_copper) { 3385 /* Read the MII Status Register and check to see if AutoNeg 3386 * has completed. We read this twice because this reg has 3387 * some "sticky" (latched) bits. 3388 */ 3389 if (e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) { 3390 DEBUGOUT("PHY Read Error \n"); 3391 return -E1000_ERR_PHY; 3392 } 3393 if (e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) { 3394 DEBUGOUT("PHY Read Error \n"); 3395 return -E1000_ERR_PHY; 3396 } 3397 3398 if (mii_status_reg & MII_SR_AUTONEG_COMPLETE) { 3399 /* The AutoNeg process has completed, so we now need to 3400 * read both the Auto Negotiation Advertisement Register 3401 * (Address 4) and the Auto_Negotiation Base Page Ability 3402 * Register (Address 5) to determine how flow control was 3403 * negotiated. 3404 */ 3405 if (e1000_read_phy_reg 3406 (hw, PHY_AUTONEG_ADV, &mii_nway_adv_reg) < 0) { 3407 DEBUGOUT("PHY Read Error\n"); 3408 return -E1000_ERR_PHY; 3409 } 3410 if (e1000_read_phy_reg 3411 (hw, PHY_LP_ABILITY, 3412 &mii_nway_lp_ability_reg) < 0) { 3413 DEBUGOUT("PHY Read Error\n"); 3414 return -E1000_ERR_PHY; 3415 } 3416 3417 /* Two bits in the Auto Negotiation Advertisement Register 3418 * (Address 4) and two bits in the Auto Negotiation Base 3419 * Page Ability Register (Address 5) determine flow control 3420 * for both the PHY and the link partner. The following 3421 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25, 3422 * 1999, describes these PAUSE resolution bits and how flow 3423 * control is determined based upon these settings. 3424 * NOTE: DC = Don't Care 3425 * 3426 * LOCAL DEVICE | LINK PARTNER 3427 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution 3428 *-------|---------|-------|---------|-------------------- 3429 * 0 | 0 | DC | DC | e1000_fc_none 3430 * 0 | 1 | 0 | DC | e1000_fc_none 3431 * 0 | 1 | 1 | 0 | e1000_fc_none 3432 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 3433 * 1 | 0 | 0 | DC | e1000_fc_none 3434 * 1 | DC | 1 | DC | e1000_fc_full 3435 * 1 | 1 | 0 | 0 | e1000_fc_none 3436 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 3437 * 3438 */ 3439 /* Are both PAUSE bits set to 1? If so, this implies 3440 * Symmetric Flow Control is enabled at both ends. The 3441 * ASM_DIR bits are irrelevant per the spec. 3442 * 3443 * For Symmetric Flow Control: 3444 * 3445 * LOCAL DEVICE | LINK PARTNER 3446 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 3447 *-------|---------|-------|---------|-------------------- 3448 * 1 | DC | 1 | DC | e1000_fc_full 3449 * 3450 */ 3451 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 3452 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) { 3453 /* Now we need to check if the user selected RX ONLY 3454 * of pause frames. In this case, we had to advertise 3455 * FULL flow control because we could not advertise RX 3456 * ONLY. Hence, we must now check to see if we need to 3457 * turn OFF the TRANSMISSION of PAUSE frames. 3458 */ 3459 if (hw->original_fc == e1000_fc_full) { 3460 hw->fc = e1000_fc_full; 3461 DEBUGOUT("Flow Control = FULL.\r\n"); 3462 } else { 3463 hw->fc = e1000_fc_rx_pause; 3464 DEBUGOUT 3465 ("Flow Control = RX PAUSE frames only.\r\n"); 3466 } 3467 } 3468 /* For receiving PAUSE frames ONLY. 3469 * 3470 * LOCAL DEVICE | LINK PARTNER 3471 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 3472 *-------|---------|-------|---------|-------------------- 3473 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 3474 * 3475 */ 3476 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) && 3477 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 3478 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 3479 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) 3480 { 3481 hw->fc = e1000_fc_tx_pause; 3482 DEBUGOUT 3483 ("Flow Control = TX PAUSE frames only.\r\n"); 3484 } 3485 /* For transmitting PAUSE frames ONLY. 3486 * 3487 * LOCAL DEVICE | LINK PARTNER 3488 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 3489 *-------|---------|-------|---------|-------------------- 3490 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 3491 * 3492 */ 3493 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 3494 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 3495 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 3496 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) 3497 { 3498 hw->fc = e1000_fc_rx_pause; 3499 DEBUGOUT 3500 ("Flow Control = RX PAUSE frames only.\r\n"); 3501 } 3502 /* Per the IEEE spec, at this point flow control should be 3503 * disabled. However, we want to consider that we could 3504 * be connected to a legacy switch that doesn't advertise 3505 * desired flow control, but can be forced on the link 3506 * partner. So if we advertised no flow control, that is 3507 * what we will resolve to. If we advertised some kind of 3508 * receive capability (Rx Pause Only or Full Flow Control) 3509 * and the link partner advertised none, we will configure 3510 * ourselves to enable Rx Flow Control only. We can do 3511 * this safely for two reasons: If the link partner really 3512 * didn't want flow control enabled, and we enable Rx, no 3513 * harm done since we won't be receiving any PAUSE frames 3514 * anyway. If the intent on the link partner was to have 3515 * flow control enabled, then by us enabling RX only, we 3516 * can at least receive pause frames and process them. 3517 * This is a good idea because in most cases, since we are 3518 * predominantly a server NIC, more times than not we will 3519 * be asked to delay transmission of packets than asking 3520 * our link partner to pause transmission of frames. 3521 */ 3522 else if (hw->original_fc == e1000_fc_none || 3523 hw->original_fc == e1000_fc_tx_pause) { 3524 hw->fc = e1000_fc_none; 3525 DEBUGOUT("Flow Control = NONE.\r\n"); 3526 } else { 3527 hw->fc = e1000_fc_rx_pause; 3528 DEBUGOUT 3529 ("Flow Control = RX PAUSE frames only.\r\n"); 3530 } 3531 3532 /* Now we need to do one last check... If we auto- 3533 * negotiated to HALF DUPLEX, flow control should not be 3534 * enabled per IEEE 802.3 spec. 3535 */ 3536 e1000_get_speed_and_duplex(hw, &speed, &duplex); 3537 3538 if (duplex == HALF_DUPLEX) 3539 hw->fc = e1000_fc_none; 3540 3541 /* Now we call a subroutine to actually force the MAC 3542 * controller to use the correct flow control settings. 3543 */ 3544 ret_val = e1000_force_mac_fc(hw); 3545 if (ret_val < 0) { 3546 DEBUGOUT 3547 ("Error forcing flow control settings\n"); 3548 return ret_val; 3549 } 3550 } else { 3551 DEBUGOUT 3552 ("Copper PHY and Auto Neg has not completed.\r\n"); 3553 } 3554 } 3555 return E1000_SUCCESS; 3556 } 3557 3558 /****************************************************************************** 3559 * Checks to see if the link status of the hardware has changed. 3560 * 3561 * hw - Struct containing variables accessed by shared code 3562 * 3563 * Called by any function that needs to check the link status of the adapter. 3564 *****************************************************************************/ 3565 static int 3566 e1000_check_for_link(struct eth_device *nic) 3567 { 3568 struct e1000_hw *hw = nic->priv; 3569 uint32_t rxcw; 3570 uint32_t ctrl; 3571 uint32_t status; 3572 uint32_t rctl; 3573 uint32_t signal; 3574 int32_t ret_val; 3575 uint16_t phy_data; 3576 uint16_t lp_capability; 3577 3578 DEBUGFUNC(); 3579 3580 /* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be 3581 * set when the optics detect a signal. On older adapters, it will be 3582 * cleared when there is a signal 3583 */ 3584 ctrl = E1000_READ_REG(hw, CTRL); 3585 if ((hw->mac_type > e1000_82544) && !(ctrl & E1000_CTRL_ILOS)) 3586 signal = E1000_CTRL_SWDPIN1; 3587 else 3588 signal = 0; 3589 3590 status = E1000_READ_REG(hw, STATUS); 3591 rxcw = E1000_READ_REG(hw, RXCW); 3592 DEBUGOUT("ctrl: %#08x status %#08x rxcw %#08x\n", ctrl, status, rxcw); 3593 3594 /* If we have a copper PHY then we only want to go out to the PHY 3595 * registers to see if Auto-Neg has completed and/or if our link 3596 * status has changed. The get_link_status flag will be set if we 3597 * receive a Link Status Change interrupt or we have Rx Sequence 3598 * Errors. 3599 */ 3600 if ((hw->media_type == e1000_media_type_copper) && hw->get_link_status) { 3601 /* First we want to see if the MII Status Register reports 3602 * link. If so, then we want to get the current speed/duplex 3603 * of the PHY. 3604 * Read the register twice since the link bit is sticky. 3605 */ 3606 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) { 3607 DEBUGOUT("PHY Read Error\n"); 3608 return -E1000_ERR_PHY; 3609 } 3610 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) { 3611 DEBUGOUT("PHY Read Error\n"); 3612 return -E1000_ERR_PHY; 3613 } 3614 3615 if (phy_data & MII_SR_LINK_STATUS) { 3616 hw->get_link_status = FALSE; 3617 } else { 3618 /* No link detected */ 3619 return -E1000_ERR_NOLINK; 3620 } 3621 3622 /* We have a M88E1000 PHY and Auto-Neg is enabled. If we 3623 * have Si on board that is 82544 or newer, Auto 3624 * Speed Detection takes care of MAC speed/duplex 3625 * configuration. So we only need to configure Collision 3626 * Distance in the MAC. Otherwise, we need to force 3627 * speed/duplex on the MAC to the current PHY speed/duplex 3628 * settings. 3629 */ 3630 if (hw->mac_type >= e1000_82544) 3631 e1000_config_collision_dist(hw); 3632 else { 3633 ret_val = e1000_config_mac_to_phy(hw); 3634 if (ret_val < 0) { 3635 DEBUGOUT 3636 ("Error configuring MAC to PHY settings\n"); 3637 return ret_val; 3638 } 3639 } 3640 3641 /* Configure Flow Control now that Auto-Neg has completed. First, we 3642 * need to restore the desired flow control settings because we may 3643 * have had to re-autoneg with a different link partner. 3644 */ 3645 ret_val = e1000_config_fc_after_link_up(hw); 3646 if (ret_val < 0) { 3647 DEBUGOUT("Error configuring flow control\n"); 3648 return ret_val; 3649 } 3650 3651 /* At this point we know that we are on copper and we have 3652 * auto-negotiated link. These are conditions for checking the link 3653 * parter capability register. We use the link partner capability to 3654 * determine if TBI Compatibility needs to be turned on or off. If 3655 * the link partner advertises any speed in addition to Gigabit, then 3656 * we assume that they are GMII-based, and TBI compatibility is not 3657 * needed. If no other speeds are advertised, we assume the link 3658 * partner is TBI-based, and we turn on TBI Compatibility. 3659 */ 3660 if (hw->tbi_compatibility_en) { 3661 if (e1000_read_phy_reg 3662 (hw, PHY_LP_ABILITY, &lp_capability) < 0) { 3663 DEBUGOUT("PHY Read Error\n"); 3664 return -E1000_ERR_PHY; 3665 } 3666 if (lp_capability & (NWAY_LPAR_10T_HD_CAPS | 3667 NWAY_LPAR_10T_FD_CAPS | 3668 NWAY_LPAR_100TX_HD_CAPS | 3669 NWAY_LPAR_100TX_FD_CAPS | 3670 NWAY_LPAR_100T4_CAPS)) { 3671 /* If our link partner advertises anything in addition to 3672 * gigabit, we do not need to enable TBI compatibility. 3673 */ 3674 if (hw->tbi_compatibility_on) { 3675 /* If we previously were in the mode, turn it off. */ 3676 rctl = E1000_READ_REG(hw, RCTL); 3677 rctl &= ~E1000_RCTL_SBP; 3678 E1000_WRITE_REG(hw, RCTL, rctl); 3679 hw->tbi_compatibility_on = FALSE; 3680 } 3681 } else { 3682 /* If TBI compatibility is was previously off, turn it on. For 3683 * compatibility with a TBI link partner, we will store bad 3684 * packets. Some frames have an additional byte on the end and 3685 * will look like CRC errors to to the hardware. 3686 */ 3687 if (!hw->tbi_compatibility_on) { 3688 hw->tbi_compatibility_on = TRUE; 3689 rctl = E1000_READ_REG(hw, RCTL); 3690 rctl |= E1000_RCTL_SBP; 3691 E1000_WRITE_REG(hw, RCTL, rctl); 3692 } 3693 } 3694 } 3695 } 3696 /* If we don't have link (auto-negotiation failed or link partner cannot 3697 * auto-negotiate), the cable is plugged in (we have signal), and our 3698 * link partner is not trying to auto-negotiate with us (we are receiving 3699 * idles or data), we need to force link up. We also need to give 3700 * auto-negotiation time to complete, in case the cable was just plugged 3701 * in. The autoneg_failed flag does this. 3702 */ 3703 else if ((hw->media_type == e1000_media_type_fiber) && 3704 (!(status & E1000_STATUS_LU)) && 3705 ((ctrl & E1000_CTRL_SWDPIN1) == signal) && 3706 (!(rxcw & E1000_RXCW_C))) { 3707 if (hw->autoneg_failed == 0) { 3708 hw->autoneg_failed = 1; 3709 return 0; 3710 } 3711 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\r\n"); 3712 3713 /* Disable auto-negotiation in the TXCW register */ 3714 E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE)); 3715 3716 /* Force link-up and also force full-duplex. */ 3717 ctrl = E1000_READ_REG(hw, CTRL); 3718 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 3719 E1000_WRITE_REG(hw, CTRL, ctrl); 3720 3721 /* Configure Flow Control after forcing link up. */ 3722 ret_val = e1000_config_fc_after_link_up(hw); 3723 if (ret_val < 0) { 3724 DEBUGOUT("Error configuring flow control\n"); 3725 return ret_val; 3726 } 3727 } 3728 /* If we are forcing link and we are receiving /C/ ordered sets, re-enable 3729 * auto-negotiation in the TXCW register and disable forced link in the 3730 * Device Control register in an attempt to auto-negotiate with our link 3731 * partner. 3732 */ 3733 else if ((hw->media_type == e1000_media_type_fiber) && 3734 (ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { 3735 DEBUGOUT 3736 ("RXing /C/, enable AutoNeg and stop forcing link.\r\n"); 3737 E1000_WRITE_REG(hw, TXCW, hw->txcw); 3738 E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU)); 3739 } 3740 return 0; 3741 } 3742 3743 /****************************************************************************** 3744 * Configure the MAC-to-PHY interface for 10/100Mbps 3745 * 3746 * hw - Struct containing variables accessed by shared code 3747 ******************************************************************************/ 3748 static int32_t 3749 e1000_configure_kmrn_for_10_100(struct e1000_hw *hw, uint16_t duplex) 3750 { 3751 int32_t ret_val = E1000_SUCCESS; 3752 uint32_t tipg; 3753 uint16_t reg_data; 3754 3755 DEBUGFUNC(); 3756 3757 reg_data = E1000_KUMCTRLSTA_HD_CTRL_10_100_DEFAULT; 3758 ret_val = e1000_write_kmrn_reg(hw, 3759 E1000_KUMCTRLSTA_OFFSET_HD_CTRL, reg_data); 3760 if (ret_val) 3761 return ret_val; 3762 3763 /* Configure Transmit Inter-Packet Gap */ 3764 tipg = E1000_READ_REG(hw, TIPG); 3765 tipg &= ~E1000_TIPG_IPGT_MASK; 3766 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_10_100; 3767 E1000_WRITE_REG(hw, TIPG, tipg); 3768 3769 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data); 3770 3771 if (ret_val) 3772 return ret_val; 3773 3774 if (duplex == HALF_DUPLEX) 3775 reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER; 3776 else 3777 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; 3778 3779 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data); 3780 3781 return ret_val; 3782 } 3783 3784 static int32_t 3785 e1000_configure_kmrn_for_1000(struct e1000_hw *hw) 3786 { 3787 int32_t ret_val = E1000_SUCCESS; 3788 uint16_t reg_data; 3789 uint32_t tipg; 3790 3791 DEBUGFUNC(); 3792 3793 reg_data = E1000_KUMCTRLSTA_HD_CTRL_1000_DEFAULT; 3794 ret_val = e1000_write_kmrn_reg(hw, 3795 E1000_KUMCTRLSTA_OFFSET_HD_CTRL, reg_data); 3796 if (ret_val) 3797 return ret_val; 3798 3799 /* Configure Transmit Inter-Packet Gap */ 3800 tipg = E1000_READ_REG(hw, TIPG); 3801 tipg &= ~E1000_TIPG_IPGT_MASK; 3802 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000; 3803 E1000_WRITE_REG(hw, TIPG, tipg); 3804 3805 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data); 3806 3807 if (ret_val) 3808 return ret_val; 3809 3810 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; 3811 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data); 3812 3813 return ret_val; 3814 } 3815 3816 /****************************************************************************** 3817 * Detects the current speed and duplex settings of the hardware. 3818 * 3819 * hw - Struct containing variables accessed by shared code 3820 * speed - Speed of the connection 3821 * duplex - Duplex setting of the connection 3822 *****************************************************************************/ 3823 static int 3824 e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t *speed, 3825 uint16_t *duplex) 3826 { 3827 uint32_t status; 3828 int32_t ret_val; 3829 uint16_t phy_data; 3830 3831 DEBUGFUNC(); 3832 3833 if (hw->mac_type >= e1000_82543) { 3834 status = E1000_READ_REG(hw, STATUS); 3835 if (status & E1000_STATUS_SPEED_1000) { 3836 *speed = SPEED_1000; 3837 DEBUGOUT("1000 Mbs, "); 3838 } else if (status & E1000_STATUS_SPEED_100) { 3839 *speed = SPEED_100; 3840 DEBUGOUT("100 Mbs, "); 3841 } else { 3842 *speed = SPEED_10; 3843 DEBUGOUT("10 Mbs, "); 3844 } 3845 3846 if (status & E1000_STATUS_FD) { 3847 *duplex = FULL_DUPLEX; 3848 DEBUGOUT("Full Duplex\r\n"); 3849 } else { 3850 *duplex = HALF_DUPLEX; 3851 DEBUGOUT(" Half Duplex\r\n"); 3852 } 3853 } else { 3854 DEBUGOUT("1000 Mbs, Full Duplex\r\n"); 3855 *speed = SPEED_1000; 3856 *duplex = FULL_DUPLEX; 3857 } 3858 3859 /* IGP01 PHY may advertise full duplex operation after speed downgrade 3860 * even if it is operating at half duplex. Here we set the duplex 3861 * settings to match the duplex in the link partner's capabilities. 3862 */ 3863 if (hw->phy_type == e1000_phy_igp && hw->speed_downgraded) { 3864 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data); 3865 if (ret_val) 3866 return ret_val; 3867 3868 if (!(phy_data & NWAY_ER_LP_NWAY_CAPS)) 3869 *duplex = HALF_DUPLEX; 3870 else { 3871 ret_val = e1000_read_phy_reg(hw, 3872 PHY_LP_ABILITY, &phy_data); 3873 if (ret_val) 3874 return ret_val; 3875 if ((*speed == SPEED_100 && 3876 !(phy_data & NWAY_LPAR_100TX_FD_CAPS)) 3877 || (*speed == SPEED_10 3878 && !(phy_data & NWAY_LPAR_10T_FD_CAPS))) 3879 *duplex = HALF_DUPLEX; 3880 } 3881 } 3882 3883 if ((hw->mac_type == e1000_80003es2lan) && 3884 (hw->media_type == e1000_media_type_copper)) { 3885 if (*speed == SPEED_1000) 3886 ret_val = e1000_configure_kmrn_for_1000(hw); 3887 else 3888 ret_val = e1000_configure_kmrn_for_10_100(hw, *duplex); 3889 if (ret_val) 3890 return ret_val; 3891 } 3892 return E1000_SUCCESS; 3893 } 3894 3895 /****************************************************************************** 3896 * Blocks until autoneg completes or times out (~4.5 seconds) 3897 * 3898 * hw - Struct containing variables accessed by shared code 3899 ******************************************************************************/ 3900 static int 3901 e1000_wait_autoneg(struct e1000_hw *hw) 3902 { 3903 uint16_t i; 3904 uint16_t phy_data; 3905 3906 DEBUGFUNC(); 3907 DEBUGOUT("Waiting for Auto-Neg to complete.\n"); 3908 3909 /* We will wait for autoneg to complete or 4.5 seconds to expire. */ 3910 for (i = PHY_AUTO_NEG_TIME; i > 0; i--) { 3911 /* Read the MII Status Register and wait for Auto-Neg 3912 * Complete bit to be set. 3913 */ 3914 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) { 3915 DEBUGOUT("PHY Read Error\n"); 3916 return -E1000_ERR_PHY; 3917 } 3918 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) { 3919 DEBUGOUT("PHY Read Error\n"); 3920 return -E1000_ERR_PHY; 3921 } 3922 if (phy_data & MII_SR_AUTONEG_COMPLETE) { 3923 DEBUGOUT("Auto-Neg complete.\n"); 3924 return 0; 3925 } 3926 mdelay(100); 3927 } 3928 DEBUGOUT("Auto-Neg timedout.\n"); 3929 return -E1000_ERR_TIMEOUT; 3930 } 3931 3932 /****************************************************************************** 3933 * Raises the Management Data Clock 3934 * 3935 * hw - Struct containing variables accessed by shared code 3936 * ctrl - Device control register's current value 3937 ******************************************************************************/ 3938 static void 3939 e1000_raise_mdi_clk(struct e1000_hw *hw, uint32_t * ctrl) 3940 { 3941 /* Raise the clock input to the Management Data Clock (by setting the MDC 3942 * bit), and then delay 2 microseconds. 3943 */ 3944 E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC)); 3945 E1000_WRITE_FLUSH(hw); 3946 udelay(2); 3947 } 3948 3949 /****************************************************************************** 3950 * Lowers the Management Data Clock 3951 * 3952 * hw - Struct containing variables accessed by shared code 3953 * ctrl - Device control register's current value 3954 ******************************************************************************/ 3955 static void 3956 e1000_lower_mdi_clk(struct e1000_hw *hw, uint32_t * ctrl) 3957 { 3958 /* Lower the clock input to the Management Data Clock (by clearing the MDC 3959 * bit), and then delay 2 microseconds. 3960 */ 3961 E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC)); 3962 E1000_WRITE_FLUSH(hw); 3963 udelay(2); 3964 } 3965 3966 /****************************************************************************** 3967 * Shifts data bits out to the PHY 3968 * 3969 * hw - Struct containing variables accessed by shared code 3970 * data - Data to send out to the PHY 3971 * count - Number of bits to shift out 3972 * 3973 * Bits are shifted out in MSB to LSB order. 3974 ******************************************************************************/ 3975 static void 3976 e1000_shift_out_mdi_bits(struct e1000_hw *hw, uint32_t data, uint16_t count) 3977 { 3978 uint32_t ctrl; 3979 uint32_t mask; 3980 3981 /* We need to shift "count" number of bits out to the PHY. So, the value 3982 * in the "data" parameter will be shifted out to the PHY one bit at a 3983 * time. In order to do this, "data" must be broken down into bits. 3984 */ 3985 mask = 0x01; 3986 mask <<= (count - 1); 3987 3988 ctrl = E1000_READ_REG(hw, CTRL); 3989 3990 /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */ 3991 ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR); 3992 3993 while (mask) { 3994 /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and 3995 * then raising and lowering the Management Data Clock. A "0" is 3996 * shifted out to the PHY by setting the MDIO bit to "0" and then 3997 * raising and lowering the clock. 3998 */ 3999 if (data & mask) 4000 ctrl |= E1000_CTRL_MDIO; 4001 else 4002 ctrl &= ~E1000_CTRL_MDIO; 4003 4004 E1000_WRITE_REG(hw, CTRL, ctrl); 4005 E1000_WRITE_FLUSH(hw); 4006 4007 udelay(2); 4008 4009 e1000_raise_mdi_clk(hw, &ctrl); 4010 e1000_lower_mdi_clk(hw, &ctrl); 4011 4012 mask = mask >> 1; 4013 } 4014 } 4015 4016 /****************************************************************************** 4017 * Shifts data bits in from the PHY 4018 * 4019 * hw - Struct containing variables accessed by shared code 4020 * 4021 * Bits are shifted in in MSB to LSB order. 4022 ******************************************************************************/ 4023 static uint16_t 4024 e1000_shift_in_mdi_bits(struct e1000_hw *hw) 4025 { 4026 uint32_t ctrl; 4027 uint16_t data = 0; 4028 uint8_t i; 4029 4030 /* In order to read a register from the PHY, we need to shift in a total 4031 * of 18 bits from the PHY. The first two bit (turnaround) times are used 4032 * to avoid contention on the MDIO pin when a read operation is performed. 4033 * These two bits are ignored by us and thrown away. Bits are "shifted in" 4034 * by raising the input to the Management Data Clock (setting the MDC bit), 4035 * and then reading the value of the MDIO bit. 4036 */ 4037 ctrl = E1000_READ_REG(hw, CTRL); 4038 4039 /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */ 4040 ctrl &= ~E1000_CTRL_MDIO_DIR; 4041 ctrl &= ~E1000_CTRL_MDIO; 4042 4043 E1000_WRITE_REG(hw, CTRL, ctrl); 4044 E1000_WRITE_FLUSH(hw); 4045 4046 /* Raise and Lower the clock before reading in the data. This accounts for 4047 * the turnaround bits. The first clock occurred when we clocked out the 4048 * last bit of the Register Address. 4049 */ 4050 e1000_raise_mdi_clk(hw, &ctrl); 4051 e1000_lower_mdi_clk(hw, &ctrl); 4052 4053 for (data = 0, i = 0; i < 16; i++) { 4054 data = data << 1; 4055 e1000_raise_mdi_clk(hw, &ctrl); 4056 ctrl = E1000_READ_REG(hw, CTRL); 4057 /* Check to see if we shifted in a "1". */ 4058 if (ctrl & E1000_CTRL_MDIO) 4059 data |= 1; 4060 e1000_lower_mdi_clk(hw, &ctrl); 4061 } 4062 4063 e1000_raise_mdi_clk(hw, &ctrl); 4064 e1000_lower_mdi_clk(hw, &ctrl); 4065 4066 return data; 4067 } 4068 4069 /***************************************************************************** 4070 * Reads the value from a PHY register 4071 * 4072 * hw - Struct containing variables accessed by shared code 4073 * reg_addr - address of the PHY register to read 4074 ******************************************************************************/ 4075 static int 4076 e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t * phy_data) 4077 { 4078 uint32_t i; 4079 uint32_t mdic = 0; 4080 const uint32_t phy_addr = 1; 4081 4082 if (reg_addr > MAX_PHY_REG_ADDRESS) { 4083 DEBUGOUT("PHY Address %d is out of range\n", reg_addr); 4084 return -E1000_ERR_PARAM; 4085 } 4086 4087 if (hw->mac_type > e1000_82543) { 4088 /* Set up Op-code, Phy Address, and register address in the MDI 4089 * Control register. The MAC will take care of interfacing with the 4090 * PHY to retrieve the desired data. 4091 */ 4092 mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) | 4093 (phy_addr << E1000_MDIC_PHY_SHIFT) | 4094 (E1000_MDIC_OP_READ)); 4095 4096 E1000_WRITE_REG(hw, MDIC, mdic); 4097 4098 /* Poll the ready bit to see if the MDI read completed */ 4099 for (i = 0; i < 64; i++) { 4100 udelay(10); 4101 mdic = E1000_READ_REG(hw, MDIC); 4102 if (mdic & E1000_MDIC_READY) 4103 break; 4104 } 4105 if (!(mdic & E1000_MDIC_READY)) { 4106 DEBUGOUT("MDI Read did not complete\n"); 4107 return -E1000_ERR_PHY; 4108 } 4109 if (mdic & E1000_MDIC_ERROR) { 4110 DEBUGOUT("MDI Error\n"); 4111 return -E1000_ERR_PHY; 4112 } 4113 *phy_data = (uint16_t) mdic; 4114 } else { 4115 /* We must first send a preamble through the MDIO pin to signal the 4116 * beginning of an MII instruction. This is done by sending 32 4117 * consecutive "1" bits. 4118 */ 4119 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); 4120 4121 /* Now combine the next few fields that are required for a read 4122 * operation. We use this method instead of calling the 4123 * e1000_shift_out_mdi_bits routine five different times. The format of 4124 * a MII read instruction consists of a shift out of 14 bits and is 4125 * defined as follows: 4126 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr> 4127 * followed by a shift in of 18 bits. This first two bits shifted in 4128 * are TurnAround bits used to avoid contention on the MDIO pin when a 4129 * READ operation is performed. These two bits are thrown away 4130 * followed by a shift in of 16 bits which contains the desired data. 4131 */ 4132 mdic = ((reg_addr) | (phy_addr << 5) | 4133 (PHY_OP_READ << 10) | (PHY_SOF << 12)); 4134 4135 e1000_shift_out_mdi_bits(hw, mdic, 14); 4136 4137 /* Now that we've shifted out the read command to the MII, we need to 4138 * "shift in" the 16-bit value (18 total bits) of the requested PHY 4139 * register address. 4140 */ 4141 *phy_data = e1000_shift_in_mdi_bits(hw); 4142 } 4143 return 0; 4144 } 4145 4146 /****************************************************************************** 4147 * Writes a value to a PHY register 4148 * 4149 * hw - Struct containing variables accessed by shared code 4150 * reg_addr - address of the PHY register to write 4151 * data - data to write to the PHY 4152 ******************************************************************************/ 4153 static int 4154 e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t phy_data) 4155 { 4156 uint32_t i; 4157 uint32_t mdic = 0; 4158 const uint32_t phy_addr = 1; 4159 4160 if (reg_addr > MAX_PHY_REG_ADDRESS) { 4161 DEBUGOUT("PHY Address %d is out of range\n", reg_addr); 4162 return -E1000_ERR_PARAM; 4163 } 4164 4165 if (hw->mac_type > e1000_82543) { 4166 /* Set up Op-code, Phy Address, register address, and data intended 4167 * for the PHY register in the MDI Control register. The MAC will take 4168 * care of interfacing with the PHY to send the desired data. 4169 */ 4170 mdic = (((uint32_t) phy_data) | 4171 (reg_addr << E1000_MDIC_REG_SHIFT) | 4172 (phy_addr << E1000_MDIC_PHY_SHIFT) | 4173 (E1000_MDIC_OP_WRITE)); 4174 4175 E1000_WRITE_REG(hw, MDIC, mdic); 4176 4177 /* Poll the ready bit to see if the MDI read completed */ 4178 for (i = 0; i < 64; i++) { 4179 udelay(10); 4180 mdic = E1000_READ_REG(hw, MDIC); 4181 if (mdic & E1000_MDIC_READY) 4182 break; 4183 } 4184 if (!(mdic & E1000_MDIC_READY)) { 4185 DEBUGOUT("MDI Write did not complete\n"); 4186 return -E1000_ERR_PHY; 4187 } 4188 } else { 4189 /* We'll need to use the SW defined pins to shift the write command 4190 * out to the PHY. We first send a preamble to the PHY to signal the 4191 * beginning of the MII instruction. This is done by sending 32 4192 * consecutive "1" bits. 4193 */ 4194 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); 4195 4196 /* Now combine the remaining required fields that will indicate a 4197 * write operation. We use this method instead of calling the 4198 * e1000_shift_out_mdi_bits routine for each field in the command. The 4199 * format of a MII write instruction is as follows: 4200 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>. 4201 */ 4202 mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) | 4203 (PHY_OP_WRITE << 12) | (PHY_SOF << 14)); 4204 mdic <<= 16; 4205 mdic |= (uint32_t) phy_data; 4206 4207 e1000_shift_out_mdi_bits(hw, mdic, 32); 4208 } 4209 return 0; 4210 } 4211 4212 /****************************************************************************** 4213 * Checks if PHY reset is blocked due to SOL/IDER session, for example. 4214 * Returning E1000_BLK_PHY_RESET isn't necessarily an error. But it's up to 4215 * the caller to figure out how to deal with it. 4216 * 4217 * hw - Struct containing variables accessed by shared code 4218 * 4219 * returns: - E1000_BLK_PHY_RESET 4220 * E1000_SUCCESS 4221 * 4222 *****************************************************************************/ 4223 int32_t 4224 e1000_check_phy_reset_block(struct e1000_hw *hw) 4225 { 4226 uint32_t manc = 0; 4227 uint32_t fwsm = 0; 4228 4229 if (hw->mac_type == e1000_ich8lan) { 4230 fwsm = E1000_READ_REG(hw, FWSM); 4231 return (fwsm & E1000_FWSM_RSPCIPHY) ? E1000_SUCCESS 4232 : E1000_BLK_PHY_RESET; 4233 } 4234 4235 if (hw->mac_type > e1000_82547_rev_2) 4236 manc = E1000_READ_REG(hw, MANC); 4237 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ? 4238 E1000_BLK_PHY_RESET : E1000_SUCCESS; 4239 } 4240 4241 /*************************************************************************** 4242 * Checks if the PHY configuration is done 4243 * 4244 * hw: Struct containing variables accessed by shared code 4245 * 4246 * returns: - E1000_ERR_RESET if fail to reset MAC 4247 * E1000_SUCCESS at any other case. 4248 * 4249 ***************************************************************************/ 4250 static int32_t 4251 e1000_get_phy_cfg_done(struct e1000_hw *hw) 4252 { 4253 int32_t timeout = PHY_CFG_TIMEOUT; 4254 uint32_t cfg_mask = E1000_EEPROM_CFG_DONE; 4255 4256 DEBUGFUNC(); 4257 4258 switch (hw->mac_type) { 4259 default: 4260 mdelay(10); 4261 break; 4262 case e1000_80003es2lan: 4263 /* Separate *_CFG_DONE_* bit for each port */ 4264 if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1) 4265 cfg_mask = E1000_EEPROM_CFG_DONE_PORT_1; 4266 /* Fall Through */ 4267 case e1000_82571: 4268 case e1000_82572: 4269 while (timeout) { 4270 if (E1000_READ_REG(hw, EEMNGCTL) & cfg_mask) 4271 break; 4272 else 4273 mdelay(1); 4274 timeout--; 4275 } 4276 if (!timeout) { 4277 DEBUGOUT("MNG configuration cycle has not " 4278 "completed.\n"); 4279 return -E1000_ERR_RESET; 4280 } 4281 break; 4282 } 4283 4284 return E1000_SUCCESS; 4285 } 4286 4287 /****************************************************************************** 4288 * Returns the PHY to the power-on reset state 4289 * 4290 * hw - Struct containing variables accessed by shared code 4291 ******************************************************************************/ 4292 int32_t 4293 e1000_phy_hw_reset(struct e1000_hw *hw) 4294 { 4295 uint32_t ctrl, ctrl_ext; 4296 uint32_t led_ctrl; 4297 int32_t ret_val; 4298 uint16_t swfw; 4299 4300 DEBUGFUNC(); 4301 4302 /* In the case of the phy reset being blocked, it's not an error, we 4303 * simply return success without performing the reset. */ 4304 ret_val = e1000_check_phy_reset_block(hw); 4305 if (ret_val) 4306 return E1000_SUCCESS; 4307 4308 DEBUGOUT("Resetting Phy...\n"); 4309 4310 if (hw->mac_type > e1000_82543) { 4311 if ((hw->mac_type == e1000_80003es2lan) && 4312 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) { 4313 swfw = E1000_SWFW_PHY1_SM; 4314 } else { 4315 swfw = E1000_SWFW_PHY0_SM; 4316 } 4317 if (e1000_swfw_sync_acquire(hw, swfw)) { 4318 DEBUGOUT("Unable to acquire swfw sync\n"); 4319 return -E1000_ERR_SWFW_SYNC; 4320 } 4321 /* Read the device control register and assert the E1000_CTRL_PHY_RST 4322 * bit. Then, take it out of reset. 4323 */ 4324 ctrl = E1000_READ_REG(hw, CTRL); 4325 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST); 4326 E1000_WRITE_FLUSH(hw); 4327 4328 if (hw->mac_type < e1000_82571) 4329 udelay(10); 4330 else 4331 udelay(100); 4332 4333 E1000_WRITE_REG(hw, CTRL, ctrl); 4334 E1000_WRITE_FLUSH(hw); 4335 4336 if (hw->mac_type >= e1000_82571) 4337 mdelay(10); 4338 4339 } else { 4340 /* Read the Extended Device Control Register, assert the PHY_RESET_DIR 4341 * bit to put the PHY into reset. Then, take it out of reset. 4342 */ 4343 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 4344 ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR; 4345 ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA; 4346 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 4347 E1000_WRITE_FLUSH(hw); 4348 mdelay(10); 4349 ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA; 4350 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 4351 E1000_WRITE_FLUSH(hw); 4352 } 4353 udelay(150); 4354 4355 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { 4356 /* Configure activity LED after PHY reset */ 4357 led_ctrl = E1000_READ_REG(hw, LEDCTL); 4358 led_ctrl &= IGP_ACTIVITY_LED_MASK; 4359 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); 4360 E1000_WRITE_REG(hw, LEDCTL, led_ctrl); 4361 } 4362 4363 /* Wait for FW to finish PHY configuration. */ 4364 ret_val = e1000_get_phy_cfg_done(hw); 4365 if (ret_val != E1000_SUCCESS) 4366 return ret_val; 4367 4368 return ret_val; 4369 } 4370 4371 /****************************************************************************** 4372 * IGP phy init script - initializes the GbE PHY 4373 * 4374 * hw - Struct containing variables accessed by shared code 4375 *****************************************************************************/ 4376 static void 4377 e1000_phy_init_script(struct e1000_hw *hw) 4378 { 4379 uint32_t ret_val; 4380 uint16_t phy_saved_data; 4381 DEBUGFUNC(); 4382 4383 if (hw->phy_init_script) { 4384 mdelay(20); 4385 4386 /* Save off the current value of register 0x2F5B to be 4387 * restored at the end of this routine. */ 4388 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data); 4389 4390 /* Disabled the PHY transmitter */ 4391 e1000_write_phy_reg(hw, 0x2F5B, 0x0003); 4392 4393 mdelay(20); 4394 4395 e1000_write_phy_reg(hw, 0x0000, 0x0140); 4396 4397 mdelay(5); 4398 4399 switch (hw->mac_type) { 4400 case e1000_82541: 4401 case e1000_82547: 4402 e1000_write_phy_reg(hw, 0x1F95, 0x0001); 4403 4404 e1000_write_phy_reg(hw, 0x1F71, 0xBD21); 4405 4406 e1000_write_phy_reg(hw, 0x1F79, 0x0018); 4407 4408 e1000_write_phy_reg(hw, 0x1F30, 0x1600); 4409 4410 e1000_write_phy_reg(hw, 0x1F31, 0x0014); 4411 4412 e1000_write_phy_reg(hw, 0x1F32, 0x161C); 4413 4414 e1000_write_phy_reg(hw, 0x1F94, 0x0003); 4415 4416 e1000_write_phy_reg(hw, 0x1F96, 0x003F); 4417 4418 e1000_write_phy_reg(hw, 0x2010, 0x0008); 4419 break; 4420 4421 case e1000_82541_rev_2: 4422 case e1000_82547_rev_2: 4423 e1000_write_phy_reg(hw, 0x1F73, 0x0099); 4424 break; 4425 default: 4426 break; 4427 } 4428 4429 e1000_write_phy_reg(hw, 0x0000, 0x3300); 4430 4431 mdelay(20); 4432 4433 /* Now enable the transmitter */ 4434 e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data); 4435 4436 if (hw->mac_type == e1000_82547) { 4437 uint16_t fused, fine, coarse; 4438 4439 /* Move to analog registers page */ 4440 e1000_read_phy_reg(hw, 4441 IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused); 4442 4443 if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) { 4444 e1000_read_phy_reg(hw, 4445 IGP01E1000_ANALOG_FUSE_STATUS, &fused); 4446 4447 fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK; 4448 coarse = fused 4449 & IGP01E1000_ANALOG_FUSE_COARSE_MASK; 4450 4451 if (coarse > 4452 IGP01E1000_ANALOG_FUSE_COARSE_THRESH) { 4453 coarse -= 4454 IGP01E1000_ANALOG_FUSE_COARSE_10; 4455 fine -= IGP01E1000_ANALOG_FUSE_FINE_1; 4456 } else if (coarse 4457 == IGP01E1000_ANALOG_FUSE_COARSE_THRESH) 4458 fine -= IGP01E1000_ANALOG_FUSE_FINE_10; 4459 4460 fused = (fused 4461 & IGP01E1000_ANALOG_FUSE_POLY_MASK) | 4462 (fine 4463 & IGP01E1000_ANALOG_FUSE_FINE_MASK) | 4464 (coarse 4465 & IGP01E1000_ANALOG_FUSE_COARSE_MASK); 4466 4467 e1000_write_phy_reg(hw, 4468 IGP01E1000_ANALOG_FUSE_CONTROL, fused); 4469 e1000_write_phy_reg(hw, 4470 IGP01E1000_ANALOG_FUSE_BYPASS, 4471 IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL); 4472 } 4473 } 4474 } 4475 } 4476 4477 /****************************************************************************** 4478 * Resets the PHY 4479 * 4480 * hw - Struct containing variables accessed by shared code 4481 * 4482 * Sets bit 15 of the MII Control register 4483 ******************************************************************************/ 4484 int32_t 4485 e1000_phy_reset(struct e1000_hw *hw) 4486 { 4487 int32_t ret_val; 4488 uint16_t phy_data; 4489 4490 DEBUGFUNC(); 4491 4492 /* In the case of the phy reset being blocked, it's not an error, we 4493 * simply return success without performing the reset. */ 4494 ret_val = e1000_check_phy_reset_block(hw); 4495 if (ret_val) 4496 return E1000_SUCCESS; 4497 4498 switch (hw->phy_type) { 4499 case e1000_phy_igp: 4500 case e1000_phy_igp_2: 4501 case e1000_phy_igp_3: 4502 case e1000_phy_ife: 4503 ret_val = e1000_phy_hw_reset(hw); 4504 if (ret_val) 4505 return ret_val; 4506 break; 4507 default: 4508 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data); 4509 if (ret_val) 4510 return ret_val; 4511 4512 phy_data |= MII_CR_RESET; 4513 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data); 4514 if (ret_val) 4515 return ret_val; 4516 4517 udelay(1); 4518 break; 4519 } 4520 4521 if (hw->phy_type == e1000_phy_igp || hw->phy_type == e1000_phy_igp_2) 4522 e1000_phy_init_script(hw); 4523 4524 return E1000_SUCCESS; 4525 } 4526 4527 static int e1000_set_phy_type (struct e1000_hw *hw) 4528 { 4529 DEBUGFUNC (); 4530 4531 if (hw->mac_type == e1000_undefined) 4532 return -E1000_ERR_PHY_TYPE; 4533 4534 switch (hw->phy_id) { 4535 case M88E1000_E_PHY_ID: 4536 case M88E1000_I_PHY_ID: 4537 case M88E1011_I_PHY_ID: 4538 case M88E1111_I_PHY_ID: 4539 hw->phy_type = e1000_phy_m88; 4540 break; 4541 case IGP01E1000_I_PHY_ID: 4542 if (hw->mac_type == e1000_82541 || 4543 hw->mac_type == e1000_82541_rev_2 || 4544 hw->mac_type == e1000_82547 || 4545 hw->mac_type == e1000_82547_rev_2) { 4546 hw->phy_type = e1000_phy_igp; 4547 hw->phy_type = e1000_phy_igp; 4548 break; 4549 } 4550 case IGP03E1000_E_PHY_ID: 4551 hw->phy_type = e1000_phy_igp_3; 4552 break; 4553 case IFE_E_PHY_ID: 4554 case IFE_PLUS_E_PHY_ID: 4555 case IFE_C_E_PHY_ID: 4556 hw->phy_type = e1000_phy_ife; 4557 break; 4558 case GG82563_E_PHY_ID: 4559 if (hw->mac_type == e1000_80003es2lan) { 4560 hw->phy_type = e1000_phy_gg82563; 4561 break; 4562 } 4563 /* Fall Through */ 4564 default: 4565 /* Should never have loaded on this device */ 4566 hw->phy_type = e1000_phy_undefined; 4567 return -E1000_ERR_PHY_TYPE; 4568 } 4569 4570 return E1000_SUCCESS; 4571 } 4572 4573 /****************************************************************************** 4574 * Probes the expected PHY address for known PHY IDs 4575 * 4576 * hw - Struct containing variables accessed by shared code 4577 ******************************************************************************/ 4578 static int32_t 4579 e1000_detect_gig_phy(struct e1000_hw *hw) 4580 { 4581 int32_t phy_init_status, ret_val; 4582 uint16_t phy_id_high, phy_id_low; 4583 boolean_t match = FALSE; 4584 4585 DEBUGFUNC(); 4586 4587 /* The 82571 firmware may still be configuring the PHY. In this 4588 * case, we cannot access the PHY until the configuration is done. So 4589 * we explicitly set the PHY values. */ 4590 if (hw->mac_type == e1000_82571 || 4591 hw->mac_type == e1000_82572) { 4592 hw->phy_id = IGP01E1000_I_PHY_ID; 4593 hw->phy_type = e1000_phy_igp_2; 4594 return E1000_SUCCESS; 4595 } 4596 4597 /* ESB-2 PHY reads require e1000_phy_gg82563 to be set because of a 4598 * work- around that forces PHY page 0 to be set or the reads fail. 4599 * The rest of the code in this routine uses e1000_read_phy_reg to 4600 * read the PHY ID. So for ESB-2 we need to have this set so our 4601 * reads won't fail. If the attached PHY is not a e1000_phy_gg82563, 4602 * the routines below will figure this out as well. */ 4603 if (hw->mac_type == e1000_80003es2lan) 4604 hw->phy_type = e1000_phy_gg82563; 4605 4606 /* Read the PHY ID Registers to identify which PHY is onboard. */ 4607 ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high); 4608 if (ret_val) 4609 return ret_val; 4610 4611 hw->phy_id = (uint32_t) (phy_id_high << 16); 4612 udelay(20); 4613 ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low); 4614 if (ret_val) 4615 return ret_val; 4616 4617 hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK); 4618 hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK; 4619 4620 switch (hw->mac_type) { 4621 case e1000_82543: 4622 if (hw->phy_id == M88E1000_E_PHY_ID) 4623 match = TRUE; 4624 break; 4625 case e1000_82544: 4626 if (hw->phy_id == M88E1000_I_PHY_ID) 4627 match = TRUE; 4628 break; 4629 case e1000_82540: 4630 case e1000_82545: 4631 case e1000_82545_rev_3: 4632 case e1000_82546: 4633 case e1000_82546_rev_3: 4634 if (hw->phy_id == M88E1011_I_PHY_ID) 4635 match = TRUE; 4636 break; 4637 case e1000_82541: 4638 case e1000_82541_rev_2: 4639 case e1000_82547: 4640 case e1000_82547_rev_2: 4641 if(hw->phy_id == IGP01E1000_I_PHY_ID) 4642 match = TRUE; 4643 4644 break; 4645 case e1000_82573: 4646 if (hw->phy_id == M88E1111_I_PHY_ID) 4647 match = TRUE; 4648 break; 4649 case e1000_80003es2lan: 4650 if (hw->phy_id == GG82563_E_PHY_ID) 4651 match = TRUE; 4652 break; 4653 case e1000_ich8lan: 4654 if (hw->phy_id == IGP03E1000_E_PHY_ID) 4655 match = TRUE; 4656 if (hw->phy_id == IFE_E_PHY_ID) 4657 match = TRUE; 4658 if (hw->phy_id == IFE_PLUS_E_PHY_ID) 4659 match = TRUE; 4660 if (hw->phy_id == IFE_C_E_PHY_ID) 4661 match = TRUE; 4662 break; 4663 default: 4664 DEBUGOUT("Invalid MAC type %d\n", hw->mac_type); 4665 return -E1000_ERR_CONFIG; 4666 } 4667 4668 phy_init_status = e1000_set_phy_type(hw); 4669 4670 if ((match) && (phy_init_status == E1000_SUCCESS)) { 4671 DEBUGOUT("PHY ID 0x%X detected\n", hw->phy_id); 4672 return 0; 4673 } 4674 DEBUGOUT("Invalid PHY ID 0x%X\n", hw->phy_id); 4675 return -E1000_ERR_PHY; 4676 } 4677 4678 /***************************************************************************** 4679 * Set media type and TBI compatibility. 4680 * 4681 * hw - Struct containing variables accessed by shared code 4682 * **************************************************************************/ 4683 void 4684 e1000_set_media_type(struct e1000_hw *hw) 4685 { 4686 uint32_t status; 4687 4688 DEBUGFUNC(); 4689 4690 if (hw->mac_type != e1000_82543) { 4691 /* tbi_compatibility is only valid on 82543 */ 4692 hw->tbi_compatibility_en = FALSE; 4693 } 4694 4695 switch (hw->device_id) { 4696 case E1000_DEV_ID_82545GM_SERDES: 4697 case E1000_DEV_ID_82546GB_SERDES: 4698 case E1000_DEV_ID_82571EB_SERDES: 4699 case E1000_DEV_ID_82571EB_SERDES_DUAL: 4700 case E1000_DEV_ID_82571EB_SERDES_QUAD: 4701 case E1000_DEV_ID_82572EI_SERDES: 4702 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT: 4703 hw->media_type = e1000_media_type_internal_serdes; 4704 break; 4705 default: 4706 switch (hw->mac_type) { 4707 case e1000_82542_rev2_0: 4708 case e1000_82542_rev2_1: 4709 hw->media_type = e1000_media_type_fiber; 4710 break; 4711 case e1000_ich8lan: 4712 case e1000_82573: 4713 /* The STATUS_TBIMODE bit is reserved or reused 4714 * for the this device. 4715 */ 4716 hw->media_type = e1000_media_type_copper; 4717 break; 4718 default: 4719 status = E1000_READ_REG(hw, STATUS); 4720 if (status & E1000_STATUS_TBIMODE) { 4721 hw->media_type = e1000_media_type_fiber; 4722 /* tbi_compatibility not valid on fiber */ 4723 hw->tbi_compatibility_en = FALSE; 4724 } else { 4725 hw->media_type = e1000_media_type_copper; 4726 } 4727 break; 4728 } 4729 } 4730 } 4731 4732 /** 4733 * e1000_sw_init - Initialize general software structures (struct e1000_adapter) 4734 * 4735 * e1000_sw_init initializes the Adapter private data structure. 4736 * Fields are initialized based on PCI device information and 4737 * OS network device settings (MTU size). 4738 **/ 4739 4740 static int 4741 e1000_sw_init(struct eth_device *nic, int cardnum) 4742 { 4743 struct e1000_hw *hw = (typeof(hw)) nic->priv; 4744 int result; 4745 4746 /* PCI config space info */ 4747 pci_read_config_word(hw->pdev, PCI_VENDOR_ID, &hw->vendor_id); 4748 pci_read_config_word(hw->pdev, PCI_DEVICE_ID, &hw->device_id); 4749 pci_read_config_word(hw->pdev, PCI_SUBSYSTEM_VENDOR_ID, 4750 &hw->subsystem_vendor_id); 4751 pci_read_config_word(hw->pdev, PCI_SUBSYSTEM_ID, &hw->subsystem_id); 4752 4753 pci_read_config_byte(hw->pdev, PCI_REVISION_ID, &hw->revision_id); 4754 pci_read_config_word(hw->pdev, PCI_COMMAND, &hw->pci_cmd_word); 4755 4756 /* identify the MAC */ 4757 result = e1000_set_mac_type(hw); 4758 if (result) { 4759 E1000_ERR("Unknown MAC Type\n"); 4760 return result; 4761 } 4762 4763 switch (hw->mac_type) { 4764 default: 4765 break; 4766 case e1000_82541: 4767 case e1000_82547: 4768 case e1000_82541_rev_2: 4769 case e1000_82547_rev_2: 4770 hw->phy_init_script = 1; 4771 break; 4772 } 4773 4774 /* lan a vs. lan b settings */ 4775 if (hw->mac_type == e1000_82546) 4776 /*this also works w/ multiple 82546 cards */ 4777 /*but not if they're intermingled /w other e1000s */ 4778 hw->lan_loc = (cardnum % 2) ? e1000_lan_b : e1000_lan_a; 4779 else 4780 hw->lan_loc = e1000_lan_a; 4781 4782 /* flow control settings */ 4783 hw->fc_high_water = E1000_FC_HIGH_THRESH; 4784 hw->fc_low_water = E1000_FC_LOW_THRESH; 4785 hw->fc_pause_time = E1000_FC_PAUSE_TIME; 4786 hw->fc_send_xon = 1; 4787 4788 /* Media type - copper or fiber */ 4789 e1000_set_media_type(hw); 4790 4791 if (hw->mac_type >= e1000_82543) { 4792 uint32_t status = E1000_READ_REG(hw, STATUS); 4793 4794 if (status & E1000_STATUS_TBIMODE) { 4795 DEBUGOUT("fiber interface\n"); 4796 hw->media_type = e1000_media_type_fiber; 4797 } else { 4798 DEBUGOUT("copper interface\n"); 4799 hw->media_type = e1000_media_type_copper; 4800 } 4801 } else { 4802 hw->media_type = e1000_media_type_fiber; 4803 } 4804 4805 hw->tbi_compatibility_en = TRUE; 4806 hw->wait_autoneg_complete = TRUE; 4807 if (hw->mac_type < e1000_82543) 4808 hw->report_tx_early = 0; 4809 else 4810 hw->report_tx_early = 1; 4811 4812 return E1000_SUCCESS; 4813 } 4814 4815 void 4816 fill_rx(struct e1000_hw *hw) 4817 { 4818 struct e1000_rx_desc *rd; 4819 4820 rx_last = rx_tail; 4821 rd = rx_base + rx_tail; 4822 rx_tail = (rx_tail + 1) % 8; 4823 memset(rd, 0, 16); 4824 rd->buffer_addr = cpu_to_le64((u32) & packet); 4825 E1000_WRITE_REG(hw, RDT, rx_tail); 4826 } 4827 4828 /** 4829 * e1000_configure_tx - Configure 8254x Transmit Unit after Reset 4830 * @adapter: board private structure 4831 * 4832 * Configure the Tx unit of the MAC after a reset. 4833 **/ 4834 4835 static void 4836 e1000_configure_tx(struct e1000_hw *hw) 4837 { 4838 unsigned long ptr; 4839 unsigned long tctl; 4840 unsigned long tipg, tarc; 4841 uint32_t ipgr1, ipgr2; 4842 4843 ptr = (u32) tx_pool; 4844 if (ptr & 0xf) 4845 ptr = (ptr + 0x10) & (~0xf); 4846 4847 tx_base = (typeof(tx_base)) ptr; 4848 4849 E1000_WRITE_REG(hw, TDBAL, (u32) tx_base); 4850 E1000_WRITE_REG(hw, TDBAH, 0); 4851 4852 E1000_WRITE_REG(hw, TDLEN, 128); 4853 4854 /* Setup the HW Tx Head and Tail descriptor pointers */ 4855 E1000_WRITE_REG(hw, TDH, 0); 4856 E1000_WRITE_REG(hw, TDT, 0); 4857 tx_tail = 0; 4858 4859 /* Set the default values for the Tx Inter Packet Gap timer */ 4860 if (hw->mac_type <= e1000_82547_rev_2 && 4861 (hw->media_type == e1000_media_type_fiber || 4862 hw->media_type == e1000_media_type_internal_serdes)) 4863 tipg = DEFAULT_82543_TIPG_IPGT_FIBER; 4864 else 4865 tipg = DEFAULT_82543_TIPG_IPGT_COPPER; 4866 4867 /* Set the default values for the Tx Inter Packet Gap timer */ 4868 switch (hw->mac_type) { 4869 case e1000_82542_rev2_0: 4870 case e1000_82542_rev2_1: 4871 tipg = DEFAULT_82542_TIPG_IPGT; 4872 ipgr1 = DEFAULT_82542_TIPG_IPGR1; 4873 ipgr2 = DEFAULT_82542_TIPG_IPGR2; 4874 break; 4875 case e1000_80003es2lan: 4876 ipgr1 = DEFAULT_82543_TIPG_IPGR1; 4877 ipgr2 = DEFAULT_80003ES2LAN_TIPG_IPGR2; 4878 break; 4879 default: 4880 ipgr1 = DEFAULT_82543_TIPG_IPGR1; 4881 ipgr2 = DEFAULT_82543_TIPG_IPGR2; 4882 break; 4883 } 4884 tipg |= ipgr1 << E1000_TIPG_IPGR1_SHIFT; 4885 tipg |= ipgr2 << E1000_TIPG_IPGR2_SHIFT; 4886 E1000_WRITE_REG(hw, TIPG, tipg); 4887 /* Program the Transmit Control Register */ 4888 tctl = E1000_READ_REG(hw, TCTL); 4889 tctl &= ~E1000_TCTL_CT; 4890 tctl |= E1000_TCTL_EN | E1000_TCTL_PSP | 4891 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); 4892 4893 if (hw->mac_type == e1000_82571 || hw->mac_type == e1000_82572) { 4894 tarc = E1000_READ_REG(hw, TARC0); 4895 /* set the speed mode bit, we'll clear it if we're not at 4896 * gigabit link later */ 4897 /* git bit can be set to 1*/ 4898 } else if (hw->mac_type == e1000_80003es2lan) { 4899 tarc = E1000_READ_REG(hw, TARC0); 4900 tarc |= 1; 4901 E1000_WRITE_REG(hw, TARC0, tarc); 4902 tarc = E1000_READ_REG(hw, TARC1); 4903 tarc |= 1; 4904 E1000_WRITE_REG(hw, TARC1, tarc); 4905 } 4906 4907 4908 e1000_config_collision_dist(hw); 4909 /* Setup Transmit Descriptor Settings for eop descriptor */ 4910 hw->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS; 4911 4912 /* Need to set up RS bit */ 4913 if (hw->mac_type < e1000_82543) 4914 hw->txd_cmd |= E1000_TXD_CMD_RPS; 4915 else 4916 hw->txd_cmd |= E1000_TXD_CMD_RS; 4917 E1000_WRITE_REG(hw, TCTL, tctl); 4918 } 4919 4920 /** 4921 * e1000_setup_rctl - configure the receive control register 4922 * @adapter: Board private structure 4923 **/ 4924 static void 4925 e1000_setup_rctl(struct e1000_hw *hw) 4926 { 4927 uint32_t rctl; 4928 4929 rctl = E1000_READ_REG(hw, RCTL); 4930 4931 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 4932 4933 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO 4934 | E1000_RCTL_RDMTS_HALF; /* | 4935 (hw.mc_filter_type << E1000_RCTL_MO_SHIFT); */ 4936 4937 if (hw->tbi_compatibility_on == 1) 4938 rctl |= E1000_RCTL_SBP; 4939 else 4940 rctl &= ~E1000_RCTL_SBP; 4941 4942 rctl &= ~(E1000_RCTL_SZ_4096); 4943 rctl |= E1000_RCTL_SZ_2048; 4944 rctl &= ~(E1000_RCTL_BSEX | E1000_RCTL_LPE); 4945 E1000_WRITE_REG(hw, RCTL, rctl); 4946 } 4947 4948 /** 4949 * e1000_configure_rx - Configure 8254x Receive Unit after Reset 4950 * @adapter: board private structure 4951 * 4952 * Configure the Rx unit of the MAC after a reset. 4953 **/ 4954 static void 4955 e1000_configure_rx(struct e1000_hw *hw) 4956 { 4957 unsigned long ptr; 4958 unsigned long rctl, ctrl_ext; 4959 rx_tail = 0; 4960 /* make sure receives are disabled while setting up the descriptors */ 4961 rctl = E1000_READ_REG(hw, RCTL); 4962 E1000_WRITE_REG(hw, RCTL, rctl & ~E1000_RCTL_EN); 4963 if (hw->mac_type >= e1000_82540) { 4964 /* Set the interrupt throttling rate. Value is calculated 4965 * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns) */ 4966 #define MAX_INTS_PER_SEC 8000 4967 #define DEFAULT_ITR 1000000000/(MAX_INTS_PER_SEC * 256) 4968 E1000_WRITE_REG(hw, ITR, DEFAULT_ITR); 4969 } 4970 4971 if (hw->mac_type >= e1000_82571) { 4972 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 4973 /* Reset delay timers after every interrupt */ 4974 ctrl_ext |= E1000_CTRL_EXT_INT_TIMER_CLR; 4975 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 4976 E1000_WRITE_FLUSH(hw); 4977 } 4978 /* Setup the Base and Length of the Rx Descriptor Ring */ 4979 ptr = (u32) rx_pool; 4980 if (ptr & 0xf) 4981 ptr = (ptr + 0x10) & (~0xf); 4982 rx_base = (typeof(rx_base)) ptr; 4983 E1000_WRITE_REG(hw, RDBAL, (u32) rx_base); 4984 E1000_WRITE_REG(hw, RDBAH, 0); 4985 4986 E1000_WRITE_REG(hw, RDLEN, 128); 4987 4988 /* Setup the HW Rx Head and Tail Descriptor Pointers */ 4989 E1000_WRITE_REG(hw, RDH, 0); 4990 E1000_WRITE_REG(hw, RDT, 0); 4991 /* Enable Receives */ 4992 4993 E1000_WRITE_REG(hw, RCTL, rctl); 4994 fill_rx(hw); 4995 } 4996 4997 /************************************************************************** 4998 POLL - Wait for a frame 4999 ***************************************************************************/ 5000 static int 5001 e1000_poll(struct eth_device *nic) 5002 { 5003 struct e1000_hw *hw = nic->priv; 5004 struct e1000_rx_desc *rd; 5005 /* return true if there's an ethernet packet ready to read */ 5006 rd = rx_base + rx_last; 5007 if (!(le32_to_cpu(rd->status)) & E1000_RXD_STAT_DD) 5008 return 0; 5009 /*DEBUGOUT("recv: packet len=%d \n", rd->length); */ 5010 NetReceive((uchar *)packet, le32_to_cpu(rd->length)); 5011 fill_rx(hw); 5012 return 1; 5013 } 5014 5015 /************************************************************************** 5016 TRANSMIT - Transmit a frame 5017 ***************************************************************************/ 5018 static int 5019 e1000_transmit(struct eth_device *nic, volatile void *packet, int length) 5020 { 5021 struct e1000_hw *hw = nic->priv; 5022 struct e1000_tx_desc *txp; 5023 int i = 0; 5024 5025 txp = tx_base + tx_tail; 5026 tx_tail = (tx_tail + 1) % 8; 5027 5028 txp->buffer_addr = cpu_to_le64(virt_to_bus(hw->pdev, packet)); 5029 txp->lower.data = cpu_to_le32(hw->txd_cmd | length); 5030 txp->upper.data = 0; 5031 E1000_WRITE_REG(hw, TDT, tx_tail); 5032 5033 E1000_WRITE_FLUSH(hw); 5034 while (!(le32_to_cpu(txp->upper.data) & E1000_TXD_STAT_DD)) { 5035 if (i++ > TOUT_LOOP) { 5036 DEBUGOUT("e1000: tx timeout\n"); 5037 return 0; 5038 } 5039 udelay(10); /* give the nic a chance to write to the register */ 5040 } 5041 return 1; 5042 } 5043 5044 /*reset function*/ 5045 static inline int 5046 e1000_reset(struct eth_device *nic) 5047 { 5048 struct e1000_hw *hw = nic->priv; 5049 5050 e1000_reset_hw(hw); 5051 if (hw->mac_type >= e1000_82544) { 5052 E1000_WRITE_REG(hw, WUC, 0); 5053 } 5054 return e1000_init_hw(nic); 5055 } 5056 5057 /************************************************************************** 5058 DISABLE - Turn off ethernet interface 5059 ***************************************************************************/ 5060 static void 5061 e1000_disable(struct eth_device *nic) 5062 { 5063 struct e1000_hw *hw = nic->priv; 5064 5065 /* Turn off the ethernet interface */ 5066 E1000_WRITE_REG(hw, RCTL, 0); 5067 E1000_WRITE_REG(hw, TCTL, 0); 5068 5069 /* Clear the transmit ring */ 5070 E1000_WRITE_REG(hw, TDH, 0); 5071 E1000_WRITE_REG(hw, TDT, 0); 5072 5073 /* Clear the receive ring */ 5074 E1000_WRITE_REG(hw, RDH, 0); 5075 E1000_WRITE_REG(hw, RDT, 0); 5076 5077 /* put the card in its initial state */ 5078 #if 0 5079 E1000_WRITE_REG(hw, CTRL, E1000_CTRL_RST); 5080 #endif 5081 mdelay(10); 5082 5083 } 5084 5085 /************************************************************************** 5086 INIT - set up ethernet interface(s) 5087 ***************************************************************************/ 5088 static int 5089 e1000_init(struct eth_device *nic, bd_t * bis) 5090 { 5091 struct e1000_hw *hw = nic->priv; 5092 int ret_val = 0; 5093 5094 ret_val = e1000_reset(nic); 5095 if (ret_val < 0) { 5096 if ((ret_val == -E1000_ERR_NOLINK) || 5097 (ret_val == -E1000_ERR_TIMEOUT)) { 5098 E1000_ERR("Valid Link not detected\n"); 5099 } else { 5100 E1000_ERR("Hardware Initialization Failed\n"); 5101 } 5102 return 0; 5103 } 5104 e1000_configure_tx(hw); 5105 e1000_setup_rctl(hw); 5106 e1000_configure_rx(hw); 5107 return 1; 5108 } 5109 5110 /****************************************************************************** 5111 * Gets the current PCI bus type of hardware 5112 * 5113 * hw - Struct containing variables accessed by shared code 5114 *****************************************************************************/ 5115 void e1000_get_bus_type(struct e1000_hw *hw) 5116 { 5117 uint32_t status; 5118 5119 switch (hw->mac_type) { 5120 case e1000_82542_rev2_0: 5121 case e1000_82542_rev2_1: 5122 hw->bus_type = e1000_bus_type_pci; 5123 break; 5124 case e1000_82571: 5125 case e1000_82572: 5126 case e1000_82573: 5127 case e1000_80003es2lan: 5128 hw->bus_type = e1000_bus_type_pci_express; 5129 break; 5130 case e1000_ich8lan: 5131 hw->bus_type = e1000_bus_type_pci_express; 5132 break; 5133 default: 5134 status = E1000_READ_REG(hw, STATUS); 5135 hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ? 5136 e1000_bus_type_pcix : e1000_bus_type_pci; 5137 break; 5138 } 5139 } 5140 5141 /************************************************************************** 5142 PROBE - Look for an adapter, this routine's visible to the outside 5143 You should omit the last argument struct pci_device * for a non-PCI NIC 5144 ***************************************************************************/ 5145 int 5146 e1000_initialize(bd_t * bis) 5147 { 5148 pci_dev_t devno; 5149 int card_number = 0; 5150 struct eth_device *nic = NULL; 5151 struct e1000_hw *hw = NULL; 5152 u32 iobase; 5153 int idx = 0; 5154 u32 PciCommandWord; 5155 5156 DEBUGFUNC(); 5157 5158 while (1) { /* Find PCI device(s) */ 5159 if ((devno = pci_find_devices(supported, idx++)) < 0) { 5160 break; 5161 } 5162 5163 pci_read_config_dword(devno, PCI_BASE_ADDRESS_0, &iobase); 5164 iobase &= ~0xf; /* Mask the bits that say "this is an io addr" */ 5165 DEBUGOUT("e1000#%d: iobase 0x%08x\n", card_number, iobase); 5166 5167 pci_write_config_dword(devno, PCI_COMMAND, 5168 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); 5169 /* Check if I/O accesses and Bus Mastering are enabled. */ 5170 pci_read_config_dword(devno, PCI_COMMAND, &PciCommandWord); 5171 if (!(PciCommandWord & PCI_COMMAND_MEMORY)) { 5172 printf("Error: Can not enable MEM access.\n"); 5173 continue; 5174 } else if (!(PciCommandWord & PCI_COMMAND_MASTER)) { 5175 printf("Error: Can not enable Bus Mastering.\n"); 5176 continue; 5177 } 5178 5179 nic = (struct eth_device *) malloc(sizeof (*nic)); 5180 hw = (struct e1000_hw *) malloc(sizeof (*hw)); 5181 hw->pdev = devno; 5182 nic->priv = hw; 5183 5184 sprintf(nic->name, "e1000#%d", card_number); 5185 5186 /* Are these variables needed? */ 5187 hw->fc = e1000_fc_default; 5188 hw->original_fc = e1000_fc_default; 5189 hw->autoneg_failed = 0; 5190 hw->autoneg = 1; 5191 hw->get_link_status = TRUE; 5192 hw->hw_addr = 5193 pci_map_bar(devno, PCI_BASE_ADDRESS_0, PCI_REGION_MEM); 5194 hw->mac_type = e1000_undefined; 5195 5196 /* MAC and Phy settings */ 5197 if (e1000_sw_init(nic, card_number) < 0) { 5198 free(hw); 5199 free(nic); 5200 return 0; 5201 } 5202 if (e1000_check_phy_reset_block(hw)) 5203 printf("phy reset block error \n"); 5204 e1000_reset_hw(hw); 5205 #if !(defined(CONFIG_AP1000) || defined(CONFIG_MVBC_1G)) 5206 if (e1000_init_eeprom_params(hw)) { 5207 printf("The EEPROM Checksum Is Not Valid\n"); 5208 free(hw); 5209 free(nic); 5210 return 0; 5211 } 5212 if (e1000_validate_eeprom_checksum(nic) < 0) { 5213 printf("The EEPROM Checksum Is Not Valid\n"); 5214 free(hw); 5215 free(nic); 5216 return 0; 5217 } 5218 #endif 5219 e1000_read_mac_addr(nic); 5220 5221 /* get the bus type information */ 5222 e1000_get_bus_type(hw); 5223 5224 printf("e1000: %02x:%02x:%02x:%02x:%02x:%02x\n", 5225 nic->enetaddr[0], nic->enetaddr[1], nic->enetaddr[2], 5226 nic->enetaddr[3], nic->enetaddr[4], nic->enetaddr[5]); 5227 5228 nic->init = e1000_init; 5229 nic->recv = e1000_poll; 5230 nic->send = e1000_transmit; 5231 nic->halt = e1000_disable; 5232 5233 eth_register(nic); 5234 5235 card_number++; 5236 } 5237 return card_number; 5238 } 5239