1 /************************************************************************** 2 Intel Pro 1000 for ppcboot/das-u-boot 3 Drivers are port from Intel's Linux driver e1000-4.3.15 4 and from Etherboot pro 1000 driver by mrakes at vivato dot net 5 tested on both gig copper and gig fiber boards 6 ***************************************************************************/ 7 /******************************************************************************* 8 9 10 Copyright(c) 1999 - 2002 Intel Corporation. All rights reserved. 11 12 This program is free software; you can redistribute it and/or modify it 13 under the terms of the GNU General Public License as published by the Free 14 Software Foundation; either version 2 of the License, or (at your option) 15 any later version. 16 17 This program is distributed in the hope that it will be useful, but WITHOUT 18 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 19 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 20 more details. 21 22 You should have received a copy of the GNU General Public License along with 23 this program; if not, write to the Free Software Foundation, Inc., 59 24 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 25 26 The full GNU General Public License is included in this distribution in the 27 file called LICENSE. 28 29 Contact Information: 30 Linux NICS <linux.nics@intel.com> 31 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 32 33 *******************************************************************************/ 34 /* 35 * Copyright (C) Archway Digital Solutions. 36 * 37 * written by Chrsitopher Li <cli at arcyway dot com> or <chrisl at gnuchina dot org> 38 * 2/9/2002 39 * 40 * Copyright (C) Linux Networx. 41 * Massive upgrade to work with the new intel gigabit NICs. 42 * <ebiederman at lnxi dot com> 43 */ 44 45 #include "e1000.h" 46 47 #define TOUT_LOOP 100000 48 49 #define virt_to_bus(devno, v) pci_virt_to_mem(devno, (void *) (v)) 50 #define bus_to_phys(devno, a) pci_mem_to_phys(devno, a) 51 #define mdelay(n) udelay((n)*1000) 52 53 #define E1000_DEFAULT_PBA 0x000a0026 54 55 /* NIC specific static variables go here */ 56 57 static char tx_pool[128 + 16]; 58 static char rx_pool[128 + 16]; 59 static char packet[2096]; 60 61 static struct e1000_tx_desc *tx_base; 62 static struct e1000_rx_desc *rx_base; 63 64 static int tx_tail; 65 static int rx_tail, rx_last; 66 67 static struct pci_device_id supported[] = { 68 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82542}, 69 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82543GC_FIBER}, 70 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82543GC_COPPER}, 71 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544EI_COPPER}, 72 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544EI_FIBER}, 73 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544GC_COPPER}, 74 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544GC_LOM}, 75 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82540EM}, 76 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545EM_COPPER}, 77 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545GM_COPPER}, 78 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_COPPER}, 79 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545EM_FIBER}, 80 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_FIBER}, 81 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82540EM_LOM}, 82 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82541ER}, 83 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82541GI_LF}, 84 /* E1000 PCIe card */ 85 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_COPPER}, 86 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_FIBER }, 87 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES }, 88 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_COPPER}, 89 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571PT_QUAD_COPPER}, 90 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_FIBER}, 91 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_COPPER_LOWPROFILE}, 92 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES_DUAL}, 93 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES_QUAD}, 94 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_COPPER}, 95 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_FIBER}, 96 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_SERDES}, 97 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI}, 98 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573E}, 99 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573E_IAMT}, 100 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573L}, 101 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546GB_QUAD_COPPER_KSP3}, 102 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_COPPER_DPT}, 103 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_SERDES_DPT}, 104 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_COPPER_SPT}, 105 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_SERDES_SPT}, 106 {} 107 }; 108 109 /* Function forward declarations */ 110 static int e1000_setup_link(struct eth_device *nic); 111 static int e1000_setup_fiber_link(struct eth_device *nic); 112 static int e1000_setup_copper_link(struct eth_device *nic); 113 static int e1000_phy_setup_autoneg(struct e1000_hw *hw); 114 static void e1000_config_collision_dist(struct e1000_hw *hw); 115 static int e1000_config_mac_to_phy(struct e1000_hw *hw); 116 static int e1000_config_fc_after_link_up(struct e1000_hw *hw); 117 static int e1000_check_for_link(struct eth_device *nic); 118 static int e1000_wait_autoneg(struct e1000_hw *hw); 119 static int e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t * speed, 120 uint16_t * duplex); 121 static int e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, 122 uint16_t * phy_data); 123 static int e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, 124 uint16_t phy_data); 125 static int32_t e1000_phy_hw_reset(struct e1000_hw *hw); 126 static int e1000_phy_reset(struct e1000_hw *hw); 127 static int e1000_detect_gig_phy(struct e1000_hw *hw); 128 static void e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw); 129 static void e1000_set_media_type(struct e1000_hw *hw); 130 131 static int32_t e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask); 132 static int32_t e1000_check_phy_reset_block(struct e1000_hw *hw); 133 #define E1000_WRITE_REG(a, reg, value) (writel((value), ((a)->hw_addr + E1000_##reg))) 134 #define E1000_READ_REG(a, reg) (readl((a)->hw_addr + E1000_##reg)) 135 #define E1000_WRITE_REG_ARRAY(a, reg, offset, value) (\ 136 writel((value), ((a)->hw_addr + E1000_##reg + ((offset) << 2)))) 137 #define E1000_READ_REG_ARRAY(a, reg, offset) ( \ 138 readl((a)->hw_addr + E1000_##reg + ((offset) << 2))) 139 #define E1000_WRITE_FLUSH(a) {uint32_t x; x = E1000_READ_REG(a, STATUS);} 140 141 #ifndef CONFIG_AP1000 /* remove for warnings */ 142 static int32_t e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset, 143 uint16_t words, 144 uint16_t *data); 145 /****************************************************************************** 146 * Raises the EEPROM's clock input. 147 * 148 * hw - Struct containing variables accessed by shared code 149 * eecd - EECD's current value 150 *****************************************************************************/ 151 static void 152 e1000_raise_ee_clk(struct e1000_hw *hw, uint32_t * eecd) 153 { 154 /* Raise the clock input to the EEPROM (by setting the SK bit), and then 155 * wait 50 microseconds. 156 */ 157 *eecd = *eecd | E1000_EECD_SK; 158 E1000_WRITE_REG(hw, EECD, *eecd); 159 E1000_WRITE_FLUSH(hw); 160 udelay(50); 161 } 162 163 /****************************************************************************** 164 * Lowers the EEPROM's clock input. 165 * 166 * hw - Struct containing variables accessed by shared code 167 * eecd - EECD's current value 168 *****************************************************************************/ 169 static void 170 e1000_lower_ee_clk(struct e1000_hw *hw, uint32_t * eecd) 171 { 172 /* Lower the clock input to the EEPROM (by clearing the SK bit), and then 173 * wait 50 microseconds. 174 */ 175 *eecd = *eecd & ~E1000_EECD_SK; 176 E1000_WRITE_REG(hw, EECD, *eecd); 177 E1000_WRITE_FLUSH(hw); 178 udelay(50); 179 } 180 181 /****************************************************************************** 182 * Shift data bits out to the EEPROM. 183 * 184 * hw - Struct containing variables accessed by shared code 185 * data - data to send to the EEPROM 186 * count - number of bits to shift out 187 *****************************************************************************/ 188 static void 189 e1000_shift_out_ee_bits(struct e1000_hw *hw, uint16_t data, uint16_t count) 190 { 191 uint32_t eecd; 192 uint32_t mask; 193 194 /* We need to shift "count" bits out to the EEPROM. So, value in the 195 * "data" parameter will be shifted out to the EEPROM one bit at a time. 196 * In order to do this, "data" must be broken down into bits. 197 */ 198 mask = 0x01 << (count - 1); 199 eecd = E1000_READ_REG(hw, EECD); 200 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI); 201 do { 202 /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1", 203 * and then raising and then lowering the clock (the SK bit controls 204 * the clock input to the EEPROM). A "0" is shifted out to the EEPROM 205 * by setting "DI" to "0" and then raising and then lowering the clock. 206 */ 207 eecd &= ~E1000_EECD_DI; 208 209 if (data & mask) 210 eecd |= E1000_EECD_DI; 211 212 E1000_WRITE_REG(hw, EECD, eecd); 213 E1000_WRITE_FLUSH(hw); 214 215 udelay(50); 216 217 e1000_raise_ee_clk(hw, &eecd); 218 e1000_lower_ee_clk(hw, &eecd); 219 220 mask = mask >> 1; 221 222 } while (mask); 223 224 /* We leave the "DI" bit set to "0" when we leave this routine. */ 225 eecd &= ~E1000_EECD_DI; 226 E1000_WRITE_REG(hw, EECD, eecd); 227 } 228 229 /****************************************************************************** 230 * Shift data bits in from the EEPROM 231 * 232 * hw - Struct containing variables accessed by shared code 233 *****************************************************************************/ 234 static uint16_t 235 e1000_shift_in_ee_bits(struct e1000_hw *hw, uint16_t count) 236 { 237 uint32_t eecd; 238 uint32_t i; 239 uint16_t data; 240 241 /* In order to read a register from the EEPROM, we need to shift 'count' 242 * bits in from the EEPROM. Bits are "shifted in" by raising the clock 243 * input to the EEPROM (setting the SK bit), and then reading the 244 * value of the "DO" bit. During this "shifting in" process the 245 * "DI" bit should always be clear. 246 */ 247 248 eecd = E1000_READ_REG(hw, EECD); 249 250 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI); 251 data = 0; 252 253 for (i = 0; i < count; i++) { 254 data = data << 1; 255 e1000_raise_ee_clk(hw, &eecd); 256 257 eecd = E1000_READ_REG(hw, EECD); 258 259 eecd &= ~(E1000_EECD_DI); 260 if (eecd & E1000_EECD_DO) 261 data |= 1; 262 263 e1000_lower_ee_clk(hw, &eecd); 264 } 265 266 return data; 267 } 268 269 /****************************************************************************** 270 * Returns EEPROM to a "standby" state 271 * 272 * hw - Struct containing variables accessed by shared code 273 *****************************************************************************/ 274 static void 275 e1000_standby_eeprom(struct e1000_hw *hw) 276 { 277 struct e1000_eeprom_info *eeprom = &hw->eeprom; 278 uint32_t eecd; 279 280 eecd = E1000_READ_REG(hw, EECD); 281 282 if (eeprom->type == e1000_eeprom_microwire) { 283 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); 284 E1000_WRITE_REG(hw, EECD, eecd); 285 E1000_WRITE_FLUSH(hw); 286 udelay(eeprom->delay_usec); 287 288 /* Clock high */ 289 eecd |= E1000_EECD_SK; 290 E1000_WRITE_REG(hw, EECD, eecd); 291 E1000_WRITE_FLUSH(hw); 292 udelay(eeprom->delay_usec); 293 294 /* Select EEPROM */ 295 eecd |= E1000_EECD_CS; 296 E1000_WRITE_REG(hw, EECD, eecd); 297 E1000_WRITE_FLUSH(hw); 298 udelay(eeprom->delay_usec); 299 300 /* Clock low */ 301 eecd &= ~E1000_EECD_SK; 302 E1000_WRITE_REG(hw, EECD, eecd); 303 E1000_WRITE_FLUSH(hw); 304 udelay(eeprom->delay_usec); 305 } else if (eeprom->type == e1000_eeprom_spi) { 306 /* Toggle CS to flush commands */ 307 eecd |= E1000_EECD_CS; 308 E1000_WRITE_REG(hw, EECD, eecd); 309 E1000_WRITE_FLUSH(hw); 310 udelay(eeprom->delay_usec); 311 eecd &= ~E1000_EECD_CS; 312 E1000_WRITE_REG(hw, EECD, eecd); 313 E1000_WRITE_FLUSH(hw); 314 udelay(eeprom->delay_usec); 315 } 316 } 317 318 /*************************************************************************** 319 * Description: Determines if the onboard NVM is FLASH or EEPROM. 320 * 321 * hw - Struct containing variables accessed by shared code 322 ****************************************************************************/ 323 static boolean_t e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw) 324 { 325 uint32_t eecd = 0; 326 327 DEBUGFUNC(); 328 329 if (hw->mac_type == e1000_ich8lan) 330 return FALSE; 331 332 if (hw->mac_type == e1000_82573) { 333 eecd = E1000_READ_REG(hw, EECD); 334 335 /* Isolate bits 15 & 16 */ 336 eecd = ((eecd >> 15) & 0x03); 337 338 /* If both bits are set, device is Flash type */ 339 if (eecd == 0x03) 340 return FALSE; 341 } 342 return TRUE; 343 } 344 345 /****************************************************************************** 346 * Prepares EEPROM for access 347 * 348 * hw - Struct containing variables accessed by shared code 349 * 350 * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This 351 * function should be called before issuing a command to the EEPROM. 352 *****************************************************************************/ 353 static int32_t 354 e1000_acquire_eeprom(struct e1000_hw *hw) 355 { 356 struct e1000_eeprom_info *eeprom = &hw->eeprom; 357 uint32_t eecd, i = 0; 358 359 DEBUGFUNC(); 360 361 if (e1000_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM)) 362 return -E1000_ERR_SWFW_SYNC; 363 eecd = E1000_READ_REG(hw, EECD); 364 365 if (hw->mac_type != e1000_82573) { 366 /* Request EEPROM Access */ 367 if (hw->mac_type > e1000_82544) { 368 eecd |= E1000_EECD_REQ; 369 E1000_WRITE_REG(hw, EECD, eecd); 370 eecd = E1000_READ_REG(hw, EECD); 371 while ((!(eecd & E1000_EECD_GNT)) && 372 (i < E1000_EEPROM_GRANT_ATTEMPTS)) { 373 i++; 374 udelay(5); 375 eecd = E1000_READ_REG(hw, EECD); 376 } 377 if (!(eecd & E1000_EECD_GNT)) { 378 eecd &= ~E1000_EECD_REQ; 379 E1000_WRITE_REG(hw, EECD, eecd); 380 DEBUGOUT("Could not acquire EEPROM grant\n"); 381 return -E1000_ERR_EEPROM; 382 } 383 } 384 } 385 386 /* Setup EEPROM for Read/Write */ 387 388 if (eeprom->type == e1000_eeprom_microwire) { 389 /* Clear SK and DI */ 390 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK); 391 E1000_WRITE_REG(hw, EECD, eecd); 392 393 /* Set CS */ 394 eecd |= E1000_EECD_CS; 395 E1000_WRITE_REG(hw, EECD, eecd); 396 } else if (eeprom->type == e1000_eeprom_spi) { 397 /* Clear SK and CS */ 398 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); 399 E1000_WRITE_REG(hw, EECD, eecd); 400 udelay(1); 401 } 402 403 return E1000_SUCCESS; 404 } 405 406 /****************************************************************************** 407 * Sets up eeprom variables in the hw struct. Must be called after mac_type 408 * is configured. Additionally, if this is ICH8, the flash controller GbE 409 * registers must be mapped, or this will crash. 410 * 411 * hw - Struct containing variables accessed by shared code 412 *****************************************************************************/ 413 static int32_t e1000_init_eeprom_params(struct e1000_hw *hw) 414 { 415 struct e1000_eeprom_info *eeprom = &hw->eeprom; 416 uint32_t eecd = E1000_READ_REG(hw, EECD); 417 int32_t ret_val = E1000_SUCCESS; 418 uint16_t eeprom_size; 419 420 DEBUGFUNC(); 421 422 switch (hw->mac_type) { 423 case e1000_82542_rev2_0: 424 case e1000_82542_rev2_1: 425 case e1000_82543: 426 case e1000_82544: 427 eeprom->type = e1000_eeprom_microwire; 428 eeprom->word_size = 64; 429 eeprom->opcode_bits = 3; 430 eeprom->address_bits = 6; 431 eeprom->delay_usec = 50; 432 eeprom->use_eerd = FALSE; 433 eeprom->use_eewr = FALSE; 434 break; 435 case e1000_82540: 436 case e1000_82545: 437 case e1000_82545_rev_3: 438 case e1000_82546: 439 case e1000_82546_rev_3: 440 eeprom->type = e1000_eeprom_microwire; 441 eeprom->opcode_bits = 3; 442 eeprom->delay_usec = 50; 443 if (eecd & E1000_EECD_SIZE) { 444 eeprom->word_size = 256; 445 eeprom->address_bits = 8; 446 } else { 447 eeprom->word_size = 64; 448 eeprom->address_bits = 6; 449 } 450 eeprom->use_eerd = FALSE; 451 eeprom->use_eewr = FALSE; 452 break; 453 case e1000_82541: 454 case e1000_82541_rev_2: 455 case e1000_82547: 456 case e1000_82547_rev_2: 457 if (eecd & E1000_EECD_TYPE) { 458 eeprom->type = e1000_eeprom_spi; 459 eeprom->opcode_bits = 8; 460 eeprom->delay_usec = 1; 461 if (eecd & E1000_EECD_ADDR_BITS) { 462 eeprom->page_size = 32; 463 eeprom->address_bits = 16; 464 } else { 465 eeprom->page_size = 8; 466 eeprom->address_bits = 8; 467 } 468 } else { 469 eeprom->type = e1000_eeprom_microwire; 470 eeprom->opcode_bits = 3; 471 eeprom->delay_usec = 50; 472 if (eecd & E1000_EECD_ADDR_BITS) { 473 eeprom->word_size = 256; 474 eeprom->address_bits = 8; 475 } else { 476 eeprom->word_size = 64; 477 eeprom->address_bits = 6; 478 } 479 } 480 eeprom->use_eerd = FALSE; 481 eeprom->use_eewr = FALSE; 482 break; 483 case e1000_82571: 484 case e1000_82572: 485 eeprom->type = e1000_eeprom_spi; 486 eeprom->opcode_bits = 8; 487 eeprom->delay_usec = 1; 488 if (eecd & E1000_EECD_ADDR_BITS) { 489 eeprom->page_size = 32; 490 eeprom->address_bits = 16; 491 } else { 492 eeprom->page_size = 8; 493 eeprom->address_bits = 8; 494 } 495 eeprom->use_eerd = FALSE; 496 eeprom->use_eewr = FALSE; 497 break; 498 case e1000_82573: 499 eeprom->type = e1000_eeprom_spi; 500 eeprom->opcode_bits = 8; 501 eeprom->delay_usec = 1; 502 if (eecd & E1000_EECD_ADDR_BITS) { 503 eeprom->page_size = 32; 504 eeprom->address_bits = 16; 505 } else { 506 eeprom->page_size = 8; 507 eeprom->address_bits = 8; 508 } 509 eeprom->use_eerd = TRUE; 510 eeprom->use_eewr = TRUE; 511 if (e1000_is_onboard_nvm_eeprom(hw) == FALSE) { 512 eeprom->type = e1000_eeprom_flash; 513 eeprom->word_size = 2048; 514 515 /* Ensure that the Autonomous FLASH update bit is cleared due to 516 * Flash update issue on parts which use a FLASH for NVM. */ 517 eecd &= ~E1000_EECD_AUPDEN; 518 E1000_WRITE_REG(hw, EECD, eecd); 519 } 520 break; 521 case e1000_80003es2lan: 522 eeprom->type = e1000_eeprom_spi; 523 eeprom->opcode_bits = 8; 524 eeprom->delay_usec = 1; 525 if (eecd & E1000_EECD_ADDR_BITS) { 526 eeprom->page_size = 32; 527 eeprom->address_bits = 16; 528 } else { 529 eeprom->page_size = 8; 530 eeprom->address_bits = 8; 531 } 532 eeprom->use_eerd = TRUE; 533 eeprom->use_eewr = FALSE; 534 break; 535 536 /* ich8lan does not support currently. if needed, please 537 * add corresponding code and functions. 538 */ 539 #if 0 540 case e1000_ich8lan: 541 { 542 int32_t i = 0; 543 544 eeprom->type = e1000_eeprom_ich8; 545 eeprom->use_eerd = FALSE; 546 eeprom->use_eewr = FALSE; 547 eeprom->word_size = E1000_SHADOW_RAM_WORDS; 548 uint32_t flash_size = E1000_READ_ICH_FLASH_REG(hw, 549 ICH_FLASH_GFPREG); 550 /* Zero the shadow RAM structure. But don't load it from NVM 551 * so as to save time for driver init */ 552 if (hw->eeprom_shadow_ram != NULL) { 553 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) { 554 hw->eeprom_shadow_ram[i].modified = FALSE; 555 hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF; 556 } 557 } 558 559 hw->flash_base_addr = (flash_size & ICH_GFPREG_BASE_MASK) * 560 ICH_FLASH_SECTOR_SIZE; 561 562 hw->flash_bank_size = ((flash_size >> 16) 563 & ICH_GFPREG_BASE_MASK) + 1; 564 hw->flash_bank_size -= (flash_size & ICH_GFPREG_BASE_MASK); 565 566 hw->flash_bank_size *= ICH_FLASH_SECTOR_SIZE; 567 568 hw->flash_bank_size /= 2 * sizeof(uint16_t); 569 break; 570 } 571 #endif 572 default: 573 break; 574 } 575 576 if (eeprom->type == e1000_eeprom_spi) { 577 /* eeprom_size will be an enum [0..8] that maps 578 * to eeprom sizes 128B to 579 * 32KB (incremented by powers of 2). 580 */ 581 if (hw->mac_type <= e1000_82547_rev_2) { 582 /* Set to default value for initial eeprom read. */ 583 eeprom->word_size = 64; 584 ret_val = e1000_read_eeprom(hw, EEPROM_CFG, 1, 585 &eeprom_size); 586 if (ret_val) 587 return ret_val; 588 eeprom_size = (eeprom_size & EEPROM_SIZE_MASK) 589 >> EEPROM_SIZE_SHIFT; 590 /* 256B eeprom size was not supported in earlier 591 * hardware, so we bump eeprom_size up one to 592 * ensure that "1" (which maps to 256B) is never 593 * the result used in the shifting logic below. */ 594 if (eeprom_size) 595 eeprom_size++; 596 } else { 597 eeprom_size = (uint16_t)((eecd & 598 E1000_EECD_SIZE_EX_MASK) >> 599 E1000_EECD_SIZE_EX_SHIFT); 600 } 601 602 eeprom->word_size = 1 << (eeprom_size + EEPROM_WORD_SIZE_SHIFT); 603 } 604 return ret_val; 605 } 606 607 /****************************************************************************** 608 * Polls the status bit (bit 1) of the EERD to determine when the read is done. 609 * 610 * hw - Struct containing variables accessed by shared code 611 *****************************************************************************/ 612 static int32_t 613 e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd) 614 { 615 uint32_t attempts = 100000; 616 uint32_t i, reg = 0; 617 int32_t done = E1000_ERR_EEPROM; 618 619 for (i = 0; i < attempts; i++) { 620 if (eerd == E1000_EEPROM_POLL_READ) 621 reg = E1000_READ_REG(hw, EERD); 622 else 623 reg = E1000_READ_REG(hw, EEWR); 624 625 if (reg & E1000_EEPROM_RW_REG_DONE) { 626 done = E1000_SUCCESS; 627 break; 628 } 629 udelay(5); 630 } 631 632 return done; 633 } 634 635 /****************************************************************************** 636 * Reads a 16 bit word from the EEPROM using the EERD register. 637 * 638 * hw - Struct containing variables accessed by shared code 639 * offset - offset of word in the EEPROM to read 640 * data - word read from the EEPROM 641 * words - number of words to read 642 *****************************************************************************/ 643 static int32_t 644 e1000_read_eeprom_eerd(struct e1000_hw *hw, 645 uint16_t offset, 646 uint16_t words, 647 uint16_t *data) 648 { 649 uint32_t i, eerd = 0; 650 int32_t error = 0; 651 652 for (i = 0; i < words; i++) { 653 eerd = ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) + 654 E1000_EEPROM_RW_REG_START; 655 656 E1000_WRITE_REG(hw, EERD, eerd); 657 error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_READ); 658 659 if (error) 660 break; 661 data[i] = (E1000_READ_REG(hw, EERD) >> 662 E1000_EEPROM_RW_REG_DATA); 663 664 } 665 666 return error; 667 } 668 669 static void 670 e1000_release_eeprom(struct e1000_hw *hw) 671 { 672 uint32_t eecd; 673 674 DEBUGFUNC(); 675 676 eecd = E1000_READ_REG(hw, EECD); 677 678 if (hw->eeprom.type == e1000_eeprom_spi) { 679 eecd |= E1000_EECD_CS; /* Pull CS high */ 680 eecd &= ~E1000_EECD_SK; /* Lower SCK */ 681 682 E1000_WRITE_REG(hw, EECD, eecd); 683 684 udelay(hw->eeprom.delay_usec); 685 } else if (hw->eeprom.type == e1000_eeprom_microwire) { 686 /* cleanup eeprom */ 687 688 /* CS on Microwire is active-high */ 689 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI); 690 691 E1000_WRITE_REG(hw, EECD, eecd); 692 693 /* Rising edge of clock */ 694 eecd |= E1000_EECD_SK; 695 E1000_WRITE_REG(hw, EECD, eecd); 696 E1000_WRITE_FLUSH(hw); 697 udelay(hw->eeprom.delay_usec); 698 699 /* Falling edge of clock */ 700 eecd &= ~E1000_EECD_SK; 701 E1000_WRITE_REG(hw, EECD, eecd); 702 E1000_WRITE_FLUSH(hw); 703 udelay(hw->eeprom.delay_usec); 704 } 705 706 /* Stop requesting EEPROM access */ 707 if (hw->mac_type > e1000_82544) { 708 eecd &= ~E1000_EECD_REQ; 709 E1000_WRITE_REG(hw, EECD, eecd); 710 } 711 } 712 /****************************************************************************** 713 * Reads a 16 bit word from the EEPROM. 714 * 715 * hw - Struct containing variables accessed by shared code 716 *****************************************************************************/ 717 static int32_t 718 e1000_spi_eeprom_ready(struct e1000_hw *hw) 719 { 720 uint16_t retry_count = 0; 721 uint8_t spi_stat_reg; 722 723 DEBUGFUNC(); 724 725 /* Read "Status Register" repeatedly until the LSB is cleared. The 726 * EEPROM will signal that the command has been completed by clearing 727 * bit 0 of the internal status register. If it's not cleared within 728 * 5 milliseconds, then error out. 729 */ 730 retry_count = 0; 731 do { 732 e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI, 733 hw->eeprom.opcode_bits); 734 spi_stat_reg = (uint8_t)e1000_shift_in_ee_bits(hw, 8); 735 if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI)) 736 break; 737 738 udelay(5); 739 retry_count += 5; 740 741 e1000_standby_eeprom(hw); 742 } while (retry_count < EEPROM_MAX_RETRY_SPI); 743 744 /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and 745 * only 0-5mSec on 5V devices) 746 */ 747 if (retry_count >= EEPROM_MAX_RETRY_SPI) { 748 DEBUGOUT("SPI EEPROM Status error\n"); 749 return -E1000_ERR_EEPROM; 750 } 751 752 return E1000_SUCCESS; 753 } 754 755 /****************************************************************************** 756 * Reads a 16 bit word from the EEPROM. 757 * 758 * hw - Struct containing variables accessed by shared code 759 * offset - offset of word in the EEPROM to read 760 * data - word read from the EEPROM 761 *****************************************************************************/ 762 static int32_t 763 e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset, 764 uint16_t words, uint16_t *data) 765 { 766 struct e1000_eeprom_info *eeprom = &hw->eeprom; 767 uint32_t i = 0; 768 769 DEBUGFUNC(); 770 771 /* If eeprom is not yet detected, do so now */ 772 if (eeprom->word_size == 0) 773 e1000_init_eeprom_params(hw); 774 775 /* A check for invalid values: offset too large, too many words, 776 * and not enough words. 777 */ 778 if ((offset >= eeprom->word_size) || 779 (words > eeprom->word_size - offset) || 780 (words == 0)) { 781 DEBUGOUT("\"words\" parameter out of bounds." 782 "Words = %d, size = %d\n", offset, eeprom->word_size); 783 return -E1000_ERR_EEPROM; 784 } 785 786 /* EEPROM's that don't use EERD to read require us to bit-bang the SPI 787 * directly. In this case, we need to acquire the EEPROM so that 788 * FW or other port software does not interrupt. 789 */ 790 if (e1000_is_onboard_nvm_eeprom(hw) == TRUE && 791 hw->eeprom.use_eerd == FALSE) { 792 793 /* Prepare the EEPROM for bit-bang reading */ 794 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS) 795 return -E1000_ERR_EEPROM; 796 } 797 798 /* Eerd register EEPROM access requires no eeprom aquire/release */ 799 if (eeprom->use_eerd == TRUE) 800 return e1000_read_eeprom_eerd(hw, offset, words, data); 801 802 /* ich8lan does not support currently. if needed, please 803 * add corresponding code and functions. 804 */ 805 #if 0 806 /* ICH EEPROM access is done via the ICH flash controller */ 807 if (eeprom->type == e1000_eeprom_ich8) 808 return e1000_read_eeprom_ich8(hw, offset, words, data); 809 #endif 810 /* Set up the SPI or Microwire EEPROM for bit-bang reading. We have 811 * acquired the EEPROM at this point, so any returns should relase it */ 812 if (eeprom->type == e1000_eeprom_spi) { 813 uint16_t word_in; 814 uint8_t read_opcode = EEPROM_READ_OPCODE_SPI; 815 816 if (e1000_spi_eeprom_ready(hw)) { 817 e1000_release_eeprom(hw); 818 return -E1000_ERR_EEPROM; 819 } 820 821 e1000_standby_eeprom(hw); 822 823 /* Some SPI eeproms use the 8th address bit embedded in 824 * the opcode */ 825 if ((eeprom->address_bits == 8) && (offset >= 128)) 826 read_opcode |= EEPROM_A8_OPCODE_SPI; 827 828 /* Send the READ command (opcode + addr) */ 829 e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits); 830 e1000_shift_out_ee_bits(hw, (uint16_t)(offset*2), 831 eeprom->address_bits); 832 833 /* Read the data. The address of the eeprom internally 834 * increments with each byte (spi) being read, saving on the 835 * overhead of eeprom setup and tear-down. The address 836 * counter will roll over if reading beyond the size of 837 * the eeprom, thus allowing the entire memory to be read 838 * starting from any offset. */ 839 for (i = 0; i < words; i++) { 840 word_in = e1000_shift_in_ee_bits(hw, 16); 841 data[i] = (word_in >> 8) | (word_in << 8); 842 } 843 } else if (eeprom->type == e1000_eeprom_microwire) { 844 for (i = 0; i < words; i++) { 845 /* Send the READ command (opcode + addr) */ 846 e1000_shift_out_ee_bits(hw, 847 EEPROM_READ_OPCODE_MICROWIRE, 848 eeprom->opcode_bits); 849 e1000_shift_out_ee_bits(hw, (uint16_t)(offset + i), 850 eeprom->address_bits); 851 852 /* Read the data. For microwire, each word requires 853 * the overhead of eeprom setup and tear-down. */ 854 data[i] = e1000_shift_in_ee_bits(hw, 16); 855 e1000_standby_eeprom(hw); 856 } 857 } 858 859 /* End this read operation */ 860 e1000_release_eeprom(hw); 861 862 return E1000_SUCCESS; 863 } 864 865 /****************************************************************************** 866 * Verifies that the EEPROM has a valid checksum 867 * 868 * hw - Struct containing variables accessed by shared code 869 * 870 * Reads the first 64 16 bit words of the EEPROM and sums the values read. 871 * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is 872 * valid. 873 *****************************************************************************/ 874 static int 875 e1000_validate_eeprom_checksum(struct eth_device *nic) 876 { 877 struct e1000_hw *hw = nic->priv; 878 uint16_t checksum = 0; 879 uint16_t i, eeprom_data; 880 881 DEBUGFUNC(); 882 883 for (i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) { 884 if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) { 885 DEBUGOUT("EEPROM Read Error\n"); 886 return -E1000_ERR_EEPROM; 887 } 888 checksum += eeprom_data; 889 } 890 891 if (checksum == (uint16_t) EEPROM_SUM) { 892 return 0; 893 } else { 894 DEBUGOUT("EEPROM Checksum Invalid\n"); 895 return -E1000_ERR_EEPROM; 896 } 897 } 898 899 /***************************************************************************** 900 * Set PHY to class A mode 901 * Assumes the following operations will follow to enable the new class mode. 902 * 1. Do a PHY soft reset 903 * 2. Restart auto-negotiation or force link. 904 * 905 * hw - Struct containing variables accessed by shared code 906 ****************************************************************************/ 907 static int32_t 908 e1000_set_phy_mode(struct e1000_hw *hw) 909 { 910 int32_t ret_val; 911 uint16_t eeprom_data; 912 913 DEBUGFUNC(); 914 915 if ((hw->mac_type == e1000_82545_rev_3) && 916 (hw->media_type == e1000_media_type_copper)) { 917 ret_val = e1000_read_eeprom(hw, EEPROM_PHY_CLASS_WORD, 918 1, &eeprom_data); 919 if (ret_val) 920 return ret_val; 921 922 if ((eeprom_data != EEPROM_RESERVED_WORD) && 923 (eeprom_data & EEPROM_PHY_CLASS_A)) { 924 ret_val = e1000_write_phy_reg(hw, 925 M88E1000_PHY_PAGE_SELECT, 0x000B); 926 if (ret_val) 927 return ret_val; 928 ret_val = e1000_write_phy_reg(hw, 929 M88E1000_PHY_GEN_CONTROL, 0x8104); 930 if (ret_val) 931 return ret_val; 932 933 hw->phy_reset_disable = FALSE; 934 } 935 } 936 937 return E1000_SUCCESS; 938 } 939 #endif /* #ifndef CONFIG_AP1000 */ 940 941 /*************************************************************************** 942 * 943 * Obtaining software semaphore bit (SMBI) before resetting PHY. 944 * 945 * hw: Struct containing variables accessed by shared code 946 * 947 * returns: - E1000_ERR_RESET if fail to obtain semaphore. 948 * E1000_SUCCESS at any other case. 949 * 950 ***************************************************************************/ 951 static int32_t 952 e1000_get_software_semaphore(struct e1000_hw *hw) 953 { 954 int32_t timeout = hw->eeprom.word_size + 1; 955 uint32_t swsm; 956 957 DEBUGFUNC(); 958 959 if (hw->mac_type != e1000_80003es2lan) 960 return E1000_SUCCESS; 961 962 while (timeout) { 963 swsm = E1000_READ_REG(hw, SWSM); 964 /* If SMBI bit cleared, it is now set and we hold 965 * the semaphore */ 966 if (!(swsm & E1000_SWSM_SMBI)) 967 break; 968 mdelay(1); 969 timeout--; 970 } 971 972 if (!timeout) { 973 DEBUGOUT("Driver can't access device - SMBI bit is set.\n"); 974 return -E1000_ERR_RESET; 975 } 976 977 return E1000_SUCCESS; 978 } 979 980 /*************************************************************************** 981 * This function clears HW semaphore bits. 982 * 983 * hw: Struct containing variables accessed by shared code 984 * 985 * returns: - None. 986 * 987 ***************************************************************************/ 988 static void 989 e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw) 990 { 991 uint32_t swsm; 992 993 DEBUGFUNC(); 994 995 if (!hw->eeprom_semaphore_present) 996 return; 997 998 swsm = E1000_READ_REG(hw, SWSM); 999 if (hw->mac_type == e1000_80003es2lan) { 1000 /* Release both semaphores. */ 1001 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI); 1002 } else 1003 swsm &= ~(E1000_SWSM_SWESMBI); 1004 E1000_WRITE_REG(hw, SWSM, swsm); 1005 } 1006 1007 /*************************************************************************** 1008 * 1009 * Using the combination of SMBI and SWESMBI semaphore bits when resetting 1010 * adapter or Eeprom access. 1011 * 1012 * hw: Struct containing variables accessed by shared code 1013 * 1014 * returns: - E1000_ERR_EEPROM if fail to access EEPROM. 1015 * E1000_SUCCESS at any other case. 1016 * 1017 ***************************************************************************/ 1018 static int32_t 1019 e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw) 1020 { 1021 int32_t timeout; 1022 uint32_t swsm; 1023 1024 DEBUGFUNC(); 1025 1026 if (!hw->eeprom_semaphore_present) 1027 return E1000_SUCCESS; 1028 1029 if (hw->mac_type == e1000_80003es2lan) { 1030 /* Get the SW semaphore. */ 1031 if (e1000_get_software_semaphore(hw) != E1000_SUCCESS) 1032 return -E1000_ERR_EEPROM; 1033 } 1034 1035 /* Get the FW semaphore. */ 1036 timeout = hw->eeprom.word_size + 1; 1037 while (timeout) { 1038 swsm = E1000_READ_REG(hw, SWSM); 1039 swsm |= E1000_SWSM_SWESMBI; 1040 E1000_WRITE_REG(hw, SWSM, swsm); 1041 /* if we managed to set the bit we got the semaphore. */ 1042 swsm = E1000_READ_REG(hw, SWSM); 1043 if (swsm & E1000_SWSM_SWESMBI) 1044 break; 1045 1046 udelay(50); 1047 timeout--; 1048 } 1049 1050 if (!timeout) { 1051 /* Release semaphores */ 1052 e1000_put_hw_eeprom_semaphore(hw); 1053 DEBUGOUT("Driver can't access the Eeprom - " 1054 "SWESMBI bit is set.\n"); 1055 return -E1000_ERR_EEPROM; 1056 } 1057 1058 return E1000_SUCCESS; 1059 } 1060 1061 static int32_t 1062 e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask) 1063 { 1064 uint32_t swfw_sync = 0; 1065 uint32_t swmask = mask; 1066 uint32_t fwmask = mask << 16; 1067 int32_t timeout = 200; 1068 1069 DEBUGFUNC(); 1070 while (timeout) { 1071 if (e1000_get_hw_eeprom_semaphore(hw)) 1072 return -E1000_ERR_SWFW_SYNC; 1073 1074 swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC); 1075 if (!(swfw_sync & (fwmask | swmask))) 1076 break; 1077 1078 /* firmware currently using resource (fwmask) */ 1079 /* or other software thread currently using resource (swmask) */ 1080 e1000_put_hw_eeprom_semaphore(hw); 1081 mdelay(5); 1082 timeout--; 1083 } 1084 1085 if (!timeout) { 1086 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n"); 1087 return -E1000_ERR_SWFW_SYNC; 1088 } 1089 1090 swfw_sync |= swmask; 1091 E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync); 1092 1093 e1000_put_hw_eeprom_semaphore(hw); 1094 return E1000_SUCCESS; 1095 } 1096 1097 /****************************************************************************** 1098 * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the 1099 * second function of dual function devices 1100 * 1101 * nic - Struct containing variables accessed by shared code 1102 *****************************************************************************/ 1103 static int 1104 e1000_read_mac_addr(struct eth_device *nic) 1105 { 1106 #ifndef CONFIG_AP1000 1107 struct e1000_hw *hw = nic->priv; 1108 uint16_t offset; 1109 uint16_t eeprom_data; 1110 int i; 1111 1112 DEBUGFUNC(); 1113 1114 for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) { 1115 offset = i >> 1; 1116 if (e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) { 1117 DEBUGOUT("EEPROM Read Error\n"); 1118 return -E1000_ERR_EEPROM; 1119 } 1120 nic->enetaddr[i] = eeprom_data & 0xff; 1121 nic->enetaddr[i + 1] = (eeprom_data >> 8) & 0xff; 1122 } 1123 if ((hw->mac_type == e1000_82546) && 1124 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) { 1125 /* Invert the last bit if this is the second device */ 1126 nic->enetaddr[5] += 1; 1127 } 1128 #ifdef CONFIG_E1000_FALLBACK_MAC 1129 if ( *(u32*)(nic->enetaddr) == 0 || *(u32*)(nic->enetaddr) == ~0 ) { 1130 unsigned char fb_mac[NODE_ADDRESS_SIZE] = CONFIG_E1000_FALLBACK_MAC; 1131 1132 memcpy (nic->enetaddr, fb_mac, NODE_ADDRESS_SIZE); 1133 } 1134 #endif 1135 #else 1136 /* 1137 * The AP1000's e1000 has no eeprom; the MAC address is stored in the 1138 * environment variables. Currently this does not support the addition 1139 * of a PMC e1000 card, which is certainly a possibility, so this should 1140 * be updated to properly use the env variable only for the onboard e1000 1141 */ 1142 1143 int ii; 1144 char *s, *e; 1145 1146 DEBUGFUNC(); 1147 1148 s = getenv ("ethaddr"); 1149 if (s == NULL) { 1150 return -E1000_ERR_EEPROM; 1151 } else { 1152 for(ii = 0; ii < 6; ii++) { 1153 nic->enetaddr[ii] = s ? simple_strtoul (s, &e, 16) : 0; 1154 if (s){ 1155 s = (*e) ? e + 1 : e; 1156 } 1157 } 1158 } 1159 #endif 1160 return 0; 1161 } 1162 1163 /****************************************************************************** 1164 * Initializes receive address filters. 1165 * 1166 * hw - Struct containing variables accessed by shared code 1167 * 1168 * Places the MAC address in receive address register 0 and clears the rest 1169 * of the receive addresss registers. Clears the multicast table. Assumes 1170 * the receiver is in reset when the routine is called. 1171 *****************************************************************************/ 1172 static void 1173 e1000_init_rx_addrs(struct eth_device *nic) 1174 { 1175 struct e1000_hw *hw = nic->priv; 1176 uint32_t i; 1177 uint32_t addr_low; 1178 uint32_t addr_high; 1179 1180 DEBUGFUNC(); 1181 1182 /* Setup the receive address. */ 1183 DEBUGOUT("Programming MAC Address into RAR[0]\n"); 1184 addr_low = (nic->enetaddr[0] | 1185 (nic->enetaddr[1] << 8) | 1186 (nic->enetaddr[2] << 16) | (nic->enetaddr[3] << 24)); 1187 1188 addr_high = (nic->enetaddr[4] | (nic->enetaddr[5] << 8) | E1000_RAH_AV); 1189 1190 E1000_WRITE_REG_ARRAY(hw, RA, 0, addr_low); 1191 E1000_WRITE_REG_ARRAY(hw, RA, 1, addr_high); 1192 1193 /* Zero out the other 15 receive addresses. */ 1194 DEBUGOUT("Clearing RAR[1-15]\n"); 1195 for (i = 1; i < E1000_RAR_ENTRIES; i++) { 1196 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0); 1197 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0); 1198 } 1199 } 1200 1201 /****************************************************************************** 1202 * Clears the VLAN filer table 1203 * 1204 * hw - Struct containing variables accessed by shared code 1205 *****************************************************************************/ 1206 static void 1207 e1000_clear_vfta(struct e1000_hw *hw) 1208 { 1209 uint32_t offset; 1210 1211 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) 1212 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, 0); 1213 } 1214 1215 /****************************************************************************** 1216 * Set the mac type member in the hw struct. 1217 * 1218 * hw - Struct containing variables accessed by shared code 1219 *****************************************************************************/ 1220 int32_t 1221 e1000_set_mac_type(struct e1000_hw *hw) 1222 { 1223 DEBUGFUNC(); 1224 1225 switch (hw->device_id) { 1226 case E1000_DEV_ID_82542: 1227 switch (hw->revision_id) { 1228 case E1000_82542_2_0_REV_ID: 1229 hw->mac_type = e1000_82542_rev2_0; 1230 break; 1231 case E1000_82542_2_1_REV_ID: 1232 hw->mac_type = e1000_82542_rev2_1; 1233 break; 1234 default: 1235 /* Invalid 82542 revision ID */ 1236 return -E1000_ERR_MAC_TYPE; 1237 } 1238 break; 1239 case E1000_DEV_ID_82543GC_FIBER: 1240 case E1000_DEV_ID_82543GC_COPPER: 1241 hw->mac_type = e1000_82543; 1242 break; 1243 case E1000_DEV_ID_82544EI_COPPER: 1244 case E1000_DEV_ID_82544EI_FIBER: 1245 case E1000_DEV_ID_82544GC_COPPER: 1246 case E1000_DEV_ID_82544GC_LOM: 1247 hw->mac_type = e1000_82544; 1248 break; 1249 case E1000_DEV_ID_82540EM: 1250 case E1000_DEV_ID_82540EM_LOM: 1251 case E1000_DEV_ID_82540EP: 1252 case E1000_DEV_ID_82540EP_LOM: 1253 case E1000_DEV_ID_82540EP_LP: 1254 hw->mac_type = e1000_82540; 1255 break; 1256 case E1000_DEV_ID_82545EM_COPPER: 1257 case E1000_DEV_ID_82545EM_FIBER: 1258 hw->mac_type = e1000_82545; 1259 break; 1260 case E1000_DEV_ID_82545GM_COPPER: 1261 case E1000_DEV_ID_82545GM_FIBER: 1262 case E1000_DEV_ID_82545GM_SERDES: 1263 hw->mac_type = e1000_82545_rev_3; 1264 break; 1265 case E1000_DEV_ID_82546EB_COPPER: 1266 case E1000_DEV_ID_82546EB_FIBER: 1267 case E1000_DEV_ID_82546EB_QUAD_COPPER: 1268 hw->mac_type = e1000_82546; 1269 break; 1270 case E1000_DEV_ID_82546GB_COPPER: 1271 case E1000_DEV_ID_82546GB_FIBER: 1272 case E1000_DEV_ID_82546GB_SERDES: 1273 case E1000_DEV_ID_82546GB_PCIE: 1274 case E1000_DEV_ID_82546GB_QUAD_COPPER: 1275 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3: 1276 hw->mac_type = e1000_82546_rev_3; 1277 break; 1278 case E1000_DEV_ID_82541EI: 1279 case E1000_DEV_ID_82541EI_MOBILE: 1280 case E1000_DEV_ID_82541ER_LOM: 1281 hw->mac_type = e1000_82541; 1282 break; 1283 case E1000_DEV_ID_82541ER: 1284 case E1000_DEV_ID_82541GI: 1285 case E1000_DEV_ID_82541GI_LF: 1286 case E1000_DEV_ID_82541GI_MOBILE: 1287 hw->mac_type = e1000_82541_rev_2; 1288 break; 1289 case E1000_DEV_ID_82547EI: 1290 case E1000_DEV_ID_82547EI_MOBILE: 1291 hw->mac_type = e1000_82547; 1292 break; 1293 case E1000_DEV_ID_82547GI: 1294 hw->mac_type = e1000_82547_rev_2; 1295 break; 1296 case E1000_DEV_ID_82571EB_COPPER: 1297 case E1000_DEV_ID_82571EB_FIBER: 1298 case E1000_DEV_ID_82571EB_SERDES: 1299 case E1000_DEV_ID_82571EB_SERDES_DUAL: 1300 case E1000_DEV_ID_82571EB_SERDES_QUAD: 1301 case E1000_DEV_ID_82571EB_QUAD_COPPER: 1302 case E1000_DEV_ID_82571PT_QUAD_COPPER: 1303 case E1000_DEV_ID_82571EB_QUAD_FIBER: 1304 case E1000_DEV_ID_82571EB_QUAD_COPPER_LOWPROFILE: 1305 hw->mac_type = e1000_82571; 1306 break; 1307 case E1000_DEV_ID_82572EI_COPPER: 1308 case E1000_DEV_ID_82572EI_FIBER: 1309 case E1000_DEV_ID_82572EI_SERDES: 1310 case E1000_DEV_ID_82572EI: 1311 hw->mac_type = e1000_82572; 1312 break; 1313 case E1000_DEV_ID_82573E: 1314 case E1000_DEV_ID_82573E_IAMT: 1315 case E1000_DEV_ID_82573L: 1316 hw->mac_type = e1000_82573; 1317 break; 1318 case E1000_DEV_ID_80003ES2LAN_COPPER_SPT: 1319 case E1000_DEV_ID_80003ES2LAN_SERDES_SPT: 1320 case E1000_DEV_ID_80003ES2LAN_COPPER_DPT: 1321 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT: 1322 hw->mac_type = e1000_80003es2lan; 1323 break; 1324 case E1000_DEV_ID_ICH8_IGP_M_AMT: 1325 case E1000_DEV_ID_ICH8_IGP_AMT: 1326 case E1000_DEV_ID_ICH8_IGP_C: 1327 case E1000_DEV_ID_ICH8_IFE: 1328 case E1000_DEV_ID_ICH8_IFE_GT: 1329 case E1000_DEV_ID_ICH8_IFE_G: 1330 case E1000_DEV_ID_ICH8_IGP_M: 1331 hw->mac_type = e1000_ich8lan; 1332 break; 1333 default: 1334 /* Should never have loaded on this device */ 1335 return -E1000_ERR_MAC_TYPE; 1336 } 1337 return E1000_SUCCESS; 1338 } 1339 1340 /****************************************************************************** 1341 * Reset the transmit and receive units; mask and clear all interrupts. 1342 * 1343 * hw - Struct containing variables accessed by shared code 1344 *****************************************************************************/ 1345 void 1346 e1000_reset_hw(struct e1000_hw *hw) 1347 { 1348 uint32_t ctrl; 1349 uint32_t ctrl_ext; 1350 uint32_t icr; 1351 uint32_t manc; 1352 1353 DEBUGFUNC(); 1354 1355 /* For 82542 (rev 2.0), disable MWI before issuing a device reset */ 1356 if (hw->mac_type == e1000_82542_rev2_0) { 1357 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n"); 1358 pci_write_config_word(hw->pdev, PCI_COMMAND, 1359 hw->pci_cmd_word & ~PCI_COMMAND_INVALIDATE); 1360 } 1361 1362 /* Clear interrupt mask to stop board from generating interrupts */ 1363 DEBUGOUT("Masking off all interrupts\n"); 1364 E1000_WRITE_REG(hw, IMC, 0xffffffff); 1365 1366 /* Disable the Transmit and Receive units. Then delay to allow 1367 * any pending transactions to complete before we hit the MAC with 1368 * the global reset. 1369 */ 1370 E1000_WRITE_REG(hw, RCTL, 0); 1371 E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP); 1372 E1000_WRITE_FLUSH(hw); 1373 1374 /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */ 1375 hw->tbi_compatibility_on = FALSE; 1376 1377 /* Delay to allow any outstanding PCI transactions to complete before 1378 * resetting the device 1379 */ 1380 mdelay(10); 1381 1382 /* Issue a global reset to the MAC. This will reset the chip's 1383 * transmit, receive, DMA, and link units. It will not effect 1384 * the current PCI configuration. The global reset bit is self- 1385 * clearing, and should clear within a microsecond. 1386 */ 1387 DEBUGOUT("Issuing a global reset to MAC\n"); 1388 ctrl = E1000_READ_REG(hw, CTRL); 1389 1390 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST)); 1391 1392 /* Force a reload from the EEPROM if necessary */ 1393 if (hw->mac_type < e1000_82540) { 1394 /* Wait for reset to complete */ 1395 udelay(10); 1396 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 1397 ctrl_ext |= E1000_CTRL_EXT_EE_RST; 1398 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 1399 E1000_WRITE_FLUSH(hw); 1400 /* Wait for EEPROM reload */ 1401 mdelay(2); 1402 } else { 1403 /* Wait for EEPROM reload (it happens automatically) */ 1404 mdelay(4); 1405 /* Dissable HW ARPs on ASF enabled adapters */ 1406 manc = E1000_READ_REG(hw, MANC); 1407 manc &= ~(E1000_MANC_ARP_EN); 1408 E1000_WRITE_REG(hw, MANC, manc); 1409 } 1410 1411 /* Clear interrupt mask to stop board from generating interrupts */ 1412 DEBUGOUT("Masking off all interrupts\n"); 1413 E1000_WRITE_REG(hw, IMC, 0xffffffff); 1414 1415 /* Clear any pending interrupt events. */ 1416 icr = E1000_READ_REG(hw, ICR); 1417 1418 /* If MWI was previously enabled, reenable it. */ 1419 if (hw->mac_type == e1000_82542_rev2_0) { 1420 pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word); 1421 } 1422 E1000_WRITE_REG(hw, PBA, E1000_DEFAULT_PBA); 1423 } 1424 1425 /****************************************************************************** 1426 * 1427 * Initialize a number of hardware-dependent bits 1428 * 1429 * hw: Struct containing variables accessed by shared code 1430 * 1431 * This function contains hardware limitation workarounds for PCI-E adapters 1432 * 1433 *****************************************************************************/ 1434 static void 1435 e1000_initialize_hardware_bits(struct e1000_hw *hw) 1436 { 1437 if ((hw->mac_type >= e1000_82571) && 1438 (!hw->initialize_hw_bits_disable)) { 1439 /* Settings common to all PCI-express silicon */ 1440 uint32_t reg_ctrl, reg_ctrl_ext; 1441 uint32_t reg_tarc0, reg_tarc1; 1442 uint32_t reg_tctl; 1443 uint32_t reg_txdctl, reg_txdctl1; 1444 1445 /* link autonegotiation/sync workarounds */ 1446 reg_tarc0 = E1000_READ_REG(hw, TARC0); 1447 reg_tarc0 &= ~((1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)); 1448 1449 /* Enable not-done TX descriptor counting */ 1450 reg_txdctl = E1000_READ_REG(hw, TXDCTL); 1451 reg_txdctl |= E1000_TXDCTL_COUNT_DESC; 1452 E1000_WRITE_REG(hw, TXDCTL, reg_txdctl); 1453 1454 reg_txdctl1 = E1000_READ_REG(hw, TXDCTL1); 1455 reg_txdctl1 |= E1000_TXDCTL_COUNT_DESC; 1456 E1000_WRITE_REG(hw, TXDCTL1, reg_txdctl1); 1457 1458 switch (hw->mac_type) { 1459 case e1000_82571: 1460 case e1000_82572: 1461 /* Clear PHY TX compatible mode bits */ 1462 reg_tarc1 = E1000_READ_REG(hw, TARC1); 1463 reg_tarc1 &= ~((1 << 30)|(1 << 29)); 1464 1465 /* link autonegotiation/sync workarounds */ 1466 reg_tarc0 |= ((1 << 26)|(1 << 25)|(1 << 24)|(1 << 23)); 1467 1468 /* TX ring control fixes */ 1469 reg_tarc1 |= ((1 << 26)|(1 << 25)|(1 << 24)); 1470 1471 /* Multiple read bit is reversed polarity */ 1472 reg_tctl = E1000_READ_REG(hw, TCTL); 1473 if (reg_tctl & E1000_TCTL_MULR) 1474 reg_tarc1 &= ~(1 << 28); 1475 else 1476 reg_tarc1 |= (1 << 28); 1477 1478 E1000_WRITE_REG(hw, TARC1, reg_tarc1); 1479 break; 1480 case e1000_82573: 1481 reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 1482 reg_ctrl_ext &= ~(1 << 23); 1483 reg_ctrl_ext |= (1 << 22); 1484 1485 /* TX byte count fix */ 1486 reg_ctrl = E1000_READ_REG(hw, CTRL); 1487 reg_ctrl &= ~(1 << 29); 1488 1489 E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext); 1490 E1000_WRITE_REG(hw, CTRL, reg_ctrl); 1491 break; 1492 case e1000_80003es2lan: 1493 /* improve small packet performace for fiber/serdes */ 1494 if ((hw->media_type == e1000_media_type_fiber) 1495 || (hw->media_type == 1496 e1000_media_type_internal_serdes)) { 1497 reg_tarc0 &= ~(1 << 20); 1498 } 1499 1500 /* Multiple read bit is reversed polarity */ 1501 reg_tctl = E1000_READ_REG(hw, TCTL); 1502 reg_tarc1 = E1000_READ_REG(hw, TARC1); 1503 if (reg_tctl & E1000_TCTL_MULR) 1504 reg_tarc1 &= ~(1 << 28); 1505 else 1506 reg_tarc1 |= (1 << 28); 1507 1508 E1000_WRITE_REG(hw, TARC1, reg_tarc1); 1509 break; 1510 case e1000_ich8lan: 1511 /* Reduce concurrent DMA requests to 3 from 4 */ 1512 if ((hw->revision_id < 3) || 1513 ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) && 1514 (hw->device_id != E1000_DEV_ID_ICH8_IGP_M))) 1515 reg_tarc0 |= ((1 << 29)|(1 << 28)); 1516 1517 reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 1518 reg_ctrl_ext |= (1 << 22); 1519 E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext); 1520 1521 /* workaround TX hang with TSO=on */ 1522 reg_tarc0 |= ((1 << 27)|(1 << 26)|(1 << 24)|(1 << 23)); 1523 1524 /* Multiple read bit is reversed polarity */ 1525 reg_tctl = E1000_READ_REG(hw, TCTL); 1526 reg_tarc1 = E1000_READ_REG(hw, TARC1); 1527 if (reg_tctl & E1000_TCTL_MULR) 1528 reg_tarc1 &= ~(1 << 28); 1529 else 1530 reg_tarc1 |= (1 << 28); 1531 1532 /* workaround TX hang with TSO=on */ 1533 reg_tarc1 |= ((1 << 30)|(1 << 26)|(1 << 24)); 1534 1535 E1000_WRITE_REG(hw, TARC1, reg_tarc1); 1536 break; 1537 default: 1538 break; 1539 } 1540 1541 E1000_WRITE_REG(hw, TARC0, reg_tarc0); 1542 } 1543 } 1544 1545 /****************************************************************************** 1546 * Performs basic configuration of the adapter. 1547 * 1548 * hw - Struct containing variables accessed by shared code 1549 * 1550 * Assumes that the controller has previously been reset and is in a 1551 * post-reset uninitialized state. Initializes the receive address registers, 1552 * multicast table, and VLAN filter table. Calls routines to setup link 1553 * configuration and flow control settings. Clears all on-chip counters. Leaves 1554 * the transmit and receive units disabled and uninitialized. 1555 *****************************************************************************/ 1556 static int 1557 e1000_init_hw(struct eth_device *nic) 1558 { 1559 struct e1000_hw *hw = nic->priv; 1560 uint32_t ctrl; 1561 uint32_t i; 1562 int32_t ret_val; 1563 uint16_t pcix_cmd_word; 1564 uint16_t pcix_stat_hi_word; 1565 uint16_t cmd_mmrbc; 1566 uint16_t stat_mmrbc; 1567 uint32_t mta_size; 1568 uint32_t reg_data; 1569 uint32_t ctrl_ext; 1570 DEBUGFUNC(); 1571 /* force full DMA clock frequency for 10/100 on ICH8 A0-B0 */ 1572 if ((hw->mac_type == e1000_ich8lan) && 1573 ((hw->revision_id < 3) || 1574 ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) && 1575 (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))) { 1576 reg_data = E1000_READ_REG(hw, STATUS); 1577 reg_data &= ~0x80000000; 1578 E1000_WRITE_REG(hw, STATUS, reg_data); 1579 } 1580 /* Do not need initialize Identification LED */ 1581 1582 /* Set the media type and TBI compatibility */ 1583 e1000_set_media_type(hw); 1584 1585 /* Must be called after e1000_set_media_type 1586 * because media_type is used */ 1587 e1000_initialize_hardware_bits(hw); 1588 1589 /* Disabling VLAN filtering. */ 1590 DEBUGOUT("Initializing the IEEE VLAN\n"); 1591 /* VET hardcoded to standard value and VFTA removed in ICH8 LAN */ 1592 if (hw->mac_type != e1000_ich8lan) { 1593 if (hw->mac_type < e1000_82545_rev_3) 1594 E1000_WRITE_REG(hw, VET, 0); 1595 e1000_clear_vfta(hw); 1596 } 1597 1598 /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */ 1599 if (hw->mac_type == e1000_82542_rev2_0) { 1600 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n"); 1601 pci_write_config_word(hw->pdev, PCI_COMMAND, 1602 hw-> 1603 pci_cmd_word & ~PCI_COMMAND_INVALIDATE); 1604 E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST); 1605 E1000_WRITE_FLUSH(hw); 1606 mdelay(5); 1607 } 1608 1609 /* Setup the receive address. This involves initializing all of the Receive 1610 * Address Registers (RARs 0 - 15). 1611 */ 1612 e1000_init_rx_addrs(nic); 1613 1614 /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */ 1615 if (hw->mac_type == e1000_82542_rev2_0) { 1616 E1000_WRITE_REG(hw, RCTL, 0); 1617 E1000_WRITE_FLUSH(hw); 1618 mdelay(1); 1619 pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word); 1620 } 1621 1622 /* Zero out the Multicast HASH table */ 1623 DEBUGOUT("Zeroing the MTA\n"); 1624 mta_size = E1000_MC_TBL_SIZE; 1625 if (hw->mac_type == e1000_ich8lan) 1626 mta_size = E1000_MC_TBL_SIZE_ICH8LAN; 1627 for (i = 0; i < mta_size; i++) { 1628 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0); 1629 /* use write flush to prevent Memory Write Block (MWB) from 1630 * occuring when accessing our register space */ 1631 E1000_WRITE_FLUSH(hw); 1632 } 1633 #if 0 1634 /* Set the PCI priority bit correctly in the CTRL register. This 1635 * determines if the adapter gives priority to receives, or if it 1636 * gives equal priority to transmits and receives. Valid only on 1637 * 82542 and 82543 silicon. 1638 */ 1639 if (hw->dma_fairness && hw->mac_type <= e1000_82543) { 1640 ctrl = E1000_READ_REG(hw, CTRL); 1641 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR); 1642 } 1643 #endif 1644 switch (hw->mac_type) { 1645 case e1000_82545_rev_3: 1646 case e1000_82546_rev_3: 1647 break; 1648 default: 1649 /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */ 1650 if (hw->bus_type == e1000_bus_type_pcix) { 1651 pci_read_config_word(hw->pdev, PCIX_COMMAND_REGISTER, 1652 &pcix_cmd_word); 1653 pci_read_config_word(hw->pdev, PCIX_STATUS_REGISTER_HI, 1654 &pcix_stat_hi_word); 1655 cmd_mmrbc = 1656 (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) >> 1657 PCIX_COMMAND_MMRBC_SHIFT; 1658 stat_mmrbc = 1659 (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >> 1660 PCIX_STATUS_HI_MMRBC_SHIFT; 1661 if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K) 1662 stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K; 1663 if (cmd_mmrbc > stat_mmrbc) { 1664 pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK; 1665 pcix_cmd_word |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT; 1666 pci_write_config_word(hw->pdev, PCIX_COMMAND_REGISTER, 1667 pcix_cmd_word); 1668 } 1669 } 1670 break; 1671 } 1672 1673 /* More time needed for PHY to initialize */ 1674 if (hw->mac_type == e1000_ich8lan) 1675 mdelay(15); 1676 1677 /* Call a subroutine to configure the link and setup flow control. */ 1678 ret_val = e1000_setup_link(nic); 1679 1680 /* Set the transmit descriptor write-back policy */ 1681 if (hw->mac_type > e1000_82544) { 1682 ctrl = E1000_READ_REG(hw, TXDCTL); 1683 ctrl = 1684 (ctrl & ~E1000_TXDCTL_WTHRESH) | 1685 E1000_TXDCTL_FULL_TX_DESC_WB; 1686 E1000_WRITE_REG(hw, TXDCTL, ctrl); 1687 } 1688 1689 switch (hw->mac_type) { 1690 default: 1691 break; 1692 case e1000_80003es2lan: 1693 /* Enable retransmit on late collisions */ 1694 reg_data = E1000_READ_REG(hw, TCTL); 1695 reg_data |= E1000_TCTL_RTLC; 1696 E1000_WRITE_REG(hw, TCTL, reg_data); 1697 1698 /* Configure Gigabit Carry Extend Padding */ 1699 reg_data = E1000_READ_REG(hw, TCTL_EXT); 1700 reg_data &= ~E1000_TCTL_EXT_GCEX_MASK; 1701 reg_data |= DEFAULT_80003ES2LAN_TCTL_EXT_GCEX; 1702 E1000_WRITE_REG(hw, TCTL_EXT, reg_data); 1703 1704 /* Configure Transmit Inter-Packet Gap */ 1705 reg_data = E1000_READ_REG(hw, TIPG); 1706 reg_data &= ~E1000_TIPG_IPGT_MASK; 1707 reg_data |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000; 1708 E1000_WRITE_REG(hw, TIPG, reg_data); 1709 1710 reg_data = E1000_READ_REG_ARRAY(hw, FFLT, 0x0001); 1711 reg_data &= ~0x00100000; 1712 E1000_WRITE_REG_ARRAY(hw, FFLT, 0x0001, reg_data); 1713 /* Fall through */ 1714 case e1000_82571: 1715 case e1000_82572: 1716 case e1000_ich8lan: 1717 ctrl = E1000_READ_REG(hw, TXDCTL1); 1718 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) 1719 | E1000_TXDCTL_FULL_TX_DESC_WB; 1720 E1000_WRITE_REG(hw, TXDCTL1, ctrl); 1721 break; 1722 } 1723 1724 if (hw->mac_type == e1000_82573) { 1725 uint32_t gcr = E1000_READ_REG(hw, GCR); 1726 gcr |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX; 1727 E1000_WRITE_REG(hw, GCR, gcr); 1728 } 1729 1730 #if 0 1731 /* Clear all of the statistics registers (clear on read). It is 1732 * important that we do this after we have tried to establish link 1733 * because the symbol error count will increment wildly if there 1734 * is no link. 1735 */ 1736 e1000_clear_hw_cntrs(hw); 1737 1738 /* ICH8 No-snoop bits are opposite polarity. 1739 * Set to snoop by default after reset. */ 1740 if (hw->mac_type == e1000_ich8lan) 1741 e1000_set_pci_ex_no_snoop(hw, PCI_EX_82566_SNOOP_ALL); 1742 #endif 1743 1744 if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER || 1745 hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) { 1746 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 1747 /* Relaxed ordering must be disabled to avoid a parity 1748 * error crash in a PCI slot. */ 1749 ctrl_ext |= E1000_CTRL_EXT_RO_DIS; 1750 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 1751 } 1752 1753 return ret_val; 1754 } 1755 1756 /****************************************************************************** 1757 * Configures flow control and link settings. 1758 * 1759 * hw - Struct containing variables accessed by shared code 1760 * 1761 * Determines which flow control settings to use. Calls the apropriate media- 1762 * specific link configuration function. Configures the flow control settings. 1763 * Assuming the adapter has a valid link partner, a valid link should be 1764 * established. Assumes the hardware has previously been reset and the 1765 * transmitter and receiver are not enabled. 1766 *****************************************************************************/ 1767 static int 1768 e1000_setup_link(struct eth_device *nic) 1769 { 1770 struct e1000_hw *hw = nic->priv; 1771 uint32_t ctrl_ext; 1772 int32_t ret_val; 1773 uint16_t eeprom_data; 1774 1775 DEBUGFUNC(); 1776 1777 /* In the case of the phy reset being blocked, we already have a link. 1778 * We do not have to set it up again. */ 1779 if (e1000_check_phy_reset_block(hw)) 1780 return E1000_SUCCESS; 1781 1782 #ifndef CONFIG_AP1000 1783 /* Read and store word 0x0F of the EEPROM. This word contains bits 1784 * that determine the hardware's default PAUSE (flow control) mode, 1785 * a bit that determines whether the HW defaults to enabling or 1786 * disabling auto-negotiation, and the direction of the 1787 * SW defined pins. If there is no SW over-ride of the flow 1788 * control setting, then the variable hw->fc will 1789 * be initialized based on a value in the EEPROM. 1790 */ 1791 if (e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, 1, 1792 &eeprom_data) < 0) { 1793 DEBUGOUT("EEPROM Read Error\n"); 1794 return -E1000_ERR_EEPROM; 1795 } 1796 #else 1797 /* we have to hardcode the proper value for our hardware. */ 1798 /* this value is for the 82540EM pci card used for prototyping, and it works. */ 1799 eeprom_data = 0xb220; 1800 #endif 1801 1802 if (hw->fc == e1000_fc_default) { 1803 switch (hw->mac_type) { 1804 case e1000_ich8lan: 1805 case e1000_82573: 1806 hw->fc = e1000_fc_full; 1807 break; 1808 default: 1809 #ifndef CONFIG_AP1000 1810 ret_val = e1000_read_eeprom(hw, 1811 EEPROM_INIT_CONTROL2_REG, 1, &eeprom_data); 1812 if (ret_val) { 1813 DEBUGOUT("EEPROM Read Error\n"); 1814 return -E1000_ERR_EEPROM; 1815 } 1816 #else 1817 eeprom_data = 0xb220; 1818 #endif 1819 if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0) 1820 hw->fc = e1000_fc_none; 1821 else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 1822 EEPROM_WORD0F_ASM_DIR) 1823 hw->fc = e1000_fc_tx_pause; 1824 else 1825 hw->fc = e1000_fc_full; 1826 break; 1827 } 1828 } 1829 1830 /* We want to save off the original Flow Control configuration just 1831 * in case we get disconnected and then reconnected into a different 1832 * hub or switch with different Flow Control capabilities. 1833 */ 1834 if (hw->mac_type == e1000_82542_rev2_0) 1835 hw->fc &= (~e1000_fc_tx_pause); 1836 1837 if ((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1)) 1838 hw->fc &= (~e1000_fc_rx_pause); 1839 1840 hw->original_fc = hw->fc; 1841 1842 DEBUGOUT("After fix-ups FlowControl is now = %x\n", hw->fc); 1843 1844 /* Take the 4 bits from EEPROM word 0x0F that determine the initial 1845 * polarity value for the SW controlled pins, and setup the 1846 * Extended Device Control reg with that info. 1847 * This is needed because one of the SW controlled pins is used for 1848 * signal detection. So this should be done before e1000_setup_pcs_link() 1849 * or e1000_phy_setup() is called. 1850 */ 1851 if (hw->mac_type == e1000_82543) { 1852 ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) << 1853 SWDPIO__EXT_SHIFT); 1854 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 1855 } 1856 1857 /* Call the necessary subroutine to configure the link. */ 1858 ret_val = (hw->media_type == e1000_media_type_fiber) ? 1859 e1000_setup_fiber_link(nic) : e1000_setup_copper_link(nic); 1860 if (ret_val < 0) { 1861 return ret_val; 1862 } 1863 1864 /* Initialize the flow control address, type, and PAUSE timer 1865 * registers to their default values. This is done even if flow 1866 * control is disabled, because it does not hurt anything to 1867 * initialize these registers. 1868 */ 1869 DEBUGOUT("Initializing the Flow Control address, type" 1870 "and timer regs\n"); 1871 1872 /* FCAL/H and FCT are hardcoded to standard values in e1000_ich8lan. */ 1873 if (hw->mac_type != e1000_ich8lan) { 1874 E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE); 1875 E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH); 1876 E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW); 1877 } 1878 1879 E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time); 1880 1881 /* Set the flow control receive threshold registers. Normally, 1882 * these registers will be set to a default threshold that may be 1883 * adjusted later by the driver's runtime code. However, if the 1884 * ability to transmit pause frames in not enabled, then these 1885 * registers will be set to 0. 1886 */ 1887 if (!(hw->fc & e1000_fc_tx_pause)) { 1888 E1000_WRITE_REG(hw, FCRTL, 0); 1889 E1000_WRITE_REG(hw, FCRTH, 0); 1890 } else { 1891 /* We need to set up the Receive Threshold high and low water marks 1892 * as well as (optionally) enabling the transmission of XON frames. 1893 */ 1894 if (hw->fc_send_xon) { 1895 E1000_WRITE_REG(hw, FCRTL, 1896 (hw->fc_low_water | E1000_FCRTL_XONE)); 1897 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water); 1898 } else { 1899 E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water); 1900 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water); 1901 } 1902 } 1903 return ret_val; 1904 } 1905 1906 /****************************************************************************** 1907 * Sets up link for a fiber based adapter 1908 * 1909 * hw - Struct containing variables accessed by shared code 1910 * 1911 * Manipulates Physical Coding Sublayer functions in order to configure 1912 * link. Assumes the hardware has been previously reset and the transmitter 1913 * and receiver are not enabled. 1914 *****************************************************************************/ 1915 static int 1916 e1000_setup_fiber_link(struct eth_device *nic) 1917 { 1918 struct e1000_hw *hw = nic->priv; 1919 uint32_t ctrl; 1920 uint32_t status; 1921 uint32_t txcw = 0; 1922 uint32_t i; 1923 uint32_t signal; 1924 int32_t ret_val; 1925 1926 DEBUGFUNC(); 1927 /* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be 1928 * set when the optics detect a signal. On older adapters, it will be 1929 * cleared when there is a signal 1930 */ 1931 ctrl = E1000_READ_REG(hw, CTRL); 1932 if ((hw->mac_type > e1000_82544) && !(ctrl & E1000_CTRL_ILOS)) 1933 signal = E1000_CTRL_SWDPIN1; 1934 else 1935 signal = 0; 1936 1937 printf("signal for %s is %x (ctrl %08x)!!!!\n", nic->name, signal, 1938 ctrl); 1939 /* Take the link out of reset */ 1940 ctrl &= ~(E1000_CTRL_LRST); 1941 1942 e1000_config_collision_dist(hw); 1943 1944 /* Check for a software override of the flow control settings, and setup 1945 * the device accordingly. If auto-negotiation is enabled, then software 1946 * will have to set the "PAUSE" bits to the correct value in the Tranmsit 1947 * Config Word Register (TXCW) and re-start auto-negotiation. However, if 1948 * auto-negotiation is disabled, then software will have to manually 1949 * configure the two flow control enable bits in the CTRL register. 1950 * 1951 * The possible values of the "fc" parameter are: 1952 * 0: Flow control is completely disabled 1953 * 1: Rx flow control is enabled (we can receive pause frames, but 1954 * not send pause frames). 1955 * 2: Tx flow control is enabled (we can send pause frames but we do 1956 * not support receiving pause frames). 1957 * 3: Both Rx and TX flow control (symmetric) are enabled. 1958 */ 1959 switch (hw->fc) { 1960 case e1000_fc_none: 1961 /* Flow control is completely disabled by a software over-ride. */ 1962 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD); 1963 break; 1964 case e1000_fc_rx_pause: 1965 /* RX Flow control is enabled and TX Flow control is disabled by a 1966 * software over-ride. Since there really isn't a way to advertise 1967 * that we are capable of RX Pause ONLY, we will advertise that we 1968 * support both symmetric and asymmetric RX PAUSE. Later, we will 1969 * disable the adapter's ability to send PAUSE frames. 1970 */ 1971 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); 1972 break; 1973 case e1000_fc_tx_pause: 1974 /* TX Flow control is enabled, and RX Flow control is disabled, by a 1975 * software over-ride. 1976 */ 1977 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR); 1978 break; 1979 case e1000_fc_full: 1980 /* Flow control (both RX and TX) is enabled by a software over-ride. */ 1981 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); 1982 break; 1983 default: 1984 DEBUGOUT("Flow control param set incorrectly\n"); 1985 return -E1000_ERR_CONFIG; 1986 break; 1987 } 1988 1989 /* Since auto-negotiation is enabled, take the link out of reset (the link 1990 * will be in reset, because we previously reset the chip). This will 1991 * restart auto-negotiation. If auto-neogtiation is successful then the 1992 * link-up status bit will be set and the flow control enable bits (RFCE 1993 * and TFCE) will be set according to their negotiated value. 1994 */ 1995 DEBUGOUT("Auto-negotiation enabled (%#x)\n", txcw); 1996 1997 E1000_WRITE_REG(hw, TXCW, txcw); 1998 E1000_WRITE_REG(hw, CTRL, ctrl); 1999 E1000_WRITE_FLUSH(hw); 2000 2001 hw->txcw = txcw; 2002 mdelay(1); 2003 2004 /* If we have a signal (the cable is plugged in) then poll for a "Link-Up" 2005 * indication in the Device Status Register. Time-out if a link isn't 2006 * seen in 500 milliseconds seconds (Auto-negotiation should complete in 2007 * less than 500 milliseconds even if the other end is doing it in SW). 2008 */ 2009 if ((E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) { 2010 DEBUGOUT("Looking for Link\n"); 2011 for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) { 2012 mdelay(10); 2013 status = E1000_READ_REG(hw, STATUS); 2014 if (status & E1000_STATUS_LU) 2015 break; 2016 } 2017 if (i == (LINK_UP_TIMEOUT / 10)) { 2018 /* AutoNeg failed to achieve a link, so we'll call 2019 * e1000_check_for_link. This routine will force the link up if we 2020 * detect a signal. This will allow us to communicate with 2021 * non-autonegotiating link partners. 2022 */ 2023 DEBUGOUT("Never got a valid link from auto-neg!!!\n"); 2024 hw->autoneg_failed = 1; 2025 ret_val = e1000_check_for_link(nic); 2026 if (ret_val < 0) { 2027 DEBUGOUT("Error while checking for link\n"); 2028 return ret_val; 2029 } 2030 hw->autoneg_failed = 0; 2031 } else { 2032 hw->autoneg_failed = 0; 2033 DEBUGOUT("Valid Link Found\n"); 2034 } 2035 } else { 2036 DEBUGOUT("No Signal Detected\n"); 2037 return -E1000_ERR_NOLINK; 2038 } 2039 return 0; 2040 } 2041 2042 /****************************************************************************** 2043 * Make sure we have a valid PHY and change PHY mode before link setup. 2044 * 2045 * hw - Struct containing variables accessed by shared code 2046 ******************************************************************************/ 2047 static int32_t 2048 e1000_copper_link_preconfig(struct e1000_hw *hw) 2049 { 2050 uint32_t ctrl; 2051 int32_t ret_val; 2052 uint16_t phy_data; 2053 2054 DEBUGFUNC(); 2055 2056 ctrl = E1000_READ_REG(hw, CTRL); 2057 /* With 82543, we need to force speed and duplex on the MAC equal to what 2058 * the PHY speed and duplex configuration is. In addition, we need to 2059 * perform a hardware reset on the PHY to take it out of reset. 2060 */ 2061 if (hw->mac_type > e1000_82543) { 2062 ctrl |= E1000_CTRL_SLU; 2063 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 2064 E1000_WRITE_REG(hw, CTRL, ctrl); 2065 } else { 2066 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX 2067 | E1000_CTRL_SLU); 2068 E1000_WRITE_REG(hw, CTRL, ctrl); 2069 ret_val = e1000_phy_hw_reset(hw); 2070 if (ret_val) 2071 return ret_val; 2072 } 2073 2074 /* Make sure we have a valid PHY */ 2075 ret_val = e1000_detect_gig_phy(hw); 2076 if (ret_val) { 2077 DEBUGOUT("Error, did not detect valid phy.\n"); 2078 return ret_val; 2079 } 2080 DEBUGOUT("Phy ID = %x \n", hw->phy_id); 2081 2082 #ifndef CONFIG_AP1000 2083 /* Set PHY to class A mode (if necessary) */ 2084 ret_val = e1000_set_phy_mode(hw); 2085 if (ret_val) 2086 return ret_val; 2087 #endif 2088 if ((hw->mac_type == e1000_82545_rev_3) || 2089 (hw->mac_type == e1000_82546_rev_3)) { 2090 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 2091 &phy_data); 2092 phy_data |= 0x00000008; 2093 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 2094 phy_data); 2095 } 2096 2097 if (hw->mac_type <= e1000_82543 || 2098 hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 || 2099 hw->mac_type == e1000_82541_rev_2 2100 || hw->mac_type == e1000_82547_rev_2) 2101 hw->phy_reset_disable = FALSE; 2102 2103 return E1000_SUCCESS; 2104 } 2105 2106 /***************************************************************************** 2107 * 2108 * This function sets the lplu state according to the active flag. When 2109 * activating lplu this function also disables smart speed and vise versa. 2110 * lplu will not be activated unless the device autonegotiation advertisment 2111 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes. 2112 * hw: Struct containing variables accessed by shared code 2113 * active - true to enable lplu false to disable lplu. 2114 * 2115 * returns: - E1000_ERR_PHY if fail to read/write the PHY 2116 * E1000_SUCCESS at any other case. 2117 * 2118 ****************************************************************************/ 2119 2120 static int32_t 2121 e1000_set_d3_lplu_state(struct e1000_hw *hw, boolean_t active) 2122 { 2123 uint32_t phy_ctrl = 0; 2124 int32_t ret_val; 2125 uint16_t phy_data; 2126 DEBUGFUNC(); 2127 2128 if (hw->phy_type != e1000_phy_igp && hw->phy_type != e1000_phy_igp_2 2129 && hw->phy_type != e1000_phy_igp_3) 2130 return E1000_SUCCESS; 2131 2132 /* During driver activity LPLU should not be used or it will attain link 2133 * from the lowest speeds starting from 10Mbps. The capability is used 2134 * for Dx transitions and states */ 2135 if (hw->mac_type == e1000_82541_rev_2 2136 || hw->mac_type == e1000_82547_rev_2) { 2137 ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, 2138 &phy_data); 2139 if (ret_val) 2140 return ret_val; 2141 } else if (hw->mac_type == e1000_ich8lan) { 2142 /* MAC writes into PHY register based on the state transition 2143 * and start auto-negotiation. SW driver can overwrite the 2144 * settings in CSR PHY power control E1000_PHY_CTRL register. */ 2145 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL); 2146 } else { 2147 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, 2148 &phy_data); 2149 if (ret_val) 2150 return ret_val; 2151 } 2152 2153 if (!active) { 2154 if (hw->mac_type == e1000_82541_rev_2 || 2155 hw->mac_type == e1000_82547_rev_2) { 2156 phy_data &= ~IGP01E1000_GMII_FLEX_SPD; 2157 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, 2158 phy_data); 2159 if (ret_val) 2160 return ret_val; 2161 } else { 2162 if (hw->mac_type == e1000_ich8lan) { 2163 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU; 2164 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); 2165 } else { 2166 phy_data &= ~IGP02E1000_PM_D3_LPLU; 2167 ret_val = e1000_write_phy_reg(hw, 2168 IGP02E1000_PHY_POWER_MGMT, phy_data); 2169 if (ret_val) 2170 return ret_val; 2171 } 2172 } 2173 2174 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during 2175 * Dx states where the power conservation is most important. During 2176 * driver activity we should enable SmartSpeed, so performance is 2177 * maintained. */ 2178 if (hw->smart_speed == e1000_smart_speed_on) { 2179 ret_val = e1000_read_phy_reg(hw, 2180 IGP01E1000_PHY_PORT_CONFIG, &phy_data); 2181 if (ret_val) 2182 return ret_val; 2183 2184 phy_data |= IGP01E1000_PSCFR_SMART_SPEED; 2185 ret_val = e1000_write_phy_reg(hw, 2186 IGP01E1000_PHY_PORT_CONFIG, phy_data); 2187 if (ret_val) 2188 return ret_val; 2189 } else if (hw->smart_speed == e1000_smart_speed_off) { 2190 ret_val = e1000_read_phy_reg(hw, 2191 IGP01E1000_PHY_PORT_CONFIG, &phy_data); 2192 if (ret_val) 2193 return ret_val; 2194 2195 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 2196 ret_val = e1000_write_phy_reg(hw, 2197 IGP01E1000_PHY_PORT_CONFIG, phy_data); 2198 if (ret_val) 2199 return ret_val; 2200 } 2201 2202 } else if ((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT) 2203 || (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL) || 2204 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) { 2205 2206 if (hw->mac_type == e1000_82541_rev_2 || 2207 hw->mac_type == e1000_82547_rev_2) { 2208 phy_data |= IGP01E1000_GMII_FLEX_SPD; 2209 ret_val = e1000_write_phy_reg(hw, 2210 IGP01E1000_GMII_FIFO, phy_data); 2211 if (ret_val) 2212 return ret_val; 2213 } else { 2214 if (hw->mac_type == e1000_ich8lan) { 2215 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU; 2216 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); 2217 } else { 2218 phy_data |= IGP02E1000_PM_D3_LPLU; 2219 ret_val = e1000_write_phy_reg(hw, 2220 IGP02E1000_PHY_POWER_MGMT, phy_data); 2221 if (ret_val) 2222 return ret_val; 2223 } 2224 } 2225 2226 /* When LPLU is enabled we should disable SmartSpeed */ 2227 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 2228 &phy_data); 2229 if (ret_val) 2230 return ret_val; 2231 2232 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 2233 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 2234 phy_data); 2235 if (ret_val) 2236 return ret_val; 2237 } 2238 return E1000_SUCCESS; 2239 } 2240 2241 /***************************************************************************** 2242 * 2243 * This function sets the lplu d0 state according to the active flag. When 2244 * activating lplu this function also disables smart speed and vise versa. 2245 * lplu will not be activated unless the device autonegotiation advertisment 2246 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes. 2247 * hw: Struct containing variables accessed by shared code 2248 * active - true to enable lplu false to disable lplu. 2249 * 2250 * returns: - E1000_ERR_PHY if fail to read/write the PHY 2251 * E1000_SUCCESS at any other case. 2252 * 2253 ****************************************************************************/ 2254 2255 static int32_t 2256 e1000_set_d0_lplu_state(struct e1000_hw *hw, boolean_t active) 2257 { 2258 uint32_t phy_ctrl = 0; 2259 int32_t ret_val; 2260 uint16_t phy_data; 2261 DEBUGFUNC(); 2262 2263 if (hw->mac_type <= e1000_82547_rev_2) 2264 return E1000_SUCCESS; 2265 2266 if (hw->mac_type == e1000_ich8lan) { 2267 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL); 2268 } else { 2269 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, 2270 &phy_data); 2271 if (ret_val) 2272 return ret_val; 2273 } 2274 2275 if (!active) { 2276 if (hw->mac_type == e1000_ich8lan) { 2277 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU; 2278 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); 2279 } else { 2280 phy_data &= ~IGP02E1000_PM_D0_LPLU; 2281 ret_val = e1000_write_phy_reg(hw, 2282 IGP02E1000_PHY_POWER_MGMT, phy_data); 2283 if (ret_val) 2284 return ret_val; 2285 } 2286 2287 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during 2288 * Dx states where the power conservation is most important. During 2289 * driver activity we should enable SmartSpeed, so performance is 2290 * maintained. */ 2291 if (hw->smart_speed == e1000_smart_speed_on) { 2292 ret_val = e1000_read_phy_reg(hw, 2293 IGP01E1000_PHY_PORT_CONFIG, &phy_data); 2294 if (ret_val) 2295 return ret_val; 2296 2297 phy_data |= IGP01E1000_PSCFR_SMART_SPEED; 2298 ret_val = e1000_write_phy_reg(hw, 2299 IGP01E1000_PHY_PORT_CONFIG, phy_data); 2300 if (ret_val) 2301 return ret_val; 2302 } else if (hw->smart_speed == e1000_smart_speed_off) { 2303 ret_val = e1000_read_phy_reg(hw, 2304 IGP01E1000_PHY_PORT_CONFIG, &phy_data); 2305 if (ret_val) 2306 return ret_val; 2307 2308 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 2309 ret_val = e1000_write_phy_reg(hw, 2310 IGP01E1000_PHY_PORT_CONFIG, phy_data); 2311 if (ret_val) 2312 return ret_val; 2313 } 2314 2315 2316 } else { 2317 2318 if (hw->mac_type == e1000_ich8lan) { 2319 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU; 2320 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); 2321 } else { 2322 phy_data |= IGP02E1000_PM_D0_LPLU; 2323 ret_val = e1000_write_phy_reg(hw, 2324 IGP02E1000_PHY_POWER_MGMT, phy_data); 2325 if (ret_val) 2326 return ret_val; 2327 } 2328 2329 /* When LPLU is enabled we should disable SmartSpeed */ 2330 ret_val = e1000_read_phy_reg(hw, 2331 IGP01E1000_PHY_PORT_CONFIG, &phy_data); 2332 if (ret_val) 2333 return ret_val; 2334 2335 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 2336 ret_val = e1000_write_phy_reg(hw, 2337 IGP01E1000_PHY_PORT_CONFIG, phy_data); 2338 if (ret_val) 2339 return ret_val; 2340 2341 } 2342 return E1000_SUCCESS; 2343 } 2344 2345 /******************************************************************** 2346 * Copper link setup for e1000_phy_igp series. 2347 * 2348 * hw - Struct containing variables accessed by shared code 2349 *********************************************************************/ 2350 static int32_t 2351 e1000_copper_link_igp_setup(struct e1000_hw *hw) 2352 { 2353 uint32_t led_ctrl; 2354 int32_t ret_val; 2355 uint16_t phy_data; 2356 2357 DEBUGFUNC(); 2358 2359 if (hw->phy_reset_disable) 2360 return E1000_SUCCESS; 2361 2362 ret_val = e1000_phy_reset(hw); 2363 if (ret_val) { 2364 DEBUGOUT("Error Resetting the PHY\n"); 2365 return ret_val; 2366 } 2367 2368 /* Wait 15ms for MAC to configure PHY from eeprom settings */ 2369 mdelay(15); 2370 if (hw->mac_type != e1000_ich8lan) { 2371 /* Configure activity LED after PHY reset */ 2372 led_ctrl = E1000_READ_REG(hw, LEDCTL); 2373 led_ctrl &= IGP_ACTIVITY_LED_MASK; 2374 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); 2375 E1000_WRITE_REG(hw, LEDCTL, led_ctrl); 2376 } 2377 2378 /* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */ 2379 if (hw->phy_type == e1000_phy_igp) { 2380 /* disable lplu d3 during driver init */ 2381 ret_val = e1000_set_d3_lplu_state(hw, FALSE); 2382 if (ret_val) { 2383 DEBUGOUT("Error Disabling LPLU D3\n"); 2384 return ret_val; 2385 } 2386 } 2387 2388 /* disable lplu d0 during driver init */ 2389 ret_val = e1000_set_d0_lplu_state(hw, FALSE); 2390 if (ret_val) { 2391 DEBUGOUT("Error Disabling LPLU D0\n"); 2392 return ret_val; 2393 } 2394 /* Configure mdi-mdix settings */ 2395 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); 2396 if (ret_val) 2397 return ret_val; 2398 2399 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { 2400 hw->dsp_config_state = e1000_dsp_config_disabled; 2401 /* Force MDI for earlier revs of the IGP PHY */ 2402 phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX 2403 | IGP01E1000_PSCR_FORCE_MDI_MDIX); 2404 hw->mdix = 1; 2405 2406 } else { 2407 hw->dsp_config_state = e1000_dsp_config_enabled; 2408 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; 2409 2410 switch (hw->mdix) { 2411 case 1: 2412 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; 2413 break; 2414 case 2: 2415 phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX; 2416 break; 2417 case 0: 2418 default: 2419 phy_data |= IGP01E1000_PSCR_AUTO_MDIX; 2420 break; 2421 } 2422 } 2423 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); 2424 if (ret_val) 2425 return ret_val; 2426 2427 /* set auto-master slave resolution settings */ 2428 if (hw->autoneg) { 2429 e1000_ms_type phy_ms_setting = hw->master_slave; 2430 2431 if (hw->ffe_config_state == e1000_ffe_config_active) 2432 hw->ffe_config_state = e1000_ffe_config_enabled; 2433 2434 if (hw->dsp_config_state == e1000_dsp_config_activated) 2435 hw->dsp_config_state = e1000_dsp_config_enabled; 2436 2437 /* when autonegotiation advertisment is only 1000Mbps then we 2438 * should disable SmartSpeed and enable Auto MasterSlave 2439 * resolution as hardware default. */ 2440 if (hw->autoneg_advertised == ADVERTISE_1000_FULL) { 2441 /* Disable SmartSpeed */ 2442 ret_val = e1000_read_phy_reg(hw, 2443 IGP01E1000_PHY_PORT_CONFIG, &phy_data); 2444 if (ret_val) 2445 return ret_val; 2446 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 2447 ret_val = e1000_write_phy_reg(hw, 2448 IGP01E1000_PHY_PORT_CONFIG, phy_data); 2449 if (ret_val) 2450 return ret_val; 2451 /* Set auto Master/Slave resolution process */ 2452 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, 2453 &phy_data); 2454 if (ret_val) 2455 return ret_val; 2456 phy_data &= ~CR_1000T_MS_ENABLE; 2457 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, 2458 phy_data); 2459 if (ret_val) 2460 return ret_val; 2461 } 2462 2463 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data); 2464 if (ret_val) 2465 return ret_val; 2466 2467 /* load defaults for future use */ 2468 hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ? 2469 ((phy_data & CR_1000T_MS_VALUE) ? 2470 e1000_ms_force_master : 2471 e1000_ms_force_slave) : 2472 e1000_ms_auto; 2473 2474 switch (phy_ms_setting) { 2475 case e1000_ms_force_master: 2476 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE); 2477 break; 2478 case e1000_ms_force_slave: 2479 phy_data |= CR_1000T_MS_ENABLE; 2480 phy_data &= ~(CR_1000T_MS_VALUE); 2481 break; 2482 case e1000_ms_auto: 2483 phy_data &= ~CR_1000T_MS_ENABLE; 2484 default: 2485 break; 2486 } 2487 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data); 2488 if (ret_val) 2489 return ret_val; 2490 } 2491 2492 return E1000_SUCCESS; 2493 } 2494 2495 /***************************************************************************** 2496 * This function checks the mode of the firmware. 2497 * 2498 * returns - TRUE when the mode is IAMT or FALSE. 2499 ****************************************************************************/ 2500 boolean_t 2501 e1000_check_mng_mode(struct e1000_hw *hw) 2502 { 2503 uint32_t fwsm; 2504 DEBUGFUNC(); 2505 2506 fwsm = E1000_READ_REG(hw, FWSM); 2507 2508 if (hw->mac_type == e1000_ich8lan) { 2509 if ((fwsm & E1000_FWSM_MODE_MASK) == 2510 (E1000_MNG_ICH_IAMT_MODE << E1000_FWSM_MODE_SHIFT)) 2511 return TRUE; 2512 } else if ((fwsm & E1000_FWSM_MODE_MASK) == 2513 (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT)) 2514 return TRUE; 2515 2516 return FALSE; 2517 } 2518 2519 static int32_t 2520 e1000_write_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t data) 2521 { 2522 uint32_t reg_val; 2523 uint16_t swfw; 2524 DEBUGFUNC(); 2525 2526 if ((hw->mac_type == e1000_80003es2lan) && 2527 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) { 2528 swfw = E1000_SWFW_PHY1_SM; 2529 } else { 2530 swfw = E1000_SWFW_PHY0_SM; 2531 } 2532 if (e1000_swfw_sync_acquire(hw, swfw)) 2533 return -E1000_ERR_SWFW_SYNC; 2534 2535 reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) 2536 & E1000_KUMCTRLSTA_OFFSET) | data; 2537 E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val); 2538 udelay(2); 2539 2540 return E1000_SUCCESS; 2541 } 2542 2543 static int32_t 2544 e1000_read_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *data) 2545 { 2546 uint32_t reg_val; 2547 uint16_t swfw; 2548 DEBUGFUNC(); 2549 2550 if ((hw->mac_type == e1000_80003es2lan) && 2551 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) { 2552 swfw = E1000_SWFW_PHY1_SM; 2553 } else { 2554 swfw = E1000_SWFW_PHY0_SM; 2555 } 2556 if (e1000_swfw_sync_acquire(hw, swfw)) 2557 return -E1000_ERR_SWFW_SYNC; 2558 2559 /* Write register address */ 2560 reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) & 2561 E1000_KUMCTRLSTA_OFFSET) | E1000_KUMCTRLSTA_REN; 2562 E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val); 2563 udelay(2); 2564 2565 /* Read the data returned */ 2566 reg_val = E1000_READ_REG(hw, KUMCTRLSTA); 2567 *data = (uint16_t)reg_val; 2568 2569 return E1000_SUCCESS; 2570 } 2571 2572 /******************************************************************** 2573 * Copper link setup for e1000_phy_gg82563 series. 2574 * 2575 * hw - Struct containing variables accessed by shared code 2576 *********************************************************************/ 2577 static int32_t 2578 e1000_copper_link_ggp_setup(struct e1000_hw *hw) 2579 { 2580 int32_t ret_val; 2581 uint16_t phy_data; 2582 uint32_t reg_data; 2583 2584 DEBUGFUNC(); 2585 2586 if (!hw->phy_reset_disable) { 2587 /* Enable CRS on TX for half-duplex operation. */ 2588 ret_val = e1000_read_phy_reg(hw, 2589 GG82563_PHY_MAC_SPEC_CTRL, &phy_data); 2590 if (ret_val) 2591 return ret_val; 2592 2593 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX; 2594 /* Use 25MHz for both link down and 1000BASE-T for Tx clock */ 2595 phy_data |= GG82563_MSCR_TX_CLK_1000MBPS_25MHZ; 2596 2597 ret_val = e1000_write_phy_reg(hw, 2598 GG82563_PHY_MAC_SPEC_CTRL, phy_data); 2599 if (ret_val) 2600 return ret_val; 2601 2602 /* Options: 2603 * MDI/MDI-X = 0 (default) 2604 * 0 - Auto for all speeds 2605 * 1 - MDI mode 2606 * 2 - MDI-X mode 2607 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) 2608 */ 2609 ret_val = e1000_read_phy_reg(hw, 2610 GG82563_PHY_SPEC_CTRL, &phy_data); 2611 if (ret_val) 2612 return ret_val; 2613 2614 phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK; 2615 2616 switch (hw->mdix) { 2617 case 1: 2618 phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDI; 2619 break; 2620 case 2: 2621 phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDIX; 2622 break; 2623 case 0: 2624 default: 2625 phy_data |= GG82563_PSCR_CROSSOVER_MODE_AUTO; 2626 break; 2627 } 2628 2629 /* Options: 2630 * disable_polarity_correction = 0 (default) 2631 * Automatic Correction for Reversed Cable Polarity 2632 * 0 - Disabled 2633 * 1 - Enabled 2634 */ 2635 phy_data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE; 2636 ret_val = e1000_write_phy_reg(hw, 2637 GG82563_PHY_SPEC_CTRL, phy_data); 2638 2639 if (ret_val) 2640 return ret_val; 2641 2642 /* SW Reset the PHY so all changes take effect */ 2643 ret_val = e1000_phy_reset(hw); 2644 if (ret_val) { 2645 DEBUGOUT("Error Resetting the PHY\n"); 2646 return ret_val; 2647 } 2648 } /* phy_reset_disable */ 2649 2650 if (hw->mac_type == e1000_80003es2lan) { 2651 /* Bypass RX and TX FIFO's */ 2652 ret_val = e1000_write_kmrn_reg(hw, 2653 E1000_KUMCTRLSTA_OFFSET_FIFO_CTRL, 2654 E1000_KUMCTRLSTA_FIFO_CTRL_RX_BYPASS 2655 | E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS); 2656 if (ret_val) 2657 return ret_val; 2658 2659 ret_val = e1000_read_phy_reg(hw, 2660 GG82563_PHY_SPEC_CTRL_2, &phy_data); 2661 if (ret_val) 2662 return ret_val; 2663 2664 phy_data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG; 2665 ret_val = e1000_write_phy_reg(hw, 2666 GG82563_PHY_SPEC_CTRL_2, phy_data); 2667 2668 if (ret_val) 2669 return ret_val; 2670 2671 reg_data = E1000_READ_REG(hw, CTRL_EXT); 2672 reg_data &= ~(E1000_CTRL_EXT_LINK_MODE_MASK); 2673 E1000_WRITE_REG(hw, CTRL_EXT, reg_data); 2674 2675 ret_val = e1000_read_phy_reg(hw, 2676 GG82563_PHY_PWR_MGMT_CTRL, &phy_data); 2677 if (ret_val) 2678 return ret_val; 2679 2680 /* Do not init these registers when the HW is in IAMT mode, since the 2681 * firmware will have already initialized them. We only initialize 2682 * them if the HW is not in IAMT mode. 2683 */ 2684 if (e1000_check_mng_mode(hw) == FALSE) { 2685 /* Enable Electrical Idle on the PHY */ 2686 phy_data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE; 2687 ret_val = e1000_write_phy_reg(hw, 2688 GG82563_PHY_PWR_MGMT_CTRL, phy_data); 2689 if (ret_val) 2690 return ret_val; 2691 2692 ret_val = e1000_read_phy_reg(hw, 2693 GG82563_PHY_KMRN_MODE_CTRL, &phy_data); 2694 if (ret_val) 2695 return ret_val; 2696 2697 phy_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; 2698 ret_val = e1000_write_phy_reg(hw, 2699 GG82563_PHY_KMRN_MODE_CTRL, phy_data); 2700 2701 if (ret_val) 2702 return ret_val; 2703 } 2704 2705 /* Workaround: Disable padding in Kumeran interface in the MAC 2706 * and in the PHY to avoid CRC errors. 2707 */ 2708 ret_val = e1000_read_phy_reg(hw, 2709 GG82563_PHY_INBAND_CTRL, &phy_data); 2710 if (ret_val) 2711 return ret_val; 2712 phy_data |= GG82563_ICR_DIS_PADDING; 2713 ret_val = e1000_write_phy_reg(hw, 2714 GG82563_PHY_INBAND_CTRL, phy_data); 2715 if (ret_val) 2716 return ret_val; 2717 } 2718 return E1000_SUCCESS; 2719 } 2720 2721 /******************************************************************** 2722 * Copper link setup for e1000_phy_m88 series. 2723 * 2724 * hw - Struct containing variables accessed by shared code 2725 *********************************************************************/ 2726 static int32_t 2727 e1000_copper_link_mgp_setup(struct e1000_hw *hw) 2728 { 2729 int32_t ret_val; 2730 uint16_t phy_data; 2731 2732 DEBUGFUNC(); 2733 2734 if (hw->phy_reset_disable) 2735 return E1000_SUCCESS; 2736 2737 /* Enable CRS on TX. This must be set for half-duplex operation. */ 2738 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 2739 if (ret_val) 2740 return ret_val; 2741 2742 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; 2743 2744 /* Options: 2745 * MDI/MDI-X = 0 (default) 2746 * 0 - Auto for all speeds 2747 * 1 - MDI mode 2748 * 2 - MDI-X mode 2749 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) 2750 */ 2751 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 2752 2753 switch (hw->mdix) { 2754 case 1: 2755 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; 2756 break; 2757 case 2: 2758 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; 2759 break; 2760 case 3: 2761 phy_data |= M88E1000_PSCR_AUTO_X_1000T; 2762 break; 2763 case 0: 2764 default: 2765 phy_data |= M88E1000_PSCR_AUTO_X_MODE; 2766 break; 2767 } 2768 2769 /* Options: 2770 * disable_polarity_correction = 0 (default) 2771 * Automatic Correction for Reversed Cable Polarity 2772 * 0 - Disabled 2773 * 1 - Enabled 2774 */ 2775 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; 2776 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 2777 if (ret_val) 2778 return ret_val; 2779 2780 if (hw->phy_revision < M88E1011_I_REV_4) { 2781 /* Force TX_CLK in the Extended PHY Specific Control Register 2782 * to 25MHz clock. 2783 */ 2784 ret_val = e1000_read_phy_reg(hw, 2785 M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); 2786 if (ret_val) 2787 return ret_val; 2788 2789 phy_data |= M88E1000_EPSCR_TX_CLK_25; 2790 2791 if ((hw->phy_revision == E1000_REVISION_2) && 2792 (hw->phy_id == M88E1111_I_PHY_ID)) { 2793 /* Vidalia Phy, set the downshift counter to 5x */ 2794 phy_data &= ~(M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK); 2795 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X; 2796 ret_val = e1000_write_phy_reg(hw, 2797 M88E1000_EXT_PHY_SPEC_CTRL, phy_data); 2798 if (ret_val) 2799 return ret_val; 2800 } else { 2801 /* Configure Master and Slave downshift values */ 2802 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 2803 | M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK); 2804 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X 2805 | M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X); 2806 ret_val = e1000_write_phy_reg(hw, 2807 M88E1000_EXT_PHY_SPEC_CTRL, phy_data); 2808 if (ret_val) 2809 return ret_val; 2810 } 2811 } 2812 2813 /* SW Reset the PHY so all changes take effect */ 2814 ret_val = e1000_phy_reset(hw); 2815 if (ret_val) { 2816 DEBUGOUT("Error Resetting the PHY\n"); 2817 return ret_val; 2818 } 2819 2820 return E1000_SUCCESS; 2821 } 2822 2823 /******************************************************************** 2824 * Setup auto-negotiation and flow control advertisements, 2825 * and then perform auto-negotiation. 2826 * 2827 * hw - Struct containing variables accessed by shared code 2828 *********************************************************************/ 2829 static int32_t 2830 e1000_copper_link_autoneg(struct e1000_hw *hw) 2831 { 2832 int32_t ret_val; 2833 uint16_t phy_data; 2834 2835 DEBUGFUNC(); 2836 2837 /* Perform some bounds checking on the hw->autoneg_advertised 2838 * parameter. If this variable is zero, then set it to the default. 2839 */ 2840 hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT; 2841 2842 /* If autoneg_advertised is zero, we assume it was not defaulted 2843 * by the calling code so we set to advertise full capability. 2844 */ 2845 if (hw->autoneg_advertised == 0) 2846 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT; 2847 2848 /* IFE phy only supports 10/100 */ 2849 if (hw->phy_type == e1000_phy_ife) 2850 hw->autoneg_advertised &= AUTONEG_ADVERTISE_10_100_ALL; 2851 2852 DEBUGOUT("Reconfiguring auto-neg advertisement params\n"); 2853 ret_val = e1000_phy_setup_autoneg(hw); 2854 if (ret_val) { 2855 DEBUGOUT("Error Setting up Auto-Negotiation\n"); 2856 return ret_val; 2857 } 2858 DEBUGOUT("Restarting Auto-Neg\n"); 2859 2860 /* Restart auto-negotiation by setting the Auto Neg Enable bit and 2861 * the Auto Neg Restart bit in the PHY control register. 2862 */ 2863 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data); 2864 if (ret_val) 2865 return ret_val; 2866 2867 phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); 2868 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data); 2869 if (ret_val) 2870 return ret_val; 2871 2872 /* Does the user want to wait for Auto-Neg to complete here, or 2873 * check at a later time (for example, callback routine). 2874 */ 2875 /* If we do not wait for autonegtation to complete I 2876 * do not see a valid link status. 2877 * wait_autoneg_complete = 1 . 2878 */ 2879 if (hw->wait_autoneg_complete) { 2880 ret_val = e1000_wait_autoneg(hw); 2881 if (ret_val) { 2882 DEBUGOUT("Error while waiting for autoneg" 2883 "to complete\n"); 2884 return ret_val; 2885 } 2886 } 2887 2888 hw->get_link_status = TRUE; 2889 2890 return E1000_SUCCESS; 2891 } 2892 2893 /****************************************************************************** 2894 * Config the MAC and the PHY after link is up. 2895 * 1) Set up the MAC to the current PHY speed/duplex 2896 * if we are on 82543. If we 2897 * are on newer silicon, we only need to configure 2898 * collision distance in the Transmit Control Register. 2899 * 2) Set up flow control on the MAC to that established with 2900 * the link partner. 2901 * 3) Config DSP to improve Gigabit link quality for some PHY revisions. 2902 * 2903 * hw - Struct containing variables accessed by shared code 2904 ******************************************************************************/ 2905 static int32_t 2906 e1000_copper_link_postconfig(struct e1000_hw *hw) 2907 { 2908 int32_t ret_val; 2909 DEBUGFUNC(); 2910 2911 if (hw->mac_type >= e1000_82544) { 2912 e1000_config_collision_dist(hw); 2913 } else { 2914 ret_val = e1000_config_mac_to_phy(hw); 2915 if (ret_val) { 2916 DEBUGOUT("Error configuring MAC to PHY settings\n"); 2917 return ret_val; 2918 } 2919 } 2920 ret_val = e1000_config_fc_after_link_up(hw); 2921 if (ret_val) { 2922 DEBUGOUT("Error Configuring Flow Control\n"); 2923 return ret_val; 2924 } 2925 return E1000_SUCCESS; 2926 } 2927 2928 /****************************************************************************** 2929 * Detects which PHY is present and setup the speed and duplex 2930 * 2931 * hw - Struct containing variables accessed by shared code 2932 ******************************************************************************/ 2933 static int 2934 e1000_setup_copper_link(struct eth_device *nic) 2935 { 2936 struct e1000_hw *hw = nic->priv; 2937 int32_t ret_val; 2938 uint16_t i; 2939 uint16_t phy_data; 2940 uint16_t reg_data; 2941 2942 DEBUGFUNC(); 2943 2944 switch (hw->mac_type) { 2945 case e1000_80003es2lan: 2946 case e1000_ich8lan: 2947 /* Set the mac to wait the maximum time between each 2948 * iteration and increase the max iterations when 2949 * polling the phy; this fixes erroneous timeouts at 10Mbps. */ 2950 ret_val = e1000_write_kmrn_reg(hw, 2951 GG82563_REG(0x34, 4), 0xFFFF); 2952 if (ret_val) 2953 return ret_val; 2954 ret_val = e1000_read_kmrn_reg(hw, 2955 GG82563_REG(0x34, 9), ®_data); 2956 if (ret_val) 2957 return ret_val; 2958 reg_data |= 0x3F; 2959 ret_val = e1000_write_kmrn_reg(hw, 2960 GG82563_REG(0x34, 9), reg_data); 2961 if (ret_val) 2962 return ret_val; 2963 default: 2964 break; 2965 } 2966 2967 /* Check if it is a valid PHY and set PHY mode if necessary. */ 2968 ret_val = e1000_copper_link_preconfig(hw); 2969 if (ret_val) 2970 return ret_val; 2971 switch (hw->mac_type) { 2972 case e1000_80003es2lan: 2973 /* Kumeran registers are written-only */ 2974 reg_data = 2975 E1000_KUMCTRLSTA_INB_CTRL_LINK_STATUS_TX_TIMEOUT_DEFAULT; 2976 reg_data |= E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING; 2977 ret_val = e1000_write_kmrn_reg(hw, 2978 E1000_KUMCTRLSTA_OFFSET_INB_CTRL, reg_data); 2979 if (ret_val) 2980 return ret_val; 2981 break; 2982 default: 2983 break; 2984 } 2985 2986 if (hw->phy_type == e1000_phy_igp || 2987 hw->phy_type == e1000_phy_igp_3 || 2988 hw->phy_type == e1000_phy_igp_2) { 2989 ret_val = e1000_copper_link_igp_setup(hw); 2990 if (ret_val) 2991 return ret_val; 2992 } else if (hw->phy_type == e1000_phy_m88) { 2993 ret_val = e1000_copper_link_mgp_setup(hw); 2994 if (ret_val) 2995 return ret_val; 2996 } else if (hw->phy_type == e1000_phy_gg82563) { 2997 ret_val = e1000_copper_link_ggp_setup(hw); 2998 if (ret_val) 2999 return ret_val; 3000 } 3001 3002 /* always auto */ 3003 /* Setup autoneg and flow control advertisement 3004 * and perform autonegotiation */ 3005 ret_val = e1000_copper_link_autoneg(hw); 3006 if (ret_val) 3007 return ret_val; 3008 3009 /* Check link status. Wait up to 100 microseconds for link to become 3010 * valid. 3011 */ 3012 for (i = 0; i < 10; i++) { 3013 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); 3014 if (ret_val) 3015 return ret_val; 3016 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); 3017 if (ret_val) 3018 return ret_val; 3019 3020 if (phy_data & MII_SR_LINK_STATUS) { 3021 /* Config the MAC and PHY after link is up */ 3022 ret_val = e1000_copper_link_postconfig(hw); 3023 if (ret_val) 3024 return ret_val; 3025 3026 DEBUGOUT("Valid link established!!!\n"); 3027 return E1000_SUCCESS; 3028 } 3029 udelay(10); 3030 } 3031 3032 DEBUGOUT("Unable to establish link!!!\n"); 3033 return E1000_SUCCESS; 3034 } 3035 3036 /****************************************************************************** 3037 * Configures PHY autoneg and flow control advertisement settings 3038 * 3039 * hw - Struct containing variables accessed by shared code 3040 ******************************************************************************/ 3041 int32_t 3042 e1000_phy_setup_autoneg(struct e1000_hw *hw) 3043 { 3044 int32_t ret_val; 3045 uint16_t mii_autoneg_adv_reg; 3046 uint16_t mii_1000t_ctrl_reg; 3047 3048 DEBUGFUNC(); 3049 3050 /* Read the MII Auto-Neg Advertisement Register (Address 4). */ 3051 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg); 3052 if (ret_val) 3053 return ret_val; 3054 3055 if (hw->phy_type != e1000_phy_ife) { 3056 /* Read the MII 1000Base-T Control Register (Address 9). */ 3057 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, 3058 &mii_1000t_ctrl_reg); 3059 if (ret_val) 3060 return ret_val; 3061 } else 3062 mii_1000t_ctrl_reg = 0; 3063 3064 /* Need to parse both autoneg_advertised and fc and set up 3065 * the appropriate PHY registers. First we will parse for 3066 * autoneg_advertised software override. Since we can advertise 3067 * a plethora of combinations, we need to check each bit 3068 * individually. 3069 */ 3070 3071 /* First we clear all the 10/100 mb speed bits in the Auto-Neg 3072 * Advertisement Register (Address 4) and the 1000 mb speed bits in 3073 * the 1000Base-T Control Register (Address 9). 3074 */ 3075 mii_autoneg_adv_reg &= ~REG4_SPEED_MASK; 3076 mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK; 3077 3078 DEBUGOUT("autoneg_advertised %x\n", hw->autoneg_advertised); 3079 3080 /* Do we want to advertise 10 Mb Half Duplex? */ 3081 if (hw->autoneg_advertised & ADVERTISE_10_HALF) { 3082 DEBUGOUT("Advertise 10mb Half duplex\n"); 3083 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS; 3084 } 3085 3086 /* Do we want to advertise 10 Mb Full Duplex? */ 3087 if (hw->autoneg_advertised & ADVERTISE_10_FULL) { 3088 DEBUGOUT("Advertise 10mb Full duplex\n"); 3089 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS; 3090 } 3091 3092 /* Do we want to advertise 100 Mb Half Duplex? */ 3093 if (hw->autoneg_advertised & ADVERTISE_100_HALF) { 3094 DEBUGOUT("Advertise 100mb Half duplex\n"); 3095 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS; 3096 } 3097 3098 /* Do we want to advertise 100 Mb Full Duplex? */ 3099 if (hw->autoneg_advertised & ADVERTISE_100_FULL) { 3100 DEBUGOUT("Advertise 100mb Full duplex\n"); 3101 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS; 3102 } 3103 3104 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */ 3105 if (hw->autoneg_advertised & ADVERTISE_1000_HALF) { 3106 DEBUGOUT 3107 ("Advertise 1000mb Half duplex requested, request denied!\n"); 3108 } 3109 3110 /* Do we want to advertise 1000 Mb Full Duplex? */ 3111 if (hw->autoneg_advertised & ADVERTISE_1000_FULL) { 3112 DEBUGOUT("Advertise 1000mb Full duplex\n"); 3113 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS; 3114 } 3115 3116 /* Check for a software override of the flow control settings, and 3117 * setup the PHY advertisement registers accordingly. If 3118 * auto-negotiation is enabled, then software will have to set the 3119 * "PAUSE" bits to the correct value in the Auto-Negotiation 3120 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation. 3121 * 3122 * The possible values of the "fc" parameter are: 3123 * 0: Flow control is completely disabled 3124 * 1: Rx flow control is enabled (we can receive pause frames 3125 * but not send pause frames). 3126 * 2: Tx flow control is enabled (we can send pause frames 3127 * but we do not support receiving pause frames). 3128 * 3: Both Rx and TX flow control (symmetric) are enabled. 3129 * other: No software override. The flow control configuration 3130 * in the EEPROM is used. 3131 */ 3132 switch (hw->fc) { 3133 case e1000_fc_none: /* 0 */ 3134 /* Flow control (RX & TX) is completely disabled by a 3135 * software over-ride. 3136 */ 3137 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 3138 break; 3139 case e1000_fc_rx_pause: /* 1 */ 3140 /* RX Flow control is enabled, and TX Flow control is 3141 * disabled, by a software over-ride. 3142 */ 3143 /* Since there really isn't a way to advertise that we are 3144 * capable of RX Pause ONLY, we will advertise that we 3145 * support both symmetric and asymmetric RX PAUSE. Later 3146 * (in e1000_config_fc_after_link_up) we will disable the 3147 *hw's ability to send PAUSE frames. 3148 */ 3149 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 3150 break; 3151 case e1000_fc_tx_pause: /* 2 */ 3152 /* TX Flow control is enabled, and RX Flow control is 3153 * disabled, by a software over-ride. 3154 */ 3155 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR; 3156 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE; 3157 break; 3158 case e1000_fc_full: /* 3 */ 3159 /* Flow control (both RX and TX) is enabled by a software 3160 * over-ride. 3161 */ 3162 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 3163 break; 3164 default: 3165 DEBUGOUT("Flow control param set incorrectly\n"); 3166 return -E1000_ERR_CONFIG; 3167 } 3168 3169 ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg); 3170 if (ret_val) 3171 return ret_val; 3172 3173 DEBUGOUT("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); 3174 3175 if (hw->phy_type != e1000_phy_ife) { 3176 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, 3177 mii_1000t_ctrl_reg); 3178 if (ret_val) 3179 return ret_val; 3180 } 3181 3182 return E1000_SUCCESS; 3183 } 3184 3185 /****************************************************************************** 3186 * Sets the collision distance in the Transmit Control register 3187 * 3188 * hw - Struct containing variables accessed by shared code 3189 * 3190 * Link should have been established previously. Reads the speed and duplex 3191 * information from the Device Status register. 3192 ******************************************************************************/ 3193 static void 3194 e1000_config_collision_dist(struct e1000_hw *hw) 3195 { 3196 uint32_t tctl, coll_dist; 3197 3198 DEBUGFUNC(); 3199 3200 if (hw->mac_type < e1000_82543) 3201 coll_dist = E1000_COLLISION_DISTANCE_82542; 3202 else 3203 coll_dist = E1000_COLLISION_DISTANCE; 3204 3205 tctl = E1000_READ_REG(hw, TCTL); 3206 3207 tctl &= ~E1000_TCTL_COLD; 3208 tctl |= coll_dist << E1000_COLD_SHIFT; 3209 3210 E1000_WRITE_REG(hw, TCTL, tctl); 3211 E1000_WRITE_FLUSH(hw); 3212 } 3213 3214 /****************************************************************************** 3215 * Sets MAC speed and duplex settings to reflect the those in the PHY 3216 * 3217 * hw - Struct containing variables accessed by shared code 3218 * mii_reg - data to write to the MII control register 3219 * 3220 * The contents of the PHY register containing the needed information need to 3221 * be passed in. 3222 ******************************************************************************/ 3223 static int 3224 e1000_config_mac_to_phy(struct e1000_hw *hw) 3225 { 3226 uint32_t ctrl; 3227 uint16_t phy_data; 3228 3229 DEBUGFUNC(); 3230 3231 /* Read the Device Control Register and set the bits to Force Speed 3232 * and Duplex. 3233 */ 3234 ctrl = E1000_READ_REG(hw, CTRL); 3235 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 3236 ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS); 3237 3238 /* Set up duplex in the Device Control and Transmit Control 3239 * registers depending on negotiated values. 3240 */ 3241 if (e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data) < 0) { 3242 DEBUGOUT("PHY Read Error\n"); 3243 return -E1000_ERR_PHY; 3244 } 3245 if (phy_data & M88E1000_PSSR_DPLX) 3246 ctrl |= E1000_CTRL_FD; 3247 else 3248 ctrl &= ~E1000_CTRL_FD; 3249 3250 e1000_config_collision_dist(hw); 3251 3252 /* Set up speed in the Device Control register depending on 3253 * negotiated values. 3254 */ 3255 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) 3256 ctrl |= E1000_CTRL_SPD_1000; 3257 else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS) 3258 ctrl |= E1000_CTRL_SPD_100; 3259 /* Write the configured values back to the Device Control Reg. */ 3260 E1000_WRITE_REG(hw, CTRL, ctrl); 3261 return 0; 3262 } 3263 3264 /****************************************************************************** 3265 * Forces the MAC's flow control settings. 3266 * 3267 * hw - Struct containing variables accessed by shared code 3268 * 3269 * Sets the TFCE and RFCE bits in the device control register to reflect 3270 * the adapter settings. TFCE and RFCE need to be explicitly set by 3271 * software when a Copper PHY is used because autonegotiation is managed 3272 * by the PHY rather than the MAC. Software must also configure these 3273 * bits when link is forced on a fiber connection. 3274 *****************************************************************************/ 3275 static int 3276 e1000_force_mac_fc(struct e1000_hw *hw) 3277 { 3278 uint32_t ctrl; 3279 3280 DEBUGFUNC(); 3281 3282 /* Get the current configuration of the Device Control Register */ 3283 ctrl = E1000_READ_REG(hw, CTRL); 3284 3285 /* Because we didn't get link via the internal auto-negotiation 3286 * mechanism (we either forced link or we got link via PHY 3287 * auto-neg), we have to manually enable/disable transmit an 3288 * receive flow control. 3289 * 3290 * The "Case" statement below enables/disable flow control 3291 * according to the "hw->fc" parameter. 3292 * 3293 * The possible values of the "fc" parameter are: 3294 * 0: Flow control is completely disabled 3295 * 1: Rx flow control is enabled (we can receive pause 3296 * frames but not send pause frames). 3297 * 2: Tx flow control is enabled (we can send pause frames 3298 * frames but we do not receive pause frames). 3299 * 3: Both Rx and TX flow control (symmetric) is enabled. 3300 * other: No other values should be possible at this point. 3301 */ 3302 3303 switch (hw->fc) { 3304 case e1000_fc_none: 3305 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE)); 3306 break; 3307 case e1000_fc_rx_pause: 3308 ctrl &= (~E1000_CTRL_TFCE); 3309 ctrl |= E1000_CTRL_RFCE; 3310 break; 3311 case e1000_fc_tx_pause: 3312 ctrl &= (~E1000_CTRL_RFCE); 3313 ctrl |= E1000_CTRL_TFCE; 3314 break; 3315 case e1000_fc_full: 3316 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE); 3317 break; 3318 default: 3319 DEBUGOUT("Flow control param set incorrectly\n"); 3320 return -E1000_ERR_CONFIG; 3321 } 3322 3323 /* Disable TX Flow Control for 82542 (rev 2.0) */ 3324 if (hw->mac_type == e1000_82542_rev2_0) 3325 ctrl &= (~E1000_CTRL_TFCE); 3326 3327 E1000_WRITE_REG(hw, CTRL, ctrl); 3328 return 0; 3329 } 3330 3331 /****************************************************************************** 3332 * Configures flow control settings after link is established 3333 * 3334 * hw - Struct containing variables accessed by shared code 3335 * 3336 * Should be called immediately after a valid link has been established. 3337 * Forces MAC flow control settings if link was forced. When in MII/GMII mode 3338 * and autonegotiation is enabled, the MAC flow control settings will be set 3339 * based on the flow control negotiated by the PHY. In TBI mode, the TFCE 3340 * and RFCE bits will be automaticaly set to the negotiated flow control mode. 3341 *****************************************************************************/ 3342 static int32_t 3343 e1000_config_fc_after_link_up(struct e1000_hw *hw) 3344 { 3345 int32_t ret_val; 3346 uint16_t mii_status_reg; 3347 uint16_t mii_nway_adv_reg; 3348 uint16_t mii_nway_lp_ability_reg; 3349 uint16_t speed; 3350 uint16_t duplex; 3351 3352 DEBUGFUNC(); 3353 3354 /* Check for the case where we have fiber media and auto-neg failed 3355 * so we had to force link. In this case, we need to force the 3356 * configuration of the MAC to match the "fc" parameter. 3357 */ 3358 if (((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed)) 3359 || ((hw->media_type == e1000_media_type_internal_serdes) 3360 && (hw->autoneg_failed)) 3361 || ((hw->media_type == e1000_media_type_copper) 3362 && (!hw->autoneg))) { 3363 ret_val = e1000_force_mac_fc(hw); 3364 if (ret_val < 0) { 3365 DEBUGOUT("Error forcing flow control settings\n"); 3366 return ret_val; 3367 } 3368 } 3369 3370 /* Check for the case where we have copper media and auto-neg is 3371 * enabled. In this case, we need to check and see if Auto-Neg 3372 * has completed, and if so, how the PHY and link partner has 3373 * flow control configured. 3374 */ 3375 if (hw->media_type == e1000_media_type_copper) { 3376 /* Read the MII Status Register and check to see if AutoNeg 3377 * has completed. We read this twice because this reg has 3378 * some "sticky" (latched) bits. 3379 */ 3380 if (e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) { 3381 DEBUGOUT("PHY Read Error \n"); 3382 return -E1000_ERR_PHY; 3383 } 3384 if (e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) { 3385 DEBUGOUT("PHY Read Error \n"); 3386 return -E1000_ERR_PHY; 3387 } 3388 3389 if (mii_status_reg & MII_SR_AUTONEG_COMPLETE) { 3390 /* The AutoNeg process has completed, so we now need to 3391 * read both the Auto Negotiation Advertisement Register 3392 * (Address 4) and the Auto_Negotiation Base Page Ability 3393 * Register (Address 5) to determine how flow control was 3394 * negotiated. 3395 */ 3396 if (e1000_read_phy_reg 3397 (hw, PHY_AUTONEG_ADV, &mii_nway_adv_reg) < 0) { 3398 DEBUGOUT("PHY Read Error\n"); 3399 return -E1000_ERR_PHY; 3400 } 3401 if (e1000_read_phy_reg 3402 (hw, PHY_LP_ABILITY, 3403 &mii_nway_lp_ability_reg) < 0) { 3404 DEBUGOUT("PHY Read Error\n"); 3405 return -E1000_ERR_PHY; 3406 } 3407 3408 /* Two bits in the Auto Negotiation Advertisement Register 3409 * (Address 4) and two bits in the Auto Negotiation Base 3410 * Page Ability Register (Address 5) determine flow control 3411 * for both the PHY and the link partner. The following 3412 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25, 3413 * 1999, describes these PAUSE resolution bits and how flow 3414 * control is determined based upon these settings. 3415 * NOTE: DC = Don't Care 3416 * 3417 * LOCAL DEVICE | LINK PARTNER 3418 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution 3419 *-------|---------|-------|---------|-------------------- 3420 * 0 | 0 | DC | DC | e1000_fc_none 3421 * 0 | 1 | 0 | DC | e1000_fc_none 3422 * 0 | 1 | 1 | 0 | e1000_fc_none 3423 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 3424 * 1 | 0 | 0 | DC | e1000_fc_none 3425 * 1 | DC | 1 | DC | e1000_fc_full 3426 * 1 | 1 | 0 | 0 | e1000_fc_none 3427 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 3428 * 3429 */ 3430 /* Are both PAUSE bits set to 1? If so, this implies 3431 * Symmetric Flow Control is enabled at both ends. The 3432 * ASM_DIR bits are irrelevant per the spec. 3433 * 3434 * For Symmetric Flow Control: 3435 * 3436 * LOCAL DEVICE | LINK PARTNER 3437 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 3438 *-------|---------|-------|---------|-------------------- 3439 * 1 | DC | 1 | DC | e1000_fc_full 3440 * 3441 */ 3442 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 3443 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) { 3444 /* Now we need to check if the user selected RX ONLY 3445 * of pause frames. In this case, we had to advertise 3446 * FULL flow control because we could not advertise RX 3447 * ONLY. Hence, we must now check to see if we need to 3448 * turn OFF the TRANSMISSION of PAUSE frames. 3449 */ 3450 if (hw->original_fc == e1000_fc_full) { 3451 hw->fc = e1000_fc_full; 3452 DEBUGOUT("Flow Control = FULL.\r\n"); 3453 } else { 3454 hw->fc = e1000_fc_rx_pause; 3455 DEBUGOUT 3456 ("Flow Control = RX PAUSE frames only.\r\n"); 3457 } 3458 } 3459 /* For receiving PAUSE frames ONLY. 3460 * 3461 * LOCAL DEVICE | LINK PARTNER 3462 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 3463 *-------|---------|-------|---------|-------------------- 3464 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 3465 * 3466 */ 3467 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) && 3468 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 3469 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 3470 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) 3471 { 3472 hw->fc = e1000_fc_tx_pause; 3473 DEBUGOUT 3474 ("Flow Control = TX PAUSE frames only.\r\n"); 3475 } 3476 /* For transmitting PAUSE frames ONLY. 3477 * 3478 * LOCAL DEVICE | LINK PARTNER 3479 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 3480 *-------|---------|-------|---------|-------------------- 3481 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 3482 * 3483 */ 3484 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 3485 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 3486 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 3487 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) 3488 { 3489 hw->fc = e1000_fc_rx_pause; 3490 DEBUGOUT 3491 ("Flow Control = RX PAUSE frames only.\r\n"); 3492 } 3493 /* Per the IEEE spec, at this point flow control should be 3494 * disabled. However, we want to consider that we could 3495 * be connected to a legacy switch that doesn't advertise 3496 * desired flow control, but can be forced on the link 3497 * partner. So if we advertised no flow control, that is 3498 * what we will resolve to. If we advertised some kind of 3499 * receive capability (Rx Pause Only or Full Flow Control) 3500 * and the link partner advertised none, we will configure 3501 * ourselves to enable Rx Flow Control only. We can do 3502 * this safely for two reasons: If the link partner really 3503 * didn't want flow control enabled, and we enable Rx, no 3504 * harm done since we won't be receiving any PAUSE frames 3505 * anyway. If the intent on the link partner was to have 3506 * flow control enabled, then by us enabling RX only, we 3507 * can at least receive pause frames and process them. 3508 * This is a good idea because in most cases, since we are 3509 * predominantly a server NIC, more times than not we will 3510 * be asked to delay transmission of packets than asking 3511 * our link partner to pause transmission of frames. 3512 */ 3513 else if (hw->original_fc == e1000_fc_none || 3514 hw->original_fc == e1000_fc_tx_pause) { 3515 hw->fc = e1000_fc_none; 3516 DEBUGOUT("Flow Control = NONE.\r\n"); 3517 } else { 3518 hw->fc = e1000_fc_rx_pause; 3519 DEBUGOUT 3520 ("Flow Control = RX PAUSE frames only.\r\n"); 3521 } 3522 3523 /* Now we need to do one last check... If we auto- 3524 * negotiated to HALF DUPLEX, flow control should not be 3525 * enabled per IEEE 802.3 spec. 3526 */ 3527 e1000_get_speed_and_duplex(hw, &speed, &duplex); 3528 3529 if (duplex == HALF_DUPLEX) 3530 hw->fc = e1000_fc_none; 3531 3532 /* Now we call a subroutine to actually force the MAC 3533 * controller to use the correct flow control settings. 3534 */ 3535 ret_val = e1000_force_mac_fc(hw); 3536 if (ret_val < 0) { 3537 DEBUGOUT 3538 ("Error forcing flow control settings\n"); 3539 return ret_val; 3540 } 3541 } else { 3542 DEBUGOUT 3543 ("Copper PHY and Auto Neg has not completed.\r\n"); 3544 } 3545 } 3546 return E1000_SUCCESS; 3547 } 3548 3549 /****************************************************************************** 3550 * Checks to see if the link status of the hardware has changed. 3551 * 3552 * hw - Struct containing variables accessed by shared code 3553 * 3554 * Called by any function that needs to check the link status of the adapter. 3555 *****************************************************************************/ 3556 static int 3557 e1000_check_for_link(struct eth_device *nic) 3558 { 3559 struct e1000_hw *hw = nic->priv; 3560 uint32_t rxcw; 3561 uint32_t ctrl; 3562 uint32_t status; 3563 uint32_t rctl; 3564 uint32_t signal; 3565 int32_t ret_val; 3566 uint16_t phy_data; 3567 uint16_t lp_capability; 3568 3569 DEBUGFUNC(); 3570 3571 /* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be 3572 * set when the optics detect a signal. On older adapters, it will be 3573 * cleared when there is a signal 3574 */ 3575 ctrl = E1000_READ_REG(hw, CTRL); 3576 if ((hw->mac_type > e1000_82544) && !(ctrl & E1000_CTRL_ILOS)) 3577 signal = E1000_CTRL_SWDPIN1; 3578 else 3579 signal = 0; 3580 3581 status = E1000_READ_REG(hw, STATUS); 3582 rxcw = E1000_READ_REG(hw, RXCW); 3583 DEBUGOUT("ctrl: %#08x status %#08x rxcw %#08x\n", ctrl, status, rxcw); 3584 3585 /* If we have a copper PHY then we only want to go out to the PHY 3586 * registers to see if Auto-Neg has completed and/or if our link 3587 * status has changed. The get_link_status flag will be set if we 3588 * receive a Link Status Change interrupt or we have Rx Sequence 3589 * Errors. 3590 */ 3591 if ((hw->media_type == e1000_media_type_copper) && hw->get_link_status) { 3592 /* First we want to see if the MII Status Register reports 3593 * link. If so, then we want to get the current speed/duplex 3594 * of the PHY. 3595 * Read the register twice since the link bit is sticky. 3596 */ 3597 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) { 3598 DEBUGOUT("PHY Read Error\n"); 3599 return -E1000_ERR_PHY; 3600 } 3601 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) { 3602 DEBUGOUT("PHY Read Error\n"); 3603 return -E1000_ERR_PHY; 3604 } 3605 3606 if (phy_data & MII_SR_LINK_STATUS) { 3607 hw->get_link_status = FALSE; 3608 } else { 3609 /* No link detected */ 3610 return -E1000_ERR_NOLINK; 3611 } 3612 3613 /* We have a M88E1000 PHY and Auto-Neg is enabled. If we 3614 * have Si on board that is 82544 or newer, Auto 3615 * Speed Detection takes care of MAC speed/duplex 3616 * configuration. So we only need to configure Collision 3617 * Distance in the MAC. Otherwise, we need to force 3618 * speed/duplex on the MAC to the current PHY speed/duplex 3619 * settings. 3620 */ 3621 if (hw->mac_type >= e1000_82544) 3622 e1000_config_collision_dist(hw); 3623 else { 3624 ret_val = e1000_config_mac_to_phy(hw); 3625 if (ret_val < 0) { 3626 DEBUGOUT 3627 ("Error configuring MAC to PHY settings\n"); 3628 return ret_val; 3629 } 3630 } 3631 3632 /* Configure Flow Control now that Auto-Neg has completed. First, we 3633 * need to restore the desired flow control settings because we may 3634 * have had to re-autoneg with a different link partner. 3635 */ 3636 ret_val = e1000_config_fc_after_link_up(hw); 3637 if (ret_val < 0) { 3638 DEBUGOUT("Error configuring flow control\n"); 3639 return ret_val; 3640 } 3641 3642 /* At this point we know that we are on copper and we have 3643 * auto-negotiated link. These are conditions for checking the link 3644 * parter capability register. We use the link partner capability to 3645 * determine if TBI Compatibility needs to be turned on or off. If 3646 * the link partner advertises any speed in addition to Gigabit, then 3647 * we assume that they are GMII-based, and TBI compatibility is not 3648 * needed. If no other speeds are advertised, we assume the link 3649 * partner is TBI-based, and we turn on TBI Compatibility. 3650 */ 3651 if (hw->tbi_compatibility_en) { 3652 if (e1000_read_phy_reg 3653 (hw, PHY_LP_ABILITY, &lp_capability) < 0) { 3654 DEBUGOUT("PHY Read Error\n"); 3655 return -E1000_ERR_PHY; 3656 } 3657 if (lp_capability & (NWAY_LPAR_10T_HD_CAPS | 3658 NWAY_LPAR_10T_FD_CAPS | 3659 NWAY_LPAR_100TX_HD_CAPS | 3660 NWAY_LPAR_100TX_FD_CAPS | 3661 NWAY_LPAR_100T4_CAPS)) { 3662 /* If our link partner advertises anything in addition to 3663 * gigabit, we do not need to enable TBI compatibility. 3664 */ 3665 if (hw->tbi_compatibility_on) { 3666 /* If we previously were in the mode, turn it off. */ 3667 rctl = E1000_READ_REG(hw, RCTL); 3668 rctl &= ~E1000_RCTL_SBP; 3669 E1000_WRITE_REG(hw, RCTL, rctl); 3670 hw->tbi_compatibility_on = FALSE; 3671 } 3672 } else { 3673 /* If TBI compatibility is was previously off, turn it on. For 3674 * compatibility with a TBI link partner, we will store bad 3675 * packets. Some frames have an additional byte on the end and 3676 * will look like CRC errors to to the hardware. 3677 */ 3678 if (!hw->tbi_compatibility_on) { 3679 hw->tbi_compatibility_on = TRUE; 3680 rctl = E1000_READ_REG(hw, RCTL); 3681 rctl |= E1000_RCTL_SBP; 3682 E1000_WRITE_REG(hw, RCTL, rctl); 3683 } 3684 } 3685 } 3686 } 3687 /* If we don't have link (auto-negotiation failed or link partner cannot 3688 * auto-negotiate), the cable is plugged in (we have signal), and our 3689 * link partner is not trying to auto-negotiate with us (we are receiving 3690 * idles or data), we need to force link up. We also need to give 3691 * auto-negotiation time to complete, in case the cable was just plugged 3692 * in. The autoneg_failed flag does this. 3693 */ 3694 else if ((hw->media_type == e1000_media_type_fiber) && 3695 (!(status & E1000_STATUS_LU)) && 3696 ((ctrl & E1000_CTRL_SWDPIN1) == signal) && 3697 (!(rxcw & E1000_RXCW_C))) { 3698 if (hw->autoneg_failed == 0) { 3699 hw->autoneg_failed = 1; 3700 return 0; 3701 } 3702 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\r\n"); 3703 3704 /* Disable auto-negotiation in the TXCW register */ 3705 E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE)); 3706 3707 /* Force link-up and also force full-duplex. */ 3708 ctrl = E1000_READ_REG(hw, CTRL); 3709 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 3710 E1000_WRITE_REG(hw, CTRL, ctrl); 3711 3712 /* Configure Flow Control after forcing link up. */ 3713 ret_val = e1000_config_fc_after_link_up(hw); 3714 if (ret_val < 0) { 3715 DEBUGOUT("Error configuring flow control\n"); 3716 return ret_val; 3717 } 3718 } 3719 /* If we are forcing link and we are receiving /C/ ordered sets, re-enable 3720 * auto-negotiation in the TXCW register and disable forced link in the 3721 * Device Control register in an attempt to auto-negotiate with our link 3722 * partner. 3723 */ 3724 else if ((hw->media_type == e1000_media_type_fiber) && 3725 (ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { 3726 DEBUGOUT 3727 ("RXing /C/, enable AutoNeg and stop forcing link.\r\n"); 3728 E1000_WRITE_REG(hw, TXCW, hw->txcw); 3729 E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU)); 3730 } 3731 return 0; 3732 } 3733 3734 /****************************************************************************** 3735 * Configure the MAC-to-PHY interface for 10/100Mbps 3736 * 3737 * hw - Struct containing variables accessed by shared code 3738 ******************************************************************************/ 3739 static int32_t 3740 e1000_configure_kmrn_for_10_100(struct e1000_hw *hw, uint16_t duplex) 3741 { 3742 int32_t ret_val = E1000_SUCCESS; 3743 uint32_t tipg; 3744 uint16_t reg_data; 3745 3746 DEBUGFUNC(); 3747 3748 reg_data = E1000_KUMCTRLSTA_HD_CTRL_10_100_DEFAULT; 3749 ret_val = e1000_write_kmrn_reg(hw, 3750 E1000_KUMCTRLSTA_OFFSET_HD_CTRL, reg_data); 3751 if (ret_val) 3752 return ret_val; 3753 3754 /* Configure Transmit Inter-Packet Gap */ 3755 tipg = E1000_READ_REG(hw, TIPG); 3756 tipg &= ~E1000_TIPG_IPGT_MASK; 3757 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_10_100; 3758 E1000_WRITE_REG(hw, TIPG, tipg); 3759 3760 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data); 3761 3762 if (ret_val) 3763 return ret_val; 3764 3765 if (duplex == HALF_DUPLEX) 3766 reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER; 3767 else 3768 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; 3769 3770 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data); 3771 3772 return ret_val; 3773 } 3774 3775 static int32_t 3776 e1000_configure_kmrn_for_1000(struct e1000_hw *hw) 3777 { 3778 int32_t ret_val = E1000_SUCCESS; 3779 uint16_t reg_data; 3780 uint32_t tipg; 3781 3782 DEBUGFUNC(); 3783 3784 reg_data = E1000_KUMCTRLSTA_HD_CTRL_1000_DEFAULT; 3785 ret_val = e1000_write_kmrn_reg(hw, 3786 E1000_KUMCTRLSTA_OFFSET_HD_CTRL, reg_data); 3787 if (ret_val) 3788 return ret_val; 3789 3790 /* Configure Transmit Inter-Packet Gap */ 3791 tipg = E1000_READ_REG(hw, TIPG); 3792 tipg &= ~E1000_TIPG_IPGT_MASK; 3793 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000; 3794 E1000_WRITE_REG(hw, TIPG, tipg); 3795 3796 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data); 3797 3798 if (ret_val) 3799 return ret_val; 3800 3801 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; 3802 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data); 3803 3804 return ret_val; 3805 } 3806 3807 /****************************************************************************** 3808 * Detects the current speed and duplex settings of the hardware. 3809 * 3810 * hw - Struct containing variables accessed by shared code 3811 * speed - Speed of the connection 3812 * duplex - Duplex setting of the connection 3813 *****************************************************************************/ 3814 static int 3815 e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t *speed, 3816 uint16_t *duplex) 3817 { 3818 uint32_t status; 3819 int32_t ret_val; 3820 uint16_t phy_data; 3821 3822 DEBUGFUNC(); 3823 3824 if (hw->mac_type >= e1000_82543) { 3825 status = E1000_READ_REG(hw, STATUS); 3826 if (status & E1000_STATUS_SPEED_1000) { 3827 *speed = SPEED_1000; 3828 DEBUGOUT("1000 Mbs, "); 3829 } else if (status & E1000_STATUS_SPEED_100) { 3830 *speed = SPEED_100; 3831 DEBUGOUT("100 Mbs, "); 3832 } else { 3833 *speed = SPEED_10; 3834 DEBUGOUT("10 Mbs, "); 3835 } 3836 3837 if (status & E1000_STATUS_FD) { 3838 *duplex = FULL_DUPLEX; 3839 DEBUGOUT("Full Duplex\r\n"); 3840 } else { 3841 *duplex = HALF_DUPLEX; 3842 DEBUGOUT(" Half Duplex\r\n"); 3843 } 3844 } else { 3845 DEBUGOUT("1000 Mbs, Full Duplex\r\n"); 3846 *speed = SPEED_1000; 3847 *duplex = FULL_DUPLEX; 3848 } 3849 3850 /* IGP01 PHY may advertise full duplex operation after speed downgrade 3851 * even if it is operating at half duplex. Here we set the duplex 3852 * settings to match the duplex in the link partner's capabilities. 3853 */ 3854 if (hw->phy_type == e1000_phy_igp && hw->speed_downgraded) { 3855 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data); 3856 if (ret_val) 3857 return ret_val; 3858 3859 if (!(phy_data & NWAY_ER_LP_NWAY_CAPS)) 3860 *duplex = HALF_DUPLEX; 3861 else { 3862 ret_val = e1000_read_phy_reg(hw, 3863 PHY_LP_ABILITY, &phy_data); 3864 if (ret_val) 3865 return ret_val; 3866 if ((*speed == SPEED_100 && 3867 !(phy_data & NWAY_LPAR_100TX_FD_CAPS)) 3868 || (*speed == SPEED_10 3869 && !(phy_data & NWAY_LPAR_10T_FD_CAPS))) 3870 *duplex = HALF_DUPLEX; 3871 } 3872 } 3873 3874 if ((hw->mac_type == e1000_80003es2lan) && 3875 (hw->media_type == e1000_media_type_copper)) { 3876 if (*speed == SPEED_1000) 3877 ret_val = e1000_configure_kmrn_for_1000(hw); 3878 else 3879 ret_val = e1000_configure_kmrn_for_10_100(hw, *duplex); 3880 if (ret_val) 3881 return ret_val; 3882 } 3883 return E1000_SUCCESS; 3884 } 3885 3886 /****************************************************************************** 3887 * Blocks until autoneg completes or times out (~4.5 seconds) 3888 * 3889 * hw - Struct containing variables accessed by shared code 3890 ******************************************************************************/ 3891 static int 3892 e1000_wait_autoneg(struct e1000_hw *hw) 3893 { 3894 uint16_t i; 3895 uint16_t phy_data; 3896 3897 DEBUGFUNC(); 3898 DEBUGOUT("Waiting for Auto-Neg to complete.\n"); 3899 3900 /* We will wait for autoneg to complete or 4.5 seconds to expire. */ 3901 for (i = PHY_AUTO_NEG_TIME; i > 0; i--) { 3902 /* Read the MII Status Register and wait for Auto-Neg 3903 * Complete bit to be set. 3904 */ 3905 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) { 3906 DEBUGOUT("PHY Read Error\n"); 3907 return -E1000_ERR_PHY; 3908 } 3909 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) { 3910 DEBUGOUT("PHY Read Error\n"); 3911 return -E1000_ERR_PHY; 3912 } 3913 if (phy_data & MII_SR_AUTONEG_COMPLETE) { 3914 DEBUGOUT("Auto-Neg complete.\n"); 3915 return 0; 3916 } 3917 mdelay(100); 3918 } 3919 DEBUGOUT("Auto-Neg timedout.\n"); 3920 return -E1000_ERR_TIMEOUT; 3921 } 3922 3923 /****************************************************************************** 3924 * Raises the Management Data Clock 3925 * 3926 * hw - Struct containing variables accessed by shared code 3927 * ctrl - Device control register's current value 3928 ******************************************************************************/ 3929 static void 3930 e1000_raise_mdi_clk(struct e1000_hw *hw, uint32_t * ctrl) 3931 { 3932 /* Raise the clock input to the Management Data Clock (by setting the MDC 3933 * bit), and then delay 2 microseconds. 3934 */ 3935 E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC)); 3936 E1000_WRITE_FLUSH(hw); 3937 udelay(2); 3938 } 3939 3940 /****************************************************************************** 3941 * Lowers the Management Data Clock 3942 * 3943 * hw - Struct containing variables accessed by shared code 3944 * ctrl - Device control register's current value 3945 ******************************************************************************/ 3946 static void 3947 e1000_lower_mdi_clk(struct e1000_hw *hw, uint32_t * ctrl) 3948 { 3949 /* Lower the clock input to the Management Data Clock (by clearing the MDC 3950 * bit), and then delay 2 microseconds. 3951 */ 3952 E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC)); 3953 E1000_WRITE_FLUSH(hw); 3954 udelay(2); 3955 } 3956 3957 /****************************************************************************** 3958 * Shifts data bits out to the PHY 3959 * 3960 * hw - Struct containing variables accessed by shared code 3961 * data - Data to send out to the PHY 3962 * count - Number of bits to shift out 3963 * 3964 * Bits are shifted out in MSB to LSB order. 3965 ******************************************************************************/ 3966 static void 3967 e1000_shift_out_mdi_bits(struct e1000_hw *hw, uint32_t data, uint16_t count) 3968 { 3969 uint32_t ctrl; 3970 uint32_t mask; 3971 3972 /* We need to shift "count" number of bits out to the PHY. So, the value 3973 * in the "data" parameter will be shifted out to the PHY one bit at a 3974 * time. In order to do this, "data" must be broken down into bits. 3975 */ 3976 mask = 0x01; 3977 mask <<= (count - 1); 3978 3979 ctrl = E1000_READ_REG(hw, CTRL); 3980 3981 /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */ 3982 ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR); 3983 3984 while (mask) { 3985 /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and 3986 * then raising and lowering the Management Data Clock. A "0" is 3987 * shifted out to the PHY by setting the MDIO bit to "0" and then 3988 * raising and lowering the clock. 3989 */ 3990 if (data & mask) 3991 ctrl |= E1000_CTRL_MDIO; 3992 else 3993 ctrl &= ~E1000_CTRL_MDIO; 3994 3995 E1000_WRITE_REG(hw, CTRL, ctrl); 3996 E1000_WRITE_FLUSH(hw); 3997 3998 udelay(2); 3999 4000 e1000_raise_mdi_clk(hw, &ctrl); 4001 e1000_lower_mdi_clk(hw, &ctrl); 4002 4003 mask = mask >> 1; 4004 } 4005 } 4006 4007 /****************************************************************************** 4008 * Shifts data bits in from the PHY 4009 * 4010 * hw - Struct containing variables accessed by shared code 4011 * 4012 * Bits are shifted in in MSB to LSB order. 4013 ******************************************************************************/ 4014 static uint16_t 4015 e1000_shift_in_mdi_bits(struct e1000_hw *hw) 4016 { 4017 uint32_t ctrl; 4018 uint16_t data = 0; 4019 uint8_t i; 4020 4021 /* In order to read a register from the PHY, we need to shift in a total 4022 * of 18 bits from the PHY. The first two bit (turnaround) times are used 4023 * to avoid contention on the MDIO pin when a read operation is performed. 4024 * These two bits are ignored by us and thrown away. Bits are "shifted in" 4025 * by raising the input to the Management Data Clock (setting the MDC bit), 4026 * and then reading the value of the MDIO bit. 4027 */ 4028 ctrl = E1000_READ_REG(hw, CTRL); 4029 4030 /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */ 4031 ctrl &= ~E1000_CTRL_MDIO_DIR; 4032 ctrl &= ~E1000_CTRL_MDIO; 4033 4034 E1000_WRITE_REG(hw, CTRL, ctrl); 4035 E1000_WRITE_FLUSH(hw); 4036 4037 /* Raise and Lower the clock before reading in the data. This accounts for 4038 * the turnaround bits. The first clock occurred when we clocked out the 4039 * last bit of the Register Address. 4040 */ 4041 e1000_raise_mdi_clk(hw, &ctrl); 4042 e1000_lower_mdi_clk(hw, &ctrl); 4043 4044 for (data = 0, i = 0; i < 16; i++) { 4045 data = data << 1; 4046 e1000_raise_mdi_clk(hw, &ctrl); 4047 ctrl = E1000_READ_REG(hw, CTRL); 4048 /* Check to see if we shifted in a "1". */ 4049 if (ctrl & E1000_CTRL_MDIO) 4050 data |= 1; 4051 e1000_lower_mdi_clk(hw, &ctrl); 4052 } 4053 4054 e1000_raise_mdi_clk(hw, &ctrl); 4055 e1000_lower_mdi_clk(hw, &ctrl); 4056 4057 return data; 4058 } 4059 4060 /***************************************************************************** 4061 * Reads the value from a PHY register 4062 * 4063 * hw - Struct containing variables accessed by shared code 4064 * reg_addr - address of the PHY register to read 4065 ******************************************************************************/ 4066 static int 4067 e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t * phy_data) 4068 { 4069 uint32_t i; 4070 uint32_t mdic = 0; 4071 const uint32_t phy_addr = 1; 4072 4073 if (reg_addr > MAX_PHY_REG_ADDRESS) { 4074 DEBUGOUT("PHY Address %d is out of range\n", reg_addr); 4075 return -E1000_ERR_PARAM; 4076 } 4077 4078 if (hw->mac_type > e1000_82543) { 4079 /* Set up Op-code, Phy Address, and register address in the MDI 4080 * Control register. The MAC will take care of interfacing with the 4081 * PHY to retrieve the desired data. 4082 */ 4083 mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) | 4084 (phy_addr << E1000_MDIC_PHY_SHIFT) | 4085 (E1000_MDIC_OP_READ)); 4086 4087 E1000_WRITE_REG(hw, MDIC, mdic); 4088 4089 /* Poll the ready bit to see if the MDI read completed */ 4090 for (i = 0; i < 64; i++) { 4091 udelay(10); 4092 mdic = E1000_READ_REG(hw, MDIC); 4093 if (mdic & E1000_MDIC_READY) 4094 break; 4095 } 4096 if (!(mdic & E1000_MDIC_READY)) { 4097 DEBUGOUT("MDI Read did not complete\n"); 4098 return -E1000_ERR_PHY; 4099 } 4100 if (mdic & E1000_MDIC_ERROR) { 4101 DEBUGOUT("MDI Error\n"); 4102 return -E1000_ERR_PHY; 4103 } 4104 *phy_data = (uint16_t) mdic; 4105 } else { 4106 /* We must first send a preamble through the MDIO pin to signal the 4107 * beginning of an MII instruction. This is done by sending 32 4108 * consecutive "1" bits. 4109 */ 4110 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); 4111 4112 /* Now combine the next few fields that are required for a read 4113 * operation. We use this method instead of calling the 4114 * e1000_shift_out_mdi_bits routine five different times. The format of 4115 * a MII read instruction consists of a shift out of 14 bits and is 4116 * defined as follows: 4117 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr> 4118 * followed by a shift in of 18 bits. This first two bits shifted in 4119 * are TurnAround bits used to avoid contention on the MDIO pin when a 4120 * READ operation is performed. These two bits are thrown away 4121 * followed by a shift in of 16 bits which contains the desired data. 4122 */ 4123 mdic = ((reg_addr) | (phy_addr << 5) | 4124 (PHY_OP_READ << 10) | (PHY_SOF << 12)); 4125 4126 e1000_shift_out_mdi_bits(hw, mdic, 14); 4127 4128 /* Now that we've shifted out the read command to the MII, we need to 4129 * "shift in" the 16-bit value (18 total bits) of the requested PHY 4130 * register address. 4131 */ 4132 *phy_data = e1000_shift_in_mdi_bits(hw); 4133 } 4134 return 0; 4135 } 4136 4137 /****************************************************************************** 4138 * Writes a value to a PHY register 4139 * 4140 * hw - Struct containing variables accessed by shared code 4141 * reg_addr - address of the PHY register to write 4142 * data - data to write to the PHY 4143 ******************************************************************************/ 4144 static int 4145 e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t phy_data) 4146 { 4147 uint32_t i; 4148 uint32_t mdic = 0; 4149 const uint32_t phy_addr = 1; 4150 4151 if (reg_addr > MAX_PHY_REG_ADDRESS) { 4152 DEBUGOUT("PHY Address %d is out of range\n", reg_addr); 4153 return -E1000_ERR_PARAM; 4154 } 4155 4156 if (hw->mac_type > e1000_82543) { 4157 /* Set up Op-code, Phy Address, register address, and data intended 4158 * for the PHY register in the MDI Control register. The MAC will take 4159 * care of interfacing with the PHY to send the desired data. 4160 */ 4161 mdic = (((uint32_t) phy_data) | 4162 (reg_addr << E1000_MDIC_REG_SHIFT) | 4163 (phy_addr << E1000_MDIC_PHY_SHIFT) | 4164 (E1000_MDIC_OP_WRITE)); 4165 4166 E1000_WRITE_REG(hw, MDIC, mdic); 4167 4168 /* Poll the ready bit to see if the MDI read completed */ 4169 for (i = 0; i < 64; i++) { 4170 udelay(10); 4171 mdic = E1000_READ_REG(hw, MDIC); 4172 if (mdic & E1000_MDIC_READY) 4173 break; 4174 } 4175 if (!(mdic & E1000_MDIC_READY)) { 4176 DEBUGOUT("MDI Write did not complete\n"); 4177 return -E1000_ERR_PHY; 4178 } 4179 } else { 4180 /* We'll need to use the SW defined pins to shift the write command 4181 * out to the PHY. We first send a preamble to the PHY to signal the 4182 * beginning of the MII instruction. This is done by sending 32 4183 * consecutive "1" bits. 4184 */ 4185 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); 4186 4187 /* Now combine the remaining required fields that will indicate a 4188 * write operation. We use this method instead of calling the 4189 * e1000_shift_out_mdi_bits routine for each field in the command. The 4190 * format of a MII write instruction is as follows: 4191 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>. 4192 */ 4193 mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) | 4194 (PHY_OP_WRITE << 12) | (PHY_SOF << 14)); 4195 mdic <<= 16; 4196 mdic |= (uint32_t) phy_data; 4197 4198 e1000_shift_out_mdi_bits(hw, mdic, 32); 4199 } 4200 return 0; 4201 } 4202 4203 /****************************************************************************** 4204 * Checks if PHY reset is blocked due to SOL/IDER session, for example. 4205 * Returning E1000_BLK_PHY_RESET isn't necessarily an error. But it's up to 4206 * the caller to figure out how to deal with it. 4207 * 4208 * hw - Struct containing variables accessed by shared code 4209 * 4210 * returns: - E1000_BLK_PHY_RESET 4211 * E1000_SUCCESS 4212 * 4213 *****************************************************************************/ 4214 int32_t 4215 e1000_check_phy_reset_block(struct e1000_hw *hw) 4216 { 4217 uint32_t manc = 0; 4218 uint32_t fwsm = 0; 4219 4220 if (hw->mac_type == e1000_ich8lan) { 4221 fwsm = E1000_READ_REG(hw, FWSM); 4222 return (fwsm & E1000_FWSM_RSPCIPHY) ? E1000_SUCCESS 4223 : E1000_BLK_PHY_RESET; 4224 } 4225 4226 if (hw->mac_type > e1000_82547_rev_2) 4227 manc = E1000_READ_REG(hw, MANC); 4228 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ? 4229 E1000_BLK_PHY_RESET : E1000_SUCCESS; 4230 } 4231 4232 /*************************************************************************** 4233 * Checks if the PHY configuration is done 4234 * 4235 * hw: Struct containing variables accessed by shared code 4236 * 4237 * returns: - E1000_ERR_RESET if fail to reset MAC 4238 * E1000_SUCCESS at any other case. 4239 * 4240 ***************************************************************************/ 4241 static int32_t 4242 e1000_get_phy_cfg_done(struct e1000_hw *hw) 4243 { 4244 int32_t timeout = PHY_CFG_TIMEOUT; 4245 uint32_t cfg_mask = E1000_EEPROM_CFG_DONE; 4246 4247 DEBUGFUNC(); 4248 4249 switch (hw->mac_type) { 4250 default: 4251 mdelay(10); 4252 break; 4253 case e1000_80003es2lan: 4254 /* Separate *_CFG_DONE_* bit for each port */ 4255 if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1) 4256 cfg_mask = E1000_EEPROM_CFG_DONE_PORT_1; 4257 /* Fall Through */ 4258 case e1000_82571: 4259 case e1000_82572: 4260 while (timeout) { 4261 if (E1000_READ_REG(hw, EEMNGCTL) & cfg_mask) 4262 break; 4263 else 4264 mdelay(1); 4265 timeout--; 4266 } 4267 if (!timeout) { 4268 DEBUGOUT("MNG configuration cycle has not " 4269 "completed.\n"); 4270 return -E1000_ERR_RESET; 4271 } 4272 break; 4273 } 4274 4275 return E1000_SUCCESS; 4276 } 4277 4278 /****************************************************************************** 4279 * Returns the PHY to the power-on reset state 4280 * 4281 * hw - Struct containing variables accessed by shared code 4282 ******************************************************************************/ 4283 int32_t 4284 e1000_phy_hw_reset(struct e1000_hw *hw) 4285 { 4286 uint32_t ctrl, ctrl_ext; 4287 uint32_t led_ctrl; 4288 int32_t ret_val; 4289 uint16_t swfw; 4290 4291 DEBUGFUNC(); 4292 4293 /* In the case of the phy reset being blocked, it's not an error, we 4294 * simply return success without performing the reset. */ 4295 ret_val = e1000_check_phy_reset_block(hw); 4296 if (ret_val) 4297 return E1000_SUCCESS; 4298 4299 DEBUGOUT("Resetting Phy...\n"); 4300 4301 if (hw->mac_type > e1000_82543) { 4302 if ((hw->mac_type == e1000_80003es2lan) && 4303 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) { 4304 swfw = E1000_SWFW_PHY1_SM; 4305 } else { 4306 swfw = E1000_SWFW_PHY0_SM; 4307 } 4308 if (e1000_swfw_sync_acquire(hw, swfw)) { 4309 DEBUGOUT("Unable to acquire swfw sync\n"); 4310 return -E1000_ERR_SWFW_SYNC; 4311 } 4312 /* Read the device control register and assert the E1000_CTRL_PHY_RST 4313 * bit. Then, take it out of reset. 4314 */ 4315 ctrl = E1000_READ_REG(hw, CTRL); 4316 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST); 4317 E1000_WRITE_FLUSH(hw); 4318 4319 if (hw->mac_type < e1000_82571) 4320 udelay(10); 4321 else 4322 udelay(100); 4323 4324 E1000_WRITE_REG(hw, CTRL, ctrl); 4325 E1000_WRITE_FLUSH(hw); 4326 4327 if (hw->mac_type >= e1000_82571) 4328 mdelay(10); 4329 4330 } else { 4331 /* Read the Extended Device Control Register, assert the PHY_RESET_DIR 4332 * bit to put the PHY into reset. Then, take it out of reset. 4333 */ 4334 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 4335 ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR; 4336 ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA; 4337 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 4338 E1000_WRITE_FLUSH(hw); 4339 mdelay(10); 4340 ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA; 4341 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 4342 E1000_WRITE_FLUSH(hw); 4343 } 4344 udelay(150); 4345 4346 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { 4347 /* Configure activity LED after PHY reset */ 4348 led_ctrl = E1000_READ_REG(hw, LEDCTL); 4349 led_ctrl &= IGP_ACTIVITY_LED_MASK; 4350 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); 4351 E1000_WRITE_REG(hw, LEDCTL, led_ctrl); 4352 } 4353 4354 /* Wait for FW to finish PHY configuration. */ 4355 ret_val = e1000_get_phy_cfg_done(hw); 4356 if (ret_val != E1000_SUCCESS) 4357 return ret_val; 4358 4359 return ret_val; 4360 } 4361 4362 /****************************************************************************** 4363 * IGP phy init script - initializes the GbE PHY 4364 * 4365 * hw - Struct containing variables accessed by shared code 4366 *****************************************************************************/ 4367 static void 4368 e1000_phy_init_script(struct e1000_hw *hw) 4369 { 4370 uint32_t ret_val; 4371 uint16_t phy_saved_data; 4372 DEBUGFUNC(); 4373 4374 if (hw->phy_init_script) { 4375 mdelay(20); 4376 4377 /* Save off the current value of register 0x2F5B to be 4378 * restored at the end of this routine. */ 4379 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data); 4380 4381 /* Disabled the PHY transmitter */ 4382 e1000_write_phy_reg(hw, 0x2F5B, 0x0003); 4383 4384 mdelay(20); 4385 4386 e1000_write_phy_reg(hw, 0x0000, 0x0140); 4387 4388 mdelay(5); 4389 4390 switch (hw->mac_type) { 4391 case e1000_82541: 4392 case e1000_82547: 4393 e1000_write_phy_reg(hw, 0x1F95, 0x0001); 4394 4395 e1000_write_phy_reg(hw, 0x1F71, 0xBD21); 4396 4397 e1000_write_phy_reg(hw, 0x1F79, 0x0018); 4398 4399 e1000_write_phy_reg(hw, 0x1F30, 0x1600); 4400 4401 e1000_write_phy_reg(hw, 0x1F31, 0x0014); 4402 4403 e1000_write_phy_reg(hw, 0x1F32, 0x161C); 4404 4405 e1000_write_phy_reg(hw, 0x1F94, 0x0003); 4406 4407 e1000_write_phy_reg(hw, 0x1F96, 0x003F); 4408 4409 e1000_write_phy_reg(hw, 0x2010, 0x0008); 4410 break; 4411 4412 case e1000_82541_rev_2: 4413 case e1000_82547_rev_2: 4414 e1000_write_phy_reg(hw, 0x1F73, 0x0099); 4415 break; 4416 default: 4417 break; 4418 } 4419 4420 e1000_write_phy_reg(hw, 0x0000, 0x3300); 4421 4422 mdelay(20); 4423 4424 /* Now enable the transmitter */ 4425 e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data); 4426 4427 if (hw->mac_type == e1000_82547) { 4428 uint16_t fused, fine, coarse; 4429 4430 /* Move to analog registers page */ 4431 e1000_read_phy_reg(hw, 4432 IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused); 4433 4434 if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) { 4435 e1000_read_phy_reg(hw, 4436 IGP01E1000_ANALOG_FUSE_STATUS, &fused); 4437 4438 fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK; 4439 coarse = fused 4440 & IGP01E1000_ANALOG_FUSE_COARSE_MASK; 4441 4442 if (coarse > 4443 IGP01E1000_ANALOG_FUSE_COARSE_THRESH) { 4444 coarse -= 4445 IGP01E1000_ANALOG_FUSE_COARSE_10; 4446 fine -= IGP01E1000_ANALOG_FUSE_FINE_1; 4447 } else if (coarse 4448 == IGP01E1000_ANALOG_FUSE_COARSE_THRESH) 4449 fine -= IGP01E1000_ANALOG_FUSE_FINE_10; 4450 4451 fused = (fused 4452 & IGP01E1000_ANALOG_FUSE_POLY_MASK) | 4453 (fine 4454 & IGP01E1000_ANALOG_FUSE_FINE_MASK) | 4455 (coarse 4456 & IGP01E1000_ANALOG_FUSE_COARSE_MASK); 4457 4458 e1000_write_phy_reg(hw, 4459 IGP01E1000_ANALOG_FUSE_CONTROL, fused); 4460 e1000_write_phy_reg(hw, 4461 IGP01E1000_ANALOG_FUSE_BYPASS, 4462 IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL); 4463 } 4464 } 4465 } 4466 } 4467 4468 /****************************************************************************** 4469 * Resets the PHY 4470 * 4471 * hw - Struct containing variables accessed by shared code 4472 * 4473 * Sets bit 15 of the MII Control register 4474 ******************************************************************************/ 4475 int32_t 4476 e1000_phy_reset(struct e1000_hw *hw) 4477 { 4478 int32_t ret_val; 4479 uint16_t phy_data; 4480 4481 DEBUGFUNC(); 4482 4483 /* In the case of the phy reset being blocked, it's not an error, we 4484 * simply return success without performing the reset. */ 4485 ret_val = e1000_check_phy_reset_block(hw); 4486 if (ret_val) 4487 return E1000_SUCCESS; 4488 4489 switch (hw->phy_type) { 4490 case e1000_phy_igp: 4491 case e1000_phy_igp_2: 4492 case e1000_phy_igp_3: 4493 case e1000_phy_ife: 4494 ret_val = e1000_phy_hw_reset(hw); 4495 if (ret_val) 4496 return ret_val; 4497 break; 4498 default: 4499 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data); 4500 if (ret_val) 4501 return ret_val; 4502 4503 phy_data |= MII_CR_RESET; 4504 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data); 4505 if (ret_val) 4506 return ret_val; 4507 4508 udelay(1); 4509 break; 4510 } 4511 4512 if (hw->phy_type == e1000_phy_igp || hw->phy_type == e1000_phy_igp_2) 4513 e1000_phy_init_script(hw); 4514 4515 return E1000_SUCCESS; 4516 } 4517 4518 static int e1000_set_phy_type (struct e1000_hw *hw) 4519 { 4520 DEBUGFUNC (); 4521 4522 if (hw->mac_type == e1000_undefined) 4523 return -E1000_ERR_PHY_TYPE; 4524 4525 switch (hw->phy_id) { 4526 case M88E1000_E_PHY_ID: 4527 case M88E1000_I_PHY_ID: 4528 case M88E1011_I_PHY_ID: 4529 case M88E1111_I_PHY_ID: 4530 hw->phy_type = e1000_phy_m88; 4531 break; 4532 case IGP01E1000_I_PHY_ID: 4533 if (hw->mac_type == e1000_82541 || 4534 hw->mac_type == e1000_82541_rev_2 || 4535 hw->mac_type == e1000_82547 || 4536 hw->mac_type == e1000_82547_rev_2) { 4537 hw->phy_type = e1000_phy_igp; 4538 hw->phy_type = e1000_phy_igp; 4539 break; 4540 } 4541 case IGP03E1000_E_PHY_ID: 4542 hw->phy_type = e1000_phy_igp_3; 4543 break; 4544 case IFE_E_PHY_ID: 4545 case IFE_PLUS_E_PHY_ID: 4546 case IFE_C_E_PHY_ID: 4547 hw->phy_type = e1000_phy_ife; 4548 break; 4549 case GG82563_E_PHY_ID: 4550 if (hw->mac_type == e1000_80003es2lan) { 4551 hw->phy_type = e1000_phy_gg82563; 4552 break; 4553 } 4554 /* Fall Through */ 4555 default: 4556 /* Should never have loaded on this device */ 4557 hw->phy_type = e1000_phy_undefined; 4558 return -E1000_ERR_PHY_TYPE; 4559 } 4560 4561 return E1000_SUCCESS; 4562 } 4563 4564 /****************************************************************************** 4565 * Probes the expected PHY address for known PHY IDs 4566 * 4567 * hw - Struct containing variables accessed by shared code 4568 ******************************************************************************/ 4569 static int32_t 4570 e1000_detect_gig_phy(struct e1000_hw *hw) 4571 { 4572 int32_t phy_init_status, ret_val; 4573 uint16_t phy_id_high, phy_id_low; 4574 boolean_t match = FALSE; 4575 4576 DEBUGFUNC(); 4577 4578 /* The 82571 firmware may still be configuring the PHY. In this 4579 * case, we cannot access the PHY until the configuration is done. So 4580 * we explicitly set the PHY values. */ 4581 if (hw->mac_type == e1000_82571 || 4582 hw->mac_type == e1000_82572) { 4583 hw->phy_id = IGP01E1000_I_PHY_ID; 4584 hw->phy_type = e1000_phy_igp_2; 4585 return E1000_SUCCESS; 4586 } 4587 4588 /* ESB-2 PHY reads require e1000_phy_gg82563 to be set because of a 4589 * work- around that forces PHY page 0 to be set or the reads fail. 4590 * The rest of the code in this routine uses e1000_read_phy_reg to 4591 * read the PHY ID. So for ESB-2 we need to have this set so our 4592 * reads won't fail. If the attached PHY is not a e1000_phy_gg82563, 4593 * the routines below will figure this out as well. */ 4594 if (hw->mac_type == e1000_80003es2lan) 4595 hw->phy_type = e1000_phy_gg82563; 4596 4597 /* Read the PHY ID Registers to identify which PHY is onboard. */ 4598 ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high); 4599 if (ret_val) 4600 return ret_val; 4601 4602 hw->phy_id = (uint32_t) (phy_id_high << 16); 4603 udelay(20); 4604 ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low); 4605 if (ret_val) 4606 return ret_val; 4607 4608 hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK); 4609 hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK; 4610 4611 switch (hw->mac_type) { 4612 case e1000_82543: 4613 if (hw->phy_id == M88E1000_E_PHY_ID) 4614 match = TRUE; 4615 break; 4616 case e1000_82544: 4617 if (hw->phy_id == M88E1000_I_PHY_ID) 4618 match = TRUE; 4619 break; 4620 case e1000_82540: 4621 case e1000_82545: 4622 case e1000_82545_rev_3: 4623 case e1000_82546: 4624 case e1000_82546_rev_3: 4625 if (hw->phy_id == M88E1011_I_PHY_ID) 4626 match = TRUE; 4627 break; 4628 case e1000_82541: 4629 case e1000_82541_rev_2: 4630 case e1000_82547: 4631 case e1000_82547_rev_2: 4632 if(hw->phy_id == IGP01E1000_I_PHY_ID) 4633 match = TRUE; 4634 4635 break; 4636 case e1000_82573: 4637 if (hw->phy_id == M88E1111_I_PHY_ID) 4638 match = TRUE; 4639 break; 4640 case e1000_80003es2lan: 4641 if (hw->phy_id == GG82563_E_PHY_ID) 4642 match = TRUE; 4643 break; 4644 case e1000_ich8lan: 4645 if (hw->phy_id == IGP03E1000_E_PHY_ID) 4646 match = TRUE; 4647 if (hw->phy_id == IFE_E_PHY_ID) 4648 match = TRUE; 4649 if (hw->phy_id == IFE_PLUS_E_PHY_ID) 4650 match = TRUE; 4651 if (hw->phy_id == IFE_C_E_PHY_ID) 4652 match = TRUE; 4653 break; 4654 default: 4655 DEBUGOUT("Invalid MAC type %d\n", hw->mac_type); 4656 return -E1000_ERR_CONFIG; 4657 } 4658 4659 phy_init_status = e1000_set_phy_type(hw); 4660 4661 if ((match) && (phy_init_status == E1000_SUCCESS)) { 4662 DEBUGOUT("PHY ID 0x%X detected\n", hw->phy_id); 4663 return 0; 4664 } 4665 DEBUGOUT("Invalid PHY ID 0x%X\n", hw->phy_id); 4666 return -E1000_ERR_PHY; 4667 } 4668 4669 /***************************************************************************** 4670 * Set media type and TBI compatibility. 4671 * 4672 * hw - Struct containing variables accessed by shared code 4673 * **************************************************************************/ 4674 void 4675 e1000_set_media_type(struct e1000_hw *hw) 4676 { 4677 uint32_t status; 4678 4679 DEBUGFUNC(); 4680 4681 if (hw->mac_type != e1000_82543) { 4682 /* tbi_compatibility is only valid on 82543 */ 4683 hw->tbi_compatibility_en = FALSE; 4684 } 4685 4686 switch (hw->device_id) { 4687 case E1000_DEV_ID_82545GM_SERDES: 4688 case E1000_DEV_ID_82546GB_SERDES: 4689 case E1000_DEV_ID_82571EB_SERDES: 4690 case E1000_DEV_ID_82571EB_SERDES_DUAL: 4691 case E1000_DEV_ID_82571EB_SERDES_QUAD: 4692 case E1000_DEV_ID_82572EI_SERDES: 4693 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT: 4694 hw->media_type = e1000_media_type_internal_serdes; 4695 break; 4696 default: 4697 switch (hw->mac_type) { 4698 case e1000_82542_rev2_0: 4699 case e1000_82542_rev2_1: 4700 hw->media_type = e1000_media_type_fiber; 4701 break; 4702 case e1000_ich8lan: 4703 case e1000_82573: 4704 /* The STATUS_TBIMODE bit is reserved or reused 4705 * for the this device. 4706 */ 4707 hw->media_type = e1000_media_type_copper; 4708 break; 4709 default: 4710 status = E1000_READ_REG(hw, STATUS); 4711 if (status & E1000_STATUS_TBIMODE) { 4712 hw->media_type = e1000_media_type_fiber; 4713 /* tbi_compatibility not valid on fiber */ 4714 hw->tbi_compatibility_en = FALSE; 4715 } else { 4716 hw->media_type = e1000_media_type_copper; 4717 } 4718 break; 4719 } 4720 } 4721 } 4722 4723 /** 4724 * e1000_sw_init - Initialize general software structures (struct e1000_adapter) 4725 * 4726 * e1000_sw_init initializes the Adapter private data structure. 4727 * Fields are initialized based on PCI device information and 4728 * OS network device settings (MTU size). 4729 **/ 4730 4731 static int 4732 e1000_sw_init(struct eth_device *nic, int cardnum) 4733 { 4734 struct e1000_hw *hw = (typeof(hw)) nic->priv; 4735 int result; 4736 4737 /* PCI config space info */ 4738 pci_read_config_word(hw->pdev, PCI_VENDOR_ID, &hw->vendor_id); 4739 pci_read_config_word(hw->pdev, PCI_DEVICE_ID, &hw->device_id); 4740 pci_read_config_word(hw->pdev, PCI_SUBSYSTEM_VENDOR_ID, 4741 &hw->subsystem_vendor_id); 4742 pci_read_config_word(hw->pdev, PCI_SUBSYSTEM_ID, &hw->subsystem_id); 4743 4744 pci_read_config_byte(hw->pdev, PCI_REVISION_ID, &hw->revision_id); 4745 pci_read_config_word(hw->pdev, PCI_COMMAND, &hw->pci_cmd_word); 4746 4747 /* identify the MAC */ 4748 result = e1000_set_mac_type(hw); 4749 if (result) { 4750 E1000_ERR("Unknown MAC Type\n"); 4751 return result; 4752 } 4753 4754 switch (hw->mac_type) { 4755 default: 4756 break; 4757 case e1000_82541: 4758 case e1000_82547: 4759 case e1000_82541_rev_2: 4760 case e1000_82547_rev_2: 4761 hw->phy_init_script = 1; 4762 break; 4763 } 4764 4765 /* lan a vs. lan b settings */ 4766 if (hw->mac_type == e1000_82546) 4767 /*this also works w/ multiple 82546 cards */ 4768 /*but not if they're intermingled /w other e1000s */ 4769 hw->lan_loc = (cardnum % 2) ? e1000_lan_b : e1000_lan_a; 4770 else 4771 hw->lan_loc = e1000_lan_a; 4772 4773 /* flow control settings */ 4774 hw->fc_high_water = E1000_FC_HIGH_THRESH; 4775 hw->fc_low_water = E1000_FC_LOW_THRESH; 4776 hw->fc_pause_time = E1000_FC_PAUSE_TIME; 4777 hw->fc_send_xon = 1; 4778 4779 /* Media type - copper or fiber */ 4780 e1000_set_media_type(hw); 4781 4782 if (hw->mac_type >= e1000_82543) { 4783 uint32_t status = E1000_READ_REG(hw, STATUS); 4784 4785 if (status & E1000_STATUS_TBIMODE) { 4786 DEBUGOUT("fiber interface\n"); 4787 hw->media_type = e1000_media_type_fiber; 4788 } else { 4789 DEBUGOUT("copper interface\n"); 4790 hw->media_type = e1000_media_type_copper; 4791 } 4792 } else { 4793 hw->media_type = e1000_media_type_fiber; 4794 } 4795 4796 hw->tbi_compatibility_en = TRUE; 4797 hw->wait_autoneg_complete = TRUE; 4798 if (hw->mac_type < e1000_82543) 4799 hw->report_tx_early = 0; 4800 else 4801 hw->report_tx_early = 1; 4802 4803 return E1000_SUCCESS; 4804 } 4805 4806 void 4807 fill_rx(struct e1000_hw *hw) 4808 { 4809 struct e1000_rx_desc *rd; 4810 4811 rx_last = rx_tail; 4812 rd = rx_base + rx_tail; 4813 rx_tail = (rx_tail + 1) % 8; 4814 memset(rd, 0, 16); 4815 rd->buffer_addr = cpu_to_le64((u32) & packet); 4816 E1000_WRITE_REG(hw, RDT, rx_tail); 4817 } 4818 4819 /** 4820 * e1000_configure_tx - Configure 8254x Transmit Unit after Reset 4821 * @adapter: board private structure 4822 * 4823 * Configure the Tx unit of the MAC after a reset. 4824 **/ 4825 4826 static void 4827 e1000_configure_tx(struct e1000_hw *hw) 4828 { 4829 unsigned long ptr; 4830 unsigned long tctl; 4831 unsigned long tipg, tarc; 4832 uint32_t ipgr1, ipgr2; 4833 4834 ptr = (u32) tx_pool; 4835 if (ptr & 0xf) 4836 ptr = (ptr + 0x10) & (~0xf); 4837 4838 tx_base = (typeof(tx_base)) ptr; 4839 4840 E1000_WRITE_REG(hw, TDBAL, (u32) tx_base); 4841 E1000_WRITE_REG(hw, TDBAH, 0); 4842 4843 E1000_WRITE_REG(hw, TDLEN, 128); 4844 4845 /* Setup the HW Tx Head and Tail descriptor pointers */ 4846 E1000_WRITE_REG(hw, TDH, 0); 4847 E1000_WRITE_REG(hw, TDT, 0); 4848 tx_tail = 0; 4849 4850 /* Set the default values for the Tx Inter Packet Gap timer */ 4851 if (hw->mac_type <= e1000_82547_rev_2 && 4852 (hw->media_type == e1000_media_type_fiber || 4853 hw->media_type == e1000_media_type_internal_serdes)) 4854 tipg = DEFAULT_82543_TIPG_IPGT_FIBER; 4855 else 4856 tipg = DEFAULT_82543_TIPG_IPGT_COPPER; 4857 4858 /* Set the default values for the Tx Inter Packet Gap timer */ 4859 switch (hw->mac_type) { 4860 case e1000_82542_rev2_0: 4861 case e1000_82542_rev2_1: 4862 tipg = DEFAULT_82542_TIPG_IPGT; 4863 ipgr1 = DEFAULT_82542_TIPG_IPGR1; 4864 ipgr2 = DEFAULT_82542_TIPG_IPGR2; 4865 break; 4866 case e1000_80003es2lan: 4867 ipgr1 = DEFAULT_82543_TIPG_IPGR1; 4868 ipgr2 = DEFAULT_80003ES2LAN_TIPG_IPGR2; 4869 break; 4870 default: 4871 ipgr1 = DEFAULT_82543_TIPG_IPGR1; 4872 ipgr2 = DEFAULT_82543_TIPG_IPGR2; 4873 break; 4874 } 4875 tipg |= ipgr1 << E1000_TIPG_IPGR1_SHIFT; 4876 tipg |= ipgr2 << E1000_TIPG_IPGR2_SHIFT; 4877 E1000_WRITE_REG(hw, TIPG, tipg); 4878 /* Program the Transmit Control Register */ 4879 tctl = E1000_READ_REG(hw, TCTL); 4880 tctl &= ~E1000_TCTL_CT; 4881 tctl |= E1000_TCTL_EN | E1000_TCTL_PSP | 4882 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); 4883 4884 if (hw->mac_type == e1000_82571 || hw->mac_type == e1000_82572) { 4885 tarc = E1000_READ_REG(hw, TARC0); 4886 /* set the speed mode bit, we'll clear it if we're not at 4887 * gigabit link later */ 4888 /* git bit can be set to 1*/ 4889 } else if (hw->mac_type == e1000_80003es2lan) { 4890 tarc = E1000_READ_REG(hw, TARC0); 4891 tarc |= 1; 4892 E1000_WRITE_REG(hw, TARC0, tarc); 4893 tarc = E1000_READ_REG(hw, TARC1); 4894 tarc |= 1; 4895 E1000_WRITE_REG(hw, TARC1, tarc); 4896 } 4897 4898 4899 e1000_config_collision_dist(hw); 4900 /* Setup Transmit Descriptor Settings for eop descriptor */ 4901 hw->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS; 4902 4903 /* Need to set up RS bit */ 4904 if (hw->mac_type < e1000_82543) 4905 hw->txd_cmd |= E1000_TXD_CMD_RPS; 4906 else 4907 hw->txd_cmd |= E1000_TXD_CMD_RS; 4908 E1000_WRITE_REG(hw, TCTL, tctl); 4909 } 4910 4911 /** 4912 * e1000_setup_rctl - configure the receive control register 4913 * @adapter: Board private structure 4914 **/ 4915 static void 4916 e1000_setup_rctl(struct e1000_hw *hw) 4917 { 4918 uint32_t rctl; 4919 4920 rctl = E1000_READ_REG(hw, RCTL); 4921 4922 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 4923 4924 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO 4925 | E1000_RCTL_RDMTS_HALF; /* | 4926 (hw.mc_filter_type << E1000_RCTL_MO_SHIFT); */ 4927 4928 if (hw->tbi_compatibility_on == 1) 4929 rctl |= E1000_RCTL_SBP; 4930 else 4931 rctl &= ~E1000_RCTL_SBP; 4932 4933 rctl &= ~(E1000_RCTL_SZ_4096); 4934 rctl |= E1000_RCTL_SZ_2048; 4935 rctl &= ~(E1000_RCTL_BSEX | E1000_RCTL_LPE); 4936 E1000_WRITE_REG(hw, RCTL, rctl); 4937 } 4938 4939 /** 4940 * e1000_configure_rx - Configure 8254x Receive Unit after Reset 4941 * @adapter: board private structure 4942 * 4943 * Configure the Rx unit of the MAC after a reset. 4944 **/ 4945 static void 4946 e1000_configure_rx(struct e1000_hw *hw) 4947 { 4948 unsigned long ptr; 4949 unsigned long rctl, ctrl_ext; 4950 rx_tail = 0; 4951 /* make sure receives are disabled while setting up the descriptors */ 4952 rctl = E1000_READ_REG(hw, RCTL); 4953 E1000_WRITE_REG(hw, RCTL, rctl & ~E1000_RCTL_EN); 4954 if (hw->mac_type >= e1000_82540) { 4955 /* Set the interrupt throttling rate. Value is calculated 4956 * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns) */ 4957 #define MAX_INTS_PER_SEC 8000 4958 #define DEFAULT_ITR 1000000000/(MAX_INTS_PER_SEC * 256) 4959 E1000_WRITE_REG(hw, ITR, DEFAULT_ITR); 4960 } 4961 4962 if (hw->mac_type >= e1000_82571) { 4963 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 4964 /* Reset delay timers after every interrupt */ 4965 ctrl_ext |= E1000_CTRL_EXT_INT_TIMER_CLR; 4966 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 4967 E1000_WRITE_FLUSH(hw); 4968 } 4969 /* Setup the Base and Length of the Rx Descriptor Ring */ 4970 ptr = (u32) rx_pool; 4971 if (ptr & 0xf) 4972 ptr = (ptr + 0x10) & (~0xf); 4973 rx_base = (typeof(rx_base)) ptr; 4974 E1000_WRITE_REG(hw, RDBAL, (u32) rx_base); 4975 E1000_WRITE_REG(hw, RDBAH, 0); 4976 4977 E1000_WRITE_REG(hw, RDLEN, 128); 4978 4979 /* Setup the HW Rx Head and Tail Descriptor Pointers */ 4980 E1000_WRITE_REG(hw, RDH, 0); 4981 E1000_WRITE_REG(hw, RDT, 0); 4982 /* Enable Receives */ 4983 4984 E1000_WRITE_REG(hw, RCTL, rctl); 4985 fill_rx(hw); 4986 } 4987 4988 /************************************************************************** 4989 POLL - Wait for a frame 4990 ***************************************************************************/ 4991 static int 4992 e1000_poll(struct eth_device *nic) 4993 { 4994 struct e1000_hw *hw = nic->priv; 4995 struct e1000_rx_desc *rd; 4996 /* return true if there's an ethernet packet ready to read */ 4997 rd = rx_base + rx_last; 4998 if (!(le32_to_cpu(rd->status)) & E1000_RXD_STAT_DD) 4999 return 0; 5000 /*DEBUGOUT("recv: packet len=%d \n", rd->length); */ 5001 NetReceive((uchar *)packet, le32_to_cpu(rd->length)); 5002 fill_rx(hw); 5003 return 1; 5004 } 5005 5006 /************************************************************************** 5007 TRANSMIT - Transmit a frame 5008 ***************************************************************************/ 5009 static int 5010 e1000_transmit(struct eth_device *nic, volatile void *packet, int length) 5011 { 5012 struct e1000_hw *hw = nic->priv; 5013 struct e1000_tx_desc *txp; 5014 int i = 0; 5015 5016 txp = tx_base + tx_tail; 5017 tx_tail = (tx_tail + 1) % 8; 5018 5019 txp->buffer_addr = cpu_to_le64(virt_to_bus(hw->pdev, packet)); 5020 txp->lower.data = cpu_to_le32(hw->txd_cmd | length); 5021 txp->upper.data = 0; 5022 E1000_WRITE_REG(hw, TDT, tx_tail); 5023 5024 E1000_WRITE_FLUSH(hw); 5025 while (!(le32_to_cpu(txp->upper.data) & E1000_TXD_STAT_DD)) { 5026 if (i++ > TOUT_LOOP) { 5027 DEBUGOUT("e1000: tx timeout\n"); 5028 return 0; 5029 } 5030 udelay(10); /* give the nic a chance to write to the register */ 5031 } 5032 return 1; 5033 } 5034 5035 /*reset function*/ 5036 static inline int 5037 e1000_reset(struct eth_device *nic) 5038 { 5039 struct e1000_hw *hw = nic->priv; 5040 5041 e1000_reset_hw(hw); 5042 if (hw->mac_type >= e1000_82544) { 5043 E1000_WRITE_REG(hw, WUC, 0); 5044 } 5045 return e1000_init_hw(nic); 5046 } 5047 5048 /************************************************************************** 5049 DISABLE - Turn off ethernet interface 5050 ***************************************************************************/ 5051 static void 5052 e1000_disable(struct eth_device *nic) 5053 { 5054 struct e1000_hw *hw = nic->priv; 5055 5056 /* Turn off the ethernet interface */ 5057 E1000_WRITE_REG(hw, RCTL, 0); 5058 E1000_WRITE_REG(hw, TCTL, 0); 5059 5060 /* Clear the transmit ring */ 5061 E1000_WRITE_REG(hw, TDH, 0); 5062 E1000_WRITE_REG(hw, TDT, 0); 5063 5064 /* Clear the receive ring */ 5065 E1000_WRITE_REG(hw, RDH, 0); 5066 E1000_WRITE_REG(hw, RDT, 0); 5067 5068 /* put the card in its initial state */ 5069 #if 0 5070 E1000_WRITE_REG(hw, CTRL, E1000_CTRL_RST); 5071 #endif 5072 mdelay(10); 5073 5074 } 5075 5076 /************************************************************************** 5077 INIT - set up ethernet interface(s) 5078 ***************************************************************************/ 5079 static int 5080 e1000_init(struct eth_device *nic, bd_t * bis) 5081 { 5082 struct e1000_hw *hw = nic->priv; 5083 int ret_val = 0; 5084 5085 ret_val = e1000_reset(nic); 5086 if (ret_val < 0) { 5087 if ((ret_val == -E1000_ERR_NOLINK) || 5088 (ret_val == -E1000_ERR_TIMEOUT)) { 5089 E1000_ERR("Valid Link not detected\n"); 5090 } else { 5091 E1000_ERR("Hardware Initialization Failed\n"); 5092 } 5093 return 0; 5094 } 5095 e1000_configure_tx(hw); 5096 e1000_setup_rctl(hw); 5097 e1000_configure_rx(hw); 5098 return 1; 5099 } 5100 5101 /****************************************************************************** 5102 * Gets the current PCI bus type of hardware 5103 * 5104 * hw - Struct containing variables accessed by shared code 5105 *****************************************************************************/ 5106 void e1000_get_bus_type(struct e1000_hw *hw) 5107 { 5108 uint32_t status; 5109 5110 switch (hw->mac_type) { 5111 case e1000_82542_rev2_0: 5112 case e1000_82542_rev2_1: 5113 hw->bus_type = e1000_bus_type_pci; 5114 break; 5115 case e1000_82571: 5116 case e1000_82572: 5117 case e1000_82573: 5118 case e1000_80003es2lan: 5119 hw->bus_type = e1000_bus_type_pci_express; 5120 break; 5121 case e1000_ich8lan: 5122 hw->bus_type = e1000_bus_type_pci_express; 5123 break; 5124 default: 5125 status = E1000_READ_REG(hw, STATUS); 5126 hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ? 5127 e1000_bus_type_pcix : e1000_bus_type_pci; 5128 break; 5129 } 5130 } 5131 5132 /************************************************************************** 5133 PROBE - Look for an adapter, this routine's visible to the outside 5134 You should omit the last argument struct pci_device * for a non-PCI NIC 5135 ***************************************************************************/ 5136 int 5137 e1000_initialize(bd_t * bis) 5138 { 5139 pci_dev_t devno; 5140 int card_number = 0; 5141 struct eth_device *nic = NULL; 5142 struct e1000_hw *hw = NULL; 5143 u32 iobase; 5144 int idx = 0; 5145 u32 PciCommandWord; 5146 5147 DEBUGFUNC(); 5148 5149 while (1) { /* Find PCI device(s) */ 5150 if ((devno = pci_find_devices(supported, idx++)) < 0) { 5151 break; 5152 } 5153 5154 pci_read_config_dword(devno, PCI_BASE_ADDRESS_0, &iobase); 5155 iobase &= ~0xf; /* Mask the bits that say "this is an io addr" */ 5156 DEBUGOUT("e1000#%d: iobase 0x%08x\n", card_number, iobase); 5157 5158 pci_write_config_dword(devno, PCI_COMMAND, 5159 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); 5160 /* Check if I/O accesses and Bus Mastering are enabled. */ 5161 pci_read_config_dword(devno, PCI_COMMAND, &PciCommandWord); 5162 if (!(PciCommandWord & PCI_COMMAND_MEMORY)) { 5163 printf("Error: Can not enable MEM access.\n"); 5164 continue; 5165 } else if (!(PciCommandWord & PCI_COMMAND_MASTER)) { 5166 printf("Error: Can not enable Bus Mastering.\n"); 5167 continue; 5168 } 5169 5170 nic = (struct eth_device *) malloc(sizeof (*nic)); 5171 hw = (struct e1000_hw *) malloc(sizeof (*hw)); 5172 hw->pdev = devno; 5173 nic->priv = hw; 5174 5175 sprintf(nic->name, "e1000#%d", card_number); 5176 5177 /* Are these variables needed? */ 5178 hw->fc = e1000_fc_default; 5179 hw->original_fc = e1000_fc_default; 5180 hw->autoneg_failed = 0; 5181 hw->autoneg = 1; 5182 hw->get_link_status = TRUE; 5183 hw->hw_addr = 5184 pci_map_bar(devno, PCI_BASE_ADDRESS_0, PCI_REGION_MEM); 5185 hw->mac_type = e1000_undefined; 5186 5187 /* MAC and Phy settings */ 5188 if (e1000_sw_init(nic, card_number) < 0) { 5189 free(hw); 5190 free(nic); 5191 return 0; 5192 } 5193 if (e1000_check_phy_reset_block(hw)) 5194 printf("phy reset block error \n"); 5195 e1000_reset_hw(hw); 5196 #if !(defined(CONFIG_AP1000) || defined(CONFIG_MVBC_1G)) 5197 if (e1000_init_eeprom_params(hw)) { 5198 printf("The EEPROM Checksum Is Not Valid\n"); 5199 free(hw); 5200 free(nic); 5201 return 0; 5202 } 5203 if (e1000_validate_eeprom_checksum(nic) < 0) { 5204 printf("The EEPROM Checksum Is Not Valid\n"); 5205 free(hw); 5206 free(nic); 5207 return 0; 5208 } 5209 #endif 5210 e1000_read_mac_addr(nic); 5211 5212 /* get the bus type information */ 5213 e1000_get_bus_type(hw); 5214 5215 printf("e1000: %02x:%02x:%02x:%02x:%02x:%02x\n", 5216 nic->enetaddr[0], nic->enetaddr[1], nic->enetaddr[2], 5217 nic->enetaddr[3], nic->enetaddr[4], nic->enetaddr[5]); 5218 5219 nic->init = e1000_init; 5220 nic->recv = e1000_poll; 5221 nic->send = e1000_transmit; 5222 nic->halt = e1000_disable; 5223 5224 eth_register(nic); 5225 5226 card_number++; 5227 } 5228 return card_number; 5229 } 5230