1 /************************************************************************** 2 Intel Pro 1000 for ppcboot/das-u-boot 3 Drivers are port from Intel's Linux driver e1000-4.3.15 4 and from Etherboot pro 1000 driver by mrakes at vivato dot net 5 tested on both gig copper and gig fiber boards 6 ***************************************************************************/ 7 /******************************************************************************* 8 9 10 Copyright(c) 1999 - 2002 Intel Corporation. All rights reserved. 11 12 This program is free software; you can redistribute it and/or modify it 13 under the terms of the GNU General Public License as published by the Free 14 Software Foundation; either version 2 of the License, or (at your option) 15 any later version. 16 17 This program is distributed in the hope that it will be useful, but WITHOUT 18 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 19 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 20 more details. 21 22 You should have received a copy of the GNU General Public License along with 23 this program; if not, write to the Free Software Foundation, Inc., 59 24 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 25 26 The full GNU General Public License is included in this distribution in the 27 file called LICENSE. 28 29 Contact Information: 30 Linux NICS <linux.nics@intel.com> 31 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 32 33 *******************************************************************************/ 34 /* 35 * Copyright (C) Archway Digital Solutions. 36 * 37 * written by Chrsitopher Li <cli at arcyway dot com> or <chrisl at gnuchina dot org> 38 * 2/9/2002 39 * 40 * Copyright (C) Linux Networx. 41 * Massive upgrade to work with the new intel gigabit NICs. 42 * <ebiederman at lnxi dot com> 43 */ 44 45 #include "e1000.h" 46 47 #if defined(CONFIG_CMD_NET) \ 48 && defined(CONFIG_NET_MULTI) && defined(CONFIG_E1000) 49 50 #define TOUT_LOOP 100000 51 52 #undef virt_to_bus 53 #define virt_to_bus(x) ((unsigned long)x) 54 #define bus_to_phys(devno, a) pci_mem_to_phys(devno, a) 55 #define mdelay(n) udelay((n)*1000) 56 57 #define E1000_DEFAULT_PBA 0x00000030 58 59 /* NIC specific static variables go here */ 60 61 static char tx_pool[128 + 16]; 62 static char rx_pool[128 + 16]; 63 static char packet[2096]; 64 65 static struct e1000_tx_desc *tx_base; 66 static struct e1000_rx_desc *rx_base; 67 68 static int tx_tail; 69 static int rx_tail, rx_last; 70 71 static struct pci_device_id supported[] = { 72 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82542}, 73 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82543GC_FIBER}, 74 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82543GC_COPPER}, 75 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544EI_COPPER}, 76 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544EI_FIBER}, 77 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544GC_COPPER}, 78 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544GC_LOM}, 79 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82540EM}, 80 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545EM_COPPER}, 81 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_COPPER}, 82 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545EM_FIBER}, 83 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_FIBER}, 84 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82540EM_LOM}, 85 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82541ER}, 86 }; 87 88 /* Function forward declarations */ 89 static int e1000_setup_link(struct eth_device *nic); 90 static int e1000_setup_fiber_link(struct eth_device *nic); 91 static int e1000_setup_copper_link(struct eth_device *nic); 92 static int e1000_phy_setup_autoneg(struct e1000_hw *hw); 93 static void e1000_config_collision_dist(struct e1000_hw *hw); 94 static int e1000_config_mac_to_phy(struct e1000_hw *hw); 95 static int e1000_config_fc_after_link_up(struct e1000_hw *hw); 96 static int e1000_check_for_link(struct eth_device *nic); 97 static int e1000_wait_autoneg(struct e1000_hw *hw); 98 static void e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t * speed, 99 uint16_t * duplex); 100 static int e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, 101 uint16_t * phy_data); 102 static int e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, 103 uint16_t phy_data); 104 static void e1000_phy_hw_reset(struct e1000_hw *hw); 105 static int e1000_phy_reset(struct e1000_hw *hw); 106 static int e1000_detect_gig_phy(struct e1000_hw *hw); 107 108 #define E1000_WRITE_REG(a, reg, value) (writel((value), ((a)->hw_addr + E1000_##reg))) 109 #define E1000_READ_REG(a, reg) (readl((a)->hw_addr + E1000_##reg)) 110 #define E1000_WRITE_REG_ARRAY(a, reg, offset, value) (\ 111 writel((value), ((a)->hw_addr + E1000_##reg + ((offset) << 2)))) 112 #define E1000_READ_REG_ARRAY(a, reg, offset) ( \ 113 readl((a)->hw_addr + E1000_##reg + ((offset) << 2))) 114 #define E1000_WRITE_FLUSH(a) {uint32_t x; x = E1000_READ_REG(a, STATUS);} 115 116 #ifndef CONFIG_AP1000 /* remove for warnings */ 117 /****************************************************************************** 118 * Raises the EEPROM's clock input. 119 * 120 * hw - Struct containing variables accessed by shared code 121 * eecd - EECD's current value 122 *****************************************************************************/ 123 static void 124 e1000_raise_ee_clk(struct e1000_hw *hw, uint32_t * eecd) 125 { 126 /* Raise the clock input to the EEPROM (by setting the SK bit), and then 127 * wait 50 microseconds. 128 */ 129 *eecd = *eecd | E1000_EECD_SK; 130 E1000_WRITE_REG(hw, EECD, *eecd); 131 E1000_WRITE_FLUSH(hw); 132 udelay(50); 133 } 134 135 /****************************************************************************** 136 * Lowers the EEPROM's clock input. 137 * 138 * hw - Struct containing variables accessed by shared code 139 * eecd - EECD's current value 140 *****************************************************************************/ 141 static void 142 e1000_lower_ee_clk(struct e1000_hw *hw, uint32_t * eecd) 143 { 144 /* Lower the clock input to the EEPROM (by clearing the SK bit), and then 145 * wait 50 microseconds. 146 */ 147 *eecd = *eecd & ~E1000_EECD_SK; 148 E1000_WRITE_REG(hw, EECD, *eecd); 149 E1000_WRITE_FLUSH(hw); 150 udelay(50); 151 } 152 153 /****************************************************************************** 154 * Shift data bits out to the EEPROM. 155 * 156 * hw - Struct containing variables accessed by shared code 157 * data - data to send to the EEPROM 158 * count - number of bits to shift out 159 *****************************************************************************/ 160 static void 161 e1000_shift_out_ee_bits(struct e1000_hw *hw, uint16_t data, uint16_t count) 162 { 163 uint32_t eecd; 164 uint32_t mask; 165 166 /* We need to shift "count" bits out to the EEPROM. So, value in the 167 * "data" parameter will be shifted out to the EEPROM one bit at a time. 168 * In order to do this, "data" must be broken down into bits. 169 */ 170 mask = 0x01 << (count - 1); 171 eecd = E1000_READ_REG(hw, EECD); 172 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI); 173 do { 174 /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1", 175 * and then raising and then lowering the clock (the SK bit controls 176 * the clock input to the EEPROM). A "0" is shifted out to the EEPROM 177 * by setting "DI" to "0" and then raising and then lowering the clock. 178 */ 179 eecd &= ~E1000_EECD_DI; 180 181 if (data & mask) 182 eecd |= E1000_EECD_DI; 183 184 E1000_WRITE_REG(hw, EECD, eecd); 185 E1000_WRITE_FLUSH(hw); 186 187 udelay(50); 188 189 e1000_raise_ee_clk(hw, &eecd); 190 e1000_lower_ee_clk(hw, &eecd); 191 192 mask = mask >> 1; 193 194 } while (mask); 195 196 /* We leave the "DI" bit set to "0" when we leave this routine. */ 197 eecd &= ~E1000_EECD_DI; 198 E1000_WRITE_REG(hw, EECD, eecd); 199 } 200 201 /****************************************************************************** 202 * Shift data bits in from the EEPROM 203 * 204 * hw - Struct containing variables accessed by shared code 205 *****************************************************************************/ 206 static uint16_t 207 e1000_shift_in_ee_bits(struct e1000_hw *hw) 208 { 209 uint32_t eecd; 210 uint32_t i; 211 uint16_t data; 212 213 /* In order to read a register from the EEPROM, we need to shift 16 bits 214 * in from the EEPROM. Bits are "shifted in" by raising the clock input to 215 * the EEPROM (setting the SK bit), and then reading the value of the "DO" 216 * bit. During this "shifting in" process the "DI" bit should always be 217 * clear.. 218 */ 219 220 eecd = E1000_READ_REG(hw, EECD); 221 222 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI); 223 data = 0; 224 225 for (i = 0; i < 16; i++) { 226 data = data << 1; 227 e1000_raise_ee_clk(hw, &eecd); 228 229 eecd = E1000_READ_REG(hw, EECD); 230 231 eecd &= ~(E1000_EECD_DI); 232 if (eecd & E1000_EECD_DO) 233 data |= 1; 234 235 e1000_lower_ee_clk(hw, &eecd); 236 } 237 238 return data; 239 } 240 241 /****************************************************************************** 242 * Prepares EEPROM for access 243 * 244 * hw - Struct containing variables accessed by shared code 245 * 246 * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This 247 * function should be called before issuing a command to the EEPROM. 248 *****************************************************************************/ 249 static void 250 e1000_setup_eeprom(struct e1000_hw *hw) 251 { 252 uint32_t eecd; 253 254 eecd = E1000_READ_REG(hw, EECD); 255 256 /* Clear SK and DI */ 257 eecd &= ~(E1000_EECD_SK | E1000_EECD_DI); 258 E1000_WRITE_REG(hw, EECD, eecd); 259 260 /* Set CS */ 261 eecd |= E1000_EECD_CS; 262 E1000_WRITE_REG(hw, EECD, eecd); 263 } 264 265 /****************************************************************************** 266 * Returns EEPROM to a "standby" state 267 * 268 * hw - Struct containing variables accessed by shared code 269 *****************************************************************************/ 270 static void 271 e1000_standby_eeprom(struct e1000_hw *hw) 272 { 273 uint32_t eecd; 274 275 eecd = E1000_READ_REG(hw, EECD); 276 277 /* Deselct EEPROM */ 278 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); 279 E1000_WRITE_REG(hw, EECD, eecd); 280 E1000_WRITE_FLUSH(hw); 281 udelay(50); 282 283 /* Clock high */ 284 eecd |= E1000_EECD_SK; 285 E1000_WRITE_REG(hw, EECD, eecd); 286 E1000_WRITE_FLUSH(hw); 287 udelay(50); 288 289 /* Select EEPROM */ 290 eecd |= E1000_EECD_CS; 291 E1000_WRITE_REG(hw, EECD, eecd); 292 E1000_WRITE_FLUSH(hw); 293 udelay(50); 294 295 /* Clock low */ 296 eecd &= ~E1000_EECD_SK; 297 E1000_WRITE_REG(hw, EECD, eecd); 298 E1000_WRITE_FLUSH(hw); 299 udelay(50); 300 } 301 302 /****************************************************************************** 303 * Reads a 16 bit word from the EEPROM. 304 * 305 * hw - Struct containing variables accessed by shared code 306 * offset - offset of word in the EEPROM to read 307 * data - word read from the EEPROM 308 *****************************************************************************/ 309 static int 310 e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset, uint16_t * data) 311 { 312 uint32_t eecd; 313 uint32_t i = 0; 314 int large_eeprom = FALSE; 315 316 /* Request EEPROM Access */ 317 if (hw->mac_type > e1000_82544) { 318 eecd = E1000_READ_REG(hw, EECD); 319 if (eecd & E1000_EECD_SIZE) 320 large_eeprom = TRUE; 321 eecd |= E1000_EECD_REQ; 322 E1000_WRITE_REG(hw, EECD, eecd); 323 eecd = E1000_READ_REG(hw, EECD); 324 while ((!(eecd & E1000_EECD_GNT)) && (i < 100)) { 325 i++; 326 udelay(10); 327 eecd = E1000_READ_REG(hw, EECD); 328 } 329 if (!(eecd & E1000_EECD_GNT)) { 330 eecd &= ~E1000_EECD_REQ; 331 E1000_WRITE_REG(hw, EECD, eecd); 332 DEBUGOUT("Could not acquire EEPROM grant\n"); 333 return -E1000_ERR_EEPROM; 334 } 335 } 336 337 /* Prepare the EEPROM for reading */ 338 e1000_setup_eeprom(hw); 339 340 /* Send the READ command (opcode + addr) */ 341 e1000_shift_out_ee_bits(hw, EEPROM_READ_OPCODE, 3); 342 e1000_shift_out_ee_bits(hw, offset, (large_eeprom) ? 8 : 6); 343 344 /* Read the data */ 345 *data = e1000_shift_in_ee_bits(hw); 346 347 /* End this read operation */ 348 e1000_standby_eeprom(hw); 349 350 /* Stop requesting EEPROM access */ 351 if (hw->mac_type > e1000_82544) { 352 eecd = E1000_READ_REG(hw, EECD); 353 eecd &= ~E1000_EECD_REQ; 354 E1000_WRITE_REG(hw, EECD, eecd); 355 } 356 357 return 0; 358 } 359 360 #if 0 361 static void 362 e1000_eeprom_cleanup(struct e1000_hw *hw) 363 { 364 uint32_t eecd; 365 366 eecd = E1000_READ_REG(hw, EECD); 367 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI); 368 E1000_WRITE_REG(hw, EECD, eecd); 369 e1000_raise_ee_clk(hw, &eecd); 370 e1000_lower_ee_clk(hw, &eecd); 371 } 372 373 static uint16_t 374 e1000_wait_eeprom_done(struct e1000_hw *hw) 375 { 376 uint32_t eecd; 377 uint32_t i; 378 379 e1000_standby_eeprom(hw); 380 for (i = 0; i < 200; i++) { 381 eecd = E1000_READ_REG(hw, EECD); 382 if (eecd & E1000_EECD_DO) 383 return (TRUE); 384 udelay(5); 385 } 386 return (FALSE); 387 } 388 389 static int 390 e1000_write_eeprom(struct e1000_hw *hw, uint16_t Reg, uint16_t Data) 391 { 392 uint32_t eecd; 393 int large_eeprom = FALSE; 394 int i = 0; 395 396 /* Request EEPROM Access */ 397 if (hw->mac_type > e1000_82544) { 398 eecd = E1000_READ_REG(hw, EECD); 399 if (eecd & E1000_EECD_SIZE) 400 large_eeprom = TRUE; 401 eecd |= E1000_EECD_REQ; 402 E1000_WRITE_REG(hw, EECD, eecd); 403 eecd = E1000_READ_REG(hw, EECD); 404 while ((!(eecd & E1000_EECD_GNT)) && (i < 100)) { 405 i++; 406 udelay(5); 407 eecd = E1000_READ_REG(hw, EECD); 408 } 409 if (!(eecd & E1000_EECD_GNT)) { 410 eecd &= ~E1000_EECD_REQ; 411 E1000_WRITE_REG(hw, EECD, eecd); 412 DEBUGOUT("Could not acquire EEPROM grant\n"); 413 return FALSE; 414 } 415 } 416 e1000_setup_eeprom(hw); 417 e1000_shift_out_ee_bits(hw, EEPROM_EWEN_OPCODE, 5); 418 e1000_shift_out_ee_bits(hw, Reg, (large_eeprom) ? 6 : 4); 419 e1000_standby_eeprom(hw); 420 e1000_shift_out_ee_bits(hw, EEPROM_WRITE_OPCODE, 3); 421 e1000_shift_out_ee_bits(hw, Reg, (large_eeprom) ? 8 : 6); 422 e1000_shift_out_ee_bits(hw, Data, 16); 423 if (!e1000_wait_eeprom_done(hw)) { 424 return FALSE; 425 } 426 e1000_shift_out_ee_bits(hw, EEPROM_EWDS_OPCODE, 5); 427 e1000_shift_out_ee_bits(hw, Reg, (large_eeprom) ? 6 : 4); 428 e1000_eeprom_cleanup(hw); 429 430 /* Stop requesting EEPROM access */ 431 if (hw->mac_type > e1000_82544) { 432 eecd = E1000_READ_REG(hw, EECD); 433 eecd &= ~E1000_EECD_REQ; 434 E1000_WRITE_REG(hw, EECD, eecd); 435 } 436 i = 0; 437 eecd = E1000_READ_REG(hw, EECD); 438 while (((eecd & E1000_EECD_GNT)) && (i < 500)) { 439 i++; 440 udelay(10); 441 eecd = E1000_READ_REG(hw, EECD); 442 } 443 if ((eecd & E1000_EECD_GNT)) { 444 DEBUGOUT("Could not release EEPROM grant\n"); 445 } 446 return TRUE; 447 } 448 #endif 449 450 /****************************************************************************** 451 * Verifies that the EEPROM has a valid checksum 452 * 453 * hw - Struct containing variables accessed by shared code 454 * 455 * Reads the first 64 16 bit words of the EEPROM and sums the values read. 456 * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is 457 * valid. 458 *****************************************************************************/ 459 static int 460 e1000_validate_eeprom_checksum(struct eth_device *nic) 461 { 462 struct e1000_hw *hw = nic->priv; 463 uint16_t checksum = 0; 464 uint16_t i, eeprom_data; 465 466 DEBUGFUNC(); 467 468 for (i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) { 469 if (e1000_read_eeprom(hw, i, &eeprom_data) < 0) { 470 DEBUGOUT("EEPROM Read Error\n"); 471 return -E1000_ERR_EEPROM; 472 } 473 checksum += eeprom_data; 474 } 475 476 if (checksum == (uint16_t) EEPROM_SUM) { 477 return 0; 478 } else { 479 DEBUGOUT("EEPROM Checksum Invalid\n"); 480 return -E1000_ERR_EEPROM; 481 } 482 } 483 #endif /* #ifndef CONFIG_AP1000 */ 484 485 /****************************************************************************** 486 * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the 487 * second function of dual function devices 488 * 489 * nic - Struct containing variables accessed by shared code 490 *****************************************************************************/ 491 static int 492 e1000_read_mac_addr(struct eth_device *nic) 493 { 494 #ifndef CONFIG_AP1000 495 struct e1000_hw *hw = nic->priv; 496 uint16_t offset; 497 uint16_t eeprom_data; 498 int i; 499 500 DEBUGFUNC(); 501 502 for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) { 503 offset = i >> 1; 504 if (e1000_read_eeprom(hw, offset, &eeprom_data) < 0) { 505 DEBUGOUT("EEPROM Read Error\n"); 506 return -E1000_ERR_EEPROM; 507 } 508 nic->enetaddr[i] = eeprom_data & 0xff; 509 nic->enetaddr[i + 1] = (eeprom_data >> 8) & 0xff; 510 } 511 if ((hw->mac_type == e1000_82546) && 512 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) { 513 /* Invert the last bit if this is the second device */ 514 nic->enetaddr[5] += 1; 515 } 516 #ifdef CONFIG_E1000_FALLBACK_MAC 517 if ( *(u32*)(nic->enetaddr) == 0 || *(u32*)(nic->enetaddr) == ~0 ) 518 for ( i=0; i < NODE_ADDRESS_SIZE; i++ ) 519 nic->enetaddr[i] = (CONFIG_E1000_FALLBACK_MAC >> (8*(5-i))) & 0xff; 520 #endif 521 #else 522 /* 523 * The AP1000's e1000 has no eeprom; the MAC address is stored in the 524 * environment variables. Currently this does not support the addition 525 * of a PMC e1000 card, which is certainly a possibility, so this should 526 * be updated to properly use the env variable only for the onboard e1000 527 */ 528 529 int ii; 530 char *s, *e; 531 532 DEBUGFUNC(); 533 534 s = getenv ("ethaddr"); 535 if (s == NULL){ 536 return -E1000_ERR_EEPROM; 537 } 538 else{ 539 for(ii = 0; ii < 6; ii++) { 540 nic->enetaddr[ii] = s ? simple_strtoul (s, &e, 16) : 0; 541 if (s){ 542 s = (*e) ? e + 1 : e; 543 } 544 } 545 } 546 #endif 547 return 0; 548 } 549 550 /****************************************************************************** 551 * Initializes receive address filters. 552 * 553 * hw - Struct containing variables accessed by shared code 554 * 555 * Places the MAC address in receive address register 0 and clears the rest 556 * of the receive addresss registers. Clears the multicast table. Assumes 557 * the receiver is in reset when the routine is called. 558 *****************************************************************************/ 559 static void 560 e1000_init_rx_addrs(struct eth_device *nic) 561 { 562 struct e1000_hw *hw = nic->priv; 563 uint32_t i; 564 uint32_t addr_low; 565 uint32_t addr_high; 566 567 DEBUGFUNC(); 568 569 /* Setup the receive address. */ 570 DEBUGOUT("Programming MAC Address into RAR[0]\n"); 571 addr_low = (nic->enetaddr[0] | 572 (nic->enetaddr[1] << 8) | 573 (nic->enetaddr[2] << 16) | (nic->enetaddr[3] << 24)); 574 575 addr_high = (nic->enetaddr[4] | (nic->enetaddr[5] << 8) | E1000_RAH_AV); 576 577 E1000_WRITE_REG_ARRAY(hw, RA, 0, addr_low); 578 E1000_WRITE_REG_ARRAY(hw, RA, 1, addr_high); 579 580 /* Zero out the other 15 receive addresses. */ 581 DEBUGOUT("Clearing RAR[1-15]\n"); 582 for (i = 1; i < E1000_RAR_ENTRIES; i++) { 583 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0); 584 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0); 585 } 586 } 587 588 /****************************************************************************** 589 * Clears the VLAN filer table 590 * 591 * hw - Struct containing variables accessed by shared code 592 *****************************************************************************/ 593 static void 594 e1000_clear_vfta(struct e1000_hw *hw) 595 { 596 uint32_t offset; 597 598 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) 599 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, 0); 600 } 601 602 /****************************************************************************** 603 * Set the mac type member in the hw struct. 604 * 605 * hw - Struct containing variables accessed by shared code 606 *****************************************************************************/ 607 static int 608 e1000_set_mac_type(struct e1000_hw *hw) 609 { 610 DEBUGFUNC(); 611 612 switch (hw->device_id) { 613 case E1000_DEV_ID_82542: 614 switch (hw->revision_id) { 615 case E1000_82542_2_0_REV_ID: 616 hw->mac_type = e1000_82542_rev2_0; 617 break; 618 case E1000_82542_2_1_REV_ID: 619 hw->mac_type = e1000_82542_rev2_1; 620 break; 621 default: 622 /* Invalid 82542 revision ID */ 623 return -E1000_ERR_MAC_TYPE; 624 } 625 break; 626 case E1000_DEV_ID_82543GC_FIBER: 627 case E1000_DEV_ID_82543GC_COPPER: 628 hw->mac_type = e1000_82543; 629 break; 630 case E1000_DEV_ID_82544EI_COPPER: 631 case E1000_DEV_ID_82544EI_FIBER: 632 case E1000_DEV_ID_82544GC_COPPER: 633 case E1000_DEV_ID_82544GC_LOM: 634 hw->mac_type = e1000_82544; 635 break; 636 case E1000_DEV_ID_82540EM: 637 case E1000_DEV_ID_82540EM_LOM: 638 hw->mac_type = e1000_82540; 639 break; 640 case E1000_DEV_ID_82545EM_COPPER: 641 case E1000_DEV_ID_82545EM_FIBER: 642 hw->mac_type = e1000_82545; 643 break; 644 case E1000_DEV_ID_82546EB_COPPER: 645 case E1000_DEV_ID_82546EB_FIBER: 646 hw->mac_type = e1000_82546; 647 break; 648 case E1000_DEV_ID_82541ER: 649 hw->mac_type = e1000_82541_rev_2; 650 break; 651 default: 652 /* Should never have loaded on this device */ 653 return -E1000_ERR_MAC_TYPE; 654 } 655 return E1000_SUCCESS; 656 } 657 658 /****************************************************************************** 659 * Reset the transmit and receive units; mask and clear all interrupts. 660 * 661 * hw - Struct containing variables accessed by shared code 662 *****************************************************************************/ 663 void 664 e1000_reset_hw(struct e1000_hw *hw) 665 { 666 uint32_t ctrl; 667 uint32_t ctrl_ext; 668 uint32_t icr; 669 uint32_t manc; 670 671 DEBUGFUNC(); 672 673 /* For 82542 (rev 2.0), disable MWI before issuing a device reset */ 674 if (hw->mac_type == e1000_82542_rev2_0) { 675 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n"); 676 pci_write_config_word(hw->pdev, PCI_COMMAND, 677 hw-> 678 pci_cmd_word & ~PCI_COMMAND_INVALIDATE); 679 } 680 681 /* Clear interrupt mask to stop board from generating interrupts */ 682 DEBUGOUT("Masking off all interrupts\n"); 683 E1000_WRITE_REG(hw, IMC, 0xffffffff); 684 685 /* Disable the Transmit and Receive units. Then delay to allow 686 * any pending transactions to complete before we hit the MAC with 687 * the global reset. 688 */ 689 E1000_WRITE_REG(hw, RCTL, 0); 690 E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP); 691 E1000_WRITE_FLUSH(hw); 692 693 /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */ 694 hw->tbi_compatibility_on = FALSE; 695 696 /* Delay to allow any outstanding PCI transactions to complete before 697 * resetting the device 698 */ 699 mdelay(10); 700 701 /* Issue a global reset to the MAC. This will reset the chip's 702 * transmit, receive, DMA, and link units. It will not effect 703 * the current PCI configuration. The global reset bit is self- 704 * clearing, and should clear within a microsecond. 705 */ 706 DEBUGOUT("Issuing a global reset to MAC\n"); 707 ctrl = E1000_READ_REG(hw, CTRL); 708 709 #if 0 710 if (hw->mac_type > e1000_82543) 711 E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST)); 712 else 713 #endif 714 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST)); 715 716 /* Force a reload from the EEPROM if necessary */ 717 if (hw->mac_type < e1000_82540) { 718 /* Wait for reset to complete */ 719 udelay(10); 720 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 721 ctrl_ext |= E1000_CTRL_EXT_EE_RST; 722 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 723 E1000_WRITE_FLUSH(hw); 724 /* Wait for EEPROM reload */ 725 mdelay(2); 726 } else { 727 /* Wait for EEPROM reload (it happens automatically) */ 728 mdelay(4); 729 /* Dissable HW ARPs on ASF enabled adapters */ 730 manc = E1000_READ_REG(hw, MANC); 731 manc &= ~(E1000_MANC_ARP_EN); 732 E1000_WRITE_REG(hw, MANC, manc); 733 } 734 735 /* Clear interrupt mask to stop board from generating interrupts */ 736 DEBUGOUT("Masking off all interrupts\n"); 737 E1000_WRITE_REG(hw, IMC, 0xffffffff); 738 739 /* Clear any pending interrupt events. */ 740 icr = E1000_READ_REG(hw, ICR); 741 742 /* If MWI was previously enabled, reenable it. */ 743 if (hw->mac_type == e1000_82542_rev2_0) { 744 pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word); 745 } 746 } 747 748 /****************************************************************************** 749 * Performs basic configuration of the adapter. 750 * 751 * hw - Struct containing variables accessed by shared code 752 * 753 * Assumes that the controller has previously been reset and is in a 754 * post-reset uninitialized state. Initializes the receive address registers, 755 * multicast table, and VLAN filter table. Calls routines to setup link 756 * configuration and flow control settings. Clears all on-chip counters. Leaves 757 * the transmit and receive units disabled and uninitialized. 758 *****************************************************************************/ 759 static int 760 e1000_init_hw(struct eth_device *nic) 761 { 762 struct e1000_hw *hw = nic->priv; 763 uint32_t ctrl, status; 764 uint32_t i; 765 int32_t ret_val; 766 uint16_t pcix_cmd_word; 767 uint16_t pcix_stat_hi_word; 768 uint16_t cmd_mmrbc; 769 uint16_t stat_mmrbc; 770 e1000_bus_type bus_type = e1000_bus_type_unknown; 771 772 DEBUGFUNC(); 773 #if 0 774 /* Initialize Identification LED */ 775 ret_val = e1000_id_led_init(hw); 776 if (ret_val < 0) { 777 DEBUGOUT("Error Initializing Identification LED\n"); 778 return ret_val; 779 } 780 #endif 781 /* Set the Media Type and exit with error if it is not valid. */ 782 if (hw->mac_type != e1000_82543) { 783 /* tbi_compatibility is only valid on 82543 */ 784 hw->tbi_compatibility_en = FALSE; 785 } 786 787 if (hw->mac_type >= e1000_82543) { 788 status = E1000_READ_REG(hw, STATUS); 789 if (status & E1000_STATUS_TBIMODE) { 790 hw->media_type = e1000_media_type_fiber; 791 /* tbi_compatibility not valid on fiber */ 792 hw->tbi_compatibility_en = FALSE; 793 } else { 794 hw->media_type = e1000_media_type_copper; 795 } 796 } else { 797 /* This is an 82542 (fiber only) */ 798 hw->media_type = e1000_media_type_fiber; 799 } 800 801 /* Disabling VLAN filtering. */ 802 DEBUGOUT("Initializing the IEEE VLAN\n"); 803 E1000_WRITE_REG(hw, VET, 0); 804 805 e1000_clear_vfta(hw); 806 807 /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */ 808 if (hw->mac_type == e1000_82542_rev2_0) { 809 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n"); 810 pci_write_config_word(hw->pdev, PCI_COMMAND, 811 hw-> 812 pci_cmd_word & ~PCI_COMMAND_INVALIDATE); 813 E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST); 814 E1000_WRITE_FLUSH(hw); 815 mdelay(5); 816 } 817 818 /* Setup the receive address. This involves initializing all of the Receive 819 * Address Registers (RARs 0 - 15). 820 */ 821 e1000_init_rx_addrs(nic); 822 823 /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */ 824 if (hw->mac_type == e1000_82542_rev2_0) { 825 E1000_WRITE_REG(hw, RCTL, 0); 826 E1000_WRITE_FLUSH(hw); 827 mdelay(1); 828 pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word); 829 } 830 831 /* Zero out the Multicast HASH table */ 832 DEBUGOUT("Zeroing the MTA\n"); 833 for (i = 0; i < E1000_MC_TBL_SIZE; i++) 834 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0); 835 836 #if 0 837 /* Set the PCI priority bit correctly in the CTRL register. This 838 * determines if the adapter gives priority to receives, or if it 839 * gives equal priority to transmits and receives. 840 */ 841 if (hw->dma_fairness) { 842 ctrl = E1000_READ_REG(hw, CTRL); 843 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR); 844 } 845 #endif 846 if (hw->mac_type >= e1000_82543) { 847 status = E1000_READ_REG(hw, STATUS); 848 bus_type = (status & E1000_STATUS_PCIX_MODE) ? 849 e1000_bus_type_pcix : e1000_bus_type_pci; 850 } 851 /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */ 852 if (bus_type == e1000_bus_type_pcix) { 853 pci_read_config_word(hw->pdev, PCIX_COMMAND_REGISTER, 854 &pcix_cmd_word); 855 pci_read_config_word(hw->pdev, PCIX_STATUS_REGISTER_HI, 856 &pcix_stat_hi_word); 857 cmd_mmrbc = 858 (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) >> 859 PCIX_COMMAND_MMRBC_SHIFT; 860 stat_mmrbc = 861 (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >> 862 PCIX_STATUS_HI_MMRBC_SHIFT; 863 if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K) 864 stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K; 865 if (cmd_mmrbc > stat_mmrbc) { 866 pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK; 867 pcix_cmd_word |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT; 868 pci_write_config_word(hw->pdev, PCIX_COMMAND_REGISTER, 869 pcix_cmd_word); 870 } 871 } 872 873 /* Call a subroutine to configure the link and setup flow control. */ 874 ret_val = e1000_setup_link(nic); 875 876 /* Set the transmit descriptor write-back policy */ 877 if (hw->mac_type > e1000_82544) { 878 ctrl = E1000_READ_REG(hw, TXDCTL); 879 ctrl = 880 (ctrl & ~E1000_TXDCTL_WTHRESH) | 881 E1000_TXDCTL_FULL_TX_DESC_WB; 882 E1000_WRITE_REG(hw, TXDCTL, ctrl); 883 } 884 #if 0 885 /* Clear all of the statistics registers (clear on read). It is 886 * important that we do this after we have tried to establish link 887 * because the symbol error count will increment wildly if there 888 * is no link. 889 */ 890 e1000_clear_hw_cntrs(hw); 891 #endif 892 893 return ret_val; 894 } 895 896 /****************************************************************************** 897 * Configures flow control and link settings. 898 * 899 * hw - Struct containing variables accessed by shared code 900 * 901 * Determines which flow control settings to use. Calls the apropriate media- 902 * specific link configuration function. Configures the flow control settings. 903 * Assuming the adapter has a valid link partner, a valid link should be 904 * established. Assumes the hardware has previously been reset and the 905 * transmitter and receiver are not enabled. 906 *****************************************************************************/ 907 static int 908 e1000_setup_link(struct eth_device *nic) 909 { 910 struct e1000_hw *hw = nic->priv; 911 uint32_t ctrl_ext; 912 int32_t ret_val; 913 uint16_t eeprom_data; 914 915 DEBUGFUNC(); 916 917 #ifndef CONFIG_AP1000 918 /* Read and store word 0x0F of the EEPROM. This word contains bits 919 * that determine the hardware's default PAUSE (flow control) mode, 920 * a bit that determines whether the HW defaults to enabling or 921 * disabling auto-negotiation, and the direction of the 922 * SW defined pins. If there is no SW over-ride of the flow 923 * control setting, then the variable hw->fc will 924 * be initialized based on a value in the EEPROM. 925 */ 926 if (e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, &eeprom_data) < 0) { 927 DEBUGOUT("EEPROM Read Error\n"); 928 return -E1000_ERR_EEPROM; 929 } 930 #else 931 /* we have to hardcode the proper value for our hardware. */ 932 /* this value is for the 82540EM pci card used for prototyping, and it works. */ 933 eeprom_data = 0xb220; 934 #endif 935 936 if (hw->fc == e1000_fc_default) { 937 if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0) 938 hw->fc = e1000_fc_none; 939 else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 940 EEPROM_WORD0F_ASM_DIR) 941 hw->fc = e1000_fc_tx_pause; 942 else 943 hw->fc = e1000_fc_full; 944 } 945 946 /* We want to save off the original Flow Control configuration just 947 * in case we get disconnected and then reconnected into a different 948 * hub or switch with different Flow Control capabilities. 949 */ 950 if (hw->mac_type == e1000_82542_rev2_0) 951 hw->fc &= (~e1000_fc_tx_pause); 952 953 if ((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1)) 954 hw->fc &= (~e1000_fc_rx_pause); 955 956 hw->original_fc = hw->fc; 957 958 DEBUGOUT("After fix-ups FlowControl is now = %x\n", hw->fc); 959 960 /* Take the 4 bits from EEPROM word 0x0F that determine the initial 961 * polarity value for the SW controlled pins, and setup the 962 * Extended Device Control reg with that info. 963 * This is needed because one of the SW controlled pins is used for 964 * signal detection. So this should be done before e1000_setup_pcs_link() 965 * or e1000_phy_setup() is called. 966 */ 967 if (hw->mac_type == e1000_82543) { 968 ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) << 969 SWDPIO__EXT_SHIFT); 970 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 971 } 972 973 /* Call the necessary subroutine to configure the link. */ 974 ret_val = (hw->media_type == e1000_media_type_fiber) ? 975 e1000_setup_fiber_link(nic) : e1000_setup_copper_link(nic); 976 if (ret_val < 0) { 977 return ret_val; 978 } 979 980 /* Initialize the flow control address, type, and PAUSE timer 981 * registers to their default values. This is done even if flow 982 * control is disabled, because it does not hurt anything to 983 * initialize these registers. 984 */ 985 DEBUGOUT 986 ("Initializing the Flow Control address, type and timer regs\n"); 987 988 E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW); 989 E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH); 990 E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE); 991 E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time); 992 993 /* Set the flow control receive threshold registers. Normally, 994 * these registers will be set to a default threshold that may be 995 * adjusted later by the driver's runtime code. However, if the 996 * ability to transmit pause frames in not enabled, then these 997 * registers will be set to 0. 998 */ 999 if (!(hw->fc & e1000_fc_tx_pause)) { 1000 E1000_WRITE_REG(hw, FCRTL, 0); 1001 E1000_WRITE_REG(hw, FCRTH, 0); 1002 } else { 1003 /* We need to set up the Receive Threshold high and low water marks 1004 * as well as (optionally) enabling the transmission of XON frames. 1005 */ 1006 if (hw->fc_send_xon) { 1007 E1000_WRITE_REG(hw, FCRTL, 1008 (hw->fc_low_water | E1000_FCRTL_XONE)); 1009 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water); 1010 } else { 1011 E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water); 1012 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water); 1013 } 1014 } 1015 return ret_val; 1016 } 1017 1018 /****************************************************************************** 1019 * Sets up link for a fiber based adapter 1020 * 1021 * hw - Struct containing variables accessed by shared code 1022 * 1023 * Manipulates Physical Coding Sublayer functions in order to configure 1024 * link. Assumes the hardware has been previously reset and the transmitter 1025 * and receiver are not enabled. 1026 *****************************************************************************/ 1027 static int 1028 e1000_setup_fiber_link(struct eth_device *nic) 1029 { 1030 struct e1000_hw *hw = nic->priv; 1031 uint32_t ctrl; 1032 uint32_t status; 1033 uint32_t txcw = 0; 1034 uint32_t i; 1035 uint32_t signal; 1036 int32_t ret_val; 1037 1038 DEBUGFUNC(); 1039 /* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be 1040 * set when the optics detect a signal. On older adapters, it will be 1041 * cleared when there is a signal 1042 */ 1043 ctrl = E1000_READ_REG(hw, CTRL); 1044 if ((hw->mac_type > e1000_82544) && !(ctrl & E1000_CTRL_ILOS)) 1045 signal = E1000_CTRL_SWDPIN1; 1046 else 1047 signal = 0; 1048 1049 printf("signal for %s is %x (ctrl %08x)!!!!\n", nic->name, signal, 1050 ctrl); 1051 /* Take the link out of reset */ 1052 ctrl &= ~(E1000_CTRL_LRST); 1053 1054 e1000_config_collision_dist(hw); 1055 1056 /* Check for a software override of the flow control settings, and setup 1057 * the device accordingly. If auto-negotiation is enabled, then software 1058 * will have to set the "PAUSE" bits to the correct value in the Tranmsit 1059 * Config Word Register (TXCW) and re-start auto-negotiation. However, if 1060 * auto-negotiation is disabled, then software will have to manually 1061 * configure the two flow control enable bits in the CTRL register. 1062 * 1063 * The possible values of the "fc" parameter are: 1064 * 0: Flow control is completely disabled 1065 * 1: Rx flow control is enabled (we can receive pause frames, but 1066 * not send pause frames). 1067 * 2: Tx flow control is enabled (we can send pause frames but we do 1068 * not support receiving pause frames). 1069 * 3: Both Rx and TX flow control (symmetric) are enabled. 1070 */ 1071 switch (hw->fc) { 1072 case e1000_fc_none: 1073 /* Flow control is completely disabled by a software over-ride. */ 1074 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD); 1075 break; 1076 case e1000_fc_rx_pause: 1077 /* RX Flow control is enabled and TX Flow control is disabled by a 1078 * software over-ride. Since there really isn't a way to advertise 1079 * that we are capable of RX Pause ONLY, we will advertise that we 1080 * support both symmetric and asymmetric RX PAUSE. Later, we will 1081 * disable the adapter's ability to send PAUSE frames. 1082 */ 1083 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); 1084 break; 1085 case e1000_fc_tx_pause: 1086 /* TX Flow control is enabled, and RX Flow control is disabled, by a 1087 * software over-ride. 1088 */ 1089 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR); 1090 break; 1091 case e1000_fc_full: 1092 /* Flow control (both RX and TX) is enabled by a software over-ride. */ 1093 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); 1094 break; 1095 default: 1096 DEBUGOUT("Flow control param set incorrectly\n"); 1097 return -E1000_ERR_CONFIG; 1098 break; 1099 } 1100 1101 /* Since auto-negotiation is enabled, take the link out of reset (the link 1102 * will be in reset, because we previously reset the chip). This will 1103 * restart auto-negotiation. If auto-neogtiation is successful then the 1104 * link-up status bit will be set and the flow control enable bits (RFCE 1105 * and TFCE) will be set according to their negotiated value. 1106 */ 1107 DEBUGOUT("Auto-negotiation enabled (%#x)\n", txcw); 1108 1109 E1000_WRITE_REG(hw, TXCW, txcw); 1110 E1000_WRITE_REG(hw, CTRL, ctrl); 1111 E1000_WRITE_FLUSH(hw); 1112 1113 hw->txcw = txcw; 1114 mdelay(1); 1115 1116 /* If we have a signal (the cable is plugged in) then poll for a "Link-Up" 1117 * indication in the Device Status Register. Time-out if a link isn't 1118 * seen in 500 milliseconds seconds (Auto-negotiation should complete in 1119 * less than 500 milliseconds even if the other end is doing it in SW). 1120 */ 1121 if ((E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) { 1122 DEBUGOUT("Looking for Link\n"); 1123 for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) { 1124 mdelay(10); 1125 status = E1000_READ_REG(hw, STATUS); 1126 if (status & E1000_STATUS_LU) 1127 break; 1128 } 1129 if (i == (LINK_UP_TIMEOUT / 10)) { 1130 /* AutoNeg failed to achieve a link, so we'll call 1131 * e1000_check_for_link. This routine will force the link up if we 1132 * detect a signal. This will allow us to communicate with 1133 * non-autonegotiating link partners. 1134 */ 1135 DEBUGOUT("Never got a valid link from auto-neg!!!\n"); 1136 hw->autoneg_failed = 1; 1137 ret_val = e1000_check_for_link(nic); 1138 if (ret_val < 0) { 1139 DEBUGOUT("Error while checking for link\n"); 1140 return ret_val; 1141 } 1142 hw->autoneg_failed = 0; 1143 } else { 1144 hw->autoneg_failed = 0; 1145 DEBUGOUT("Valid Link Found\n"); 1146 } 1147 } else { 1148 DEBUGOUT("No Signal Detected\n"); 1149 return -E1000_ERR_NOLINK; 1150 } 1151 return 0; 1152 } 1153 1154 /****************************************************************************** 1155 * Detects which PHY is present and the speed and duplex 1156 * 1157 * hw - Struct containing variables accessed by shared code 1158 ******************************************************************************/ 1159 static int 1160 e1000_setup_copper_link(struct eth_device *nic) 1161 { 1162 struct e1000_hw *hw = nic->priv; 1163 uint32_t ctrl; 1164 int32_t ret_val; 1165 uint16_t i; 1166 uint16_t phy_data; 1167 1168 DEBUGFUNC(); 1169 1170 ctrl = E1000_READ_REG(hw, CTRL); 1171 /* With 82543, we need to force speed and duplex on the MAC equal to what 1172 * the PHY speed and duplex configuration is. In addition, we need to 1173 * perform a hardware reset on the PHY to take it out of reset. 1174 */ 1175 if (hw->mac_type > e1000_82543) { 1176 ctrl |= E1000_CTRL_SLU; 1177 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1178 E1000_WRITE_REG(hw, CTRL, ctrl); 1179 } else { 1180 ctrl |= 1181 (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU); 1182 E1000_WRITE_REG(hw, CTRL, ctrl); 1183 e1000_phy_hw_reset(hw); 1184 } 1185 1186 /* Make sure we have a valid PHY */ 1187 ret_val = e1000_detect_gig_phy(hw); 1188 if (ret_val < 0) { 1189 DEBUGOUT("Error, did not detect valid phy.\n"); 1190 return ret_val; 1191 } 1192 DEBUGOUT("Phy ID = %x \n", hw->phy_id); 1193 1194 /* Enable CRS on TX. This must be set for half-duplex operation. */ 1195 if (e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data) < 0) { 1196 DEBUGOUT("PHY Read Error\n"); 1197 return -E1000_ERR_PHY; 1198 } 1199 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; 1200 1201 #if 0 1202 /* Options: 1203 * MDI/MDI-X = 0 (default) 1204 * 0 - Auto for all speeds 1205 * 1 - MDI mode 1206 * 2 - MDI-X mode 1207 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) 1208 */ 1209 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 1210 switch (hw->mdix) { 1211 case 1: 1212 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; 1213 break; 1214 case 2: 1215 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; 1216 break; 1217 case 3: 1218 phy_data |= M88E1000_PSCR_AUTO_X_1000T; 1219 break; 1220 case 0: 1221 default: 1222 phy_data |= M88E1000_PSCR_AUTO_X_MODE; 1223 break; 1224 } 1225 #else 1226 phy_data |= M88E1000_PSCR_AUTO_X_MODE; 1227 #endif 1228 1229 #if 0 1230 /* Options: 1231 * disable_polarity_correction = 0 (default) 1232 * Automatic Correction for Reversed Cable Polarity 1233 * 0 - Disabled 1234 * 1 - Enabled 1235 */ 1236 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; 1237 if (hw->disable_polarity_correction == 1) 1238 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL; 1239 #else 1240 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; 1241 #endif 1242 if (e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data) < 0) { 1243 DEBUGOUT("PHY Write Error\n"); 1244 return -E1000_ERR_PHY; 1245 } 1246 1247 /* Force TX_CLK in the Extended PHY Specific Control Register 1248 * to 25MHz clock. 1249 */ 1250 if (e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data) < 0) { 1251 DEBUGOUT("PHY Read Error\n"); 1252 return -E1000_ERR_PHY; 1253 } 1254 phy_data |= M88E1000_EPSCR_TX_CLK_25; 1255 /* Configure Master and Slave downshift values */ 1256 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK | 1257 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK); 1258 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X | 1259 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X); 1260 if (e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data) < 0) { 1261 DEBUGOUT("PHY Write Error\n"); 1262 return -E1000_ERR_PHY; 1263 } 1264 1265 /* SW Reset the PHY so all changes take effect */ 1266 ret_val = e1000_phy_reset(hw); 1267 if (ret_val < 0) { 1268 DEBUGOUT("Error Resetting the PHY\n"); 1269 return ret_val; 1270 } 1271 1272 /* Options: 1273 * autoneg = 1 (default) 1274 * PHY will advertise value(s) parsed from 1275 * autoneg_advertised and fc 1276 * autoneg = 0 1277 * PHY will be set to 10H, 10F, 100H, or 100F 1278 * depending on value parsed from forced_speed_duplex. 1279 */ 1280 1281 /* Is autoneg enabled? This is enabled by default or by software override. 1282 * If so, call e1000_phy_setup_autoneg routine to parse the 1283 * autoneg_advertised and fc options. If autoneg is NOT enabled, then the 1284 * user should have provided a speed/duplex override. If so, then call 1285 * e1000_phy_force_speed_duplex to parse and set this up. 1286 */ 1287 /* Perform some bounds checking on the hw->autoneg_advertised 1288 * parameter. If this variable is zero, then set it to the default. 1289 */ 1290 hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT; 1291 1292 /* If autoneg_advertised is zero, we assume it was not defaulted 1293 * by the calling code so we set to advertise full capability. 1294 */ 1295 if (hw->autoneg_advertised == 0) 1296 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT; 1297 1298 DEBUGOUT("Reconfiguring auto-neg advertisement params\n"); 1299 ret_val = e1000_phy_setup_autoneg(hw); 1300 if (ret_val < 0) { 1301 DEBUGOUT("Error Setting up Auto-Negotiation\n"); 1302 return ret_val; 1303 } 1304 DEBUGOUT("Restarting Auto-Neg\n"); 1305 1306 /* Restart auto-negotiation by setting the Auto Neg Enable bit and 1307 * the Auto Neg Restart bit in the PHY control register. 1308 */ 1309 if (e1000_read_phy_reg(hw, PHY_CTRL, &phy_data) < 0) { 1310 DEBUGOUT("PHY Read Error\n"); 1311 return -E1000_ERR_PHY; 1312 } 1313 phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); 1314 if (e1000_write_phy_reg(hw, PHY_CTRL, phy_data) < 0) { 1315 DEBUGOUT("PHY Write Error\n"); 1316 return -E1000_ERR_PHY; 1317 } 1318 #if 0 1319 /* Does the user want to wait for Auto-Neg to complete here, or 1320 * check at a later time (for example, callback routine). 1321 */ 1322 if (hw->wait_autoneg_complete) { 1323 ret_val = e1000_wait_autoneg(hw); 1324 if (ret_val < 0) { 1325 DEBUGOUT 1326 ("Error while waiting for autoneg to complete\n"); 1327 return ret_val; 1328 } 1329 } 1330 #else 1331 /* If we do not wait for autonegtation to complete I 1332 * do not see a valid link status. 1333 */ 1334 ret_val = e1000_wait_autoneg(hw); 1335 if (ret_val < 0) { 1336 DEBUGOUT("Error while waiting for autoneg to complete\n"); 1337 return ret_val; 1338 } 1339 #endif 1340 1341 /* Check link status. Wait up to 100 microseconds for link to become 1342 * valid. 1343 */ 1344 for (i = 0; i < 10; i++) { 1345 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) { 1346 DEBUGOUT("PHY Read Error\n"); 1347 return -E1000_ERR_PHY; 1348 } 1349 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) { 1350 DEBUGOUT("PHY Read Error\n"); 1351 return -E1000_ERR_PHY; 1352 } 1353 if (phy_data & MII_SR_LINK_STATUS) { 1354 /* We have link, so we need to finish the config process: 1355 * 1) Set up the MAC to the current PHY speed/duplex 1356 * if we are on 82543. If we 1357 * are on newer silicon, we only need to configure 1358 * collision distance in the Transmit Control Register. 1359 * 2) Set up flow control on the MAC to that established with 1360 * the link partner. 1361 */ 1362 if (hw->mac_type >= e1000_82544) { 1363 e1000_config_collision_dist(hw); 1364 } else { 1365 ret_val = e1000_config_mac_to_phy(hw); 1366 if (ret_val < 0) { 1367 DEBUGOUT 1368 ("Error configuring MAC to PHY settings\n"); 1369 return ret_val; 1370 } 1371 } 1372 ret_val = e1000_config_fc_after_link_up(hw); 1373 if (ret_val < 0) { 1374 DEBUGOUT("Error Configuring Flow Control\n"); 1375 return ret_val; 1376 } 1377 DEBUGOUT("Valid link established!!!\n"); 1378 return 0; 1379 } 1380 udelay(10); 1381 } 1382 1383 DEBUGOUT("Unable to establish link!!!\n"); 1384 return -E1000_ERR_NOLINK; 1385 } 1386 1387 /****************************************************************************** 1388 * Configures PHY autoneg and flow control advertisement settings 1389 * 1390 * hw - Struct containing variables accessed by shared code 1391 ******************************************************************************/ 1392 static int 1393 e1000_phy_setup_autoneg(struct e1000_hw *hw) 1394 { 1395 uint16_t mii_autoneg_adv_reg; 1396 uint16_t mii_1000t_ctrl_reg; 1397 1398 DEBUGFUNC(); 1399 1400 /* Read the MII Auto-Neg Advertisement Register (Address 4). */ 1401 if (e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg) < 0) { 1402 DEBUGOUT("PHY Read Error\n"); 1403 return -E1000_ERR_PHY; 1404 } 1405 1406 /* Read the MII 1000Base-T Control Register (Address 9). */ 1407 if (e1000_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg) < 0) { 1408 DEBUGOUT("PHY Read Error\n"); 1409 return -E1000_ERR_PHY; 1410 } 1411 1412 /* Need to parse both autoneg_advertised and fc and set up 1413 * the appropriate PHY registers. First we will parse for 1414 * autoneg_advertised software override. Since we can advertise 1415 * a plethora of combinations, we need to check each bit 1416 * individually. 1417 */ 1418 1419 /* First we clear all the 10/100 mb speed bits in the Auto-Neg 1420 * Advertisement Register (Address 4) and the 1000 mb speed bits in 1421 * the 1000Base-T Control Register (Address 9). 1422 */ 1423 mii_autoneg_adv_reg &= ~REG4_SPEED_MASK; 1424 mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK; 1425 1426 DEBUGOUT("autoneg_advertised %x\n", hw->autoneg_advertised); 1427 1428 /* Do we want to advertise 10 Mb Half Duplex? */ 1429 if (hw->autoneg_advertised & ADVERTISE_10_HALF) { 1430 DEBUGOUT("Advertise 10mb Half duplex\n"); 1431 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS; 1432 } 1433 1434 /* Do we want to advertise 10 Mb Full Duplex? */ 1435 if (hw->autoneg_advertised & ADVERTISE_10_FULL) { 1436 DEBUGOUT("Advertise 10mb Full duplex\n"); 1437 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS; 1438 } 1439 1440 /* Do we want to advertise 100 Mb Half Duplex? */ 1441 if (hw->autoneg_advertised & ADVERTISE_100_HALF) { 1442 DEBUGOUT("Advertise 100mb Half duplex\n"); 1443 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS; 1444 } 1445 1446 /* Do we want to advertise 100 Mb Full Duplex? */ 1447 if (hw->autoneg_advertised & ADVERTISE_100_FULL) { 1448 DEBUGOUT("Advertise 100mb Full duplex\n"); 1449 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS; 1450 } 1451 1452 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */ 1453 if (hw->autoneg_advertised & ADVERTISE_1000_HALF) { 1454 DEBUGOUT 1455 ("Advertise 1000mb Half duplex requested, request denied!\n"); 1456 } 1457 1458 /* Do we want to advertise 1000 Mb Full Duplex? */ 1459 if (hw->autoneg_advertised & ADVERTISE_1000_FULL) { 1460 DEBUGOUT("Advertise 1000mb Full duplex\n"); 1461 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS; 1462 } 1463 1464 /* Check for a software override of the flow control settings, and 1465 * setup the PHY advertisement registers accordingly. If 1466 * auto-negotiation is enabled, then software will have to set the 1467 * "PAUSE" bits to the correct value in the Auto-Negotiation 1468 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation. 1469 * 1470 * The possible values of the "fc" parameter are: 1471 * 0: Flow control is completely disabled 1472 * 1: Rx flow control is enabled (we can receive pause frames 1473 * but not send pause frames). 1474 * 2: Tx flow control is enabled (we can send pause frames 1475 * but we do not support receiving pause frames). 1476 * 3: Both Rx and TX flow control (symmetric) are enabled. 1477 * other: No software override. The flow control configuration 1478 * in the EEPROM is used. 1479 */ 1480 switch (hw->fc) { 1481 case e1000_fc_none: /* 0 */ 1482 /* Flow control (RX & TX) is completely disabled by a 1483 * software over-ride. 1484 */ 1485 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 1486 break; 1487 case e1000_fc_rx_pause: /* 1 */ 1488 /* RX Flow control is enabled, and TX Flow control is 1489 * disabled, by a software over-ride. 1490 */ 1491 /* Since there really isn't a way to advertise that we are 1492 * capable of RX Pause ONLY, we will advertise that we 1493 * support both symmetric and asymmetric RX PAUSE. Later 1494 * (in e1000_config_fc_after_link_up) we will disable the 1495 *hw's ability to send PAUSE frames. 1496 */ 1497 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 1498 break; 1499 case e1000_fc_tx_pause: /* 2 */ 1500 /* TX Flow control is enabled, and RX Flow control is 1501 * disabled, by a software over-ride. 1502 */ 1503 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR; 1504 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE; 1505 break; 1506 case e1000_fc_full: /* 3 */ 1507 /* Flow control (both RX and TX) is enabled by a software 1508 * over-ride. 1509 */ 1510 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 1511 break; 1512 default: 1513 DEBUGOUT("Flow control param set incorrectly\n"); 1514 return -E1000_ERR_CONFIG; 1515 } 1516 1517 if (e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg) < 0) { 1518 DEBUGOUT("PHY Write Error\n"); 1519 return -E1000_ERR_PHY; 1520 } 1521 1522 DEBUGOUT("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); 1523 1524 if (e1000_write_phy_reg(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg) < 0) { 1525 DEBUGOUT("PHY Write Error\n"); 1526 return -E1000_ERR_PHY; 1527 } 1528 return 0; 1529 } 1530 1531 /****************************************************************************** 1532 * Sets the collision distance in the Transmit Control register 1533 * 1534 * hw - Struct containing variables accessed by shared code 1535 * 1536 * Link should have been established previously. Reads the speed and duplex 1537 * information from the Device Status register. 1538 ******************************************************************************/ 1539 static void 1540 e1000_config_collision_dist(struct e1000_hw *hw) 1541 { 1542 uint32_t tctl; 1543 1544 tctl = E1000_READ_REG(hw, TCTL); 1545 1546 tctl &= ~E1000_TCTL_COLD; 1547 tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT; 1548 1549 E1000_WRITE_REG(hw, TCTL, tctl); 1550 E1000_WRITE_FLUSH(hw); 1551 } 1552 1553 /****************************************************************************** 1554 * Sets MAC speed and duplex settings to reflect the those in the PHY 1555 * 1556 * hw - Struct containing variables accessed by shared code 1557 * mii_reg - data to write to the MII control register 1558 * 1559 * The contents of the PHY register containing the needed information need to 1560 * be passed in. 1561 ******************************************************************************/ 1562 static int 1563 e1000_config_mac_to_phy(struct e1000_hw *hw) 1564 { 1565 uint32_t ctrl; 1566 uint16_t phy_data; 1567 1568 DEBUGFUNC(); 1569 1570 /* Read the Device Control Register and set the bits to Force Speed 1571 * and Duplex. 1572 */ 1573 ctrl = E1000_READ_REG(hw, CTRL); 1574 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1575 ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS); 1576 1577 /* Set up duplex in the Device Control and Transmit Control 1578 * registers depending on negotiated values. 1579 */ 1580 if (e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data) < 0) { 1581 DEBUGOUT("PHY Read Error\n"); 1582 return -E1000_ERR_PHY; 1583 } 1584 if (phy_data & M88E1000_PSSR_DPLX) 1585 ctrl |= E1000_CTRL_FD; 1586 else 1587 ctrl &= ~E1000_CTRL_FD; 1588 1589 e1000_config_collision_dist(hw); 1590 1591 /* Set up speed in the Device Control register depending on 1592 * negotiated values. 1593 */ 1594 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) 1595 ctrl |= E1000_CTRL_SPD_1000; 1596 else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS) 1597 ctrl |= E1000_CTRL_SPD_100; 1598 /* Write the configured values back to the Device Control Reg. */ 1599 E1000_WRITE_REG(hw, CTRL, ctrl); 1600 return 0; 1601 } 1602 1603 /****************************************************************************** 1604 * Forces the MAC's flow control settings. 1605 * 1606 * hw - Struct containing variables accessed by shared code 1607 * 1608 * Sets the TFCE and RFCE bits in the device control register to reflect 1609 * the adapter settings. TFCE and RFCE need to be explicitly set by 1610 * software when a Copper PHY is used because autonegotiation is managed 1611 * by the PHY rather than the MAC. Software must also configure these 1612 * bits when link is forced on a fiber connection. 1613 *****************************************************************************/ 1614 static int 1615 e1000_force_mac_fc(struct e1000_hw *hw) 1616 { 1617 uint32_t ctrl; 1618 1619 DEBUGFUNC(); 1620 1621 /* Get the current configuration of the Device Control Register */ 1622 ctrl = E1000_READ_REG(hw, CTRL); 1623 1624 /* Because we didn't get link via the internal auto-negotiation 1625 * mechanism (we either forced link or we got link via PHY 1626 * auto-neg), we have to manually enable/disable transmit an 1627 * receive flow control. 1628 * 1629 * The "Case" statement below enables/disable flow control 1630 * according to the "hw->fc" parameter. 1631 * 1632 * The possible values of the "fc" parameter are: 1633 * 0: Flow control is completely disabled 1634 * 1: Rx flow control is enabled (we can receive pause 1635 * frames but not send pause frames). 1636 * 2: Tx flow control is enabled (we can send pause frames 1637 * frames but we do not receive pause frames). 1638 * 3: Both Rx and TX flow control (symmetric) is enabled. 1639 * other: No other values should be possible at this point. 1640 */ 1641 1642 switch (hw->fc) { 1643 case e1000_fc_none: 1644 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE)); 1645 break; 1646 case e1000_fc_rx_pause: 1647 ctrl &= (~E1000_CTRL_TFCE); 1648 ctrl |= E1000_CTRL_RFCE; 1649 break; 1650 case e1000_fc_tx_pause: 1651 ctrl &= (~E1000_CTRL_RFCE); 1652 ctrl |= E1000_CTRL_TFCE; 1653 break; 1654 case e1000_fc_full: 1655 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE); 1656 break; 1657 default: 1658 DEBUGOUT("Flow control param set incorrectly\n"); 1659 return -E1000_ERR_CONFIG; 1660 } 1661 1662 /* Disable TX Flow Control for 82542 (rev 2.0) */ 1663 if (hw->mac_type == e1000_82542_rev2_0) 1664 ctrl &= (~E1000_CTRL_TFCE); 1665 1666 E1000_WRITE_REG(hw, CTRL, ctrl); 1667 return 0; 1668 } 1669 1670 /****************************************************************************** 1671 * Configures flow control settings after link is established 1672 * 1673 * hw - Struct containing variables accessed by shared code 1674 * 1675 * Should be called immediately after a valid link has been established. 1676 * Forces MAC flow control settings if link was forced. When in MII/GMII mode 1677 * and autonegotiation is enabled, the MAC flow control settings will be set 1678 * based on the flow control negotiated by the PHY. In TBI mode, the TFCE 1679 * and RFCE bits will be automaticaly set to the negotiated flow control mode. 1680 *****************************************************************************/ 1681 static int 1682 e1000_config_fc_after_link_up(struct e1000_hw *hw) 1683 { 1684 int32_t ret_val; 1685 uint16_t mii_status_reg; 1686 uint16_t mii_nway_adv_reg; 1687 uint16_t mii_nway_lp_ability_reg; 1688 uint16_t speed; 1689 uint16_t duplex; 1690 1691 DEBUGFUNC(); 1692 1693 /* Check for the case where we have fiber media and auto-neg failed 1694 * so we had to force link. In this case, we need to force the 1695 * configuration of the MAC to match the "fc" parameter. 1696 */ 1697 if ((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed)) { 1698 ret_val = e1000_force_mac_fc(hw); 1699 if (ret_val < 0) { 1700 DEBUGOUT("Error forcing flow control settings\n"); 1701 return ret_val; 1702 } 1703 } 1704 1705 /* Check for the case where we have copper media and auto-neg is 1706 * enabled. In this case, we need to check and see if Auto-Neg 1707 * has completed, and if so, how the PHY and link partner has 1708 * flow control configured. 1709 */ 1710 if (hw->media_type == e1000_media_type_copper) { 1711 /* Read the MII Status Register and check to see if AutoNeg 1712 * has completed. We read this twice because this reg has 1713 * some "sticky" (latched) bits. 1714 */ 1715 if (e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) { 1716 DEBUGOUT("PHY Read Error \n"); 1717 return -E1000_ERR_PHY; 1718 } 1719 if (e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) { 1720 DEBUGOUT("PHY Read Error \n"); 1721 return -E1000_ERR_PHY; 1722 } 1723 1724 if (mii_status_reg & MII_SR_AUTONEG_COMPLETE) { 1725 /* The AutoNeg process has completed, so we now need to 1726 * read both the Auto Negotiation Advertisement Register 1727 * (Address 4) and the Auto_Negotiation Base Page Ability 1728 * Register (Address 5) to determine how flow control was 1729 * negotiated. 1730 */ 1731 if (e1000_read_phy_reg 1732 (hw, PHY_AUTONEG_ADV, &mii_nway_adv_reg) < 0) { 1733 DEBUGOUT("PHY Read Error\n"); 1734 return -E1000_ERR_PHY; 1735 } 1736 if (e1000_read_phy_reg 1737 (hw, PHY_LP_ABILITY, 1738 &mii_nway_lp_ability_reg) < 0) { 1739 DEBUGOUT("PHY Read Error\n"); 1740 return -E1000_ERR_PHY; 1741 } 1742 1743 /* Two bits in the Auto Negotiation Advertisement Register 1744 * (Address 4) and two bits in the Auto Negotiation Base 1745 * Page Ability Register (Address 5) determine flow control 1746 * for both the PHY and the link partner. The following 1747 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25, 1748 * 1999, describes these PAUSE resolution bits and how flow 1749 * control is determined based upon these settings. 1750 * NOTE: DC = Don't Care 1751 * 1752 * LOCAL DEVICE | LINK PARTNER 1753 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution 1754 *-------|---------|-------|---------|-------------------- 1755 * 0 | 0 | DC | DC | e1000_fc_none 1756 * 0 | 1 | 0 | DC | e1000_fc_none 1757 * 0 | 1 | 1 | 0 | e1000_fc_none 1758 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 1759 * 1 | 0 | 0 | DC | e1000_fc_none 1760 * 1 | DC | 1 | DC | e1000_fc_full 1761 * 1 | 1 | 0 | 0 | e1000_fc_none 1762 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 1763 * 1764 */ 1765 /* Are both PAUSE bits set to 1? If so, this implies 1766 * Symmetric Flow Control is enabled at both ends. The 1767 * ASM_DIR bits are irrelevant per the spec. 1768 * 1769 * For Symmetric Flow Control: 1770 * 1771 * LOCAL DEVICE | LINK PARTNER 1772 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1773 *-------|---------|-------|---------|-------------------- 1774 * 1 | DC | 1 | DC | e1000_fc_full 1775 * 1776 */ 1777 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 1778 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) { 1779 /* Now we need to check if the user selected RX ONLY 1780 * of pause frames. In this case, we had to advertise 1781 * FULL flow control because we could not advertise RX 1782 * ONLY. Hence, we must now check to see if we need to 1783 * turn OFF the TRANSMISSION of PAUSE frames. 1784 */ 1785 if (hw->original_fc == e1000_fc_full) { 1786 hw->fc = e1000_fc_full; 1787 DEBUGOUT("Flow Control = FULL.\r\n"); 1788 } else { 1789 hw->fc = e1000_fc_rx_pause; 1790 DEBUGOUT 1791 ("Flow Control = RX PAUSE frames only.\r\n"); 1792 } 1793 } 1794 /* For receiving PAUSE frames ONLY. 1795 * 1796 * LOCAL DEVICE | LINK PARTNER 1797 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1798 *-------|---------|-------|---------|-------------------- 1799 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 1800 * 1801 */ 1802 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) && 1803 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 1804 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 1805 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) 1806 { 1807 hw->fc = e1000_fc_tx_pause; 1808 DEBUGOUT 1809 ("Flow Control = TX PAUSE frames only.\r\n"); 1810 } 1811 /* For transmitting PAUSE frames ONLY. 1812 * 1813 * LOCAL DEVICE | LINK PARTNER 1814 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1815 *-------|---------|-------|---------|-------------------- 1816 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 1817 * 1818 */ 1819 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 1820 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 1821 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 1822 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) 1823 { 1824 hw->fc = e1000_fc_rx_pause; 1825 DEBUGOUT 1826 ("Flow Control = RX PAUSE frames only.\r\n"); 1827 } 1828 /* Per the IEEE spec, at this point flow control should be 1829 * disabled. However, we want to consider that we could 1830 * be connected to a legacy switch that doesn't advertise 1831 * desired flow control, but can be forced on the link 1832 * partner. So if we advertised no flow control, that is 1833 * what we will resolve to. If we advertised some kind of 1834 * receive capability (Rx Pause Only or Full Flow Control) 1835 * and the link partner advertised none, we will configure 1836 * ourselves to enable Rx Flow Control only. We can do 1837 * this safely for two reasons: If the link partner really 1838 * didn't want flow control enabled, and we enable Rx, no 1839 * harm done since we won't be receiving any PAUSE frames 1840 * anyway. If the intent on the link partner was to have 1841 * flow control enabled, then by us enabling RX only, we 1842 * can at least receive pause frames and process them. 1843 * This is a good idea because in most cases, since we are 1844 * predominantly a server NIC, more times than not we will 1845 * be asked to delay transmission of packets than asking 1846 * our link partner to pause transmission of frames. 1847 */ 1848 else if (hw->original_fc == e1000_fc_none || 1849 hw->original_fc == e1000_fc_tx_pause) { 1850 hw->fc = e1000_fc_none; 1851 DEBUGOUT("Flow Control = NONE.\r\n"); 1852 } else { 1853 hw->fc = e1000_fc_rx_pause; 1854 DEBUGOUT 1855 ("Flow Control = RX PAUSE frames only.\r\n"); 1856 } 1857 1858 /* Now we need to do one last check... If we auto- 1859 * negotiated to HALF DUPLEX, flow control should not be 1860 * enabled per IEEE 802.3 spec. 1861 */ 1862 e1000_get_speed_and_duplex(hw, &speed, &duplex); 1863 1864 if (duplex == HALF_DUPLEX) 1865 hw->fc = e1000_fc_none; 1866 1867 /* Now we call a subroutine to actually force the MAC 1868 * controller to use the correct flow control settings. 1869 */ 1870 ret_val = e1000_force_mac_fc(hw); 1871 if (ret_val < 0) { 1872 DEBUGOUT 1873 ("Error forcing flow control settings\n"); 1874 return ret_val; 1875 } 1876 } else { 1877 DEBUGOUT 1878 ("Copper PHY and Auto Neg has not completed.\r\n"); 1879 } 1880 } 1881 return 0; 1882 } 1883 1884 /****************************************************************************** 1885 * Checks to see if the link status of the hardware has changed. 1886 * 1887 * hw - Struct containing variables accessed by shared code 1888 * 1889 * Called by any function that needs to check the link status of the adapter. 1890 *****************************************************************************/ 1891 static int 1892 e1000_check_for_link(struct eth_device *nic) 1893 { 1894 struct e1000_hw *hw = nic->priv; 1895 uint32_t rxcw; 1896 uint32_t ctrl; 1897 uint32_t status; 1898 uint32_t rctl; 1899 uint32_t signal; 1900 int32_t ret_val; 1901 uint16_t phy_data; 1902 uint16_t lp_capability; 1903 1904 DEBUGFUNC(); 1905 1906 /* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be 1907 * set when the optics detect a signal. On older adapters, it will be 1908 * cleared when there is a signal 1909 */ 1910 ctrl = E1000_READ_REG(hw, CTRL); 1911 if ((hw->mac_type > e1000_82544) && !(ctrl & E1000_CTRL_ILOS)) 1912 signal = E1000_CTRL_SWDPIN1; 1913 else 1914 signal = 0; 1915 1916 status = E1000_READ_REG(hw, STATUS); 1917 rxcw = E1000_READ_REG(hw, RXCW); 1918 DEBUGOUT("ctrl: %#08x status %#08x rxcw %#08x\n", ctrl, status, rxcw); 1919 1920 /* If we have a copper PHY then we only want to go out to the PHY 1921 * registers to see if Auto-Neg has completed and/or if our link 1922 * status has changed. The get_link_status flag will be set if we 1923 * receive a Link Status Change interrupt or we have Rx Sequence 1924 * Errors. 1925 */ 1926 if ((hw->media_type == e1000_media_type_copper) && hw->get_link_status) { 1927 /* First we want to see if the MII Status Register reports 1928 * link. If so, then we want to get the current speed/duplex 1929 * of the PHY. 1930 * Read the register twice since the link bit is sticky. 1931 */ 1932 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) { 1933 DEBUGOUT("PHY Read Error\n"); 1934 return -E1000_ERR_PHY; 1935 } 1936 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) { 1937 DEBUGOUT("PHY Read Error\n"); 1938 return -E1000_ERR_PHY; 1939 } 1940 1941 if (phy_data & MII_SR_LINK_STATUS) { 1942 hw->get_link_status = FALSE; 1943 } else { 1944 /* No link detected */ 1945 return -E1000_ERR_NOLINK; 1946 } 1947 1948 /* We have a M88E1000 PHY and Auto-Neg is enabled. If we 1949 * have Si on board that is 82544 or newer, Auto 1950 * Speed Detection takes care of MAC speed/duplex 1951 * configuration. So we only need to configure Collision 1952 * Distance in the MAC. Otherwise, we need to force 1953 * speed/duplex on the MAC to the current PHY speed/duplex 1954 * settings. 1955 */ 1956 if (hw->mac_type >= e1000_82544) 1957 e1000_config_collision_dist(hw); 1958 else { 1959 ret_val = e1000_config_mac_to_phy(hw); 1960 if (ret_val < 0) { 1961 DEBUGOUT 1962 ("Error configuring MAC to PHY settings\n"); 1963 return ret_val; 1964 } 1965 } 1966 1967 /* Configure Flow Control now that Auto-Neg has completed. First, we 1968 * need to restore the desired flow control settings because we may 1969 * have had to re-autoneg with a different link partner. 1970 */ 1971 ret_val = e1000_config_fc_after_link_up(hw); 1972 if (ret_val < 0) { 1973 DEBUGOUT("Error configuring flow control\n"); 1974 return ret_val; 1975 } 1976 1977 /* At this point we know that we are on copper and we have 1978 * auto-negotiated link. These are conditions for checking the link 1979 * parter capability register. We use the link partner capability to 1980 * determine if TBI Compatibility needs to be turned on or off. If 1981 * the link partner advertises any speed in addition to Gigabit, then 1982 * we assume that they are GMII-based, and TBI compatibility is not 1983 * needed. If no other speeds are advertised, we assume the link 1984 * partner is TBI-based, and we turn on TBI Compatibility. 1985 */ 1986 if (hw->tbi_compatibility_en) { 1987 if (e1000_read_phy_reg 1988 (hw, PHY_LP_ABILITY, &lp_capability) < 0) { 1989 DEBUGOUT("PHY Read Error\n"); 1990 return -E1000_ERR_PHY; 1991 } 1992 if (lp_capability & (NWAY_LPAR_10T_HD_CAPS | 1993 NWAY_LPAR_10T_FD_CAPS | 1994 NWAY_LPAR_100TX_HD_CAPS | 1995 NWAY_LPAR_100TX_FD_CAPS | 1996 NWAY_LPAR_100T4_CAPS)) { 1997 /* If our link partner advertises anything in addition to 1998 * gigabit, we do not need to enable TBI compatibility. 1999 */ 2000 if (hw->tbi_compatibility_on) { 2001 /* If we previously were in the mode, turn it off. */ 2002 rctl = E1000_READ_REG(hw, RCTL); 2003 rctl &= ~E1000_RCTL_SBP; 2004 E1000_WRITE_REG(hw, RCTL, rctl); 2005 hw->tbi_compatibility_on = FALSE; 2006 } 2007 } else { 2008 /* If TBI compatibility is was previously off, turn it on. For 2009 * compatibility with a TBI link partner, we will store bad 2010 * packets. Some frames have an additional byte on the end and 2011 * will look like CRC errors to to the hardware. 2012 */ 2013 if (!hw->tbi_compatibility_on) { 2014 hw->tbi_compatibility_on = TRUE; 2015 rctl = E1000_READ_REG(hw, RCTL); 2016 rctl |= E1000_RCTL_SBP; 2017 E1000_WRITE_REG(hw, RCTL, rctl); 2018 } 2019 } 2020 } 2021 } 2022 /* If we don't have link (auto-negotiation failed or link partner cannot 2023 * auto-negotiate), the cable is plugged in (we have signal), and our 2024 * link partner is not trying to auto-negotiate with us (we are receiving 2025 * idles or data), we need to force link up. We also need to give 2026 * auto-negotiation time to complete, in case the cable was just plugged 2027 * in. The autoneg_failed flag does this. 2028 */ 2029 else if ((hw->media_type == e1000_media_type_fiber) && 2030 (!(status & E1000_STATUS_LU)) && 2031 ((ctrl & E1000_CTRL_SWDPIN1) == signal) && 2032 (!(rxcw & E1000_RXCW_C))) { 2033 if (hw->autoneg_failed == 0) { 2034 hw->autoneg_failed = 1; 2035 return 0; 2036 } 2037 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\r\n"); 2038 2039 /* Disable auto-negotiation in the TXCW register */ 2040 E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE)); 2041 2042 /* Force link-up and also force full-duplex. */ 2043 ctrl = E1000_READ_REG(hw, CTRL); 2044 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 2045 E1000_WRITE_REG(hw, CTRL, ctrl); 2046 2047 /* Configure Flow Control after forcing link up. */ 2048 ret_val = e1000_config_fc_after_link_up(hw); 2049 if (ret_val < 0) { 2050 DEBUGOUT("Error configuring flow control\n"); 2051 return ret_val; 2052 } 2053 } 2054 /* If we are forcing link and we are receiving /C/ ordered sets, re-enable 2055 * auto-negotiation in the TXCW register and disable forced link in the 2056 * Device Control register in an attempt to auto-negotiate with our link 2057 * partner. 2058 */ 2059 else if ((hw->media_type == e1000_media_type_fiber) && 2060 (ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { 2061 DEBUGOUT 2062 ("RXing /C/, enable AutoNeg and stop forcing link.\r\n"); 2063 E1000_WRITE_REG(hw, TXCW, hw->txcw); 2064 E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU)); 2065 } 2066 return 0; 2067 } 2068 2069 /****************************************************************************** 2070 * Detects the current speed and duplex settings of the hardware. 2071 * 2072 * hw - Struct containing variables accessed by shared code 2073 * speed - Speed of the connection 2074 * duplex - Duplex setting of the connection 2075 *****************************************************************************/ 2076 static void 2077 e1000_get_speed_and_duplex(struct e1000_hw *hw, 2078 uint16_t * speed, uint16_t * duplex) 2079 { 2080 uint32_t status; 2081 2082 DEBUGFUNC(); 2083 2084 if (hw->mac_type >= e1000_82543) { 2085 status = E1000_READ_REG(hw, STATUS); 2086 if (status & E1000_STATUS_SPEED_1000) { 2087 *speed = SPEED_1000; 2088 DEBUGOUT("1000 Mbs, "); 2089 } else if (status & E1000_STATUS_SPEED_100) { 2090 *speed = SPEED_100; 2091 DEBUGOUT("100 Mbs, "); 2092 } else { 2093 *speed = SPEED_10; 2094 DEBUGOUT("10 Mbs, "); 2095 } 2096 2097 if (status & E1000_STATUS_FD) { 2098 *duplex = FULL_DUPLEX; 2099 DEBUGOUT("Full Duplex\r\n"); 2100 } else { 2101 *duplex = HALF_DUPLEX; 2102 DEBUGOUT(" Half Duplex\r\n"); 2103 } 2104 } else { 2105 DEBUGOUT("1000 Mbs, Full Duplex\r\n"); 2106 *speed = SPEED_1000; 2107 *duplex = FULL_DUPLEX; 2108 } 2109 } 2110 2111 /****************************************************************************** 2112 * Blocks until autoneg completes or times out (~4.5 seconds) 2113 * 2114 * hw - Struct containing variables accessed by shared code 2115 ******************************************************************************/ 2116 static int 2117 e1000_wait_autoneg(struct e1000_hw *hw) 2118 { 2119 uint16_t i; 2120 uint16_t phy_data; 2121 2122 DEBUGFUNC(); 2123 DEBUGOUT("Waiting for Auto-Neg to complete.\n"); 2124 2125 /* We will wait for autoneg to complete or 4.5 seconds to expire. */ 2126 for (i = PHY_AUTO_NEG_TIME; i > 0; i--) { 2127 /* Read the MII Status Register and wait for Auto-Neg 2128 * Complete bit to be set. 2129 */ 2130 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) { 2131 DEBUGOUT("PHY Read Error\n"); 2132 return -E1000_ERR_PHY; 2133 } 2134 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) { 2135 DEBUGOUT("PHY Read Error\n"); 2136 return -E1000_ERR_PHY; 2137 } 2138 if (phy_data & MII_SR_AUTONEG_COMPLETE) { 2139 DEBUGOUT("Auto-Neg complete.\n"); 2140 return 0; 2141 } 2142 mdelay(100); 2143 } 2144 DEBUGOUT("Auto-Neg timedout.\n"); 2145 return -E1000_ERR_TIMEOUT; 2146 } 2147 2148 /****************************************************************************** 2149 * Raises the Management Data Clock 2150 * 2151 * hw - Struct containing variables accessed by shared code 2152 * ctrl - Device control register's current value 2153 ******************************************************************************/ 2154 static void 2155 e1000_raise_mdi_clk(struct e1000_hw *hw, uint32_t * ctrl) 2156 { 2157 /* Raise the clock input to the Management Data Clock (by setting the MDC 2158 * bit), and then delay 2 microseconds. 2159 */ 2160 E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC)); 2161 E1000_WRITE_FLUSH(hw); 2162 udelay(2); 2163 } 2164 2165 /****************************************************************************** 2166 * Lowers the Management Data Clock 2167 * 2168 * hw - Struct containing variables accessed by shared code 2169 * ctrl - Device control register's current value 2170 ******************************************************************************/ 2171 static void 2172 e1000_lower_mdi_clk(struct e1000_hw *hw, uint32_t * ctrl) 2173 { 2174 /* Lower the clock input to the Management Data Clock (by clearing the MDC 2175 * bit), and then delay 2 microseconds. 2176 */ 2177 E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC)); 2178 E1000_WRITE_FLUSH(hw); 2179 udelay(2); 2180 } 2181 2182 /****************************************************************************** 2183 * Shifts data bits out to the PHY 2184 * 2185 * hw - Struct containing variables accessed by shared code 2186 * data - Data to send out to the PHY 2187 * count - Number of bits to shift out 2188 * 2189 * Bits are shifted out in MSB to LSB order. 2190 ******************************************************************************/ 2191 static void 2192 e1000_shift_out_mdi_bits(struct e1000_hw *hw, uint32_t data, uint16_t count) 2193 { 2194 uint32_t ctrl; 2195 uint32_t mask; 2196 2197 /* We need to shift "count" number of bits out to the PHY. So, the value 2198 * in the "data" parameter will be shifted out to the PHY one bit at a 2199 * time. In order to do this, "data" must be broken down into bits. 2200 */ 2201 mask = 0x01; 2202 mask <<= (count - 1); 2203 2204 ctrl = E1000_READ_REG(hw, CTRL); 2205 2206 /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */ 2207 ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR); 2208 2209 while (mask) { 2210 /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and 2211 * then raising and lowering the Management Data Clock. A "0" is 2212 * shifted out to the PHY by setting the MDIO bit to "0" and then 2213 * raising and lowering the clock. 2214 */ 2215 if (data & mask) 2216 ctrl |= E1000_CTRL_MDIO; 2217 else 2218 ctrl &= ~E1000_CTRL_MDIO; 2219 2220 E1000_WRITE_REG(hw, CTRL, ctrl); 2221 E1000_WRITE_FLUSH(hw); 2222 2223 udelay(2); 2224 2225 e1000_raise_mdi_clk(hw, &ctrl); 2226 e1000_lower_mdi_clk(hw, &ctrl); 2227 2228 mask = mask >> 1; 2229 } 2230 } 2231 2232 /****************************************************************************** 2233 * Shifts data bits in from the PHY 2234 * 2235 * hw - Struct containing variables accessed by shared code 2236 * 2237 * Bits are shifted in in MSB to LSB order. 2238 ******************************************************************************/ 2239 static uint16_t 2240 e1000_shift_in_mdi_bits(struct e1000_hw *hw) 2241 { 2242 uint32_t ctrl; 2243 uint16_t data = 0; 2244 uint8_t i; 2245 2246 /* In order to read a register from the PHY, we need to shift in a total 2247 * of 18 bits from the PHY. The first two bit (turnaround) times are used 2248 * to avoid contention on the MDIO pin when a read operation is performed. 2249 * These two bits are ignored by us and thrown away. Bits are "shifted in" 2250 * by raising the input to the Management Data Clock (setting the MDC bit), 2251 * and then reading the value of the MDIO bit. 2252 */ 2253 ctrl = E1000_READ_REG(hw, CTRL); 2254 2255 /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */ 2256 ctrl &= ~E1000_CTRL_MDIO_DIR; 2257 ctrl &= ~E1000_CTRL_MDIO; 2258 2259 E1000_WRITE_REG(hw, CTRL, ctrl); 2260 E1000_WRITE_FLUSH(hw); 2261 2262 /* Raise and Lower the clock before reading in the data. This accounts for 2263 * the turnaround bits. The first clock occurred when we clocked out the 2264 * last bit of the Register Address. 2265 */ 2266 e1000_raise_mdi_clk(hw, &ctrl); 2267 e1000_lower_mdi_clk(hw, &ctrl); 2268 2269 for (data = 0, i = 0; i < 16; i++) { 2270 data = data << 1; 2271 e1000_raise_mdi_clk(hw, &ctrl); 2272 ctrl = E1000_READ_REG(hw, CTRL); 2273 /* Check to see if we shifted in a "1". */ 2274 if (ctrl & E1000_CTRL_MDIO) 2275 data |= 1; 2276 e1000_lower_mdi_clk(hw, &ctrl); 2277 } 2278 2279 e1000_raise_mdi_clk(hw, &ctrl); 2280 e1000_lower_mdi_clk(hw, &ctrl); 2281 2282 return data; 2283 } 2284 2285 /***************************************************************************** 2286 * Reads the value from a PHY register 2287 * 2288 * hw - Struct containing variables accessed by shared code 2289 * reg_addr - address of the PHY register to read 2290 ******************************************************************************/ 2291 static int 2292 e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t * phy_data) 2293 { 2294 uint32_t i; 2295 uint32_t mdic = 0; 2296 const uint32_t phy_addr = 1; 2297 2298 if (reg_addr > MAX_PHY_REG_ADDRESS) { 2299 DEBUGOUT("PHY Address %d is out of range\n", reg_addr); 2300 return -E1000_ERR_PARAM; 2301 } 2302 2303 if (hw->mac_type > e1000_82543) { 2304 /* Set up Op-code, Phy Address, and register address in the MDI 2305 * Control register. The MAC will take care of interfacing with the 2306 * PHY to retrieve the desired data. 2307 */ 2308 mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) | 2309 (phy_addr << E1000_MDIC_PHY_SHIFT) | 2310 (E1000_MDIC_OP_READ)); 2311 2312 E1000_WRITE_REG(hw, MDIC, mdic); 2313 2314 /* Poll the ready bit to see if the MDI read completed */ 2315 for (i = 0; i < 64; i++) { 2316 udelay(10); 2317 mdic = E1000_READ_REG(hw, MDIC); 2318 if (mdic & E1000_MDIC_READY) 2319 break; 2320 } 2321 if (!(mdic & E1000_MDIC_READY)) { 2322 DEBUGOUT("MDI Read did not complete\n"); 2323 return -E1000_ERR_PHY; 2324 } 2325 if (mdic & E1000_MDIC_ERROR) { 2326 DEBUGOUT("MDI Error\n"); 2327 return -E1000_ERR_PHY; 2328 } 2329 *phy_data = (uint16_t) mdic; 2330 } else { 2331 /* We must first send a preamble through the MDIO pin to signal the 2332 * beginning of an MII instruction. This is done by sending 32 2333 * consecutive "1" bits. 2334 */ 2335 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); 2336 2337 /* Now combine the next few fields that are required for a read 2338 * operation. We use this method instead of calling the 2339 * e1000_shift_out_mdi_bits routine five different times. The format of 2340 * a MII read instruction consists of a shift out of 14 bits and is 2341 * defined as follows: 2342 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr> 2343 * followed by a shift in of 18 bits. This first two bits shifted in 2344 * are TurnAround bits used to avoid contention on the MDIO pin when a 2345 * READ operation is performed. These two bits are thrown away 2346 * followed by a shift in of 16 bits which contains the desired data. 2347 */ 2348 mdic = ((reg_addr) | (phy_addr << 5) | 2349 (PHY_OP_READ << 10) | (PHY_SOF << 12)); 2350 2351 e1000_shift_out_mdi_bits(hw, mdic, 14); 2352 2353 /* Now that we've shifted out the read command to the MII, we need to 2354 * "shift in" the 16-bit value (18 total bits) of the requested PHY 2355 * register address. 2356 */ 2357 *phy_data = e1000_shift_in_mdi_bits(hw); 2358 } 2359 return 0; 2360 } 2361 2362 /****************************************************************************** 2363 * Writes a value to a PHY register 2364 * 2365 * hw - Struct containing variables accessed by shared code 2366 * reg_addr - address of the PHY register to write 2367 * data - data to write to the PHY 2368 ******************************************************************************/ 2369 static int 2370 e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t phy_data) 2371 { 2372 uint32_t i; 2373 uint32_t mdic = 0; 2374 const uint32_t phy_addr = 1; 2375 2376 if (reg_addr > MAX_PHY_REG_ADDRESS) { 2377 DEBUGOUT("PHY Address %d is out of range\n", reg_addr); 2378 return -E1000_ERR_PARAM; 2379 } 2380 2381 if (hw->mac_type > e1000_82543) { 2382 /* Set up Op-code, Phy Address, register address, and data intended 2383 * for the PHY register in the MDI Control register. The MAC will take 2384 * care of interfacing with the PHY to send the desired data. 2385 */ 2386 mdic = (((uint32_t) phy_data) | 2387 (reg_addr << E1000_MDIC_REG_SHIFT) | 2388 (phy_addr << E1000_MDIC_PHY_SHIFT) | 2389 (E1000_MDIC_OP_WRITE)); 2390 2391 E1000_WRITE_REG(hw, MDIC, mdic); 2392 2393 /* Poll the ready bit to see if the MDI read completed */ 2394 for (i = 0; i < 64; i++) { 2395 udelay(10); 2396 mdic = E1000_READ_REG(hw, MDIC); 2397 if (mdic & E1000_MDIC_READY) 2398 break; 2399 } 2400 if (!(mdic & E1000_MDIC_READY)) { 2401 DEBUGOUT("MDI Write did not complete\n"); 2402 return -E1000_ERR_PHY; 2403 } 2404 } else { 2405 /* We'll need to use the SW defined pins to shift the write command 2406 * out to the PHY. We first send a preamble to the PHY to signal the 2407 * beginning of the MII instruction. This is done by sending 32 2408 * consecutive "1" bits. 2409 */ 2410 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); 2411 2412 /* Now combine the remaining required fields that will indicate a 2413 * write operation. We use this method instead of calling the 2414 * e1000_shift_out_mdi_bits routine for each field in the command. The 2415 * format of a MII write instruction is as follows: 2416 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>. 2417 */ 2418 mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) | 2419 (PHY_OP_WRITE << 12) | (PHY_SOF << 14)); 2420 mdic <<= 16; 2421 mdic |= (uint32_t) phy_data; 2422 2423 e1000_shift_out_mdi_bits(hw, mdic, 32); 2424 } 2425 return 0; 2426 } 2427 2428 /****************************************************************************** 2429 * Returns the PHY to the power-on reset state 2430 * 2431 * hw - Struct containing variables accessed by shared code 2432 ******************************************************************************/ 2433 static void 2434 e1000_phy_hw_reset(struct e1000_hw *hw) 2435 { 2436 uint32_t ctrl; 2437 uint32_t ctrl_ext; 2438 2439 DEBUGFUNC(); 2440 2441 DEBUGOUT("Resetting Phy...\n"); 2442 2443 if (hw->mac_type > e1000_82543) { 2444 /* Read the device control register and assert the E1000_CTRL_PHY_RST 2445 * bit. Then, take it out of reset. 2446 */ 2447 ctrl = E1000_READ_REG(hw, CTRL); 2448 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST); 2449 E1000_WRITE_FLUSH(hw); 2450 mdelay(10); 2451 E1000_WRITE_REG(hw, CTRL, ctrl); 2452 E1000_WRITE_FLUSH(hw); 2453 } else { 2454 /* Read the Extended Device Control Register, assert the PHY_RESET_DIR 2455 * bit to put the PHY into reset. Then, take it out of reset. 2456 */ 2457 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 2458 ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR; 2459 ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA; 2460 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 2461 E1000_WRITE_FLUSH(hw); 2462 mdelay(10); 2463 ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA; 2464 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 2465 E1000_WRITE_FLUSH(hw); 2466 } 2467 udelay(150); 2468 } 2469 2470 /****************************************************************************** 2471 * Resets the PHY 2472 * 2473 * hw - Struct containing variables accessed by shared code 2474 * 2475 * Sets bit 15 of the MII Control regiser 2476 ******************************************************************************/ 2477 static int 2478 e1000_phy_reset(struct e1000_hw *hw) 2479 { 2480 uint16_t phy_data; 2481 2482 DEBUGFUNC(); 2483 2484 if (e1000_read_phy_reg(hw, PHY_CTRL, &phy_data) < 0) { 2485 DEBUGOUT("PHY Read Error\n"); 2486 return -E1000_ERR_PHY; 2487 } 2488 phy_data |= MII_CR_RESET; 2489 if (e1000_write_phy_reg(hw, PHY_CTRL, phy_data) < 0) { 2490 DEBUGOUT("PHY Write Error\n"); 2491 return -E1000_ERR_PHY; 2492 } 2493 udelay(1); 2494 return 0; 2495 } 2496 2497 static int e1000_set_phy_type (struct e1000_hw *hw) 2498 { 2499 DEBUGFUNC (); 2500 2501 if (hw->mac_type == e1000_undefined) 2502 return -E1000_ERR_PHY_TYPE; 2503 2504 switch (hw->phy_id) { 2505 case M88E1000_E_PHY_ID: 2506 case M88E1000_I_PHY_ID: 2507 case M88E1011_I_PHY_ID: 2508 hw->phy_type = e1000_phy_m88; 2509 break; 2510 case IGP01E1000_I_PHY_ID: 2511 if (hw->mac_type == e1000_82541 || 2512 hw->mac_type == e1000_82541_rev_2) { 2513 hw->phy_type = e1000_phy_igp; 2514 break; 2515 } 2516 /* Fall Through */ 2517 default: 2518 /* Should never have loaded on this device */ 2519 hw->phy_type = e1000_phy_undefined; 2520 return -E1000_ERR_PHY_TYPE; 2521 } 2522 2523 return E1000_SUCCESS; 2524 } 2525 2526 /****************************************************************************** 2527 * Probes the expected PHY address for known PHY IDs 2528 * 2529 * hw - Struct containing variables accessed by shared code 2530 ******************************************************************************/ 2531 static int 2532 e1000_detect_gig_phy(struct e1000_hw *hw) 2533 { 2534 int32_t phy_init_status; 2535 uint16_t phy_id_high, phy_id_low; 2536 int match = FALSE; 2537 2538 DEBUGFUNC(); 2539 2540 /* Read the PHY ID Registers to identify which PHY is onboard. */ 2541 if (e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high) < 0) { 2542 DEBUGOUT("PHY Read Error\n"); 2543 return -E1000_ERR_PHY; 2544 } 2545 hw->phy_id = (uint32_t) (phy_id_high << 16); 2546 udelay(2); 2547 if (e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low) < 0) { 2548 DEBUGOUT("PHY Read Error\n"); 2549 return -E1000_ERR_PHY; 2550 } 2551 hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK); 2552 2553 switch (hw->mac_type) { 2554 case e1000_82543: 2555 if (hw->phy_id == M88E1000_E_PHY_ID) 2556 match = TRUE; 2557 break; 2558 case e1000_82544: 2559 if (hw->phy_id == M88E1000_I_PHY_ID) 2560 match = TRUE; 2561 break; 2562 case e1000_82540: 2563 case e1000_82545: 2564 case e1000_82546: 2565 if (hw->phy_id == M88E1011_I_PHY_ID) 2566 match = TRUE; 2567 break; 2568 case e1000_82541_rev_2: 2569 if(hw->phy_id == IGP01E1000_I_PHY_ID) 2570 match = TRUE; 2571 2572 break; 2573 default: 2574 DEBUGOUT("Invalid MAC type %d\n", hw->mac_type); 2575 return -E1000_ERR_CONFIG; 2576 } 2577 2578 phy_init_status = e1000_set_phy_type(hw); 2579 2580 if ((match) && (phy_init_status == E1000_SUCCESS)) { 2581 DEBUGOUT("PHY ID 0x%X detected\n", hw->phy_id); 2582 return 0; 2583 } 2584 DEBUGOUT("Invalid PHY ID 0x%X\n", hw->phy_id); 2585 return -E1000_ERR_PHY; 2586 } 2587 2588 /** 2589 * e1000_sw_init - Initialize general software structures (struct e1000_adapter) 2590 * 2591 * e1000_sw_init initializes the Adapter private data structure. 2592 * Fields are initialized based on PCI device information and 2593 * OS network device settings (MTU size). 2594 **/ 2595 2596 static int 2597 e1000_sw_init(struct eth_device *nic, int cardnum) 2598 { 2599 struct e1000_hw *hw = (typeof(hw)) nic->priv; 2600 int result; 2601 2602 /* PCI config space info */ 2603 pci_read_config_word(hw->pdev, PCI_VENDOR_ID, &hw->vendor_id); 2604 pci_read_config_word(hw->pdev, PCI_DEVICE_ID, &hw->device_id); 2605 pci_read_config_word(hw->pdev, PCI_SUBSYSTEM_VENDOR_ID, 2606 &hw->subsystem_vendor_id); 2607 pci_read_config_word(hw->pdev, PCI_SUBSYSTEM_ID, &hw->subsystem_id); 2608 2609 pci_read_config_byte(hw->pdev, PCI_REVISION_ID, &hw->revision_id); 2610 pci_read_config_word(hw->pdev, PCI_COMMAND, &hw->pci_cmd_word); 2611 2612 /* identify the MAC */ 2613 result = e1000_set_mac_type(hw); 2614 if (result) { 2615 E1000_ERR("Unknown MAC Type\n"); 2616 return result; 2617 } 2618 2619 /* lan a vs. lan b settings */ 2620 if (hw->mac_type == e1000_82546) 2621 /*this also works w/ multiple 82546 cards */ 2622 /*but not if they're intermingled /w other e1000s */ 2623 hw->lan_loc = (cardnum % 2) ? e1000_lan_b : e1000_lan_a; 2624 else 2625 hw->lan_loc = e1000_lan_a; 2626 2627 /* flow control settings */ 2628 hw->fc_high_water = E1000_FC_HIGH_THRESH; 2629 hw->fc_low_water = E1000_FC_LOW_THRESH; 2630 hw->fc_pause_time = E1000_FC_PAUSE_TIME; 2631 hw->fc_send_xon = 1; 2632 2633 /* Media type - copper or fiber */ 2634 2635 if (hw->mac_type >= e1000_82543) { 2636 uint32_t status = E1000_READ_REG(hw, STATUS); 2637 2638 if (status & E1000_STATUS_TBIMODE) { 2639 DEBUGOUT("fiber interface\n"); 2640 hw->media_type = e1000_media_type_fiber; 2641 } else { 2642 DEBUGOUT("copper interface\n"); 2643 hw->media_type = e1000_media_type_copper; 2644 } 2645 } else { 2646 hw->media_type = e1000_media_type_fiber; 2647 } 2648 2649 if (hw->mac_type < e1000_82543) 2650 hw->report_tx_early = 0; 2651 else 2652 hw->report_tx_early = 1; 2653 2654 hw->tbi_compatibility_en = TRUE; 2655 #if 0 2656 hw->wait_autoneg_complete = FALSE; 2657 hw->adaptive_ifs = TRUE; 2658 2659 /* Copper options */ 2660 if (hw->media_type == e1000_media_type_copper) { 2661 hw->mdix = AUTO_ALL_MODES; 2662 hw->disable_polarity_correction = FALSE; 2663 } 2664 #endif 2665 return E1000_SUCCESS; 2666 } 2667 2668 void 2669 fill_rx(struct e1000_hw *hw) 2670 { 2671 struct e1000_rx_desc *rd; 2672 2673 rx_last = rx_tail; 2674 rd = rx_base + rx_tail; 2675 rx_tail = (rx_tail + 1) % 8; 2676 memset(rd, 0, 16); 2677 rd->buffer_addr = cpu_to_le64((u32) & packet); 2678 E1000_WRITE_REG(hw, RDT, rx_tail); 2679 } 2680 2681 /** 2682 * e1000_configure_tx - Configure 8254x Transmit Unit after Reset 2683 * @adapter: board private structure 2684 * 2685 * Configure the Tx unit of the MAC after a reset. 2686 **/ 2687 2688 static void 2689 e1000_configure_tx(struct e1000_hw *hw) 2690 { 2691 unsigned long ptr; 2692 unsigned long tctl; 2693 unsigned long tipg; 2694 2695 ptr = (u32) tx_pool; 2696 if (ptr & 0xf) 2697 ptr = (ptr + 0x10) & (~0xf); 2698 2699 tx_base = (typeof(tx_base)) ptr; 2700 2701 E1000_WRITE_REG(hw, TDBAL, (u32) tx_base); 2702 E1000_WRITE_REG(hw, TDBAH, 0); 2703 2704 E1000_WRITE_REG(hw, TDLEN, 128); 2705 2706 /* Setup the HW Tx Head and Tail descriptor pointers */ 2707 E1000_WRITE_REG(hw, TDH, 0); 2708 E1000_WRITE_REG(hw, TDT, 0); 2709 tx_tail = 0; 2710 2711 /* Set the default values for the Tx Inter Packet Gap timer */ 2712 switch (hw->mac_type) { 2713 case e1000_82542_rev2_0: 2714 case e1000_82542_rev2_1: 2715 tipg = DEFAULT_82542_TIPG_IPGT; 2716 tipg |= DEFAULT_82542_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 2717 tipg |= DEFAULT_82542_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 2718 break; 2719 default: 2720 if (hw->media_type == e1000_media_type_fiber) 2721 tipg = DEFAULT_82543_TIPG_IPGT_FIBER; 2722 else 2723 tipg = DEFAULT_82543_TIPG_IPGT_COPPER; 2724 tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 2725 tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 2726 } 2727 E1000_WRITE_REG(hw, TIPG, tipg); 2728 #if 0 2729 /* Set the Tx Interrupt Delay register */ 2730 E1000_WRITE_REG(hw, TIDV, adapter->tx_int_delay); 2731 if (hw->mac_type >= e1000_82540) 2732 E1000_WRITE_REG(hw, TADV, adapter->tx_abs_int_delay); 2733 #endif 2734 /* Program the Transmit Control Register */ 2735 tctl = E1000_READ_REG(hw, TCTL); 2736 tctl &= ~E1000_TCTL_CT; 2737 tctl |= E1000_TCTL_EN | E1000_TCTL_PSP | 2738 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); 2739 E1000_WRITE_REG(hw, TCTL, tctl); 2740 2741 e1000_config_collision_dist(hw); 2742 #if 0 2743 /* Setup Transmit Descriptor Settings for this adapter */ 2744 adapter->txd_cmd = E1000_TXD_CMD_IFCS | E1000_TXD_CMD_IDE; 2745 2746 if (adapter->hw.report_tx_early == 1) 2747 adapter->txd_cmd |= E1000_TXD_CMD_RS; 2748 else 2749 adapter->txd_cmd |= E1000_TXD_CMD_RPS; 2750 #endif 2751 } 2752 2753 /** 2754 * e1000_setup_rctl - configure the receive control register 2755 * @adapter: Board private structure 2756 **/ 2757 static void 2758 e1000_setup_rctl(struct e1000_hw *hw) 2759 { 2760 uint32_t rctl; 2761 2762 rctl = E1000_READ_REG(hw, RCTL); 2763 2764 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 2765 2766 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF; /* | 2767 (hw.mc_filter_type << E1000_RCTL_MO_SHIFT); */ 2768 2769 if (hw->tbi_compatibility_on == 1) 2770 rctl |= E1000_RCTL_SBP; 2771 else 2772 rctl &= ~E1000_RCTL_SBP; 2773 2774 rctl &= ~(E1000_RCTL_SZ_4096); 2775 #if 0 2776 switch (adapter->rx_buffer_len) { 2777 case E1000_RXBUFFER_2048: 2778 default: 2779 #endif 2780 rctl |= E1000_RCTL_SZ_2048; 2781 rctl &= ~(E1000_RCTL_BSEX | E1000_RCTL_LPE); 2782 #if 0 2783 break; 2784 case E1000_RXBUFFER_4096: 2785 rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX | E1000_RCTL_LPE; 2786 break; 2787 case E1000_RXBUFFER_8192: 2788 rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX | E1000_RCTL_LPE; 2789 break; 2790 case E1000_RXBUFFER_16384: 2791 rctl |= E1000_RCTL_SZ_16384 | E1000_RCTL_BSEX | E1000_RCTL_LPE; 2792 break; 2793 } 2794 #endif 2795 E1000_WRITE_REG(hw, RCTL, rctl); 2796 } 2797 2798 /** 2799 * e1000_configure_rx - Configure 8254x Receive Unit after Reset 2800 * @adapter: board private structure 2801 * 2802 * Configure the Rx unit of the MAC after a reset. 2803 **/ 2804 static void 2805 e1000_configure_rx(struct e1000_hw *hw) 2806 { 2807 unsigned long ptr; 2808 unsigned long rctl; 2809 #if 0 2810 unsigned long rxcsum; 2811 #endif 2812 rx_tail = 0; 2813 /* make sure receives are disabled while setting up the descriptors */ 2814 rctl = E1000_READ_REG(hw, RCTL); 2815 E1000_WRITE_REG(hw, RCTL, rctl & ~E1000_RCTL_EN); 2816 #if 0 2817 /* set the Receive Delay Timer Register */ 2818 2819 E1000_WRITE_REG(hw, RDTR, adapter->rx_int_delay); 2820 #endif 2821 if (hw->mac_type >= e1000_82540) { 2822 #if 0 2823 E1000_WRITE_REG(hw, RADV, adapter->rx_abs_int_delay); 2824 #endif 2825 /* Set the interrupt throttling rate. Value is calculated 2826 * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns) */ 2827 #define MAX_INTS_PER_SEC 8000 2828 #define DEFAULT_ITR 1000000000/(MAX_INTS_PER_SEC * 256) 2829 E1000_WRITE_REG(hw, ITR, DEFAULT_ITR); 2830 } 2831 2832 /* Setup the Base and Length of the Rx Descriptor Ring */ 2833 ptr = (u32) rx_pool; 2834 if (ptr & 0xf) 2835 ptr = (ptr + 0x10) & (~0xf); 2836 rx_base = (typeof(rx_base)) ptr; 2837 E1000_WRITE_REG(hw, RDBAL, (u32) rx_base); 2838 E1000_WRITE_REG(hw, RDBAH, 0); 2839 2840 E1000_WRITE_REG(hw, RDLEN, 128); 2841 2842 /* Setup the HW Rx Head and Tail Descriptor Pointers */ 2843 E1000_WRITE_REG(hw, RDH, 0); 2844 E1000_WRITE_REG(hw, RDT, 0); 2845 #if 0 2846 /* Enable 82543 Receive Checksum Offload for TCP and UDP */ 2847 if ((adapter->hw.mac_type >= e1000_82543) && (adapter->rx_csum == TRUE)) { 2848 rxcsum = E1000_READ_REG(hw, RXCSUM); 2849 rxcsum |= E1000_RXCSUM_TUOFL; 2850 E1000_WRITE_REG(hw, RXCSUM, rxcsum); 2851 } 2852 #endif 2853 /* Enable Receives */ 2854 2855 E1000_WRITE_REG(hw, RCTL, rctl); 2856 fill_rx(hw); 2857 } 2858 2859 /************************************************************************** 2860 POLL - Wait for a frame 2861 ***************************************************************************/ 2862 static int 2863 e1000_poll(struct eth_device *nic) 2864 { 2865 struct e1000_hw *hw = nic->priv; 2866 struct e1000_rx_desc *rd; 2867 /* return true if there's an ethernet packet ready to read */ 2868 rd = rx_base + rx_last; 2869 if (!(le32_to_cpu(rd->status)) & E1000_RXD_STAT_DD) 2870 return 0; 2871 /*DEBUGOUT("recv: packet len=%d \n", rd->length); */ 2872 NetReceive((uchar *)packet, le32_to_cpu(rd->length)); 2873 fill_rx(hw); 2874 return 1; 2875 } 2876 2877 /************************************************************************** 2878 TRANSMIT - Transmit a frame 2879 ***************************************************************************/ 2880 static int 2881 e1000_transmit(struct eth_device *nic, volatile void *packet, int length) 2882 { 2883 struct e1000_hw *hw = nic->priv; 2884 struct e1000_tx_desc *txp; 2885 int i = 0; 2886 2887 txp = tx_base + tx_tail; 2888 tx_tail = (tx_tail + 1) % 8; 2889 2890 txp->buffer_addr = cpu_to_le64(virt_to_bus(packet)); 2891 txp->lower.data = cpu_to_le32(E1000_TXD_CMD_RPS | E1000_TXD_CMD_EOP | 2892 E1000_TXD_CMD_IFCS | length); 2893 txp->upper.data = 0; 2894 E1000_WRITE_REG(hw, TDT, tx_tail); 2895 2896 while (!(le32_to_cpu(txp->upper.data) & E1000_TXD_STAT_DD)) { 2897 if (i++ > TOUT_LOOP) { 2898 DEBUGOUT("e1000: tx timeout\n"); 2899 return 0; 2900 } 2901 udelay(10); /* give the nic a chance to write to the register */ 2902 } 2903 return 1; 2904 } 2905 2906 /*reset function*/ 2907 static inline int 2908 e1000_reset(struct eth_device *nic) 2909 { 2910 struct e1000_hw *hw = nic->priv; 2911 2912 e1000_reset_hw(hw); 2913 if (hw->mac_type >= e1000_82544) { 2914 E1000_WRITE_REG(hw, WUC, 0); 2915 } 2916 return e1000_init_hw(nic); 2917 } 2918 2919 /************************************************************************** 2920 DISABLE - Turn off ethernet interface 2921 ***************************************************************************/ 2922 static void 2923 e1000_disable(struct eth_device *nic) 2924 { 2925 struct e1000_hw *hw = nic->priv; 2926 2927 /* Turn off the ethernet interface */ 2928 E1000_WRITE_REG(hw, RCTL, 0); 2929 E1000_WRITE_REG(hw, TCTL, 0); 2930 2931 /* Clear the transmit ring */ 2932 E1000_WRITE_REG(hw, TDH, 0); 2933 E1000_WRITE_REG(hw, TDT, 0); 2934 2935 /* Clear the receive ring */ 2936 E1000_WRITE_REG(hw, RDH, 0); 2937 E1000_WRITE_REG(hw, RDT, 0); 2938 2939 /* put the card in its initial state */ 2940 #if 0 2941 E1000_WRITE_REG(hw, CTRL, E1000_CTRL_RST); 2942 #endif 2943 mdelay(10); 2944 2945 } 2946 2947 /************************************************************************** 2948 INIT - set up ethernet interface(s) 2949 ***************************************************************************/ 2950 static int 2951 e1000_init(struct eth_device *nic, bd_t * bis) 2952 { 2953 struct e1000_hw *hw = nic->priv; 2954 int ret_val = 0; 2955 2956 ret_val = e1000_reset(nic); 2957 if (ret_val < 0) { 2958 if ((ret_val == -E1000_ERR_NOLINK) || 2959 (ret_val == -E1000_ERR_TIMEOUT)) { 2960 E1000_ERR("Valid Link not detected\n"); 2961 } else { 2962 E1000_ERR("Hardware Initialization Failed\n"); 2963 } 2964 return 0; 2965 } 2966 e1000_configure_tx(hw); 2967 e1000_setup_rctl(hw); 2968 e1000_configure_rx(hw); 2969 return 1; 2970 } 2971 2972 /************************************************************************** 2973 PROBE - Look for an adapter, this routine's visible to the outside 2974 You should omit the last argument struct pci_device * for a non-PCI NIC 2975 ***************************************************************************/ 2976 int 2977 e1000_initialize(bd_t * bis) 2978 { 2979 pci_dev_t devno; 2980 int card_number = 0; 2981 struct eth_device *nic = NULL; 2982 struct e1000_hw *hw = NULL; 2983 u32 iobase; 2984 int idx = 0; 2985 u32 PciCommandWord; 2986 2987 while (1) { /* Find PCI device(s) */ 2988 if ((devno = pci_find_devices(supported, idx++)) < 0) { 2989 break; 2990 } 2991 2992 pci_read_config_dword(devno, PCI_BASE_ADDRESS_0, &iobase); 2993 iobase &= ~0xf; /* Mask the bits that say "this is an io addr" */ 2994 DEBUGOUT("e1000#%d: iobase 0x%08x\n", card_number, iobase); 2995 2996 pci_write_config_dword(devno, PCI_COMMAND, 2997 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); 2998 /* Check if I/O accesses and Bus Mastering are enabled. */ 2999 pci_read_config_dword(devno, PCI_COMMAND, &PciCommandWord); 3000 if (!(PciCommandWord & PCI_COMMAND_MEMORY)) { 3001 printf("Error: Can not enable MEM access.\n"); 3002 continue; 3003 } else if (!(PciCommandWord & PCI_COMMAND_MASTER)) { 3004 printf("Error: Can not enable Bus Mastering.\n"); 3005 continue; 3006 } 3007 3008 nic = (struct eth_device *) malloc(sizeof (*nic)); 3009 hw = (struct e1000_hw *) malloc(sizeof (*hw)); 3010 hw->pdev = devno; 3011 nic->priv = hw; 3012 nic->iobase = bus_to_phys(devno, iobase); 3013 3014 sprintf(nic->name, "e1000#%d", card_number); 3015 3016 /* Are these variables needed? */ 3017 #if 0 3018 hw->fc = e1000_fc_none; 3019 hw->original_fc = e1000_fc_none; 3020 #else 3021 hw->fc = e1000_fc_default; 3022 hw->original_fc = e1000_fc_default; 3023 #endif 3024 hw->autoneg_failed = 0; 3025 hw->get_link_status = TRUE; 3026 hw->hw_addr = (typeof(hw->hw_addr)) iobase; 3027 hw->mac_type = e1000_undefined; 3028 3029 /* MAC and Phy settings */ 3030 if (e1000_sw_init(nic, card_number) < 0) { 3031 free(hw); 3032 free(nic); 3033 return 0; 3034 } 3035 #if !(defined(CONFIG_AP1000) || defined(CONFIG_MVBC_1G)) 3036 if (e1000_validate_eeprom_checksum(nic) < 0) { 3037 printf("The EEPROM Checksum Is Not Valid\n"); 3038 free(hw); 3039 free(nic); 3040 return 0; 3041 } 3042 #endif 3043 e1000_read_mac_addr(nic); 3044 3045 E1000_WRITE_REG(hw, PBA, E1000_DEFAULT_PBA); 3046 3047 printf("e1000: %02x:%02x:%02x:%02x:%02x:%02x\n", 3048 nic->enetaddr[0], nic->enetaddr[1], nic->enetaddr[2], 3049 nic->enetaddr[3], nic->enetaddr[4], nic->enetaddr[5]); 3050 3051 nic->init = e1000_init; 3052 nic->recv = e1000_poll; 3053 nic->send = e1000_transmit; 3054 nic->halt = e1000_disable; 3055 3056 eth_register(nic); 3057 3058 card_number++; 3059 } 3060 return 1; 3061 } 3062 3063 #endif 3064