xref: /openbmc/u-boot/drivers/net/e1000.c (revision 4101f687)
1 /**************************************************************************
2 Intel Pro 1000 for ppcboot/das-u-boot
3 Drivers are port from Intel's Linux driver e1000-4.3.15
4 and from Etherboot pro 1000 driver by mrakes at vivato dot net
5 tested on both gig copper and gig fiber boards
6 ***************************************************************************/
7 /*******************************************************************************
8 
9 
10   Copyright(c) 1999 - 2002 Intel Corporation. All rights reserved.
11 
12  * SPDX-License-Identifier:	GPL-2.0+
13 
14   Contact Information:
15   Linux NICS <linux.nics@intel.com>
16   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
17 
18 *******************************************************************************/
19 /*
20  *  Copyright (C) Archway Digital Solutions.
21  *
22  *  written by Chrsitopher Li <cli at arcyway dot com> or <chrisl at gnuchina dot org>
23  *  2/9/2002
24  *
25  *  Copyright (C) Linux Networx.
26  *  Massive upgrade to work with the new intel gigabit NICs.
27  *  <ebiederman at lnxi dot com>
28  *
29  *  Copyright 2011 Freescale Semiconductor, Inc.
30  */
31 
32 #include <common.h>
33 #include <dm.h>
34 #include <errno.h>
35 #include <memalign.h>
36 #include <pci.h>
37 #include "e1000.h"
38 
39 #define TOUT_LOOP   100000
40 
41 #ifdef CONFIG_DM_ETH
42 #define virt_to_bus(devno, v)	dm_pci_virt_to_mem(devno, (void *) (v))
43 #define bus_to_phys(devno, a)	dm_pci_mem_to_phys(devno, a)
44 #else
45 #define virt_to_bus(devno, v)	pci_virt_to_mem(devno, (void *) (v))
46 #define bus_to_phys(devno, a)	pci_mem_to_phys(devno, a)
47 #endif
48 
49 #define E1000_DEFAULT_PCI_PBA	0x00000030
50 #define E1000_DEFAULT_PCIE_PBA	0x000a0026
51 
52 /* NIC specific static variables go here */
53 
54 /* Intel i210 needs the DMA descriptor rings aligned to 128b */
55 #define E1000_BUFFER_ALIGN	128
56 
57 /*
58  * TODO(sjg@chromium.org): Even with driver model we share these buffers.
59  * Concurrent receiving on multiple active Ethernet devices will not work.
60  * Normally U-Boot does not support this anyway. To fix it in this driver,
61  * move these buffers and the tx/rx pointers to struct e1000_hw.
62  */
63 DEFINE_ALIGN_BUFFER(struct e1000_tx_desc, tx_base, 16, E1000_BUFFER_ALIGN);
64 DEFINE_ALIGN_BUFFER(struct e1000_rx_desc, rx_base, 16, E1000_BUFFER_ALIGN);
65 DEFINE_ALIGN_BUFFER(unsigned char, packet, 4096, E1000_BUFFER_ALIGN);
66 
67 static int tx_tail;
68 static int rx_tail, rx_last;
69 #ifdef CONFIG_DM_ETH
70 static int num_cards;	/* Number of E1000 devices seen so far */
71 #endif
72 
73 static struct pci_device_id e1000_supported[] = {
74 	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82542) },
75 	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82543GC_FIBER) },
76 	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82543GC_COPPER) },
77 	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544EI_COPPER) },
78 	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544EI_FIBER) },
79 	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544GC_COPPER) },
80 	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544GC_LOM) },
81 	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82540EM) },
82 	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545EM_COPPER) },
83 	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545GM_COPPER) },
84 	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_COPPER) },
85 	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545EM_FIBER) },
86 	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_FIBER) },
87 	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546GB_COPPER) },
88 	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82540EM_LOM) },
89 	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82541ER) },
90 	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82541GI_LF) },
91 	/* E1000 PCIe card */
92 	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_COPPER) },
93 	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_FIBER) },
94 	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES) },
95 	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_COPPER) },
96 	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571PT_QUAD_COPPER) },
97 	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_FIBER) },
98 	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_COPPER_LOWPROFILE) },
99 	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES_DUAL) },
100 	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES_QUAD) },
101 	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_COPPER) },
102 	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_FIBER) },
103 	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_SERDES) },
104 	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI) },
105 	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573E) },
106 	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573E_IAMT) },
107 	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573L) },
108 	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82574L) },
109 	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546GB_QUAD_COPPER_KSP3) },
110 	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_COPPER_DPT) },
111 	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_SERDES_DPT) },
112 	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_COPPER_SPT) },
113 	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_SERDES_SPT) },
114 	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_UNPROGRAMMED) },
115 	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I211_UNPROGRAMMED) },
116 	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_COPPER) },
117 	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I211_COPPER) },
118 	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_COPPER_FLASHLESS) },
119 	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_SERDES) },
120 	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_SERDES_FLASHLESS) },
121 	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_1000BASEKX) },
122 
123 	{}
124 };
125 
126 /* Function forward declarations */
127 static int e1000_setup_link(struct e1000_hw *hw);
128 static int e1000_setup_fiber_link(struct e1000_hw *hw);
129 static int e1000_setup_copper_link(struct e1000_hw *hw);
130 static int e1000_phy_setup_autoneg(struct e1000_hw *hw);
131 static void e1000_config_collision_dist(struct e1000_hw *hw);
132 static int e1000_config_mac_to_phy(struct e1000_hw *hw);
133 static int e1000_config_fc_after_link_up(struct e1000_hw *hw);
134 static int e1000_check_for_link(struct e1000_hw *hw);
135 static int e1000_wait_autoneg(struct e1000_hw *hw);
136 static int e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t * speed,
137 				       uint16_t * duplex);
138 static int e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr,
139 			      uint16_t * phy_data);
140 static int e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr,
141 			       uint16_t phy_data);
142 static int32_t e1000_phy_hw_reset(struct e1000_hw *hw);
143 static int e1000_phy_reset(struct e1000_hw *hw);
144 static int e1000_detect_gig_phy(struct e1000_hw *hw);
145 static void e1000_set_media_type(struct e1000_hw *hw);
146 
147 static int32_t e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask);
148 static void e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask);
149 static int32_t e1000_check_phy_reset_block(struct e1000_hw *hw);
150 
151 #ifndef CONFIG_E1000_NO_NVM
152 static void e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw);
153 static int32_t e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset,
154 		uint16_t words,
155 		uint16_t *data);
156 /******************************************************************************
157  * Raises the EEPROM's clock input.
158  *
159  * hw - Struct containing variables accessed by shared code
160  * eecd - EECD's current value
161  *****************************************************************************/
162 void e1000_raise_ee_clk(struct e1000_hw *hw, uint32_t * eecd)
163 {
164 	/* Raise the clock input to the EEPROM (by setting the SK bit), and then
165 	 * wait 50 microseconds.
166 	 */
167 	*eecd = *eecd | E1000_EECD_SK;
168 	E1000_WRITE_REG(hw, EECD, *eecd);
169 	E1000_WRITE_FLUSH(hw);
170 	udelay(50);
171 }
172 
173 /******************************************************************************
174  * Lowers the EEPROM's clock input.
175  *
176  * hw - Struct containing variables accessed by shared code
177  * eecd - EECD's current value
178  *****************************************************************************/
179 void e1000_lower_ee_clk(struct e1000_hw *hw, uint32_t * eecd)
180 {
181 	/* Lower the clock input to the EEPROM (by clearing the SK bit), and then
182 	 * wait 50 microseconds.
183 	 */
184 	*eecd = *eecd & ~E1000_EECD_SK;
185 	E1000_WRITE_REG(hw, EECD, *eecd);
186 	E1000_WRITE_FLUSH(hw);
187 	udelay(50);
188 }
189 
190 /******************************************************************************
191  * Shift data bits out to the EEPROM.
192  *
193  * hw - Struct containing variables accessed by shared code
194  * data - data to send to the EEPROM
195  * count - number of bits to shift out
196  *****************************************************************************/
197 static void
198 e1000_shift_out_ee_bits(struct e1000_hw *hw, uint16_t data, uint16_t count)
199 {
200 	uint32_t eecd;
201 	uint32_t mask;
202 
203 	/* We need to shift "count" bits out to the EEPROM. So, value in the
204 	 * "data" parameter will be shifted out to the EEPROM one bit at a time.
205 	 * In order to do this, "data" must be broken down into bits.
206 	 */
207 	mask = 0x01 << (count - 1);
208 	eecd = E1000_READ_REG(hw, EECD);
209 	eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
210 	do {
211 		/* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1",
212 		 * and then raising and then lowering the clock (the SK bit controls
213 		 * the clock input to the EEPROM).  A "0" is shifted out to the EEPROM
214 		 * by setting "DI" to "0" and then raising and then lowering the clock.
215 		 */
216 		eecd &= ~E1000_EECD_DI;
217 
218 		if (data & mask)
219 			eecd |= E1000_EECD_DI;
220 
221 		E1000_WRITE_REG(hw, EECD, eecd);
222 		E1000_WRITE_FLUSH(hw);
223 
224 		udelay(50);
225 
226 		e1000_raise_ee_clk(hw, &eecd);
227 		e1000_lower_ee_clk(hw, &eecd);
228 
229 		mask = mask >> 1;
230 
231 	} while (mask);
232 
233 	/* We leave the "DI" bit set to "0" when we leave this routine. */
234 	eecd &= ~E1000_EECD_DI;
235 	E1000_WRITE_REG(hw, EECD, eecd);
236 }
237 
238 /******************************************************************************
239  * Shift data bits in from the EEPROM
240  *
241  * hw - Struct containing variables accessed by shared code
242  *****************************************************************************/
243 static uint16_t
244 e1000_shift_in_ee_bits(struct e1000_hw *hw, uint16_t count)
245 {
246 	uint32_t eecd;
247 	uint32_t i;
248 	uint16_t data;
249 
250 	/* In order to read a register from the EEPROM, we need to shift 'count'
251 	 * bits in from the EEPROM. Bits are "shifted in" by raising the clock
252 	 * input to the EEPROM (setting the SK bit), and then reading the
253 	 * value of the "DO" bit.  During this "shifting in" process the
254 	 * "DI" bit should always be clear.
255 	 */
256 
257 	eecd = E1000_READ_REG(hw, EECD);
258 
259 	eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
260 	data = 0;
261 
262 	for (i = 0; i < count; i++) {
263 		data = data << 1;
264 		e1000_raise_ee_clk(hw, &eecd);
265 
266 		eecd = E1000_READ_REG(hw, EECD);
267 
268 		eecd &= ~(E1000_EECD_DI);
269 		if (eecd & E1000_EECD_DO)
270 			data |= 1;
271 
272 		e1000_lower_ee_clk(hw, &eecd);
273 	}
274 
275 	return data;
276 }
277 
278 /******************************************************************************
279  * Returns EEPROM to a "standby" state
280  *
281  * hw - Struct containing variables accessed by shared code
282  *****************************************************************************/
283 void e1000_standby_eeprom(struct e1000_hw *hw)
284 {
285 	struct e1000_eeprom_info *eeprom = &hw->eeprom;
286 	uint32_t eecd;
287 
288 	eecd = E1000_READ_REG(hw, EECD);
289 
290 	if (eeprom->type == e1000_eeprom_microwire) {
291 		eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
292 		E1000_WRITE_REG(hw, EECD, eecd);
293 		E1000_WRITE_FLUSH(hw);
294 		udelay(eeprom->delay_usec);
295 
296 		/* Clock high */
297 		eecd |= E1000_EECD_SK;
298 		E1000_WRITE_REG(hw, EECD, eecd);
299 		E1000_WRITE_FLUSH(hw);
300 		udelay(eeprom->delay_usec);
301 
302 		/* Select EEPROM */
303 		eecd |= E1000_EECD_CS;
304 		E1000_WRITE_REG(hw, EECD, eecd);
305 		E1000_WRITE_FLUSH(hw);
306 		udelay(eeprom->delay_usec);
307 
308 		/* Clock low */
309 		eecd &= ~E1000_EECD_SK;
310 		E1000_WRITE_REG(hw, EECD, eecd);
311 		E1000_WRITE_FLUSH(hw);
312 		udelay(eeprom->delay_usec);
313 	} else if (eeprom->type == e1000_eeprom_spi) {
314 		/* Toggle CS to flush commands */
315 		eecd |= E1000_EECD_CS;
316 		E1000_WRITE_REG(hw, EECD, eecd);
317 		E1000_WRITE_FLUSH(hw);
318 		udelay(eeprom->delay_usec);
319 		eecd &= ~E1000_EECD_CS;
320 		E1000_WRITE_REG(hw, EECD, eecd);
321 		E1000_WRITE_FLUSH(hw);
322 		udelay(eeprom->delay_usec);
323 	}
324 }
325 
326 /***************************************************************************
327 * Description:     Determines if the onboard NVM is FLASH or EEPROM.
328 *
329 * hw - Struct containing variables accessed by shared code
330 ****************************************************************************/
331 static bool e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw)
332 {
333 	uint32_t eecd = 0;
334 
335 	DEBUGFUNC();
336 
337 	if (hw->mac_type == e1000_ich8lan)
338 		return false;
339 
340 	if (hw->mac_type == e1000_82573 || hw->mac_type == e1000_82574) {
341 		eecd = E1000_READ_REG(hw, EECD);
342 
343 		/* Isolate bits 15 & 16 */
344 		eecd = ((eecd >> 15) & 0x03);
345 
346 		/* If both bits are set, device is Flash type */
347 		if (eecd == 0x03)
348 			return false;
349 	}
350 	return true;
351 }
352 
353 /******************************************************************************
354  * Prepares EEPROM for access
355  *
356  * hw - Struct containing variables accessed by shared code
357  *
358  * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This
359  * function should be called before issuing a command to the EEPROM.
360  *****************************************************************************/
361 int32_t e1000_acquire_eeprom(struct e1000_hw *hw)
362 {
363 	struct e1000_eeprom_info *eeprom = &hw->eeprom;
364 	uint32_t eecd, i = 0;
365 
366 	DEBUGFUNC();
367 
368 	if (e1000_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM))
369 		return -E1000_ERR_SWFW_SYNC;
370 	eecd = E1000_READ_REG(hw, EECD);
371 
372 	if (hw->mac_type != e1000_82573 && hw->mac_type != e1000_82574) {
373 		/* Request EEPROM Access */
374 		if (hw->mac_type > e1000_82544) {
375 			eecd |= E1000_EECD_REQ;
376 			E1000_WRITE_REG(hw, EECD, eecd);
377 			eecd = E1000_READ_REG(hw, EECD);
378 			while ((!(eecd & E1000_EECD_GNT)) &&
379 				(i < E1000_EEPROM_GRANT_ATTEMPTS)) {
380 				i++;
381 				udelay(5);
382 				eecd = E1000_READ_REG(hw, EECD);
383 			}
384 			if (!(eecd & E1000_EECD_GNT)) {
385 				eecd &= ~E1000_EECD_REQ;
386 				E1000_WRITE_REG(hw, EECD, eecd);
387 				DEBUGOUT("Could not acquire EEPROM grant\n");
388 				return -E1000_ERR_EEPROM;
389 			}
390 		}
391 	}
392 
393 	/* Setup EEPROM for Read/Write */
394 
395 	if (eeprom->type == e1000_eeprom_microwire) {
396 		/* Clear SK and DI */
397 		eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);
398 		E1000_WRITE_REG(hw, EECD, eecd);
399 
400 		/* Set CS */
401 		eecd |= E1000_EECD_CS;
402 		E1000_WRITE_REG(hw, EECD, eecd);
403 	} else if (eeprom->type == e1000_eeprom_spi) {
404 		/* Clear SK and CS */
405 		eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
406 		E1000_WRITE_REG(hw, EECD, eecd);
407 		udelay(1);
408 	}
409 
410 	return E1000_SUCCESS;
411 }
412 
413 /******************************************************************************
414  * Sets up eeprom variables in the hw struct.  Must be called after mac_type
415  * is configured.  Additionally, if this is ICH8, the flash controller GbE
416  * registers must be mapped, or this will crash.
417  *
418  * hw - Struct containing variables accessed by shared code
419  *****************************************************************************/
420 static int32_t e1000_init_eeprom_params(struct e1000_hw *hw)
421 {
422 	struct e1000_eeprom_info *eeprom = &hw->eeprom;
423 	uint32_t eecd;
424 	int32_t ret_val = E1000_SUCCESS;
425 	uint16_t eeprom_size;
426 
427 	if (hw->mac_type == e1000_igb)
428 		eecd = E1000_READ_REG(hw, I210_EECD);
429 	else
430 		eecd = E1000_READ_REG(hw, EECD);
431 
432 	DEBUGFUNC();
433 
434 	switch (hw->mac_type) {
435 	case e1000_82542_rev2_0:
436 	case e1000_82542_rev2_1:
437 	case e1000_82543:
438 	case e1000_82544:
439 		eeprom->type = e1000_eeprom_microwire;
440 		eeprom->word_size = 64;
441 		eeprom->opcode_bits = 3;
442 		eeprom->address_bits = 6;
443 		eeprom->delay_usec = 50;
444 		eeprom->use_eerd = false;
445 		eeprom->use_eewr = false;
446 	break;
447 	case e1000_82540:
448 	case e1000_82545:
449 	case e1000_82545_rev_3:
450 	case e1000_82546:
451 	case e1000_82546_rev_3:
452 		eeprom->type = e1000_eeprom_microwire;
453 		eeprom->opcode_bits = 3;
454 		eeprom->delay_usec = 50;
455 		if (eecd & E1000_EECD_SIZE) {
456 			eeprom->word_size = 256;
457 			eeprom->address_bits = 8;
458 		} else {
459 			eeprom->word_size = 64;
460 			eeprom->address_bits = 6;
461 		}
462 		eeprom->use_eerd = false;
463 		eeprom->use_eewr = false;
464 		break;
465 	case e1000_82541:
466 	case e1000_82541_rev_2:
467 	case e1000_82547:
468 	case e1000_82547_rev_2:
469 		if (eecd & E1000_EECD_TYPE) {
470 			eeprom->type = e1000_eeprom_spi;
471 			eeprom->opcode_bits = 8;
472 			eeprom->delay_usec = 1;
473 			if (eecd & E1000_EECD_ADDR_BITS) {
474 				eeprom->page_size = 32;
475 				eeprom->address_bits = 16;
476 			} else {
477 				eeprom->page_size = 8;
478 				eeprom->address_bits = 8;
479 			}
480 		} else {
481 			eeprom->type = e1000_eeprom_microwire;
482 			eeprom->opcode_bits = 3;
483 			eeprom->delay_usec = 50;
484 			if (eecd & E1000_EECD_ADDR_BITS) {
485 				eeprom->word_size = 256;
486 				eeprom->address_bits = 8;
487 			} else {
488 				eeprom->word_size = 64;
489 				eeprom->address_bits = 6;
490 			}
491 		}
492 		eeprom->use_eerd = false;
493 		eeprom->use_eewr = false;
494 		break;
495 	case e1000_82571:
496 	case e1000_82572:
497 		eeprom->type = e1000_eeprom_spi;
498 		eeprom->opcode_bits = 8;
499 		eeprom->delay_usec = 1;
500 		if (eecd & E1000_EECD_ADDR_BITS) {
501 			eeprom->page_size = 32;
502 			eeprom->address_bits = 16;
503 		} else {
504 			eeprom->page_size = 8;
505 			eeprom->address_bits = 8;
506 		}
507 		eeprom->use_eerd = false;
508 		eeprom->use_eewr = false;
509 		break;
510 	case e1000_82573:
511 	case e1000_82574:
512 		eeprom->type = e1000_eeprom_spi;
513 		eeprom->opcode_bits = 8;
514 		eeprom->delay_usec = 1;
515 		if (eecd & E1000_EECD_ADDR_BITS) {
516 			eeprom->page_size = 32;
517 			eeprom->address_bits = 16;
518 		} else {
519 			eeprom->page_size = 8;
520 			eeprom->address_bits = 8;
521 		}
522 		if (e1000_is_onboard_nvm_eeprom(hw) == false) {
523 			eeprom->use_eerd = true;
524 			eeprom->use_eewr = true;
525 
526 			eeprom->type = e1000_eeprom_flash;
527 			eeprom->word_size = 2048;
528 
529 		/* Ensure that the Autonomous FLASH update bit is cleared due to
530 		 * Flash update issue on parts which use a FLASH for NVM. */
531 			eecd &= ~E1000_EECD_AUPDEN;
532 			E1000_WRITE_REG(hw, EECD, eecd);
533 		}
534 		break;
535 	case e1000_80003es2lan:
536 		eeprom->type = e1000_eeprom_spi;
537 		eeprom->opcode_bits = 8;
538 		eeprom->delay_usec = 1;
539 		if (eecd & E1000_EECD_ADDR_BITS) {
540 			eeprom->page_size = 32;
541 			eeprom->address_bits = 16;
542 		} else {
543 			eeprom->page_size = 8;
544 			eeprom->address_bits = 8;
545 		}
546 		eeprom->use_eerd = true;
547 		eeprom->use_eewr = false;
548 		break;
549 	case e1000_igb:
550 		/* i210 has 4k of iNVM mapped as EEPROM */
551 		eeprom->type = e1000_eeprom_invm;
552 		eeprom->opcode_bits = 8;
553 		eeprom->delay_usec = 1;
554 		eeprom->page_size = 32;
555 		eeprom->address_bits = 16;
556 		eeprom->use_eerd = true;
557 		eeprom->use_eewr = false;
558 		break;
559 	default:
560 		break;
561 	}
562 
563 	if (eeprom->type == e1000_eeprom_spi ||
564 	    eeprom->type == e1000_eeprom_invm) {
565 		/* eeprom_size will be an enum [0..8] that maps
566 		 * to eeprom sizes 128B to
567 		 * 32KB (incremented by powers of 2).
568 		 */
569 		if (hw->mac_type <= e1000_82547_rev_2) {
570 			/* Set to default value for initial eeprom read. */
571 			eeprom->word_size = 64;
572 			ret_val = e1000_read_eeprom(hw, EEPROM_CFG, 1,
573 					&eeprom_size);
574 			if (ret_val)
575 				return ret_val;
576 			eeprom_size = (eeprom_size & EEPROM_SIZE_MASK)
577 				>> EEPROM_SIZE_SHIFT;
578 			/* 256B eeprom size was not supported in earlier
579 			 * hardware, so we bump eeprom_size up one to
580 			 * ensure that "1" (which maps to 256B) is never
581 			 * the result used in the shifting logic below. */
582 			if (eeprom_size)
583 				eeprom_size++;
584 		} else {
585 			eeprom_size = (uint16_t)((eecd &
586 				E1000_EECD_SIZE_EX_MASK) >>
587 				E1000_EECD_SIZE_EX_SHIFT);
588 		}
589 
590 		eeprom->word_size = 1 << (eeprom_size + EEPROM_WORD_SIZE_SHIFT);
591 	}
592 	return ret_val;
593 }
594 
595 /******************************************************************************
596  * Polls the status bit (bit 1) of the EERD to determine when the read is done.
597  *
598  * hw - Struct containing variables accessed by shared code
599  *****************************************************************************/
600 static int32_t
601 e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd)
602 {
603 	uint32_t attempts = 100000;
604 	uint32_t i, reg = 0;
605 	int32_t done = E1000_ERR_EEPROM;
606 
607 	for (i = 0; i < attempts; i++) {
608 		if (eerd == E1000_EEPROM_POLL_READ) {
609 			if (hw->mac_type == e1000_igb)
610 				reg = E1000_READ_REG(hw, I210_EERD);
611 			else
612 				reg = E1000_READ_REG(hw, EERD);
613 		} else {
614 			if (hw->mac_type == e1000_igb)
615 				reg = E1000_READ_REG(hw, I210_EEWR);
616 			else
617 				reg = E1000_READ_REG(hw, EEWR);
618 		}
619 
620 		if (reg & E1000_EEPROM_RW_REG_DONE) {
621 			done = E1000_SUCCESS;
622 			break;
623 		}
624 		udelay(5);
625 	}
626 
627 	return done;
628 }
629 
630 /******************************************************************************
631  * Reads a 16 bit word from the EEPROM using the EERD register.
632  *
633  * hw - Struct containing variables accessed by shared code
634  * offset - offset of  word in the EEPROM to read
635  * data - word read from the EEPROM
636  * words - number of words to read
637  *****************************************************************************/
638 static int32_t
639 e1000_read_eeprom_eerd(struct e1000_hw *hw,
640 			uint16_t offset,
641 			uint16_t words,
642 			uint16_t *data)
643 {
644 	uint32_t i, eerd = 0;
645 	int32_t error = 0;
646 
647 	for (i = 0; i < words; i++) {
648 		eerd = ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) +
649 			E1000_EEPROM_RW_REG_START;
650 
651 		if (hw->mac_type == e1000_igb)
652 			E1000_WRITE_REG(hw, I210_EERD, eerd);
653 		else
654 			E1000_WRITE_REG(hw, EERD, eerd);
655 
656 		error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_READ);
657 
658 		if (error)
659 			break;
660 
661 		if (hw->mac_type == e1000_igb) {
662 			data[i] = (E1000_READ_REG(hw, I210_EERD) >>
663 				E1000_EEPROM_RW_REG_DATA);
664 		} else {
665 			data[i] = (E1000_READ_REG(hw, EERD) >>
666 				E1000_EEPROM_RW_REG_DATA);
667 		}
668 
669 	}
670 
671 	return error;
672 }
673 
674 void e1000_release_eeprom(struct e1000_hw *hw)
675 {
676 	uint32_t eecd;
677 
678 	DEBUGFUNC();
679 
680 	eecd = E1000_READ_REG(hw, EECD);
681 
682 	if (hw->eeprom.type == e1000_eeprom_spi) {
683 		eecd |= E1000_EECD_CS;  /* Pull CS high */
684 		eecd &= ~E1000_EECD_SK; /* Lower SCK */
685 
686 		E1000_WRITE_REG(hw, EECD, eecd);
687 
688 		udelay(hw->eeprom.delay_usec);
689 	} else if (hw->eeprom.type == e1000_eeprom_microwire) {
690 		/* cleanup eeprom */
691 
692 		/* CS on Microwire is active-high */
693 		eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
694 
695 		E1000_WRITE_REG(hw, EECD, eecd);
696 
697 		/* Rising edge of clock */
698 		eecd |= E1000_EECD_SK;
699 		E1000_WRITE_REG(hw, EECD, eecd);
700 		E1000_WRITE_FLUSH(hw);
701 		udelay(hw->eeprom.delay_usec);
702 
703 		/* Falling edge of clock */
704 		eecd &= ~E1000_EECD_SK;
705 		E1000_WRITE_REG(hw, EECD, eecd);
706 		E1000_WRITE_FLUSH(hw);
707 		udelay(hw->eeprom.delay_usec);
708 	}
709 
710 	/* Stop requesting EEPROM access */
711 	if (hw->mac_type > e1000_82544) {
712 		eecd &= ~E1000_EECD_REQ;
713 		E1000_WRITE_REG(hw, EECD, eecd);
714 	}
715 
716 	e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM);
717 }
718 
719 /******************************************************************************
720  * Reads a 16 bit word from the EEPROM.
721  *
722  * hw - Struct containing variables accessed by shared code
723  *****************************************************************************/
724 static int32_t
725 e1000_spi_eeprom_ready(struct e1000_hw *hw)
726 {
727 	uint16_t retry_count = 0;
728 	uint8_t spi_stat_reg;
729 
730 	DEBUGFUNC();
731 
732 	/* Read "Status Register" repeatedly until the LSB is cleared.  The
733 	 * EEPROM will signal that the command has been completed by clearing
734 	 * bit 0 of the internal status register.  If it's not cleared within
735 	 * 5 milliseconds, then error out.
736 	 */
737 	retry_count = 0;
738 	do {
739 		e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI,
740 			hw->eeprom.opcode_bits);
741 		spi_stat_reg = (uint8_t)e1000_shift_in_ee_bits(hw, 8);
742 		if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI))
743 			break;
744 
745 		udelay(5);
746 		retry_count += 5;
747 
748 		e1000_standby_eeprom(hw);
749 	} while (retry_count < EEPROM_MAX_RETRY_SPI);
750 
751 	/* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and
752 	 * only 0-5mSec on 5V devices)
753 	 */
754 	if (retry_count >= EEPROM_MAX_RETRY_SPI) {
755 		DEBUGOUT("SPI EEPROM Status error\n");
756 		return -E1000_ERR_EEPROM;
757 	}
758 
759 	return E1000_SUCCESS;
760 }
761 
762 /******************************************************************************
763  * Reads a 16 bit word from the EEPROM.
764  *
765  * hw - Struct containing variables accessed by shared code
766  * offset - offset of  word in the EEPROM to read
767  * data - word read from the EEPROM
768  *****************************************************************************/
769 static int32_t
770 e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset,
771 		uint16_t words, uint16_t *data)
772 {
773 	struct e1000_eeprom_info *eeprom = &hw->eeprom;
774 	uint32_t i = 0;
775 
776 	DEBUGFUNC();
777 
778 	/* If eeprom is not yet detected, do so now */
779 	if (eeprom->word_size == 0)
780 		e1000_init_eeprom_params(hw);
781 
782 	/* A check for invalid values:  offset too large, too many words,
783 	 * and not enough words.
784 	 */
785 	if ((offset >= eeprom->word_size) ||
786 		(words > eeprom->word_size - offset) ||
787 		(words == 0)) {
788 		DEBUGOUT("\"words\" parameter out of bounds."
789 			"Words = %d, size = %d\n", offset, eeprom->word_size);
790 		return -E1000_ERR_EEPROM;
791 	}
792 
793 	/* EEPROM's that don't use EERD to read require us to bit-bang the SPI
794 	 * directly. In this case, we need to acquire the EEPROM so that
795 	 * FW or other port software does not interrupt.
796 	 */
797 	if (e1000_is_onboard_nvm_eeprom(hw) == true &&
798 		hw->eeprom.use_eerd == false) {
799 
800 		/* Prepare the EEPROM for bit-bang reading */
801 		if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
802 			return -E1000_ERR_EEPROM;
803 	}
804 
805 	/* Eerd register EEPROM access requires no eeprom aquire/release */
806 	if (eeprom->use_eerd == true)
807 		return e1000_read_eeprom_eerd(hw, offset, words, data);
808 
809 	/* Set up the SPI or Microwire EEPROM for bit-bang reading.  We have
810 	 * acquired the EEPROM at this point, so any returns should relase it */
811 	if (eeprom->type == e1000_eeprom_spi) {
812 		uint16_t word_in;
813 		uint8_t read_opcode = EEPROM_READ_OPCODE_SPI;
814 
815 		if (e1000_spi_eeprom_ready(hw)) {
816 			e1000_release_eeprom(hw);
817 			return -E1000_ERR_EEPROM;
818 		}
819 
820 		e1000_standby_eeprom(hw);
821 
822 		/* Some SPI eeproms use the 8th address bit embedded in
823 		 * the opcode */
824 		if ((eeprom->address_bits == 8) && (offset >= 128))
825 			read_opcode |= EEPROM_A8_OPCODE_SPI;
826 
827 		/* Send the READ command (opcode + addr)  */
828 		e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits);
829 		e1000_shift_out_ee_bits(hw, (uint16_t)(offset*2),
830 				eeprom->address_bits);
831 
832 		/* Read the data.  The address of the eeprom internally
833 		 * increments with each byte (spi) being read, saving on the
834 		 * overhead of eeprom setup and tear-down.  The address
835 		 * counter will roll over if reading beyond the size of
836 		 * the eeprom, thus allowing the entire memory to be read
837 		 * starting from any offset. */
838 		for (i = 0; i < words; i++) {
839 			word_in = e1000_shift_in_ee_bits(hw, 16);
840 			data[i] = (word_in >> 8) | (word_in << 8);
841 		}
842 	} else if (eeprom->type == e1000_eeprom_microwire) {
843 		for (i = 0; i < words; i++) {
844 			/* Send the READ command (opcode + addr)  */
845 			e1000_shift_out_ee_bits(hw,
846 				EEPROM_READ_OPCODE_MICROWIRE,
847 				eeprom->opcode_bits);
848 			e1000_shift_out_ee_bits(hw, (uint16_t)(offset + i),
849 				eeprom->address_bits);
850 
851 			/* Read the data.  For microwire, each word requires
852 			 * the overhead of eeprom setup and tear-down. */
853 			data[i] = e1000_shift_in_ee_bits(hw, 16);
854 			e1000_standby_eeprom(hw);
855 		}
856 	}
857 
858 	/* End this read operation */
859 	e1000_release_eeprom(hw);
860 
861 	return E1000_SUCCESS;
862 }
863 
864 /******************************************************************************
865  * Verifies that the EEPROM has a valid checksum
866  *
867  * hw - Struct containing variables accessed by shared code
868  *
869  * Reads the first 64 16 bit words of the EEPROM and sums the values read.
870  * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is
871  * valid.
872  *****************************************************************************/
873 static int e1000_validate_eeprom_checksum(struct e1000_hw *hw)
874 {
875 	uint16_t i, checksum, checksum_reg, *buf;
876 
877 	DEBUGFUNC();
878 
879 	/* Allocate a temporary buffer */
880 	buf = malloc(sizeof(buf[0]) * (EEPROM_CHECKSUM_REG + 1));
881 	if (!buf) {
882 		E1000_ERR(hw, "Unable to allocate EEPROM buffer!\n");
883 		return -E1000_ERR_EEPROM;
884 	}
885 
886 	/* Read the EEPROM */
887 	if (e1000_read_eeprom(hw, 0, EEPROM_CHECKSUM_REG + 1, buf) < 0) {
888 		E1000_ERR(hw, "Unable to read EEPROM!\n");
889 		return -E1000_ERR_EEPROM;
890 	}
891 
892 	/* Compute the checksum */
893 	checksum = 0;
894 	for (i = 0; i < EEPROM_CHECKSUM_REG; i++)
895 		checksum += buf[i];
896 	checksum = ((uint16_t)EEPROM_SUM) - checksum;
897 	checksum_reg = buf[i];
898 
899 	/* Verify it! */
900 	if (checksum == checksum_reg)
901 		return 0;
902 
903 	/* Hrm, verification failed, print an error */
904 	E1000_ERR(hw, "EEPROM checksum is incorrect!\n");
905 	E1000_ERR(hw, "  ...register was 0x%04hx, calculated 0x%04hx\n",
906 		  checksum_reg, checksum);
907 
908 	return -E1000_ERR_EEPROM;
909 }
910 #endif /* CONFIG_E1000_NO_NVM */
911 
912 /*****************************************************************************
913  * Set PHY to class A mode
914  * Assumes the following operations will follow to enable the new class mode.
915  *  1. Do a PHY soft reset
916  *  2. Restart auto-negotiation or force link.
917  *
918  * hw - Struct containing variables accessed by shared code
919  ****************************************************************************/
920 static int32_t
921 e1000_set_phy_mode(struct e1000_hw *hw)
922 {
923 #ifndef CONFIG_E1000_NO_NVM
924 	int32_t ret_val;
925 	uint16_t eeprom_data;
926 
927 	DEBUGFUNC();
928 
929 	if ((hw->mac_type == e1000_82545_rev_3) &&
930 		(hw->media_type == e1000_media_type_copper)) {
931 		ret_val = e1000_read_eeprom(hw, EEPROM_PHY_CLASS_WORD,
932 				1, &eeprom_data);
933 		if (ret_val)
934 			return ret_val;
935 
936 		if ((eeprom_data != EEPROM_RESERVED_WORD) &&
937 			(eeprom_data & EEPROM_PHY_CLASS_A)) {
938 			ret_val = e1000_write_phy_reg(hw,
939 					M88E1000_PHY_PAGE_SELECT, 0x000B);
940 			if (ret_val)
941 				return ret_val;
942 			ret_val = e1000_write_phy_reg(hw,
943 					M88E1000_PHY_GEN_CONTROL, 0x8104);
944 			if (ret_val)
945 				return ret_val;
946 
947 			hw->phy_reset_disable = false;
948 		}
949 	}
950 #endif
951 	return E1000_SUCCESS;
952 }
953 
954 #ifndef CONFIG_E1000_NO_NVM
955 /***************************************************************************
956  *
957  * Obtaining software semaphore bit (SMBI) before resetting PHY.
958  *
959  * hw: Struct containing variables accessed by shared code
960  *
961  * returns: - E1000_ERR_RESET if fail to obtain semaphore.
962  *            E1000_SUCCESS at any other case.
963  *
964  ***************************************************************************/
965 static int32_t
966 e1000_get_software_semaphore(struct e1000_hw *hw)
967 {
968 	 int32_t timeout = hw->eeprom.word_size + 1;
969 	 uint32_t swsm;
970 
971 	DEBUGFUNC();
972 
973 	if (hw->mac_type != e1000_80003es2lan)
974 		return E1000_SUCCESS;
975 
976 	while (timeout) {
977 		swsm = E1000_READ_REG(hw, SWSM);
978 		/* If SMBI bit cleared, it is now set and we hold
979 		 * the semaphore */
980 		if (!(swsm & E1000_SWSM_SMBI))
981 			break;
982 		mdelay(1);
983 		timeout--;
984 	}
985 
986 	if (!timeout) {
987 		DEBUGOUT("Driver can't access device - SMBI bit is set.\n");
988 		return -E1000_ERR_RESET;
989 	}
990 
991 	return E1000_SUCCESS;
992 }
993 #endif
994 
995 /***************************************************************************
996  * This function clears HW semaphore bits.
997  *
998  * hw: Struct containing variables accessed by shared code
999  *
1000  * returns: - None.
1001  *
1002  ***************************************************************************/
1003 static void
1004 e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw)
1005 {
1006 #ifndef CONFIG_E1000_NO_NVM
1007 	 uint32_t swsm;
1008 
1009 	DEBUGFUNC();
1010 
1011 	if (!hw->eeprom_semaphore_present)
1012 		return;
1013 
1014 	swsm = E1000_READ_REG(hw, SWSM);
1015 	if (hw->mac_type == e1000_80003es2lan) {
1016 		/* Release both semaphores. */
1017 		swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
1018 	} else
1019 		swsm &= ~(E1000_SWSM_SWESMBI);
1020 	E1000_WRITE_REG(hw, SWSM, swsm);
1021 #endif
1022 }
1023 
1024 /***************************************************************************
1025  *
1026  * Using the combination of SMBI and SWESMBI semaphore bits when resetting
1027  * adapter or Eeprom access.
1028  *
1029  * hw: Struct containing variables accessed by shared code
1030  *
1031  * returns: - E1000_ERR_EEPROM if fail to access EEPROM.
1032  *            E1000_SUCCESS at any other case.
1033  *
1034  ***************************************************************************/
1035 static int32_t
1036 e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw)
1037 {
1038 #ifndef CONFIG_E1000_NO_NVM
1039 	int32_t timeout;
1040 	uint32_t swsm;
1041 
1042 	DEBUGFUNC();
1043 
1044 	if (!hw->eeprom_semaphore_present)
1045 		return E1000_SUCCESS;
1046 
1047 	if (hw->mac_type == e1000_80003es2lan) {
1048 		/* Get the SW semaphore. */
1049 		if (e1000_get_software_semaphore(hw) != E1000_SUCCESS)
1050 			return -E1000_ERR_EEPROM;
1051 	}
1052 
1053 	/* Get the FW semaphore. */
1054 	timeout = hw->eeprom.word_size + 1;
1055 	while (timeout) {
1056 		swsm = E1000_READ_REG(hw, SWSM);
1057 		swsm |= E1000_SWSM_SWESMBI;
1058 		E1000_WRITE_REG(hw, SWSM, swsm);
1059 		/* if we managed to set the bit we got the semaphore. */
1060 		swsm = E1000_READ_REG(hw, SWSM);
1061 		if (swsm & E1000_SWSM_SWESMBI)
1062 			break;
1063 
1064 		udelay(50);
1065 		timeout--;
1066 	}
1067 
1068 	if (!timeout) {
1069 		/* Release semaphores */
1070 		e1000_put_hw_eeprom_semaphore(hw);
1071 		DEBUGOUT("Driver can't access the Eeprom - "
1072 				"SWESMBI bit is set.\n");
1073 		return -E1000_ERR_EEPROM;
1074 	}
1075 #endif
1076 	return E1000_SUCCESS;
1077 }
1078 
1079 /* Take ownership of the PHY */
1080 static int32_t
1081 e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask)
1082 {
1083 	uint32_t swfw_sync = 0;
1084 	uint32_t swmask = mask;
1085 	uint32_t fwmask = mask << 16;
1086 	int32_t timeout = 200;
1087 
1088 	DEBUGFUNC();
1089 	while (timeout) {
1090 		if (e1000_get_hw_eeprom_semaphore(hw))
1091 			return -E1000_ERR_SWFW_SYNC;
1092 
1093 		swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC);
1094 		if (!(swfw_sync & (fwmask | swmask)))
1095 			break;
1096 
1097 		/* firmware currently using resource (fwmask) */
1098 		/* or other software thread currently using resource (swmask) */
1099 		e1000_put_hw_eeprom_semaphore(hw);
1100 		mdelay(5);
1101 		timeout--;
1102 	}
1103 
1104 	if (!timeout) {
1105 		DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n");
1106 		return -E1000_ERR_SWFW_SYNC;
1107 	}
1108 
1109 	swfw_sync |= swmask;
1110 	E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync);
1111 
1112 	e1000_put_hw_eeprom_semaphore(hw);
1113 	return E1000_SUCCESS;
1114 }
1115 
1116 static void e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask)
1117 {
1118 	uint32_t swfw_sync = 0;
1119 
1120 	DEBUGFUNC();
1121 	while (e1000_get_hw_eeprom_semaphore(hw))
1122 		; /* Empty */
1123 
1124 	swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC);
1125 	swfw_sync &= ~mask;
1126 	E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync);
1127 
1128 	e1000_put_hw_eeprom_semaphore(hw);
1129 }
1130 
1131 static bool e1000_is_second_port(struct e1000_hw *hw)
1132 {
1133 	switch (hw->mac_type) {
1134 	case e1000_80003es2lan:
1135 	case e1000_82546:
1136 	case e1000_82571:
1137 		if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)
1138 			return true;
1139 		/* Fallthrough */
1140 	default:
1141 		return false;
1142 	}
1143 }
1144 
1145 #ifndef CONFIG_E1000_NO_NVM
1146 /******************************************************************************
1147  * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the
1148  * second function of dual function devices
1149  *
1150  * nic - Struct containing variables accessed by shared code
1151  *****************************************************************************/
1152 static int
1153 e1000_read_mac_addr(struct e1000_hw *hw, unsigned char enetaddr[6])
1154 {
1155 	uint16_t offset;
1156 	uint16_t eeprom_data;
1157 	uint32_t reg_data = 0;
1158 	int i;
1159 
1160 	DEBUGFUNC();
1161 
1162 	for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) {
1163 		offset = i >> 1;
1164 		if (hw->mac_type == e1000_igb) {
1165 			/* i210 preloads MAC address into RAL/RAH registers */
1166 			if (offset == 0)
1167 				reg_data = E1000_READ_REG_ARRAY(hw, RA, 0);
1168 			else if (offset == 1)
1169 				reg_data >>= 16;
1170 			else if (offset == 2)
1171 				reg_data = E1000_READ_REG_ARRAY(hw, RA, 1);
1172 			eeprom_data = reg_data & 0xffff;
1173 		} else if (e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
1174 			DEBUGOUT("EEPROM Read Error\n");
1175 			return -E1000_ERR_EEPROM;
1176 		}
1177 		enetaddr[i] = eeprom_data & 0xff;
1178 		enetaddr[i + 1] = (eeprom_data >> 8) & 0xff;
1179 	}
1180 
1181 	/* Invert the last bit if this is the second device */
1182 	if (e1000_is_second_port(hw))
1183 		enetaddr[5] ^= 1;
1184 
1185 	return 0;
1186 }
1187 #endif
1188 
1189 /******************************************************************************
1190  * Initializes receive address filters.
1191  *
1192  * hw - Struct containing variables accessed by shared code
1193  *
1194  * Places the MAC address in receive address register 0 and clears the rest
1195  * of the receive addresss registers. Clears the multicast table. Assumes
1196  * the receiver is in reset when the routine is called.
1197  *****************************************************************************/
1198 static void
1199 e1000_init_rx_addrs(struct e1000_hw *hw, unsigned char enetaddr[6])
1200 {
1201 	uint32_t i;
1202 	uint32_t addr_low;
1203 	uint32_t addr_high;
1204 
1205 	DEBUGFUNC();
1206 
1207 	/* Setup the receive address. */
1208 	DEBUGOUT("Programming MAC Address into RAR[0]\n");
1209 	addr_low = (enetaddr[0] |
1210 		    (enetaddr[1] << 8) |
1211 		    (enetaddr[2] << 16) | (enetaddr[3] << 24));
1212 
1213 	addr_high = (enetaddr[4] | (enetaddr[5] << 8) | E1000_RAH_AV);
1214 
1215 	E1000_WRITE_REG_ARRAY(hw, RA, 0, addr_low);
1216 	E1000_WRITE_REG_ARRAY(hw, RA, 1, addr_high);
1217 
1218 	/* Zero out the other 15 receive addresses. */
1219 	DEBUGOUT("Clearing RAR[1-15]\n");
1220 	for (i = 1; i < E1000_RAR_ENTRIES; i++) {
1221 		E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
1222 		E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
1223 	}
1224 }
1225 
1226 /******************************************************************************
1227  * Clears the VLAN filer table
1228  *
1229  * hw - Struct containing variables accessed by shared code
1230  *****************************************************************************/
1231 static void
1232 e1000_clear_vfta(struct e1000_hw *hw)
1233 {
1234 	uint32_t offset;
1235 
1236 	for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++)
1237 		E1000_WRITE_REG_ARRAY(hw, VFTA, offset, 0);
1238 }
1239 
1240 /******************************************************************************
1241  * Set the mac type member in the hw struct.
1242  *
1243  * hw - Struct containing variables accessed by shared code
1244  *****************************************************************************/
1245 int32_t
1246 e1000_set_mac_type(struct e1000_hw *hw)
1247 {
1248 	DEBUGFUNC();
1249 
1250 	switch (hw->device_id) {
1251 	case E1000_DEV_ID_82542:
1252 		switch (hw->revision_id) {
1253 		case E1000_82542_2_0_REV_ID:
1254 			hw->mac_type = e1000_82542_rev2_0;
1255 			break;
1256 		case E1000_82542_2_1_REV_ID:
1257 			hw->mac_type = e1000_82542_rev2_1;
1258 			break;
1259 		default:
1260 			/* Invalid 82542 revision ID */
1261 			return -E1000_ERR_MAC_TYPE;
1262 		}
1263 		break;
1264 	case E1000_DEV_ID_82543GC_FIBER:
1265 	case E1000_DEV_ID_82543GC_COPPER:
1266 		hw->mac_type = e1000_82543;
1267 		break;
1268 	case E1000_DEV_ID_82544EI_COPPER:
1269 	case E1000_DEV_ID_82544EI_FIBER:
1270 	case E1000_DEV_ID_82544GC_COPPER:
1271 	case E1000_DEV_ID_82544GC_LOM:
1272 		hw->mac_type = e1000_82544;
1273 		break;
1274 	case E1000_DEV_ID_82540EM:
1275 	case E1000_DEV_ID_82540EM_LOM:
1276 	case E1000_DEV_ID_82540EP:
1277 	case E1000_DEV_ID_82540EP_LOM:
1278 	case E1000_DEV_ID_82540EP_LP:
1279 		hw->mac_type = e1000_82540;
1280 		break;
1281 	case E1000_DEV_ID_82545EM_COPPER:
1282 	case E1000_DEV_ID_82545EM_FIBER:
1283 		hw->mac_type = e1000_82545;
1284 		break;
1285 	case E1000_DEV_ID_82545GM_COPPER:
1286 	case E1000_DEV_ID_82545GM_FIBER:
1287 	case E1000_DEV_ID_82545GM_SERDES:
1288 		hw->mac_type = e1000_82545_rev_3;
1289 		break;
1290 	case E1000_DEV_ID_82546EB_COPPER:
1291 	case E1000_DEV_ID_82546EB_FIBER:
1292 	case E1000_DEV_ID_82546EB_QUAD_COPPER:
1293 		hw->mac_type = e1000_82546;
1294 		break;
1295 	case E1000_DEV_ID_82546GB_COPPER:
1296 	case E1000_DEV_ID_82546GB_FIBER:
1297 	case E1000_DEV_ID_82546GB_SERDES:
1298 	case E1000_DEV_ID_82546GB_PCIE:
1299 	case E1000_DEV_ID_82546GB_QUAD_COPPER:
1300 	case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
1301 		hw->mac_type = e1000_82546_rev_3;
1302 		break;
1303 	case E1000_DEV_ID_82541EI:
1304 	case E1000_DEV_ID_82541EI_MOBILE:
1305 	case E1000_DEV_ID_82541ER_LOM:
1306 		hw->mac_type = e1000_82541;
1307 		break;
1308 	case E1000_DEV_ID_82541ER:
1309 	case E1000_DEV_ID_82541GI:
1310 	case E1000_DEV_ID_82541GI_LF:
1311 	case E1000_DEV_ID_82541GI_MOBILE:
1312 		hw->mac_type = e1000_82541_rev_2;
1313 		break;
1314 	case E1000_DEV_ID_82547EI:
1315 	case E1000_DEV_ID_82547EI_MOBILE:
1316 		hw->mac_type = e1000_82547;
1317 		break;
1318 	case E1000_DEV_ID_82547GI:
1319 		hw->mac_type = e1000_82547_rev_2;
1320 		break;
1321 	case E1000_DEV_ID_82571EB_COPPER:
1322 	case E1000_DEV_ID_82571EB_FIBER:
1323 	case E1000_DEV_ID_82571EB_SERDES:
1324 	case E1000_DEV_ID_82571EB_SERDES_DUAL:
1325 	case E1000_DEV_ID_82571EB_SERDES_QUAD:
1326 	case E1000_DEV_ID_82571EB_QUAD_COPPER:
1327 	case E1000_DEV_ID_82571PT_QUAD_COPPER:
1328 	case E1000_DEV_ID_82571EB_QUAD_FIBER:
1329 	case E1000_DEV_ID_82571EB_QUAD_COPPER_LOWPROFILE:
1330 		hw->mac_type = e1000_82571;
1331 		break;
1332 	case E1000_DEV_ID_82572EI_COPPER:
1333 	case E1000_DEV_ID_82572EI_FIBER:
1334 	case E1000_DEV_ID_82572EI_SERDES:
1335 	case E1000_DEV_ID_82572EI:
1336 		hw->mac_type = e1000_82572;
1337 		break;
1338 	case E1000_DEV_ID_82573E:
1339 	case E1000_DEV_ID_82573E_IAMT:
1340 	case E1000_DEV_ID_82573L:
1341 		hw->mac_type = e1000_82573;
1342 		break;
1343 	case E1000_DEV_ID_82574L:
1344 		hw->mac_type = e1000_82574;
1345 		break;
1346 	case E1000_DEV_ID_80003ES2LAN_COPPER_SPT:
1347 	case E1000_DEV_ID_80003ES2LAN_SERDES_SPT:
1348 	case E1000_DEV_ID_80003ES2LAN_COPPER_DPT:
1349 	case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
1350 		hw->mac_type = e1000_80003es2lan;
1351 		break;
1352 	case E1000_DEV_ID_ICH8_IGP_M_AMT:
1353 	case E1000_DEV_ID_ICH8_IGP_AMT:
1354 	case E1000_DEV_ID_ICH8_IGP_C:
1355 	case E1000_DEV_ID_ICH8_IFE:
1356 	case E1000_DEV_ID_ICH8_IFE_GT:
1357 	case E1000_DEV_ID_ICH8_IFE_G:
1358 	case E1000_DEV_ID_ICH8_IGP_M:
1359 		hw->mac_type = e1000_ich8lan;
1360 		break;
1361 	case PCI_DEVICE_ID_INTEL_I210_UNPROGRAMMED:
1362 	case PCI_DEVICE_ID_INTEL_I211_UNPROGRAMMED:
1363 	case PCI_DEVICE_ID_INTEL_I210_COPPER:
1364 	case PCI_DEVICE_ID_INTEL_I211_COPPER:
1365 	case PCI_DEVICE_ID_INTEL_I210_COPPER_FLASHLESS:
1366 	case PCI_DEVICE_ID_INTEL_I210_SERDES:
1367 	case PCI_DEVICE_ID_INTEL_I210_SERDES_FLASHLESS:
1368 	case PCI_DEVICE_ID_INTEL_I210_1000BASEKX:
1369 		hw->mac_type = e1000_igb;
1370 		break;
1371 	default:
1372 		/* Should never have loaded on this device */
1373 		return -E1000_ERR_MAC_TYPE;
1374 	}
1375 	return E1000_SUCCESS;
1376 }
1377 
1378 /******************************************************************************
1379  * Reset the transmit and receive units; mask and clear all interrupts.
1380  *
1381  * hw - Struct containing variables accessed by shared code
1382  *****************************************************************************/
1383 void
1384 e1000_reset_hw(struct e1000_hw *hw)
1385 {
1386 	uint32_t ctrl;
1387 	uint32_t ctrl_ext;
1388 	uint32_t manc;
1389 	uint32_t pba = 0;
1390 	uint32_t reg;
1391 
1392 	DEBUGFUNC();
1393 
1394 	/* get the correct pba value for both PCI and PCIe*/
1395 	if (hw->mac_type <  e1000_82571)
1396 		pba = E1000_DEFAULT_PCI_PBA;
1397 	else
1398 		pba = E1000_DEFAULT_PCIE_PBA;
1399 
1400 	/* For 82542 (rev 2.0), disable MWI before issuing a device reset */
1401 	if (hw->mac_type == e1000_82542_rev2_0) {
1402 		DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
1403 #ifdef CONFIG_DM_ETH
1404 		dm_pci_write_config16(hw->pdev, PCI_COMMAND,
1405 				hw->pci_cmd_word & ~PCI_COMMAND_INVALIDATE);
1406 #else
1407 		pci_write_config_word(hw->pdev, PCI_COMMAND,
1408 				hw->pci_cmd_word & ~PCI_COMMAND_INVALIDATE);
1409 #endif
1410 	}
1411 
1412 	/* Clear interrupt mask to stop board from generating interrupts */
1413 	DEBUGOUT("Masking off all interrupts\n");
1414 	if (hw->mac_type == e1000_igb)
1415 		E1000_WRITE_REG(hw, I210_IAM, 0);
1416 	E1000_WRITE_REG(hw, IMC, 0xffffffff);
1417 
1418 	/* Disable the Transmit and Receive units.  Then delay to allow
1419 	 * any pending transactions to complete before we hit the MAC with
1420 	 * the global reset.
1421 	 */
1422 	E1000_WRITE_REG(hw, RCTL, 0);
1423 	E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP);
1424 	E1000_WRITE_FLUSH(hw);
1425 
1426 	/* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */
1427 	hw->tbi_compatibility_on = false;
1428 
1429 	/* Delay to allow any outstanding PCI transactions to complete before
1430 	 * resetting the device
1431 	 */
1432 	mdelay(10);
1433 
1434 	/* Issue a global reset to the MAC.  This will reset the chip's
1435 	 * transmit, receive, DMA, and link units.  It will not effect
1436 	 * the current PCI configuration.  The global reset bit is self-
1437 	 * clearing, and should clear within a microsecond.
1438 	 */
1439 	DEBUGOUT("Issuing a global reset to MAC\n");
1440 	ctrl = E1000_READ_REG(hw, CTRL);
1441 
1442 	E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));
1443 
1444 	/* Force a reload from the EEPROM if necessary */
1445 	if (hw->mac_type == e1000_igb) {
1446 		mdelay(20);
1447 		reg = E1000_READ_REG(hw, STATUS);
1448 		if (reg & E1000_STATUS_PF_RST_DONE)
1449 			DEBUGOUT("PF OK\n");
1450 		reg = E1000_READ_REG(hw, I210_EECD);
1451 		if (reg & E1000_EECD_AUTO_RD)
1452 			DEBUGOUT("EEC OK\n");
1453 	} else if (hw->mac_type < e1000_82540) {
1454 		/* Wait for reset to complete */
1455 		udelay(10);
1456 		ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1457 		ctrl_ext |= E1000_CTRL_EXT_EE_RST;
1458 		E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
1459 		E1000_WRITE_FLUSH(hw);
1460 		/* Wait for EEPROM reload */
1461 		mdelay(2);
1462 	} else {
1463 		/* Wait for EEPROM reload (it happens automatically) */
1464 		mdelay(4);
1465 		/* Dissable HW ARPs on ASF enabled adapters */
1466 		manc = E1000_READ_REG(hw, MANC);
1467 		manc &= ~(E1000_MANC_ARP_EN);
1468 		E1000_WRITE_REG(hw, MANC, manc);
1469 	}
1470 
1471 	/* Clear interrupt mask to stop board from generating interrupts */
1472 	DEBUGOUT("Masking off all interrupts\n");
1473 	if (hw->mac_type == e1000_igb)
1474 		E1000_WRITE_REG(hw, I210_IAM, 0);
1475 	E1000_WRITE_REG(hw, IMC, 0xffffffff);
1476 
1477 	/* Clear any pending interrupt events. */
1478 	E1000_READ_REG(hw, ICR);
1479 
1480 	/* If MWI was previously enabled, reenable it. */
1481 	if (hw->mac_type == e1000_82542_rev2_0) {
1482 #ifdef CONFIG_DM_ETH
1483 		dm_pci_write_config16(hw->pdev, PCI_COMMAND, hw->pci_cmd_word);
1484 #else
1485 		pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word);
1486 #endif
1487 	}
1488 	if (hw->mac_type != e1000_igb)
1489 		E1000_WRITE_REG(hw, PBA, pba);
1490 }
1491 
1492 /******************************************************************************
1493  *
1494  * Initialize a number of hardware-dependent bits
1495  *
1496  * hw: Struct containing variables accessed by shared code
1497  *
1498  * This function contains hardware limitation workarounds for PCI-E adapters
1499  *
1500  *****************************************************************************/
1501 static void
1502 e1000_initialize_hardware_bits(struct e1000_hw *hw)
1503 {
1504 	if ((hw->mac_type >= e1000_82571) &&
1505 			(!hw->initialize_hw_bits_disable)) {
1506 		/* Settings common to all PCI-express silicon */
1507 		uint32_t reg_ctrl, reg_ctrl_ext;
1508 		uint32_t reg_tarc0, reg_tarc1;
1509 		uint32_t reg_tctl;
1510 		uint32_t reg_txdctl, reg_txdctl1;
1511 
1512 		/* link autonegotiation/sync workarounds */
1513 		reg_tarc0 = E1000_READ_REG(hw, TARC0);
1514 		reg_tarc0 &= ~((1 << 30)|(1 << 29)|(1 << 28)|(1 << 27));
1515 
1516 		/* Enable not-done TX descriptor counting */
1517 		reg_txdctl = E1000_READ_REG(hw, TXDCTL);
1518 		reg_txdctl |= E1000_TXDCTL_COUNT_DESC;
1519 		E1000_WRITE_REG(hw, TXDCTL, reg_txdctl);
1520 
1521 		reg_txdctl1 = E1000_READ_REG(hw, TXDCTL1);
1522 		reg_txdctl1 |= E1000_TXDCTL_COUNT_DESC;
1523 		E1000_WRITE_REG(hw, TXDCTL1, reg_txdctl1);
1524 
1525 	/* IGB is cool */
1526 	if (hw->mac_type == e1000_igb)
1527 		return;
1528 
1529 		switch (hw->mac_type) {
1530 		case e1000_82571:
1531 		case e1000_82572:
1532 			/* Clear PHY TX compatible mode bits */
1533 			reg_tarc1 = E1000_READ_REG(hw, TARC1);
1534 			reg_tarc1 &= ~((1 << 30)|(1 << 29));
1535 
1536 			/* link autonegotiation/sync workarounds */
1537 			reg_tarc0 |= ((1 << 26)|(1 << 25)|(1 << 24)|(1 << 23));
1538 
1539 			/* TX ring control fixes */
1540 			reg_tarc1 |= ((1 << 26)|(1 << 25)|(1 << 24));
1541 
1542 			/* Multiple read bit is reversed polarity */
1543 			reg_tctl = E1000_READ_REG(hw, TCTL);
1544 			if (reg_tctl & E1000_TCTL_MULR)
1545 				reg_tarc1 &= ~(1 << 28);
1546 			else
1547 				reg_tarc1 |= (1 << 28);
1548 
1549 			E1000_WRITE_REG(hw, TARC1, reg_tarc1);
1550 			break;
1551 		case e1000_82573:
1552 		case e1000_82574:
1553 			reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1554 			reg_ctrl_ext &= ~(1 << 23);
1555 			reg_ctrl_ext |= (1 << 22);
1556 
1557 			/* TX byte count fix */
1558 			reg_ctrl = E1000_READ_REG(hw, CTRL);
1559 			reg_ctrl &= ~(1 << 29);
1560 
1561 			E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext);
1562 			E1000_WRITE_REG(hw, CTRL, reg_ctrl);
1563 			break;
1564 		case e1000_80003es2lan:
1565 	/* improve small packet performace for fiber/serdes */
1566 			if ((hw->media_type == e1000_media_type_fiber)
1567 			|| (hw->media_type ==
1568 				e1000_media_type_internal_serdes)) {
1569 				reg_tarc0 &= ~(1 << 20);
1570 			}
1571 
1572 		/* Multiple read bit is reversed polarity */
1573 			reg_tctl = E1000_READ_REG(hw, TCTL);
1574 			reg_tarc1 = E1000_READ_REG(hw, TARC1);
1575 			if (reg_tctl & E1000_TCTL_MULR)
1576 				reg_tarc1 &= ~(1 << 28);
1577 			else
1578 				reg_tarc1 |= (1 << 28);
1579 
1580 			E1000_WRITE_REG(hw, TARC1, reg_tarc1);
1581 			break;
1582 		case e1000_ich8lan:
1583 			/* Reduce concurrent DMA requests to 3 from 4 */
1584 			if ((hw->revision_id < 3) ||
1585 			((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) &&
1586 				(hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))
1587 				reg_tarc0 |= ((1 << 29)|(1 << 28));
1588 
1589 			reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1590 			reg_ctrl_ext |= (1 << 22);
1591 			E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext);
1592 
1593 			/* workaround TX hang with TSO=on */
1594 			reg_tarc0 |= ((1 << 27)|(1 << 26)|(1 << 24)|(1 << 23));
1595 
1596 			/* Multiple read bit is reversed polarity */
1597 			reg_tctl = E1000_READ_REG(hw, TCTL);
1598 			reg_tarc1 = E1000_READ_REG(hw, TARC1);
1599 			if (reg_tctl & E1000_TCTL_MULR)
1600 				reg_tarc1 &= ~(1 << 28);
1601 			else
1602 				reg_tarc1 |= (1 << 28);
1603 
1604 			/* workaround TX hang with TSO=on */
1605 			reg_tarc1 |= ((1 << 30)|(1 << 26)|(1 << 24));
1606 
1607 			E1000_WRITE_REG(hw, TARC1, reg_tarc1);
1608 			break;
1609 		default:
1610 			break;
1611 		}
1612 
1613 		E1000_WRITE_REG(hw, TARC0, reg_tarc0);
1614 	}
1615 }
1616 
1617 /******************************************************************************
1618  * Performs basic configuration of the adapter.
1619  *
1620  * hw - Struct containing variables accessed by shared code
1621  *
1622  * Assumes that the controller has previously been reset and is in a
1623  * post-reset uninitialized state. Initializes the receive address registers,
1624  * multicast table, and VLAN filter table. Calls routines to setup link
1625  * configuration and flow control settings. Clears all on-chip counters. Leaves
1626  * the transmit and receive units disabled and uninitialized.
1627  *****************************************************************************/
1628 static int
1629 e1000_init_hw(struct e1000_hw *hw, unsigned char enetaddr[6])
1630 {
1631 	uint32_t ctrl;
1632 	uint32_t i;
1633 	int32_t ret_val;
1634 	uint16_t pcix_cmd_word;
1635 	uint16_t pcix_stat_hi_word;
1636 	uint16_t cmd_mmrbc;
1637 	uint16_t stat_mmrbc;
1638 	uint32_t mta_size;
1639 	uint32_t reg_data;
1640 	uint32_t ctrl_ext;
1641 	DEBUGFUNC();
1642 	/* force full DMA clock frequency for 10/100 on ICH8 A0-B0 */
1643 	if ((hw->mac_type == e1000_ich8lan) &&
1644 		((hw->revision_id < 3) ||
1645 		((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) &&
1646 		(hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))) {
1647 			reg_data = E1000_READ_REG(hw, STATUS);
1648 			reg_data &= ~0x80000000;
1649 			E1000_WRITE_REG(hw, STATUS, reg_data);
1650 	}
1651 	/* Do not need initialize Identification LED */
1652 
1653 	/* Set the media type and TBI compatibility */
1654 	e1000_set_media_type(hw);
1655 
1656 	/* Must be called after e1000_set_media_type
1657 	 * because media_type is used */
1658 	e1000_initialize_hardware_bits(hw);
1659 
1660 	/* Disabling VLAN filtering. */
1661 	DEBUGOUT("Initializing the IEEE VLAN\n");
1662 	/* VET hardcoded to standard value and VFTA removed in ICH8 LAN */
1663 	if (hw->mac_type != e1000_ich8lan) {
1664 		if (hw->mac_type < e1000_82545_rev_3)
1665 			E1000_WRITE_REG(hw, VET, 0);
1666 		e1000_clear_vfta(hw);
1667 	}
1668 
1669 	/* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
1670 	if (hw->mac_type == e1000_82542_rev2_0) {
1671 		DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
1672 #ifdef CONFIG_DM_ETH
1673 		dm_pci_write_config16(hw->pdev, PCI_COMMAND,
1674 				      hw->
1675 				      pci_cmd_word & ~PCI_COMMAND_INVALIDATE);
1676 #else
1677 		pci_write_config_word(hw->pdev, PCI_COMMAND,
1678 				      hw->
1679 				      pci_cmd_word & ~PCI_COMMAND_INVALIDATE);
1680 #endif
1681 		E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST);
1682 		E1000_WRITE_FLUSH(hw);
1683 		mdelay(5);
1684 	}
1685 
1686 	/* Setup the receive address. This involves initializing all of the Receive
1687 	 * Address Registers (RARs 0 - 15).
1688 	 */
1689 	e1000_init_rx_addrs(hw, enetaddr);
1690 
1691 	/* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */
1692 	if (hw->mac_type == e1000_82542_rev2_0) {
1693 		E1000_WRITE_REG(hw, RCTL, 0);
1694 		E1000_WRITE_FLUSH(hw);
1695 		mdelay(1);
1696 #ifdef CONFIG_DM_ETH
1697 		dm_pci_write_config16(hw->pdev, PCI_COMMAND, hw->pci_cmd_word);
1698 #else
1699 		pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word);
1700 #endif
1701 	}
1702 
1703 	/* Zero out the Multicast HASH table */
1704 	DEBUGOUT("Zeroing the MTA\n");
1705 	mta_size = E1000_MC_TBL_SIZE;
1706 	if (hw->mac_type == e1000_ich8lan)
1707 		mta_size = E1000_MC_TBL_SIZE_ICH8LAN;
1708 	for (i = 0; i < mta_size; i++) {
1709 		E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
1710 		/* use write flush to prevent Memory Write Block (MWB) from
1711 		 * occuring when accessing our register space */
1712 		E1000_WRITE_FLUSH(hw);
1713 	}
1714 
1715 	switch (hw->mac_type) {
1716 	case e1000_82545_rev_3:
1717 	case e1000_82546_rev_3:
1718 	case e1000_igb:
1719 		break;
1720 	default:
1721 	/* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */
1722 	if (hw->bus_type == e1000_bus_type_pcix) {
1723 #ifdef CONFIG_DM_ETH
1724 		dm_pci_read_config16(hw->pdev, PCIX_COMMAND_REGISTER,
1725 				     &pcix_cmd_word);
1726 		dm_pci_read_config16(hw->pdev, PCIX_STATUS_REGISTER_HI,
1727 				     &pcix_stat_hi_word);
1728 #else
1729 		pci_read_config_word(hw->pdev, PCIX_COMMAND_REGISTER,
1730 				     &pcix_cmd_word);
1731 		pci_read_config_word(hw->pdev, PCIX_STATUS_REGISTER_HI,
1732 				     &pcix_stat_hi_word);
1733 #endif
1734 		cmd_mmrbc =
1735 		    (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) >>
1736 		    PCIX_COMMAND_MMRBC_SHIFT;
1737 		stat_mmrbc =
1738 		    (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >>
1739 		    PCIX_STATUS_HI_MMRBC_SHIFT;
1740 		if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K)
1741 			stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K;
1742 		if (cmd_mmrbc > stat_mmrbc) {
1743 			pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK;
1744 			pcix_cmd_word |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT;
1745 #ifdef CONFIG_DM_ETH
1746 			dm_pci_write_config16(hw->pdev, PCIX_COMMAND_REGISTER,
1747 					      pcix_cmd_word);
1748 #else
1749 			pci_write_config_word(hw->pdev, PCIX_COMMAND_REGISTER,
1750 					      pcix_cmd_word);
1751 #endif
1752 		}
1753 	}
1754 		break;
1755 	}
1756 
1757 	/* More time needed for PHY to initialize */
1758 	if (hw->mac_type == e1000_ich8lan)
1759 		mdelay(15);
1760 	if (hw->mac_type == e1000_igb)
1761 		mdelay(15);
1762 
1763 	/* Call a subroutine to configure the link and setup flow control. */
1764 	ret_val = e1000_setup_link(hw);
1765 
1766 	/* Set the transmit descriptor write-back policy */
1767 	if (hw->mac_type > e1000_82544) {
1768 		ctrl = E1000_READ_REG(hw, TXDCTL);
1769 		ctrl =
1770 		    (ctrl & ~E1000_TXDCTL_WTHRESH) |
1771 		    E1000_TXDCTL_FULL_TX_DESC_WB;
1772 		E1000_WRITE_REG(hw, TXDCTL, ctrl);
1773 	}
1774 
1775 	/* Set the receive descriptor write back policy */
1776 	if (hw->mac_type >= e1000_82571) {
1777 		ctrl = E1000_READ_REG(hw, RXDCTL);
1778 		ctrl =
1779 		    (ctrl & ~E1000_RXDCTL_WTHRESH) |
1780 		    E1000_RXDCTL_FULL_RX_DESC_WB;
1781 		E1000_WRITE_REG(hw, RXDCTL, ctrl);
1782 	}
1783 
1784 	switch (hw->mac_type) {
1785 	default:
1786 		break;
1787 	case e1000_80003es2lan:
1788 		/* Enable retransmit on late collisions */
1789 		reg_data = E1000_READ_REG(hw, TCTL);
1790 		reg_data |= E1000_TCTL_RTLC;
1791 		E1000_WRITE_REG(hw, TCTL, reg_data);
1792 
1793 		/* Configure Gigabit Carry Extend Padding */
1794 		reg_data = E1000_READ_REG(hw, TCTL_EXT);
1795 		reg_data &= ~E1000_TCTL_EXT_GCEX_MASK;
1796 		reg_data |= DEFAULT_80003ES2LAN_TCTL_EXT_GCEX;
1797 		E1000_WRITE_REG(hw, TCTL_EXT, reg_data);
1798 
1799 		/* Configure Transmit Inter-Packet Gap */
1800 		reg_data = E1000_READ_REG(hw, TIPG);
1801 		reg_data &= ~E1000_TIPG_IPGT_MASK;
1802 		reg_data |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;
1803 		E1000_WRITE_REG(hw, TIPG, reg_data);
1804 
1805 		reg_data = E1000_READ_REG_ARRAY(hw, FFLT, 0x0001);
1806 		reg_data &= ~0x00100000;
1807 		E1000_WRITE_REG_ARRAY(hw, FFLT, 0x0001, reg_data);
1808 		/* Fall through */
1809 	case e1000_82571:
1810 	case e1000_82572:
1811 	case e1000_ich8lan:
1812 		ctrl = E1000_READ_REG(hw, TXDCTL1);
1813 		ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH)
1814 			| E1000_TXDCTL_FULL_TX_DESC_WB;
1815 		E1000_WRITE_REG(hw, TXDCTL1, ctrl);
1816 		break;
1817 	case e1000_82573:
1818 	case e1000_82574:
1819 		reg_data = E1000_READ_REG(hw, GCR);
1820 		reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
1821 		E1000_WRITE_REG(hw, GCR, reg_data);
1822 	case e1000_igb:
1823 		break;
1824 	}
1825 
1826 	if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER ||
1827 		hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) {
1828 		ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1829 		/* Relaxed ordering must be disabled to avoid a parity
1830 		 * error crash in a PCI slot. */
1831 		ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
1832 		E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
1833 	}
1834 
1835 	return ret_val;
1836 }
1837 
1838 /******************************************************************************
1839  * Configures flow control and link settings.
1840  *
1841  * hw - Struct containing variables accessed by shared code
1842  *
1843  * Determines which flow control settings to use. Calls the apropriate media-
1844  * specific link configuration function. Configures the flow control settings.
1845  * Assuming the adapter has a valid link partner, a valid link should be
1846  * established. Assumes the hardware has previously been reset and the
1847  * transmitter and receiver are not enabled.
1848  *****************************************************************************/
1849 static int
1850 e1000_setup_link(struct e1000_hw *hw)
1851 {
1852 	int32_t ret_val;
1853 #ifndef CONFIG_E1000_NO_NVM
1854 	uint32_t ctrl_ext;
1855 	uint16_t eeprom_data;
1856 #endif
1857 
1858 	DEBUGFUNC();
1859 
1860 	/* In the case of the phy reset being blocked, we already have a link.
1861 	 * We do not have to set it up again. */
1862 	if (e1000_check_phy_reset_block(hw))
1863 		return E1000_SUCCESS;
1864 
1865 #ifndef CONFIG_E1000_NO_NVM
1866 	/* Read and store word 0x0F of the EEPROM. This word contains bits
1867 	 * that determine the hardware's default PAUSE (flow control) mode,
1868 	 * a bit that determines whether the HW defaults to enabling or
1869 	 * disabling auto-negotiation, and the direction of the
1870 	 * SW defined pins. If there is no SW over-ride of the flow
1871 	 * control setting, then the variable hw->fc will
1872 	 * be initialized based on a value in the EEPROM.
1873 	 */
1874 	if (e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, 1,
1875 				&eeprom_data) < 0) {
1876 		DEBUGOUT("EEPROM Read Error\n");
1877 		return -E1000_ERR_EEPROM;
1878 	}
1879 #endif
1880 	if (hw->fc == e1000_fc_default) {
1881 		switch (hw->mac_type) {
1882 		case e1000_ich8lan:
1883 		case e1000_82573:
1884 		case e1000_82574:
1885 		case e1000_igb:
1886 			hw->fc = e1000_fc_full;
1887 			break;
1888 		default:
1889 #ifndef CONFIG_E1000_NO_NVM
1890 			ret_val = e1000_read_eeprom(hw,
1891 				EEPROM_INIT_CONTROL2_REG, 1, &eeprom_data);
1892 			if (ret_val) {
1893 				DEBUGOUT("EEPROM Read Error\n");
1894 				return -E1000_ERR_EEPROM;
1895 			}
1896 			if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0)
1897 				hw->fc = e1000_fc_none;
1898 			else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) ==
1899 				    EEPROM_WORD0F_ASM_DIR)
1900 				hw->fc = e1000_fc_tx_pause;
1901 			else
1902 #endif
1903 				hw->fc = e1000_fc_full;
1904 			break;
1905 		}
1906 	}
1907 
1908 	/* We want to save off the original Flow Control configuration just
1909 	 * in case we get disconnected and then reconnected into a different
1910 	 * hub or switch with different Flow Control capabilities.
1911 	 */
1912 	if (hw->mac_type == e1000_82542_rev2_0)
1913 		hw->fc &= (~e1000_fc_tx_pause);
1914 
1915 	if ((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1))
1916 		hw->fc &= (~e1000_fc_rx_pause);
1917 
1918 	hw->original_fc = hw->fc;
1919 
1920 	DEBUGOUT("After fix-ups FlowControl is now = %x\n", hw->fc);
1921 
1922 #ifndef CONFIG_E1000_NO_NVM
1923 	/* Take the 4 bits from EEPROM word 0x0F that determine the initial
1924 	 * polarity value for the SW controlled pins, and setup the
1925 	 * Extended Device Control reg with that info.
1926 	 * This is needed because one of the SW controlled pins is used for
1927 	 * signal detection.  So this should be done before e1000_setup_pcs_link()
1928 	 * or e1000_phy_setup() is called.
1929 	 */
1930 	if (hw->mac_type == e1000_82543) {
1931 		ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) <<
1932 			    SWDPIO__EXT_SHIFT);
1933 		E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
1934 	}
1935 #endif
1936 
1937 	/* Call the necessary subroutine to configure the link. */
1938 	ret_val = (hw->media_type == e1000_media_type_fiber) ?
1939 	    e1000_setup_fiber_link(hw) : e1000_setup_copper_link(hw);
1940 	if (ret_val < 0) {
1941 		return ret_val;
1942 	}
1943 
1944 	/* Initialize the flow control address, type, and PAUSE timer
1945 	 * registers to their default values.  This is done even if flow
1946 	 * control is disabled, because it does not hurt anything to
1947 	 * initialize these registers.
1948 	 */
1949 	DEBUGOUT("Initializing the Flow Control address, type"
1950 			"and timer regs\n");
1951 
1952 	/* FCAL/H and FCT are hardcoded to standard values in e1000_ich8lan. */
1953 	if (hw->mac_type != e1000_ich8lan) {
1954 		E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE);
1955 		E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH);
1956 		E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW);
1957 	}
1958 
1959 	E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time);
1960 
1961 	/* Set the flow control receive threshold registers.  Normally,
1962 	 * these registers will be set to a default threshold that may be
1963 	 * adjusted later by the driver's runtime code.  However, if the
1964 	 * ability to transmit pause frames in not enabled, then these
1965 	 * registers will be set to 0.
1966 	 */
1967 	if (!(hw->fc & e1000_fc_tx_pause)) {
1968 		E1000_WRITE_REG(hw, FCRTL, 0);
1969 		E1000_WRITE_REG(hw, FCRTH, 0);
1970 	} else {
1971 		/* We need to set up the Receive Threshold high and low water marks
1972 		 * as well as (optionally) enabling the transmission of XON frames.
1973 		 */
1974 		if (hw->fc_send_xon) {
1975 			E1000_WRITE_REG(hw, FCRTL,
1976 					(hw->fc_low_water | E1000_FCRTL_XONE));
1977 			E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
1978 		} else {
1979 			E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water);
1980 			E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
1981 		}
1982 	}
1983 	return ret_val;
1984 }
1985 
1986 /******************************************************************************
1987  * Sets up link for a fiber based adapter
1988  *
1989  * hw - Struct containing variables accessed by shared code
1990  *
1991  * Manipulates Physical Coding Sublayer functions in order to configure
1992  * link. Assumes the hardware has been previously reset and the transmitter
1993  * and receiver are not enabled.
1994  *****************************************************************************/
1995 static int
1996 e1000_setup_fiber_link(struct e1000_hw *hw)
1997 {
1998 	uint32_t ctrl;
1999 	uint32_t status;
2000 	uint32_t txcw = 0;
2001 	uint32_t i;
2002 	uint32_t signal;
2003 	int32_t ret_val;
2004 
2005 	DEBUGFUNC();
2006 	/* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be
2007 	 * set when the optics detect a signal. On older adapters, it will be
2008 	 * cleared when there is a signal
2009 	 */
2010 	ctrl = E1000_READ_REG(hw, CTRL);
2011 	if ((hw->mac_type > e1000_82544) && !(ctrl & E1000_CTRL_ILOS))
2012 		signal = E1000_CTRL_SWDPIN1;
2013 	else
2014 		signal = 0;
2015 
2016 	printf("signal for %s is %x (ctrl %08x)!!!!\n", hw->name, signal,
2017 	       ctrl);
2018 	/* Take the link out of reset */
2019 	ctrl &= ~(E1000_CTRL_LRST);
2020 
2021 	e1000_config_collision_dist(hw);
2022 
2023 	/* Check for a software override of the flow control settings, and setup
2024 	 * the device accordingly.  If auto-negotiation is enabled, then software
2025 	 * will have to set the "PAUSE" bits to the correct value in the Tranmsit
2026 	 * Config Word Register (TXCW) and re-start auto-negotiation.  However, if
2027 	 * auto-negotiation is disabled, then software will have to manually
2028 	 * configure the two flow control enable bits in the CTRL register.
2029 	 *
2030 	 * The possible values of the "fc" parameter are:
2031 	 *	0:  Flow control is completely disabled
2032 	 *	1:  Rx flow control is enabled (we can receive pause frames, but
2033 	 *	    not send pause frames).
2034 	 *	2:  Tx flow control is enabled (we can send pause frames but we do
2035 	 *	    not support receiving pause frames).
2036 	 *	3:  Both Rx and TX flow control (symmetric) are enabled.
2037 	 */
2038 	switch (hw->fc) {
2039 	case e1000_fc_none:
2040 		/* Flow control is completely disabled by a software over-ride. */
2041 		txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
2042 		break;
2043 	case e1000_fc_rx_pause:
2044 		/* RX Flow control is enabled and TX Flow control is disabled by a
2045 		 * software over-ride. Since there really isn't a way to advertise
2046 		 * that we are capable of RX Pause ONLY, we will advertise that we
2047 		 * support both symmetric and asymmetric RX PAUSE. Later, we will
2048 		 *  disable the adapter's ability to send PAUSE frames.
2049 		 */
2050 		txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
2051 		break;
2052 	case e1000_fc_tx_pause:
2053 		/* TX Flow control is enabled, and RX Flow control is disabled, by a
2054 		 * software over-ride.
2055 		 */
2056 		txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
2057 		break;
2058 	case e1000_fc_full:
2059 		/* Flow control (both RX and TX) is enabled by a software over-ride. */
2060 		txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
2061 		break;
2062 	default:
2063 		DEBUGOUT("Flow control param set incorrectly\n");
2064 		return -E1000_ERR_CONFIG;
2065 		break;
2066 	}
2067 
2068 	/* Since auto-negotiation is enabled, take the link out of reset (the link
2069 	 * will be in reset, because we previously reset the chip). This will
2070 	 * restart auto-negotiation.  If auto-neogtiation is successful then the
2071 	 * link-up status bit will be set and the flow control enable bits (RFCE
2072 	 * and TFCE) will be set according to their negotiated value.
2073 	 */
2074 	DEBUGOUT("Auto-negotiation enabled (%#x)\n", txcw);
2075 
2076 	E1000_WRITE_REG(hw, TXCW, txcw);
2077 	E1000_WRITE_REG(hw, CTRL, ctrl);
2078 	E1000_WRITE_FLUSH(hw);
2079 
2080 	hw->txcw = txcw;
2081 	mdelay(1);
2082 
2083 	/* If we have a signal (the cable is plugged in) then poll for a "Link-Up"
2084 	 * indication in the Device Status Register.  Time-out if a link isn't
2085 	 * seen in 500 milliseconds seconds (Auto-negotiation should complete in
2086 	 * less than 500 milliseconds even if the other end is doing it in SW).
2087 	 */
2088 	if ((E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) {
2089 		DEBUGOUT("Looking for Link\n");
2090 		for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) {
2091 			mdelay(10);
2092 			status = E1000_READ_REG(hw, STATUS);
2093 			if (status & E1000_STATUS_LU)
2094 				break;
2095 		}
2096 		if (i == (LINK_UP_TIMEOUT / 10)) {
2097 			/* AutoNeg failed to achieve a link, so we'll call
2098 			 * e1000_check_for_link. This routine will force the link up if we
2099 			 * detect a signal. This will allow us to communicate with
2100 			 * non-autonegotiating link partners.
2101 			 */
2102 			DEBUGOUT("Never got a valid link from auto-neg!!!\n");
2103 			hw->autoneg_failed = 1;
2104 			ret_val = e1000_check_for_link(hw);
2105 			if (ret_val < 0) {
2106 				DEBUGOUT("Error while checking for link\n");
2107 				return ret_val;
2108 			}
2109 			hw->autoneg_failed = 0;
2110 		} else {
2111 			hw->autoneg_failed = 0;
2112 			DEBUGOUT("Valid Link Found\n");
2113 		}
2114 	} else {
2115 		DEBUGOUT("No Signal Detected\n");
2116 		return -E1000_ERR_NOLINK;
2117 	}
2118 	return 0;
2119 }
2120 
2121 /******************************************************************************
2122 * Make sure we have a valid PHY and change PHY mode before link setup.
2123 *
2124 * hw - Struct containing variables accessed by shared code
2125 ******************************************************************************/
2126 static int32_t
2127 e1000_copper_link_preconfig(struct e1000_hw *hw)
2128 {
2129 	uint32_t ctrl;
2130 	int32_t ret_val;
2131 	uint16_t phy_data;
2132 
2133 	DEBUGFUNC();
2134 
2135 	ctrl = E1000_READ_REG(hw, CTRL);
2136 	/* With 82543, we need to force speed and duplex on the MAC equal to what
2137 	 * the PHY speed and duplex configuration is. In addition, we need to
2138 	 * perform a hardware reset on the PHY to take it out of reset.
2139 	 */
2140 	if (hw->mac_type > e1000_82543) {
2141 		ctrl |= E1000_CTRL_SLU;
2142 		ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
2143 		E1000_WRITE_REG(hw, CTRL, ctrl);
2144 	} else {
2145 		ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX
2146 				| E1000_CTRL_SLU);
2147 		E1000_WRITE_REG(hw, CTRL, ctrl);
2148 		ret_val = e1000_phy_hw_reset(hw);
2149 		if (ret_val)
2150 			return ret_val;
2151 	}
2152 
2153 	/* Make sure we have a valid PHY */
2154 	ret_val = e1000_detect_gig_phy(hw);
2155 	if (ret_val) {
2156 		DEBUGOUT("Error, did not detect valid phy.\n");
2157 		return ret_val;
2158 	}
2159 	DEBUGOUT("Phy ID = %x\n", hw->phy_id);
2160 
2161 	/* Set PHY to class A mode (if necessary) */
2162 	ret_val = e1000_set_phy_mode(hw);
2163 	if (ret_val)
2164 		return ret_val;
2165 	if ((hw->mac_type == e1000_82545_rev_3) ||
2166 		(hw->mac_type == e1000_82546_rev_3)) {
2167 		ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
2168 				&phy_data);
2169 		phy_data |= 0x00000008;
2170 		ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
2171 				phy_data);
2172 	}
2173 
2174 	if (hw->mac_type <= e1000_82543 ||
2175 		hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 ||
2176 		hw->mac_type == e1000_82541_rev_2
2177 		|| hw->mac_type == e1000_82547_rev_2)
2178 			hw->phy_reset_disable = false;
2179 
2180 	return E1000_SUCCESS;
2181 }
2182 
2183 /*****************************************************************************
2184  *
2185  * This function sets the lplu state according to the active flag.  When
2186  * activating lplu this function also disables smart speed and vise versa.
2187  * lplu will not be activated unless the device autonegotiation advertisment
2188  * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
2189  * hw: Struct containing variables accessed by shared code
2190  * active - true to enable lplu false to disable lplu.
2191  *
2192  * returns: - E1000_ERR_PHY if fail to read/write the PHY
2193  *            E1000_SUCCESS at any other case.
2194  *
2195  ****************************************************************************/
2196 
2197 static int32_t
2198 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active)
2199 {
2200 	uint32_t phy_ctrl = 0;
2201 	int32_t ret_val;
2202 	uint16_t phy_data;
2203 	DEBUGFUNC();
2204 
2205 	if (hw->phy_type != e1000_phy_igp && hw->phy_type != e1000_phy_igp_2
2206 	    && hw->phy_type != e1000_phy_igp_3)
2207 		return E1000_SUCCESS;
2208 
2209 	/* During driver activity LPLU should not be used or it will attain link
2210 	 * from the lowest speeds starting from 10Mbps. The capability is used
2211 	 * for Dx transitions and states */
2212 	if (hw->mac_type == e1000_82541_rev_2
2213 			|| hw->mac_type == e1000_82547_rev_2) {
2214 		ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO,
2215 				&phy_data);
2216 		if (ret_val)
2217 			return ret_val;
2218 	} else if (hw->mac_type == e1000_ich8lan) {
2219 		/* MAC writes into PHY register based on the state transition
2220 		 * and start auto-negotiation. SW driver can overwrite the
2221 		 * settings in CSR PHY power control E1000_PHY_CTRL register. */
2222 		phy_ctrl = E1000_READ_REG(hw, PHY_CTRL);
2223 	} else {
2224 		ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
2225 				&phy_data);
2226 		if (ret_val)
2227 			return ret_val;
2228 	}
2229 
2230 	if (!active) {
2231 		if (hw->mac_type == e1000_82541_rev_2 ||
2232 			hw->mac_type == e1000_82547_rev_2) {
2233 			phy_data &= ~IGP01E1000_GMII_FLEX_SPD;
2234 			ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
2235 					phy_data);
2236 			if (ret_val)
2237 				return ret_val;
2238 		} else {
2239 			if (hw->mac_type == e1000_ich8lan) {
2240 				phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
2241 				E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
2242 			} else {
2243 				phy_data &= ~IGP02E1000_PM_D3_LPLU;
2244 				ret_val = e1000_write_phy_reg(hw,
2245 					IGP02E1000_PHY_POWER_MGMT, phy_data);
2246 				if (ret_val)
2247 					return ret_val;
2248 			}
2249 		}
2250 
2251 	/* LPLU and SmartSpeed are mutually exclusive.  LPLU is used during
2252 	 * Dx states where the power conservation is most important.  During
2253 	 * driver activity we should enable SmartSpeed, so performance is
2254 	 * maintained. */
2255 		if (hw->smart_speed == e1000_smart_speed_on) {
2256 			ret_val = e1000_read_phy_reg(hw,
2257 					IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2258 			if (ret_val)
2259 				return ret_val;
2260 
2261 			phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
2262 			ret_val = e1000_write_phy_reg(hw,
2263 					IGP01E1000_PHY_PORT_CONFIG, phy_data);
2264 			if (ret_val)
2265 				return ret_val;
2266 		} else if (hw->smart_speed == e1000_smart_speed_off) {
2267 			ret_val = e1000_read_phy_reg(hw,
2268 					IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2269 			if (ret_val)
2270 				return ret_val;
2271 
2272 			phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2273 			ret_val = e1000_write_phy_reg(hw,
2274 					IGP01E1000_PHY_PORT_CONFIG, phy_data);
2275 			if (ret_val)
2276 				return ret_val;
2277 		}
2278 
2279 	} else if ((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT)
2280 		|| (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL) ||
2281 		(hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) {
2282 
2283 		if (hw->mac_type == e1000_82541_rev_2 ||
2284 		    hw->mac_type == e1000_82547_rev_2) {
2285 			phy_data |= IGP01E1000_GMII_FLEX_SPD;
2286 			ret_val = e1000_write_phy_reg(hw,
2287 					IGP01E1000_GMII_FIFO, phy_data);
2288 			if (ret_val)
2289 				return ret_val;
2290 		} else {
2291 			if (hw->mac_type == e1000_ich8lan) {
2292 				phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
2293 				E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
2294 			} else {
2295 				phy_data |= IGP02E1000_PM_D3_LPLU;
2296 				ret_val = e1000_write_phy_reg(hw,
2297 					IGP02E1000_PHY_POWER_MGMT, phy_data);
2298 				if (ret_val)
2299 					return ret_val;
2300 			}
2301 		}
2302 
2303 		/* When LPLU is enabled we should disable SmartSpeed */
2304 		ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
2305 				&phy_data);
2306 		if (ret_val)
2307 			return ret_val;
2308 
2309 		phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2310 		ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
2311 				phy_data);
2312 		if (ret_val)
2313 			return ret_val;
2314 	}
2315 	return E1000_SUCCESS;
2316 }
2317 
2318 /*****************************************************************************
2319  *
2320  * This function sets the lplu d0 state according to the active flag.  When
2321  * activating lplu this function also disables smart speed and vise versa.
2322  * lplu will not be activated unless the device autonegotiation advertisment
2323  * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
2324  * hw: Struct containing variables accessed by shared code
2325  * active - true to enable lplu false to disable lplu.
2326  *
2327  * returns: - E1000_ERR_PHY if fail to read/write the PHY
2328  *            E1000_SUCCESS at any other case.
2329  *
2330  ****************************************************************************/
2331 
2332 static int32_t
2333 e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active)
2334 {
2335 	uint32_t phy_ctrl = 0;
2336 	int32_t ret_val;
2337 	uint16_t phy_data;
2338 	DEBUGFUNC();
2339 
2340 	if (hw->mac_type <= e1000_82547_rev_2)
2341 		return E1000_SUCCESS;
2342 
2343 	if (hw->mac_type == e1000_ich8lan) {
2344 		phy_ctrl = E1000_READ_REG(hw, PHY_CTRL);
2345 	} else if (hw->mac_type == e1000_igb) {
2346 		phy_ctrl = E1000_READ_REG(hw, I210_PHY_CTRL);
2347 	} else {
2348 		ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
2349 				&phy_data);
2350 		if (ret_val)
2351 			return ret_val;
2352 	}
2353 
2354 	if (!active) {
2355 		if (hw->mac_type == e1000_ich8lan) {
2356 			phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
2357 			E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
2358 		} else if (hw->mac_type == e1000_igb) {
2359 			phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
2360 			E1000_WRITE_REG(hw, I210_PHY_CTRL, phy_ctrl);
2361 		} else {
2362 			phy_data &= ~IGP02E1000_PM_D0_LPLU;
2363 			ret_val = e1000_write_phy_reg(hw,
2364 					IGP02E1000_PHY_POWER_MGMT, phy_data);
2365 			if (ret_val)
2366 				return ret_val;
2367 		}
2368 
2369 		if (hw->mac_type == e1000_igb)
2370 			return E1000_SUCCESS;
2371 
2372 	/* LPLU and SmartSpeed are mutually exclusive.  LPLU is used during
2373 	 * Dx states where the power conservation is most important.  During
2374 	 * driver activity we should enable SmartSpeed, so performance is
2375 	 * maintained. */
2376 		if (hw->smart_speed == e1000_smart_speed_on) {
2377 			ret_val = e1000_read_phy_reg(hw,
2378 					IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2379 			if (ret_val)
2380 				return ret_val;
2381 
2382 			phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
2383 			ret_val = e1000_write_phy_reg(hw,
2384 					IGP01E1000_PHY_PORT_CONFIG, phy_data);
2385 			if (ret_val)
2386 				return ret_val;
2387 		} else if (hw->smart_speed == e1000_smart_speed_off) {
2388 			ret_val = e1000_read_phy_reg(hw,
2389 					IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2390 			if (ret_val)
2391 				return ret_val;
2392 
2393 			phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2394 			ret_val = e1000_write_phy_reg(hw,
2395 					IGP01E1000_PHY_PORT_CONFIG, phy_data);
2396 			if (ret_val)
2397 				return ret_val;
2398 		}
2399 
2400 
2401 	} else {
2402 
2403 		if (hw->mac_type == e1000_ich8lan) {
2404 			phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
2405 			E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
2406 		} else if (hw->mac_type == e1000_igb) {
2407 			phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
2408 			E1000_WRITE_REG(hw, I210_PHY_CTRL, phy_ctrl);
2409 		} else {
2410 			phy_data |= IGP02E1000_PM_D0_LPLU;
2411 			ret_val = e1000_write_phy_reg(hw,
2412 					IGP02E1000_PHY_POWER_MGMT, phy_data);
2413 			if (ret_val)
2414 				return ret_val;
2415 		}
2416 
2417 		if (hw->mac_type == e1000_igb)
2418 			return E1000_SUCCESS;
2419 
2420 		/* When LPLU is enabled we should disable SmartSpeed */
2421 		ret_val = e1000_read_phy_reg(hw,
2422 				IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2423 		if (ret_val)
2424 			return ret_val;
2425 
2426 		phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2427 		ret_val = e1000_write_phy_reg(hw,
2428 				IGP01E1000_PHY_PORT_CONFIG, phy_data);
2429 		if (ret_val)
2430 			return ret_val;
2431 
2432 	}
2433 	return E1000_SUCCESS;
2434 }
2435 
2436 /********************************************************************
2437 * Copper link setup for e1000_phy_igp series.
2438 *
2439 * hw - Struct containing variables accessed by shared code
2440 *********************************************************************/
2441 static int32_t
2442 e1000_copper_link_igp_setup(struct e1000_hw *hw)
2443 {
2444 	uint32_t led_ctrl;
2445 	int32_t ret_val;
2446 	uint16_t phy_data;
2447 
2448 	DEBUGFUNC();
2449 
2450 	if (hw->phy_reset_disable)
2451 		return E1000_SUCCESS;
2452 
2453 	ret_val = e1000_phy_reset(hw);
2454 	if (ret_val) {
2455 		DEBUGOUT("Error Resetting the PHY\n");
2456 		return ret_val;
2457 	}
2458 
2459 	/* Wait 15ms for MAC to configure PHY from eeprom settings */
2460 	mdelay(15);
2461 	if (hw->mac_type != e1000_ich8lan) {
2462 		/* Configure activity LED after PHY reset */
2463 		led_ctrl = E1000_READ_REG(hw, LEDCTL);
2464 		led_ctrl &= IGP_ACTIVITY_LED_MASK;
2465 		led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
2466 		E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
2467 	}
2468 
2469 	/* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */
2470 	if (hw->phy_type == e1000_phy_igp) {
2471 		/* disable lplu d3 during driver init */
2472 		ret_val = e1000_set_d3_lplu_state(hw, false);
2473 		if (ret_val) {
2474 			DEBUGOUT("Error Disabling LPLU D3\n");
2475 			return ret_val;
2476 		}
2477 	}
2478 
2479 	/* disable lplu d0 during driver init */
2480 	ret_val = e1000_set_d0_lplu_state(hw, false);
2481 	if (ret_val) {
2482 		DEBUGOUT("Error Disabling LPLU D0\n");
2483 		return ret_val;
2484 	}
2485 	/* Configure mdi-mdix settings */
2486 	ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
2487 	if (ret_val)
2488 		return ret_val;
2489 
2490 	if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
2491 		hw->dsp_config_state = e1000_dsp_config_disabled;
2492 		/* Force MDI for earlier revs of the IGP PHY */
2493 		phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX
2494 				| IGP01E1000_PSCR_FORCE_MDI_MDIX);
2495 		hw->mdix = 1;
2496 
2497 	} else {
2498 		hw->dsp_config_state = e1000_dsp_config_enabled;
2499 		phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
2500 
2501 		switch (hw->mdix) {
2502 		case 1:
2503 			phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
2504 			break;
2505 		case 2:
2506 			phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
2507 			break;
2508 		case 0:
2509 		default:
2510 			phy_data |= IGP01E1000_PSCR_AUTO_MDIX;
2511 			break;
2512 		}
2513 	}
2514 	ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
2515 	if (ret_val)
2516 		return ret_val;
2517 
2518 	/* set auto-master slave resolution settings */
2519 	if (hw->autoneg) {
2520 		e1000_ms_type phy_ms_setting = hw->master_slave;
2521 
2522 		if (hw->ffe_config_state == e1000_ffe_config_active)
2523 			hw->ffe_config_state = e1000_ffe_config_enabled;
2524 
2525 		if (hw->dsp_config_state == e1000_dsp_config_activated)
2526 			hw->dsp_config_state = e1000_dsp_config_enabled;
2527 
2528 		/* when autonegotiation advertisment is only 1000Mbps then we
2529 		  * should disable SmartSpeed and enable Auto MasterSlave
2530 		  * resolution as hardware default. */
2531 		if (hw->autoneg_advertised == ADVERTISE_1000_FULL) {
2532 			/* Disable SmartSpeed */
2533 			ret_val = e1000_read_phy_reg(hw,
2534 					IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2535 			if (ret_val)
2536 				return ret_val;
2537 			phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2538 			ret_val = e1000_write_phy_reg(hw,
2539 					IGP01E1000_PHY_PORT_CONFIG, phy_data);
2540 			if (ret_val)
2541 				return ret_val;
2542 			/* Set auto Master/Slave resolution process */
2543 			ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL,
2544 					&phy_data);
2545 			if (ret_val)
2546 				return ret_val;
2547 			phy_data &= ~CR_1000T_MS_ENABLE;
2548 			ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL,
2549 					phy_data);
2550 			if (ret_val)
2551 				return ret_val;
2552 		}
2553 
2554 		ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
2555 		if (ret_val)
2556 			return ret_val;
2557 
2558 		/* load defaults for future use */
2559 		hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ?
2560 				((phy_data & CR_1000T_MS_VALUE) ?
2561 				e1000_ms_force_master :
2562 				e1000_ms_force_slave) :
2563 				e1000_ms_auto;
2564 
2565 		switch (phy_ms_setting) {
2566 		case e1000_ms_force_master:
2567 			phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
2568 			break;
2569 		case e1000_ms_force_slave:
2570 			phy_data |= CR_1000T_MS_ENABLE;
2571 			phy_data &= ~(CR_1000T_MS_VALUE);
2572 			break;
2573 		case e1000_ms_auto:
2574 			phy_data &= ~CR_1000T_MS_ENABLE;
2575 		default:
2576 			break;
2577 		}
2578 		ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
2579 		if (ret_val)
2580 			return ret_val;
2581 	}
2582 
2583 	return E1000_SUCCESS;
2584 }
2585 
2586 /*****************************************************************************
2587  * This function checks the mode of the firmware.
2588  *
2589  * returns  - true when the mode is IAMT or false.
2590  ****************************************************************************/
2591 bool
2592 e1000_check_mng_mode(struct e1000_hw *hw)
2593 {
2594 	uint32_t fwsm;
2595 	DEBUGFUNC();
2596 
2597 	fwsm = E1000_READ_REG(hw, FWSM);
2598 
2599 	if (hw->mac_type == e1000_ich8lan) {
2600 		if ((fwsm & E1000_FWSM_MODE_MASK) ==
2601 		    (E1000_MNG_ICH_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
2602 			return true;
2603 	} else if ((fwsm & E1000_FWSM_MODE_MASK) ==
2604 		       (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
2605 			return true;
2606 
2607 	return false;
2608 }
2609 
2610 static int32_t
2611 e1000_write_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t data)
2612 {
2613 	uint16_t swfw = E1000_SWFW_PHY0_SM;
2614 	uint32_t reg_val;
2615 	DEBUGFUNC();
2616 
2617 	if (e1000_is_second_port(hw))
2618 		swfw = E1000_SWFW_PHY1_SM;
2619 
2620 	if (e1000_swfw_sync_acquire(hw, swfw))
2621 		return -E1000_ERR_SWFW_SYNC;
2622 
2623 	reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT)
2624 			& E1000_KUMCTRLSTA_OFFSET) | data;
2625 	E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val);
2626 	udelay(2);
2627 
2628 	return E1000_SUCCESS;
2629 }
2630 
2631 static int32_t
2632 e1000_read_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *data)
2633 {
2634 	uint16_t swfw = E1000_SWFW_PHY0_SM;
2635 	uint32_t reg_val;
2636 	DEBUGFUNC();
2637 
2638 	if (e1000_is_second_port(hw))
2639 		swfw = E1000_SWFW_PHY1_SM;
2640 
2641 	if (e1000_swfw_sync_acquire(hw, swfw)) {
2642 		debug("%s[%i]\n", __func__, __LINE__);
2643 		return -E1000_ERR_SWFW_SYNC;
2644 	}
2645 
2646 	/* Write register address */
2647 	reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) &
2648 			E1000_KUMCTRLSTA_OFFSET) | E1000_KUMCTRLSTA_REN;
2649 	E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val);
2650 	udelay(2);
2651 
2652 	/* Read the data returned */
2653 	reg_val = E1000_READ_REG(hw, KUMCTRLSTA);
2654 	*data = (uint16_t)reg_val;
2655 
2656 	return E1000_SUCCESS;
2657 }
2658 
2659 /********************************************************************
2660 * Copper link setup for e1000_phy_gg82563 series.
2661 *
2662 * hw - Struct containing variables accessed by shared code
2663 *********************************************************************/
2664 static int32_t
2665 e1000_copper_link_ggp_setup(struct e1000_hw *hw)
2666 {
2667 	int32_t ret_val;
2668 	uint16_t phy_data;
2669 	uint32_t reg_data;
2670 
2671 	DEBUGFUNC();
2672 
2673 	if (!hw->phy_reset_disable) {
2674 		/* Enable CRS on TX for half-duplex operation. */
2675 		ret_val = e1000_read_phy_reg(hw,
2676 				GG82563_PHY_MAC_SPEC_CTRL, &phy_data);
2677 		if (ret_val)
2678 			return ret_val;
2679 
2680 		phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
2681 		/* Use 25MHz for both link down and 1000BASE-T for Tx clock */
2682 		phy_data |= GG82563_MSCR_TX_CLK_1000MBPS_25MHZ;
2683 
2684 		ret_val = e1000_write_phy_reg(hw,
2685 				GG82563_PHY_MAC_SPEC_CTRL, phy_data);
2686 		if (ret_val)
2687 			return ret_val;
2688 
2689 		/* Options:
2690 		 *   MDI/MDI-X = 0 (default)
2691 		 *   0 - Auto for all speeds
2692 		 *   1 - MDI mode
2693 		 *   2 - MDI-X mode
2694 		 *   3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
2695 		 */
2696 		ret_val = e1000_read_phy_reg(hw,
2697 				GG82563_PHY_SPEC_CTRL, &phy_data);
2698 		if (ret_val)
2699 			return ret_val;
2700 
2701 		phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK;
2702 
2703 		switch (hw->mdix) {
2704 		case 1:
2705 			phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDI;
2706 			break;
2707 		case 2:
2708 			phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDIX;
2709 			break;
2710 		case 0:
2711 		default:
2712 			phy_data |= GG82563_PSCR_CROSSOVER_MODE_AUTO;
2713 			break;
2714 		}
2715 
2716 		/* Options:
2717 		 *   disable_polarity_correction = 0 (default)
2718 		 *       Automatic Correction for Reversed Cable Polarity
2719 		 *   0 - Disabled
2720 		 *   1 - Enabled
2721 		 */
2722 		phy_data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
2723 		ret_val = e1000_write_phy_reg(hw,
2724 				GG82563_PHY_SPEC_CTRL, phy_data);
2725 
2726 		if (ret_val)
2727 			return ret_val;
2728 
2729 		/* SW Reset the PHY so all changes take effect */
2730 		ret_val = e1000_phy_reset(hw);
2731 		if (ret_val) {
2732 			DEBUGOUT("Error Resetting the PHY\n");
2733 			return ret_val;
2734 		}
2735 	} /* phy_reset_disable */
2736 
2737 	if (hw->mac_type == e1000_80003es2lan) {
2738 		/* Bypass RX and TX FIFO's */
2739 		ret_val = e1000_write_kmrn_reg(hw,
2740 				E1000_KUMCTRLSTA_OFFSET_FIFO_CTRL,
2741 				E1000_KUMCTRLSTA_FIFO_CTRL_RX_BYPASS
2742 				| E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS);
2743 		if (ret_val)
2744 			return ret_val;
2745 
2746 		ret_val = e1000_read_phy_reg(hw,
2747 				GG82563_PHY_SPEC_CTRL_2, &phy_data);
2748 		if (ret_val)
2749 			return ret_val;
2750 
2751 		phy_data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG;
2752 		ret_val = e1000_write_phy_reg(hw,
2753 				GG82563_PHY_SPEC_CTRL_2, phy_data);
2754 
2755 		if (ret_val)
2756 			return ret_val;
2757 
2758 		reg_data = E1000_READ_REG(hw, CTRL_EXT);
2759 		reg_data &= ~(E1000_CTRL_EXT_LINK_MODE_MASK);
2760 		E1000_WRITE_REG(hw, CTRL_EXT, reg_data);
2761 
2762 		ret_val = e1000_read_phy_reg(hw,
2763 				GG82563_PHY_PWR_MGMT_CTRL, &phy_data);
2764 		if (ret_val)
2765 			return ret_val;
2766 
2767 	/* Do not init these registers when the HW is in IAMT mode, since the
2768 	 * firmware will have already initialized them.  We only initialize
2769 	 * them if the HW is not in IAMT mode.
2770 	 */
2771 		if (e1000_check_mng_mode(hw) == false) {
2772 			/* Enable Electrical Idle on the PHY */
2773 			phy_data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE;
2774 			ret_val = e1000_write_phy_reg(hw,
2775 					GG82563_PHY_PWR_MGMT_CTRL, phy_data);
2776 			if (ret_val)
2777 				return ret_val;
2778 
2779 			ret_val = e1000_read_phy_reg(hw,
2780 					GG82563_PHY_KMRN_MODE_CTRL, &phy_data);
2781 			if (ret_val)
2782 				return ret_val;
2783 
2784 			phy_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
2785 			ret_val = e1000_write_phy_reg(hw,
2786 					GG82563_PHY_KMRN_MODE_CTRL, phy_data);
2787 
2788 			if (ret_val)
2789 				return ret_val;
2790 		}
2791 
2792 		/* Workaround: Disable padding in Kumeran interface in the MAC
2793 		 * and in the PHY to avoid CRC errors.
2794 		 */
2795 		ret_val = e1000_read_phy_reg(hw,
2796 				GG82563_PHY_INBAND_CTRL, &phy_data);
2797 		if (ret_val)
2798 			return ret_val;
2799 		phy_data |= GG82563_ICR_DIS_PADDING;
2800 		ret_val = e1000_write_phy_reg(hw,
2801 				GG82563_PHY_INBAND_CTRL, phy_data);
2802 		if (ret_val)
2803 			return ret_val;
2804 	}
2805 	return E1000_SUCCESS;
2806 }
2807 
2808 /********************************************************************
2809 * Copper link setup for e1000_phy_m88 series.
2810 *
2811 * hw - Struct containing variables accessed by shared code
2812 *********************************************************************/
2813 static int32_t
2814 e1000_copper_link_mgp_setup(struct e1000_hw *hw)
2815 {
2816 	int32_t ret_val;
2817 	uint16_t phy_data;
2818 
2819 	DEBUGFUNC();
2820 
2821 	if (hw->phy_reset_disable)
2822 		return E1000_SUCCESS;
2823 
2824 	/* Enable CRS on TX. This must be set for half-duplex operation. */
2825 	ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
2826 	if (ret_val)
2827 		return ret_val;
2828 
2829 	phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
2830 
2831 	/* Options:
2832 	 *   MDI/MDI-X = 0 (default)
2833 	 *   0 - Auto for all speeds
2834 	 *   1 - MDI mode
2835 	 *   2 - MDI-X mode
2836 	 *   3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
2837 	 */
2838 	phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
2839 
2840 	switch (hw->mdix) {
2841 	case 1:
2842 		phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
2843 		break;
2844 	case 2:
2845 		phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
2846 		break;
2847 	case 3:
2848 		phy_data |= M88E1000_PSCR_AUTO_X_1000T;
2849 		break;
2850 	case 0:
2851 	default:
2852 		phy_data |= M88E1000_PSCR_AUTO_X_MODE;
2853 		break;
2854 	}
2855 
2856 	/* Options:
2857 	 *   disable_polarity_correction = 0 (default)
2858 	 *       Automatic Correction for Reversed Cable Polarity
2859 	 *   0 - Disabled
2860 	 *   1 - Enabled
2861 	 */
2862 	phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
2863 	ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
2864 	if (ret_val)
2865 		return ret_val;
2866 
2867 	if (hw->phy_revision < M88E1011_I_REV_4) {
2868 		/* Force TX_CLK in the Extended PHY Specific Control Register
2869 		 * to 25MHz clock.
2870 		 */
2871 		ret_val = e1000_read_phy_reg(hw,
2872 				M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
2873 		if (ret_val)
2874 			return ret_val;
2875 
2876 		phy_data |= M88E1000_EPSCR_TX_CLK_25;
2877 
2878 		if ((hw->phy_revision == E1000_REVISION_2) &&
2879 			(hw->phy_id == M88E1111_I_PHY_ID)) {
2880 			/* Vidalia Phy, set the downshift counter to 5x */
2881 			phy_data &= ~(M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK);
2882 			phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
2883 			ret_val = e1000_write_phy_reg(hw,
2884 					M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
2885 			if (ret_val)
2886 				return ret_val;
2887 		} else {
2888 			/* Configure Master and Slave downshift values */
2889 			phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK
2890 					| M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
2891 			phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X
2892 					| M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
2893 			ret_val = e1000_write_phy_reg(hw,
2894 					M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
2895 			if (ret_val)
2896 				return ret_val;
2897 		}
2898 	}
2899 
2900 	/* SW Reset the PHY so all changes take effect */
2901 	ret_val = e1000_phy_reset(hw);
2902 	if (ret_val) {
2903 		DEBUGOUT("Error Resetting the PHY\n");
2904 		return ret_val;
2905 	}
2906 
2907 	return E1000_SUCCESS;
2908 }
2909 
2910 /********************************************************************
2911 * Setup auto-negotiation and flow control advertisements,
2912 * and then perform auto-negotiation.
2913 *
2914 * hw - Struct containing variables accessed by shared code
2915 *********************************************************************/
2916 static int32_t
2917 e1000_copper_link_autoneg(struct e1000_hw *hw)
2918 {
2919 	int32_t ret_val;
2920 	uint16_t phy_data;
2921 
2922 	DEBUGFUNC();
2923 
2924 	/* Perform some bounds checking on the hw->autoneg_advertised
2925 	 * parameter.  If this variable is zero, then set it to the default.
2926 	 */
2927 	hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT;
2928 
2929 	/* If autoneg_advertised is zero, we assume it was not defaulted
2930 	 * by the calling code so we set to advertise full capability.
2931 	 */
2932 	if (hw->autoneg_advertised == 0)
2933 		hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
2934 
2935 	/* IFE phy only supports 10/100 */
2936 	if (hw->phy_type == e1000_phy_ife)
2937 		hw->autoneg_advertised &= AUTONEG_ADVERTISE_10_100_ALL;
2938 
2939 	DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
2940 	ret_val = e1000_phy_setup_autoneg(hw);
2941 	if (ret_val) {
2942 		DEBUGOUT("Error Setting up Auto-Negotiation\n");
2943 		return ret_val;
2944 	}
2945 	DEBUGOUT("Restarting Auto-Neg\n");
2946 
2947 	/* Restart auto-negotiation by setting the Auto Neg Enable bit and
2948 	 * the Auto Neg Restart bit in the PHY control register.
2949 	 */
2950 	ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
2951 	if (ret_val)
2952 		return ret_val;
2953 
2954 	phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
2955 	ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
2956 	if (ret_val)
2957 		return ret_val;
2958 
2959 	/* Does the user want to wait for Auto-Neg to complete here, or
2960 	 * check at a later time (for example, callback routine).
2961 	 */
2962 	/* If we do not wait for autonegtation to complete I
2963 	 * do not see a valid link status.
2964 	 * wait_autoneg_complete = 1 .
2965 	 */
2966 	if (hw->wait_autoneg_complete) {
2967 		ret_val = e1000_wait_autoneg(hw);
2968 		if (ret_val) {
2969 			DEBUGOUT("Error while waiting for autoneg"
2970 					"to complete\n");
2971 			return ret_val;
2972 		}
2973 	}
2974 
2975 	hw->get_link_status = true;
2976 
2977 	return E1000_SUCCESS;
2978 }
2979 
2980 /******************************************************************************
2981 * Config the MAC and the PHY after link is up.
2982 *   1) Set up the MAC to the current PHY speed/duplex
2983 *      if we are on 82543.  If we
2984 *      are on newer silicon, we only need to configure
2985 *      collision distance in the Transmit Control Register.
2986 *   2) Set up flow control on the MAC to that established with
2987 *      the link partner.
2988 *   3) Config DSP to improve Gigabit link quality for some PHY revisions.
2989 *
2990 * hw - Struct containing variables accessed by shared code
2991 ******************************************************************************/
2992 static int32_t
2993 e1000_copper_link_postconfig(struct e1000_hw *hw)
2994 {
2995 	int32_t ret_val;
2996 	DEBUGFUNC();
2997 
2998 	if (hw->mac_type >= e1000_82544) {
2999 		e1000_config_collision_dist(hw);
3000 	} else {
3001 		ret_val = e1000_config_mac_to_phy(hw);
3002 		if (ret_val) {
3003 			DEBUGOUT("Error configuring MAC to PHY settings\n");
3004 			return ret_val;
3005 		}
3006 	}
3007 	ret_val = e1000_config_fc_after_link_up(hw);
3008 	if (ret_val) {
3009 		DEBUGOUT("Error Configuring Flow Control\n");
3010 		return ret_val;
3011 	}
3012 	return E1000_SUCCESS;
3013 }
3014 
3015 /******************************************************************************
3016 * Detects which PHY is present and setup the speed and duplex
3017 *
3018 * hw - Struct containing variables accessed by shared code
3019 ******************************************************************************/
3020 static int
3021 e1000_setup_copper_link(struct e1000_hw *hw)
3022 {
3023 	int32_t ret_val;
3024 	uint16_t i;
3025 	uint16_t phy_data;
3026 	uint16_t reg_data;
3027 
3028 	DEBUGFUNC();
3029 
3030 	switch (hw->mac_type) {
3031 	case e1000_80003es2lan:
3032 	case e1000_ich8lan:
3033 		/* Set the mac to wait the maximum time between each
3034 		 * iteration and increase the max iterations when
3035 		 * polling the phy; this fixes erroneous timeouts at 10Mbps. */
3036 		ret_val = e1000_write_kmrn_reg(hw,
3037 				GG82563_REG(0x34, 4), 0xFFFF);
3038 		if (ret_val)
3039 			return ret_val;
3040 		ret_val = e1000_read_kmrn_reg(hw,
3041 				GG82563_REG(0x34, 9), &reg_data);
3042 		if (ret_val)
3043 			return ret_val;
3044 		reg_data |= 0x3F;
3045 		ret_val = e1000_write_kmrn_reg(hw,
3046 				GG82563_REG(0x34, 9), reg_data);
3047 		if (ret_val)
3048 			return ret_val;
3049 	default:
3050 		break;
3051 	}
3052 
3053 	/* Check if it is a valid PHY and set PHY mode if necessary. */
3054 	ret_val = e1000_copper_link_preconfig(hw);
3055 	if (ret_val)
3056 		return ret_val;
3057 	switch (hw->mac_type) {
3058 	case e1000_80003es2lan:
3059 		/* Kumeran registers are written-only */
3060 		reg_data =
3061 		E1000_KUMCTRLSTA_INB_CTRL_LINK_STATUS_TX_TIMEOUT_DEFAULT;
3062 		reg_data |= E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING;
3063 		ret_val = e1000_write_kmrn_reg(hw,
3064 				E1000_KUMCTRLSTA_OFFSET_INB_CTRL, reg_data);
3065 		if (ret_val)
3066 			return ret_val;
3067 		break;
3068 	default:
3069 		break;
3070 	}
3071 
3072 	if (hw->phy_type == e1000_phy_igp ||
3073 		hw->phy_type == e1000_phy_igp_3 ||
3074 		hw->phy_type == e1000_phy_igp_2) {
3075 		ret_val = e1000_copper_link_igp_setup(hw);
3076 		if (ret_val)
3077 			return ret_val;
3078 	} else if (hw->phy_type == e1000_phy_m88 ||
3079 		hw->phy_type == e1000_phy_igb) {
3080 		ret_val = e1000_copper_link_mgp_setup(hw);
3081 		if (ret_val)
3082 			return ret_val;
3083 	} else if (hw->phy_type == e1000_phy_gg82563) {
3084 		ret_val = e1000_copper_link_ggp_setup(hw);
3085 		if (ret_val)
3086 			return ret_val;
3087 	}
3088 
3089 	/* always auto */
3090 	/* Setup autoneg and flow control advertisement
3091 	  * and perform autonegotiation */
3092 	ret_val = e1000_copper_link_autoneg(hw);
3093 	if (ret_val)
3094 		return ret_val;
3095 
3096 	/* Check link status. Wait up to 100 microseconds for link to become
3097 	 * valid.
3098 	 */
3099 	for (i = 0; i < 10; i++) {
3100 		ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3101 		if (ret_val)
3102 			return ret_val;
3103 		ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3104 		if (ret_val)
3105 			return ret_val;
3106 
3107 		if (phy_data & MII_SR_LINK_STATUS) {
3108 			/* Config the MAC and PHY after link is up */
3109 			ret_val = e1000_copper_link_postconfig(hw);
3110 			if (ret_val)
3111 				return ret_val;
3112 
3113 			DEBUGOUT("Valid link established!!!\n");
3114 			return E1000_SUCCESS;
3115 		}
3116 		udelay(10);
3117 	}
3118 
3119 	DEBUGOUT("Unable to establish link!!!\n");
3120 	return E1000_SUCCESS;
3121 }
3122 
3123 /******************************************************************************
3124 * Configures PHY autoneg and flow control advertisement settings
3125 *
3126 * hw - Struct containing variables accessed by shared code
3127 ******************************************************************************/
3128 int32_t
3129 e1000_phy_setup_autoneg(struct e1000_hw *hw)
3130 {
3131 	int32_t ret_val;
3132 	uint16_t mii_autoneg_adv_reg;
3133 	uint16_t mii_1000t_ctrl_reg;
3134 
3135 	DEBUGFUNC();
3136 
3137 	/* Read the MII Auto-Neg Advertisement Register (Address 4). */
3138 	ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
3139 	if (ret_val)
3140 		return ret_val;
3141 
3142 	if (hw->phy_type != e1000_phy_ife) {
3143 		/* Read the MII 1000Base-T Control Register (Address 9). */
3144 		ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL,
3145 				&mii_1000t_ctrl_reg);
3146 		if (ret_val)
3147 			return ret_val;
3148 	} else
3149 		mii_1000t_ctrl_reg = 0;
3150 
3151 	/* Need to parse both autoneg_advertised and fc and set up
3152 	 * the appropriate PHY registers.  First we will parse for
3153 	 * autoneg_advertised software override.  Since we can advertise
3154 	 * a plethora of combinations, we need to check each bit
3155 	 * individually.
3156 	 */
3157 
3158 	/* First we clear all the 10/100 mb speed bits in the Auto-Neg
3159 	 * Advertisement Register (Address 4) and the 1000 mb speed bits in
3160 	 * the  1000Base-T Control Register (Address 9).
3161 	 */
3162 	mii_autoneg_adv_reg &= ~REG4_SPEED_MASK;
3163 	mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK;
3164 
3165 	DEBUGOUT("autoneg_advertised %x\n", hw->autoneg_advertised);
3166 
3167 	/* Do we want to advertise 10 Mb Half Duplex? */
3168 	if (hw->autoneg_advertised & ADVERTISE_10_HALF) {
3169 		DEBUGOUT("Advertise 10mb Half duplex\n");
3170 		mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
3171 	}
3172 
3173 	/* Do we want to advertise 10 Mb Full Duplex? */
3174 	if (hw->autoneg_advertised & ADVERTISE_10_FULL) {
3175 		DEBUGOUT("Advertise 10mb Full duplex\n");
3176 		mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
3177 	}
3178 
3179 	/* Do we want to advertise 100 Mb Half Duplex? */
3180 	if (hw->autoneg_advertised & ADVERTISE_100_HALF) {
3181 		DEBUGOUT("Advertise 100mb Half duplex\n");
3182 		mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
3183 	}
3184 
3185 	/* Do we want to advertise 100 Mb Full Duplex? */
3186 	if (hw->autoneg_advertised & ADVERTISE_100_FULL) {
3187 		DEBUGOUT("Advertise 100mb Full duplex\n");
3188 		mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
3189 	}
3190 
3191 	/* We do not allow the Phy to advertise 1000 Mb Half Duplex */
3192 	if (hw->autoneg_advertised & ADVERTISE_1000_HALF) {
3193 		DEBUGOUT
3194 		    ("Advertise 1000mb Half duplex requested, request denied!\n");
3195 	}
3196 
3197 	/* Do we want to advertise 1000 Mb Full Duplex? */
3198 	if (hw->autoneg_advertised & ADVERTISE_1000_FULL) {
3199 		DEBUGOUT("Advertise 1000mb Full duplex\n");
3200 		mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
3201 	}
3202 
3203 	/* Check for a software override of the flow control settings, and
3204 	 * setup the PHY advertisement registers accordingly.  If
3205 	 * auto-negotiation is enabled, then software will have to set the
3206 	 * "PAUSE" bits to the correct value in the Auto-Negotiation
3207 	 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation.
3208 	 *
3209 	 * The possible values of the "fc" parameter are:
3210 	 *	0:  Flow control is completely disabled
3211 	 *	1:  Rx flow control is enabled (we can receive pause frames
3212 	 *	    but not send pause frames).
3213 	 *	2:  Tx flow control is enabled (we can send pause frames
3214 	 *	    but we do not support receiving pause frames).
3215 	 *	3:  Both Rx and TX flow control (symmetric) are enabled.
3216 	 *  other:  No software override.  The flow control configuration
3217 	 *	    in the EEPROM is used.
3218 	 */
3219 	switch (hw->fc) {
3220 	case e1000_fc_none:	/* 0 */
3221 		/* Flow control (RX & TX) is completely disabled by a
3222 		 * software over-ride.
3223 		 */
3224 		mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
3225 		break;
3226 	case e1000_fc_rx_pause:	/* 1 */
3227 		/* RX Flow control is enabled, and TX Flow control is
3228 		 * disabled, by a software over-ride.
3229 		 */
3230 		/* Since there really isn't a way to advertise that we are
3231 		 * capable of RX Pause ONLY, we will advertise that we
3232 		 * support both symmetric and asymmetric RX PAUSE.  Later
3233 		 * (in e1000_config_fc_after_link_up) we will disable the
3234 		 *hw's ability to send PAUSE frames.
3235 		 */
3236 		mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
3237 		break;
3238 	case e1000_fc_tx_pause:	/* 2 */
3239 		/* TX Flow control is enabled, and RX Flow control is
3240 		 * disabled, by a software over-ride.
3241 		 */
3242 		mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
3243 		mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
3244 		break;
3245 	case e1000_fc_full:	/* 3 */
3246 		/* Flow control (both RX and TX) is enabled by a software
3247 		 * over-ride.
3248 		 */
3249 		mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
3250 		break;
3251 	default:
3252 		DEBUGOUT("Flow control param set incorrectly\n");
3253 		return -E1000_ERR_CONFIG;
3254 	}
3255 
3256 	ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
3257 	if (ret_val)
3258 		return ret_val;
3259 
3260 	DEBUGOUT("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
3261 
3262 	if (hw->phy_type != e1000_phy_ife) {
3263 		ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL,
3264 				mii_1000t_ctrl_reg);
3265 		if (ret_val)
3266 			return ret_val;
3267 	}
3268 
3269 	return E1000_SUCCESS;
3270 }
3271 
3272 /******************************************************************************
3273 * Sets the collision distance in the Transmit Control register
3274 *
3275 * hw - Struct containing variables accessed by shared code
3276 *
3277 * Link should have been established previously. Reads the speed and duplex
3278 * information from the Device Status register.
3279 ******************************************************************************/
3280 static void
3281 e1000_config_collision_dist(struct e1000_hw *hw)
3282 {
3283 	uint32_t tctl, coll_dist;
3284 
3285 	DEBUGFUNC();
3286 
3287 	if (hw->mac_type < e1000_82543)
3288 		coll_dist = E1000_COLLISION_DISTANCE_82542;
3289 	else
3290 		coll_dist = E1000_COLLISION_DISTANCE;
3291 
3292 	tctl = E1000_READ_REG(hw, TCTL);
3293 
3294 	tctl &= ~E1000_TCTL_COLD;
3295 	tctl |= coll_dist << E1000_COLD_SHIFT;
3296 
3297 	E1000_WRITE_REG(hw, TCTL, tctl);
3298 	E1000_WRITE_FLUSH(hw);
3299 }
3300 
3301 /******************************************************************************
3302 * Sets MAC speed and duplex settings to reflect the those in the PHY
3303 *
3304 * hw - Struct containing variables accessed by shared code
3305 * mii_reg - data to write to the MII control register
3306 *
3307 * The contents of the PHY register containing the needed information need to
3308 * be passed in.
3309 ******************************************************************************/
3310 static int
3311 e1000_config_mac_to_phy(struct e1000_hw *hw)
3312 {
3313 	uint32_t ctrl;
3314 	uint16_t phy_data;
3315 
3316 	DEBUGFUNC();
3317 
3318 	/* Read the Device Control Register and set the bits to Force Speed
3319 	 * and Duplex.
3320 	 */
3321 	ctrl = E1000_READ_REG(hw, CTRL);
3322 	ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
3323 	ctrl &= ~(E1000_CTRL_ILOS);
3324 	ctrl |= (E1000_CTRL_SPD_SEL);
3325 
3326 	/* Set up duplex in the Device Control and Transmit Control
3327 	 * registers depending on negotiated values.
3328 	 */
3329 	if (e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data) < 0) {
3330 		DEBUGOUT("PHY Read Error\n");
3331 		return -E1000_ERR_PHY;
3332 	}
3333 	if (phy_data & M88E1000_PSSR_DPLX)
3334 		ctrl |= E1000_CTRL_FD;
3335 	else
3336 		ctrl &= ~E1000_CTRL_FD;
3337 
3338 	e1000_config_collision_dist(hw);
3339 
3340 	/* Set up speed in the Device Control register depending on
3341 	 * negotiated values.
3342 	 */
3343 	if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)
3344 		ctrl |= E1000_CTRL_SPD_1000;
3345 	else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS)
3346 		ctrl |= E1000_CTRL_SPD_100;
3347 	/* Write the configured values back to the Device Control Reg. */
3348 	E1000_WRITE_REG(hw, CTRL, ctrl);
3349 	return 0;
3350 }
3351 
3352 /******************************************************************************
3353  * Forces the MAC's flow control settings.
3354  *
3355  * hw - Struct containing variables accessed by shared code
3356  *
3357  * Sets the TFCE and RFCE bits in the device control register to reflect
3358  * the adapter settings. TFCE and RFCE need to be explicitly set by
3359  * software when a Copper PHY is used because autonegotiation is managed
3360  * by the PHY rather than the MAC. Software must also configure these
3361  * bits when link is forced on a fiber connection.
3362  *****************************************************************************/
3363 static int
3364 e1000_force_mac_fc(struct e1000_hw *hw)
3365 {
3366 	uint32_t ctrl;
3367 
3368 	DEBUGFUNC();
3369 
3370 	/* Get the current configuration of the Device Control Register */
3371 	ctrl = E1000_READ_REG(hw, CTRL);
3372 
3373 	/* Because we didn't get link via the internal auto-negotiation
3374 	 * mechanism (we either forced link or we got link via PHY
3375 	 * auto-neg), we have to manually enable/disable transmit an
3376 	 * receive flow control.
3377 	 *
3378 	 * The "Case" statement below enables/disable flow control
3379 	 * according to the "hw->fc" parameter.
3380 	 *
3381 	 * The possible values of the "fc" parameter are:
3382 	 *	0:  Flow control is completely disabled
3383 	 *	1:  Rx flow control is enabled (we can receive pause
3384 	 *	    frames but not send pause frames).
3385 	 *	2:  Tx flow control is enabled (we can send pause frames
3386 	 *	    frames but we do not receive pause frames).
3387 	 *	3:  Both Rx and TX flow control (symmetric) is enabled.
3388 	 *  other:  No other values should be possible at this point.
3389 	 */
3390 
3391 	switch (hw->fc) {
3392 	case e1000_fc_none:
3393 		ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
3394 		break;
3395 	case e1000_fc_rx_pause:
3396 		ctrl &= (~E1000_CTRL_TFCE);
3397 		ctrl |= E1000_CTRL_RFCE;
3398 		break;
3399 	case e1000_fc_tx_pause:
3400 		ctrl &= (~E1000_CTRL_RFCE);
3401 		ctrl |= E1000_CTRL_TFCE;
3402 		break;
3403 	case e1000_fc_full:
3404 		ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
3405 		break;
3406 	default:
3407 		DEBUGOUT("Flow control param set incorrectly\n");
3408 		return -E1000_ERR_CONFIG;
3409 	}
3410 
3411 	/* Disable TX Flow Control for 82542 (rev 2.0) */
3412 	if (hw->mac_type == e1000_82542_rev2_0)
3413 		ctrl &= (~E1000_CTRL_TFCE);
3414 
3415 	E1000_WRITE_REG(hw, CTRL, ctrl);
3416 	return 0;
3417 }
3418 
3419 /******************************************************************************
3420  * Configures flow control settings after link is established
3421  *
3422  * hw - Struct containing variables accessed by shared code
3423  *
3424  * Should be called immediately after a valid link has been established.
3425  * Forces MAC flow control settings if link was forced. When in MII/GMII mode
3426  * and autonegotiation is enabled, the MAC flow control settings will be set
3427  * based on the flow control negotiated by the PHY. In TBI mode, the TFCE
3428  * and RFCE bits will be automaticaly set to the negotiated flow control mode.
3429  *****************************************************************************/
3430 static int32_t
3431 e1000_config_fc_after_link_up(struct e1000_hw *hw)
3432 {
3433 	int32_t ret_val;
3434 	uint16_t mii_status_reg;
3435 	uint16_t mii_nway_adv_reg;
3436 	uint16_t mii_nway_lp_ability_reg;
3437 	uint16_t speed;
3438 	uint16_t duplex;
3439 
3440 	DEBUGFUNC();
3441 
3442 	/* Check for the case where we have fiber media and auto-neg failed
3443 	 * so we had to force link.  In this case, we need to force the
3444 	 * configuration of the MAC to match the "fc" parameter.
3445 	 */
3446 	if (((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed))
3447 		|| ((hw->media_type == e1000_media_type_internal_serdes)
3448 		&& (hw->autoneg_failed))
3449 		|| ((hw->media_type == e1000_media_type_copper)
3450 		&& (!hw->autoneg))) {
3451 		ret_val = e1000_force_mac_fc(hw);
3452 		if (ret_val < 0) {
3453 			DEBUGOUT("Error forcing flow control settings\n");
3454 			return ret_val;
3455 		}
3456 	}
3457 
3458 	/* Check for the case where we have copper media and auto-neg is
3459 	 * enabled.  In this case, we need to check and see if Auto-Neg
3460 	 * has completed, and if so, how the PHY and link partner has
3461 	 * flow control configured.
3462 	 */
3463 	if (hw->media_type == e1000_media_type_copper) {
3464 		/* Read the MII Status Register and check to see if AutoNeg
3465 		 * has completed.  We read this twice because this reg has
3466 		 * some "sticky" (latched) bits.
3467 		 */
3468 		if (e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) {
3469 			DEBUGOUT("PHY Read Error\n");
3470 			return -E1000_ERR_PHY;
3471 		}
3472 		if (e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) {
3473 			DEBUGOUT("PHY Read Error\n");
3474 			return -E1000_ERR_PHY;
3475 		}
3476 
3477 		if (mii_status_reg & MII_SR_AUTONEG_COMPLETE) {
3478 			/* The AutoNeg process has completed, so we now need to
3479 			 * read both the Auto Negotiation Advertisement Register
3480 			 * (Address 4) and the Auto_Negotiation Base Page Ability
3481 			 * Register (Address 5) to determine how flow control was
3482 			 * negotiated.
3483 			 */
3484 			if (e1000_read_phy_reg
3485 			    (hw, PHY_AUTONEG_ADV, &mii_nway_adv_reg) < 0) {
3486 				DEBUGOUT("PHY Read Error\n");
3487 				return -E1000_ERR_PHY;
3488 			}
3489 			if (e1000_read_phy_reg
3490 			    (hw, PHY_LP_ABILITY,
3491 			     &mii_nway_lp_ability_reg) < 0) {
3492 				DEBUGOUT("PHY Read Error\n");
3493 				return -E1000_ERR_PHY;
3494 			}
3495 
3496 			/* Two bits in the Auto Negotiation Advertisement Register
3497 			 * (Address 4) and two bits in the Auto Negotiation Base
3498 			 * Page Ability Register (Address 5) determine flow control
3499 			 * for both the PHY and the link partner.  The following
3500 			 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
3501 			 * 1999, describes these PAUSE resolution bits and how flow
3502 			 * control is determined based upon these settings.
3503 			 * NOTE:  DC = Don't Care
3504 			 *
3505 			 *   LOCAL DEVICE  |   LINK PARTNER
3506 			 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
3507 			 *-------|---------|-------|---------|--------------------
3508 			 *   0	 |    0    |  DC   |   DC    | e1000_fc_none
3509 			 *   0	 |    1    |   0   |   DC    | e1000_fc_none
3510 			 *   0	 |    1    |   1   |	0    | e1000_fc_none
3511 			 *   0	 |    1    |   1   |	1    | e1000_fc_tx_pause
3512 			 *   1	 |    0    |   0   |   DC    | e1000_fc_none
3513 			 *   1	 |   DC    |   1   |   DC    | e1000_fc_full
3514 			 *   1	 |    1    |   0   |	0    | e1000_fc_none
3515 			 *   1	 |    1    |   0   |	1    | e1000_fc_rx_pause
3516 			 *
3517 			 */
3518 			/* Are both PAUSE bits set to 1?  If so, this implies
3519 			 * Symmetric Flow Control is enabled at both ends.  The
3520 			 * ASM_DIR bits are irrelevant per the spec.
3521 			 *
3522 			 * For Symmetric Flow Control:
3523 			 *
3524 			 *   LOCAL DEVICE  |   LINK PARTNER
3525 			 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
3526 			 *-------|---------|-------|---------|--------------------
3527 			 *   1	 |   DC    |   1   |   DC    | e1000_fc_full
3528 			 *
3529 			 */
3530 			if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
3531 			    (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
3532 				/* Now we need to check if the user selected RX ONLY
3533 				 * of pause frames.  In this case, we had to advertise
3534 				 * FULL flow control because we could not advertise RX
3535 				 * ONLY. Hence, we must now check to see if we need to
3536 				 * turn OFF  the TRANSMISSION of PAUSE frames.
3537 				 */
3538 				if (hw->original_fc == e1000_fc_full) {
3539 					hw->fc = e1000_fc_full;
3540 					DEBUGOUT("Flow Control = FULL.\r\n");
3541 				} else {
3542 					hw->fc = e1000_fc_rx_pause;
3543 					DEBUGOUT
3544 					    ("Flow Control = RX PAUSE frames only.\r\n");
3545 				}
3546 			}
3547 			/* For receiving PAUSE frames ONLY.
3548 			 *
3549 			 *   LOCAL DEVICE  |   LINK PARTNER
3550 			 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
3551 			 *-------|---------|-------|---------|--------------------
3552 			 *   0	 |    1    |   1   |	1    | e1000_fc_tx_pause
3553 			 *
3554 			 */
3555 			else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
3556 				 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
3557 				 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
3558 				 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR))
3559 			{
3560 				hw->fc = e1000_fc_tx_pause;
3561 				DEBUGOUT
3562 				    ("Flow Control = TX PAUSE frames only.\r\n");
3563 			}
3564 			/* For transmitting PAUSE frames ONLY.
3565 			 *
3566 			 *   LOCAL DEVICE  |   LINK PARTNER
3567 			 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
3568 			 *-------|---------|-------|---------|--------------------
3569 			 *   1	 |    1    |   0   |	1    | e1000_fc_rx_pause
3570 			 *
3571 			 */
3572 			else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
3573 				 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
3574 				 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
3575 				 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR))
3576 			{
3577 				hw->fc = e1000_fc_rx_pause;
3578 				DEBUGOUT
3579 				    ("Flow Control = RX PAUSE frames only.\r\n");
3580 			}
3581 			/* Per the IEEE spec, at this point flow control should be
3582 			 * disabled.  However, we want to consider that we could
3583 			 * be connected to a legacy switch that doesn't advertise
3584 			 * desired flow control, but can be forced on the link
3585 			 * partner.  So if we advertised no flow control, that is
3586 			 * what we will resolve to.  If we advertised some kind of
3587 			 * receive capability (Rx Pause Only or Full Flow Control)
3588 			 * and the link partner advertised none, we will configure
3589 			 * ourselves to enable Rx Flow Control only.  We can do
3590 			 * this safely for two reasons:  If the link partner really
3591 			 * didn't want flow control enabled, and we enable Rx, no
3592 			 * harm done since we won't be receiving any PAUSE frames
3593 			 * anyway.  If the intent on the link partner was to have
3594 			 * flow control enabled, then by us enabling RX only, we
3595 			 * can at least receive pause frames and process them.
3596 			 * This is a good idea because in most cases, since we are
3597 			 * predominantly a server NIC, more times than not we will
3598 			 * be asked to delay transmission of packets than asking
3599 			 * our link partner to pause transmission of frames.
3600 			 */
3601 			else if (hw->original_fc == e1000_fc_none ||
3602 				 hw->original_fc == e1000_fc_tx_pause) {
3603 				hw->fc = e1000_fc_none;
3604 				DEBUGOUT("Flow Control = NONE.\r\n");
3605 			} else {
3606 				hw->fc = e1000_fc_rx_pause;
3607 				DEBUGOUT
3608 				    ("Flow Control = RX PAUSE frames only.\r\n");
3609 			}
3610 
3611 			/* Now we need to do one last check...	If we auto-
3612 			 * negotiated to HALF DUPLEX, flow control should not be
3613 			 * enabled per IEEE 802.3 spec.
3614 			 */
3615 			e1000_get_speed_and_duplex(hw, &speed, &duplex);
3616 
3617 			if (duplex == HALF_DUPLEX)
3618 				hw->fc = e1000_fc_none;
3619 
3620 			/* Now we call a subroutine to actually force the MAC
3621 			 * controller to use the correct flow control settings.
3622 			 */
3623 			ret_val = e1000_force_mac_fc(hw);
3624 			if (ret_val < 0) {
3625 				DEBUGOUT
3626 				    ("Error forcing flow control settings\n");
3627 				return ret_val;
3628 			}
3629 		} else {
3630 			DEBUGOUT
3631 			    ("Copper PHY and Auto Neg has not completed.\r\n");
3632 		}
3633 	}
3634 	return E1000_SUCCESS;
3635 }
3636 
3637 /******************************************************************************
3638  * Checks to see if the link status of the hardware has changed.
3639  *
3640  * hw - Struct containing variables accessed by shared code
3641  *
3642  * Called by any function that needs to check the link status of the adapter.
3643  *****************************************************************************/
3644 static int
3645 e1000_check_for_link(struct e1000_hw *hw)
3646 {
3647 	uint32_t rxcw;
3648 	uint32_t ctrl;
3649 	uint32_t status;
3650 	uint32_t rctl;
3651 	uint32_t signal;
3652 	int32_t ret_val;
3653 	uint16_t phy_data;
3654 	uint16_t lp_capability;
3655 
3656 	DEBUGFUNC();
3657 
3658 	/* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be
3659 	 * set when the optics detect a signal. On older adapters, it will be
3660 	 * cleared when there is a signal
3661 	 */
3662 	ctrl = E1000_READ_REG(hw, CTRL);
3663 	if ((hw->mac_type > e1000_82544) && !(ctrl & E1000_CTRL_ILOS))
3664 		signal = E1000_CTRL_SWDPIN1;
3665 	else
3666 		signal = 0;
3667 
3668 	status = E1000_READ_REG(hw, STATUS);
3669 	rxcw = E1000_READ_REG(hw, RXCW);
3670 	DEBUGOUT("ctrl: %#08x status %#08x rxcw %#08x\n", ctrl, status, rxcw);
3671 
3672 	/* If we have a copper PHY then we only want to go out to the PHY
3673 	 * registers to see if Auto-Neg has completed and/or if our link
3674 	 * status has changed.	The get_link_status flag will be set if we
3675 	 * receive a Link Status Change interrupt or we have Rx Sequence
3676 	 * Errors.
3677 	 */
3678 	if ((hw->media_type == e1000_media_type_copper) && hw->get_link_status) {
3679 		/* First we want to see if the MII Status Register reports
3680 		 * link.  If so, then we want to get the current speed/duplex
3681 		 * of the PHY.
3682 		 * Read the register twice since the link bit is sticky.
3683 		 */
3684 		if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
3685 			DEBUGOUT("PHY Read Error\n");
3686 			return -E1000_ERR_PHY;
3687 		}
3688 		if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
3689 			DEBUGOUT("PHY Read Error\n");
3690 			return -E1000_ERR_PHY;
3691 		}
3692 
3693 		if (phy_data & MII_SR_LINK_STATUS) {
3694 			hw->get_link_status = false;
3695 		} else {
3696 			/* No link detected */
3697 			return -E1000_ERR_NOLINK;
3698 		}
3699 
3700 		/* We have a M88E1000 PHY and Auto-Neg is enabled.  If we
3701 		 * have Si on board that is 82544 or newer, Auto
3702 		 * Speed Detection takes care of MAC speed/duplex
3703 		 * configuration.  So we only need to configure Collision
3704 		 * Distance in the MAC.  Otherwise, we need to force
3705 		 * speed/duplex on the MAC to the current PHY speed/duplex
3706 		 * settings.
3707 		 */
3708 		if (hw->mac_type >= e1000_82544)
3709 			e1000_config_collision_dist(hw);
3710 		else {
3711 			ret_val = e1000_config_mac_to_phy(hw);
3712 			if (ret_val < 0) {
3713 				DEBUGOUT
3714 				    ("Error configuring MAC to PHY settings\n");
3715 				return ret_val;
3716 			}
3717 		}
3718 
3719 		/* Configure Flow Control now that Auto-Neg has completed. First, we
3720 		 * need to restore the desired flow control settings because we may
3721 		 * have had to re-autoneg with a different link partner.
3722 		 */
3723 		ret_val = e1000_config_fc_after_link_up(hw);
3724 		if (ret_val < 0) {
3725 			DEBUGOUT("Error configuring flow control\n");
3726 			return ret_val;
3727 		}
3728 
3729 		/* At this point we know that we are on copper and we have
3730 		 * auto-negotiated link.  These are conditions for checking the link
3731 		 * parter capability register.	We use the link partner capability to
3732 		 * determine if TBI Compatibility needs to be turned on or off.  If
3733 		 * the link partner advertises any speed in addition to Gigabit, then
3734 		 * we assume that they are GMII-based, and TBI compatibility is not
3735 		 * needed. If no other speeds are advertised, we assume the link
3736 		 * partner is TBI-based, and we turn on TBI Compatibility.
3737 		 */
3738 		if (hw->tbi_compatibility_en) {
3739 			if (e1000_read_phy_reg
3740 			    (hw, PHY_LP_ABILITY, &lp_capability) < 0) {
3741 				DEBUGOUT("PHY Read Error\n");
3742 				return -E1000_ERR_PHY;
3743 			}
3744 			if (lp_capability & (NWAY_LPAR_10T_HD_CAPS |
3745 					     NWAY_LPAR_10T_FD_CAPS |
3746 					     NWAY_LPAR_100TX_HD_CAPS |
3747 					     NWAY_LPAR_100TX_FD_CAPS |
3748 					     NWAY_LPAR_100T4_CAPS)) {
3749 				/* If our link partner advertises anything in addition to
3750 				 * gigabit, we do not need to enable TBI compatibility.
3751 				 */
3752 				if (hw->tbi_compatibility_on) {
3753 					/* If we previously were in the mode, turn it off. */
3754 					rctl = E1000_READ_REG(hw, RCTL);
3755 					rctl &= ~E1000_RCTL_SBP;
3756 					E1000_WRITE_REG(hw, RCTL, rctl);
3757 					hw->tbi_compatibility_on = false;
3758 				}
3759 			} else {
3760 				/* If TBI compatibility is was previously off, turn it on. For
3761 				 * compatibility with a TBI link partner, we will store bad
3762 				 * packets. Some frames have an additional byte on the end and
3763 				 * will look like CRC errors to to the hardware.
3764 				 */
3765 				if (!hw->tbi_compatibility_on) {
3766 					hw->tbi_compatibility_on = true;
3767 					rctl = E1000_READ_REG(hw, RCTL);
3768 					rctl |= E1000_RCTL_SBP;
3769 					E1000_WRITE_REG(hw, RCTL, rctl);
3770 				}
3771 			}
3772 		}
3773 	}
3774 	/* If we don't have link (auto-negotiation failed or link partner cannot
3775 	 * auto-negotiate), the cable is plugged in (we have signal), and our
3776 	 * link partner is not trying to auto-negotiate with us (we are receiving
3777 	 * idles or data), we need to force link up. We also need to give
3778 	 * auto-negotiation time to complete, in case the cable was just plugged
3779 	 * in. The autoneg_failed flag does this.
3780 	 */
3781 	else if ((hw->media_type == e1000_media_type_fiber) &&
3782 		 (!(status & E1000_STATUS_LU)) &&
3783 		 ((ctrl & E1000_CTRL_SWDPIN1) == signal) &&
3784 		 (!(rxcw & E1000_RXCW_C))) {
3785 		if (hw->autoneg_failed == 0) {
3786 			hw->autoneg_failed = 1;
3787 			return 0;
3788 		}
3789 		DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\r\n");
3790 
3791 		/* Disable auto-negotiation in the TXCW register */
3792 		E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE));
3793 
3794 		/* Force link-up and also force full-duplex. */
3795 		ctrl = E1000_READ_REG(hw, CTRL);
3796 		ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
3797 		E1000_WRITE_REG(hw, CTRL, ctrl);
3798 
3799 		/* Configure Flow Control after forcing link up. */
3800 		ret_val = e1000_config_fc_after_link_up(hw);
3801 		if (ret_val < 0) {
3802 			DEBUGOUT("Error configuring flow control\n");
3803 			return ret_val;
3804 		}
3805 	}
3806 	/* If we are forcing link and we are receiving /C/ ordered sets, re-enable
3807 	 * auto-negotiation in the TXCW register and disable forced link in the
3808 	 * Device Control register in an attempt to auto-negotiate with our link
3809 	 * partner.
3810 	 */
3811 	else if ((hw->media_type == e1000_media_type_fiber) &&
3812 		 (ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
3813 		DEBUGOUT
3814 		    ("RXing /C/, enable AutoNeg and stop forcing link.\r\n");
3815 		E1000_WRITE_REG(hw, TXCW, hw->txcw);
3816 		E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU));
3817 	}
3818 	return 0;
3819 }
3820 
3821 /******************************************************************************
3822 * Configure the MAC-to-PHY interface for 10/100Mbps
3823 *
3824 * hw - Struct containing variables accessed by shared code
3825 ******************************************************************************/
3826 static int32_t
3827 e1000_configure_kmrn_for_10_100(struct e1000_hw *hw, uint16_t duplex)
3828 {
3829 	int32_t ret_val = E1000_SUCCESS;
3830 	uint32_t tipg;
3831 	uint16_t reg_data;
3832 
3833 	DEBUGFUNC();
3834 
3835 	reg_data = E1000_KUMCTRLSTA_HD_CTRL_10_100_DEFAULT;
3836 	ret_val = e1000_write_kmrn_reg(hw,
3837 			E1000_KUMCTRLSTA_OFFSET_HD_CTRL, reg_data);
3838 	if (ret_val)
3839 		return ret_val;
3840 
3841 	/* Configure Transmit Inter-Packet Gap */
3842 	tipg = E1000_READ_REG(hw, TIPG);
3843 	tipg &= ~E1000_TIPG_IPGT_MASK;
3844 	tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_10_100;
3845 	E1000_WRITE_REG(hw, TIPG, tipg);
3846 
3847 	ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
3848 
3849 	if (ret_val)
3850 		return ret_val;
3851 
3852 	if (duplex == HALF_DUPLEX)
3853 		reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER;
3854 	else
3855 		reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
3856 
3857 	ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
3858 
3859 	return ret_val;
3860 }
3861 
3862 static int32_t
3863 e1000_configure_kmrn_for_1000(struct e1000_hw *hw)
3864 {
3865 	int32_t ret_val = E1000_SUCCESS;
3866 	uint16_t reg_data;
3867 	uint32_t tipg;
3868 
3869 	DEBUGFUNC();
3870 
3871 	reg_data = E1000_KUMCTRLSTA_HD_CTRL_1000_DEFAULT;
3872 	ret_val = e1000_write_kmrn_reg(hw,
3873 			E1000_KUMCTRLSTA_OFFSET_HD_CTRL, reg_data);
3874 	if (ret_val)
3875 		return ret_val;
3876 
3877 	/* Configure Transmit Inter-Packet Gap */
3878 	tipg = E1000_READ_REG(hw, TIPG);
3879 	tipg &= ~E1000_TIPG_IPGT_MASK;
3880 	tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;
3881 	E1000_WRITE_REG(hw, TIPG, tipg);
3882 
3883 	ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
3884 
3885 	if (ret_val)
3886 		return ret_val;
3887 
3888 	reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
3889 	ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
3890 
3891 	return ret_val;
3892 }
3893 
3894 /******************************************************************************
3895  * Detects the current speed and duplex settings of the hardware.
3896  *
3897  * hw - Struct containing variables accessed by shared code
3898  * speed - Speed of the connection
3899  * duplex - Duplex setting of the connection
3900  *****************************************************************************/
3901 static int
3902 e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t *speed,
3903 		uint16_t *duplex)
3904 {
3905 	uint32_t status;
3906 	int32_t ret_val;
3907 	uint16_t phy_data;
3908 
3909 	DEBUGFUNC();
3910 
3911 	if (hw->mac_type >= e1000_82543) {
3912 		status = E1000_READ_REG(hw, STATUS);
3913 		if (status & E1000_STATUS_SPEED_1000) {
3914 			*speed = SPEED_1000;
3915 			DEBUGOUT("1000 Mbs, ");
3916 		} else if (status & E1000_STATUS_SPEED_100) {
3917 			*speed = SPEED_100;
3918 			DEBUGOUT("100 Mbs, ");
3919 		} else {
3920 			*speed = SPEED_10;
3921 			DEBUGOUT("10 Mbs, ");
3922 		}
3923 
3924 		if (status & E1000_STATUS_FD) {
3925 			*duplex = FULL_DUPLEX;
3926 			DEBUGOUT("Full Duplex\r\n");
3927 		} else {
3928 			*duplex = HALF_DUPLEX;
3929 			DEBUGOUT(" Half Duplex\r\n");
3930 		}
3931 	} else {
3932 		DEBUGOUT("1000 Mbs, Full Duplex\r\n");
3933 		*speed = SPEED_1000;
3934 		*duplex = FULL_DUPLEX;
3935 	}
3936 
3937 	/* IGP01 PHY may advertise full duplex operation after speed downgrade
3938 	 * even if it is operating at half duplex.  Here we set the duplex
3939 	 * settings to match the duplex in the link partner's capabilities.
3940 	 */
3941 	if (hw->phy_type == e1000_phy_igp && hw->speed_downgraded) {
3942 		ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data);
3943 		if (ret_val)
3944 			return ret_val;
3945 
3946 		if (!(phy_data & NWAY_ER_LP_NWAY_CAPS))
3947 			*duplex = HALF_DUPLEX;
3948 		else {
3949 			ret_val = e1000_read_phy_reg(hw,
3950 					PHY_LP_ABILITY, &phy_data);
3951 			if (ret_val)
3952 				return ret_val;
3953 			if ((*speed == SPEED_100 &&
3954 				!(phy_data & NWAY_LPAR_100TX_FD_CAPS))
3955 				|| (*speed == SPEED_10
3956 				&& !(phy_data & NWAY_LPAR_10T_FD_CAPS)))
3957 				*duplex = HALF_DUPLEX;
3958 		}
3959 	}
3960 
3961 	if ((hw->mac_type == e1000_80003es2lan) &&
3962 		(hw->media_type == e1000_media_type_copper)) {
3963 		if (*speed == SPEED_1000)
3964 			ret_val = e1000_configure_kmrn_for_1000(hw);
3965 		else
3966 			ret_val = e1000_configure_kmrn_for_10_100(hw, *duplex);
3967 		if (ret_val)
3968 			return ret_val;
3969 	}
3970 	return E1000_SUCCESS;
3971 }
3972 
3973 /******************************************************************************
3974 * Blocks until autoneg completes or times out (~4.5 seconds)
3975 *
3976 * hw - Struct containing variables accessed by shared code
3977 ******************************************************************************/
3978 static int
3979 e1000_wait_autoneg(struct e1000_hw *hw)
3980 {
3981 	uint16_t i;
3982 	uint16_t phy_data;
3983 
3984 	DEBUGFUNC();
3985 	DEBUGOUT("Waiting for Auto-Neg to complete.\n");
3986 
3987 	/* We will wait for autoneg to complete or timeout to expire. */
3988 	for (i = PHY_AUTO_NEG_TIME; i > 0; i--) {
3989 		/* Read the MII Status Register and wait for Auto-Neg
3990 		 * Complete bit to be set.
3991 		 */
3992 		if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
3993 			DEBUGOUT("PHY Read Error\n");
3994 			return -E1000_ERR_PHY;
3995 		}
3996 		if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
3997 			DEBUGOUT("PHY Read Error\n");
3998 			return -E1000_ERR_PHY;
3999 		}
4000 		if (phy_data & MII_SR_AUTONEG_COMPLETE) {
4001 			DEBUGOUT("Auto-Neg complete.\n");
4002 			return 0;
4003 		}
4004 		mdelay(100);
4005 	}
4006 	DEBUGOUT("Auto-Neg timedout.\n");
4007 	return -E1000_ERR_TIMEOUT;
4008 }
4009 
4010 /******************************************************************************
4011 * Raises the Management Data Clock
4012 *
4013 * hw - Struct containing variables accessed by shared code
4014 * ctrl - Device control register's current value
4015 ******************************************************************************/
4016 static void
4017 e1000_raise_mdi_clk(struct e1000_hw *hw, uint32_t * ctrl)
4018 {
4019 	/* Raise the clock input to the Management Data Clock (by setting the MDC
4020 	 * bit), and then delay 2 microseconds.
4021 	 */
4022 	E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC));
4023 	E1000_WRITE_FLUSH(hw);
4024 	udelay(2);
4025 }
4026 
4027 /******************************************************************************
4028 * Lowers the Management Data Clock
4029 *
4030 * hw - Struct containing variables accessed by shared code
4031 * ctrl - Device control register's current value
4032 ******************************************************************************/
4033 static void
4034 e1000_lower_mdi_clk(struct e1000_hw *hw, uint32_t * ctrl)
4035 {
4036 	/* Lower the clock input to the Management Data Clock (by clearing the MDC
4037 	 * bit), and then delay 2 microseconds.
4038 	 */
4039 	E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC));
4040 	E1000_WRITE_FLUSH(hw);
4041 	udelay(2);
4042 }
4043 
4044 /******************************************************************************
4045 * Shifts data bits out to the PHY
4046 *
4047 * hw - Struct containing variables accessed by shared code
4048 * data - Data to send out to the PHY
4049 * count - Number of bits to shift out
4050 *
4051 * Bits are shifted out in MSB to LSB order.
4052 ******************************************************************************/
4053 static void
4054 e1000_shift_out_mdi_bits(struct e1000_hw *hw, uint32_t data, uint16_t count)
4055 {
4056 	uint32_t ctrl;
4057 	uint32_t mask;
4058 
4059 	/* We need to shift "count" number of bits out to the PHY. So, the value
4060 	 * in the "data" parameter will be shifted out to the PHY one bit at a
4061 	 * time. In order to do this, "data" must be broken down into bits.
4062 	 */
4063 	mask = 0x01;
4064 	mask <<= (count - 1);
4065 
4066 	ctrl = E1000_READ_REG(hw, CTRL);
4067 
4068 	/* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */
4069 	ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR);
4070 
4071 	while (mask) {
4072 		/* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and
4073 		 * then raising and lowering the Management Data Clock. A "0" is
4074 		 * shifted out to the PHY by setting the MDIO bit to "0" and then
4075 		 * raising and lowering the clock.
4076 		 */
4077 		if (data & mask)
4078 			ctrl |= E1000_CTRL_MDIO;
4079 		else
4080 			ctrl &= ~E1000_CTRL_MDIO;
4081 
4082 		E1000_WRITE_REG(hw, CTRL, ctrl);
4083 		E1000_WRITE_FLUSH(hw);
4084 
4085 		udelay(2);
4086 
4087 		e1000_raise_mdi_clk(hw, &ctrl);
4088 		e1000_lower_mdi_clk(hw, &ctrl);
4089 
4090 		mask = mask >> 1;
4091 	}
4092 }
4093 
4094 /******************************************************************************
4095 * Shifts data bits in from the PHY
4096 *
4097 * hw - Struct containing variables accessed by shared code
4098 *
4099 * Bits are shifted in in MSB to LSB order.
4100 ******************************************************************************/
4101 static uint16_t
4102 e1000_shift_in_mdi_bits(struct e1000_hw *hw)
4103 {
4104 	uint32_t ctrl;
4105 	uint16_t data = 0;
4106 	uint8_t i;
4107 
4108 	/* In order to read a register from the PHY, we need to shift in a total
4109 	 * of 18 bits from the PHY. The first two bit (turnaround) times are used
4110 	 * to avoid contention on the MDIO pin when a read operation is performed.
4111 	 * These two bits are ignored by us and thrown away. Bits are "shifted in"
4112 	 * by raising the input to the Management Data Clock (setting the MDC bit),
4113 	 * and then reading the value of the MDIO bit.
4114 	 */
4115 	ctrl = E1000_READ_REG(hw, CTRL);
4116 
4117 	/* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */
4118 	ctrl &= ~E1000_CTRL_MDIO_DIR;
4119 	ctrl &= ~E1000_CTRL_MDIO;
4120 
4121 	E1000_WRITE_REG(hw, CTRL, ctrl);
4122 	E1000_WRITE_FLUSH(hw);
4123 
4124 	/* Raise and Lower the clock before reading in the data. This accounts for
4125 	 * the turnaround bits. The first clock occurred when we clocked out the
4126 	 * last bit of the Register Address.
4127 	 */
4128 	e1000_raise_mdi_clk(hw, &ctrl);
4129 	e1000_lower_mdi_clk(hw, &ctrl);
4130 
4131 	for (data = 0, i = 0; i < 16; i++) {
4132 		data = data << 1;
4133 		e1000_raise_mdi_clk(hw, &ctrl);
4134 		ctrl = E1000_READ_REG(hw, CTRL);
4135 		/* Check to see if we shifted in a "1". */
4136 		if (ctrl & E1000_CTRL_MDIO)
4137 			data |= 1;
4138 		e1000_lower_mdi_clk(hw, &ctrl);
4139 	}
4140 
4141 	e1000_raise_mdi_clk(hw, &ctrl);
4142 	e1000_lower_mdi_clk(hw, &ctrl);
4143 
4144 	return data;
4145 }
4146 
4147 /*****************************************************************************
4148 * Reads the value from a PHY register
4149 *
4150 * hw - Struct containing variables accessed by shared code
4151 * reg_addr - address of the PHY register to read
4152 ******************************************************************************/
4153 static int
4154 e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t * phy_data)
4155 {
4156 	uint32_t i;
4157 	uint32_t mdic = 0;
4158 	const uint32_t phy_addr = 1;
4159 
4160 	if (reg_addr > MAX_PHY_REG_ADDRESS) {
4161 		DEBUGOUT("PHY Address %d is out of range\n", reg_addr);
4162 		return -E1000_ERR_PARAM;
4163 	}
4164 
4165 	if (hw->mac_type > e1000_82543) {
4166 		/* Set up Op-code, Phy Address, and register address in the MDI
4167 		 * Control register.  The MAC will take care of interfacing with the
4168 		 * PHY to retrieve the desired data.
4169 		 */
4170 		mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) |
4171 			(phy_addr << E1000_MDIC_PHY_SHIFT) |
4172 			(E1000_MDIC_OP_READ));
4173 
4174 		E1000_WRITE_REG(hw, MDIC, mdic);
4175 
4176 		/* Poll the ready bit to see if the MDI read completed */
4177 		for (i = 0; i < 64; i++) {
4178 			udelay(10);
4179 			mdic = E1000_READ_REG(hw, MDIC);
4180 			if (mdic & E1000_MDIC_READY)
4181 				break;
4182 		}
4183 		if (!(mdic & E1000_MDIC_READY)) {
4184 			DEBUGOUT("MDI Read did not complete\n");
4185 			return -E1000_ERR_PHY;
4186 		}
4187 		if (mdic & E1000_MDIC_ERROR) {
4188 			DEBUGOUT("MDI Error\n");
4189 			return -E1000_ERR_PHY;
4190 		}
4191 		*phy_data = (uint16_t) mdic;
4192 	} else {
4193 		/* We must first send a preamble through the MDIO pin to signal the
4194 		 * beginning of an MII instruction.  This is done by sending 32
4195 		 * consecutive "1" bits.
4196 		 */
4197 		e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
4198 
4199 		/* Now combine the next few fields that are required for a read
4200 		 * operation.  We use this method instead of calling the
4201 		 * e1000_shift_out_mdi_bits routine five different times. The format of
4202 		 * a MII read instruction consists of a shift out of 14 bits and is
4203 		 * defined as follows:
4204 		 *    <Preamble><SOF><Op Code><Phy Addr><Reg Addr>
4205 		 * followed by a shift in of 18 bits.  This first two bits shifted in
4206 		 * are TurnAround bits used to avoid contention on the MDIO pin when a
4207 		 * READ operation is performed.  These two bits are thrown away
4208 		 * followed by a shift in of 16 bits which contains the desired data.
4209 		 */
4210 		mdic = ((reg_addr) | (phy_addr << 5) |
4211 			(PHY_OP_READ << 10) | (PHY_SOF << 12));
4212 
4213 		e1000_shift_out_mdi_bits(hw, mdic, 14);
4214 
4215 		/* Now that we've shifted out the read command to the MII, we need to
4216 		 * "shift in" the 16-bit value (18 total bits) of the requested PHY
4217 		 * register address.
4218 		 */
4219 		*phy_data = e1000_shift_in_mdi_bits(hw);
4220 	}
4221 	return 0;
4222 }
4223 
4224 /******************************************************************************
4225 * Writes a value to a PHY register
4226 *
4227 * hw - Struct containing variables accessed by shared code
4228 * reg_addr - address of the PHY register to write
4229 * data - data to write to the PHY
4230 ******************************************************************************/
4231 static int
4232 e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t phy_data)
4233 {
4234 	uint32_t i;
4235 	uint32_t mdic = 0;
4236 	const uint32_t phy_addr = 1;
4237 
4238 	if (reg_addr > MAX_PHY_REG_ADDRESS) {
4239 		DEBUGOUT("PHY Address %d is out of range\n", reg_addr);
4240 		return -E1000_ERR_PARAM;
4241 	}
4242 
4243 	if (hw->mac_type > e1000_82543) {
4244 		/* Set up Op-code, Phy Address, register address, and data intended
4245 		 * for the PHY register in the MDI Control register.  The MAC will take
4246 		 * care of interfacing with the PHY to send the desired data.
4247 		 */
4248 		mdic = (((uint32_t) phy_data) |
4249 			(reg_addr << E1000_MDIC_REG_SHIFT) |
4250 			(phy_addr << E1000_MDIC_PHY_SHIFT) |
4251 			(E1000_MDIC_OP_WRITE));
4252 
4253 		E1000_WRITE_REG(hw, MDIC, mdic);
4254 
4255 		/* Poll the ready bit to see if the MDI read completed */
4256 		for (i = 0; i < 64; i++) {
4257 			udelay(10);
4258 			mdic = E1000_READ_REG(hw, MDIC);
4259 			if (mdic & E1000_MDIC_READY)
4260 				break;
4261 		}
4262 		if (!(mdic & E1000_MDIC_READY)) {
4263 			DEBUGOUT("MDI Write did not complete\n");
4264 			return -E1000_ERR_PHY;
4265 		}
4266 	} else {
4267 		/* We'll need to use the SW defined pins to shift the write command
4268 		 * out to the PHY. We first send a preamble to the PHY to signal the
4269 		 * beginning of the MII instruction.  This is done by sending 32
4270 		 * consecutive "1" bits.
4271 		 */
4272 		e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
4273 
4274 		/* Now combine the remaining required fields that will indicate a
4275 		 * write operation. We use this method instead of calling the
4276 		 * e1000_shift_out_mdi_bits routine for each field in the command. The
4277 		 * format of a MII write instruction is as follows:
4278 		 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>.
4279 		 */
4280 		mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) |
4281 			(PHY_OP_WRITE << 12) | (PHY_SOF << 14));
4282 		mdic <<= 16;
4283 		mdic |= (uint32_t) phy_data;
4284 
4285 		e1000_shift_out_mdi_bits(hw, mdic, 32);
4286 	}
4287 	return 0;
4288 }
4289 
4290 /******************************************************************************
4291  * Checks if PHY reset is blocked due to SOL/IDER session, for example.
4292  * Returning E1000_BLK_PHY_RESET isn't necessarily an error.  But it's up to
4293  * the caller to figure out how to deal with it.
4294  *
4295  * hw - Struct containing variables accessed by shared code
4296  *
4297  * returns: - E1000_BLK_PHY_RESET
4298  *            E1000_SUCCESS
4299  *
4300  *****************************************************************************/
4301 int32_t
4302 e1000_check_phy_reset_block(struct e1000_hw *hw)
4303 {
4304 	uint32_t manc = 0;
4305 	uint32_t fwsm = 0;
4306 
4307 	if (hw->mac_type == e1000_ich8lan) {
4308 		fwsm = E1000_READ_REG(hw, FWSM);
4309 		return (fwsm & E1000_FWSM_RSPCIPHY) ? E1000_SUCCESS
4310 						: E1000_BLK_PHY_RESET;
4311 	}
4312 
4313 	if (hw->mac_type > e1000_82547_rev_2)
4314 		manc = E1000_READ_REG(hw, MANC);
4315 	return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?
4316 		E1000_BLK_PHY_RESET : E1000_SUCCESS;
4317 }
4318 
4319 /***************************************************************************
4320  * Checks if the PHY configuration is done
4321  *
4322  * hw: Struct containing variables accessed by shared code
4323  *
4324  * returns: - E1000_ERR_RESET if fail to reset MAC
4325  *            E1000_SUCCESS at any other case.
4326  *
4327  ***************************************************************************/
4328 static int32_t
4329 e1000_get_phy_cfg_done(struct e1000_hw *hw)
4330 {
4331 	int32_t timeout = PHY_CFG_TIMEOUT;
4332 	uint32_t cfg_mask = E1000_EEPROM_CFG_DONE;
4333 
4334 	DEBUGFUNC();
4335 
4336 	switch (hw->mac_type) {
4337 	default:
4338 		mdelay(10);
4339 		break;
4340 
4341 	case e1000_80003es2lan:
4342 		/* Separate *_CFG_DONE_* bit for each port */
4343 		if (e1000_is_second_port(hw))
4344 			cfg_mask = E1000_EEPROM_CFG_DONE_PORT_1;
4345 		/* Fall Through */
4346 
4347 	case e1000_82571:
4348 	case e1000_82572:
4349 	case e1000_igb:
4350 		while (timeout) {
4351 			if (hw->mac_type == e1000_igb) {
4352 				if (E1000_READ_REG(hw, I210_EEMNGCTL) & cfg_mask)
4353 					break;
4354 			} else {
4355 				if (E1000_READ_REG(hw, EEMNGCTL) & cfg_mask)
4356 					break;
4357 			}
4358 			mdelay(1);
4359 			timeout--;
4360 		}
4361 		if (!timeout) {
4362 			DEBUGOUT("MNG configuration cycle has not "
4363 					"completed.\n");
4364 			return -E1000_ERR_RESET;
4365 		}
4366 		break;
4367 	}
4368 
4369 	return E1000_SUCCESS;
4370 }
4371 
4372 /******************************************************************************
4373 * Returns the PHY to the power-on reset state
4374 *
4375 * hw - Struct containing variables accessed by shared code
4376 ******************************************************************************/
4377 int32_t
4378 e1000_phy_hw_reset(struct e1000_hw *hw)
4379 {
4380 	uint16_t swfw = E1000_SWFW_PHY0_SM;
4381 	uint32_t ctrl, ctrl_ext;
4382 	uint32_t led_ctrl;
4383 	int32_t ret_val;
4384 
4385 	DEBUGFUNC();
4386 
4387 	/* In the case of the phy reset being blocked, it's not an error, we
4388 	 * simply return success without performing the reset. */
4389 	ret_val = e1000_check_phy_reset_block(hw);
4390 	if (ret_val)
4391 		return E1000_SUCCESS;
4392 
4393 	DEBUGOUT("Resetting Phy...\n");
4394 
4395 	if (hw->mac_type > e1000_82543) {
4396 		if (e1000_is_second_port(hw))
4397 			swfw = E1000_SWFW_PHY1_SM;
4398 
4399 		if (e1000_swfw_sync_acquire(hw, swfw)) {
4400 			DEBUGOUT("Unable to acquire swfw sync\n");
4401 			return -E1000_ERR_SWFW_SYNC;
4402 		}
4403 
4404 		/* Read the device control register and assert the E1000_CTRL_PHY_RST
4405 		 * bit. Then, take it out of reset.
4406 		 */
4407 		ctrl = E1000_READ_REG(hw, CTRL);
4408 		E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST);
4409 		E1000_WRITE_FLUSH(hw);
4410 
4411 		if (hw->mac_type < e1000_82571)
4412 			udelay(10);
4413 		else
4414 			udelay(100);
4415 
4416 		E1000_WRITE_REG(hw, CTRL, ctrl);
4417 		E1000_WRITE_FLUSH(hw);
4418 
4419 		if (hw->mac_type >= e1000_82571)
4420 			mdelay(10);
4421 
4422 	} else {
4423 		/* Read the Extended Device Control Register, assert the PHY_RESET_DIR
4424 		 * bit to put the PHY into reset. Then, take it out of reset.
4425 		 */
4426 		ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
4427 		ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR;
4428 		ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA;
4429 		E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
4430 		E1000_WRITE_FLUSH(hw);
4431 		mdelay(10);
4432 		ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA;
4433 		E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
4434 		E1000_WRITE_FLUSH(hw);
4435 	}
4436 	udelay(150);
4437 
4438 	if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
4439 		/* Configure activity LED after PHY reset */
4440 		led_ctrl = E1000_READ_REG(hw, LEDCTL);
4441 		led_ctrl &= IGP_ACTIVITY_LED_MASK;
4442 		led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
4443 		E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
4444 	}
4445 
4446 	e1000_swfw_sync_release(hw, swfw);
4447 
4448 	/* Wait for FW to finish PHY configuration. */
4449 	ret_val = e1000_get_phy_cfg_done(hw);
4450 	if (ret_val != E1000_SUCCESS)
4451 		return ret_val;
4452 
4453 	return ret_val;
4454 }
4455 
4456 /******************************************************************************
4457  * IGP phy init script - initializes the GbE PHY
4458  *
4459  * hw - Struct containing variables accessed by shared code
4460  *****************************************************************************/
4461 static void
4462 e1000_phy_init_script(struct e1000_hw *hw)
4463 {
4464 	uint32_t ret_val;
4465 	uint16_t phy_saved_data;
4466 	DEBUGFUNC();
4467 
4468 	if (hw->phy_init_script) {
4469 		mdelay(20);
4470 
4471 		/* Save off the current value of register 0x2F5B to be
4472 		 * restored at the end of this routine. */
4473 		ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
4474 
4475 		/* Disabled the PHY transmitter */
4476 		e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
4477 
4478 		mdelay(20);
4479 
4480 		e1000_write_phy_reg(hw, 0x0000, 0x0140);
4481 
4482 		mdelay(5);
4483 
4484 		switch (hw->mac_type) {
4485 		case e1000_82541:
4486 		case e1000_82547:
4487 			e1000_write_phy_reg(hw, 0x1F95, 0x0001);
4488 
4489 			e1000_write_phy_reg(hw, 0x1F71, 0xBD21);
4490 
4491 			e1000_write_phy_reg(hw, 0x1F79, 0x0018);
4492 
4493 			e1000_write_phy_reg(hw, 0x1F30, 0x1600);
4494 
4495 			e1000_write_phy_reg(hw, 0x1F31, 0x0014);
4496 
4497 			e1000_write_phy_reg(hw, 0x1F32, 0x161C);
4498 
4499 			e1000_write_phy_reg(hw, 0x1F94, 0x0003);
4500 
4501 			e1000_write_phy_reg(hw, 0x1F96, 0x003F);
4502 
4503 			e1000_write_phy_reg(hw, 0x2010, 0x0008);
4504 			break;
4505 
4506 		case e1000_82541_rev_2:
4507 		case e1000_82547_rev_2:
4508 			e1000_write_phy_reg(hw, 0x1F73, 0x0099);
4509 			break;
4510 		default:
4511 			break;
4512 		}
4513 
4514 		e1000_write_phy_reg(hw, 0x0000, 0x3300);
4515 
4516 		mdelay(20);
4517 
4518 		/* Now enable the transmitter */
4519 		if (!ret_val)
4520 			e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
4521 
4522 		if (hw->mac_type == e1000_82547) {
4523 			uint16_t fused, fine, coarse;
4524 
4525 			/* Move to analog registers page */
4526 			e1000_read_phy_reg(hw,
4527 				IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused);
4528 
4529 			if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {
4530 				e1000_read_phy_reg(hw,
4531 					IGP01E1000_ANALOG_FUSE_STATUS, &fused);
4532 
4533 				fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;
4534 				coarse = fused
4535 					& IGP01E1000_ANALOG_FUSE_COARSE_MASK;
4536 
4537 				if (coarse >
4538 					IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {
4539 					coarse -=
4540 					IGP01E1000_ANALOG_FUSE_COARSE_10;
4541 					fine -= IGP01E1000_ANALOG_FUSE_FINE_1;
4542 				} else if (coarse
4543 					== IGP01E1000_ANALOG_FUSE_COARSE_THRESH)
4544 					fine -= IGP01E1000_ANALOG_FUSE_FINE_10;
4545 
4546 				fused = (fused
4547 					& IGP01E1000_ANALOG_FUSE_POLY_MASK) |
4548 					(fine
4549 					& IGP01E1000_ANALOG_FUSE_FINE_MASK) |
4550 					(coarse
4551 					& IGP01E1000_ANALOG_FUSE_COARSE_MASK);
4552 
4553 				e1000_write_phy_reg(hw,
4554 					IGP01E1000_ANALOG_FUSE_CONTROL, fused);
4555 				e1000_write_phy_reg(hw,
4556 					IGP01E1000_ANALOG_FUSE_BYPASS,
4557 				IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL);
4558 			}
4559 		}
4560 	}
4561 }
4562 
4563 /******************************************************************************
4564 * Resets the PHY
4565 *
4566 * hw - Struct containing variables accessed by shared code
4567 *
4568 * Sets bit 15 of the MII Control register
4569 ******************************************************************************/
4570 int32_t
4571 e1000_phy_reset(struct e1000_hw *hw)
4572 {
4573 	int32_t ret_val;
4574 	uint16_t phy_data;
4575 
4576 	DEBUGFUNC();
4577 
4578 	/* In the case of the phy reset being blocked, it's not an error, we
4579 	 * simply return success without performing the reset. */
4580 	ret_val = e1000_check_phy_reset_block(hw);
4581 	if (ret_val)
4582 		return E1000_SUCCESS;
4583 
4584 	switch (hw->phy_type) {
4585 	case e1000_phy_igp:
4586 	case e1000_phy_igp_2:
4587 	case e1000_phy_igp_3:
4588 	case e1000_phy_ife:
4589 	case e1000_phy_igb:
4590 		ret_val = e1000_phy_hw_reset(hw);
4591 		if (ret_val)
4592 			return ret_val;
4593 		break;
4594 	default:
4595 		ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
4596 		if (ret_val)
4597 			return ret_val;
4598 
4599 		phy_data |= MII_CR_RESET;
4600 		ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
4601 		if (ret_val)
4602 			return ret_val;
4603 
4604 		udelay(1);
4605 		break;
4606 	}
4607 
4608 	if (hw->phy_type == e1000_phy_igp || hw->phy_type == e1000_phy_igp_2)
4609 		e1000_phy_init_script(hw);
4610 
4611 	return E1000_SUCCESS;
4612 }
4613 
4614 static int e1000_set_phy_type (struct e1000_hw *hw)
4615 {
4616 	DEBUGFUNC ();
4617 
4618 	if (hw->mac_type == e1000_undefined)
4619 		return -E1000_ERR_PHY_TYPE;
4620 
4621 	switch (hw->phy_id) {
4622 	case M88E1000_E_PHY_ID:
4623 	case M88E1000_I_PHY_ID:
4624 	case M88E1011_I_PHY_ID:
4625 	case M88E1111_I_PHY_ID:
4626 		hw->phy_type = e1000_phy_m88;
4627 		break;
4628 	case IGP01E1000_I_PHY_ID:
4629 		if (hw->mac_type == e1000_82541 ||
4630 			hw->mac_type == e1000_82541_rev_2 ||
4631 			hw->mac_type == e1000_82547 ||
4632 			hw->mac_type == e1000_82547_rev_2) {
4633 			hw->phy_type = e1000_phy_igp;
4634 			break;
4635 		}
4636 	case IGP03E1000_E_PHY_ID:
4637 		hw->phy_type = e1000_phy_igp_3;
4638 		break;
4639 	case IFE_E_PHY_ID:
4640 	case IFE_PLUS_E_PHY_ID:
4641 	case IFE_C_E_PHY_ID:
4642 		hw->phy_type = e1000_phy_ife;
4643 		break;
4644 	case GG82563_E_PHY_ID:
4645 		if (hw->mac_type == e1000_80003es2lan) {
4646 			hw->phy_type = e1000_phy_gg82563;
4647 			break;
4648 		}
4649 	case BME1000_E_PHY_ID:
4650 		hw->phy_type = e1000_phy_bm;
4651 		break;
4652 	case I210_I_PHY_ID:
4653 		hw->phy_type = e1000_phy_igb;
4654 		break;
4655 		/* Fall Through */
4656 	default:
4657 		/* Should never have loaded on this device */
4658 		hw->phy_type = e1000_phy_undefined;
4659 		return -E1000_ERR_PHY_TYPE;
4660 	}
4661 
4662 	return E1000_SUCCESS;
4663 }
4664 
4665 /******************************************************************************
4666 * Probes the expected PHY address for known PHY IDs
4667 *
4668 * hw - Struct containing variables accessed by shared code
4669 ******************************************************************************/
4670 static int32_t
4671 e1000_detect_gig_phy(struct e1000_hw *hw)
4672 {
4673 	int32_t phy_init_status, ret_val;
4674 	uint16_t phy_id_high, phy_id_low;
4675 	bool match = false;
4676 
4677 	DEBUGFUNC();
4678 
4679 	/* The 82571 firmware may still be configuring the PHY.  In this
4680 	 * case, we cannot access the PHY until the configuration is done.  So
4681 	 * we explicitly set the PHY values. */
4682 	if (hw->mac_type == e1000_82571 ||
4683 		hw->mac_type == e1000_82572) {
4684 		hw->phy_id = IGP01E1000_I_PHY_ID;
4685 		hw->phy_type = e1000_phy_igp_2;
4686 		return E1000_SUCCESS;
4687 	}
4688 
4689 	/* ESB-2 PHY reads require e1000_phy_gg82563 to be set because of a
4690 	 * work- around that forces PHY page 0 to be set or the reads fail.
4691 	 * The rest of the code in this routine uses e1000_read_phy_reg to
4692 	 * read the PHY ID.  So for ESB-2 we need to have this set so our
4693 	 * reads won't fail.  If the attached PHY is not a e1000_phy_gg82563,
4694 	 * the routines below will figure this out as well. */
4695 	if (hw->mac_type == e1000_80003es2lan)
4696 		hw->phy_type = e1000_phy_gg82563;
4697 
4698 	/* Read the PHY ID Registers to identify which PHY is onboard. */
4699 	ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high);
4700 	if (ret_val)
4701 		return ret_val;
4702 
4703 	hw->phy_id = (uint32_t) (phy_id_high << 16);
4704 	udelay(20);
4705 	ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low);
4706 	if (ret_val)
4707 		return ret_val;
4708 
4709 	hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK);
4710 	hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK;
4711 
4712 	switch (hw->mac_type) {
4713 	case e1000_82543:
4714 		if (hw->phy_id == M88E1000_E_PHY_ID)
4715 			match = true;
4716 		break;
4717 	case e1000_82544:
4718 		if (hw->phy_id == M88E1000_I_PHY_ID)
4719 			match = true;
4720 		break;
4721 	case e1000_82540:
4722 	case e1000_82545:
4723 	case e1000_82545_rev_3:
4724 	case e1000_82546:
4725 	case e1000_82546_rev_3:
4726 		if (hw->phy_id == M88E1011_I_PHY_ID)
4727 			match = true;
4728 		break;
4729 	case e1000_82541:
4730 	case e1000_82541_rev_2:
4731 	case e1000_82547:
4732 	case e1000_82547_rev_2:
4733 		if(hw->phy_id == IGP01E1000_I_PHY_ID)
4734 			match = true;
4735 
4736 		break;
4737 	case e1000_82573:
4738 		if (hw->phy_id == M88E1111_I_PHY_ID)
4739 			match = true;
4740 		break;
4741 	case e1000_82574:
4742 		if (hw->phy_id == BME1000_E_PHY_ID)
4743 			match = true;
4744 		break;
4745 	case e1000_80003es2lan:
4746 		if (hw->phy_id == GG82563_E_PHY_ID)
4747 			match = true;
4748 		break;
4749 	case e1000_ich8lan:
4750 		if (hw->phy_id == IGP03E1000_E_PHY_ID)
4751 			match = true;
4752 		if (hw->phy_id == IFE_E_PHY_ID)
4753 			match = true;
4754 		if (hw->phy_id == IFE_PLUS_E_PHY_ID)
4755 			match = true;
4756 		if (hw->phy_id == IFE_C_E_PHY_ID)
4757 			match = true;
4758 		break;
4759 	case e1000_igb:
4760 		if (hw->phy_id == I210_I_PHY_ID)
4761 			match = true;
4762 		break;
4763 	default:
4764 		DEBUGOUT("Invalid MAC type %d\n", hw->mac_type);
4765 		return -E1000_ERR_CONFIG;
4766 	}
4767 
4768 	phy_init_status = e1000_set_phy_type(hw);
4769 
4770 	if ((match) && (phy_init_status == E1000_SUCCESS)) {
4771 		DEBUGOUT("PHY ID 0x%X detected\n", hw->phy_id);
4772 		return 0;
4773 	}
4774 	DEBUGOUT("Invalid PHY ID 0x%X\n", hw->phy_id);
4775 	return -E1000_ERR_PHY;
4776 }
4777 
4778 /*****************************************************************************
4779  * Set media type and TBI compatibility.
4780  *
4781  * hw - Struct containing variables accessed by shared code
4782  * **************************************************************************/
4783 void
4784 e1000_set_media_type(struct e1000_hw *hw)
4785 {
4786 	uint32_t status;
4787 
4788 	DEBUGFUNC();
4789 
4790 	if (hw->mac_type != e1000_82543) {
4791 		/* tbi_compatibility is only valid on 82543 */
4792 		hw->tbi_compatibility_en = false;
4793 	}
4794 
4795 	switch (hw->device_id) {
4796 	case E1000_DEV_ID_82545GM_SERDES:
4797 	case E1000_DEV_ID_82546GB_SERDES:
4798 	case E1000_DEV_ID_82571EB_SERDES:
4799 	case E1000_DEV_ID_82571EB_SERDES_DUAL:
4800 	case E1000_DEV_ID_82571EB_SERDES_QUAD:
4801 	case E1000_DEV_ID_82572EI_SERDES:
4802 	case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
4803 		hw->media_type = e1000_media_type_internal_serdes;
4804 		break;
4805 	default:
4806 		switch (hw->mac_type) {
4807 		case e1000_82542_rev2_0:
4808 		case e1000_82542_rev2_1:
4809 			hw->media_type = e1000_media_type_fiber;
4810 			break;
4811 		case e1000_ich8lan:
4812 		case e1000_82573:
4813 		case e1000_82574:
4814 		case e1000_igb:
4815 			/* The STATUS_TBIMODE bit is reserved or reused
4816 			 * for the this device.
4817 			 */
4818 			hw->media_type = e1000_media_type_copper;
4819 			break;
4820 		default:
4821 			status = E1000_READ_REG(hw, STATUS);
4822 			if (status & E1000_STATUS_TBIMODE) {
4823 				hw->media_type = e1000_media_type_fiber;
4824 				/* tbi_compatibility not valid on fiber */
4825 				hw->tbi_compatibility_en = false;
4826 			} else {
4827 				hw->media_type = e1000_media_type_copper;
4828 			}
4829 			break;
4830 		}
4831 	}
4832 }
4833 
4834 /**
4835  * e1000_sw_init - Initialize general software structures (struct e1000_adapter)
4836  *
4837  * e1000_sw_init initializes the Adapter private data structure.
4838  * Fields are initialized based on PCI device information and
4839  * OS network device settings (MTU size).
4840  **/
4841 
4842 static int
4843 e1000_sw_init(struct e1000_hw *hw)
4844 {
4845 	int result;
4846 
4847 	/* PCI config space info */
4848 #ifdef CONFIG_DM_ETH
4849 	dm_pci_read_config16(hw->pdev, PCI_VENDOR_ID, &hw->vendor_id);
4850 	dm_pci_read_config16(hw->pdev, PCI_DEVICE_ID, &hw->device_id);
4851 	dm_pci_read_config16(hw->pdev, PCI_SUBSYSTEM_VENDOR_ID,
4852 			     &hw->subsystem_vendor_id);
4853 	dm_pci_read_config16(hw->pdev, PCI_SUBSYSTEM_ID, &hw->subsystem_id);
4854 
4855 	dm_pci_read_config8(hw->pdev, PCI_REVISION_ID, &hw->revision_id);
4856 	dm_pci_read_config16(hw->pdev, PCI_COMMAND, &hw->pci_cmd_word);
4857 #else
4858 	pci_read_config_word(hw->pdev, PCI_VENDOR_ID, &hw->vendor_id);
4859 	pci_read_config_word(hw->pdev, PCI_DEVICE_ID, &hw->device_id);
4860 	pci_read_config_word(hw->pdev, PCI_SUBSYSTEM_VENDOR_ID,
4861 			     &hw->subsystem_vendor_id);
4862 	pci_read_config_word(hw->pdev, PCI_SUBSYSTEM_ID, &hw->subsystem_id);
4863 
4864 	pci_read_config_byte(hw->pdev, PCI_REVISION_ID, &hw->revision_id);
4865 	pci_read_config_word(hw->pdev, PCI_COMMAND, &hw->pci_cmd_word);
4866 #endif
4867 
4868 	/* identify the MAC */
4869 	result = e1000_set_mac_type(hw);
4870 	if (result) {
4871 		E1000_ERR(hw, "Unknown MAC Type\n");
4872 		return result;
4873 	}
4874 
4875 	switch (hw->mac_type) {
4876 	default:
4877 		break;
4878 	case e1000_82541:
4879 	case e1000_82547:
4880 	case e1000_82541_rev_2:
4881 	case e1000_82547_rev_2:
4882 		hw->phy_init_script = 1;
4883 		break;
4884 	}
4885 
4886 	/* flow control settings */
4887 	hw->fc_high_water = E1000_FC_HIGH_THRESH;
4888 	hw->fc_low_water = E1000_FC_LOW_THRESH;
4889 	hw->fc_pause_time = E1000_FC_PAUSE_TIME;
4890 	hw->fc_send_xon = 1;
4891 
4892 	/* Media type - copper or fiber */
4893 	hw->tbi_compatibility_en = true;
4894 	e1000_set_media_type(hw);
4895 
4896 	if (hw->mac_type >= e1000_82543) {
4897 		uint32_t status = E1000_READ_REG(hw, STATUS);
4898 
4899 		if (status & E1000_STATUS_TBIMODE) {
4900 			DEBUGOUT("fiber interface\n");
4901 			hw->media_type = e1000_media_type_fiber;
4902 		} else {
4903 			DEBUGOUT("copper interface\n");
4904 			hw->media_type = e1000_media_type_copper;
4905 		}
4906 	} else {
4907 		hw->media_type = e1000_media_type_fiber;
4908 	}
4909 
4910 	hw->wait_autoneg_complete = true;
4911 	if (hw->mac_type < e1000_82543)
4912 		hw->report_tx_early = 0;
4913 	else
4914 		hw->report_tx_early = 1;
4915 
4916 	return E1000_SUCCESS;
4917 }
4918 
4919 void
4920 fill_rx(struct e1000_hw *hw)
4921 {
4922 	struct e1000_rx_desc *rd;
4923 	unsigned long flush_start, flush_end;
4924 
4925 	rx_last = rx_tail;
4926 	rd = rx_base + rx_tail;
4927 	rx_tail = (rx_tail + 1) % 8;
4928 	memset(rd, 0, 16);
4929 	rd->buffer_addr = cpu_to_le64((unsigned long)packet);
4930 
4931 	/*
4932 	 * Make sure there are no stale data in WB over this area, which
4933 	 * might get written into the memory while the e1000 also writes
4934 	 * into the same memory area.
4935 	 */
4936 	invalidate_dcache_range((unsigned long)packet,
4937 				(unsigned long)packet + 4096);
4938 	/* Dump the DMA descriptor into RAM. */
4939 	flush_start = ((unsigned long)rd) & ~(ARCH_DMA_MINALIGN - 1);
4940 	flush_end = flush_start + roundup(sizeof(*rd), ARCH_DMA_MINALIGN);
4941 	flush_dcache_range(flush_start, flush_end);
4942 
4943 	E1000_WRITE_REG(hw, RDT, rx_tail);
4944 }
4945 
4946 /**
4947  * e1000_configure_tx - Configure 8254x Transmit Unit after Reset
4948  * @adapter: board private structure
4949  *
4950  * Configure the Tx unit of the MAC after a reset.
4951  **/
4952 
4953 static void
4954 e1000_configure_tx(struct e1000_hw *hw)
4955 {
4956 	unsigned long tctl;
4957 	unsigned long tipg, tarc;
4958 	uint32_t ipgr1, ipgr2;
4959 
4960 	E1000_WRITE_REG(hw, TDBAL, lower_32_bits((unsigned long)tx_base));
4961 	E1000_WRITE_REG(hw, TDBAH, upper_32_bits((unsigned long)tx_base));
4962 
4963 	E1000_WRITE_REG(hw, TDLEN, 128);
4964 
4965 	/* Setup the HW Tx Head and Tail descriptor pointers */
4966 	E1000_WRITE_REG(hw, TDH, 0);
4967 	E1000_WRITE_REG(hw, TDT, 0);
4968 	tx_tail = 0;
4969 
4970 	/* Set the default values for the Tx Inter Packet Gap timer */
4971 	if (hw->mac_type <= e1000_82547_rev_2 &&
4972 	    (hw->media_type == e1000_media_type_fiber ||
4973 	     hw->media_type == e1000_media_type_internal_serdes))
4974 		tipg = DEFAULT_82543_TIPG_IPGT_FIBER;
4975 	else
4976 		tipg = DEFAULT_82543_TIPG_IPGT_COPPER;
4977 
4978 	/* Set the default values for the Tx Inter Packet Gap timer */
4979 	switch (hw->mac_type) {
4980 	case e1000_82542_rev2_0:
4981 	case e1000_82542_rev2_1:
4982 		tipg = DEFAULT_82542_TIPG_IPGT;
4983 		ipgr1 = DEFAULT_82542_TIPG_IPGR1;
4984 		ipgr2 = DEFAULT_82542_TIPG_IPGR2;
4985 		break;
4986 	case e1000_80003es2lan:
4987 		ipgr1 = DEFAULT_82543_TIPG_IPGR1;
4988 		ipgr2 = DEFAULT_80003ES2LAN_TIPG_IPGR2;
4989 		break;
4990 	default:
4991 		ipgr1 = DEFAULT_82543_TIPG_IPGR1;
4992 		ipgr2 = DEFAULT_82543_TIPG_IPGR2;
4993 		break;
4994 	}
4995 	tipg |= ipgr1 << E1000_TIPG_IPGR1_SHIFT;
4996 	tipg |= ipgr2 << E1000_TIPG_IPGR2_SHIFT;
4997 	E1000_WRITE_REG(hw, TIPG, tipg);
4998 	/* Program the Transmit Control Register */
4999 	tctl = E1000_READ_REG(hw, TCTL);
5000 	tctl &= ~E1000_TCTL_CT;
5001 	tctl |= E1000_TCTL_EN | E1000_TCTL_PSP |
5002 	    (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
5003 
5004 	if (hw->mac_type == e1000_82571 || hw->mac_type == e1000_82572) {
5005 		tarc = E1000_READ_REG(hw, TARC0);
5006 		/* set the speed mode bit, we'll clear it if we're not at
5007 		 * gigabit link later */
5008 		/* git bit can be set to 1*/
5009 	} else if (hw->mac_type == e1000_80003es2lan) {
5010 		tarc = E1000_READ_REG(hw, TARC0);
5011 		tarc |= 1;
5012 		E1000_WRITE_REG(hw, TARC0, tarc);
5013 		tarc = E1000_READ_REG(hw, TARC1);
5014 		tarc |= 1;
5015 		E1000_WRITE_REG(hw, TARC1, tarc);
5016 	}
5017 
5018 
5019 	e1000_config_collision_dist(hw);
5020 	/* Setup Transmit Descriptor Settings for eop descriptor */
5021 	hw->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS;
5022 
5023 	/* Need to set up RS bit */
5024 	if (hw->mac_type < e1000_82543)
5025 		hw->txd_cmd |= E1000_TXD_CMD_RPS;
5026 	else
5027 		hw->txd_cmd |= E1000_TXD_CMD_RS;
5028 
5029 
5030 	if (hw->mac_type == e1000_igb) {
5031 		E1000_WRITE_REG(hw, TCTL_EXT, 0x42 << 10);
5032 
5033 		uint32_t reg_txdctl = E1000_READ_REG(hw, TXDCTL);
5034 		reg_txdctl |= 1 << 25;
5035 		E1000_WRITE_REG(hw, TXDCTL, reg_txdctl);
5036 		mdelay(20);
5037 	}
5038 
5039 
5040 
5041 	E1000_WRITE_REG(hw, TCTL, tctl);
5042 
5043 
5044 }
5045 
5046 /**
5047  * e1000_setup_rctl - configure the receive control register
5048  * @adapter: Board private structure
5049  **/
5050 static void
5051 e1000_setup_rctl(struct e1000_hw *hw)
5052 {
5053 	uint32_t rctl;
5054 
5055 	rctl = E1000_READ_REG(hw, RCTL);
5056 
5057 	rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
5058 
5059 	rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO
5060 		| E1000_RCTL_RDMTS_HALF;	/* |
5061 			(hw.mc_filter_type << E1000_RCTL_MO_SHIFT); */
5062 
5063 	if (hw->tbi_compatibility_on == 1)
5064 		rctl |= E1000_RCTL_SBP;
5065 	else
5066 		rctl &= ~E1000_RCTL_SBP;
5067 
5068 	rctl &= ~(E1000_RCTL_SZ_4096);
5069 		rctl |= E1000_RCTL_SZ_2048;
5070 		rctl &= ~(E1000_RCTL_BSEX | E1000_RCTL_LPE);
5071 	E1000_WRITE_REG(hw, RCTL, rctl);
5072 }
5073 
5074 /**
5075  * e1000_configure_rx - Configure 8254x Receive Unit after Reset
5076  * @adapter: board private structure
5077  *
5078  * Configure the Rx unit of the MAC after a reset.
5079  **/
5080 static void
5081 e1000_configure_rx(struct e1000_hw *hw)
5082 {
5083 	unsigned long rctl, ctrl_ext;
5084 	rx_tail = 0;
5085 
5086 	/* make sure receives are disabled while setting up the descriptors */
5087 	rctl = E1000_READ_REG(hw, RCTL);
5088 	E1000_WRITE_REG(hw, RCTL, rctl & ~E1000_RCTL_EN);
5089 	if (hw->mac_type >= e1000_82540) {
5090 		/* Set the interrupt throttling rate.  Value is calculated
5091 		 * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns) */
5092 #define MAX_INTS_PER_SEC	8000
5093 #define DEFAULT_ITR		1000000000/(MAX_INTS_PER_SEC * 256)
5094 		E1000_WRITE_REG(hw, ITR, DEFAULT_ITR);
5095 	}
5096 
5097 	if (hw->mac_type >= e1000_82571) {
5098 		ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
5099 		/* Reset delay timers after every interrupt */
5100 		ctrl_ext |= E1000_CTRL_EXT_INT_TIMER_CLR;
5101 		E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
5102 		E1000_WRITE_FLUSH(hw);
5103 	}
5104 	/* Setup the Base and Length of the Rx Descriptor Ring */
5105 	E1000_WRITE_REG(hw, RDBAL, lower_32_bits((unsigned long)rx_base));
5106 	E1000_WRITE_REG(hw, RDBAH, upper_32_bits((unsigned long)rx_base));
5107 
5108 	E1000_WRITE_REG(hw, RDLEN, 128);
5109 
5110 	/* Setup the HW Rx Head and Tail Descriptor Pointers */
5111 	E1000_WRITE_REG(hw, RDH, 0);
5112 	E1000_WRITE_REG(hw, RDT, 0);
5113 	/* Enable Receives */
5114 
5115 	if (hw->mac_type == e1000_igb) {
5116 
5117 		uint32_t reg_rxdctl = E1000_READ_REG(hw, RXDCTL);
5118 		reg_rxdctl |= 1 << 25;
5119 		E1000_WRITE_REG(hw, RXDCTL, reg_rxdctl);
5120 		mdelay(20);
5121 	}
5122 
5123 	E1000_WRITE_REG(hw, RCTL, rctl);
5124 
5125 	fill_rx(hw);
5126 }
5127 
5128 /**************************************************************************
5129 POLL - Wait for a frame
5130 ***************************************************************************/
5131 static int
5132 _e1000_poll(struct e1000_hw *hw)
5133 {
5134 	struct e1000_rx_desc *rd;
5135 	unsigned long inval_start, inval_end;
5136 	uint32_t len;
5137 
5138 	/* return true if there's an ethernet packet ready to read */
5139 	rd = rx_base + rx_last;
5140 
5141 	/* Re-load the descriptor from RAM. */
5142 	inval_start = ((unsigned long)rd) & ~(ARCH_DMA_MINALIGN - 1);
5143 	inval_end = inval_start + roundup(sizeof(*rd), ARCH_DMA_MINALIGN);
5144 	invalidate_dcache_range(inval_start, inval_end);
5145 
5146 	if (!(rd->status & E1000_RXD_STAT_DD))
5147 		return 0;
5148 	/* DEBUGOUT("recv: packet len=%d\n", rd->length); */
5149 	/* Packet received, make sure the data are re-loaded from RAM. */
5150 	len = le16_to_cpu(rd->length);
5151 	invalidate_dcache_range((unsigned long)packet,
5152 				(unsigned long)packet +
5153 				roundup(len, ARCH_DMA_MINALIGN));
5154 	return len;
5155 }
5156 
5157 static int _e1000_transmit(struct e1000_hw *hw, void *txpacket, int length)
5158 {
5159 	void *nv_packet = (void *)txpacket;
5160 	struct e1000_tx_desc *txp;
5161 	int i = 0;
5162 	unsigned long flush_start, flush_end;
5163 
5164 	txp = tx_base + tx_tail;
5165 	tx_tail = (tx_tail + 1) % 8;
5166 
5167 	txp->buffer_addr = cpu_to_le64(virt_to_bus(hw->pdev, nv_packet));
5168 	txp->lower.data = cpu_to_le32(hw->txd_cmd | length);
5169 	txp->upper.data = 0;
5170 
5171 	/* Dump the packet into RAM so e1000 can pick them. */
5172 	flush_dcache_range((unsigned long)nv_packet,
5173 			   (unsigned long)nv_packet +
5174 			   roundup(length, ARCH_DMA_MINALIGN));
5175 	/* Dump the descriptor into RAM as well. */
5176 	flush_start = ((unsigned long)txp) & ~(ARCH_DMA_MINALIGN - 1);
5177 	flush_end = flush_start + roundup(sizeof(*txp), ARCH_DMA_MINALIGN);
5178 	flush_dcache_range(flush_start, flush_end);
5179 
5180 	E1000_WRITE_REG(hw, TDT, tx_tail);
5181 
5182 	E1000_WRITE_FLUSH(hw);
5183 	while (1) {
5184 		invalidate_dcache_range(flush_start, flush_end);
5185 		if (le32_to_cpu(txp->upper.data) & E1000_TXD_STAT_DD)
5186 			break;
5187 		if (i++ > TOUT_LOOP) {
5188 			DEBUGOUT("e1000: tx timeout\n");
5189 			return 0;
5190 		}
5191 		udelay(10);	/* give the nic a chance to write to the register */
5192 	}
5193 	return 1;
5194 }
5195 
5196 static void
5197 _e1000_disable(struct e1000_hw *hw)
5198 {
5199 	/* Turn off the ethernet interface */
5200 	E1000_WRITE_REG(hw, RCTL, 0);
5201 	E1000_WRITE_REG(hw, TCTL, 0);
5202 
5203 	/* Clear the transmit ring */
5204 	E1000_WRITE_REG(hw, TDH, 0);
5205 	E1000_WRITE_REG(hw, TDT, 0);
5206 
5207 	/* Clear the receive ring */
5208 	E1000_WRITE_REG(hw, RDH, 0);
5209 	E1000_WRITE_REG(hw, RDT, 0);
5210 
5211 	mdelay(10);
5212 }
5213 
5214 /*reset function*/
5215 static inline int
5216 e1000_reset(struct e1000_hw *hw, unsigned char enetaddr[6])
5217 {
5218 	e1000_reset_hw(hw);
5219 	if (hw->mac_type >= e1000_82544)
5220 		E1000_WRITE_REG(hw, WUC, 0);
5221 
5222 	return e1000_init_hw(hw, enetaddr);
5223 }
5224 
5225 static int
5226 _e1000_init(struct e1000_hw *hw, unsigned char enetaddr[6])
5227 {
5228 	int ret_val = 0;
5229 
5230 	ret_val = e1000_reset(hw, enetaddr);
5231 	if (ret_val < 0) {
5232 		if ((ret_val == -E1000_ERR_NOLINK) ||
5233 		    (ret_val == -E1000_ERR_TIMEOUT)) {
5234 			E1000_ERR(hw, "Valid Link not detected: %d\n", ret_val);
5235 		} else {
5236 			E1000_ERR(hw, "Hardware Initialization Failed\n");
5237 		}
5238 		return ret_val;
5239 	}
5240 	e1000_configure_tx(hw);
5241 	e1000_setup_rctl(hw);
5242 	e1000_configure_rx(hw);
5243 	return 0;
5244 }
5245 
5246 /******************************************************************************
5247  * Gets the current PCI bus type of hardware
5248  *
5249  * hw - Struct containing variables accessed by shared code
5250  *****************************************************************************/
5251 void e1000_get_bus_type(struct e1000_hw *hw)
5252 {
5253 	uint32_t status;
5254 
5255 	switch (hw->mac_type) {
5256 	case e1000_82542_rev2_0:
5257 	case e1000_82542_rev2_1:
5258 		hw->bus_type = e1000_bus_type_pci;
5259 		break;
5260 	case e1000_82571:
5261 	case e1000_82572:
5262 	case e1000_82573:
5263 	case e1000_82574:
5264 	case e1000_80003es2lan:
5265 	case e1000_ich8lan:
5266 	case e1000_igb:
5267 		hw->bus_type = e1000_bus_type_pci_express;
5268 		break;
5269 	default:
5270 		status = E1000_READ_REG(hw, STATUS);
5271 		hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ?
5272 				e1000_bus_type_pcix : e1000_bus_type_pci;
5273 		break;
5274 	}
5275 }
5276 
5277 #ifndef CONFIG_DM_ETH
5278 /* A list of all registered e1000 devices */
5279 static LIST_HEAD(e1000_hw_list);
5280 #endif
5281 
5282 #ifdef CONFIG_DM_ETH
5283 static int e1000_init_one(struct e1000_hw *hw, int cardnum,
5284 			  struct udevice *devno, unsigned char enetaddr[6])
5285 #else
5286 static int e1000_init_one(struct e1000_hw *hw, int cardnum, pci_dev_t devno,
5287 			  unsigned char enetaddr[6])
5288 #endif
5289 {
5290 	u32 val;
5291 
5292 	/* Assign the passed-in values */
5293 #ifdef CONFIG_DM_ETH
5294 	hw->pdev = devno;
5295 #else
5296 	hw->pdev = devno;
5297 #endif
5298 	hw->cardnum = cardnum;
5299 
5300 	/* Print a debug message with the IO base address */
5301 #ifdef CONFIG_DM_ETH
5302 	dm_pci_read_config32(devno, PCI_BASE_ADDRESS_0, &val);
5303 #else
5304 	pci_read_config_dword(devno, PCI_BASE_ADDRESS_0, &val);
5305 #endif
5306 	E1000_DBG(hw, "iobase 0x%08x\n", val & 0xfffffff0);
5307 
5308 	/* Try to enable I/O accesses and bus-mastering */
5309 	val = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
5310 #ifdef CONFIG_DM_ETH
5311 	dm_pci_write_config32(devno, PCI_COMMAND, val);
5312 #else
5313 	pci_write_config_dword(devno, PCI_COMMAND, val);
5314 #endif
5315 
5316 	/* Make sure it worked */
5317 #ifdef CONFIG_DM_ETH
5318 	dm_pci_read_config32(devno, PCI_COMMAND, &val);
5319 #else
5320 	pci_read_config_dword(devno, PCI_COMMAND, &val);
5321 #endif
5322 	if (!(val & PCI_COMMAND_MEMORY)) {
5323 		E1000_ERR(hw, "Can't enable I/O memory\n");
5324 		return -ENOSPC;
5325 	}
5326 	if (!(val & PCI_COMMAND_MASTER)) {
5327 		E1000_ERR(hw, "Can't enable bus-mastering\n");
5328 		return -EPERM;
5329 	}
5330 
5331 	/* Are these variables needed? */
5332 	hw->fc = e1000_fc_default;
5333 	hw->original_fc = e1000_fc_default;
5334 	hw->autoneg_failed = 0;
5335 	hw->autoneg = 1;
5336 	hw->get_link_status = true;
5337 #ifndef CONFIG_E1000_NO_NVM
5338 	hw->eeprom_semaphore_present = true;
5339 #endif
5340 #ifdef CONFIG_DM_ETH
5341 	hw->hw_addr = dm_pci_map_bar(devno,	PCI_BASE_ADDRESS_0,
5342 						PCI_REGION_MEM);
5343 #else
5344 	hw->hw_addr = pci_map_bar(devno,	PCI_BASE_ADDRESS_0,
5345 						PCI_REGION_MEM);
5346 #endif
5347 	hw->mac_type = e1000_undefined;
5348 
5349 	/* MAC and Phy settings */
5350 	if (e1000_sw_init(hw) < 0) {
5351 		E1000_ERR(hw, "Software init failed\n");
5352 		return -EIO;
5353 	}
5354 	if (e1000_check_phy_reset_block(hw))
5355 		E1000_ERR(hw, "PHY Reset is blocked!\n");
5356 
5357 	/* Basic init was OK, reset the hardware and allow SPI access */
5358 	e1000_reset_hw(hw);
5359 
5360 #ifndef CONFIG_E1000_NO_NVM
5361 	/* Validate the EEPROM and get chipset information */
5362 	if (e1000_init_eeprom_params(hw)) {
5363 		E1000_ERR(hw, "EEPROM is invalid!\n");
5364 		return -EINVAL;
5365 	}
5366 	if ((E1000_READ_REG(hw, I210_EECD) & E1000_EECD_FLUPD) &&
5367 	    e1000_validate_eeprom_checksum(hw))
5368 		return -ENXIO;
5369 	e1000_read_mac_addr(hw, enetaddr);
5370 #endif
5371 	e1000_get_bus_type(hw);
5372 
5373 #ifndef CONFIG_E1000_NO_NVM
5374 	printf("e1000: %02x:%02x:%02x:%02x:%02x:%02x\n       ",
5375 	       enetaddr[0], enetaddr[1], enetaddr[2],
5376 	       enetaddr[3], enetaddr[4], enetaddr[5]);
5377 #else
5378 	memset(enetaddr, 0, 6);
5379 	printf("e1000: no NVM\n");
5380 #endif
5381 
5382 	return 0;
5383 }
5384 
5385 /* Put the name of a device in a string */
5386 static void e1000_name(char *str, int cardnum)
5387 {
5388 	sprintf(str, "e1000#%u", cardnum);
5389 }
5390 
5391 #ifndef CONFIG_DM_ETH
5392 /**************************************************************************
5393 TRANSMIT - Transmit a frame
5394 ***************************************************************************/
5395 static int e1000_transmit(struct eth_device *nic, void *txpacket, int length)
5396 {
5397 	struct e1000_hw *hw = nic->priv;
5398 
5399 	return _e1000_transmit(hw, txpacket, length);
5400 }
5401 
5402 /**************************************************************************
5403 DISABLE - Turn off ethernet interface
5404 ***************************************************************************/
5405 static void
5406 e1000_disable(struct eth_device *nic)
5407 {
5408 	struct e1000_hw *hw = nic->priv;
5409 
5410 	_e1000_disable(hw);
5411 }
5412 
5413 /**************************************************************************
5414 INIT - set up ethernet interface(s)
5415 ***************************************************************************/
5416 static int
5417 e1000_init(struct eth_device *nic, bd_t *bis)
5418 {
5419 	struct e1000_hw *hw = nic->priv;
5420 
5421 	return _e1000_init(hw, nic->enetaddr);
5422 }
5423 
5424 static int
5425 e1000_poll(struct eth_device *nic)
5426 {
5427 	struct e1000_hw *hw = nic->priv;
5428 	int len;
5429 
5430 	len = _e1000_poll(hw);
5431 	if (len) {
5432 		net_process_received_packet((uchar *)packet, len);
5433 		fill_rx(hw);
5434 	}
5435 
5436 	return len ? 1 : 0;
5437 }
5438 
5439 /**************************************************************************
5440 PROBE - Look for an adapter, this routine's visible to the outside
5441 You should omit the last argument struct pci_device * for a non-PCI NIC
5442 ***************************************************************************/
5443 int
5444 e1000_initialize(bd_t * bis)
5445 {
5446 	unsigned int i;
5447 	pci_dev_t devno;
5448 	int ret;
5449 
5450 	DEBUGFUNC();
5451 
5452 	/* Find and probe all the matching PCI devices */
5453 	for (i = 0; (devno = pci_find_devices(e1000_supported, i)) >= 0; i++) {
5454 		/*
5455 		 * These will never get freed due to errors, this allows us to
5456 		 * perform SPI EEPROM programming from U-Boot, for example.
5457 		 */
5458 		struct eth_device *nic = malloc(sizeof(*nic));
5459 		struct e1000_hw *hw = malloc(sizeof(*hw));
5460 		if (!nic || !hw) {
5461 			printf("e1000#%u: Out of Memory!\n", i);
5462 			free(nic);
5463 			free(hw);
5464 			continue;
5465 		}
5466 
5467 		/* Make sure all of the fields are initially zeroed */
5468 		memset(nic, 0, sizeof(*nic));
5469 		memset(hw, 0, sizeof(*hw));
5470 		nic->priv = hw;
5471 
5472 		/* Generate a card name */
5473 		e1000_name(nic->name, i);
5474 		hw->name = nic->name;
5475 
5476 		ret = e1000_init_one(hw, i, devno, nic->enetaddr);
5477 		if (ret)
5478 			continue;
5479 		list_add_tail(&hw->list_node, &e1000_hw_list);
5480 
5481 		hw->nic = nic;
5482 
5483 		/* Set up the function pointers and register the device */
5484 		nic->init = e1000_init;
5485 		nic->recv = e1000_poll;
5486 		nic->send = e1000_transmit;
5487 		nic->halt = e1000_disable;
5488 		eth_register(nic);
5489 	}
5490 
5491 	return i;
5492 }
5493 
5494 struct e1000_hw *e1000_find_card(unsigned int cardnum)
5495 {
5496 	struct e1000_hw *hw;
5497 
5498 	list_for_each_entry(hw, &e1000_hw_list, list_node)
5499 		if (hw->cardnum == cardnum)
5500 			return hw;
5501 
5502 	return NULL;
5503 }
5504 #endif /* !CONFIG_DM_ETH */
5505 
5506 #ifdef CONFIG_CMD_E1000
5507 static int do_e1000(cmd_tbl_t *cmdtp, int flag,
5508 		int argc, char * const argv[])
5509 {
5510 	unsigned char *mac = NULL;
5511 #ifdef CONFIG_DM_ETH
5512 	struct eth_pdata *plat;
5513 	struct udevice *dev;
5514 	char name[30];
5515 	int ret;
5516 #else
5517 	struct e1000_hw *hw;
5518 #endif
5519 	int cardnum;
5520 
5521 	if (argc < 3) {
5522 		cmd_usage(cmdtp);
5523 		return 1;
5524 	}
5525 
5526 	/* Make sure we can find the requested e1000 card */
5527 	cardnum = simple_strtoul(argv[1], NULL, 10);
5528 #ifdef CONFIG_DM_ETH
5529 	e1000_name(name, cardnum);
5530 	ret = uclass_get_device_by_name(UCLASS_ETH, name, &dev);
5531 	if (!ret) {
5532 		plat = dev_get_platdata(dev);
5533 		mac = plat->enetaddr;
5534 	}
5535 #else
5536 	hw = e1000_find_card(cardnum);
5537 	if (hw)
5538 		mac = hw->nic->enetaddr;
5539 #endif
5540 	if (!mac) {
5541 		printf("e1000: ERROR: No such device: e1000#%s\n", argv[1]);
5542 		return 1;
5543 	}
5544 
5545 	if (!strcmp(argv[2], "print-mac-address")) {
5546 		printf("%02x:%02x:%02x:%02x:%02x:%02x\n",
5547 			mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
5548 		return 0;
5549 	}
5550 
5551 #ifdef CONFIG_E1000_SPI
5552 	/* Handle the "SPI" subcommand */
5553 	if (!strcmp(argv[2], "spi"))
5554 		return do_e1000_spi(cmdtp, hw, argc - 3, argv + 3);
5555 #endif
5556 
5557 	cmd_usage(cmdtp);
5558 	return 1;
5559 }
5560 
5561 U_BOOT_CMD(
5562 	e1000, 7, 0, do_e1000,
5563 	"Intel e1000 controller management",
5564 	/*  */"<card#> print-mac-address\n"
5565 #ifdef CONFIG_E1000_SPI
5566 	"e1000 <card#> spi show [<offset> [<length>]]\n"
5567 	"e1000 <card#> spi dump <addr> <offset> <length>\n"
5568 	"e1000 <card#> spi program <addr> <offset> <length>\n"
5569 	"e1000 <card#> spi checksum [update]\n"
5570 #endif
5571 	"       - Manage the Intel E1000 PCI device"
5572 );
5573 #endif /* not CONFIG_CMD_E1000 */
5574 
5575 #ifdef CONFIG_DM_ETH
5576 static int e1000_eth_start(struct udevice *dev)
5577 {
5578 	struct eth_pdata *plat = dev_get_platdata(dev);
5579 	struct e1000_hw *hw = dev_get_priv(dev);
5580 
5581 	return _e1000_init(hw, plat->enetaddr);
5582 }
5583 
5584 static void e1000_eth_stop(struct udevice *dev)
5585 {
5586 	struct e1000_hw *hw = dev_get_priv(dev);
5587 
5588 	_e1000_disable(hw);
5589 }
5590 
5591 static int e1000_eth_send(struct udevice *dev, void *packet, int length)
5592 {
5593 	struct e1000_hw *hw = dev_get_priv(dev);
5594 	int ret;
5595 
5596 	ret = _e1000_transmit(hw, packet, length);
5597 
5598 	return ret ? 0 : -ETIMEDOUT;
5599 }
5600 
5601 static int e1000_eth_recv(struct udevice *dev, int flags, uchar **packetp)
5602 {
5603 	struct e1000_hw *hw = dev_get_priv(dev);
5604 	int len;
5605 
5606 	len = _e1000_poll(hw);
5607 	if (len)
5608 		*packetp = packet;
5609 
5610 	return len ? len : -EAGAIN;
5611 }
5612 
5613 static int e1000_free_pkt(struct udevice *dev, uchar *packet, int length)
5614 {
5615 	struct e1000_hw *hw = dev_get_priv(dev);
5616 
5617 	fill_rx(hw);
5618 
5619 	return 0;
5620 }
5621 
5622 static int e1000_eth_probe(struct udevice *dev)
5623 {
5624 	struct eth_pdata *plat = dev_get_platdata(dev);
5625 	struct e1000_hw *hw = dev_get_priv(dev);
5626 	int ret;
5627 
5628 	hw->name = dev->name;
5629 	ret = e1000_init_one(hw, trailing_strtol(dev->name),
5630 			     dev, plat->enetaddr);
5631 	if (ret < 0) {
5632 		printf(pr_fmt("failed to initialize card: %d\n"), ret);
5633 		return ret;
5634 	}
5635 
5636 	return 0;
5637 }
5638 
5639 static int e1000_eth_bind(struct udevice *dev)
5640 {
5641 	char name[20];
5642 
5643 	/*
5644 	 * A simple way to number the devices. When device tree is used this
5645 	 * is unnecessary, but when the device is just discovered on the PCI
5646 	 * bus we need a name. We could instead have the uclass figure out
5647 	 * which devices are different and number them.
5648 	 */
5649 	e1000_name(name, num_cards++);
5650 
5651 	return device_set_name(dev, name);
5652 }
5653 
5654 static const struct eth_ops e1000_eth_ops = {
5655 	.start	= e1000_eth_start,
5656 	.send	= e1000_eth_send,
5657 	.recv	= e1000_eth_recv,
5658 	.stop	= e1000_eth_stop,
5659 	.free_pkt = e1000_free_pkt,
5660 };
5661 
5662 static const struct udevice_id e1000_eth_ids[] = {
5663 	{ .compatible = "intel,e1000" },
5664 	{ }
5665 };
5666 
5667 U_BOOT_DRIVER(eth_e1000) = {
5668 	.name	= "eth_e1000",
5669 	.id	= UCLASS_ETH,
5670 	.of_match = e1000_eth_ids,
5671 	.bind	= e1000_eth_bind,
5672 	.probe	= e1000_eth_probe,
5673 	.ops	= &e1000_eth_ops,
5674 	.priv_auto_alloc_size = sizeof(struct e1000_hw),
5675 	.platdata_auto_alloc_size = sizeof(struct eth_pdata),
5676 };
5677 
5678 U_BOOT_PCI_DEVICE(eth_e1000, e1000_supported);
5679 #endif
5680