1 /************************************************************************** 2 Intel Pro 1000 for ppcboot/das-u-boot 3 Drivers are port from Intel's Linux driver e1000-4.3.15 4 and from Etherboot pro 1000 driver by mrakes at vivato dot net 5 tested on both gig copper and gig fiber boards 6 ***************************************************************************/ 7 /******************************************************************************* 8 9 10 Copyright(c) 1999 - 2002 Intel Corporation. All rights reserved. 11 12 * SPDX-License-Identifier: GPL-2.0+ 13 14 Contact Information: 15 Linux NICS <linux.nics@intel.com> 16 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 17 18 *******************************************************************************/ 19 /* 20 * Copyright (C) Archway Digital Solutions. 21 * 22 * written by Chrsitopher Li <cli at arcyway dot com> or <chrisl at gnuchina dot org> 23 * 2/9/2002 24 * 25 * Copyright (C) Linux Networx. 26 * Massive upgrade to work with the new intel gigabit NICs. 27 * <ebiederman at lnxi dot com> 28 * 29 * Copyright 2011 Freescale Semiconductor, Inc. 30 */ 31 32 #include "e1000.h" 33 34 #define TOUT_LOOP 100000 35 36 #define virt_to_bus(devno, v) pci_virt_to_mem(devno, (void *) (v)) 37 #define bus_to_phys(devno, a) pci_mem_to_phys(devno, a) 38 39 #define E1000_DEFAULT_PCI_PBA 0x00000030 40 #define E1000_DEFAULT_PCIE_PBA 0x000a0026 41 42 /* NIC specific static variables go here */ 43 44 /* Intel i210 needs the DMA descriptor rings aligned to 128b */ 45 #define E1000_BUFFER_ALIGN 128 46 47 DEFINE_ALIGN_BUFFER(struct e1000_tx_desc, tx_base, 16, E1000_BUFFER_ALIGN); 48 DEFINE_ALIGN_BUFFER(struct e1000_rx_desc, rx_base, 16, E1000_BUFFER_ALIGN); 49 DEFINE_ALIGN_BUFFER(unsigned char, packet, 4096, E1000_BUFFER_ALIGN); 50 51 static int tx_tail; 52 static int rx_tail, rx_last; 53 54 static struct pci_device_id e1000_supported[] = { 55 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82542}, 56 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82543GC_FIBER}, 57 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82543GC_COPPER}, 58 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544EI_COPPER}, 59 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544EI_FIBER}, 60 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544GC_COPPER}, 61 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544GC_LOM}, 62 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82540EM}, 63 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545EM_COPPER}, 64 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545GM_COPPER}, 65 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_COPPER}, 66 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545EM_FIBER}, 67 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_FIBER}, 68 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546GB_COPPER}, 69 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82540EM_LOM}, 70 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82541ER}, 71 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82541GI_LF}, 72 /* E1000 PCIe card */ 73 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_COPPER}, 74 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_FIBER }, 75 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES }, 76 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_COPPER}, 77 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571PT_QUAD_COPPER}, 78 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_FIBER}, 79 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_COPPER_LOWPROFILE}, 80 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES_DUAL}, 81 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES_QUAD}, 82 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_COPPER}, 83 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_FIBER}, 84 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_SERDES}, 85 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI}, 86 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573E}, 87 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573E_IAMT}, 88 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573L}, 89 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82574L}, 90 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546GB_QUAD_COPPER_KSP3}, 91 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_COPPER_DPT}, 92 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_SERDES_DPT}, 93 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_COPPER_SPT}, 94 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_SERDES_SPT}, 95 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_COPPER}, 96 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_COPPER_FLASHLESS}, 97 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_SERDES}, 98 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_SERDES_FLASHLESS}, 99 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_1000BASEKX}, 100 101 {} 102 }; 103 104 /* Function forward declarations */ 105 static int e1000_setup_link(struct eth_device *nic); 106 static int e1000_setup_fiber_link(struct eth_device *nic); 107 static int e1000_setup_copper_link(struct eth_device *nic); 108 static int e1000_phy_setup_autoneg(struct e1000_hw *hw); 109 static void e1000_config_collision_dist(struct e1000_hw *hw); 110 static int e1000_config_mac_to_phy(struct e1000_hw *hw); 111 static int e1000_config_fc_after_link_up(struct e1000_hw *hw); 112 static int e1000_check_for_link(struct eth_device *nic); 113 static int e1000_wait_autoneg(struct e1000_hw *hw); 114 static int e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t * speed, 115 uint16_t * duplex); 116 static int e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, 117 uint16_t * phy_data); 118 static int e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, 119 uint16_t phy_data); 120 static int32_t e1000_phy_hw_reset(struct e1000_hw *hw); 121 static int e1000_phy_reset(struct e1000_hw *hw); 122 static int e1000_detect_gig_phy(struct e1000_hw *hw); 123 static void e1000_set_media_type(struct e1000_hw *hw); 124 125 static int32_t e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask); 126 static int32_t e1000_check_phy_reset_block(struct e1000_hw *hw); 127 128 #ifndef CONFIG_E1000_NO_NVM 129 static void e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw); 130 static int32_t e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset, 131 uint16_t words, 132 uint16_t *data); 133 /****************************************************************************** 134 * Raises the EEPROM's clock input. 135 * 136 * hw - Struct containing variables accessed by shared code 137 * eecd - EECD's current value 138 *****************************************************************************/ 139 void e1000_raise_ee_clk(struct e1000_hw *hw, uint32_t * eecd) 140 { 141 /* Raise the clock input to the EEPROM (by setting the SK bit), and then 142 * wait 50 microseconds. 143 */ 144 *eecd = *eecd | E1000_EECD_SK; 145 E1000_WRITE_REG(hw, EECD, *eecd); 146 E1000_WRITE_FLUSH(hw); 147 udelay(50); 148 } 149 150 /****************************************************************************** 151 * Lowers the EEPROM's clock input. 152 * 153 * hw - Struct containing variables accessed by shared code 154 * eecd - EECD's current value 155 *****************************************************************************/ 156 void e1000_lower_ee_clk(struct e1000_hw *hw, uint32_t * eecd) 157 { 158 /* Lower the clock input to the EEPROM (by clearing the SK bit), and then 159 * wait 50 microseconds. 160 */ 161 *eecd = *eecd & ~E1000_EECD_SK; 162 E1000_WRITE_REG(hw, EECD, *eecd); 163 E1000_WRITE_FLUSH(hw); 164 udelay(50); 165 } 166 167 /****************************************************************************** 168 * Shift data bits out to the EEPROM. 169 * 170 * hw - Struct containing variables accessed by shared code 171 * data - data to send to the EEPROM 172 * count - number of bits to shift out 173 *****************************************************************************/ 174 static void 175 e1000_shift_out_ee_bits(struct e1000_hw *hw, uint16_t data, uint16_t count) 176 { 177 uint32_t eecd; 178 uint32_t mask; 179 180 /* We need to shift "count" bits out to the EEPROM. So, value in the 181 * "data" parameter will be shifted out to the EEPROM one bit at a time. 182 * In order to do this, "data" must be broken down into bits. 183 */ 184 mask = 0x01 << (count - 1); 185 eecd = E1000_READ_REG(hw, EECD); 186 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI); 187 do { 188 /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1", 189 * and then raising and then lowering the clock (the SK bit controls 190 * the clock input to the EEPROM). A "0" is shifted out to the EEPROM 191 * by setting "DI" to "0" and then raising and then lowering the clock. 192 */ 193 eecd &= ~E1000_EECD_DI; 194 195 if (data & mask) 196 eecd |= E1000_EECD_DI; 197 198 E1000_WRITE_REG(hw, EECD, eecd); 199 E1000_WRITE_FLUSH(hw); 200 201 udelay(50); 202 203 e1000_raise_ee_clk(hw, &eecd); 204 e1000_lower_ee_clk(hw, &eecd); 205 206 mask = mask >> 1; 207 208 } while (mask); 209 210 /* We leave the "DI" bit set to "0" when we leave this routine. */ 211 eecd &= ~E1000_EECD_DI; 212 E1000_WRITE_REG(hw, EECD, eecd); 213 } 214 215 /****************************************************************************** 216 * Shift data bits in from the EEPROM 217 * 218 * hw - Struct containing variables accessed by shared code 219 *****************************************************************************/ 220 static uint16_t 221 e1000_shift_in_ee_bits(struct e1000_hw *hw, uint16_t count) 222 { 223 uint32_t eecd; 224 uint32_t i; 225 uint16_t data; 226 227 /* In order to read a register from the EEPROM, we need to shift 'count' 228 * bits in from the EEPROM. Bits are "shifted in" by raising the clock 229 * input to the EEPROM (setting the SK bit), and then reading the 230 * value of the "DO" bit. During this "shifting in" process the 231 * "DI" bit should always be clear. 232 */ 233 234 eecd = E1000_READ_REG(hw, EECD); 235 236 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI); 237 data = 0; 238 239 for (i = 0; i < count; i++) { 240 data = data << 1; 241 e1000_raise_ee_clk(hw, &eecd); 242 243 eecd = E1000_READ_REG(hw, EECD); 244 245 eecd &= ~(E1000_EECD_DI); 246 if (eecd & E1000_EECD_DO) 247 data |= 1; 248 249 e1000_lower_ee_clk(hw, &eecd); 250 } 251 252 return data; 253 } 254 255 /****************************************************************************** 256 * Returns EEPROM to a "standby" state 257 * 258 * hw - Struct containing variables accessed by shared code 259 *****************************************************************************/ 260 void e1000_standby_eeprom(struct e1000_hw *hw) 261 { 262 struct e1000_eeprom_info *eeprom = &hw->eeprom; 263 uint32_t eecd; 264 265 eecd = E1000_READ_REG(hw, EECD); 266 267 if (eeprom->type == e1000_eeprom_microwire) { 268 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); 269 E1000_WRITE_REG(hw, EECD, eecd); 270 E1000_WRITE_FLUSH(hw); 271 udelay(eeprom->delay_usec); 272 273 /* Clock high */ 274 eecd |= E1000_EECD_SK; 275 E1000_WRITE_REG(hw, EECD, eecd); 276 E1000_WRITE_FLUSH(hw); 277 udelay(eeprom->delay_usec); 278 279 /* Select EEPROM */ 280 eecd |= E1000_EECD_CS; 281 E1000_WRITE_REG(hw, EECD, eecd); 282 E1000_WRITE_FLUSH(hw); 283 udelay(eeprom->delay_usec); 284 285 /* Clock low */ 286 eecd &= ~E1000_EECD_SK; 287 E1000_WRITE_REG(hw, EECD, eecd); 288 E1000_WRITE_FLUSH(hw); 289 udelay(eeprom->delay_usec); 290 } else if (eeprom->type == e1000_eeprom_spi) { 291 /* Toggle CS to flush commands */ 292 eecd |= E1000_EECD_CS; 293 E1000_WRITE_REG(hw, EECD, eecd); 294 E1000_WRITE_FLUSH(hw); 295 udelay(eeprom->delay_usec); 296 eecd &= ~E1000_EECD_CS; 297 E1000_WRITE_REG(hw, EECD, eecd); 298 E1000_WRITE_FLUSH(hw); 299 udelay(eeprom->delay_usec); 300 } 301 } 302 303 /*************************************************************************** 304 * Description: Determines if the onboard NVM is FLASH or EEPROM. 305 * 306 * hw - Struct containing variables accessed by shared code 307 ****************************************************************************/ 308 static bool e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw) 309 { 310 uint32_t eecd = 0; 311 312 DEBUGFUNC(); 313 314 if (hw->mac_type == e1000_ich8lan) 315 return false; 316 317 if (hw->mac_type == e1000_82573 || hw->mac_type == e1000_82574) { 318 eecd = E1000_READ_REG(hw, EECD); 319 320 /* Isolate bits 15 & 16 */ 321 eecd = ((eecd >> 15) & 0x03); 322 323 /* If both bits are set, device is Flash type */ 324 if (eecd == 0x03) 325 return false; 326 } 327 return true; 328 } 329 330 /****************************************************************************** 331 * Prepares EEPROM for access 332 * 333 * hw - Struct containing variables accessed by shared code 334 * 335 * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This 336 * function should be called before issuing a command to the EEPROM. 337 *****************************************************************************/ 338 int32_t e1000_acquire_eeprom(struct e1000_hw *hw) 339 { 340 struct e1000_eeprom_info *eeprom = &hw->eeprom; 341 uint32_t eecd, i = 0; 342 343 DEBUGFUNC(); 344 345 if (e1000_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM)) 346 return -E1000_ERR_SWFW_SYNC; 347 eecd = E1000_READ_REG(hw, EECD); 348 349 if (hw->mac_type != e1000_82573 && hw->mac_type != e1000_82574) { 350 /* Request EEPROM Access */ 351 if (hw->mac_type > e1000_82544) { 352 eecd |= E1000_EECD_REQ; 353 E1000_WRITE_REG(hw, EECD, eecd); 354 eecd = E1000_READ_REG(hw, EECD); 355 while ((!(eecd & E1000_EECD_GNT)) && 356 (i < E1000_EEPROM_GRANT_ATTEMPTS)) { 357 i++; 358 udelay(5); 359 eecd = E1000_READ_REG(hw, EECD); 360 } 361 if (!(eecd & E1000_EECD_GNT)) { 362 eecd &= ~E1000_EECD_REQ; 363 E1000_WRITE_REG(hw, EECD, eecd); 364 DEBUGOUT("Could not acquire EEPROM grant\n"); 365 return -E1000_ERR_EEPROM; 366 } 367 } 368 } 369 370 /* Setup EEPROM for Read/Write */ 371 372 if (eeprom->type == e1000_eeprom_microwire) { 373 /* Clear SK and DI */ 374 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK); 375 E1000_WRITE_REG(hw, EECD, eecd); 376 377 /* Set CS */ 378 eecd |= E1000_EECD_CS; 379 E1000_WRITE_REG(hw, EECD, eecd); 380 } else if (eeprom->type == e1000_eeprom_spi) { 381 /* Clear SK and CS */ 382 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); 383 E1000_WRITE_REG(hw, EECD, eecd); 384 udelay(1); 385 } 386 387 return E1000_SUCCESS; 388 } 389 390 /****************************************************************************** 391 * Sets up eeprom variables in the hw struct. Must be called after mac_type 392 * is configured. Additionally, if this is ICH8, the flash controller GbE 393 * registers must be mapped, or this will crash. 394 * 395 * hw - Struct containing variables accessed by shared code 396 *****************************************************************************/ 397 static int32_t e1000_init_eeprom_params(struct e1000_hw *hw) 398 { 399 struct e1000_eeprom_info *eeprom = &hw->eeprom; 400 uint32_t eecd; 401 int32_t ret_val = E1000_SUCCESS; 402 uint16_t eeprom_size; 403 404 if (hw->mac_type == e1000_igb) 405 eecd = E1000_READ_REG(hw, I210_EECD); 406 else 407 eecd = E1000_READ_REG(hw, EECD); 408 409 DEBUGFUNC(); 410 411 switch (hw->mac_type) { 412 case e1000_82542_rev2_0: 413 case e1000_82542_rev2_1: 414 case e1000_82543: 415 case e1000_82544: 416 eeprom->type = e1000_eeprom_microwire; 417 eeprom->word_size = 64; 418 eeprom->opcode_bits = 3; 419 eeprom->address_bits = 6; 420 eeprom->delay_usec = 50; 421 eeprom->use_eerd = false; 422 eeprom->use_eewr = false; 423 break; 424 case e1000_82540: 425 case e1000_82545: 426 case e1000_82545_rev_3: 427 case e1000_82546: 428 case e1000_82546_rev_3: 429 eeprom->type = e1000_eeprom_microwire; 430 eeprom->opcode_bits = 3; 431 eeprom->delay_usec = 50; 432 if (eecd & E1000_EECD_SIZE) { 433 eeprom->word_size = 256; 434 eeprom->address_bits = 8; 435 } else { 436 eeprom->word_size = 64; 437 eeprom->address_bits = 6; 438 } 439 eeprom->use_eerd = false; 440 eeprom->use_eewr = false; 441 break; 442 case e1000_82541: 443 case e1000_82541_rev_2: 444 case e1000_82547: 445 case e1000_82547_rev_2: 446 if (eecd & E1000_EECD_TYPE) { 447 eeprom->type = e1000_eeprom_spi; 448 eeprom->opcode_bits = 8; 449 eeprom->delay_usec = 1; 450 if (eecd & E1000_EECD_ADDR_BITS) { 451 eeprom->page_size = 32; 452 eeprom->address_bits = 16; 453 } else { 454 eeprom->page_size = 8; 455 eeprom->address_bits = 8; 456 } 457 } else { 458 eeprom->type = e1000_eeprom_microwire; 459 eeprom->opcode_bits = 3; 460 eeprom->delay_usec = 50; 461 if (eecd & E1000_EECD_ADDR_BITS) { 462 eeprom->word_size = 256; 463 eeprom->address_bits = 8; 464 } else { 465 eeprom->word_size = 64; 466 eeprom->address_bits = 6; 467 } 468 } 469 eeprom->use_eerd = false; 470 eeprom->use_eewr = false; 471 break; 472 case e1000_82571: 473 case e1000_82572: 474 eeprom->type = e1000_eeprom_spi; 475 eeprom->opcode_bits = 8; 476 eeprom->delay_usec = 1; 477 if (eecd & E1000_EECD_ADDR_BITS) { 478 eeprom->page_size = 32; 479 eeprom->address_bits = 16; 480 } else { 481 eeprom->page_size = 8; 482 eeprom->address_bits = 8; 483 } 484 eeprom->use_eerd = false; 485 eeprom->use_eewr = false; 486 break; 487 case e1000_82573: 488 case e1000_82574: 489 eeprom->type = e1000_eeprom_spi; 490 eeprom->opcode_bits = 8; 491 eeprom->delay_usec = 1; 492 if (eecd & E1000_EECD_ADDR_BITS) { 493 eeprom->page_size = 32; 494 eeprom->address_bits = 16; 495 } else { 496 eeprom->page_size = 8; 497 eeprom->address_bits = 8; 498 } 499 if (e1000_is_onboard_nvm_eeprom(hw) == false) { 500 eeprom->use_eerd = true; 501 eeprom->use_eewr = true; 502 503 eeprom->type = e1000_eeprom_flash; 504 eeprom->word_size = 2048; 505 506 /* Ensure that the Autonomous FLASH update bit is cleared due to 507 * Flash update issue on parts which use a FLASH for NVM. */ 508 eecd &= ~E1000_EECD_AUPDEN; 509 E1000_WRITE_REG(hw, EECD, eecd); 510 } 511 break; 512 case e1000_80003es2lan: 513 eeprom->type = e1000_eeprom_spi; 514 eeprom->opcode_bits = 8; 515 eeprom->delay_usec = 1; 516 if (eecd & E1000_EECD_ADDR_BITS) { 517 eeprom->page_size = 32; 518 eeprom->address_bits = 16; 519 } else { 520 eeprom->page_size = 8; 521 eeprom->address_bits = 8; 522 } 523 eeprom->use_eerd = true; 524 eeprom->use_eewr = false; 525 break; 526 case e1000_igb: 527 /* i210 has 4k of iNVM mapped as EEPROM */ 528 eeprom->type = e1000_eeprom_invm; 529 eeprom->opcode_bits = 8; 530 eeprom->delay_usec = 1; 531 eeprom->page_size = 32; 532 eeprom->address_bits = 16; 533 eeprom->use_eerd = true; 534 eeprom->use_eewr = false; 535 break; 536 537 /* ich8lan does not support currently. if needed, please 538 * add corresponding code and functions. 539 */ 540 #if 0 541 case e1000_ich8lan: 542 { 543 int32_t i = 0; 544 545 eeprom->type = e1000_eeprom_ich8; 546 eeprom->use_eerd = false; 547 eeprom->use_eewr = false; 548 eeprom->word_size = E1000_SHADOW_RAM_WORDS; 549 uint32_t flash_size = E1000_READ_ICH_FLASH_REG(hw, 550 ICH_FLASH_GFPREG); 551 /* Zero the shadow RAM structure. But don't load it from NVM 552 * so as to save time for driver init */ 553 if (hw->eeprom_shadow_ram != NULL) { 554 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) { 555 hw->eeprom_shadow_ram[i].modified = false; 556 hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF; 557 } 558 } 559 560 hw->flash_base_addr = (flash_size & ICH_GFPREG_BASE_MASK) * 561 ICH_FLASH_SECTOR_SIZE; 562 563 hw->flash_bank_size = ((flash_size >> 16) 564 & ICH_GFPREG_BASE_MASK) + 1; 565 hw->flash_bank_size -= (flash_size & ICH_GFPREG_BASE_MASK); 566 567 hw->flash_bank_size *= ICH_FLASH_SECTOR_SIZE; 568 569 hw->flash_bank_size /= 2 * sizeof(uint16_t); 570 break; 571 } 572 #endif 573 default: 574 break; 575 } 576 577 if (eeprom->type == e1000_eeprom_spi || 578 eeprom->type == e1000_eeprom_invm) { 579 /* eeprom_size will be an enum [0..8] that maps 580 * to eeprom sizes 128B to 581 * 32KB (incremented by powers of 2). 582 */ 583 if (hw->mac_type <= e1000_82547_rev_2) { 584 /* Set to default value for initial eeprom read. */ 585 eeprom->word_size = 64; 586 ret_val = e1000_read_eeprom(hw, EEPROM_CFG, 1, 587 &eeprom_size); 588 if (ret_val) 589 return ret_val; 590 eeprom_size = (eeprom_size & EEPROM_SIZE_MASK) 591 >> EEPROM_SIZE_SHIFT; 592 /* 256B eeprom size was not supported in earlier 593 * hardware, so we bump eeprom_size up one to 594 * ensure that "1" (which maps to 256B) is never 595 * the result used in the shifting logic below. */ 596 if (eeprom_size) 597 eeprom_size++; 598 } else { 599 eeprom_size = (uint16_t)((eecd & 600 E1000_EECD_SIZE_EX_MASK) >> 601 E1000_EECD_SIZE_EX_SHIFT); 602 } 603 604 eeprom->word_size = 1 << (eeprom_size + EEPROM_WORD_SIZE_SHIFT); 605 } 606 return ret_val; 607 } 608 609 /****************************************************************************** 610 * Polls the status bit (bit 1) of the EERD to determine when the read is done. 611 * 612 * hw - Struct containing variables accessed by shared code 613 *****************************************************************************/ 614 static int32_t 615 e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd) 616 { 617 uint32_t attempts = 100000; 618 uint32_t i, reg = 0; 619 int32_t done = E1000_ERR_EEPROM; 620 621 for (i = 0; i < attempts; i++) { 622 if (eerd == E1000_EEPROM_POLL_READ) { 623 if (hw->mac_type == e1000_igb) 624 reg = E1000_READ_REG(hw, I210_EERD); 625 else 626 reg = E1000_READ_REG(hw, EERD); 627 } else { 628 if (hw->mac_type == e1000_igb) 629 reg = E1000_READ_REG(hw, I210_EEWR); 630 else 631 reg = E1000_READ_REG(hw, EEWR); 632 } 633 634 if (reg & E1000_EEPROM_RW_REG_DONE) { 635 done = E1000_SUCCESS; 636 break; 637 } 638 udelay(5); 639 } 640 641 return done; 642 } 643 644 /****************************************************************************** 645 * Reads a 16 bit word from the EEPROM using the EERD register. 646 * 647 * hw - Struct containing variables accessed by shared code 648 * offset - offset of word in the EEPROM to read 649 * data - word read from the EEPROM 650 * words - number of words to read 651 *****************************************************************************/ 652 static int32_t 653 e1000_read_eeprom_eerd(struct e1000_hw *hw, 654 uint16_t offset, 655 uint16_t words, 656 uint16_t *data) 657 { 658 uint32_t i, eerd = 0; 659 int32_t error = 0; 660 661 for (i = 0; i < words; i++) { 662 eerd = ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) + 663 E1000_EEPROM_RW_REG_START; 664 665 if (hw->mac_type == e1000_igb) 666 E1000_WRITE_REG(hw, I210_EERD, eerd); 667 else 668 E1000_WRITE_REG(hw, EERD, eerd); 669 670 error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_READ); 671 672 if (error) 673 break; 674 675 if (hw->mac_type == e1000_igb) { 676 data[i] = (E1000_READ_REG(hw, I210_EERD) >> 677 E1000_EEPROM_RW_REG_DATA); 678 } else { 679 data[i] = (E1000_READ_REG(hw, EERD) >> 680 E1000_EEPROM_RW_REG_DATA); 681 } 682 683 } 684 685 return error; 686 } 687 688 void e1000_release_eeprom(struct e1000_hw *hw) 689 { 690 uint32_t eecd; 691 692 DEBUGFUNC(); 693 694 eecd = E1000_READ_REG(hw, EECD); 695 696 if (hw->eeprom.type == e1000_eeprom_spi) { 697 eecd |= E1000_EECD_CS; /* Pull CS high */ 698 eecd &= ~E1000_EECD_SK; /* Lower SCK */ 699 700 E1000_WRITE_REG(hw, EECD, eecd); 701 702 udelay(hw->eeprom.delay_usec); 703 } else if (hw->eeprom.type == e1000_eeprom_microwire) { 704 /* cleanup eeprom */ 705 706 /* CS on Microwire is active-high */ 707 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI); 708 709 E1000_WRITE_REG(hw, EECD, eecd); 710 711 /* Rising edge of clock */ 712 eecd |= E1000_EECD_SK; 713 E1000_WRITE_REG(hw, EECD, eecd); 714 E1000_WRITE_FLUSH(hw); 715 udelay(hw->eeprom.delay_usec); 716 717 /* Falling edge of clock */ 718 eecd &= ~E1000_EECD_SK; 719 E1000_WRITE_REG(hw, EECD, eecd); 720 E1000_WRITE_FLUSH(hw); 721 udelay(hw->eeprom.delay_usec); 722 } 723 724 /* Stop requesting EEPROM access */ 725 if (hw->mac_type > e1000_82544) { 726 eecd &= ~E1000_EECD_REQ; 727 E1000_WRITE_REG(hw, EECD, eecd); 728 } 729 } 730 /****************************************************************************** 731 * Reads a 16 bit word from the EEPROM. 732 * 733 * hw - Struct containing variables accessed by shared code 734 *****************************************************************************/ 735 static int32_t 736 e1000_spi_eeprom_ready(struct e1000_hw *hw) 737 { 738 uint16_t retry_count = 0; 739 uint8_t spi_stat_reg; 740 741 DEBUGFUNC(); 742 743 /* Read "Status Register" repeatedly until the LSB is cleared. The 744 * EEPROM will signal that the command has been completed by clearing 745 * bit 0 of the internal status register. If it's not cleared within 746 * 5 milliseconds, then error out. 747 */ 748 retry_count = 0; 749 do { 750 e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI, 751 hw->eeprom.opcode_bits); 752 spi_stat_reg = (uint8_t)e1000_shift_in_ee_bits(hw, 8); 753 if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI)) 754 break; 755 756 udelay(5); 757 retry_count += 5; 758 759 e1000_standby_eeprom(hw); 760 } while (retry_count < EEPROM_MAX_RETRY_SPI); 761 762 /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and 763 * only 0-5mSec on 5V devices) 764 */ 765 if (retry_count >= EEPROM_MAX_RETRY_SPI) { 766 DEBUGOUT("SPI EEPROM Status error\n"); 767 return -E1000_ERR_EEPROM; 768 } 769 770 return E1000_SUCCESS; 771 } 772 773 /****************************************************************************** 774 * Reads a 16 bit word from the EEPROM. 775 * 776 * hw - Struct containing variables accessed by shared code 777 * offset - offset of word in the EEPROM to read 778 * data - word read from the EEPROM 779 *****************************************************************************/ 780 static int32_t 781 e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset, 782 uint16_t words, uint16_t *data) 783 { 784 struct e1000_eeprom_info *eeprom = &hw->eeprom; 785 uint32_t i = 0; 786 787 DEBUGFUNC(); 788 789 /* If eeprom is not yet detected, do so now */ 790 if (eeprom->word_size == 0) 791 e1000_init_eeprom_params(hw); 792 793 /* A check for invalid values: offset too large, too many words, 794 * and not enough words. 795 */ 796 if ((offset >= eeprom->word_size) || 797 (words > eeprom->word_size - offset) || 798 (words == 0)) { 799 DEBUGOUT("\"words\" parameter out of bounds." 800 "Words = %d, size = %d\n", offset, eeprom->word_size); 801 return -E1000_ERR_EEPROM; 802 } 803 804 /* EEPROM's that don't use EERD to read require us to bit-bang the SPI 805 * directly. In this case, we need to acquire the EEPROM so that 806 * FW or other port software does not interrupt. 807 */ 808 if (e1000_is_onboard_nvm_eeprom(hw) == true && 809 hw->eeprom.use_eerd == false) { 810 811 /* Prepare the EEPROM for bit-bang reading */ 812 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS) 813 return -E1000_ERR_EEPROM; 814 } 815 816 /* Eerd register EEPROM access requires no eeprom aquire/release */ 817 if (eeprom->use_eerd == true) 818 return e1000_read_eeprom_eerd(hw, offset, words, data); 819 820 /* ich8lan does not support currently. if needed, please 821 * add corresponding code and functions. 822 */ 823 #if 0 824 /* ICH EEPROM access is done via the ICH flash controller */ 825 if (eeprom->type == e1000_eeprom_ich8) 826 return e1000_read_eeprom_ich8(hw, offset, words, data); 827 #endif 828 /* Set up the SPI or Microwire EEPROM for bit-bang reading. We have 829 * acquired the EEPROM at this point, so any returns should relase it */ 830 if (eeprom->type == e1000_eeprom_spi) { 831 uint16_t word_in; 832 uint8_t read_opcode = EEPROM_READ_OPCODE_SPI; 833 834 if (e1000_spi_eeprom_ready(hw)) { 835 e1000_release_eeprom(hw); 836 return -E1000_ERR_EEPROM; 837 } 838 839 e1000_standby_eeprom(hw); 840 841 /* Some SPI eeproms use the 8th address bit embedded in 842 * the opcode */ 843 if ((eeprom->address_bits == 8) && (offset >= 128)) 844 read_opcode |= EEPROM_A8_OPCODE_SPI; 845 846 /* Send the READ command (opcode + addr) */ 847 e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits); 848 e1000_shift_out_ee_bits(hw, (uint16_t)(offset*2), 849 eeprom->address_bits); 850 851 /* Read the data. The address of the eeprom internally 852 * increments with each byte (spi) being read, saving on the 853 * overhead of eeprom setup and tear-down. The address 854 * counter will roll over if reading beyond the size of 855 * the eeprom, thus allowing the entire memory to be read 856 * starting from any offset. */ 857 for (i = 0; i < words; i++) { 858 word_in = e1000_shift_in_ee_bits(hw, 16); 859 data[i] = (word_in >> 8) | (word_in << 8); 860 } 861 } else if (eeprom->type == e1000_eeprom_microwire) { 862 for (i = 0; i < words; i++) { 863 /* Send the READ command (opcode + addr) */ 864 e1000_shift_out_ee_bits(hw, 865 EEPROM_READ_OPCODE_MICROWIRE, 866 eeprom->opcode_bits); 867 e1000_shift_out_ee_bits(hw, (uint16_t)(offset + i), 868 eeprom->address_bits); 869 870 /* Read the data. For microwire, each word requires 871 * the overhead of eeprom setup and tear-down. */ 872 data[i] = e1000_shift_in_ee_bits(hw, 16); 873 e1000_standby_eeprom(hw); 874 } 875 } 876 877 /* End this read operation */ 878 e1000_release_eeprom(hw); 879 880 return E1000_SUCCESS; 881 } 882 883 /****************************************************************************** 884 * Verifies that the EEPROM has a valid checksum 885 * 886 * hw - Struct containing variables accessed by shared code 887 * 888 * Reads the first 64 16 bit words of the EEPROM and sums the values read. 889 * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is 890 * valid. 891 *****************************************************************************/ 892 static int e1000_validate_eeprom_checksum(struct e1000_hw *hw) 893 { 894 uint16_t i, checksum, checksum_reg, *buf; 895 896 DEBUGFUNC(); 897 898 /* Allocate a temporary buffer */ 899 buf = malloc(sizeof(buf[0]) * (EEPROM_CHECKSUM_REG + 1)); 900 if (!buf) { 901 E1000_ERR(hw->nic, "Unable to allocate EEPROM buffer!\n"); 902 return -E1000_ERR_EEPROM; 903 } 904 905 /* Read the EEPROM */ 906 if (e1000_read_eeprom(hw, 0, EEPROM_CHECKSUM_REG + 1, buf) < 0) { 907 E1000_ERR(hw->nic, "Unable to read EEPROM!\n"); 908 return -E1000_ERR_EEPROM; 909 } 910 911 /* Compute the checksum */ 912 checksum = 0; 913 for (i = 0; i < EEPROM_CHECKSUM_REG; i++) 914 checksum += buf[i]; 915 checksum = ((uint16_t)EEPROM_SUM) - checksum; 916 checksum_reg = buf[i]; 917 918 /* Verify it! */ 919 if (checksum == checksum_reg) 920 return 0; 921 922 /* Hrm, verification failed, print an error */ 923 E1000_ERR(hw->nic, "EEPROM checksum is incorrect!\n"); 924 E1000_ERR(hw->nic, " ...register was 0x%04hx, calculated 0x%04hx\n", 925 checksum_reg, checksum); 926 927 return -E1000_ERR_EEPROM; 928 } 929 #endif /* CONFIG_E1000_NO_NVM */ 930 931 /***************************************************************************** 932 * Set PHY to class A mode 933 * Assumes the following operations will follow to enable the new class mode. 934 * 1. Do a PHY soft reset 935 * 2. Restart auto-negotiation or force link. 936 * 937 * hw - Struct containing variables accessed by shared code 938 ****************************************************************************/ 939 static int32_t 940 e1000_set_phy_mode(struct e1000_hw *hw) 941 { 942 #ifndef CONFIG_E1000_NO_NVM 943 int32_t ret_val; 944 uint16_t eeprom_data; 945 946 DEBUGFUNC(); 947 948 if ((hw->mac_type == e1000_82545_rev_3) && 949 (hw->media_type == e1000_media_type_copper)) { 950 ret_val = e1000_read_eeprom(hw, EEPROM_PHY_CLASS_WORD, 951 1, &eeprom_data); 952 if (ret_val) 953 return ret_val; 954 955 if ((eeprom_data != EEPROM_RESERVED_WORD) && 956 (eeprom_data & EEPROM_PHY_CLASS_A)) { 957 ret_val = e1000_write_phy_reg(hw, 958 M88E1000_PHY_PAGE_SELECT, 0x000B); 959 if (ret_val) 960 return ret_val; 961 ret_val = e1000_write_phy_reg(hw, 962 M88E1000_PHY_GEN_CONTROL, 0x8104); 963 if (ret_val) 964 return ret_val; 965 966 hw->phy_reset_disable = false; 967 } 968 } 969 #endif 970 return E1000_SUCCESS; 971 } 972 973 #ifndef CONFIG_E1000_NO_NVM 974 /*************************************************************************** 975 * 976 * Obtaining software semaphore bit (SMBI) before resetting PHY. 977 * 978 * hw: Struct containing variables accessed by shared code 979 * 980 * returns: - E1000_ERR_RESET if fail to obtain semaphore. 981 * E1000_SUCCESS at any other case. 982 * 983 ***************************************************************************/ 984 static int32_t 985 e1000_get_software_semaphore(struct e1000_hw *hw) 986 { 987 int32_t timeout = hw->eeprom.word_size + 1; 988 uint32_t swsm; 989 990 DEBUGFUNC(); 991 992 swsm = E1000_READ_REG(hw, SWSM); 993 swsm &= ~E1000_SWSM_SMBI; 994 E1000_WRITE_REG(hw, SWSM, swsm); 995 996 if (hw->mac_type != e1000_80003es2lan) 997 return E1000_SUCCESS; 998 999 while (timeout) { 1000 swsm = E1000_READ_REG(hw, SWSM); 1001 /* If SMBI bit cleared, it is now set and we hold 1002 * the semaphore */ 1003 if (!(swsm & E1000_SWSM_SMBI)) 1004 break; 1005 mdelay(1); 1006 timeout--; 1007 } 1008 1009 if (!timeout) { 1010 DEBUGOUT("Driver can't access device - SMBI bit is set.\n"); 1011 return -E1000_ERR_RESET; 1012 } 1013 1014 return E1000_SUCCESS; 1015 } 1016 #endif 1017 1018 /*************************************************************************** 1019 * This function clears HW semaphore bits. 1020 * 1021 * hw: Struct containing variables accessed by shared code 1022 * 1023 * returns: - None. 1024 * 1025 ***************************************************************************/ 1026 static void 1027 e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw) 1028 { 1029 #ifndef CONFIG_E1000_NO_NVM 1030 uint32_t swsm; 1031 1032 DEBUGFUNC(); 1033 1034 if (!hw->eeprom_semaphore_present) 1035 return; 1036 1037 swsm = E1000_READ_REG(hw, SWSM); 1038 if (hw->mac_type == e1000_80003es2lan) { 1039 /* Release both semaphores. */ 1040 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI); 1041 } else 1042 swsm &= ~(E1000_SWSM_SWESMBI); 1043 E1000_WRITE_REG(hw, SWSM, swsm); 1044 #endif 1045 } 1046 1047 /*************************************************************************** 1048 * 1049 * Using the combination of SMBI and SWESMBI semaphore bits when resetting 1050 * adapter or Eeprom access. 1051 * 1052 * hw: Struct containing variables accessed by shared code 1053 * 1054 * returns: - E1000_ERR_EEPROM if fail to access EEPROM. 1055 * E1000_SUCCESS at any other case. 1056 * 1057 ***************************************************************************/ 1058 static int32_t 1059 e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw) 1060 { 1061 #ifndef CONFIG_E1000_NO_NVM 1062 int32_t timeout; 1063 uint32_t swsm; 1064 1065 DEBUGFUNC(); 1066 1067 if (!hw->eeprom_semaphore_present) 1068 return E1000_SUCCESS; 1069 1070 if (hw->mac_type == e1000_80003es2lan) { 1071 /* Get the SW semaphore. */ 1072 if (e1000_get_software_semaphore(hw) != E1000_SUCCESS) 1073 return -E1000_ERR_EEPROM; 1074 } 1075 1076 /* Get the FW semaphore. */ 1077 timeout = hw->eeprom.word_size + 1; 1078 while (timeout) { 1079 swsm = E1000_READ_REG(hw, SWSM); 1080 swsm |= E1000_SWSM_SWESMBI; 1081 E1000_WRITE_REG(hw, SWSM, swsm); 1082 /* if we managed to set the bit we got the semaphore. */ 1083 swsm = E1000_READ_REG(hw, SWSM); 1084 if (swsm & E1000_SWSM_SWESMBI) 1085 break; 1086 1087 udelay(50); 1088 timeout--; 1089 } 1090 1091 if (!timeout) { 1092 /* Release semaphores */ 1093 e1000_put_hw_eeprom_semaphore(hw); 1094 DEBUGOUT("Driver can't access the Eeprom - " 1095 "SWESMBI bit is set.\n"); 1096 return -E1000_ERR_EEPROM; 1097 } 1098 #endif 1099 return E1000_SUCCESS; 1100 } 1101 1102 static int32_t 1103 e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask) 1104 { 1105 uint32_t swfw_sync = 0; 1106 uint32_t swmask = mask; 1107 uint32_t fwmask = mask << 16; 1108 int32_t timeout = 200; 1109 1110 DEBUGFUNC(); 1111 while (timeout) { 1112 if (e1000_get_hw_eeprom_semaphore(hw)) 1113 return -E1000_ERR_SWFW_SYNC; 1114 1115 swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC); 1116 if ((swfw_sync & swmask) && !(swfw_sync & fwmask)) 1117 break; 1118 1119 /* firmware currently using resource (fwmask) */ 1120 /* or other software thread currently using resource (swmask) */ 1121 e1000_put_hw_eeprom_semaphore(hw); 1122 mdelay(5); 1123 timeout--; 1124 } 1125 1126 if (!timeout) { 1127 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n"); 1128 return -E1000_ERR_SWFW_SYNC; 1129 } 1130 1131 swfw_sync |= swmask; 1132 E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync); 1133 1134 e1000_put_hw_eeprom_semaphore(hw); 1135 return E1000_SUCCESS; 1136 } 1137 1138 static bool e1000_is_second_port(struct e1000_hw *hw) 1139 { 1140 switch (hw->mac_type) { 1141 case e1000_80003es2lan: 1142 case e1000_82546: 1143 case e1000_82571: 1144 if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1) 1145 return true; 1146 /* Fallthrough */ 1147 default: 1148 return false; 1149 } 1150 } 1151 1152 #ifndef CONFIG_E1000_NO_NVM 1153 /****************************************************************************** 1154 * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the 1155 * second function of dual function devices 1156 * 1157 * nic - Struct containing variables accessed by shared code 1158 *****************************************************************************/ 1159 static int 1160 e1000_read_mac_addr(struct eth_device *nic) 1161 { 1162 struct e1000_hw *hw = nic->priv; 1163 uint16_t offset; 1164 uint16_t eeprom_data; 1165 uint32_t reg_data = 0; 1166 int i; 1167 1168 DEBUGFUNC(); 1169 1170 for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) { 1171 offset = i >> 1; 1172 if (hw->mac_type == e1000_igb) { 1173 /* i210 preloads MAC address into RAL/RAH registers */ 1174 if (offset == 0) 1175 reg_data = E1000_READ_REG_ARRAY(hw, RA, 0); 1176 else if (offset == 1) 1177 reg_data >>= 16; 1178 else if (offset == 2) 1179 reg_data = E1000_READ_REG_ARRAY(hw, RA, 1); 1180 eeprom_data = reg_data & 0xffff; 1181 } else if (e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) { 1182 DEBUGOUT("EEPROM Read Error\n"); 1183 return -E1000_ERR_EEPROM; 1184 } 1185 nic->enetaddr[i] = eeprom_data & 0xff; 1186 nic->enetaddr[i + 1] = (eeprom_data >> 8) & 0xff; 1187 } 1188 1189 /* Invert the last bit if this is the second device */ 1190 if (e1000_is_second_port(hw)) 1191 nic->enetaddr[5] ^= 1; 1192 1193 #ifdef CONFIG_E1000_FALLBACK_MAC 1194 if (!is_valid_ether_addr(nic->enetaddr)) { 1195 unsigned char fb_mac[NODE_ADDRESS_SIZE] = CONFIG_E1000_FALLBACK_MAC; 1196 1197 memcpy (nic->enetaddr, fb_mac, NODE_ADDRESS_SIZE); 1198 } 1199 #endif 1200 return 0; 1201 } 1202 #endif 1203 1204 /****************************************************************************** 1205 * Initializes receive address filters. 1206 * 1207 * hw - Struct containing variables accessed by shared code 1208 * 1209 * Places the MAC address in receive address register 0 and clears the rest 1210 * of the receive addresss registers. Clears the multicast table. Assumes 1211 * the receiver is in reset when the routine is called. 1212 *****************************************************************************/ 1213 static void 1214 e1000_init_rx_addrs(struct eth_device *nic) 1215 { 1216 struct e1000_hw *hw = nic->priv; 1217 uint32_t i; 1218 uint32_t addr_low; 1219 uint32_t addr_high; 1220 1221 DEBUGFUNC(); 1222 1223 /* Setup the receive address. */ 1224 DEBUGOUT("Programming MAC Address into RAR[0]\n"); 1225 addr_low = (nic->enetaddr[0] | 1226 (nic->enetaddr[1] << 8) | 1227 (nic->enetaddr[2] << 16) | (nic->enetaddr[3] << 24)); 1228 1229 addr_high = (nic->enetaddr[4] | (nic->enetaddr[5] << 8) | E1000_RAH_AV); 1230 1231 E1000_WRITE_REG_ARRAY(hw, RA, 0, addr_low); 1232 E1000_WRITE_REG_ARRAY(hw, RA, 1, addr_high); 1233 1234 /* Zero out the other 15 receive addresses. */ 1235 DEBUGOUT("Clearing RAR[1-15]\n"); 1236 for (i = 1; i < E1000_RAR_ENTRIES; i++) { 1237 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0); 1238 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0); 1239 } 1240 } 1241 1242 /****************************************************************************** 1243 * Clears the VLAN filer table 1244 * 1245 * hw - Struct containing variables accessed by shared code 1246 *****************************************************************************/ 1247 static void 1248 e1000_clear_vfta(struct e1000_hw *hw) 1249 { 1250 uint32_t offset; 1251 1252 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) 1253 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, 0); 1254 } 1255 1256 /****************************************************************************** 1257 * Set the mac type member in the hw struct. 1258 * 1259 * hw - Struct containing variables accessed by shared code 1260 *****************************************************************************/ 1261 int32_t 1262 e1000_set_mac_type(struct e1000_hw *hw) 1263 { 1264 DEBUGFUNC(); 1265 1266 switch (hw->device_id) { 1267 case E1000_DEV_ID_82542: 1268 switch (hw->revision_id) { 1269 case E1000_82542_2_0_REV_ID: 1270 hw->mac_type = e1000_82542_rev2_0; 1271 break; 1272 case E1000_82542_2_1_REV_ID: 1273 hw->mac_type = e1000_82542_rev2_1; 1274 break; 1275 default: 1276 /* Invalid 82542 revision ID */ 1277 return -E1000_ERR_MAC_TYPE; 1278 } 1279 break; 1280 case E1000_DEV_ID_82543GC_FIBER: 1281 case E1000_DEV_ID_82543GC_COPPER: 1282 hw->mac_type = e1000_82543; 1283 break; 1284 case E1000_DEV_ID_82544EI_COPPER: 1285 case E1000_DEV_ID_82544EI_FIBER: 1286 case E1000_DEV_ID_82544GC_COPPER: 1287 case E1000_DEV_ID_82544GC_LOM: 1288 hw->mac_type = e1000_82544; 1289 break; 1290 case E1000_DEV_ID_82540EM: 1291 case E1000_DEV_ID_82540EM_LOM: 1292 case E1000_DEV_ID_82540EP: 1293 case E1000_DEV_ID_82540EP_LOM: 1294 case E1000_DEV_ID_82540EP_LP: 1295 hw->mac_type = e1000_82540; 1296 break; 1297 case E1000_DEV_ID_82545EM_COPPER: 1298 case E1000_DEV_ID_82545EM_FIBER: 1299 hw->mac_type = e1000_82545; 1300 break; 1301 case E1000_DEV_ID_82545GM_COPPER: 1302 case E1000_DEV_ID_82545GM_FIBER: 1303 case E1000_DEV_ID_82545GM_SERDES: 1304 hw->mac_type = e1000_82545_rev_3; 1305 break; 1306 case E1000_DEV_ID_82546EB_COPPER: 1307 case E1000_DEV_ID_82546EB_FIBER: 1308 case E1000_DEV_ID_82546EB_QUAD_COPPER: 1309 hw->mac_type = e1000_82546; 1310 break; 1311 case E1000_DEV_ID_82546GB_COPPER: 1312 case E1000_DEV_ID_82546GB_FIBER: 1313 case E1000_DEV_ID_82546GB_SERDES: 1314 case E1000_DEV_ID_82546GB_PCIE: 1315 case E1000_DEV_ID_82546GB_QUAD_COPPER: 1316 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3: 1317 hw->mac_type = e1000_82546_rev_3; 1318 break; 1319 case E1000_DEV_ID_82541EI: 1320 case E1000_DEV_ID_82541EI_MOBILE: 1321 case E1000_DEV_ID_82541ER_LOM: 1322 hw->mac_type = e1000_82541; 1323 break; 1324 case E1000_DEV_ID_82541ER: 1325 case E1000_DEV_ID_82541GI: 1326 case E1000_DEV_ID_82541GI_LF: 1327 case E1000_DEV_ID_82541GI_MOBILE: 1328 hw->mac_type = e1000_82541_rev_2; 1329 break; 1330 case E1000_DEV_ID_82547EI: 1331 case E1000_DEV_ID_82547EI_MOBILE: 1332 hw->mac_type = e1000_82547; 1333 break; 1334 case E1000_DEV_ID_82547GI: 1335 hw->mac_type = e1000_82547_rev_2; 1336 break; 1337 case E1000_DEV_ID_82571EB_COPPER: 1338 case E1000_DEV_ID_82571EB_FIBER: 1339 case E1000_DEV_ID_82571EB_SERDES: 1340 case E1000_DEV_ID_82571EB_SERDES_DUAL: 1341 case E1000_DEV_ID_82571EB_SERDES_QUAD: 1342 case E1000_DEV_ID_82571EB_QUAD_COPPER: 1343 case E1000_DEV_ID_82571PT_QUAD_COPPER: 1344 case E1000_DEV_ID_82571EB_QUAD_FIBER: 1345 case E1000_DEV_ID_82571EB_QUAD_COPPER_LOWPROFILE: 1346 hw->mac_type = e1000_82571; 1347 break; 1348 case E1000_DEV_ID_82572EI_COPPER: 1349 case E1000_DEV_ID_82572EI_FIBER: 1350 case E1000_DEV_ID_82572EI_SERDES: 1351 case E1000_DEV_ID_82572EI: 1352 hw->mac_type = e1000_82572; 1353 break; 1354 case E1000_DEV_ID_82573E: 1355 case E1000_DEV_ID_82573E_IAMT: 1356 case E1000_DEV_ID_82573L: 1357 hw->mac_type = e1000_82573; 1358 break; 1359 case E1000_DEV_ID_82574L: 1360 hw->mac_type = e1000_82574; 1361 break; 1362 case E1000_DEV_ID_80003ES2LAN_COPPER_SPT: 1363 case E1000_DEV_ID_80003ES2LAN_SERDES_SPT: 1364 case E1000_DEV_ID_80003ES2LAN_COPPER_DPT: 1365 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT: 1366 hw->mac_type = e1000_80003es2lan; 1367 break; 1368 case E1000_DEV_ID_ICH8_IGP_M_AMT: 1369 case E1000_DEV_ID_ICH8_IGP_AMT: 1370 case E1000_DEV_ID_ICH8_IGP_C: 1371 case E1000_DEV_ID_ICH8_IFE: 1372 case E1000_DEV_ID_ICH8_IFE_GT: 1373 case E1000_DEV_ID_ICH8_IFE_G: 1374 case E1000_DEV_ID_ICH8_IGP_M: 1375 hw->mac_type = e1000_ich8lan; 1376 break; 1377 case PCI_DEVICE_ID_INTEL_I210_COPPER: 1378 case PCI_DEVICE_ID_INTEL_I210_COPPER_FLASHLESS: 1379 case PCI_DEVICE_ID_INTEL_I210_SERDES: 1380 case PCI_DEVICE_ID_INTEL_I210_SERDES_FLASHLESS: 1381 case PCI_DEVICE_ID_INTEL_I210_1000BASEKX: 1382 hw->mac_type = e1000_igb; 1383 break; 1384 default: 1385 /* Should never have loaded on this device */ 1386 return -E1000_ERR_MAC_TYPE; 1387 } 1388 return E1000_SUCCESS; 1389 } 1390 1391 /****************************************************************************** 1392 * Reset the transmit and receive units; mask and clear all interrupts. 1393 * 1394 * hw - Struct containing variables accessed by shared code 1395 *****************************************************************************/ 1396 void 1397 e1000_reset_hw(struct e1000_hw *hw) 1398 { 1399 uint32_t ctrl; 1400 uint32_t ctrl_ext; 1401 uint32_t manc; 1402 uint32_t pba = 0; 1403 uint32_t reg; 1404 1405 DEBUGFUNC(); 1406 1407 /* get the correct pba value for both PCI and PCIe*/ 1408 if (hw->mac_type < e1000_82571) 1409 pba = E1000_DEFAULT_PCI_PBA; 1410 else 1411 pba = E1000_DEFAULT_PCIE_PBA; 1412 1413 /* For 82542 (rev 2.0), disable MWI before issuing a device reset */ 1414 if (hw->mac_type == e1000_82542_rev2_0) { 1415 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n"); 1416 pci_write_config_word(hw->pdev, PCI_COMMAND, 1417 hw->pci_cmd_word & ~PCI_COMMAND_INVALIDATE); 1418 } 1419 1420 /* Clear interrupt mask to stop board from generating interrupts */ 1421 DEBUGOUT("Masking off all interrupts\n"); 1422 if (hw->mac_type == e1000_igb) 1423 E1000_WRITE_REG(hw, I210_IAM, 0); 1424 E1000_WRITE_REG(hw, IMC, 0xffffffff); 1425 1426 /* Disable the Transmit and Receive units. Then delay to allow 1427 * any pending transactions to complete before we hit the MAC with 1428 * the global reset. 1429 */ 1430 E1000_WRITE_REG(hw, RCTL, 0); 1431 E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP); 1432 E1000_WRITE_FLUSH(hw); 1433 1434 /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */ 1435 hw->tbi_compatibility_on = false; 1436 1437 /* Delay to allow any outstanding PCI transactions to complete before 1438 * resetting the device 1439 */ 1440 mdelay(10); 1441 1442 /* Issue a global reset to the MAC. This will reset the chip's 1443 * transmit, receive, DMA, and link units. It will not effect 1444 * the current PCI configuration. The global reset bit is self- 1445 * clearing, and should clear within a microsecond. 1446 */ 1447 DEBUGOUT("Issuing a global reset to MAC\n"); 1448 ctrl = E1000_READ_REG(hw, CTRL); 1449 1450 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST)); 1451 1452 /* Force a reload from the EEPROM if necessary */ 1453 if (hw->mac_type == e1000_igb) { 1454 mdelay(20); 1455 reg = E1000_READ_REG(hw, STATUS); 1456 if (reg & E1000_STATUS_PF_RST_DONE) 1457 DEBUGOUT("PF OK\n"); 1458 reg = E1000_READ_REG(hw, I210_EECD); 1459 if (reg & E1000_EECD_AUTO_RD) 1460 DEBUGOUT("EEC OK\n"); 1461 } else if (hw->mac_type < e1000_82540) { 1462 /* Wait for reset to complete */ 1463 udelay(10); 1464 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 1465 ctrl_ext |= E1000_CTRL_EXT_EE_RST; 1466 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 1467 E1000_WRITE_FLUSH(hw); 1468 /* Wait for EEPROM reload */ 1469 mdelay(2); 1470 } else { 1471 /* Wait for EEPROM reload (it happens automatically) */ 1472 mdelay(4); 1473 /* Dissable HW ARPs on ASF enabled adapters */ 1474 manc = E1000_READ_REG(hw, MANC); 1475 manc &= ~(E1000_MANC_ARP_EN); 1476 E1000_WRITE_REG(hw, MANC, manc); 1477 } 1478 1479 /* Clear interrupt mask to stop board from generating interrupts */ 1480 DEBUGOUT("Masking off all interrupts\n"); 1481 if (hw->mac_type == e1000_igb) 1482 E1000_WRITE_REG(hw, I210_IAM, 0); 1483 E1000_WRITE_REG(hw, IMC, 0xffffffff); 1484 1485 /* Clear any pending interrupt events. */ 1486 E1000_READ_REG(hw, ICR); 1487 1488 /* If MWI was previously enabled, reenable it. */ 1489 if (hw->mac_type == e1000_82542_rev2_0) { 1490 pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word); 1491 } 1492 if (hw->mac_type != e1000_igb) 1493 E1000_WRITE_REG(hw, PBA, pba); 1494 } 1495 1496 /****************************************************************************** 1497 * 1498 * Initialize a number of hardware-dependent bits 1499 * 1500 * hw: Struct containing variables accessed by shared code 1501 * 1502 * This function contains hardware limitation workarounds for PCI-E adapters 1503 * 1504 *****************************************************************************/ 1505 static void 1506 e1000_initialize_hardware_bits(struct e1000_hw *hw) 1507 { 1508 if ((hw->mac_type >= e1000_82571) && 1509 (!hw->initialize_hw_bits_disable)) { 1510 /* Settings common to all PCI-express silicon */ 1511 uint32_t reg_ctrl, reg_ctrl_ext; 1512 uint32_t reg_tarc0, reg_tarc1; 1513 uint32_t reg_tctl; 1514 uint32_t reg_txdctl, reg_txdctl1; 1515 1516 /* link autonegotiation/sync workarounds */ 1517 reg_tarc0 = E1000_READ_REG(hw, TARC0); 1518 reg_tarc0 &= ~((1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)); 1519 1520 /* Enable not-done TX descriptor counting */ 1521 reg_txdctl = E1000_READ_REG(hw, TXDCTL); 1522 reg_txdctl |= E1000_TXDCTL_COUNT_DESC; 1523 E1000_WRITE_REG(hw, TXDCTL, reg_txdctl); 1524 1525 reg_txdctl1 = E1000_READ_REG(hw, TXDCTL1); 1526 reg_txdctl1 |= E1000_TXDCTL_COUNT_DESC; 1527 E1000_WRITE_REG(hw, TXDCTL1, reg_txdctl1); 1528 1529 /* IGB is cool */ 1530 if (hw->mac_type == e1000_igb) 1531 return; 1532 1533 switch (hw->mac_type) { 1534 case e1000_82571: 1535 case e1000_82572: 1536 /* Clear PHY TX compatible mode bits */ 1537 reg_tarc1 = E1000_READ_REG(hw, TARC1); 1538 reg_tarc1 &= ~((1 << 30)|(1 << 29)); 1539 1540 /* link autonegotiation/sync workarounds */ 1541 reg_tarc0 |= ((1 << 26)|(1 << 25)|(1 << 24)|(1 << 23)); 1542 1543 /* TX ring control fixes */ 1544 reg_tarc1 |= ((1 << 26)|(1 << 25)|(1 << 24)); 1545 1546 /* Multiple read bit is reversed polarity */ 1547 reg_tctl = E1000_READ_REG(hw, TCTL); 1548 if (reg_tctl & E1000_TCTL_MULR) 1549 reg_tarc1 &= ~(1 << 28); 1550 else 1551 reg_tarc1 |= (1 << 28); 1552 1553 E1000_WRITE_REG(hw, TARC1, reg_tarc1); 1554 break; 1555 case e1000_82573: 1556 case e1000_82574: 1557 reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 1558 reg_ctrl_ext &= ~(1 << 23); 1559 reg_ctrl_ext |= (1 << 22); 1560 1561 /* TX byte count fix */ 1562 reg_ctrl = E1000_READ_REG(hw, CTRL); 1563 reg_ctrl &= ~(1 << 29); 1564 1565 E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext); 1566 E1000_WRITE_REG(hw, CTRL, reg_ctrl); 1567 break; 1568 case e1000_80003es2lan: 1569 /* improve small packet performace for fiber/serdes */ 1570 if ((hw->media_type == e1000_media_type_fiber) 1571 || (hw->media_type == 1572 e1000_media_type_internal_serdes)) { 1573 reg_tarc0 &= ~(1 << 20); 1574 } 1575 1576 /* Multiple read bit is reversed polarity */ 1577 reg_tctl = E1000_READ_REG(hw, TCTL); 1578 reg_tarc1 = E1000_READ_REG(hw, TARC1); 1579 if (reg_tctl & E1000_TCTL_MULR) 1580 reg_tarc1 &= ~(1 << 28); 1581 else 1582 reg_tarc1 |= (1 << 28); 1583 1584 E1000_WRITE_REG(hw, TARC1, reg_tarc1); 1585 break; 1586 case e1000_ich8lan: 1587 /* Reduce concurrent DMA requests to 3 from 4 */ 1588 if ((hw->revision_id < 3) || 1589 ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) && 1590 (hw->device_id != E1000_DEV_ID_ICH8_IGP_M))) 1591 reg_tarc0 |= ((1 << 29)|(1 << 28)); 1592 1593 reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 1594 reg_ctrl_ext |= (1 << 22); 1595 E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext); 1596 1597 /* workaround TX hang with TSO=on */ 1598 reg_tarc0 |= ((1 << 27)|(1 << 26)|(1 << 24)|(1 << 23)); 1599 1600 /* Multiple read bit is reversed polarity */ 1601 reg_tctl = E1000_READ_REG(hw, TCTL); 1602 reg_tarc1 = E1000_READ_REG(hw, TARC1); 1603 if (reg_tctl & E1000_TCTL_MULR) 1604 reg_tarc1 &= ~(1 << 28); 1605 else 1606 reg_tarc1 |= (1 << 28); 1607 1608 /* workaround TX hang with TSO=on */ 1609 reg_tarc1 |= ((1 << 30)|(1 << 26)|(1 << 24)); 1610 1611 E1000_WRITE_REG(hw, TARC1, reg_tarc1); 1612 break; 1613 default: 1614 break; 1615 } 1616 1617 E1000_WRITE_REG(hw, TARC0, reg_tarc0); 1618 } 1619 } 1620 1621 /****************************************************************************** 1622 * Performs basic configuration of the adapter. 1623 * 1624 * hw - Struct containing variables accessed by shared code 1625 * 1626 * Assumes that the controller has previously been reset and is in a 1627 * post-reset uninitialized state. Initializes the receive address registers, 1628 * multicast table, and VLAN filter table. Calls routines to setup link 1629 * configuration and flow control settings. Clears all on-chip counters. Leaves 1630 * the transmit and receive units disabled and uninitialized. 1631 *****************************************************************************/ 1632 static int 1633 e1000_init_hw(struct eth_device *nic) 1634 { 1635 struct e1000_hw *hw = nic->priv; 1636 uint32_t ctrl; 1637 uint32_t i; 1638 int32_t ret_val; 1639 uint16_t pcix_cmd_word; 1640 uint16_t pcix_stat_hi_word; 1641 uint16_t cmd_mmrbc; 1642 uint16_t stat_mmrbc; 1643 uint32_t mta_size; 1644 uint32_t reg_data; 1645 uint32_t ctrl_ext; 1646 DEBUGFUNC(); 1647 /* force full DMA clock frequency for 10/100 on ICH8 A0-B0 */ 1648 if ((hw->mac_type == e1000_ich8lan) && 1649 ((hw->revision_id < 3) || 1650 ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) && 1651 (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))) { 1652 reg_data = E1000_READ_REG(hw, STATUS); 1653 reg_data &= ~0x80000000; 1654 E1000_WRITE_REG(hw, STATUS, reg_data); 1655 } 1656 /* Do not need initialize Identification LED */ 1657 1658 /* Set the media type and TBI compatibility */ 1659 e1000_set_media_type(hw); 1660 1661 /* Must be called after e1000_set_media_type 1662 * because media_type is used */ 1663 e1000_initialize_hardware_bits(hw); 1664 1665 /* Disabling VLAN filtering. */ 1666 DEBUGOUT("Initializing the IEEE VLAN\n"); 1667 /* VET hardcoded to standard value and VFTA removed in ICH8 LAN */ 1668 if (hw->mac_type != e1000_ich8lan) { 1669 if (hw->mac_type < e1000_82545_rev_3) 1670 E1000_WRITE_REG(hw, VET, 0); 1671 e1000_clear_vfta(hw); 1672 } 1673 1674 /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */ 1675 if (hw->mac_type == e1000_82542_rev2_0) { 1676 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n"); 1677 pci_write_config_word(hw->pdev, PCI_COMMAND, 1678 hw-> 1679 pci_cmd_word & ~PCI_COMMAND_INVALIDATE); 1680 E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST); 1681 E1000_WRITE_FLUSH(hw); 1682 mdelay(5); 1683 } 1684 1685 /* Setup the receive address. This involves initializing all of the Receive 1686 * Address Registers (RARs 0 - 15). 1687 */ 1688 e1000_init_rx_addrs(nic); 1689 1690 /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */ 1691 if (hw->mac_type == e1000_82542_rev2_0) { 1692 E1000_WRITE_REG(hw, RCTL, 0); 1693 E1000_WRITE_FLUSH(hw); 1694 mdelay(1); 1695 pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word); 1696 } 1697 1698 /* Zero out the Multicast HASH table */ 1699 DEBUGOUT("Zeroing the MTA\n"); 1700 mta_size = E1000_MC_TBL_SIZE; 1701 if (hw->mac_type == e1000_ich8lan) 1702 mta_size = E1000_MC_TBL_SIZE_ICH8LAN; 1703 for (i = 0; i < mta_size; i++) { 1704 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0); 1705 /* use write flush to prevent Memory Write Block (MWB) from 1706 * occuring when accessing our register space */ 1707 E1000_WRITE_FLUSH(hw); 1708 } 1709 #if 0 1710 /* Set the PCI priority bit correctly in the CTRL register. This 1711 * determines if the adapter gives priority to receives, or if it 1712 * gives equal priority to transmits and receives. Valid only on 1713 * 82542 and 82543 silicon. 1714 */ 1715 if (hw->dma_fairness && hw->mac_type <= e1000_82543) { 1716 ctrl = E1000_READ_REG(hw, CTRL); 1717 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR); 1718 } 1719 #endif 1720 switch (hw->mac_type) { 1721 case e1000_82545_rev_3: 1722 case e1000_82546_rev_3: 1723 case e1000_igb: 1724 break; 1725 default: 1726 /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */ 1727 if (hw->bus_type == e1000_bus_type_pcix) { 1728 pci_read_config_word(hw->pdev, PCIX_COMMAND_REGISTER, 1729 &pcix_cmd_word); 1730 pci_read_config_word(hw->pdev, PCIX_STATUS_REGISTER_HI, 1731 &pcix_stat_hi_word); 1732 cmd_mmrbc = 1733 (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) >> 1734 PCIX_COMMAND_MMRBC_SHIFT; 1735 stat_mmrbc = 1736 (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >> 1737 PCIX_STATUS_HI_MMRBC_SHIFT; 1738 if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K) 1739 stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K; 1740 if (cmd_mmrbc > stat_mmrbc) { 1741 pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK; 1742 pcix_cmd_word |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT; 1743 pci_write_config_word(hw->pdev, PCIX_COMMAND_REGISTER, 1744 pcix_cmd_word); 1745 } 1746 } 1747 break; 1748 } 1749 1750 /* More time needed for PHY to initialize */ 1751 if (hw->mac_type == e1000_ich8lan) 1752 mdelay(15); 1753 if (hw->mac_type == e1000_igb) 1754 mdelay(15); 1755 1756 /* Call a subroutine to configure the link and setup flow control. */ 1757 ret_val = e1000_setup_link(nic); 1758 1759 /* Set the transmit descriptor write-back policy */ 1760 if (hw->mac_type > e1000_82544) { 1761 ctrl = E1000_READ_REG(hw, TXDCTL); 1762 ctrl = 1763 (ctrl & ~E1000_TXDCTL_WTHRESH) | 1764 E1000_TXDCTL_FULL_TX_DESC_WB; 1765 E1000_WRITE_REG(hw, TXDCTL, ctrl); 1766 } 1767 1768 /* Set the receive descriptor write back policy */ 1769 if (hw->mac_type >= e1000_82571) { 1770 ctrl = E1000_READ_REG(hw, RXDCTL); 1771 ctrl = 1772 (ctrl & ~E1000_RXDCTL_WTHRESH) | 1773 E1000_RXDCTL_FULL_RX_DESC_WB; 1774 E1000_WRITE_REG(hw, RXDCTL, ctrl); 1775 } 1776 1777 switch (hw->mac_type) { 1778 default: 1779 break; 1780 case e1000_80003es2lan: 1781 /* Enable retransmit on late collisions */ 1782 reg_data = E1000_READ_REG(hw, TCTL); 1783 reg_data |= E1000_TCTL_RTLC; 1784 E1000_WRITE_REG(hw, TCTL, reg_data); 1785 1786 /* Configure Gigabit Carry Extend Padding */ 1787 reg_data = E1000_READ_REG(hw, TCTL_EXT); 1788 reg_data &= ~E1000_TCTL_EXT_GCEX_MASK; 1789 reg_data |= DEFAULT_80003ES2LAN_TCTL_EXT_GCEX; 1790 E1000_WRITE_REG(hw, TCTL_EXT, reg_data); 1791 1792 /* Configure Transmit Inter-Packet Gap */ 1793 reg_data = E1000_READ_REG(hw, TIPG); 1794 reg_data &= ~E1000_TIPG_IPGT_MASK; 1795 reg_data |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000; 1796 E1000_WRITE_REG(hw, TIPG, reg_data); 1797 1798 reg_data = E1000_READ_REG_ARRAY(hw, FFLT, 0x0001); 1799 reg_data &= ~0x00100000; 1800 E1000_WRITE_REG_ARRAY(hw, FFLT, 0x0001, reg_data); 1801 /* Fall through */ 1802 case e1000_82571: 1803 case e1000_82572: 1804 case e1000_ich8lan: 1805 ctrl = E1000_READ_REG(hw, TXDCTL1); 1806 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) 1807 | E1000_TXDCTL_FULL_TX_DESC_WB; 1808 E1000_WRITE_REG(hw, TXDCTL1, ctrl); 1809 break; 1810 case e1000_82573: 1811 case e1000_82574: 1812 reg_data = E1000_READ_REG(hw, GCR); 1813 reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX; 1814 E1000_WRITE_REG(hw, GCR, reg_data); 1815 case e1000_igb: 1816 break; 1817 } 1818 1819 #if 0 1820 /* Clear all of the statistics registers (clear on read). It is 1821 * important that we do this after we have tried to establish link 1822 * because the symbol error count will increment wildly if there 1823 * is no link. 1824 */ 1825 e1000_clear_hw_cntrs(hw); 1826 1827 /* ICH8 No-snoop bits are opposite polarity. 1828 * Set to snoop by default after reset. */ 1829 if (hw->mac_type == e1000_ich8lan) 1830 e1000_set_pci_ex_no_snoop(hw, PCI_EX_82566_SNOOP_ALL); 1831 #endif 1832 1833 if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER || 1834 hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) { 1835 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 1836 /* Relaxed ordering must be disabled to avoid a parity 1837 * error crash in a PCI slot. */ 1838 ctrl_ext |= E1000_CTRL_EXT_RO_DIS; 1839 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 1840 } 1841 1842 return ret_val; 1843 } 1844 1845 /****************************************************************************** 1846 * Configures flow control and link settings. 1847 * 1848 * hw - Struct containing variables accessed by shared code 1849 * 1850 * Determines which flow control settings to use. Calls the apropriate media- 1851 * specific link configuration function. Configures the flow control settings. 1852 * Assuming the adapter has a valid link partner, a valid link should be 1853 * established. Assumes the hardware has previously been reset and the 1854 * transmitter and receiver are not enabled. 1855 *****************************************************************************/ 1856 static int 1857 e1000_setup_link(struct eth_device *nic) 1858 { 1859 struct e1000_hw *hw = nic->priv; 1860 int32_t ret_val; 1861 #ifndef CONFIG_E1000_NO_NVM 1862 uint32_t ctrl_ext; 1863 uint16_t eeprom_data; 1864 #endif 1865 1866 DEBUGFUNC(); 1867 1868 /* In the case of the phy reset being blocked, we already have a link. 1869 * We do not have to set it up again. */ 1870 if (e1000_check_phy_reset_block(hw)) 1871 return E1000_SUCCESS; 1872 1873 #ifndef CONFIG_E1000_NO_NVM 1874 /* Read and store word 0x0F of the EEPROM. This word contains bits 1875 * that determine the hardware's default PAUSE (flow control) mode, 1876 * a bit that determines whether the HW defaults to enabling or 1877 * disabling auto-negotiation, and the direction of the 1878 * SW defined pins. If there is no SW over-ride of the flow 1879 * control setting, then the variable hw->fc will 1880 * be initialized based on a value in the EEPROM. 1881 */ 1882 if (e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, 1, 1883 &eeprom_data) < 0) { 1884 DEBUGOUT("EEPROM Read Error\n"); 1885 return -E1000_ERR_EEPROM; 1886 } 1887 #endif 1888 if (hw->fc == e1000_fc_default) { 1889 switch (hw->mac_type) { 1890 case e1000_ich8lan: 1891 case e1000_82573: 1892 case e1000_82574: 1893 case e1000_igb: 1894 hw->fc = e1000_fc_full; 1895 break; 1896 default: 1897 #ifndef CONFIG_E1000_NO_NVM 1898 ret_val = e1000_read_eeprom(hw, 1899 EEPROM_INIT_CONTROL2_REG, 1, &eeprom_data); 1900 if (ret_val) { 1901 DEBUGOUT("EEPROM Read Error\n"); 1902 return -E1000_ERR_EEPROM; 1903 } 1904 if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0) 1905 hw->fc = e1000_fc_none; 1906 else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 1907 EEPROM_WORD0F_ASM_DIR) 1908 hw->fc = e1000_fc_tx_pause; 1909 else 1910 #endif 1911 hw->fc = e1000_fc_full; 1912 break; 1913 } 1914 } 1915 1916 /* We want to save off the original Flow Control configuration just 1917 * in case we get disconnected and then reconnected into a different 1918 * hub or switch with different Flow Control capabilities. 1919 */ 1920 if (hw->mac_type == e1000_82542_rev2_0) 1921 hw->fc &= (~e1000_fc_tx_pause); 1922 1923 if ((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1)) 1924 hw->fc &= (~e1000_fc_rx_pause); 1925 1926 hw->original_fc = hw->fc; 1927 1928 DEBUGOUT("After fix-ups FlowControl is now = %x\n", hw->fc); 1929 1930 #ifndef CONFIG_E1000_NO_NVM 1931 /* Take the 4 bits from EEPROM word 0x0F that determine the initial 1932 * polarity value for the SW controlled pins, and setup the 1933 * Extended Device Control reg with that info. 1934 * This is needed because one of the SW controlled pins is used for 1935 * signal detection. So this should be done before e1000_setup_pcs_link() 1936 * or e1000_phy_setup() is called. 1937 */ 1938 if (hw->mac_type == e1000_82543) { 1939 ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) << 1940 SWDPIO__EXT_SHIFT); 1941 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 1942 } 1943 #endif 1944 1945 /* Call the necessary subroutine to configure the link. */ 1946 ret_val = (hw->media_type == e1000_media_type_fiber) ? 1947 e1000_setup_fiber_link(nic) : e1000_setup_copper_link(nic); 1948 if (ret_val < 0) { 1949 return ret_val; 1950 } 1951 1952 /* Initialize the flow control address, type, and PAUSE timer 1953 * registers to their default values. This is done even if flow 1954 * control is disabled, because it does not hurt anything to 1955 * initialize these registers. 1956 */ 1957 DEBUGOUT("Initializing the Flow Control address, type" 1958 "and timer regs\n"); 1959 1960 /* FCAL/H and FCT are hardcoded to standard values in e1000_ich8lan. */ 1961 if (hw->mac_type != e1000_ich8lan) { 1962 E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE); 1963 E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH); 1964 E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW); 1965 } 1966 1967 E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time); 1968 1969 /* Set the flow control receive threshold registers. Normally, 1970 * these registers will be set to a default threshold that may be 1971 * adjusted later by the driver's runtime code. However, if the 1972 * ability to transmit pause frames in not enabled, then these 1973 * registers will be set to 0. 1974 */ 1975 if (!(hw->fc & e1000_fc_tx_pause)) { 1976 E1000_WRITE_REG(hw, FCRTL, 0); 1977 E1000_WRITE_REG(hw, FCRTH, 0); 1978 } else { 1979 /* We need to set up the Receive Threshold high and low water marks 1980 * as well as (optionally) enabling the transmission of XON frames. 1981 */ 1982 if (hw->fc_send_xon) { 1983 E1000_WRITE_REG(hw, FCRTL, 1984 (hw->fc_low_water | E1000_FCRTL_XONE)); 1985 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water); 1986 } else { 1987 E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water); 1988 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water); 1989 } 1990 } 1991 return ret_val; 1992 } 1993 1994 /****************************************************************************** 1995 * Sets up link for a fiber based adapter 1996 * 1997 * hw - Struct containing variables accessed by shared code 1998 * 1999 * Manipulates Physical Coding Sublayer functions in order to configure 2000 * link. Assumes the hardware has been previously reset and the transmitter 2001 * and receiver are not enabled. 2002 *****************************************************************************/ 2003 static int 2004 e1000_setup_fiber_link(struct eth_device *nic) 2005 { 2006 struct e1000_hw *hw = nic->priv; 2007 uint32_t ctrl; 2008 uint32_t status; 2009 uint32_t txcw = 0; 2010 uint32_t i; 2011 uint32_t signal; 2012 int32_t ret_val; 2013 2014 DEBUGFUNC(); 2015 /* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be 2016 * set when the optics detect a signal. On older adapters, it will be 2017 * cleared when there is a signal 2018 */ 2019 ctrl = E1000_READ_REG(hw, CTRL); 2020 if ((hw->mac_type > e1000_82544) && !(ctrl & E1000_CTRL_ILOS)) 2021 signal = E1000_CTRL_SWDPIN1; 2022 else 2023 signal = 0; 2024 2025 printf("signal for %s is %x (ctrl %08x)!!!!\n", nic->name, signal, 2026 ctrl); 2027 /* Take the link out of reset */ 2028 ctrl &= ~(E1000_CTRL_LRST); 2029 2030 e1000_config_collision_dist(hw); 2031 2032 /* Check for a software override of the flow control settings, and setup 2033 * the device accordingly. If auto-negotiation is enabled, then software 2034 * will have to set the "PAUSE" bits to the correct value in the Tranmsit 2035 * Config Word Register (TXCW) and re-start auto-negotiation. However, if 2036 * auto-negotiation is disabled, then software will have to manually 2037 * configure the two flow control enable bits in the CTRL register. 2038 * 2039 * The possible values of the "fc" parameter are: 2040 * 0: Flow control is completely disabled 2041 * 1: Rx flow control is enabled (we can receive pause frames, but 2042 * not send pause frames). 2043 * 2: Tx flow control is enabled (we can send pause frames but we do 2044 * not support receiving pause frames). 2045 * 3: Both Rx and TX flow control (symmetric) are enabled. 2046 */ 2047 switch (hw->fc) { 2048 case e1000_fc_none: 2049 /* Flow control is completely disabled by a software over-ride. */ 2050 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD); 2051 break; 2052 case e1000_fc_rx_pause: 2053 /* RX Flow control is enabled and TX Flow control is disabled by a 2054 * software over-ride. Since there really isn't a way to advertise 2055 * that we are capable of RX Pause ONLY, we will advertise that we 2056 * support both symmetric and asymmetric RX PAUSE. Later, we will 2057 * disable the adapter's ability to send PAUSE frames. 2058 */ 2059 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); 2060 break; 2061 case e1000_fc_tx_pause: 2062 /* TX Flow control is enabled, and RX Flow control is disabled, by a 2063 * software over-ride. 2064 */ 2065 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR); 2066 break; 2067 case e1000_fc_full: 2068 /* Flow control (both RX and TX) is enabled by a software over-ride. */ 2069 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); 2070 break; 2071 default: 2072 DEBUGOUT("Flow control param set incorrectly\n"); 2073 return -E1000_ERR_CONFIG; 2074 break; 2075 } 2076 2077 /* Since auto-negotiation is enabled, take the link out of reset (the link 2078 * will be in reset, because we previously reset the chip). This will 2079 * restart auto-negotiation. If auto-neogtiation is successful then the 2080 * link-up status bit will be set and the flow control enable bits (RFCE 2081 * and TFCE) will be set according to their negotiated value. 2082 */ 2083 DEBUGOUT("Auto-negotiation enabled (%#x)\n", txcw); 2084 2085 E1000_WRITE_REG(hw, TXCW, txcw); 2086 E1000_WRITE_REG(hw, CTRL, ctrl); 2087 E1000_WRITE_FLUSH(hw); 2088 2089 hw->txcw = txcw; 2090 mdelay(1); 2091 2092 /* If we have a signal (the cable is plugged in) then poll for a "Link-Up" 2093 * indication in the Device Status Register. Time-out if a link isn't 2094 * seen in 500 milliseconds seconds (Auto-negotiation should complete in 2095 * less than 500 milliseconds even if the other end is doing it in SW). 2096 */ 2097 if ((E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) { 2098 DEBUGOUT("Looking for Link\n"); 2099 for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) { 2100 mdelay(10); 2101 status = E1000_READ_REG(hw, STATUS); 2102 if (status & E1000_STATUS_LU) 2103 break; 2104 } 2105 if (i == (LINK_UP_TIMEOUT / 10)) { 2106 /* AutoNeg failed to achieve a link, so we'll call 2107 * e1000_check_for_link. This routine will force the link up if we 2108 * detect a signal. This will allow us to communicate with 2109 * non-autonegotiating link partners. 2110 */ 2111 DEBUGOUT("Never got a valid link from auto-neg!!!\n"); 2112 hw->autoneg_failed = 1; 2113 ret_val = e1000_check_for_link(nic); 2114 if (ret_val < 0) { 2115 DEBUGOUT("Error while checking for link\n"); 2116 return ret_val; 2117 } 2118 hw->autoneg_failed = 0; 2119 } else { 2120 hw->autoneg_failed = 0; 2121 DEBUGOUT("Valid Link Found\n"); 2122 } 2123 } else { 2124 DEBUGOUT("No Signal Detected\n"); 2125 return -E1000_ERR_NOLINK; 2126 } 2127 return 0; 2128 } 2129 2130 /****************************************************************************** 2131 * Make sure we have a valid PHY and change PHY mode before link setup. 2132 * 2133 * hw - Struct containing variables accessed by shared code 2134 ******************************************************************************/ 2135 static int32_t 2136 e1000_copper_link_preconfig(struct e1000_hw *hw) 2137 { 2138 uint32_t ctrl; 2139 int32_t ret_val; 2140 uint16_t phy_data; 2141 2142 DEBUGFUNC(); 2143 2144 ctrl = E1000_READ_REG(hw, CTRL); 2145 /* With 82543, we need to force speed and duplex on the MAC equal to what 2146 * the PHY speed and duplex configuration is. In addition, we need to 2147 * perform a hardware reset on the PHY to take it out of reset. 2148 */ 2149 if (hw->mac_type > e1000_82543) { 2150 ctrl |= E1000_CTRL_SLU; 2151 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 2152 E1000_WRITE_REG(hw, CTRL, ctrl); 2153 } else { 2154 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX 2155 | E1000_CTRL_SLU); 2156 E1000_WRITE_REG(hw, CTRL, ctrl); 2157 ret_val = e1000_phy_hw_reset(hw); 2158 if (ret_val) 2159 return ret_val; 2160 } 2161 2162 /* Make sure we have a valid PHY */ 2163 ret_val = e1000_detect_gig_phy(hw); 2164 if (ret_val) { 2165 DEBUGOUT("Error, did not detect valid phy.\n"); 2166 return ret_val; 2167 } 2168 DEBUGOUT("Phy ID = %x \n", hw->phy_id); 2169 2170 /* Set PHY to class A mode (if necessary) */ 2171 ret_val = e1000_set_phy_mode(hw); 2172 if (ret_val) 2173 return ret_val; 2174 if ((hw->mac_type == e1000_82545_rev_3) || 2175 (hw->mac_type == e1000_82546_rev_3)) { 2176 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 2177 &phy_data); 2178 phy_data |= 0x00000008; 2179 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 2180 phy_data); 2181 } 2182 2183 if (hw->mac_type <= e1000_82543 || 2184 hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 || 2185 hw->mac_type == e1000_82541_rev_2 2186 || hw->mac_type == e1000_82547_rev_2) 2187 hw->phy_reset_disable = false; 2188 2189 return E1000_SUCCESS; 2190 } 2191 2192 /***************************************************************************** 2193 * 2194 * This function sets the lplu state according to the active flag. When 2195 * activating lplu this function also disables smart speed and vise versa. 2196 * lplu will not be activated unless the device autonegotiation advertisment 2197 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes. 2198 * hw: Struct containing variables accessed by shared code 2199 * active - true to enable lplu false to disable lplu. 2200 * 2201 * returns: - E1000_ERR_PHY if fail to read/write the PHY 2202 * E1000_SUCCESS at any other case. 2203 * 2204 ****************************************************************************/ 2205 2206 static int32_t 2207 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active) 2208 { 2209 uint32_t phy_ctrl = 0; 2210 int32_t ret_val; 2211 uint16_t phy_data; 2212 DEBUGFUNC(); 2213 2214 if (hw->phy_type != e1000_phy_igp && hw->phy_type != e1000_phy_igp_2 2215 && hw->phy_type != e1000_phy_igp_3) 2216 return E1000_SUCCESS; 2217 2218 /* During driver activity LPLU should not be used or it will attain link 2219 * from the lowest speeds starting from 10Mbps. The capability is used 2220 * for Dx transitions and states */ 2221 if (hw->mac_type == e1000_82541_rev_2 2222 || hw->mac_type == e1000_82547_rev_2) { 2223 ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, 2224 &phy_data); 2225 if (ret_val) 2226 return ret_val; 2227 } else if (hw->mac_type == e1000_ich8lan) { 2228 /* MAC writes into PHY register based on the state transition 2229 * and start auto-negotiation. SW driver can overwrite the 2230 * settings in CSR PHY power control E1000_PHY_CTRL register. */ 2231 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL); 2232 } else { 2233 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, 2234 &phy_data); 2235 if (ret_val) 2236 return ret_val; 2237 } 2238 2239 if (!active) { 2240 if (hw->mac_type == e1000_82541_rev_2 || 2241 hw->mac_type == e1000_82547_rev_2) { 2242 phy_data &= ~IGP01E1000_GMII_FLEX_SPD; 2243 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, 2244 phy_data); 2245 if (ret_val) 2246 return ret_val; 2247 } else { 2248 if (hw->mac_type == e1000_ich8lan) { 2249 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU; 2250 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); 2251 } else { 2252 phy_data &= ~IGP02E1000_PM_D3_LPLU; 2253 ret_val = e1000_write_phy_reg(hw, 2254 IGP02E1000_PHY_POWER_MGMT, phy_data); 2255 if (ret_val) 2256 return ret_val; 2257 } 2258 } 2259 2260 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during 2261 * Dx states where the power conservation is most important. During 2262 * driver activity we should enable SmartSpeed, so performance is 2263 * maintained. */ 2264 if (hw->smart_speed == e1000_smart_speed_on) { 2265 ret_val = e1000_read_phy_reg(hw, 2266 IGP01E1000_PHY_PORT_CONFIG, &phy_data); 2267 if (ret_val) 2268 return ret_val; 2269 2270 phy_data |= IGP01E1000_PSCFR_SMART_SPEED; 2271 ret_val = e1000_write_phy_reg(hw, 2272 IGP01E1000_PHY_PORT_CONFIG, phy_data); 2273 if (ret_val) 2274 return ret_val; 2275 } else if (hw->smart_speed == e1000_smart_speed_off) { 2276 ret_val = e1000_read_phy_reg(hw, 2277 IGP01E1000_PHY_PORT_CONFIG, &phy_data); 2278 if (ret_val) 2279 return ret_val; 2280 2281 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 2282 ret_val = e1000_write_phy_reg(hw, 2283 IGP01E1000_PHY_PORT_CONFIG, phy_data); 2284 if (ret_val) 2285 return ret_val; 2286 } 2287 2288 } else if ((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT) 2289 || (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL) || 2290 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) { 2291 2292 if (hw->mac_type == e1000_82541_rev_2 || 2293 hw->mac_type == e1000_82547_rev_2) { 2294 phy_data |= IGP01E1000_GMII_FLEX_SPD; 2295 ret_val = e1000_write_phy_reg(hw, 2296 IGP01E1000_GMII_FIFO, phy_data); 2297 if (ret_val) 2298 return ret_val; 2299 } else { 2300 if (hw->mac_type == e1000_ich8lan) { 2301 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU; 2302 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); 2303 } else { 2304 phy_data |= IGP02E1000_PM_D3_LPLU; 2305 ret_val = e1000_write_phy_reg(hw, 2306 IGP02E1000_PHY_POWER_MGMT, phy_data); 2307 if (ret_val) 2308 return ret_val; 2309 } 2310 } 2311 2312 /* When LPLU is enabled we should disable SmartSpeed */ 2313 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 2314 &phy_data); 2315 if (ret_val) 2316 return ret_val; 2317 2318 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 2319 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 2320 phy_data); 2321 if (ret_val) 2322 return ret_val; 2323 } 2324 return E1000_SUCCESS; 2325 } 2326 2327 /***************************************************************************** 2328 * 2329 * This function sets the lplu d0 state according to the active flag. When 2330 * activating lplu this function also disables smart speed and vise versa. 2331 * lplu will not be activated unless the device autonegotiation advertisment 2332 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes. 2333 * hw: Struct containing variables accessed by shared code 2334 * active - true to enable lplu false to disable lplu. 2335 * 2336 * returns: - E1000_ERR_PHY if fail to read/write the PHY 2337 * E1000_SUCCESS at any other case. 2338 * 2339 ****************************************************************************/ 2340 2341 static int32_t 2342 e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active) 2343 { 2344 uint32_t phy_ctrl = 0; 2345 int32_t ret_val; 2346 uint16_t phy_data; 2347 DEBUGFUNC(); 2348 2349 if (hw->mac_type <= e1000_82547_rev_2) 2350 return E1000_SUCCESS; 2351 2352 if (hw->mac_type == e1000_ich8lan) { 2353 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL); 2354 } else if (hw->mac_type == e1000_igb) { 2355 phy_ctrl = E1000_READ_REG(hw, I210_PHY_CTRL); 2356 } else { 2357 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, 2358 &phy_data); 2359 if (ret_val) 2360 return ret_val; 2361 } 2362 2363 if (!active) { 2364 if (hw->mac_type == e1000_ich8lan) { 2365 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU; 2366 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); 2367 } else if (hw->mac_type == e1000_igb) { 2368 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU; 2369 E1000_WRITE_REG(hw, I210_PHY_CTRL, phy_ctrl); 2370 } else { 2371 phy_data &= ~IGP02E1000_PM_D0_LPLU; 2372 ret_val = e1000_write_phy_reg(hw, 2373 IGP02E1000_PHY_POWER_MGMT, phy_data); 2374 if (ret_val) 2375 return ret_val; 2376 } 2377 2378 if (hw->mac_type == e1000_igb) 2379 return E1000_SUCCESS; 2380 2381 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during 2382 * Dx states where the power conservation is most important. During 2383 * driver activity we should enable SmartSpeed, so performance is 2384 * maintained. */ 2385 if (hw->smart_speed == e1000_smart_speed_on) { 2386 ret_val = e1000_read_phy_reg(hw, 2387 IGP01E1000_PHY_PORT_CONFIG, &phy_data); 2388 if (ret_val) 2389 return ret_val; 2390 2391 phy_data |= IGP01E1000_PSCFR_SMART_SPEED; 2392 ret_val = e1000_write_phy_reg(hw, 2393 IGP01E1000_PHY_PORT_CONFIG, phy_data); 2394 if (ret_val) 2395 return ret_val; 2396 } else if (hw->smart_speed == e1000_smart_speed_off) { 2397 ret_val = e1000_read_phy_reg(hw, 2398 IGP01E1000_PHY_PORT_CONFIG, &phy_data); 2399 if (ret_val) 2400 return ret_val; 2401 2402 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 2403 ret_val = e1000_write_phy_reg(hw, 2404 IGP01E1000_PHY_PORT_CONFIG, phy_data); 2405 if (ret_val) 2406 return ret_val; 2407 } 2408 2409 2410 } else { 2411 2412 if (hw->mac_type == e1000_ich8lan) { 2413 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU; 2414 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); 2415 } else if (hw->mac_type == e1000_igb) { 2416 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU; 2417 E1000_WRITE_REG(hw, I210_PHY_CTRL, phy_ctrl); 2418 } else { 2419 phy_data |= IGP02E1000_PM_D0_LPLU; 2420 ret_val = e1000_write_phy_reg(hw, 2421 IGP02E1000_PHY_POWER_MGMT, phy_data); 2422 if (ret_val) 2423 return ret_val; 2424 } 2425 2426 if (hw->mac_type == e1000_igb) 2427 return E1000_SUCCESS; 2428 2429 /* When LPLU is enabled we should disable SmartSpeed */ 2430 ret_val = e1000_read_phy_reg(hw, 2431 IGP01E1000_PHY_PORT_CONFIG, &phy_data); 2432 if (ret_val) 2433 return ret_val; 2434 2435 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 2436 ret_val = e1000_write_phy_reg(hw, 2437 IGP01E1000_PHY_PORT_CONFIG, phy_data); 2438 if (ret_val) 2439 return ret_val; 2440 2441 } 2442 return E1000_SUCCESS; 2443 } 2444 2445 /******************************************************************** 2446 * Copper link setup for e1000_phy_igp series. 2447 * 2448 * hw - Struct containing variables accessed by shared code 2449 *********************************************************************/ 2450 static int32_t 2451 e1000_copper_link_igp_setup(struct e1000_hw *hw) 2452 { 2453 uint32_t led_ctrl; 2454 int32_t ret_val; 2455 uint16_t phy_data; 2456 2457 DEBUGFUNC(); 2458 2459 if (hw->phy_reset_disable) 2460 return E1000_SUCCESS; 2461 2462 ret_val = e1000_phy_reset(hw); 2463 if (ret_val) { 2464 DEBUGOUT("Error Resetting the PHY\n"); 2465 return ret_val; 2466 } 2467 2468 /* Wait 15ms for MAC to configure PHY from eeprom settings */ 2469 mdelay(15); 2470 if (hw->mac_type != e1000_ich8lan) { 2471 /* Configure activity LED after PHY reset */ 2472 led_ctrl = E1000_READ_REG(hw, LEDCTL); 2473 led_ctrl &= IGP_ACTIVITY_LED_MASK; 2474 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); 2475 E1000_WRITE_REG(hw, LEDCTL, led_ctrl); 2476 } 2477 2478 /* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */ 2479 if (hw->phy_type == e1000_phy_igp) { 2480 /* disable lplu d3 during driver init */ 2481 ret_val = e1000_set_d3_lplu_state(hw, false); 2482 if (ret_val) { 2483 DEBUGOUT("Error Disabling LPLU D3\n"); 2484 return ret_val; 2485 } 2486 } 2487 2488 /* disable lplu d0 during driver init */ 2489 ret_val = e1000_set_d0_lplu_state(hw, false); 2490 if (ret_val) { 2491 DEBUGOUT("Error Disabling LPLU D0\n"); 2492 return ret_val; 2493 } 2494 /* Configure mdi-mdix settings */ 2495 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); 2496 if (ret_val) 2497 return ret_val; 2498 2499 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { 2500 hw->dsp_config_state = e1000_dsp_config_disabled; 2501 /* Force MDI for earlier revs of the IGP PHY */ 2502 phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX 2503 | IGP01E1000_PSCR_FORCE_MDI_MDIX); 2504 hw->mdix = 1; 2505 2506 } else { 2507 hw->dsp_config_state = e1000_dsp_config_enabled; 2508 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; 2509 2510 switch (hw->mdix) { 2511 case 1: 2512 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; 2513 break; 2514 case 2: 2515 phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX; 2516 break; 2517 case 0: 2518 default: 2519 phy_data |= IGP01E1000_PSCR_AUTO_MDIX; 2520 break; 2521 } 2522 } 2523 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); 2524 if (ret_val) 2525 return ret_val; 2526 2527 /* set auto-master slave resolution settings */ 2528 if (hw->autoneg) { 2529 e1000_ms_type phy_ms_setting = hw->master_slave; 2530 2531 if (hw->ffe_config_state == e1000_ffe_config_active) 2532 hw->ffe_config_state = e1000_ffe_config_enabled; 2533 2534 if (hw->dsp_config_state == e1000_dsp_config_activated) 2535 hw->dsp_config_state = e1000_dsp_config_enabled; 2536 2537 /* when autonegotiation advertisment is only 1000Mbps then we 2538 * should disable SmartSpeed and enable Auto MasterSlave 2539 * resolution as hardware default. */ 2540 if (hw->autoneg_advertised == ADVERTISE_1000_FULL) { 2541 /* Disable SmartSpeed */ 2542 ret_val = e1000_read_phy_reg(hw, 2543 IGP01E1000_PHY_PORT_CONFIG, &phy_data); 2544 if (ret_val) 2545 return ret_val; 2546 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 2547 ret_val = e1000_write_phy_reg(hw, 2548 IGP01E1000_PHY_PORT_CONFIG, phy_data); 2549 if (ret_val) 2550 return ret_val; 2551 /* Set auto Master/Slave resolution process */ 2552 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, 2553 &phy_data); 2554 if (ret_val) 2555 return ret_val; 2556 phy_data &= ~CR_1000T_MS_ENABLE; 2557 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, 2558 phy_data); 2559 if (ret_val) 2560 return ret_val; 2561 } 2562 2563 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data); 2564 if (ret_val) 2565 return ret_val; 2566 2567 /* load defaults for future use */ 2568 hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ? 2569 ((phy_data & CR_1000T_MS_VALUE) ? 2570 e1000_ms_force_master : 2571 e1000_ms_force_slave) : 2572 e1000_ms_auto; 2573 2574 switch (phy_ms_setting) { 2575 case e1000_ms_force_master: 2576 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE); 2577 break; 2578 case e1000_ms_force_slave: 2579 phy_data |= CR_1000T_MS_ENABLE; 2580 phy_data &= ~(CR_1000T_MS_VALUE); 2581 break; 2582 case e1000_ms_auto: 2583 phy_data &= ~CR_1000T_MS_ENABLE; 2584 default: 2585 break; 2586 } 2587 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data); 2588 if (ret_val) 2589 return ret_val; 2590 } 2591 2592 return E1000_SUCCESS; 2593 } 2594 2595 /***************************************************************************** 2596 * This function checks the mode of the firmware. 2597 * 2598 * returns - true when the mode is IAMT or false. 2599 ****************************************************************************/ 2600 bool 2601 e1000_check_mng_mode(struct e1000_hw *hw) 2602 { 2603 uint32_t fwsm; 2604 DEBUGFUNC(); 2605 2606 fwsm = E1000_READ_REG(hw, FWSM); 2607 2608 if (hw->mac_type == e1000_ich8lan) { 2609 if ((fwsm & E1000_FWSM_MODE_MASK) == 2610 (E1000_MNG_ICH_IAMT_MODE << E1000_FWSM_MODE_SHIFT)) 2611 return true; 2612 } else if ((fwsm & E1000_FWSM_MODE_MASK) == 2613 (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT)) 2614 return true; 2615 2616 return false; 2617 } 2618 2619 static int32_t 2620 e1000_write_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t data) 2621 { 2622 uint16_t swfw = E1000_SWFW_PHY0_SM; 2623 uint32_t reg_val; 2624 DEBUGFUNC(); 2625 2626 if (e1000_is_second_port(hw)) 2627 swfw = E1000_SWFW_PHY1_SM; 2628 2629 if (e1000_swfw_sync_acquire(hw, swfw)) 2630 return -E1000_ERR_SWFW_SYNC; 2631 2632 reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) 2633 & E1000_KUMCTRLSTA_OFFSET) | data; 2634 E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val); 2635 udelay(2); 2636 2637 return E1000_SUCCESS; 2638 } 2639 2640 static int32_t 2641 e1000_read_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *data) 2642 { 2643 uint16_t swfw = E1000_SWFW_PHY0_SM; 2644 uint32_t reg_val; 2645 DEBUGFUNC(); 2646 2647 if (e1000_is_second_port(hw)) 2648 swfw = E1000_SWFW_PHY1_SM; 2649 2650 if (e1000_swfw_sync_acquire(hw, swfw)) { 2651 debug("%s[%i]\n", __func__, __LINE__); 2652 return -E1000_ERR_SWFW_SYNC; 2653 } 2654 2655 /* Write register address */ 2656 reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) & 2657 E1000_KUMCTRLSTA_OFFSET) | E1000_KUMCTRLSTA_REN; 2658 E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val); 2659 udelay(2); 2660 2661 /* Read the data returned */ 2662 reg_val = E1000_READ_REG(hw, KUMCTRLSTA); 2663 *data = (uint16_t)reg_val; 2664 2665 return E1000_SUCCESS; 2666 } 2667 2668 /******************************************************************** 2669 * Copper link setup for e1000_phy_gg82563 series. 2670 * 2671 * hw - Struct containing variables accessed by shared code 2672 *********************************************************************/ 2673 static int32_t 2674 e1000_copper_link_ggp_setup(struct e1000_hw *hw) 2675 { 2676 int32_t ret_val; 2677 uint16_t phy_data; 2678 uint32_t reg_data; 2679 2680 DEBUGFUNC(); 2681 2682 if (!hw->phy_reset_disable) { 2683 /* Enable CRS on TX for half-duplex operation. */ 2684 ret_val = e1000_read_phy_reg(hw, 2685 GG82563_PHY_MAC_SPEC_CTRL, &phy_data); 2686 if (ret_val) 2687 return ret_val; 2688 2689 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX; 2690 /* Use 25MHz for both link down and 1000BASE-T for Tx clock */ 2691 phy_data |= GG82563_MSCR_TX_CLK_1000MBPS_25MHZ; 2692 2693 ret_val = e1000_write_phy_reg(hw, 2694 GG82563_PHY_MAC_SPEC_CTRL, phy_data); 2695 if (ret_val) 2696 return ret_val; 2697 2698 /* Options: 2699 * MDI/MDI-X = 0 (default) 2700 * 0 - Auto for all speeds 2701 * 1 - MDI mode 2702 * 2 - MDI-X mode 2703 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) 2704 */ 2705 ret_val = e1000_read_phy_reg(hw, 2706 GG82563_PHY_SPEC_CTRL, &phy_data); 2707 if (ret_val) 2708 return ret_val; 2709 2710 phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK; 2711 2712 switch (hw->mdix) { 2713 case 1: 2714 phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDI; 2715 break; 2716 case 2: 2717 phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDIX; 2718 break; 2719 case 0: 2720 default: 2721 phy_data |= GG82563_PSCR_CROSSOVER_MODE_AUTO; 2722 break; 2723 } 2724 2725 /* Options: 2726 * disable_polarity_correction = 0 (default) 2727 * Automatic Correction for Reversed Cable Polarity 2728 * 0 - Disabled 2729 * 1 - Enabled 2730 */ 2731 phy_data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE; 2732 ret_val = e1000_write_phy_reg(hw, 2733 GG82563_PHY_SPEC_CTRL, phy_data); 2734 2735 if (ret_val) 2736 return ret_val; 2737 2738 /* SW Reset the PHY so all changes take effect */ 2739 ret_val = e1000_phy_reset(hw); 2740 if (ret_val) { 2741 DEBUGOUT("Error Resetting the PHY\n"); 2742 return ret_val; 2743 } 2744 } /* phy_reset_disable */ 2745 2746 if (hw->mac_type == e1000_80003es2lan) { 2747 /* Bypass RX and TX FIFO's */ 2748 ret_val = e1000_write_kmrn_reg(hw, 2749 E1000_KUMCTRLSTA_OFFSET_FIFO_CTRL, 2750 E1000_KUMCTRLSTA_FIFO_CTRL_RX_BYPASS 2751 | E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS); 2752 if (ret_val) 2753 return ret_val; 2754 2755 ret_val = e1000_read_phy_reg(hw, 2756 GG82563_PHY_SPEC_CTRL_2, &phy_data); 2757 if (ret_val) 2758 return ret_val; 2759 2760 phy_data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG; 2761 ret_val = e1000_write_phy_reg(hw, 2762 GG82563_PHY_SPEC_CTRL_2, phy_data); 2763 2764 if (ret_val) 2765 return ret_val; 2766 2767 reg_data = E1000_READ_REG(hw, CTRL_EXT); 2768 reg_data &= ~(E1000_CTRL_EXT_LINK_MODE_MASK); 2769 E1000_WRITE_REG(hw, CTRL_EXT, reg_data); 2770 2771 ret_val = e1000_read_phy_reg(hw, 2772 GG82563_PHY_PWR_MGMT_CTRL, &phy_data); 2773 if (ret_val) 2774 return ret_val; 2775 2776 /* Do not init these registers when the HW is in IAMT mode, since the 2777 * firmware will have already initialized them. We only initialize 2778 * them if the HW is not in IAMT mode. 2779 */ 2780 if (e1000_check_mng_mode(hw) == false) { 2781 /* Enable Electrical Idle on the PHY */ 2782 phy_data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE; 2783 ret_val = e1000_write_phy_reg(hw, 2784 GG82563_PHY_PWR_MGMT_CTRL, phy_data); 2785 if (ret_val) 2786 return ret_val; 2787 2788 ret_val = e1000_read_phy_reg(hw, 2789 GG82563_PHY_KMRN_MODE_CTRL, &phy_data); 2790 if (ret_val) 2791 return ret_val; 2792 2793 phy_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; 2794 ret_val = e1000_write_phy_reg(hw, 2795 GG82563_PHY_KMRN_MODE_CTRL, phy_data); 2796 2797 if (ret_val) 2798 return ret_val; 2799 } 2800 2801 /* Workaround: Disable padding in Kumeran interface in the MAC 2802 * and in the PHY to avoid CRC errors. 2803 */ 2804 ret_val = e1000_read_phy_reg(hw, 2805 GG82563_PHY_INBAND_CTRL, &phy_data); 2806 if (ret_val) 2807 return ret_val; 2808 phy_data |= GG82563_ICR_DIS_PADDING; 2809 ret_val = e1000_write_phy_reg(hw, 2810 GG82563_PHY_INBAND_CTRL, phy_data); 2811 if (ret_val) 2812 return ret_val; 2813 } 2814 return E1000_SUCCESS; 2815 } 2816 2817 /******************************************************************** 2818 * Copper link setup for e1000_phy_m88 series. 2819 * 2820 * hw - Struct containing variables accessed by shared code 2821 *********************************************************************/ 2822 static int32_t 2823 e1000_copper_link_mgp_setup(struct e1000_hw *hw) 2824 { 2825 int32_t ret_val; 2826 uint16_t phy_data; 2827 2828 DEBUGFUNC(); 2829 2830 if (hw->phy_reset_disable) 2831 return E1000_SUCCESS; 2832 2833 /* Enable CRS on TX. This must be set for half-duplex operation. */ 2834 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 2835 if (ret_val) 2836 return ret_val; 2837 2838 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; 2839 2840 /* Options: 2841 * MDI/MDI-X = 0 (default) 2842 * 0 - Auto for all speeds 2843 * 1 - MDI mode 2844 * 2 - MDI-X mode 2845 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) 2846 */ 2847 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 2848 2849 switch (hw->mdix) { 2850 case 1: 2851 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; 2852 break; 2853 case 2: 2854 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; 2855 break; 2856 case 3: 2857 phy_data |= M88E1000_PSCR_AUTO_X_1000T; 2858 break; 2859 case 0: 2860 default: 2861 phy_data |= M88E1000_PSCR_AUTO_X_MODE; 2862 break; 2863 } 2864 2865 /* Options: 2866 * disable_polarity_correction = 0 (default) 2867 * Automatic Correction for Reversed Cable Polarity 2868 * 0 - Disabled 2869 * 1 - Enabled 2870 */ 2871 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; 2872 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 2873 if (ret_val) 2874 return ret_val; 2875 2876 if (hw->phy_revision < M88E1011_I_REV_4) { 2877 /* Force TX_CLK in the Extended PHY Specific Control Register 2878 * to 25MHz clock. 2879 */ 2880 ret_val = e1000_read_phy_reg(hw, 2881 M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); 2882 if (ret_val) 2883 return ret_val; 2884 2885 phy_data |= M88E1000_EPSCR_TX_CLK_25; 2886 2887 if ((hw->phy_revision == E1000_REVISION_2) && 2888 (hw->phy_id == M88E1111_I_PHY_ID)) { 2889 /* Vidalia Phy, set the downshift counter to 5x */ 2890 phy_data &= ~(M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK); 2891 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X; 2892 ret_val = e1000_write_phy_reg(hw, 2893 M88E1000_EXT_PHY_SPEC_CTRL, phy_data); 2894 if (ret_val) 2895 return ret_val; 2896 } else { 2897 /* Configure Master and Slave downshift values */ 2898 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 2899 | M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK); 2900 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X 2901 | M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X); 2902 ret_val = e1000_write_phy_reg(hw, 2903 M88E1000_EXT_PHY_SPEC_CTRL, phy_data); 2904 if (ret_val) 2905 return ret_val; 2906 } 2907 } 2908 2909 /* SW Reset the PHY so all changes take effect */ 2910 ret_val = e1000_phy_reset(hw); 2911 if (ret_val) { 2912 DEBUGOUT("Error Resetting the PHY\n"); 2913 return ret_val; 2914 } 2915 2916 return E1000_SUCCESS; 2917 } 2918 2919 /******************************************************************** 2920 * Setup auto-negotiation and flow control advertisements, 2921 * and then perform auto-negotiation. 2922 * 2923 * hw - Struct containing variables accessed by shared code 2924 *********************************************************************/ 2925 static int32_t 2926 e1000_copper_link_autoneg(struct e1000_hw *hw) 2927 { 2928 int32_t ret_val; 2929 uint16_t phy_data; 2930 2931 DEBUGFUNC(); 2932 2933 /* Perform some bounds checking on the hw->autoneg_advertised 2934 * parameter. If this variable is zero, then set it to the default. 2935 */ 2936 hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT; 2937 2938 /* If autoneg_advertised is zero, we assume it was not defaulted 2939 * by the calling code so we set to advertise full capability. 2940 */ 2941 if (hw->autoneg_advertised == 0) 2942 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT; 2943 2944 /* IFE phy only supports 10/100 */ 2945 if (hw->phy_type == e1000_phy_ife) 2946 hw->autoneg_advertised &= AUTONEG_ADVERTISE_10_100_ALL; 2947 2948 DEBUGOUT("Reconfiguring auto-neg advertisement params\n"); 2949 ret_val = e1000_phy_setup_autoneg(hw); 2950 if (ret_val) { 2951 DEBUGOUT("Error Setting up Auto-Negotiation\n"); 2952 return ret_val; 2953 } 2954 DEBUGOUT("Restarting Auto-Neg\n"); 2955 2956 /* Restart auto-negotiation by setting the Auto Neg Enable bit and 2957 * the Auto Neg Restart bit in the PHY control register. 2958 */ 2959 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data); 2960 if (ret_val) 2961 return ret_val; 2962 2963 phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); 2964 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data); 2965 if (ret_val) 2966 return ret_val; 2967 2968 /* Does the user want to wait for Auto-Neg to complete here, or 2969 * check at a later time (for example, callback routine). 2970 */ 2971 /* If we do not wait for autonegtation to complete I 2972 * do not see a valid link status. 2973 * wait_autoneg_complete = 1 . 2974 */ 2975 if (hw->wait_autoneg_complete) { 2976 ret_val = e1000_wait_autoneg(hw); 2977 if (ret_val) { 2978 DEBUGOUT("Error while waiting for autoneg" 2979 "to complete\n"); 2980 return ret_val; 2981 } 2982 } 2983 2984 hw->get_link_status = true; 2985 2986 return E1000_SUCCESS; 2987 } 2988 2989 /****************************************************************************** 2990 * Config the MAC and the PHY after link is up. 2991 * 1) Set up the MAC to the current PHY speed/duplex 2992 * if we are on 82543. If we 2993 * are on newer silicon, we only need to configure 2994 * collision distance in the Transmit Control Register. 2995 * 2) Set up flow control on the MAC to that established with 2996 * the link partner. 2997 * 3) Config DSP to improve Gigabit link quality for some PHY revisions. 2998 * 2999 * hw - Struct containing variables accessed by shared code 3000 ******************************************************************************/ 3001 static int32_t 3002 e1000_copper_link_postconfig(struct e1000_hw *hw) 3003 { 3004 int32_t ret_val; 3005 DEBUGFUNC(); 3006 3007 if (hw->mac_type >= e1000_82544) { 3008 e1000_config_collision_dist(hw); 3009 } else { 3010 ret_val = e1000_config_mac_to_phy(hw); 3011 if (ret_val) { 3012 DEBUGOUT("Error configuring MAC to PHY settings\n"); 3013 return ret_val; 3014 } 3015 } 3016 ret_val = e1000_config_fc_after_link_up(hw); 3017 if (ret_val) { 3018 DEBUGOUT("Error Configuring Flow Control\n"); 3019 return ret_val; 3020 } 3021 return E1000_SUCCESS; 3022 } 3023 3024 /****************************************************************************** 3025 * Detects which PHY is present and setup the speed and duplex 3026 * 3027 * hw - Struct containing variables accessed by shared code 3028 ******************************************************************************/ 3029 static int 3030 e1000_setup_copper_link(struct eth_device *nic) 3031 { 3032 struct e1000_hw *hw = nic->priv; 3033 int32_t ret_val; 3034 uint16_t i; 3035 uint16_t phy_data; 3036 uint16_t reg_data; 3037 3038 DEBUGFUNC(); 3039 3040 switch (hw->mac_type) { 3041 case e1000_80003es2lan: 3042 case e1000_ich8lan: 3043 /* Set the mac to wait the maximum time between each 3044 * iteration and increase the max iterations when 3045 * polling the phy; this fixes erroneous timeouts at 10Mbps. */ 3046 ret_val = e1000_write_kmrn_reg(hw, 3047 GG82563_REG(0x34, 4), 0xFFFF); 3048 if (ret_val) 3049 return ret_val; 3050 ret_val = e1000_read_kmrn_reg(hw, 3051 GG82563_REG(0x34, 9), ®_data); 3052 if (ret_val) 3053 return ret_val; 3054 reg_data |= 0x3F; 3055 ret_val = e1000_write_kmrn_reg(hw, 3056 GG82563_REG(0x34, 9), reg_data); 3057 if (ret_val) 3058 return ret_val; 3059 default: 3060 break; 3061 } 3062 3063 /* Check if it is a valid PHY and set PHY mode if necessary. */ 3064 ret_val = e1000_copper_link_preconfig(hw); 3065 if (ret_val) 3066 return ret_val; 3067 switch (hw->mac_type) { 3068 case e1000_80003es2lan: 3069 /* Kumeran registers are written-only */ 3070 reg_data = 3071 E1000_KUMCTRLSTA_INB_CTRL_LINK_STATUS_TX_TIMEOUT_DEFAULT; 3072 reg_data |= E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING; 3073 ret_val = e1000_write_kmrn_reg(hw, 3074 E1000_KUMCTRLSTA_OFFSET_INB_CTRL, reg_data); 3075 if (ret_val) 3076 return ret_val; 3077 break; 3078 default: 3079 break; 3080 } 3081 3082 if (hw->phy_type == e1000_phy_igp || 3083 hw->phy_type == e1000_phy_igp_3 || 3084 hw->phy_type == e1000_phy_igp_2) { 3085 ret_val = e1000_copper_link_igp_setup(hw); 3086 if (ret_val) 3087 return ret_val; 3088 } else if (hw->phy_type == e1000_phy_m88 || 3089 hw->phy_type == e1000_phy_igb) { 3090 ret_val = e1000_copper_link_mgp_setup(hw); 3091 if (ret_val) 3092 return ret_val; 3093 } else if (hw->phy_type == e1000_phy_gg82563) { 3094 ret_val = e1000_copper_link_ggp_setup(hw); 3095 if (ret_val) 3096 return ret_val; 3097 } 3098 3099 /* always auto */ 3100 /* Setup autoneg and flow control advertisement 3101 * and perform autonegotiation */ 3102 ret_val = e1000_copper_link_autoneg(hw); 3103 if (ret_val) 3104 return ret_val; 3105 3106 /* Check link status. Wait up to 100 microseconds for link to become 3107 * valid. 3108 */ 3109 for (i = 0; i < 10; i++) { 3110 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); 3111 if (ret_val) 3112 return ret_val; 3113 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); 3114 if (ret_val) 3115 return ret_val; 3116 3117 if (phy_data & MII_SR_LINK_STATUS) { 3118 /* Config the MAC and PHY after link is up */ 3119 ret_val = e1000_copper_link_postconfig(hw); 3120 if (ret_val) 3121 return ret_val; 3122 3123 DEBUGOUT("Valid link established!!!\n"); 3124 return E1000_SUCCESS; 3125 } 3126 udelay(10); 3127 } 3128 3129 DEBUGOUT("Unable to establish link!!!\n"); 3130 return E1000_SUCCESS; 3131 } 3132 3133 /****************************************************************************** 3134 * Configures PHY autoneg and flow control advertisement settings 3135 * 3136 * hw - Struct containing variables accessed by shared code 3137 ******************************************************************************/ 3138 int32_t 3139 e1000_phy_setup_autoneg(struct e1000_hw *hw) 3140 { 3141 int32_t ret_val; 3142 uint16_t mii_autoneg_adv_reg; 3143 uint16_t mii_1000t_ctrl_reg; 3144 3145 DEBUGFUNC(); 3146 3147 /* Read the MII Auto-Neg Advertisement Register (Address 4). */ 3148 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg); 3149 if (ret_val) 3150 return ret_val; 3151 3152 if (hw->phy_type != e1000_phy_ife) { 3153 /* Read the MII 1000Base-T Control Register (Address 9). */ 3154 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, 3155 &mii_1000t_ctrl_reg); 3156 if (ret_val) 3157 return ret_val; 3158 } else 3159 mii_1000t_ctrl_reg = 0; 3160 3161 /* Need to parse both autoneg_advertised and fc and set up 3162 * the appropriate PHY registers. First we will parse for 3163 * autoneg_advertised software override. Since we can advertise 3164 * a plethora of combinations, we need to check each bit 3165 * individually. 3166 */ 3167 3168 /* First we clear all the 10/100 mb speed bits in the Auto-Neg 3169 * Advertisement Register (Address 4) and the 1000 mb speed bits in 3170 * the 1000Base-T Control Register (Address 9). 3171 */ 3172 mii_autoneg_adv_reg &= ~REG4_SPEED_MASK; 3173 mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK; 3174 3175 DEBUGOUT("autoneg_advertised %x\n", hw->autoneg_advertised); 3176 3177 /* Do we want to advertise 10 Mb Half Duplex? */ 3178 if (hw->autoneg_advertised & ADVERTISE_10_HALF) { 3179 DEBUGOUT("Advertise 10mb Half duplex\n"); 3180 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS; 3181 } 3182 3183 /* Do we want to advertise 10 Mb Full Duplex? */ 3184 if (hw->autoneg_advertised & ADVERTISE_10_FULL) { 3185 DEBUGOUT("Advertise 10mb Full duplex\n"); 3186 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS; 3187 } 3188 3189 /* Do we want to advertise 100 Mb Half Duplex? */ 3190 if (hw->autoneg_advertised & ADVERTISE_100_HALF) { 3191 DEBUGOUT("Advertise 100mb Half duplex\n"); 3192 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS; 3193 } 3194 3195 /* Do we want to advertise 100 Mb Full Duplex? */ 3196 if (hw->autoneg_advertised & ADVERTISE_100_FULL) { 3197 DEBUGOUT("Advertise 100mb Full duplex\n"); 3198 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS; 3199 } 3200 3201 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */ 3202 if (hw->autoneg_advertised & ADVERTISE_1000_HALF) { 3203 DEBUGOUT 3204 ("Advertise 1000mb Half duplex requested, request denied!\n"); 3205 } 3206 3207 /* Do we want to advertise 1000 Mb Full Duplex? */ 3208 if (hw->autoneg_advertised & ADVERTISE_1000_FULL) { 3209 DEBUGOUT("Advertise 1000mb Full duplex\n"); 3210 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS; 3211 } 3212 3213 /* Check for a software override of the flow control settings, and 3214 * setup the PHY advertisement registers accordingly. If 3215 * auto-negotiation is enabled, then software will have to set the 3216 * "PAUSE" bits to the correct value in the Auto-Negotiation 3217 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation. 3218 * 3219 * The possible values of the "fc" parameter are: 3220 * 0: Flow control is completely disabled 3221 * 1: Rx flow control is enabled (we can receive pause frames 3222 * but not send pause frames). 3223 * 2: Tx flow control is enabled (we can send pause frames 3224 * but we do not support receiving pause frames). 3225 * 3: Both Rx and TX flow control (symmetric) are enabled. 3226 * other: No software override. The flow control configuration 3227 * in the EEPROM is used. 3228 */ 3229 switch (hw->fc) { 3230 case e1000_fc_none: /* 0 */ 3231 /* Flow control (RX & TX) is completely disabled by a 3232 * software over-ride. 3233 */ 3234 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 3235 break; 3236 case e1000_fc_rx_pause: /* 1 */ 3237 /* RX Flow control is enabled, and TX Flow control is 3238 * disabled, by a software over-ride. 3239 */ 3240 /* Since there really isn't a way to advertise that we are 3241 * capable of RX Pause ONLY, we will advertise that we 3242 * support both symmetric and asymmetric RX PAUSE. Later 3243 * (in e1000_config_fc_after_link_up) we will disable the 3244 *hw's ability to send PAUSE frames. 3245 */ 3246 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 3247 break; 3248 case e1000_fc_tx_pause: /* 2 */ 3249 /* TX Flow control is enabled, and RX Flow control is 3250 * disabled, by a software over-ride. 3251 */ 3252 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR; 3253 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE; 3254 break; 3255 case e1000_fc_full: /* 3 */ 3256 /* Flow control (both RX and TX) is enabled by a software 3257 * over-ride. 3258 */ 3259 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 3260 break; 3261 default: 3262 DEBUGOUT("Flow control param set incorrectly\n"); 3263 return -E1000_ERR_CONFIG; 3264 } 3265 3266 ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg); 3267 if (ret_val) 3268 return ret_val; 3269 3270 DEBUGOUT("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); 3271 3272 if (hw->phy_type != e1000_phy_ife) { 3273 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, 3274 mii_1000t_ctrl_reg); 3275 if (ret_val) 3276 return ret_val; 3277 } 3278 3279 return E1000_SUCCESS; 3280 } 3281 3282 /****************************************************************************** 3283 * Sets the collision distance in the Transmit Control register 3284 * 3285 * hw - Struct containing variables accessed by shared code 3286 * 3287 * Link should have been established previously. Reads the speed and duplex 3288 * information from the Device Status register. 3289 ******************************************************************************/ 3290 static void 3291 e1000_config_collision_dist(struct e1000_hw *hw) 3292 { 3293 uint32_t tctl, coll_dist; 3294 3295 DEBUGFUNC(); 3296 3297 if (hw->mac_type < e1000_82543) 3298 coll_dist = E1000_COLLISION_DISTANCE_82542; 3299 else 3300 coll_dist = E1000_COLLISION_DISTANCE; 3301 3302 tctl = E1000_READ_REG(hw, TCTL); 3303 3304 tctl &= ~E1000_TCTL_COLD; 3305 tctl |= coll_dist << E1000_COLD_SHIFT; 3306 3307 E1000_WRITE_REG(hw, TCTL, tctl); 3308 E1000_WRITE_FLUSH(hw); 3309 } 3310 3311 /****************************************************************************** 3312 * Sets MAC speed and duplex settings to reflect the those in the PHY 3313 * 3314 * hw - Struct containing variables accessed by shared code 3315 * mii_reg - data to write to the MII control register 3316 * 3317 * The contents of the PHY register containing the needed information need to 3318 * be passed in. 3319 ******************************************************************************/ 3320 static int 3321 e1000_config_mac_to_phy(struct e1000_hw *hw) 3322 { 3323 uint32_t ctrl; 3324 uint16_t phy_data; 3325 3326 DEBUGFUNC(); 3327 3328 /* Read the Device Control Register and set the bits to Force Speed 3329 * and Duplex. 3330 */ 3331 ctrl = E1000_READ_REG(hw, CTRL); 3332 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 3333 ctrl &= ~(E1000_CTRL_ILOS); 3334 ctrl |= (E1000_CTRL_SPD_SEL); 3335 3336 /* Set up duplex in the Device Control and Transmit Control 3337 * registers depending on negotiated values. 3338 */ 3339 if (e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data) < 0) { 3340 DEBUGOUT("PHY Read Error\n"); 3341 return -E1000_ERR_PHY; 3342 } 3343 if (phy_data & M88E1000_PSSR_DPLX) 3344 ctrl |= E1000_CTRL_FD; 3345 else 3346 ctrl &= ~E1000_CTRL_FD; 3347 3348 e1000_config_collision_dist(hw); 3349 3350 /* Set up speed in the Device Control register depending on 3351 * negotiated values. 3352 */ 3353 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) 3354 ctrl |= E1000_CTRL_SPD_1000; 3355 else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS) 3356 ctrl |= E1000_CTRL_SPD_100; 3357 /* Write the configured values back to the Device Control Reg. */ 3358 E1000_WRITE_REG(hw, CTRL, ctrl); 3359 return 0; 3360 } 3361 3362 /****************************************************************************** 3363 * Forces the MAC's flow control settings. 3364 * 3365 * hw - Struct containing variables accessed by shared code 3366 * 3367 * Sets the TFCE and RFCE bits in the device control register to reflect 3368 * the adapter settings. TFCE and RFCE need to be explicitly set by 3369 * software when a Copper PHY is used because autonegotiation is managed 3370 * by the PHY rather than the MAC. Software must also configure these 3371 * bits when link is forced on a fiber connection. 3372 *****************************************************************************/ 3373 static int 3374 e1000_force_mac_fc(struct e1000_hw *hw) 3375 { 3376 uint32_t ctrl; 3377 3378 DEBUGFUNC(); 3379 3380 /* Get the current configuration of the Device Control Register */ 3381 ctrl = E1000_READ_REG(hw, CTRL); 3382 3383 /* Because we didn't get link via the internal auto-negotiation 3384 * mechanism (we either forced link or we got link via PHY 3385 * auto-neg), we have to manually enable/disable transmit an 3386 * receive flow control. 3387 * 3388 * The "Case" statement below enables/disable flow control 3389 * according to the "hw->fc" parameter. 3390 * 3391 * The possible values of the "fc" parameter are: 3392 * 0: Flow control is completely disabled 3393 * 1: Rx flow control is enabled (we can receive pause 3394 * frames but not send pause frames). 3395 * 2: Tx flow control is enabled (we can send pause frames 3396 * frames but we do not receive pause frames). 3397 * 3: Both Rx and TX flow control (symmetric) is enabled. 3398 * other: No other values should be possible at this point. 3399 */ 3400 3401 switch (hw->fc) { 3402 case e1000_fc_none: 3403 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE)); 3404 break; 3405 case e1000_fc_rx_pause: 3406 ctrl &= (~E1000_CTRL_TFCE); 3407 ctrl |= E1000_CTRL_RFCE; 3408 break; 3409 case e1000_fc_tx_pause: 3410 ctrl &= (~E1000_CTRL_RFCE); 3411 ctrl |= E1000_CTRL_TFCE; 3412 break; 3413 case e1000_fc_full: 3414 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE); 3415 break; 3416 default: 3417 DEBUGOUT("Flow control param set incorrectly\n"); 3418 return -E1000_ERR_CONFIG; 3419 } 3420 3421 /* Disable TX Flow Control for 82542 (rev 2.0) */ 3422 if (hw->mac_type == e1000_82542_rev2_0) 3423 ctrl &= (~E1000_CTRL_TFCE); 3424 3425 E1000_WRITE_REG(hw, CTRL, ctrl); 3426 return 0; 3427 } 3428 3429 /****************************************************************************** 3430 * Configures flow control settings after link is established 3431 * 3432 * hw - Struct containing variables accessed by shared code 3433 * 3434 * Should be called immediately after a valid link has been established. 3435 * Forces MAC flow control settings if link was forced. When in MII/GMII mode 3436 * and autonegotiation is enabled, the MAC flow control settings will be set 3437 * based on the flow control negotiated by the PHY. In TBI mode, the TFCE 3438 * and RFCE bits will be automaticaly set to the negotiated flow control mode. 3439 *****************************************************************************/ 3440 static int32_t 3441 e1000_config_fc_after_link_up(struct e1000_hw *hw) 3442 { 3443 int32_t ret_val; 3444 uint16_t mii_status_reg; 3445 uint16_t mii_nway_adv_reg; 3446 uint16_t mii_nway_lp_ability_reg; 3447 uint16_t speed; 3448 uint16_t duplex; 3449 3450 DEBUGFUNC(); 3451 3452 /* Check for the case where we have fiber media and auto-neg failed 3453 * so we had to force link. In this case, we need to force the 3454 * configuration of the MAC to match the "fc" parameter. 3455 */ 3456 if (((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed)) 3457 || ((hw->media_type == e1000_media_type_internal_serdes) 3458 && (hw->autoneg_failed)) 3459 || ((hw->media_type == e1000_media_type_copper) 3460 && (!hw->autoneg))) { 3461 ret_val = e1000_force_mac_fc(hw); 3462 if (ret_val < 0) { 3463 DEBUGOUT("Error forcing flow control settings\n"); 3464 return ret_val; 3465 } 3466 } 3467 3468 /* Check for the case where we have copper media and auto-neg is 3469 * enabled. In this case, we need to check and see if Auto-Neg 3470 * has completed, and if so, how the PHY and link partner has 3471 * flow control configured. 3472 */ 3473 if (hw->media_type == e1000_media_type_copper) { 3474 /* Read the MII Status Register and check to see if AutoNeg 3475 * has completed. We read this twice because this reg has 3476 * some "sticky" (latched) bits. 3477 */ 3478 if (e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) { 3479 DEBUGOUT("PHY Read Error \n"); 3480 return -E1000_ERR_PHY; 3481 } 3482 if (e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) { 3483 DEBUGOUT("PHY Read Error \n"); 3484 return -E1000_ERR_PHY; 3485 } 3486 3487 if (mii_status_reg & MII_SR_AUTONEG_COMPLETE) { 3488 /* The AutoNeg process has completed, so we now need to 3489 * read both the Auto Negotiation Advertisement Register 3490 * (Address 4) and the Auto_Negotiation Base Page Ability 3491 * Register (Address 5) to determine how flow control was 3492 * negotiated. 3493 */ 3494 if (e1000_read_phy_reg 3495 (hw, PHY_AUTONEG_ADV, &mii_nway_adv_reg) < 0) { 3496 DEBUGOUT("PHY Read Error\n"); 3497 return -E1000_ERR_PHY; 3498 } 3499 if (e1000_read_phy_reg 3500 (hw, PHY_LP_ABILITY, 3501 &mii_nway_lp_ability_reg) < 0) { 3502 DEBUGOUT("PHY Read Error\n"); 3503 return -E1000_ERR_PHY; 3504 } 3505 3506 /* Two bits in the Auto Negotiation Advertisement Register 3507 * (Address 4) and two bits in the Auto Negotiation Base 3508 * Page Ability Register (Address 5) determine flow control 3509 * for both the PHY and the link partner. The following 3510 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25, 3511 * 1999, describes these PAUSE resolution bits and how flow 3512 * control is determined based upon these settings. 3513 * NOTE: DC = Don't Care 3514 * 3515 * LOCAL DEVICE | LINK PARTNER 3516 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution 3517 *-------|---------|-------|---------|-------------------- 3518 * 0 | 0 | DC | DC | e1000_fc_none 3519 * 0 | 1 | 0 | DC | e1000_fc_none 3520 * 0 | 1 | 1 | 0 | e1000_fc_none 3521 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 3522 * 1 | 0 | 0 | DC | e1000_fc_none 3523 * 1 | DC | 1 | DC | e1000_fc_full 3524 * 1 | 1 | 0 | 0 | e1000_fc_none 3525 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 3526 * 3527 */ 3528 /* Are both PAUSE bits set to 1? If so, this implies 3529 * Symmetric Flow Control is enabled at both ends. The 3530 * ASM_DIR bits are irrelevant per the spec. 3531 * 3532 * For Symmetric Flow Control: 3533 * 3534 * LOCAL DEVICE | LINK PARTNER 3535 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 3536 *-------|---------|-------|---------|-------------------- 3537 * 1 | DC | 1 | DC | e1000_fc_full 3538 * 3539 */ 3540 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 3541 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) { 3542 /* Now we need to check if the user selected RX ONLY 3543 * of pause frames. In this case, we had to advertise 3544 * FULL flow control because we could not advertise RX 3545 * ONLY. Hence, we must now check to see if we need to 3546 * turn OFF the TRANSMISSION of PAUSE frames. 3547 */ 3548 if (hw->original_fc == e1000_fc_full) { 3549 hw->fc = e1000_fc_full; 3550 DEBUGOUT("Flow Control = FULL.\r\n"); 3551 } else { 3552 hw->fc = e1000_fc_rx_pause; 3553 DEBUGOUT 3554 ("Flow Control = RX PAUSE frames only.\r\n"); 3555 } 3556 } 3557 /* For receiving PAUSE frames ONLY. 3558 * 3559 * LOCAL DEVICE | LINK PARTNER 3560 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 3561 *-------|---------|-------|---------|-------------------- 3562 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 3563 * 3564 */ 3565 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) && 3566 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 3567 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 3568 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) 3569 { 3570 hw->fc = e1000_fc_tx_pause; 3571 DEBUGOUT 3572 ("Flow Control = TX PAUSE frames only.\r\n"); 3573 } 3574 /* For transmitting PAUSE frames ONLY. 3575 * 3576 * LOCAL DEVICE | LINK PARTNER 3577 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 3578 *-------|---------|-------|---------|-------------------- 3579 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 3580 * 3581 */ 3582 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 3583 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 3584 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 3585 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) 3586 { 3587 hw->fc = e1000_fc_rx_pause; 3588 DEBUGOUT 3589 ("Flow Control = RX PAUSE frames only.\r\n"); 3590 } 3591 /* Per the IEEE spec, at this point flow control should be 3592 * disabled. However, we want to consider that we could 3593 * be connected to a legacy switch that doesn't advertise 3594 * desired flow control, but can be forced on the link 3595 * partner. So if we advertised no flow control, that is 3596 * what we will resolve to. If we advertised some kind of 3597 * receive capability (Rx Pause Only or Full Flow Control) 3598 * and the link partner advertised none, we will configure 3599 * ourselves to enable Rx Flow Control only. We can do 3600 * this safely for two reasons: If the link partner really 3601 * didn't want flow control enabled, and we enable Rx, no 3602 * harm done since we won't be receiving any PAUSE frames 3603 * anyway. If the intent on the link partner was to have 3604 * flow control enabled, then by us enabling RX only, we 3605 * can at least receive pause frames and process them. 3606 * This is a good idea because in most cases, since we are 3607 * predominantly a server NIC, more times than not we will 3608 * be asked to delay transmission of packets than asking 3609 * our link partner to pause transmission of frames. 3610 */ 3611 else if (hw->original_fc == e1000_fc_none || 3612 hw->original_fc == e1000_fc_tx_pause) { 3613 hw->fc = e1000_fc_none; 3614 DEBUGOUT("Flow Control = NONE.\r\n"); 3615 } else { 3616 hw->fc = e1000_fc_rx_pause; 3617 DEBUGOUT 3618 ("Flow Control = RX PAUSE frames only.\r\n"); 3619 } 3620 3621 /* Now we need to do one last check... If we auto- 3622 * negotiated to HALF DUPLEX, flow control should not be 3623 * enabled per IEEE 802.3 spec. 3624 */ 3625 e1000_get_speed_and_duplex(hw, &speed, &duplex); 3626 3627 if (duplex == HALF_DUPLEX) 3628 hw->fc = e1000_fc_none; 3629 3630 /* Now we call a subroutine to actually force the MAC 3631 * controller to use the correct flow control settings. 3632 */ 3633 ret_val = e1000_force_mac_fc(hw); 3634 if (ret_val < 0) { 3635 DEBUGOUT 3636 ("Error forcing flow control settings\n"); 3637 return ret_val; 3638 } 3639 } else { 3640 DEBUGOUT 3641 ("Copper PHY and Auto Neg has not completed.\r\n"); 3642 } 3643 } 3644 return E1000_SUCCESS; 3645 } 3646 3647 /****************************************************************************** 3648 * Checks to see if the link status of the hardware has changed. 3649 * 3650 * hw - Struct containing variables accessed by shared code 3651 * 3652 * Called by any function that needs to check the link status of the adapter. 3653 *****************************************************************************/ 3654 static int 3655 e1000_check_for_link(struct eth_device *nic) 3656 { 3657 struct e1000_hw *hw = nic->priv; 3658 uint32_t rxcw; 3659 uint32_t ctrl; 3660 uint32_t status; 3661 uint32_t rctl; 3662 uint32_t signal; 3663 int32_t ret_val; 3664 uint16_t phy_data; 3665 uint16_t lp_capability; 3666 3667 DEBUGFUNC(); 3668 3669 /* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be 3670 * set when the optics detect a signal. On older adapters, it will be 3671 * cleared when there is a signal 3672 */ 3673 ctrl = E1000_READ_REG(hw, CTRL); 3674 if ((hw->mac_type > e1000_82544) && !(ctrl & E1000_CTRL_ILOS)) 3675 signal = E1000_CTRL_SWDPIN1; 3676 else 3677 signal = 0; 3678 3679 status = E1000_READ_REG(hw, STATUS); 3680 rxcw = E1000_READ_REG(hw, RXCW); 3681 DEBUGOUT("ctrl: %#08x status %#08x rxcw %#08x\n", ctrl, status, rxcw); 3682 3683 /* If we have a copper PHY then we only want to go out to the PHY 3684 * registers to see if Auto-Neg has completed and/or if our link 3685 * status has changed. The get_link_status flag will be set if we 3686 * receive a Link Status Change interrupt or we have Rx Sequence 3687 * Errors. 3688 */ 3689 if ((hw->media_type == e1000_media_type_copper) && hw->get_link_status) { 3690 /* First we want to see if the MII Status Register reports 3691 * link. If so, then we want to get the current speed/duplex 3692 * of the PHY. 3693 * Read the register twice since the link bit is sticky. 3694 */ 3695 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) { 3696 DEBUGOUT("PHY Read Error\n"); 3697 return -E1000_ERR_PHY; 3698 } 3699 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) { 3700 DEBUGOUT("PHY Read Error\n"); 3701 return -E1000_ERR_PHY; 3702 } 3703 3704 if (phy_data & MII_SR_LINK_STATUS) { 3705 hw->get_link_status = false; 3706 } else { 3707 /* No link detected */ 3708 return -E1000_ERR_NOLINK; 3709 } 3710 3711 /* We have a M88E1000 PHY and Auto-Neg is enabled. If we 3712 * have Si on board that is 82544 or newer, Auto 3713 * Speed Detection takes care of MAC speed/duplex 3714 * configuration. So we only need to configure Collision 3715 * Distance in the MAC. Otherwise, we need to force 3716 * speed/duplex on the MAC to the current PHY speed/duplex 3717 * settings. 3718 */ 3719 if (hw->mac_type >= e1000_82544) 3720 e1000_config_collision_dist(hw); 3721 else { 3722 ret_val = e1000_config_mac_to_phy(hw); 3723 if (ret_val < 0) { 3724 DEBUGOUT 3725 ("Error configuring MAC to PHY settings\n"); 3726 return ret_val; 3727 } 3728 } 3729 3730 /* Configure Flow Control now that Auto-Neg has completed. First, we 3731 * need to restore the desired flow control settings because we may 3732 * have had to re-autoneg with a different link partner. 3733 */ 3734 ret_val = e1000_config_fc_after_link_up(hw); 3735 if (ret_val < 0) { 3736 DEBUGOUT("Error configuring flow control\n"); 3737 return ret_val; 3738 } 3739 3740 /* At this point we know that we are on copper and we have 3741 * auto-negotiated link. These are conditions for checking the link 3742 * parter capability register. We use the link partner capability to 3743 * determine if TBI Compatibility needs to be turned on or off. If 3744 * the link partner advertises any speed in addition to Gigabit, then 3745 * we assume that they are GMII-based, and TBI compatibility is not 3746 * needed. If no other speeds are advertised, we assume the link 3747 * partner is TBI-based, and we turn on TBI Compatibility. 3748 */ 3749 if (hw->tbi_compatibility_en) { 3750 if (e1000_read_phy_reg 3751 (hw, PHY_LP_ABILITY, &lp_capability) < 0) { 3752 DEBUGOUT("PHY Read Error\n"); 3753 return -E1000_ERR_PHY; 3754 } 3755 if (lp_capability & (NWAY_LPAR_10T_HD_CAPS | 3756 NWAY_LPAR_10T_FD_CAPS | 3757 NWAY_LPAR_100TX_HD_CAPS | 3758 NWAY_LPAR_100TX_FD_CAPS | 3759 NWAY_LPAR_100T4_CAPS)) { 3760 /* If our link partner advertises anything in addition to 3761 * gigabit, we do not need to enable TBI compatibility. 3762 */ 3763 if (hw->tbi_compatibility_on) { 3764 /* If we previously were in the mode, turn it off. */ 3765 rctl = E1000_READ_REG(hw, RCTL); 3766 rctl &= ~E1000_RCTL_SBP; 3767 E1000_WRITE_REG(hw, RCTL, rctl); 3768 hw->tbi_compatibility_on = false; 3769 } 3770 } else { 3771 /* If TBI compatibility is was previously off, turn it on. For 3772 * compatibility with a TBI link partner, we will store bad 3773 * packets. Some frames have an additional byte on the end and 3774 * will look like CRC errors to to the hardware. 3775 */ 3776 if (!hw->tbi_compatibility_on) { 3777 hw->tbi_compatibility_on = true; 3778 rctl = E1000_READ_REG(hw, RCTL); 3779 rctl |= E1000_RCTL_SBP; 3780 E1000_WRITE_REG(hw, RCTL, rctl); 3781 } 3782 } 3783 } 3784 } 3785 /* If we don't have link (auto-negotiation failed or link partner cannot 3786 * auto-negotiate), the cable is plugged in (we have signal), and our 3787 * link partner is not trying to auto-negotiate with us (we are receiving 3788 * idles or data), we need to force link up. We also need to give 3789 * auto-negotiation time to complete, in case the cable was just plugged 3790 * in. The autoneg_failed flag does this. 3791 */ 3792 else if ((hw->media_type == e1000_media_type_fiber) && 3793 (!(status & E1000_STATUS_LU)) && 3794 ((ctrl & E1000_CTRL_SWDPIN1) == signal) && 3795 (!(rxcw & E1000_RXCW_C))) { 3796 if (hw->autoneg_failed == 0) { 3797 hw->autoneg_failed = 1; 3798 return 0; 3799 } 3800 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\r\n"); 3801 3802 /* Disable auto-negotiation in the TXCW register */ 3803 E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE)); 3804 3805 /* Force link-up and also force full-duplex. */ 3806 ctrl = E1000_READ_REG(hw, CTRL); 3807 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 3808 E1000_WRITE_REG(hw, CTRL, ctrl); 3809 3810 /* Configure Flow Control after forcing link up. */ 3811 ret_val = e1000_config_fc_after_link_up(hw); 3812 if (ret_val < 0) { 3813 DEBUGOUT("Error configuring flow control\n"); 3814 return ret_val; 3815 } 3816 } 3817 /* If we are forcing link and we are receiving /C/ ordered sets, re-enable 3818 * auto-negotiation in the TXCW register and disable forced link in the 3819 * Device Control register in an attempt to auto-negotiate with our link 3820 * partner. 3821 */ 3822 else if ((hw->media_type == e1000_media_type_fiber) && 3823 (ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { 3824 DEBUGOUT 3825 ("RXing /C/, enable AutoNeg and stop forcing link.\r\n"); 3826 E1000_WRITE_REG(hw, TXCW, hw->txcw); 3827 E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU)); 3828 } 3829 return 0; 3830 } 3831 3832 /****************************************************************************** 3833 * Configure the MAC-to-PHY interface for 10/100Mbps 3834 * 3835 * hw - Struct containing variables accessed by shared code 3836 ******************************************************************************/ 3837 static int32_t 3838 e1000_configure_kmrn_for_10_100(struct e1000_hw *hw, uint16_t duplex) 3839 { 3840 int32_t ret_val = E1000_SUCCESS; 3841 uint32_t tipg; 3842 uint16_t reg_data; 3843 3844 DEBUGFUNC(); 3845 3846 reg_data = E1000_KUMCTRLSTA_HD_CTRL_10_100_DEFAULT; 3847 ret_val = e1000_write_kmrn_reg(hw, 3848 E1000_KUMCTRLSTA_OFFSET_HD_CTRL, reg_data); 3849 if (ret_val) 3850 return ret_val; 3851 3852 /* Configure Transmit Inter-Packet Gap */ 3853 tipg = E1000_READ_REG(hw, TIPG); 3854 tipg &= ~E1000_TIPG_IPGT_MASK; 3855 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_10_100; 3856 E1000_WRITE_REG(hw, TIPG, tipg); 3857 3858 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data); 3859 3860 if (ret_val) 3861 return ret_val; 3862 3863 if (duplex == HALF_DUPLEX) 3864 reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER; 3865 else 3866 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; 3867 3868 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data); 3869 3870 return ret_val; 3871 } 3872 3873 static int32_t 3874 e1000_configure_kmrn_for_1000(struct e1000_hw *hw) 3875 { 3876 int32_t ret_val = E1000_SUCCESS; 3877 uint16_t reg_data; 3878 uint32_t tipg; 3879 3880 DEBUGFUNC(); 3881 3882 reg_data = E1000_KUMCTRLSTA_HD_CTRL_1000_DEFAULT; 3883 ret_val = e1000_write_kmrn_reg(hw, 3884 E1000_KUMCTRLSTA_OFFSET_HD_CTRL, reg_data); 3885 if (ret_val) 3886 return ret_val; 3887 3888 /* Configure Transmit Inter-Packet Gap */ 3889 tipg = E1000_READ_REG(hw, TIPG); 3890 tipg &= ~E1000_TIPG_IPGT_MASK; 3891 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000; 3892 E1000_WRITE_REG(hw, TIPG, tipg); 3893 3894 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data); 3895 3896 if (ret_val) 3897 return ret_val; 3898 3899 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; 3900 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data); 3901 3902 return ret_val; 3903 } 3904 3905 /****************************************************************************** 3906 * Detects the current speed and duplex settings of the hardware. 3907 * 3908 * hw - Struct containing variables accessed by shared code 3909 * speed - Speed of the connection 3910 * duplex - Duplex setting of the connection 3911 *****************************************************************************/ 3912 static int 3913 e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t *speed, 3914 uint16_t *duplex) 3915 { 3916 uint32_t status; 3917 int32_t ret_val; 3918 uint16_t phy_data; 3919 3920 DEBUGFUNC(); 3921 3922 if (hw->mac_type >= e1000_82543) { 3923 status = E1000_READ_REG(hw, STATUS); 3924 if (status & E1000_STATUS_SPEED_1000) { 3925 *speed = SPEED_1000; 3926 DEBUGOUT("1000 Mbs, "); 3927 } else if (status & E1000_STATUS_SPEED_100) { 3928 *speed = SPEED_100; 3929 DEBUGOUT("100 Mbs, "); 3930 } else { 3931 *speed = SPEED_10; 3932 DEBUGOUT("10 Mbs, "); 3933 } 3934 3935 if (status & E1000_STATUS_FD) { 3936 *duplex = FULL_DUPLEX; 3937 DEBUGOUT("Full Duplex\r\n"); 3938 } else { 3939 *duplex = HALF_DUPLEX; 3940 DEBUGOUT(" Half Duplex\r\n"); 3941 } 3942 } else { 3943 DEBUGOUT("1000 Mbs, Full Duplex\r\n"); 3944 *speed = SPEED_1000; 3945 *duplex = FULL_DUPLEX; 3946 } 3947 3948 /* IGP01 PHY may advertise full duplex operation after speed downgrade 3949 * even if it is operating at half duplex. Here we set the duplex 3950 * settings to match the duplex in the link partner's capabilities. 3951 */ 3952 if (hw->phy_type == e1000_phy_igp && hw->speed_downgraded) { 3953 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data); 3954 if (ret_val) 3955 return ret_val; 3956 3957 if (!(phy_data & NWAY_ER_LP_NWAY_CAPS)) 3958 *duplex = HALF_DUPLEX; 3959 else { 3960 ret_val = e1000_read_phy_reg(hw, 3961 PHY_LP_ABILITY, &phy_data); 3962 if (ret_val) 3963 return ret_val; 3964 if ((*speed == SPEED_100 && 3965 !(phy_data & NWAY_LPAR_100TX_FD_CAPS)) 3966 || (*speed == SPEED_10 3967 && !(phy_data & NWAY_LPAR_10T_FD_CAPS))) 3968 *duplex = HALF_DUPLEX; 3969 } 3970 } 3971 3972 if ((hw->mac_type == e1000_80003es2lan) && 3973 (hw->media_type == e1000_media_type_copper)) { 3974 if (*speed == SPEED_1000) 3975 ret_val = e1000_configure_kmrn_for_1000(hw); 3976 else 3977 ret_val = e1000_configure_kmrn_for_10_100(hw, *duplex); 3978 if (ret_val) 3979 return ret_val; 3980 } 3981 return E1000_SUCCESS; 3982 } 3983 3984 /****************************************************************************** 3985 * Blocks until autoneg completes or times out (~4.5 seconds) 3986 * 3987 * hw - Struct containing variables accessed by shared code 3988 ******************************************************************************/ 3989 static int 3990 e1000_wait_autoneg(struct e1000_hw *hw) 3991 { 3992 uint16_t i; 3993 uint16_t phy_data; 3994 3995 DEBUGFUNC(); 3996 DEBUGOUT("Waiting for Auto-Neg to complete.\n"); 3997 3998 /* We will wait for autoneg to complete or 4.5 seconds to expire. */ 3999 for (i = PHY_AUTO_NEG_TIME; i > 0; i--) { 4000 /* Read the MII Status Register and wait for Auto-Neg 4001 * Complete bit to be set. 4002 */ 4003 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) { 4004 DEBUGOUT("PHY Read Error\n"); 4005 return -E1000_ERR_PHY; 4006 } 4007 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) { 4008 DEBUGOUT("PHY Read Error\n"); 4009 return -E1000_ERR_PHY; 4010 } 4011 if (phy_data & MII_SR_AUTONEG_COMPLETE) { 4012 DEBUGOUT("Auto-Neg complete.\n"); 4013 return 0; 4014 } 4015 mdelay(100); 4016 } 4017 DEBUGOUT("Auto-Neg timedout.\n"); 4018 return -E1000_ERR_TIMEOUT; 4019 } 4020 4021 /****************************************************************************** 4022 * Raises the Management Data Clock 4023 * 4024 * hw - Struct containing variables accessed by shared code 4025 * ctrl - Device control register's current value 4026 ******************************************************************************/ 4027 static void 4028 e1000_raise_mdi_clk(struct e1000_hw *hw, uint32_t * ctrl) 4029 { 4030 /* Raise the clock input to the Management Data Clock (by setting the MDC 4031 * bit), and then delay 2 microseconds. 4032 */ 4033 E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC)); 4034 E1000_WRITE_FLUSH(hw); 4035 udelay(2); 4036 } 4037 4038 /****************************************************************************** 4039 * Lowers the Management Data Clock 4040 * 4041 * hw - Struct containing variables accessed by shared code 4042 * ctrl - Device control register's current value 4043 ******************************************************************************/ 4044 static void 4045 e1000_lower_mdi_clk(struct e1000_hw *hw, uint32_t * ctrl) 4046 { 4047 /* Lower the clock input to the Management Data Clock (by clearing the MDC 4048 * bit), and then delay 2 microseconds. 4049 */ 4050 E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC)); 4051 E1000_WRITE_FLUSH(hw); 4052 udelay(2); 4053 } 4054 4055 /****************************************************************************** 4056 * Shifts data bits out to the PHY 4057 * 4058 * hw - Struct containing variables accessed by shared code 4059 * data - Data to send out to the PHY 4060 * count - Number of bits to shift out 4061 * 4062 * Bits are shifted out in MSB to LSB order. 4063 ******************************************************************************/ 4064 static void 4065 e1000_shift_out_mdi_bits(struct e1000_hw *hw, uint32_t data, uint16_t count) 4066 { 4067 uint32_t ctrl; 4068 uint32_t mask; 4069 4070 /* We need to shift "count" number of bits out to the PHY. So, the value 4071 * in the "data" parameter will be shifted out to the PHY one bit at a 4072 * time. In order to do this, "data" must be broken down into bits. 4073 */ 4074 mask = 0x01; 4075 mask <<= (count - 1); 4076 4077 ctrl = E1000_READ_REG(hw, CTRL); 4078 4079 /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */ 4080 ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR); 4081 4082 while (mask) { 4083 /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and 4084 * then raising and lowering the Management Data Clock. A "0" is 4085 * shifted out to the PHY by setting the MDIO bit to "0" and then 4086 * raising and lowering the clock. 4087 */ 4088 if (data & mask) 4089 ctrl |= E1000_CTRL_MDIO; 4090 else 4091 ctrl &= ~E1000_CTRL_MDIO; 4092 4093 E1000_WRITE_REG(hw, CTRL, ctrl); 4094 E1000_WRITE_FLUSH(hw); 4095 4096 udelay(2); 4097 4098 e1000_raise_mdi_clk(hw, &ctrl); 4099 e1000_lower_mdi_clk(hw, &ctrl); 4100 4101 mask = mask >> 1; 4102 } 4103 } 4104 4105 /****************************************************************************** 4106 * Shifts data bits in from the PHY 4107 * 4108 * hw - Struct containing variables accessed by shared code 4109 * 4110 * Bits are shifted in in MSB to LSB order. 4111 ******************************************************************************/ 4112 static uint16_t 4113 e1000_shift_in_mdi_bits(struct e1000_hw *hw) 4114 { 4115 uint32_t ctrl; 4116 uint16_t data = 0; 4117 uint8_t i; 4118 4119 /* In order to read a register from the PHY, we need to shift in a total 4120 * of 18 bits from the PHY. The first two bit (turnaround) times are used 4121 * to avoid contention on the MDIO pin when a read operation is performed. 4122 * These two bits are ignored by us and thrown away. Bits are "shifted in" 4123 * by raising the input to the Management Data Clock (setting the MDC bit), 4124 * and then reading the value of the MDIO bit. 4125 */ 4126 ctrl = E1000_READ_REG(hw, CTRL); 4127 4128 /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */ 4129 ctrl &= ~E1000_CTRL_MDIO_DIR; 4130 ctrl &= ~E1000_CTRL_MDIO; 4131 4132 E1000_WRITE_REG(hw, CTRL, ctrl); 4133 E1000_WRITE_FLUSH(hw); 4134 4135 /* Raise and Lower the clock before reading in the data. This accounts for 4136 * the turnaround bits. The first clock occurred when we clocked out the 4137 * last bit of the Register Address. 4138 */ 4139 e1000_raise_mdi_clk(hw, &ctrl); 4140 e1000_lower_mdi_clk(hw, &ctrl); 4141 4142 for (data = 0, i = 0; i < 16; i++) { 4143 data = data << 1; 4144 e1000_raise_mdi_clk(hw, &ctrl); 4145 ctrl = E1000_READ_REG(hw, CTRL); 4146 /* Check to see if we shifted in a "1". */ 4147 if (ctrl & E1000_CTRL_MDIO) 4148 data |= 1; 4149 e1000_lower_mdi_clk(hw, &ctrl); 4150 } 4151 4152 e1000_raise_mdi_clk(hw, &ctrl); 4153 e1000_lower_mdi_clk(hw, &ctrl); 4154 4155 return data; 4156 } 4157 4158 /***************************************************************************** 4159 * Reads the value from a PHY register 4160 * 4161 * hw - Struct containing variables accessed by shared code 4162 * reg_addr - address of the PHY register to read 4163 ******************************************************************************/ 4164 static int 4165 e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t * phy_data) 4166 { 4167 uint32_t i; 4168 uint32_t mdic = 0; 4169 const uint32_t phy_addr = 1; 4170 4171 if (reg_addr > MAX_PHY_REG_ADDRESS) { 4172 DEBUGOUT("PHY Address %d is out of range\n", reg_addr); 4173 return -E1000_ERR_PARAM; 4174 } 4175 4176 if (hw->mac_type > e1000_82543) { 4177 /* Set up Op-code, Phy Address, and register address in the MDI 4178 * Control register. The MAC will take care of interfacing with the 4179 * PHY to retrieve the desired data. 4180 */ 4181 mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) | 4182 (phy_addr << E1000_MDIC_PHY_SHIFT) | 4183 (E1000_MDIC_OP_READ)); 4184 4185 E1000_WRITE_REG(hw, MDIC, mdic); 4186 4187 /* Poll the ready bit to see if the MDI read completed */ 4188 for (i = 0; i < 64; i++) { 4189 udelay(10); 4190 mdic = E1000_READ_REG(hw, MDIC); 4191 if (mdic & E1000_MDIC_READY) 4192 break; 4193 } 4194 if (!(mdic & E1000_MDIC_READY)) { 4195 DEBUGOUT("MDI Read did not complete\n"); 4196 return -E1000_ERR_PHY; 4197 } 4198 if (mdic & E1000_MDIC_ERROR) { 4199 DEBUGOUT("MDI Error\n"); 4200 return -E1000_ERR_PHY; 4201 } 4202 *phy_data = (uint16_t) mdic; 4203 } else { 4204 /* We must first send a preamble through the MDIO pin to signal the 4205 * beginning of an MII instruction. This is done by sending 32 4206 * consecutive "1" bits. 4207 */ 4208 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); 4209 4210 /* Now combine the next few fields that are required for a read 4211 * operation. We use this method instead of calling the 4212 * e1000_shift_out_mdi_bits routine five different times. The format of 4213 * a MII read instruction consists of a shift out of 14 bits and is 4214 * defined as follows: 4215 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr> 4216 * followed by a shift in of 18 bits. This first two bits shifted in 4217 * are TurnAround bits used to avoid contention on the MDIO pin when a 4218 * READ operation is performed. These two bits are thrown away 4219 * followed by a shift in of 16 bits which contains the desired data. 4220 */ 4221 mdic = ((reg_addr) | (phy_addr << 5) | 4222 (PHY_OP_READ << 10) | (PHY_SOF << 12)); 4223 4224 e1000_shift_out_mdi_bits(hw, mdic, 14); 4225 4226 /* Now that we've shifted out the read command to the MII, we need to 4227 * "shift in" the 16-bit value (18 total bits) of the requested PHY 4228 * register address. 4229 */ 4230 *phy_data = e1000_shift_in_mdi_bits(hw); 4231 } 4232 return 0; 4233 } 4234 4235 /****************************************************************************** 4236 * Writes a value to a PHY register 4237 * 4238 * hw - Struct containing variables accessed by shared code 4239 * reg_addr - address of the PHY register to write 4240 * data - data to write to the PHY 4241 ******************************************************************************/ 4242 static int 4243 e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t phy_data) 4244 { 4245 uint32_t i; 4246 uint32_t mdic = 0; 4247 const uint32_t phy_addr = 1; 4248 4249 if (reg_addr > MAX_PHY_REG_ADDRESS) { 4250 DEBUGOUT("PHY Address %d is out of range\n", reg_addr); 4251 return -E1000_ERR_PARAM; 4252 } 4253 4254 if (hw->mac_type > e1000_82543) { 4255 /* Set up Op-code, Phy Address, register address, and data intended 4256 * for the PHY register in the MDI Control register. The MAC will take 4257 * care of interfacing with the PHY to send the desired data. 4258 */ 4259 mdic = (((uint32_t) phy_data) | 4260 (reg_addr << E1000_MDIC_REG_SHIFT) | 4261 (phy_addr << E1000_MDIC_PHY_SHIFT) | 4262 (E1000_MDIC_OP_WRITE)); 4263 4264 E1000_WRITE_REG(hw, MDIC, mdic); 4265 4266 /* Poll the ready bit to see if the MDI read completed */ 4267 for (i = 0; i < 64; i++) { 4268 udelay(10); 4269 mdic = E1000_READ_REG(hw, MDIC); 4270 if (mdic & E1000_MDIC_READY) 4271 break; 4272 } 4273 if (!(mdic & E1000_MDIC_READY)) { 4274 DEBUGOUT("MDI Write did not complete\n"); 4275 return -E1000_ERR_PHY; 4276 } 4277 } else { 4278 /* We'll need to use the SW defined pins to shift the write command 4279 * out to the PHY. We first send a preamble to the PHY to signal the 4280 * beginning of the MII instruction. This is done by sending 32 4281 * consecutive "1" bits. 4282 */ 4283 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); 4284 4285 /* Now combine the remaining required fields that will indicate a 4286 * write operation. We use this method instead of calling the 4287 * e1000_shift_out_mdi_bits routine for each field in the command. The 4288 * format of a MII write instruction is as follows: 4289 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>. 4290 */ 4291 mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) | 4292 (PHY_OP_WRITE << 12) | (PHY_SOF << 14)); 4293 mdic <<= 16; 4294 mdic |= (uint32_t) phy_data; 4295 4296 e1000_shift_out_mdi_bits(hw, mdic, 32); 4297 } 4298 return 0; 4299 } 4300 4301 /****************************************************************************** 4302 * Checks if PHY reset is blocked due to SOL/IDER session, for example. 4303 * Returning E1000_BLK_PHY_RESET isn't necessarily an error. But it's up to 4304 * the caller to figure out how to deal with it. 4305 * 4306 * hw - Struct containing variables accessed by shared code 4307 * 4308 * returns: - E1000_BLK_PHY_RESET 4309 * E1000_SUCCESS 4310 * 4311 *****************************************************************************/ 4312 int32_t 4313 e1000_check_phy_reset_block(struct e1000_hw *hw) 4314 { 4315 uint32_t manc = 0; 4316 uint32_t fwsm = 0; 4317 4318 if (hw->mac_type == e1000_ich8lan) { 4319 fwsm = E1000_READ_REG(hw, FWSM); 4320 return (fwsm & E1000_FWSM_RSPCIPHY) ? E1000_SUCCESS 4321 : E1000_BLK_PHY_RESET; 4322 } 4323 4324 if (hw->mac_type > e1000_82547_rev_2) 4325 manc = E1000_READ_REG(hw, MANC); 4326 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ? 4327 E1000_BLK_PHY_RESET : E1000_SUCCESS; 4328 } 4329 4330 /*************************************************************************** 4331 * Checks if the PHY configuration is done 4332 * 4333 * hw: Struct containing variables accessed by shared code 4334 * 4335 * returns: - E1000_ERR_RESET if fail to reset MAC 4336 * E1000_SUCCESS at any other case. 4337 * 4338 ***************************************************************************/ 4339 static int32_t 4340 e1000_get_phy_cfg_done(struct e1000_hw *hw) 4341 { 4342 int32_t timeout = PHY_CFG_TIMEOUT; 4343 uint32_t cfg_mask = E1000_EEPROM_CFG_DONE; 4344 4345 DEBUGFUNC(); 4346 4347 switch (hw->mac_type) { 4348 default: 4349 mdelay(10); 4350 break; 4351 4352 case e1000_80003es2lan: 4353 /* Separate *_CFG_DONE_* bit for each port */ 4354 if (e1000_is_second_port(hw)) 4355 cfg_mask = E1000_EEPROM_CFG_DONE_PORT_1; 4356 /* Fall Through */ 4357 4358 case e1000_82571: 4359 case e1000_82572: 4360 case e1000_igb: 4361 while (timeout) { 4362 if (hw->mac_type == e1000_igb) { 4363 if (E1000_READ_REG(hw, I210_EEMNGCTL) & cfg_mask) 4364 break; 4365 } else { 4366 if (E1000_READ_REG(hw, EEMNGCTL) & cfg_mask) 4367 break; 4368 } 4369 mdelay(1); 4370 timeout--; 4371 } 4372 if (!timeout) { 4373 DEBUGOUT("MNG configuration cycle has not " 4374 "completed.\n"); 4375 return -E1000_ERR_RESET; 4376 } 4377 break; 4378 } 4379 4380 return E1000_SUCCESS; 4381 } 4382 4383 /****************************************************************************** 4384 * Returns the PHY to the power-on reset state 4385 * 4386 * hw - Struct containing variables accessed by shared code 4387 ******************************************************************************/ 4388 int32_t 4389 e1000_phy_hw_reset(struct e1000_hw *hw) 4390 { 4391 uint16_t swfw = E1000_SWFW_PHY0_SM; 4392 uint32_t ctrl, ctrl_ext; 4393 uint32_t led_ctrl; 4394 int32_t ret_val; 4395 4396 DEBUGFUNC(); 4397 4398 /* In the case of the phy reset being blocked, it's not an error, we 4399 * simply return success without performing the reset. */ 4400 ret_val = e1000_check_phy_reset_block(hw); 4401 if (ret_val) 4402 return E1000_SUCCESS; 4403 4404 DEBUGOUT("Resetting Phy...\n"); 4405 4406 if (hw->mac_type > e1000_82543) { 4407 if (e1000_is_second_port(hw)) 4408 swfw = E1000_SWFW_PHY1_SM; 4409 4410 if (e1000_swfw_sync_acquire(hw, swfw)) { 4411 DEBUGOUT("Unable to acquire swfw sync\n"); 4412 return -E1000_ERR_SWFW_SYNC; 4413 } 4414 4415 /* Read the device control register and assert the E1000_CTRL_PHY_RST 4416 * bit. Then, take it out of reset. 4417 */ 4418 ctrl = E1000_READ_REG(hw, CTRL); 4419 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST); 4420 E1000_WRITE_FLUSH(hw); 4421 4422 if (hw->mac_type < e1000_82571) 4423 udelay(10); 4424 else 4425 udelay(100); 4426 4427 E1000_WRITE_REG(hw, CTRL, ctrl); 4428 E1000_WRITE_FLUSH(hw); 4429 4430 if (hw->mac_type >= e1000_82571) 4431 mdelay(10); 4432 4433 } else { 4434 /* Read the Extended Device Control Register, assert the PHY_RESET_DIR 4435 * bit to put the PHY into reset. Then, take it out of reset. 4436 */ 4437 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 4438 ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR; 4439 ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA; 4440 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 4441 E1000_WRITE_FLUSH(hw); 4442 mdelay(10); 4443 ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA; 4444 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 4445 E1000_WRITE_FLUSH(hw); 4446 } 4447 udelay(150); 4448 4449 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { 4450 /* Configure activity LED after PHY reset */ 4451 led_ctrl = E1000_READ_REG(hw, LEDCTL); 4452 led_ctrl &= IGP_ACTIVITY_LED_MASK; 4453 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); 4454 E1000_WRITE_REG(hw, LEDCTL, led_ctrl); 4455 } 4456 4457 /* Wait for FW to finish PHY configuration. */ 4458 ret_val = e1000_get_phy_cfg_done(hw); 4459 if (ret_val != E1000_SUCCESS) 4460 return ret_val; 4461 4462 return ret_val; 4463 } 4464 4465 /****************************************************************************** 4466 * IGP phy init script - initializes the GbE PHY 4467 * 4468 * hw - Struct containing variables accessed by shared code 4469 *****************************************************************************/ 4470 static void 4471 e1000_phy_init_script(struct e1000_hw *hw) 4472 { 4473 uint32_t ret_val; 4474 uint16_t phy_saved_data; 4475 DEBUGFUNC(); 4476 4477 if (hw->phy_init_script) { 4478 mdelay(20); 4479 4480 /* Save off the current value of register 0x2F5B to be 4481 * restored at the end of this routine. */ 4482 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data); 4483 4484 /* Disabled the PHY transmitter */ 4485 e1000_write_phy_reg(hw, 0x2F5B, 0x0003); 4486 4487 mdelay(20); 4488 4489 e1000_write_phy_reg(hw, 0x0000, 0x0140); 4490 4491 mdelay(5); 4492 4493 switch (hw->mac_type) { 4494 case e1000_82541: 4495 case e1000_82547: 4496 e1000_write_phy_reg(hw, 0x1F95, 0x0001); 4497 4498 e1000_write_phy_reg(hw, 0x1F71, 0xBD21); 4499 4500 e1000_write_phy_reg(hw, 0x1F79, 0x0018); 4501 4502 e1000_write_phy_reg(hw, 0x1F30, 0x1600); 4503 4504 e1000_write_phy_reg(hw, 0x1F31, 0x0014); 4505 4506 e1000_write_phy_reg(hw, 0x1F32, 0x161C); 4507 4508 e1000_write_phy_reg(hw, 0x1F94, 0x0003); 4509 4510 e1000_write_phy_reg(hw, 0x1F96, 0x003F); 4511 4512 e1000_write_phy_reg(hw, 0x2010, 0x0008); 4513 break; 4514 4515 case e1000_82541_rev_2: 4516 case e1000_82547_rev_2: 4517 e1000_write_phy_reg(hw, 0x1F73, 0x0099); 4518 break; 4519 default: 4520 break; 4521 } 4522 4523 e1000_write_phy_reg(hw, 0x0000, 0x3300); 4524 4525 mdelay(20); 4526 4527 /* Now enable the transmitter */ 4528 if (!ret_val) 4529 e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data); 4530 4531 if (hw->mac_type == e1000_82547) { 4532 uint16_t fused, fine, coarse; 4533 4534 /* Move to analog registers page */ 4535 e1000_read_phy_reg(hw, 4536 IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused); 4537 4538 if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) { 4539 e1000_read_phy_reg(hw, 4540 IGP01E1000_ANALOG_FUSE_STATUS, &fused); 4541 4542 fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK; 4543 coarse = fused 4544 & IGP01E1000_ANALOG_FUSE_COARSE_MASK; 4545 4546 if (coarse > 4547 IGP01E1000_ANALOG_FUSE_COARSE_THRESH) { 4548 coarse -= 4549 IGP01E1000_ANALOG_FUSE_COARSE_10; 4550 fine -= IGP01E1000_ANALOG_FUSE_FINE_1; 4551 } else if (coarse 4552 == IGP01E1000_ANALOG_FUSE_COARSE_THRESH) 4553 fine -= IGP01E1000_ANALOG_FUSE_FINE_10; 4554 4555 fused = (fused 4556 & IGP01E1000_ANALOG_FUSE_POLY_MASK) | 4557 (fine 4558 & IGP01E1000_ANALOG_FUSE_FINE_MASK) | 4559 (coarse 4560 & IGP01E1000_ANALOG_FUSE_COARSE_MASK); 4561 4562 e1000_write_phy_reg(hw, 4563 IGP01E1000_ANALOG_FUSE_CONTROL, fused); 4564 e1000_write_phy_reg(hw, 4565 IGP01E1000_ANALOG_FUSE_BYPASS, 4566 IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL); 4567 } 4568 } 4569 } 4570 } 4571 4572 /****************************************************************************** 4573 * Resets the PHY 4574 * 4575 * hw - Struct containing variables accessed by shared code 4576 * 4577 * Sets bit 15 of the MII Control register 4578 ******************************************************************************/ 4579 int32_t 4580 e1000_phy_reset(struct e1000_hw *hw) 4581 { 4582 int32_t ret_val; 4583 uint16_t phy_data; 4584 4585 DEBUGFUNC(); 4586 4587 /* In the case of the phy reset being blocked, it's not an error, we 4588 * simply return success without performing the reset. */ 4589 ret_val = e1000_check_phy_reset_block(hw); 4590 if (ret_val) 4591 return E1000_SUCCESS; 4592 4593 switch (hw->phy_type) { 4594 case e1000_phy_igp: 4595 case e1000_phy_igp_2: 4596 case e1000_phy_igp_3: 4597 case e1000_phy_ife: 4598 case e1000_phy_igb: 4599 ret_val = e1000_phy_hw_reset(hw); 4600 if (ret_val) 4601 return ret_val; 4602 break; 4603 default: 4604 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data); 4605 if (ret_val) 4606 return ret_val; 4607 4608 phy_data |= MII_CR_RESET; 4609 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data); 4610 if (ret_val) 4611 return ret_val; 4612 4613 udelay(1); 4614 break; 4615 } 4616 4617 if (hw->phy_type == e1000_phy_igp || hw->phy_type == e1000_phy_igp_2) 4618 e1000_phy_init_script(hw); 4619 4620 return E1000_SUCCESS; 4621 } 4622 4623 static int e1000_set_phy_type (struct e1000_hw *hw) 4624 { 4625 DEBUGFUNC (); 4626 4627 if (hw->mac_type == e1000_undefined) 4628 return -E1000_ERR_PHY_TYPE; 4629 4630 switch (hw->phy_id) { 4631 case M88E1000_E_PHY_ID: 4632 case M88E1000_I_PHY_ID: 4633 case M88E1011_I_PHY_ID: 4634 case M88E1111_I_PHY_ID: 4635 hw->phy_type = e1000_phy_m88; 4636 break; 4637 case IGP01E1000_I_PHY_ID: 4638 if (hw->mac_type == e1000_82541 || 4639 hw->mac_type == e1000_82541_rev_2 || 4640 hw->mac_type == e1000_82547 || 4641 hw->mac_type == e1000_82547_rev_2) { 4642 hw->phy_type = e1000_phy_igp; 4643 break; 4644 } 4645 case IGP03E1000_E_PHY_ID: 4646 hw->phy_type = e1000_phy_igp_3; 4647 break; 4648 case IFE_E_PHY_ID: 4649 case IFE_PLUS_E_PHY_ID: 4650 case IFE_C_E_PHY_ID: 4651 hw->phy_type = e1000_phy_ife; 4652 break; 4653 case GG82563_E_PHY_ID: 4654 if (hw->mac_type == e1000_80003es2lan) { 4655 hw->phy_type = e1000_phy_gg82563; 4656 break; 4657 } 4658 case BME1000_E_PHY_ID: 4659 hw->phy_type = e1000_phy_bm; 4660 break; 4661 case I210_I_PHY_ID: 4662 hw->phy_type = e1000_phy_igb; 4663 break; 4664 /* Fall Through */ 4665 default: 4666 /* Should never have loaded on this device */ 4667 hw->phy_type = e1000_phy_undefined; 4668 return -E1000_ERR_PHY_TYPE; 4669 } 4670 4671 return E1000_SUCCESS; 4672 } 4673 4674 /****************************************************************************** 4675 * Probes the expected PHY address for known PHY IDs 4676 * 4677 * hw - Struct containing variables accessed by shared code 4678 ******************************************************************************/ 4679 static int32_t 4680 e1000_detect_gig_phy(struct e1000_hw *hw) 4681 { 4682 int32_t phy_init_status, ret_val; 4683 uint16_t phy_id_high, phy_id_low; 4684 bool match = false; 4685 4686 DEBUGFUNC(); 4687 4688 /* The 82571 firmware may still be configuring the PHY. In this 4689 * case, we cannot access the PHY until the configuration is done. So 4690 * we explicitly set the PHY values. */ 4691 if (hw->mac_type == e1000_82571 || 4692 hw->mac_type == e1000_82572) { 4693 hw->phy_id = IGP01E1000_I_PHY_ID; 4694 hw->phy_type = e1000_phy_igp_2; 4695 return E1000_SUCCESS; 4696 } 4697 4698 /* ESB-2 PHY reads require e1000_phy_gg82563 to be set because of a 4699 * work- around that forces PHY page 0 to be set or the reads fail. 4700 * The rest of the code in this routine uses e1000_read_phy_reg to 4701 * read the PHY ID. So for ESB-2 we need to have this set so our 4702 * reads won't fail. If the attached PHY is not a e1000_phy_gg82563, 4703 * the routines below will figure this out as well. */ 4704 if (hw->mac_type == e1000_80003es2lan) 4705 hw->phy_type = e1000_phy_gg82563; 4706 4707 /* Read the PHY ID Registers to identify which PHY is onboard. */ 4708 ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high); 4709 if (ret_val) 4710 return ret_val; 4711 4712 hw->phy_id = (uint32_t) (phy_id_high << 16); 4713 udelay(20); 4714 ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low); 4715 if (ret_val) 4716 return ret_val; 4717 4718 hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK); 4719 hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK; 4720 4721 switch (hw->mac_type) { 4722 case e1000_82543: 4723 if (hw->phy_id == M88E1000_E_PHY_ID) 4724 match = true; 4725 break; 4726 case e1000_82544: 4727 if (hw->phy_id == M88E1000_I_PHY_ID) 4728 match = true; 4729 break; 4730 case e1000_82540: 4731 case e1000_82545: 4732 case e1000_82545_rev_3: 4733 case e1000_82546: 4734 case e1000_82546_rev_3: 4735 if (hw->phy_id == M88E1011_I_PHY_ID) 4736 match = true; 4737 break; 4738 case e1000_82541: 4739 case e1000_82541_rev_2: 4740 case e1000_82547: 4741 case e1000_82547_rev_2: 4742 if(hw->phy_id == IGP01E1000_I_PHY_ID) 4743 match = true; 4744 4745 break; 4746 case e1000_82573: 4747 if (hw->phy_id == M88E1111_I_PHY_ID) 4748 match = true; 4749 break; 4750 case e1000_82574: 4751 if (hw->phy_id == BME1000_E_PHY_ID) 4752 match = true; 4753 break; 4754 case e1000_80003es2lan: 4755 if (hw->phy_id == GG82563_E_PHY_ID) 4756 match = true; 4757 break; 4758 case e1000_ich8lan: 4759 if (hw->phy_id == IGP03E1000_E_PHY_ID) 4760 match = true; 4761 if (hw->phy_id == IFE_E_PHY_ID) 4762 match = true; 4763 if (hw->phy_id == IFE_PLUS_E_PHY_ID) 4764 match = true; 4765 if (hw->phy_id == IFE_C_E_PHY_ID) 4766 match = true; 4767 break; 4768 case e1000_igb: 4769 if (hw->phy_id == I210_I_PHY_ID) 4770 match = true; 4771 break; 4772 default: 4773 DEBUGOUT("Invalid MAC type %d\n", hw->mac_type); 4774 return -E1000_ERR_CONFIG; 4775 } 4776 4777 phy_init_status = e1000_set_phy_type(hw); 4778 4779 if ((match) && (phy_init_status == E1000_SUCCESS)) { 4780 DEBUGOUT("PHY ID 0x%X detected\n", hw->phy_id); 4781 return 0; 4782 } 4783 DEBUGOUT("Invalid PHY ID 0x%X\n", hw->phy_id); 4784 return -E1000_ERR_PHY; 4785 } 4786 4787 /***************************************************************************** 4788 * Set media type and TBI compatibility. 4789 * 4790 * hw - Struct containing variables accessed by shared code 4791 * **************************************************************************/ 4792 void 4793 e1000_set_media_type(struct e1000_hw *hw) 4794 { 4795 uint32_t status; 4796 4797 DEBUGFUNC(); 4798 4799 if (hw->mac_type != e1000_82543) { 4800 /* tbi_compatibility is only valid on 82543 */ 4801 hw->tbi_compatibility_en = false; 4802 } 4803 4804 switch (hw->device_id) { 4805 case E1000_DEV_ID_82545GM_SERDES: 4806 case E1000_DEV_ID_82546GB_SERDES: 4807 case E1000_DEV_ID_82571EB_SERDES: 4808 case E1000_DEV_ID_82571EB_SERDES_DUAL: 4809 case E1000_DEV_ID_82571EB_SERDES_QUAD: 4810 case E1000_DEV_ID_82572EI_SERDES: 4811 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT: 4812 hw->media_type = e1000_media_type_internal_serdes; 4813 break; 4814 default: 4815 switch (hw->mac_type) { 4816 case e1000_82542_rev2_0: 4817 case e1000_82542_rev2_1: 4818 hw->media_type = e1000_media_type_fiber; 4819 break; 4820 case e1000_ich8lan: 4821 case e1000_82573: 4822 case e1000_82574: 4823 case e1000_igb: 4824 /* The STATUS_TBIMODE bit is reserved or reused 4825 * for the this device. 4826 */ 4827 hw->media_type = e1000_media_type_copper; 4828 break; 4829 default: 4830 status = E1000_READ_REG(hw, STATUS); 4831 if (status & E1000_STATUS_TBIMODE) { 4832 hw->media_type = e1000_media_type_fiber; 4833 /* tbi_compatibility not valid on fiber */ 4834 hw->tbi_compatibility_en = false; 4835 } else { 4836 hw->media_type = e1000_media_type_copper; 4837 } 4838 break; 4839 } 4840 } 4841 } 4842 4843 /** 4844 * e1000_sw_init - Initialize general software structures (struct e1000_adapter) 4845 * 4846 * e1000_sw_init initializes the Adapter private data structure. 4847 * Fields are initialized based on PCI device information and 4848 * OS network device settings (MTU size). 4849 **/ 4850 4851 static int 4852 e1000_sw_init(struct eth_device *nic) 4853 { 4854 struct e1000_hw *hw = (typeof(hw)) nic->priv; 4855 int result; 4856 4857 /* PCI config space info */ 4858 pci_read_config_word(hw->pdev, PCI_VENDOR_ID, &hw->vendor_id); 4859 pci_read_config_word(hw->pdev, PCI_DEVICE_ID, &hw->device_id); 4860 pci_read_config_word(hw->pdev, PCI_SUBSYSTEM_VENDOR_ID, 4861 &hw->subsystem_vendor_id); 4862 pci_read_config_word(hw->pdev, PCI_SUBSYSTEM_ID, &hw->subsystem_id); 4863 4864 pci_read_config_byte(hw->pdev, PCI_REVISION_ID, &hw->revision_id); 4865 pci_read_config_word(hw->pdev, PCI_COMMAND, &hw->pci_cmd_word); 4866 4867 /* identify the MAC */ 4868 result = e1000_set_mac_type(hw); 4869 if (result) { 4870 E1000_ERR(hw->nic, "Unknown MAC Type\n"); 4871 return result; 4872 } 4873 4874 switch (hw->mac_type) { 4875 default: 4876 break; 4877 case e1000_82541: 4878 case e1000_82547: 4879 case e1000_82541_rev_2: 4880 case e1000_82547_rev_2: 4881 hw->phy_init_script = 1; 4882 break; 4883 } 4884 4885 /* flow control settings */ 4886 hw->fc_high_water = E1000_FC_HIGH_THRESH; 4887 hw->fc_low_water = E1000_FC_LOW_THRESH; 4888 hw->fc_pause_time = E1000_FC_PAUSE_TIME; 4889 hw->fc_send_xon = 1; 4890 4891 /* Media type - copper or fiber */ 4892 hw->tbi_compatibility_en = true; 4893 e1000_set_media_type(hw); 4894 4895 if (hw->mac_type >= e1000_82543) { 4896 uint32_t status = E1000_READ_REG(hw, STATUS); 4897 4898 if (status & E1000_STATUS_TBIMODE) { 4899 DEBUGOUT("fiber interface\n"); 4900 hw->media_type = e1000_media_type_fiber; 4901 } else { 4902 DEBUGOUT("copper interface\n"); 4903 hw->media_type = e1000_media_type_copper; 4904 } 4905 } else { 4906 hw->media_type = e1000_media_type_fiber; 4907 } 4908 4909 hw->wait_autoneg_complete = true; 4910 if (hw->mac_type < e1000_82543) 4911 hw->report_tx_early = 0; 4912 else 4913 hw->report_tx_early = 1; 4914 4915 return E1000_SUCCESS; 4916 } 4917 4918 void 4919 fill_rx(struct e1000_hw *hw) 4920 { 4921 struct e1000_rx_desc *rd; 4922 uint32_t flush_start, flush_end; 4923 4924 rx_last = rx_tail; 4925 rd = rx_base + rx_tail; 4926 rx_tail = (rx_tail + 1) % 8; 4927 memset(rd, 0, 16); 4928 rd->buffer_addr = cpu_to_le64((u32)packet); 4929 4930 /* 4931 * Make sure there are no stale data in WB over this area, which 4932 * might get written into the memory while the e1000 also writes 4933 * into the same memory area. 4934 */ 4935 invalidate_dcache_range((u32)packet, (u32)packet + 4096); 4936 /* Dump the DMA descriptor into RAM. */ 4937 flush_start = ((u32)rd) & ~(ARCH_DMA_MINALIGN - 1); 4938 flush_end = flush_start + roundup(sizeof(*rd), ARCH_DMA_MINALIGN); 4939 flush_dcache_range(flush_start, flush_end); 4940 4941 E1000_WRITE_REG(hw, RDT, rx_tail); 4942 } 4943 4944 /** 4945 * e1000_configure_tx - Configure 8254x Transmit Unit after Reset 4946 * @adapter: board private structure 4947 * 4948 * Configure the Tx unit of the MAC after a reset. 4949 **/ 4950 4951 static void 4952 e1000_configure_tx(struct e1000_hw *hw) 4953 { 4954 unsigned long tctl; 4955 unsigned long tipg, tarc; 4956 uint32_t ipgr1, ipgr2; 4957 4958 E1000_WRITE_REG(hw, TDBAL, (u32) tx_base); 4959 E1000_WRITE_REG(hw, TDBAH, 0); 4960 4961 E1000_WRITE_REG(hw, TDLEN, 128); 4962 4963 /* Setup the HW Tx Head and Tail descriptor pointers */ 4964 E1000_WRITE_REG(hw, TDH, 0); 4965 E1000_WRITE_REG(hw, TDT, 0); 4966 tx_tail = 0; 4967 4968 /* Set the default values for the Tx Inter Packet Gap timer */ 4969 if (hw->mac_type <= e1000_82547_rev_2 && 4970 (hw->media_type == e1000_media_type_fiber || 4971 hw->media_type == e1000_media_type_internal_serdes)) 4972 tipg = DEFAULT_82543_TIPG_IPGT_FIBER; 4973 else 4974 tipg = DEFAULT_82543_TIPG_IPGT_COPPER; 4975 4976 /* Set the default values for the Tx Inter Packet Gap timer */ 4977 switch (hw->mac_type) { 4978 case e1000_82542_rev2_0: 4979 case e1000_82542_rev2_1: 4980 tipg = DEFAULT_82542_TIPG_IPGT; 4981 ipgr1 = DEFAULT_82542_TIPG_IPGR1; 4982 ipgr2 = DEFAULT_82542_TIPG_IPGR2; 4983 break; 4984 case e1000_80003es2lan: 4985 ipgr1 = DEFAULT_82543_TIPG_IPGR1; 4986 ipgr2 = DEFAULT_80003ES2LAN_TIPG_IPGR2; 4987 break; 4988 default: 4989 ipgr1 = DEFAULT_82543_TIPG_IPGR1; 4990 ipgr2 = DEFAULT_82543_TIPG_IPGR2; 4991 break; 4992 } 4993 tipg |= ipgr1 << E1000_TIPG_IPGR1_SHIFT; 4994 tipg |= ipgr2 << E1000_TIPG_IPGR2_SHIFT; 4995 E1000_WRITE_REG(hw, TIPG, tipg); 4996 /* Program the Transmit Control Register */ 4997 tctl = E1000_READ_REG(hw, TCTL); 4998 tctl &= ~E1000_TCTL_CT; 4999 tctl |= E1000_TCTL_EN | E1000_TCTL_PSP | 5000 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); 5001 5002 if (hw->mac_type == e1000_82571 || hw->mac_type == e1000_82572) { 5003 tarc = E1000_READ_REG(hw, TARC0); 5004 /* set the speed mode bit, we'll clear it if we're not at 5005 * gigabit link later */ 5006 /* git bit can be set to 1*/ 5007 } else if (hw->mac_type == e1000_80003es2lan) { 5008 tarc = E1000_READ_REG(hw, TARC0); 5009 tarc |= 1; 5010 E1000_WRITE_REG(hw, TARC0, tarc); 5011 tarc = E1000_READ_REG(hw, TARC1); 5012 tarc |= 1; 5013 E1000_WRITE_REG(hw, TARC1, tarc); 5014 } 5015 5016 5017 e1000_config_collision_dist(hw); 5018 /* Setup Transmit Descriptor Settings for eop descriptor */ 5019 hw->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS; 5020 5021 /* Need to set up RS bit */ 5022 if (hw->mac_type < e1000_82543) 5023 hw->txd_cmd |= E1000_TXD_CMD_RPS; 5024 else 5025 hw->txd_cmd |= E1000_TXD_CMD_RS; 5026 5027 5028 if (hw->mac_type == e1000_igb) { 5029 E1000_WRITE_REG(hw, TCTL_EXT, 0x42 << 10); 5030 5031 uint32_t reg_txdctl = E1000_READ_REG(hw, TXDCTL); 5032 reg_txdctl |= 1 << 25; 5033 E1000_WRITE_REG(hw, TXDCTL, reg_txdctl); 5034 mdelay(20); 5035 } 5036 5037 5038 5039 E1000_WRITE_REG(hw, TCTL, tctl); 5040 5041 5042 } 5043 5044 /** 5045 * e1000_setup_rctl - configure the receive control register 5046 * @adapter: Board private structure 5047 **/ 5048 static void 5049 e1000_setup_rctl(struct e1000_hw *hw) 5050 { 5051 uint32_t rctl; 5052 5053 rctl = E1000_READ_REG(hw, RCTL); 5054 5055 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 5056 5057 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO 5058 | E1000_RCTL_RDMTS_HALF; /* | 5059 (hw.mc_filter_type << E1000_RCTL_MO_SHIFT); */ 5060 5061 if (hw->tbi_compatibility_on == 1) 5062 rctl |= E1000_RCTL_SBP; 5063 else 5064 rctl &= ~E1000_RCTL_SBP; 5065 5066 rctl &= ~(E1000_RCTL_SZ_4096); 5067 rctl |= E1000_RCTL_SZ_2048; 5068 rctl &= ~(E1000_RCTL_BSEX | E1000_RCTL_LPE); 5069 E1000_WRITE_REG(hw, RCTL, rctl); 5070 } 5071 5072 /** 5073 * e1000_configure_rx - Configure 8254x Receive Unit after Reset 5074 * @adapter: board private structure 5075 * 5076 * Configure the Rx unit of the MAC after a reset. 5077 **/ 5078 static void 5079 e1000_configure_rx(struct e1000_hw *hw) 5080 { 5081 unsigned long rctl, ctrl_ext; 5082 rx_tail = 0; 5083 /* make sure receives are disabled while setting up the descriptors */ 5084 rctl = E1000_READ_REG(hw, RCTL); 5085 E1000_WRITE_REG(hw, RCTL, rctl & ~E1000_RCTL_EN); 5086 if (hw->mac_type >= e1000_82540) { 5087 /* Set the interrupt throttling rate. Value is calculated 5088 * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns) */ 5089 #define MAX_INTS_PER_SEC 8000 5090 #define DEFAULT_ITR 1000000000/(MAX_INTS_PER_SEC * 256) 5091 E1000_WRITE_REG(hw, ITR, DEFAULT_ITR); 5092 } 5093 5094 if (hw->mac_type >= e1000_82571) { 5095 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 5096 /* Reset delay timers after every interrupt */ 5097 ctrl_ext |= E1000_CTRL_EXT_INT_TIMER_CLR; 5098 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 5099 E1000_WRITE_FLUSH(hw); 5100 } 5101 /* Setup the Base and Length of the Rx Descriptor Ring */ 5102 E1000_WRITE_REG(hw, RDBAL, (u32) rx_base); 5103 E1000_WRITE_REG(hw, RDBAH, 0); 5104 5105 E1000_WRITE_REG(hw, RDLEN, 128); 5106 5107 /* Setup the HW Rx Head and Tail Descriptor Pointers */ 5108 E1000_WRITE_REG(hw, RDH, 0); 5109 E1000_WRITE_REG(hw, RDT, 0); 5110 /* Enable Receives */ 5111 5112 if (hw->mac_type == e1000_igb) { 5113 5114 uint32_t reg_rxdctl = E1000_READ_REG(hw, RXDCTL); 5115 reg_rxdctl |= 1 << 25; 5116 E1000_WRITE_REG(hw, RXDCTL, reg_rxdctl); 5117 mdelay(20); 5118 } 5119 5120 E1000_WRITE_REG(hw, RCTL, rctl); 5121 5122 fill_rx(hw); 5123 } 5124 5125 /************************************************************************** 5126 POLL - Wait for a frame 5127 ***************************************************************************/ 5128 static int 5129 e1000_poll(struct eth_device *nic) 5130 { 5131 struct e1000_hw *hw = nic->priv; 5132 struct e1000_rx_desc *rd; 5133 uint32_t inval_start, inval_end; 5134 uint32_t len; 5135 5136 /* return true if there's an ethernet packet ready to read */ 5137 rd = rx_base + rx_last; 5138 5139 /* Re-load the descriptor from RAM. */ 5140 inval_start = ((u32)rd) & ~(ARCH_DMA_MINALIGN - 1); 5141 inval_end = inval_start + roundup(sizeof(*rd), ARCH_DMA_MINALIGN); 5142 invalidate_dcache_range(inval_start, inval_end); 5143 5144 if (!(le32_to_cpu(rd->status)) & E1000_RXD_STAT_DD) 5145 return 0; 5146 /*DEBUGOUT("recv: packet len=%d \n", rd->length); */ 5147 /* Packet received, make sure the data are re-loaded from RAM. */ 5148 len = le32_to_cpu(rd->length); 5149 invalidate_dcache_range((u32)packet, 5150 (u32)packet + roundup(len, ARCH_DMA_MINALIGN)); 5151 NetReceive((uchar *)packet, len); 5152 fill_rx(hw); 5153 return 1; 5154 } 5155 5156 /************************************************************************** 5157 TRANSMIT - Transmit a frame 5158 ***************************************************************************/ 5159 static int e1000_transmit(struct eth_device *nic, void *txpacket, int length) 5160 { 5161 void *nv_packet = (void *)txpacket; 5162 struct e1000_hw *hw = nic->priv; 5163 struct e1000_tx_desc *txp; 5164 int i = 0; 5165 uint32_t flush_start, flush_end; 5166 5167 txp = tx_base + tx_tail; 5168 tx_tail = (tx_tail + 1) % 8; 5169 5170 txp->buffer_addr = cpu_to_le64(virt_to_bus(hw->pdev, nv_packet)); 5171 txp->lower.data = cpu_to_le32(hw->txd_cmd | length); 5172 txp->upper.data = 0; 5173 5174 /* Dump the packet into RAM so e1000 can pick them. */ 5175 flush_dcache_range((u32)nv_packet, 5176 (u32)nv_packet + roundup(length, ARCH_DMA_MINALIGN)); 5177 /* Dump the descriptor into RAM as well. */ 5178 flush_start = ((u32)txp) & ~(ARCH_DMA_MINALIGN - 1); 5179 flush_end = flush_start + roundup(sizeof(*txp), ARCH_DMA_MINALIGN); 5180 flush_dcache_range(flush_start, flush_end); 5181 5182 E1000_WRITE_REG(hw, TDT, tx_tail); 5183 5184 E1000_WRITE_FLUSH(hw); 5185 while (1) { 5186 invalidate_dcache_range(flush_start, flush_end); 5187 if (le32_to_cpu(txp->upper.data) & E1000_TXD_STAT_DD) 5188 break; 5189 if (i++ > TOUT_LOOP) { 5190 DEBUGOUT("e1000: tx timeout\n"); 5191 return 0; 5192 } 5193 udelay(10); /* give the nic a chance to write to the register */ 5194 } 5195 return 1; 5196 } 5197 5198 /*reset function*/ 5199 static inline int 5200 e1000_reset(struct eth_device *nic) 5201 { 5202 struct e1000_hw *hw = nic->priv; 5203 5204 e1000_reset_hw(hw); 5205 if (hw->mac_type >= e1000_82544) { 5206 E1000_WRITE_REG(hw, WUC, 0); 5207 } 5208 return e1000_init_hw(nic); 5209 } 5210 5211 /************************************************************************** 5212 DISABLE - Turn off ethernet interface 5213 ***************************************************************************/ 5214 static void 5215 e1000_disable(struct eth_device *nic) 5216 { 5217 struct e1000_hw *hw = nic->priv; 5218 5219 /* Turn off the ethernet interface */ 5220 E1000_WRITE_REG(hw, RCTL, 0); 5221 E1000_WRITE_REG(hw, TCTL, 0); 5222 5223 /* Clear the transmit ring */ 5224 E1000_WRITE_REG(hw, TDH, 0); 5225 E1000_WRITE_REG(hw, TDT, 0); 5226 5227 /* Clear the receive ring */ 5228 E1000_WRITE_REG(hw, RDH, 0); 5229 E1000_WRITE_REG(hw, RDT, 0); 5230 5231 /* put the card in its initial state */ 5232 #if 0 5233 E1000_WRITE_REG(hw, CTRL, E1000_CTRL_RST); 5234 #endif 5235 mdelay(10); 5236 5237 } 5238 5239 /************************************************************************** 5240 INIT - set up ethernet interface(s) 5241 ***************************************************************************/ 5242 static int 5243 e1000_init(struct eth_device *nic, bd_t * bis) 5244 { 5245 struct e1000_hw *hw = nic->priv; 5246 int ret_val = 0; 5247 5248 ret_val = e1000_reset(nic); 5249 if (ret_val < 0) { 5250 if ((ret_val == -E1000_ERR_NOLINK) || 5251 (ret_val == -E1000_ERR_TIMEOUT)) { 5252 E1000_ERR(hw->nic, "Valid Link not detected\n"); 5253 } else { 5254 E1000_ERR(hw->nic, "Hardware Initialization Failed\n"); 5255 } 5256 return 0; 5257 } 5258 e1000_configure_tx(hw); 5259 e1000_setup_rctl(hw); 5260 e1000_configure_rx(hw); 5261 return 1; 5262 } 5263 5264 /****************************************************************************** 5265 * Gets the current PCI bus type of hardware 5266 * 5267 * hw - Struct containing variables accessed by shared code 5268 *****************************************************************************/ 5269 void e1000_get_bus_type(struct e1000_hw *hw) 5270 { 5271 uint32_t status; 5272 5273 switch (hw->mac_type) { 5274 case e1000_82542_rev2_0: 5275 case e1000_82542_rev2_1: 5276 hw->bus_type = e1000_bus_type_pci; 5277 break; 5278 case e1000_82571: 5279 case e1000_82572: 5280 case e1000_82573: 5281 case e1000_82574: 5282 case e1000_80003es2lan: 5283 case e1000_ich8lan: 5284 case e1000_igb: 5285 hw->bus_type = e1000_bus_type_pci_express; 5286 break; 5287 default: 5288 status = E1000_READ_REG(hw, STATUS); 5289 hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ? 5290 e1000_bus_type_pcix : e1000_bus_type_pci; 5291 break; 5292 } 5293 } 5294 5295 /* A list of all registered e1000 devices */ 5296 static LIST_HEAD(e1000_hw_list); 5297 5298 /************************************************************************** 5299 PROBE - Look for an adapter, this routine's visible to the outside 5300 You should omit the last argument struct pci_device * for a non-PCI NIC 5301 ***************************************************************************/ 5302 int 5303 e1000_initialize(bd_t * bis) 5304 { 5305 unsigned int i; 5306 pci_dev_t devno; 5307 5308 DEBUGFUNC(); 5309 5310 /* Find and probe all the matching PCI devices */ 5311 for (i = 0; (devno = pci_find_devices(e1000_supported, i)) >= 0; i++) { 5312 u32 val; 5313 5314 /* 5315 * These will never get freed due to errors, this allows us to 5316 * perform SPI EEPROM programming from U-boot, for example. 5317 */ 5318 struct eth_device *nic = malloc(sizeof(*nic)); 5319 struct e1000_hw *hw = malloc(sizeof(*hw)); 5320 if (!nic || !hw) { 5321 printf("e1000#%u: Out of Memory!\n", i); 5322 free(nic); 5323 free(hw); 5324 continue; 5325 } 5326 5327 /* Make sure all of the fields are initially zeroed */ 5328 memset(nic, 0, sizeof(*nic)); 5329 memset(hw, 0, sizeof(*hw)); 5330 5331 /* Assign the passed-in values */ 5332 hw->cardnum = i; 5333 hw->pdev = devno; 5334 hw->nic = nic; 5335 nic->priv = hw; 5336 5337 /* Generate a card name */ 5338 sprintf(nic->name, "e1000#%u", hw->cardnum); 5339 5340 /* Print a debug message with the IO base address */ 5341 pci_read_config_dword(devno, PCI_BASE_ADDRESS_0, &val); 5342 E1000_DBG(nic, "iobase 0x%08x\n", val & 0xfffffff0); 5343 5344 /* Try to enable I/O accesses and bus-mastering */ 5345 val = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; 5346 pci_write_config_dword(devno, PCI_COMMAND, val); 5347 5348 /* Make sure it worked */ 5349 pci_read_config_dword(devno, PCI_COMMAND, &val); 5350 if (!(val & PCI_COMMAND_MEMORY)) { 5351 E1000_ERR(nic, "Can't enable I/O memory\n"); 5352 continue; 5353 } 5354 if (!(val & PCI_COMMAND_MASTER)) { 5355 E1000_ERR(nic, "Can't enable bus-mastering\n"); 5356 continue; 5357 } 5358 5359 /* Are these variables needed? */ 5360 hw->fc = e1000_fc_default; 5361 hw->original_fc = e1000_fc_default; 5362 hw->autoneg_failed = 0; 5363 hw->autoneg = 1; 5364 hw->get_link_status = true; 5365 hw->eeprom_semaphore_present = true; 5366 hw->hw_addr = pci_map_bar(devno, PCI_BASE_ADDRESS_0, 5367 PCI_REGION_MEM); 5368 hw->mac_type = e1000_undefined; 5369 5370 /* MAC and Phy settings */ 5371 if (e1000_sw_init(nic) < 0) { 5372 E1000_ERR(nic, "Software init failed\n"); 5373 continue; 5374 } 5375 if (e1000_check_phy_reset_block(hw)) 5376 E1000_ERR(nic, "PHY Reset is blocked!\n"); 5377 5378 /* Basic init was OK, reset the hardware and allow SPI access */ 5379 e1000_reset_hw(hw); 5380 list_add_tail(&hw->list_node, &e1000_hw_list); 5381 5382 #ifndef CONFIG_E1000_NO_NVM 5383 /* Validate the EEPROM and get chipset information */ 5384 #if !defined(CONFIG_MVBC_1G) 5385 if (e1000_init_eeprom_params(hw)) { 5386 E1000_ERR(nic, "EEPROM is invalid!\n"); 5387 continue; 5388 } 5389 if ((E1000_READ_REG(hw, I210_EECD) & E1000_EECD_FLUPD) && 5390 e1000_validate_eeprom_checksum(hw)) 5391 continue; 5392 #endif 5393 e1000_read_mac_addr(nic); 5394 #endif 5395 e1000_get_bus_type(hw); 5396 5397 #ifndef CONFIG_E1000_NO_NVM 5398 printf("e1000: %02x:%02x:%02x:%02x:%02x:%02x\n ", 5399 nic->enetaddr[0], nic->enetaddr[1], nic->enetaddr[2], 5400 nic->enetaddr[3], nic->enetaddr[4], nic->enetaddr[5]); 5401 #else 5402 memset(nic->enetaddr, 0, 6); 5403 printf("e1000: no NVM\n"); 5404 #endif 5405 5406 /* Set up the function pointers and register the device */ 5407 nic->init = e1000_init; 5408 nic->recv = e1000_poll; 5409 nic->send = e1000_transmit; 5410 nic->halt = e1000_disable; 5411 eth_register(nic); 5412 } 5413 5414 return i; 5415 } 5416 5417 struct e1000_hw *e1000_find_card(unsigned int cardnum) 5418 { 5419 struct e1000_hw *hw; 5420 5421 list_for_each_entry(hw, &e1000_hw_list, list_node) 5422 if (hw->cardnum == cardnum) 5423 return hw; 5424 5425 return NULL; 5426 } 5427 5428 #ifdef CONFIG_CMD_E1000 5429 static int do_e1000(cmd_tbl_t *cmdtp, int flag, 5430 int argc, char * const argv[]) 5431 { 5432 struct e1000_hw *hw; 5433 5434 if (argc < 3) { 5435 cmd_usage(cmdtp); 5436 return 1; 5437 } 5438 5439 /* Make sure we can find the requested e1000 card */ 5440 hw = e1000_find_card(simple_strtoul(argv[1], NULL, 10)); 5441 if (!hw) { 5442 printf("e1000: ERROR: No such device: e1000#%s\n", argv[1]); 5443 return 1; 5444 } 5445 5446 if (!strcmp(argv[2], "print-mac-address")) { 5447 unsigned char *mac = hw->nic->enetaddr; 5448 printf("%02x:%02x:%02x:%02x:%02x:%02x\n", 5449 mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]); 5450 return 0; 5451 } 5452 5453 #ifdef CONFIG_E1000_SPI 5454 /* Handle the "SPI" subcommand */ 5455 if (!strcmp(argv[2], "spi")) 5456 return do_e1000_spi(cmdtp, hw, argc - 3, argv + 3); 5457 #endif 5458 5459 cmd_usage(cmdtp); 5460 return 1; 5461 } 5462 5463 U_BOOT_CMD( 5464 e1000, 7, 0, do_e1000, 5465 "Intel e1000 controller management", 5466 /* */"<card#> print-mac-address\n" 5467 #ifdef CONFIG_E1000_SPI 5468 "e1000 <card#> spi show [<offset> [<length>]]\n" 5469 "e1000 <card#> spi dump <addr> <offset> <length>\n" 5470 "e1000 <card#> spi program <addr> <offset> <length>\n" 5471 "e1000 <card#> spi checksum [update]\n" 5472 #endif 5473 " - Manage the Intel E1000 PCI device" 5474 ); 5475 #endif /* not CONFIG_CMD_E1000 */ 5476