1 /************************************************************************** 2 Intel Pro 1000 for ppcboot/das-u-boot 3 Drivers are port from Intel's Linux driver e1000-4.3.15 4 and from Etherboot pro 1000 driver by mrakes at vivato dot net 5 tested on both gig copper and gig fiber boards 6 ***************************************************************************/ 7 /******************************************************************************* 8 9 10 Copyright(c) 1999 - 2002 Intel Corporation. All rights reserved. 11 12 This program is free software; you can redistribute it and/or modify it 13 under the terms of the GNU General Public License as published by the Free 14 Software Foundation; either version 2 of the License, or (at your option) 15 any later version. 16 17 This program is distributed in the hope that it will be useful, but WITHOUT 18 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 19 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 20 more details. 21 22 You should have received a copy of the GNU General Public License along with 23 this program; if not, write to the Free Software Foundation, Inc., 59 24 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 25 26 The full GNU General Public License is included in this distribution in the 27 file called LICENSE. 28 29 Contact Information: 30 Linux NICS <linux.nics@intel.com> 31 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 32 33 *******************************************************************************/ 34 /* 35 * Copyright (C) Archway Digital Solutions. 36 * 37 * written by Chrsitopher Li <cli at arcyway dot com> or <chrisl at gnuchina dot org> 38 * 2/9/2002 39 * 40 * Copyright (C) Linux Networx. 41 * Massive upgrade to work with the new intel gigabit NICs. 42 * <ebiederman at lnxi dot com> 43 * 44 * Copyright 2011 Freescale Semiconductor, Inc. 45 */ 46 47 #include "e1000.h" 48 49 #define TOUT_LOOP 100000 50 51 #define virt_to_bus(devno, v) pci_virt_to_mem(devno, (void *) (v)) 52 #define bus_to_phys(devno, a) pci_mem_to_phys(devno, a) 53 54 #define E1000_DEFAULT_PCI_PBA 0x00000030 55 #define E1000_DEFAULT_PCIE_PBA 0x000a0026 56 57 /* NIC specific static variables go here */ 58 59 static char tx_pool[128 + 16]; 60 static char rx_pool[128 + 16]; 61 static char packet[2096]; 62 63 static struct e1000_tx_desc *tx_base; 64 static struct e1000_rx_desc *rx_base; 65 66 static int tx_tail; 67 static int rx_tail, rx_last; 68 69 static struct pci_device_id e1000_supported[] = { 70 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82542}, 71 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82543GC_FIBER}, 72 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82543GC_COPPER}, 73 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544EI_COPPER}, 74 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544EI_FIBER}, 75 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544GC_COPPER}, 76 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544GC_LOM}, 77 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82540EM}, 78 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545EM_COPPER}, 79 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545GM_COPPER}, 80 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_COPPER}, 81 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545EM_FIBER}, 82 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_FIBER}, 83 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546GB_COPPER}, 84 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82540EM_LOM}, 85 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82541ER}, 86 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82541GI_LF}, 87 /* E1000 PCIe card */ 88 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_COPPER}, 89 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_FIBER }, 90 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES }, 91 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_COPPER}, 92 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571PT_QUAD_COPPER}, 93 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_FIBER}, 94 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_COPPER_LOWPROFILE}, 95 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES_DUAL}, 96 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES_QUAD}, 97 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_COPPER}, 98 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_FIBER}, 99 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_SERDES}, 100 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI}, 101 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573E}, 102 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573E_IAMT}, 103 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573L}, 104 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82574L}, 105 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546GB_QUAD_COPPER_KSP3}, 106 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_COPPER_DPT}, 107 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_SERDES_DPT}, 108 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_COPPER_SPT}, 109 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_SERDES_SPT}, 110 {} 111 }; 112 113 /* Function forward declarations */ 114 static int e1000_setup_link(struct eth_device *nic); 115 static int e1000_setup_fiber_link(struct eth_device *nic); 116 static int e1000_setup_copper_link(struct eth_device *nic); 117 static int e1000_phy_setup_autoneg(struct e1000_hw *hw); 118 static void e1000_config_collision_dist(struct e1000_hw *hw); 119 static int e1000_config_mac_to_phy(struct e1000_hw *hw); 120 static int e1000_config_fc_after_link_up(struct e1000_hw *hw); 121 static int e1000_check_for_link(struct eth_device *nic); 122 static int e1000_wait_autoneg(struct e1000_hw *hw); 123 static int e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t * speed, 124 uint16_t * duplex); 125 static int e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, 126 uint16_t * phy_data); 127 static int e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, 128 uint16_t phy_data); 129 static int32_t e1000_phy_hw_reset(struct e1000_hw *hw); 130 static int e1000_phy_reset(struct e1000_hw *hw); 131 static int e1000_detect_gig_phy(struct e1000_hw *hw); 132 static void e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw); 133 static void e1000_set_media_type(struct e1000_hw *hw); 134 135 static int32_t e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask); 136 static int32_t e1000_check_phy_reset_block(struct e1000_hw *hw); 137 138 static int32_t e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset, 139 uint16_t words, 140 uint16_t *data); 141 /****************************************************************************** 142 * Raises the EEPROM's clock input. 143 * 144 * hw - Struct containing variables accessed by shared code 145 * eecd - EECD's current value 146 *****************************************************************************/ 147 void e1000_raise_ee_clk(struct e1000_hw *hw, uint32_t * eecd) 148 { 149 /* Raise the clock input to the EEPROM (by setting the SK bit), and then 150 * wait 50 microseconds. 151 */ 152 *eecd = *eecd | E1000_EECD_SK; 153 E1000_WRITE_REG(hw, EECD, *eecd); 154 E1000_WRITE_FLUSH(hw); 155 udelay(50); 156 } 157 158 /****************************************************************************** 159 * Lowers the EEPROM's clock input. 160 * 161 * hw - Struct containing variables accessed by shared code 162 * eecd - EECD's current value 163 *****************************************************************************/ 164 void e1000_lower_ee_clk(struct e1000_hw *hw, uint32_t * eecd) 165 { 166 /* Lower the clock input to the EEPROM (by clearing the SK bit), and then 167 * wait 50 microseconds. 168 */ 169 *eecd = *eecd & ~E1000_EECD_SK; 170 E1000_WRITE_REG(hw, EECD, *eecd); 171 E1000_WRITE_FLUSH(hw); 172 udelay(50); 173 } 174 175 /****************************************************************************** 176 * Shift data bits out to the EEPROM. 177 * 178 * hw - Struct containing variables accessed by shared code 179 * data - data to send to the EEPROM 180 * count - number of bits to shift out 181 *****************************************************************************/ 182 static void 183 e1000_shift_out_ee_bits(struct e1000_hw *hw, uint16_t data, uint16_t count) 184 { 185 uint32_t eecd; 186 uint32_t mask; 187 188 /* We need to shift "count" bits out to the EEPROM. So, value in the 189 * "data" parameter will be shifted out to the EEPROM one bit at a time. 190 * In order to do this, "data" must be broken down into bits. 191 */ 192 mask = 0x01 << (count - 1); 193 eecd = E1000_READ_REG(hw, EECD); 194 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI); 195 do { 196 /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1", 197 * and then raising and then lowering the clock (the SK bit controls 198 * the clock input to the EEPROM). A "0" is shifted out to the EEPROM 199 * by setting "DI" to "0" and then raising and then lowering the clock. 200 */ 201 eecd &= ~E1000_EECD_DI; 202 203 if (data & mask) 204 eecd |= E1000_EECD_DI; 205 206 E1000_WRITE_REG(hw, EECD, eecd); 207 E1000_WRITE_FLUSH(hw); 208 209 udelay(50); 210 211 e1000_raise_ee_clk(hw, &eecd); 212 e1000_lower_ee_clk(hw, &eecd); 213 214 mask = mask >> 1; 215 216 } while (mask); 217 218 /* We leave the "DI" bit set to "0" when we leave this routine. */ 219 eecd &= ~E1000_EECD_DI; 220 E1000_WRITE_REG(hw, EECD, eecd); 221 } 222 223 /****************************************************************************** 224 * Shift data bits in from the EEPROM 225 * 226 * hw - Struct containing variables accessed by shared code 227 *****************************************************************************/ 228 static uint16_t 229 e1000_shift_in_ee_bits(struct e1000_hw *hw, uint16_t count) 230 { 231 uint32_t eecd; 232 uint32_t i; 233 uint16_t data; 234 235 /* In order to read a register from the EEPROM, we need to shift 'count' 236 * bits in from the EEPROM. Bits are "shifted in" by raising the clock 237 * input to the EEPROM (setting the SK bit), and then reading the 238 * value of the "DO" bit. During this "shifting in" process the 239 * "DI" bit should always be clear. 240 */ 241 242 eecd = E1000_READ_REG(hw, EECD); 243 244 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI); 245 data = 0; 246 247 for (i = 0; i < count; i++) { 248 data = data << 1; 249 e1000_raise_ee_clk(hw, &eecd); 250 251 eecd = E1000_READ_REG(hw, EECD); 252 253 eecd &= ~(E1000_EECD_DI); 254 if (eecd & E1000_EECD_DO) 255 data |= 1; 256 257 e1000_lower_ee_clk(hw, &eecd); 258 } 259 260 return data; 261 } 262 263 /****************************************************************************** 264 * Returns EEPROM to a "standby" state 265 * 266 * hw - Struct containing variables accessed by shared code 267 *****************************************************************************/ 268 void e1000_standby_eeprom(struct e1000_hw *hw) 269 { 270 struct e1000_eeprom_info *eeprom = &hw->eeprom; 271 uint32_t eecd; 272 273 eecd = E1000_READ_REG(hw, EECD); 274 275 if (eeprom->type == e1000_eeprom_microwire) { 276 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); 277 E1000_WRITE_REG(hw, EECD, eecd); 278 E1000_WRITE_FLUSH(hw); 279 udelay(eeprom->delay_usec); 280 281 /* Clock high */ 282 eecd |= E1000_EECD_SK; 283 E1000_WRITE_REG(hw, EECD, eecd); 284 E1000_WRITE_FLUSH(hw); 285 udelay(eeprom->delay_usec); 286 287 /* Select EEPROM */ 288 eecd |= E1000_EECD_CS; 289 E1000_WRITE_REG(hw, EECD, eecd); 290 E1000_WRITE_FLUSH(hw); 291 udelay(eeprom->delay_usec); 292 293 /* Clock low */ 294 eecd &= ~E1000_EECD_SK; 295 E1000_WRITE_REG(hw, EECD, eecd); 296 E1000_WRITE_FLUSH(hw); 297 udelay(eeprom->delay_usec); 298 } else if (eeprom->type == e1000_eeprom_spi) { 299 /* Toggle CS to flush commands */ 300 eecd |= E1000_EECD_CS; 301 E1000_WRITE_REG(hw, EECD, eecd); 302 E1000_WRITE_FLUSH(hw); 303 udelay(eeprom->delay_usec); 304 eecd &= ~E1000_EECD_CS; 305 E1000_WRITE_REG(hw, EECD, eecd); 306 E1000_WRITE_FLUSH(hw); 307 udelay(eeprom->delay_usec); 308 } 309 } 310 311 /*************************************************************************** 312 * Description: Determines if the onboard NVM is FLASH or EEPROM. 313 * 314 * hw - Struct containing variables accessed by shared code 315 ****************************************************************************/ 316 static boolean_t e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw) 317 { 318 uint32_t eecd = 0; 319 320 DEBUGFUNC(); 321 322 if (hw->mac_type == e1000_ich8lan) 323 return FALSE; 324 325 if (hw->mac_type == e1000_82573 || hw->mac_type == e1000_82574) { 326 eecd = E1000_READ_REG(hw, EECD); 327 328 /* Isolate bits 15 & 16 */ 329 eecd = ((eecd >> 15) & 0x03); 330 331 /* If both bits are set, device is Flash type */ 332 if (eecd == 0x03) 333 return FALSE; 334 } 335 return TRUE; 336 } 337 338 /****************************************************************************** 339 * Prepares EEPROM for access 340 * 341 * hw - Struct containing variables accessed by shared code 342 * 343 * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This 344 * function should be called before issuing a command to the EEPROM. 345 *****************************************************************************/ 346 int32_t e1000_acquire_eeprom(struct e1000_hw *hw) 347 { 348 struct e1000_eeprom_info *eeprom = &hw->eeprom; 349 uint32_t eecd, i = 0; 350 351 DEBUGFUNC(); 352 353 if (e1000_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM)) 354 return -E1000_ERR_SWFW_SYNC; 355 eecd = E1000_READ_REG(hw, EECD); 356 357 if (hw->mac_type != e1000_82573 || hw->mac_type != e1000_82574) { 358 /* Request EEPROM Access */ 359 if (hw->mac_type > e1000_82544) { 360 eecd |= E1000_EECD_REQ; 361 E1000_WRITE_REG(hw, EECD, eecd); 362 eecd = E1000_READ_REG(hw, EECD); 363 while ((!(eecd & E1000_EECD_GNT)) && 364 (i < E1000_EEPROM_GRANT_ATTEMPTS)) { 365 i++; 366 udelay(5); 367 eecd = E1000_READ_REG(hw, EECD); 368 } 369 if (!(eecd & E1000_EECD_GNT)) { 370 eecd &= ~E1000_EECD_REQ; 371 E1000_WRITE_REG(hw, EECD, eecd); 372 DEBUGOUT("Could not acquire EEPROM grant\n"); 373 return -E1000_ERR_EEPROM; 374 } 375 } 376 } 377 378 /* Setup EEPROM for Read/Write */ 379 380 if (eeprom->type == e1000_eeprom_microwire) { 381 /* Clear SK and DI */ 382 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK); 383 E1000_WRITE_REG(hw, EECD, eecd); 384 385 /* Set CS */ 386 eecd |= E1000_EECD_CS; 387 E1000_WRITE_REG(hw, EECD, eecd); 388 } else if (eeprom->type == e1000_eeprom_spi) { 389 /* Clear SK and CS */ 390 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); 391 E1000_WRITE_REG(hw, EECD, eecd); 392 udelay(1); 393 } 394 395 return E1000_SUCCESS; 396 } 397 398 /****************************************************************************** 399 * Sets up eeprom variables in the hw struct. Must be called after mac_type 400 * is configured. Additionally, if this is ICH8, the flash controller GbE 401 * registers must be mapped, or this will crash. 402 * 403 * hw - Struct containing variables accessed by shared code 404 *****************************************************************************/ 405 static int32_t e1000_init_eeprom_params(struct e1000_hw *hw) 406 { 407 struct e1000_eeprom_info *eeprom = &hw->eeprom; 408 uint32_t eecd = E1000_READ_REG(hw, EECD); 409 int32_t ret_val = E1000_SUCCESS; 410 uint16_t eeprom_size; 411 412 DEBUGFUNC(); 413 414 switch (hw->mac_type) { 415 case e1000_82542_rev2_0: 416 case e1000_82542_rev2_1: 417 case e1000_82543: 418 case e1000_82544: 419 eeprom->type = e1000_eeprom_microwire; 420 eeprom->word_size = 64; 421 eeprom->opcode_bits = 3; 422 eeprom->address_bits = 6; 423 eeprom->delay_usec = 50; 424 eeprom->use_eerd = FALSE; 425 eeprom->use_eewr = FALSE; 426 break; 427 case e1000_82540: 428 case e1000_82545: 429 case e1000_82545_rev_3: 430 case e1000_82546: 431 case e1000_82546_rev_3: 432 eeprom->type = e1000_eeprom_microwire; 433 eeprom->opcode_bits = 3; 434 eeprom->delay_usec = 50; 435 if (eecd & E1000_EECD_SIZE) { 436 eeprom->word_size = 256; 437 eeprom->address_bits = 8; 438 } else { 439 eeprom->word_size = 64; 440 eeprom->address_bits = 6; 441 } 442 eeprom->use_eerd = FALSE; 443 eeprom->use_eewr = FALSE; 444 break; 445 case e1000_82541: 446 case e1000_82541_rev_2: 447 case e1000_82547: 448 case e1000_82547_rev_2: 449 if (eecd & E1000_EECD_TYPE) { 450 eeprom->type = e1000_eeprom_spi; 451 eeprom->opcode_bits = 8; 452 eeprom->delay_usec = 1; 453 if (eecd & E1000_EECD_ADDR_BITS) { 454 eeprom->page_size = 32; 455 eeprom->address_bits = 16; 456 } else { 457 eeprom->page_size = 8; 458 eeprom->address_bits = 8; 459 } 460 } else { 461 eeprom->type = e1000_eeprom_microwire; 462 eeprom->opcode_bits = 3; 463 eeprom->delay_usec = 50; 464 if (eecd & E1000_EECD_ADDR_BITS) { 465 eeprom->word_size = 256; 466 eeprom->address_bits = 8; 467 } else { 468 eeprom->word_size = 64; 469 eeprom->address_bits = 6; 470 } 471 } 472 eeprom->use_eerd = FALSE; 473 eeprom->use_eewr = FALSE; 474 break; 475 case e1000_82571: 476 case e1000_82572: 477 eeprom->type = e1000_eeprom_spi; 478 eeprom->opcode_bits = 8; 479 eeprom->delay_usec = 1; 480 if (eecd & E1000_EECD_ADDR_BITS) { 481 eeprom->page_size = 32; 482 eeprom->address_bits = 16; 483 } else { 484 eeprom->page_size = 8; 485 eeprom->address_bits = 8; 486 } 487 eeprom->use_eerd = FALSE; 488 eeprom->use_eewr = FALSE; 489 break; 490 case e1000_82573: 491 case e1000_82574: 492 eeprom->type = e1000_eeprom_spi; 493 eeprom->opcode_bits = 8; 494 eeprom->delay_usec = 1; 495 if (eecd & E1000_EECD_ADDR_BITS) { 496 eeprom->page_size = 32; 497 eeprom->address_bits = 16; 498 } else { 499 eeprom->page_size = 8; 500 eeprom->address_bits = 8; 501 } 502 eeprom->use_eerd = TRUE; 503 eeprom->use_eewr = TRUE; 504 if (e1000_is_onboard_nvm_eeprom(hw) == FALSE) { 505 eeprom->type = e1000_eeprom_flash; 506 eeprom->word_size = 2048; 507 508 /* Ensure that the Autonomous FLASH update bit is cleared due to 509 * Flash update issue on parts which use a FLASH for NVM. */ 510 eecd &= ~E1000_EECD_AUPDEN; 511 E1000_WRITE_REG(hw, EECD, eecd); 512 } 513 break; 514 case e1000_80003es2lan: 515 eeprom->type = e1000_eeprom_spi; 516 eeprom->opcode_bits = 8; 517 eeprom->delay_usec = 1; 518 if (eecd & E1000_EECD_ADDR_BITS) { 519 eeprom->page_size = 32; 520 eeprom->address_bits = 16; 521 } else { 522 eeprom->page_size = 8; 523 eeprom->address_bits = 8; 524 } 525 eeprom->use_eerd = TRUE; 526 eeprom->use_eewr = FALSE; 527 break; 528 529 /* ich8lan does not support currently. if needed, please 530 * add corresponding code and functions. 531 */ 532 #if 0 533 case e1000_ich8lan: 534 { 535 int32_t i = 0; 536 537 eeprom->type = e1000_eeprom_ich8; 538 eeprom->use_eerd = FALSE; 539 eeprom->use_eewr = FALSE; 540 eeprom->word_size = E1000_SHADOW_RAM_WORDS; 541 uint32_t flash_size = E1000_READ_ICH_FLASH_REG(hw, 542 ICH_FLASH_GFPREG); 543 /* Zero the shadow RAM structure. But don't load it from NVM 544 * so as to save time for driver init */ 545 if (hw->eeprom_shadow_ram != NULL) { 546 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) { 547 hw->eeprom_shadow_ram[i].modified = FALSE; 548 hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF; 549 } 550 } 551 552 hw->flash_base_addr = (flash_size & ICH_GFPREG_BASE_MASK) * 553 ICH_FLASH_SECTOR_SIZE; 554 555 hw->flash_bank_size = ((flash_size >> 16) 556 & ICH_GFPREG_BASE_MASK) + 1; 557 hw->flash_bank_size -= (flash_size & ICH_GFPREG_BASE_MASK); 558 559 hw->flash_bank_size *= ICH_FLASH_SECTOR_SIZE; 560 561 hw->flash_bank_size /= 2 * sizeof(uint16_t); 562 break; 563 } 564 #endif 565 default: 566 break; 567 } 568 569 if (eeprom->type == e1000_eeprom_spi) { 570 /* eeprom_size will be an enum [0..8] that maps 571 * to eeprom sizes 128B to 572 * 32KB (incremented by powers of 2). 573 */ 574 if (hw->mac_type <= e1000_82547_rev_2) { 575 /* Set to default value for initial eeprom read. */ 576 eeprom->word_size = 64; 577 ret_val = e1000_read_eeprom(hw, EEPROM_CFG, 1, 578 &eeprom_size); 579 if (ret_val) 580 return ret_val; 581 eeprom_size = (eeprom_size & EEPROM_SIZE_MASK) 582 >> EEPROM_SIZE_SHIFT; 583 /* 256B eeprom size was not supported in earlier 584 * hardware, so we bump eeprom_size up one to 585 * ensure that "1" (which maps to 256B) is never 586 * the result used in the shifting logic below. */ 587 if (eeprom_size) 588 eeprom_size++; 589 } else { 590 eeprom_size = (uint16_t)((eecd & 591 E1000_EECD_SIZE_EX_MASK) >> 592 E1000_EECD_SIZE_EX_SHIFT); 593 } 594 595 eeprom->word_size = 1 << (eeprom_size + EEPROM_WORD_SIZE_SHIFT); 596 } 597 return ret_val; 598 } 599 600 /****************************************************************************** 601 * Polls the status bit (bit 1) of the EERD to determine when the read is done. 602 * 603 * hw - Struct containing variables accessed by shared code 604 *****************************************************************************/ 605 static int32_t 606 e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd) 607 { 608 uint32_t attempts = 100000; 609 uint32_t i, reg = 0; 610 int32_t done = E1000_ERR_EEPROM; 611 612 for (i = 0; i < attempts; i++) { 613 if (eerd == E1000_EEPROM_POLL_READ) 614 reg = E1000_READ_REG(hw, EERD); 615 else 616 reg = E1000_READ_REG(hw, EEWR); 617 618 if (reg & E1000_EEPROM_RW_REG_DONE) { 619 done = E1000_SUCCESS; 620 break; 621 } 622 udelay(5); 623 } 624 625 return done; 626 } 627 628 /****************************************************************************** 629 * Reads a 16 bit word from the EEPROM using the EERD register. 630 * 631 * hw - Struct containing variables accessed by shared code 632 * offset - offset of word in the EEPROM to read 633 * data - word read from the EEPROM 634 * words - number of words to read 635 *****************************************************************************/ 636 static int32_t 637 e1000_read_eeprom_eerd(struct e1000_hw *hw, 638 uint16_t offset, 639 uint16_t words, 640 uint16_t *data) 641 { 642 uint32_t i, eerd = 0; 643 int32_t error = 0; 644 645 for (i = 0; i < words; i++) { 646 eerd = ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) + 647 E1000_EEPROM_RW_REG_START; 648 649 E1000_WRITE_REG(hw, EERD, eerd); 650 error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_READ); 651 652 if (error) 653 break; 654 data[i] = (E1000_READ_REG(hw, EERD) >> 655 E1000_EEPROM_RW_REG_DATA); 656 657 } 658 659 return error; 660 } 661 662 void e1000_release_eeprom(struct e1000_hw *hw) 663 { 664 uint32_t eecd; 665 666 DEBUGFUNC(); 667 668 eecd = E1000_READ_REG(hw, EECD); 669 670 if (hw->eeprom.type == e1000_eeprom_spi) { 671 eecd |= E1000_EECD_CS; /* Pull CS high */ 672 eecd &= ~E1000_EECD_SK; /* Lower SCK */ 673 674 E1000_WRITE_REG(hw, EECD, eecd); 675 676 udelay(hw->eeprom.delay_usec); 677 } else if (hw->eeprom.type == e1000_eeprom_microwire) { 678 /* cleanup eeprom */ 679 680 /* CS on Microwire is active-high */ 681 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI); 682 683 E1000_WRITE_REG(hw, EECD, eecd); 684 685 /* Rising edge of clock */ 686 eecd |= E1000_EECD_SK; 687 E1000_WRITE_REG(hw, EECD, eecd); 688 E1000_WRITE_FLUSH(hw); 689 udelay(hw->eeprom.delay_usec); 690 691 /* Falling edge of clock */ 692 eecd &= ~E1000_EECD_SK; 693 E1000_WRITE_REG(hw, EECD, eecd); 694 E1000_WRITE_FLUSH(hw); 695 udelay(hw->eeprom.delay_usec); 696 } 697 698 /* Stop requesting EEPROM access */ 699 if (hw->mac_type > e1000_82544) { 700 eecd &= ~E1000_EECD_REQ; 701 E1000_WRITE_REG(hw, EECD, eecd); 702 } 703 } 704 /****************************************************************************** 705 * Reads a 16 bit word from the EEPROM. 706 * 707 * hw - Struct containing variables accessed by shared code 708 *****************************************************************************/ 709 static int32_t 710 e1000_spi_eeprom_ready(struct e1000_hw *hw) 711 { 712 uint16_t retry_count = 0; 713 uint8_t spi_stat_reg; 714 715 DEBUGFUNC(); 716 717 /* Read "Status Register" repeatedly until the LSB is cleared. The 718 * EEPROM will signal that the command has been completed by clearing 719 * bit 0 of the internal status register. If it's not cleared within 720 * 5 milliseconds, then error out. 721 */ 722 retry_count = 0; 723 do { 724 e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI, 725 hw->eeprom.opcode_bits); 726 spi_stat_reg = (uint8_t)e1000_shift_in_ee_bits(hw, 8); 727 if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI)) 728 break; 729 730 udelay(5); 731 retry_count += 5; 732 733 e1000_standby_eeprom(hw); 734 } while (retry_count < EEPROM_MAX_RETRY_SPI); 735 736 /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and 737 * only 0-5mSec on 5V devices) 738 */ 739 if (retry_count >= EEPROM_MAX_RETRY_SPI) { 740 DEBUGOUT("SPI EEPROM Status error\n"); 741 return -E1000_ERR_EEPROM; 742 } 743 744 return E1000_SUCCESS; 745 } 746 747 /****************************************************************************** 748 * Reads a 16 bit word from the EEPROM. 749 * 750 * hw - Struct containing variables accessed by shared code 751 * offset - offset of word in the EEPROM to read 752 * data - word read from the EEPROM 753 *****************************************************************************/ 754 static int32_t 755 e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset, 756 uint16_t words, uint16_t *data) 757 { 758 struct e1000_eeprom_info *eeprom = &hw->eeprom; 759 uint32_t i = 0; 760 761 DEBUGFUNC(); 762 763 /* If eeprom is not yet detected, do so now */ 764 if (eeprom->word_size == 0) 765 e1000_init_eeprom_params(hw); 766 767 /* A check for invalid values: offset too large, too many words, 768 * and not enough words. 769 */ 770 if ((offset >= eeprom->word_size) || 771 (words > eeprom->word_size - offset) || 772 (words == 0)) { 773 DEBUGOUT("\"words\" parameter out of bounds." 774 "Words = %d, size = %d\n", offset, eeprom->word_size); 775 return -E1000_ERR_EEPROM; 776 } 777 778 /* EEPROM's that don't use EERD to read require us to bit-bang the SPI 779 * directly. In this case, we need to acquire the EEPROM so that 780 * FW or other port software does not interrupt. 781 */ 782 if (e1000_is_onboard_nvm_eeprom(hw) == TRUE && 783 hw->eeprom.use_eerd == FALSE) { 784 785 /* Prepare the EEPROM for bit-bang reading */ 786 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS) 787 return -E1000_ERR_EEPROM; 788 } 789 790 /* Eerd register EEPROM access requires no eeprom aquire/release */ 791 if (eeprom->use_eerd == TRUE) 792 return e1000_read_eeprom_eerd(hw, offset, words, data); 793 794 /* ich8lan does not support currently. if needed, please 795 * add corresponding code and functions. 796 */ 797 #if 0 798 /* ICH EEPROM access is done via the ICH flash controller */ 799 if (eeprom->type == e1000_eeprom_ich8) 800 return e1000_read_eeprom_ich8(hw, offset, words, data); 801 #endif 802 /* Set up the SPI or Microwire EEPROM for bit-bang reading. We have 803 * acquired the EEPROM at this point, so any returns should relase it */ 804 if (eeprom->type == e1000_eeprom_spi) { 805 uint16_t word_in; 806 uint8_t read_opcode = EEPROM_READ_OPCODE_SPI; 807 808 if (e1000_spi_eeprom_ready(hw)) { 809 e1000_release_eeprom(hw); 810 return -E1000_ERR_EEPROM; 811 } 812 813 e1000_standby_eeprom(hw); 814 815 /* Some SPI eeproms use the 8th address bit embedded in 816 * the opcode */ 817 if ((eeprom->address_bits == 8) && (offset >= 128)) 818 read_opcode |= EEPROM_A8_OPCODE_SPI; 819 820 /* Send the READ command (opcode + addr) */ 821 e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits); 822 e1000_shift_out_ee_bits(hw, (uint16_t)(offset*2), 823 eeprom->address_bits); 824 825 /* Read the data. The address of the eeprom internally 826 * increments with each byte (spi) being read, saving on the 827 * overhead of eeprom setup and tear-down. The address 828 * counter will roll over if reading beyond the size of 829 * the eeprom, thus allowing the entire memory to be read 830 * starting from any offset. */ 831 for (i = 0; i < words; i++) { 832 word_in = e1000_shift_in_ee_bits(hw, 16); 833 data[i] = (word_in >> 8) | (word_in << 8); 834 } 835 } else if (eeprom->type == e1000_eeprom_microwire) { 836 for (i = 0; i < words; i++) { 837 /* Send the READ command (opcode + addr) */ 838 e1000_shift_out_ee_bits(hw, 839 EEPROM_READ_OPCODE_MICROWIRE, 840 eeprom->opcode_bits); 841 e1000_shift_out_ee_bits(hw, (uint16_t)(offset + i), 842 eeprom->address_bits); 843 844 /* Read the data. For microwire, each word requires 845 * the overhead of eeprom setup and tear-down. */ 846 data[i] = e1000_shift_in_ee_bits(hw, 16); 847 e1000_standby_eeprom(hw); 848 } 849 } 850 851 /* End this read operation */ 852 e1000_release_eeprom(hw); 853 854 return E1000_SUCCESS; 855 } 856 857 /****************************************************************************** 858 * Verifies that the EEPROM has a valid checksum 859 * 860 * hw - Struct containing variables accessed by shared code 861 * 862 * Reads the first 64 16 bit words of the EEPROM and sums the values read. 863 * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is 864 * valid. 865 *****************************************************************************/ 866 static int e1000_validate_eeprom_checksum(struct e1000_hw *hw) 867 { 868 uint16_t i, checksum, checksum_reg, *buf; 869 870 DEBUGFUNC(); 871 872 /* Allocate a temporary buffer */ 873 buf = malloc(sizeof(buf[0]) * (EEPROM_CHECKSUM_REG + 1)); 874 if (!buf) { 875 E1000_ERR(hw->nic, "Unable to allocate EEPROM buffer!\n"); 876 return -E1000_ERR_EEPROM; 877 } 878 879 /* Read the EEPROM */ 880 if (e1000_read_eeprom(hw, 0, EEPROM_CHECKSUM_REG + 1, buf) < 0) { 881 E1000_ERR(hw->nic, "Unable to read EEPROM!\n"); 882 return -E1000_ERR_EEPROM; 883 } 884 885 /* Compute the checksum */ 886 checksum = 0; 887 for (i = 0; i < EEPROM_CHECKSUM_REG; i++) 888 checksum += buf[i]; 889 checksum = ((uint16_t)EEPROM_SUM) - checksum; 890 checksum_reg = buf[i]; 891 892 /* Verify it! */ 893 if (checksum == checksum_reg) 894 return 0; 895 896 /* Hrm, verification failed, print an error */ 897 E1000_ERR(hw->nic, "EEPROM checksum is incorrect!\n"); 898 E1000_ERR(hw->nic, " ...register was 0x%04hx, calculated 0x%04hx\n", 899 checksum_reg, checksum); 900 901 return -E1000_ERR_EEPROM; 902 } 903 904 /***************************************************************************** 905 * Set PHY to class A mode 906 * Assumes the following operations will follow to enable the new class mode. 907 * 1. Do a PHY soft reset 908 * 2. Restart auto-negotiation or force link. 909 * 910 * hw - Struct containing variables accessed by shared code 911 ****************************************************************************/ 912 static int32_t 913 e1000_set_phy_mode(struct e1000_hw *hw) 914 { 915 int32_t ret_val; 916 uint16_t eeprom_data; 917 918 DEBUGFUNC(); 919 920 if ((hw->mac_type == e1000_82545_rev_3) && 921 (hw->media_type == e1000_media_type_copper)) { 922 ret_val = e1000_read_eeprom(hw, EEPROM_PHY_CLASS_WORD, 923 1, &eeprom_data); 924 if (ret_val) 925 return ret_val; 926 927 if ((eeprom_data != EEPROM_RESERVED_WORD) && 928 (eeprom_data & EEPROM_PHY_CLASS_A)) { 929 ret_val = e1000_write_phy_reg(hw, 930 M88E1000_PHY_PAGE_SELECT, 0x000B); 931 if (ret_val) 932 return ret_val; 933 ret_val = e1000_write_phy_reg(hw, 934 M88E1000_PHY_GEN_CONTROL, 0x8104); 935 if (ret_val) 936 return ret_val; 937 938 hw->phy_reset_disable = FALSE; 939 } 940 } 941 942 return E1000_SUCCESS; 943 } 944 945 /*************************************************************************** 946 * 947 * Obtaining software semaphore bit (SMBI) before resetting PHY. 948 * 949 * hw: Struct containing variables accessed by shared code 950 * 951 * returns: - E1000_ERR_RESET if fail to obtain semaphore. 952 * E1000_SUCCESS at any other case. 953 * 954 ***************************************************************************/ 955 static int32_t 956 e1000_get_software_semaphore(struct e1000_hw *hw) 957 { 958 int32_t timeout = hw->eeprom.word_size + 1; 959 uint32_t swsm; 960 961 DEBUGFUNC(); 962 963 if (hw->mac_type != e1000_80003es2lan) 964 return E1000_SUCCESS; 965 966 while (timeout) { 967 swsm = E1000_READ_REG(hw, SWSM); 968 /* If SMBI bit cleared, it is now set and we hold 969 * the semaphore */ 970 if (!(swsm & E1000_SWSM_SMBI)) 971 break; 972 mdelay(1); 973 timeout--; 974 } 975 976 if (!timeout) { 977 DEBUGOUT("Driver can't access device - SMBI bit is set.\n"); 978 return -E1000_ERR_RESET; 979 } 980 981 return E1000_SUCCESS; 982 } 983 984 /*************************************************************************** 985 * This function clears HW semaphore bits. 986 * 987 * hw: Struct containing variables accessed by shared code 988 * 989 * returns: - None. 990 * 991 ***************************************************************************/ 992 static void 993 e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw) 994 { 995 uint32_t swsm; 996 997 DEBUGFUNC(); 998 999 if (!hw->eeprom_semaphore_present) 1000 return; 1001 1002 swsm = E1000_READ_REG(hw, SWSM); 1003 if (hw->mac_type == e1000_80003es2lan) { 1004 /* Release both semaphores. */ 1005 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI); 1006 } else 1007 swsm &= ~(E1000_SWSM_SWESMBI); 1008 E1000_WRITE_REG(hw, SWSM, swsm); 1009 } 1010 1011 /*************************************************************************** 1012 * 1013 * Using the combination of SMBI and SWESMBI semaphore bits when resetting 1014 * adapter or Eeprom access. 1015 * 1016 * hw: Struct containing variables accessed by shared code 1017 * 1018 * returns: - E1000_ERR_EEPROM if fail to access EEPROM. 1019 * E1000_SUCCESS at any other case. 1020 * 1021 ***************************************************************************/ 1022 static int32_t 1023 e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw) 1024 { 1025 int32_t timeout; 1026 uint32_t swsm; 1027 1028 DEBUGFUNC(); 1029 1030 if (!hw->eeprom_semaphore_present) 1031 return E1000_SUCCESS; 1032 1033 if (hw->mac_type == e1000_80003es2lan) { 1034 /* Get the SW semaphore. */ 1035 if (e1000_get_software_semaphore(hw) != E1000_SUCCESS) 1036 return -E1000_ERR_EEPROM; 1037 } 1038 1039 /* Get the FW semaphore. */ 1040 timeout = hw->eeprom.word_size + 1; 1041 while (timeout) { 1042 swsm = E1000_READ_REG(hw, SWSM); 1043 swsm |= E1000_SWSM_SWESMBI; 1044 E1000_WRITE_REG(hw, SWSM, swsm); 1045 /* if we managed to set the bit we got the semaphore. */ 1046 swsm = E1000_READ_REG(hw, SWSM); 1047 if (swsm & E1000_SWSM_SWESMBI) 1048 break; 1049 1050 udelay(50); 1051 timeout--; 1052 } 1053 1054 if (!timeout) { 1055 /* Release semaphores */ 1056 e1000_put_hw_eeprom_semaphore(hw); 1057 DEBUGOUT("Driver can't access the Eeprom - " 1058 "SWESMBI bit is set.\n"); 1059 return -E1000_ERR_EEPROM; 1060 } 1061 1062 return E1000_SUCCESS; 1063 } 1064 1065 static int32_t 1066 e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask) 1067 { 1068 uint32_t swfw_sync = 0; 1069 uint32_t swmask = mask; 1070 uint32_t fwmask = mask << 16; 1071 int32_t timeout = 200; 1072 1073 DEBUGFUNC(); 1074 while (timeout) { 1075 if (e1000_get_hw_eeprom_semaphore(hw)) 1076 return -E1000_ERR_SWFW_SYNC; 1077 1078 swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC); 1079 if (!(swfw_sync & (fwmask | swmask))) 1080 break; 1081 1082 /* firmware currently using resource (fwmask) */ 1083 /* or other software thread currently using resource (swmask) */ 1084 e1000_put_hw_eeprom_semaphore(hw); 1085 mdelay(5); 1086 timeout--; 1087 } 1088 1089 if (!timeout) { 1090 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n"); 1091 return -E1000_ERR_SWFW_SYNC; 1092 } 1093 1094 swfw_sync |= swmask; 1095 E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync); 1096 1097 e1000_put_hw_eeprom_semaphore(hw); 1098 return E1000_SUCCESS; 1099 } 1100 1101 static boolean_t e1000_is_second_port(struct e1000_hw *hw) 1102 { 1103 switch (hw->mac_type) { 1104 case e1000_80003es2lan: 1105 case e1000_82546: 1106 case e1000_82571: 1107 if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1) 1108 return TRUE; 1109 /* Fallthrough */ 1110 default: 1111 return FALSE; 1112 } 1113 } 1114 1115 /****************************************************************************** 1116 * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the 1117 * second function of dual function devices 1118 * 1119 * nic - Struct containing variables accessed by shared code 1120 *****************************************************************************/ 1121 static int 1122 e1000_read_mac_addr(struct eth_device *nic) 1123 { 1124 struct e1000_hw *hw = nic->priv; 1125 uint16_t offset; 1126 uint16_t eeprom_data; 1127 int i; 1128 1129 DEBUGFUNC(); 1130 1131 for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) { 1132 offset = i >> 1; 1133 if (e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) { 1134 DEBUGOUT("EEPROM Read Error\n"); 1135 return -E1000_ERR_EEPROM; 1136 } 1137 nic->enetaddr[i] = eeprom_data & 0xff; 1138 nic->enetaddr[i + 1] = (eeprom_data >> 8) & 0xff; 1139 } 1140 1141 /* Invert the last bit if this is the second device */ 1142 if (e1000_is_second_port(hw)) 1143 nic->enetaddr[5] ^= 1; 1144 1145 #ifdef CONFIG_E1000_FALLBACK_MAC 1146 if (!is_valid_ether_addr(nic->enetaddr)) { 1147 unsigned char fb_mac[NODE_ADDRESS_SIZE] = CONFIG_E1000_FALLBACK_MAC; 1148 1149 memcpy (nic->enetaddr, fb_mac, NODE_ADDRESS_SIZE); 1150 } 1151 #endif 1152 return 0; 1153 } 1154 1155 /****************************************************************************** 1156 * Initializes receive address filters. 1157 * 1158 * hw - Struct containing variables accessed by shared code 1159 * 1160 * Places the MAC address in receive address register 0 and clears the rest 1161 * of the receive addresss registers. Clears the multicast table. Assumes 1162 * the receiver is in reset when the routine is called. 1163 *****************************************************************************/ 1164 static void 1165 e1000_init_rx_addrs(struct eth_device *nic) 1166 { 1167 struct e1000_hw *hw = nic->priv; 1168 uint32_t i; 1169 uint32_t addr_low; 1170 uint32_t addr_high; 1171 1172 DEBUGFUNC(); 1173 1174 /* Setup the receive address. */ 1175 DEBUGOUT("Programming MAC Address into RAR[0]\n"); 1176 addr_low = (nic->enetaddr[0] | 1177 (nic->enetaddr[1] << 8) | 1178 (nic->enetaddr[2] << 16) | (nic->enetaddr[3] << 24)); 1179 1180 addr_high = (nic->enetaddr[4] | (nic->enetaddr[5] << 8) | E1000_RAH_AV); 1181 1182 E1000_WRITE_REG_ARRAY(hw, RA, 0, addr_low); 1183 E1000_WRITE_REG_ARRAY(hw, RA, 1, addr_high); 1184 1185 /* Zero out the other 15 receive addresses. */ 1186 DEBUGOUT("Clearing RAR[1-15]\n"); 1187 for (i = 1; i < E1000_RAR_ENTRIES; i++) { 1188 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0); 1189 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0); 1190 } 1191 } 1192 1193 /****************************************************************************** 1194 * Clears the VLAN filer table 1195 * 1196 * hw - Struct containing variables accessed by shared code 1197 *****************************************************************************/ 1198 static void 1199 e1000_clear_vfta(struct e1000_hw *hw) 1200 { 1201 uint32_t offset; 1202 1203 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) 1204 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, 0); 1205 } 1206 1207 /****************************************************************************** 1208 * Set the mac type member in the hw struct. 1209 * 1210 * hw - Struct containing variables accessed by shared code 1211 *****************************************************************************/ 1212 int32_t 1213 e1000_set_mac_type(struct e1000_hw *hw) 1214 { 1215 DEBUGFUNC(); 1216 1217 switch (hw->device_id) { 1218 case E1000_DEV_ID_82542: 1219 switch (hw->revision_id) { 1220 case E1000_82542_2_0_REV_ID: 1221 hw->mac_type = e1000_82542_rev2_0; 1222 break; 1223 case E1000_82542_2_1_REV_ID: 1224 hw->mac_type = e1000_82542_rev2_1; 1225 break; 1226 default: 1227 /* Invalid 82542 revision ID */ 1228 return -E1000_ERR_MAC_TYPE; 1229 } 1230 break; 1231 case E1000_DEV_ID_82543GC_FIBER: 1232 case E1000_DEV_ID_82543GC_COPPER: 1233 hw->mac_type = e1000_82543; 1234 break; 1235 case E1000_DEV_ID_82544EI_COPPER: 1236 case E1000_DEV_ID_82544EI_FIBER: 1237 case E1000_DEV_ID_82544GC_COPPER: 1238 case E1000_DEV_ID_82544GC_LOM: 1239 hw->mac_type = e1000_82544; 1240 break; 1241 case E1000_DEV_ID_82540EM: 1242 case E1000_DEV_ID_82540EM_LOM: 1243 case E1000_DEV_ID_82540EP: 1244 case E1000_DEV_ID_82540EP_LOM: 1245 case E1000_DEV_ID_82540EP_LP: 1246 hw->mac_type = e1000_82540; 1247 break; 1248 case E1000_DEV_ID_82545EM_COPPER: 1249 case E1000_DEV_ID_82545EM_FIBER: 1250 hw->mac_type = e1000_82545; 1251 break; 1252 case E1000_DEV_ID_82545GM_COPPER: 1253 case E1000_DEV_ID_82545GM_FIBER: 1254 case E1000_DEV_ID_82545GM_SERDES: 1255 hw->mac_type = e1000_82545_rev_3; 1256 break; 1257 case E1000_DEV_ID_82546EB_COPPER: 1258 case E1000_DEV_ID_82546EB_FIBER: 1259 case E1000_DEV_ID_82546EB_QUAD_COPPER: 1260 hw->mac_type = e1000_82546; 1261 break; 1262 case E1000_DEV_ID_82546GB_COPPER: 1263 case E1000_DEV_ID_82546GB_FIBER: 1264 case E1000_DEV_ID_82546GB_SERDES: 1265 case E1000_DEV_ID_82546GB_PCIE: 1266 case E1000_DEV_ID_82546GB_QUAD_COPPER: 1267 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3: 1268 hw->mac_type = e1000_82546_rev_3; 1269 break; 1270 case E1000_DEV_ID_82541EI: 1271 case E1000_DEV_ID_82541EI_MOBILE: 1272 case E1000_DEV_ID_82541ER_LOM: 1273 hw->mac_type = e1000_82541; 1274 break; 1275 case E1000_DEV_ID_82541ER: 1276 case E1000_DEV_ID_82541GI: 1277 case E1000_DEV_ID_82541GI_LF: 1278 case E1000_DEV_ID_82541GI_MOBILE: 1279 hw->mac_type = e1000_82541_rev_2; 1280 break; 1281 case E1000_DEV_ID_82547EI: 1282 case E1000_DEV_ID_82547EI_MOBILE: 1283 hw->mac_type = e1000_82547; 1284 break; 1285 case E1000_DEV_ID_82547GI: 1286 hw->mac_type = e1000_82547_rev_2; 1287 break; 1288 case E1000_DEV_ID_82571EB_COPPER: 1289 case E1000_DEV_ID_82571EB_FIBER: 1290 case E1000_DEV_ID_82571EB_SERDES: 1291 case E1000_DEV_ID_82571EB_SERDES_DUAL: 1292 case E1000_DEV_ID_82571EB_SERDES_QUAD: 1293 case E1000_DEV_ID_82571EB_QUAD_COPPER: 1294 case E1000_DEV_ID_82571PT_QUAD_COPPER: 1295 case E1000_DEV_ID_82571EB_QUAD_FIBER: 1296 case E1000_DEV_ID_82571EB_QUAD_COPPER_LOWPROFILE: 1297 hw->mac_type = e1000_82571; 1298 break; 1299 case E1000_DEV_ID_82572EI_COPPER: 1300 case E1000_DEV_ID_82572EI_FIBER: 1301 case E1000_DEV_ID_82572EI_SERDES: 1302 case E1000_DEV_ID_82572EI: 1303 hw->mac_type = e1000_82572; 1304 break; 1305 case E1000_DEV_ID_82573E: 1306 case E1000_DEV_ID_82573E_IAMT: 1307 case E1000_DEV_ID_82573L: 1308 hw->mac_type = e1000_82573; 1309 break; 1310 case E1000_DEV_ID_82574L: 1311 hw->mac_type = e1000_82574; 1312 break; 1313 case E1000_DEV_ID_80003ES2LAN_COPPER_SPT: 1314 case E1000_DEV_ID_80003ES2LAN_SERDES_SPT: 1315 case E1000_DEV_ID_80003ES2LAN_COPPER_DPT: 1316 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT: 1317 hw->mac_type = e1000_80003es2lan; 1318 break; 1319 case E1000_DEV_ID_ICH8_IGP_M_AMT: 1320 case E1000_DEV_ID_ICH8_IGP_AMT: 1321 case E1000_DEV_ID_ICH8_IGP_C: 1322 case E1000_DEV_ID_ICH8_IFE: 1323 case E1000_DEV_ID_ICH8_IFE_GT: 1324 case E1000_DEV_ID_ICH8_IFE_G: 1325 case E1000_DEV_ID_ICH8_IGP_M: 1326 hw->mac_type = e1000_ich8lan; 1327 break; 1328 default: 1329 /* Should never have loaded on this device */ 1330 return -E1000_ERR_MAC_TYPE; 1331 } 1332 return E1000_SUCCESS; 1333 } 1334 1335 /****************************************************************************** 1336 * Reset the transmit and receive units; mask and clear all interrupts. 1337 * 1338 * hw - Struct containing variables accessed by shared code 1339 *****************************************************************************/ 1340 void 1341 e1000_reset_hw(struct e1000_hw *hw) 1342 { 1343 uint32_t ctrl; 1344 uint32_t ctrl_ext; 1345 uint32_t manc; 1346 uint32_t pba = 0; 1347 1348 DEBUGFUNC(); 1349 1350 /* get the correct pba value for both PCI and PCIe*/ 1351 if (hw->mac_type < e1000_82571) 1352 pba = E1000_DEFAULT_PCI_PBA; 1353 else 1354 pba = E1000_DEFAULT_PCIE_PBA; 1355 1356 /* For 82542 (rev 2.0), disable MWI before issuing a device reset */ 1357 if (hw->mac_type == e1000_82542_rev2_0) { 1358 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n"); 1359 pci_write_config_word(hw->pdev, PCI_COMMAND, 1360 hw->pci_cmd_word & ~PCI_COMMAND_INVALIDATE); 1361 } 1362 1363 /* Clear interrupt mask to stop board from generating interrupts */ 1364 DEBUGOUT("Masking off all interrupts\n"); 1365 E1000_WRITE_REG(hw, IMC, 0xffffffff); 1366 1367 /* Disable the Transmit and Receive units. Then delay to allow 1368 * any pending transactions to complete before we hit the MAC with 1369 * the global reset. 1370 */ 1371 E1000_WRITE_REG(hw, RCTL, 0); 1372 E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP); 1373 E1000_WRITE_FLUSH(hw); 1374 1375 /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */ 1376 hw->tbi_compatibility_on = FALSE; 1377 1378 /* Delay to allow any outstanding PCI transactions to complete before 1379 * resetting the device 1380 */ 1381 mdelay(10); 1382 1383 /* Issue a global reset to the MAC. This will reset the chip's 1384 * transmit, receive, DMA, and link units. It will not effect 1385 * the current PCI configuration. The global reset bit is self- 1386 * clearing, and should clear within a microsecond. 1387 */ 1388 DEBUGOUT("Issuing a global reset to MAC\n"); 1389 ctrl = E1000_READ_REG(hw, CTRL); 1390 1391 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST)); 1392 1393 /* Force a reload from the EEPROM if necessary */ 1394 if (hw->mac_type < e1000_82540) { 1395 /* Wait for reset to complete */ 1396 udelay(10); 1397 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 1398 ctrl_ext |= E1000_CTRL_EXT_EE_RST; 1399 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 1400 E1000_WRITE_FLUSH(hw); 1401 /* Wait for EEPROM reload */ 1402 mdelay(2); 1403 } else { 1404 /* Wait for EEPROM reload (it happens automatically) */ 1405 mdelay(4); 1406 /* Dissable HW ARPs on ASF enabled adapters */ 1407 manc = E1000_READ_REG(hw, MANC); 1408 manc &= ~(E1000_MANC_ARP_EN); 1409 E1000_WRITE_REG(hw, MANC, manc); 1410 } 1411 1412 /* Clear interrupt mask to stop board from generating interrupts */ 1413 DEBUGOUT("Masking off all interrupts\n"); 1414 E1000_WRITE_REG(hw, IMC, 0xffffffff); 1415 1416 /* Clear any pending interrupt events. */ 1417 E1000_READ_REG(hw, ICR); 1418 1419 /* If MWI was previously enabled, reenable it. */ 1420 if (hw->mac_type == e1000_82542_rev2_0) { 1421 pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word); 1422 } 1423 E1000_WRITE_REG(hw, PBA, pba); 1424 } 1425 1426 /****************************************************************************** 1427 * 1428 * Initialize a number of hardware-dependent bits 1429 * 1430 * hw: Struct containing variables accessed by shared code 1431 * 1432 * This function contains hardware limitation workarounds for PCI-E adapters 1433 * 1434 *****************************************************************************/ 1435 static void 1436 e1000_initialize_hardware_bits(struct e1000_hw *hw) 1437 { 1438 if ((hw->mac_type >= e1000_82571) && 1439 (!hw->initialize_hw_bits_disable)) { 1440 /* Settings common to all PCI-express silicon */ 1441 uint32_t reg_ctrl, reg_ctrl_ext; 1442 uint32_t reg_tarc0, reg_tarc1; 1443 uint32_t reg_tctl; 1444 uint32_t reg_txdctl, reg_txdctl1; 1445 1446 /* link autonegotiation/sync workarounds */ 1447 reg_tarc0 = E1000_READ_REG(hw, TARC0); 1448 reg_tarc0 &= ~((1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)); 1449 1450 /* Enable not-done TX descriptor counting */ 1451 reg_txdctl = E1000_READ_REG(hw, TXDCTL); 1452 reg_txdctl |= E1000_TXDCTL_COUNT_DESC; 1453 E1000_WRITE_REG(hw, TXDCTL, reg_txdctl); 1454 1455 reg_txdctl1 = E1000_READ_REG(hw, TXDCTL1); 1456 reg_txdctl1 |= E1000_TXDCTL_COUNT_DESC; 1457 E1000_WRITE_REG(hw, TXDCTL1, reg_txdctl1); 1458 1459 switch (hw->mac_type) { 1460 case e1000_82571: 1461 case e1000_82572: 1462 /* Clear PHY TX compatible mode bits */ 1463 reg_tarc1 = E1000_READ_REG(hw, TARC1); 1464 reg_tarc1 &= ~((1 << 30)|(1 << 29)); 1465 1466 /* link autonegotiation/sync workarounds */ 1467 reg_tarc0 |= ((1 << 26)|(1 << 25)|(1 << 24)|(1 << 23)); 1468 1469 /* TX ring control fixes */ 1470 reg_tarc1 |= ((1 << 26)|(1 << 25)|(1 << 24)); 1471 1472 /* Multiple read bit is reversed polarity */ 1473 reg_tctl = E1000_READ_REG(hw, TCTL); 1474 if (reg_tctl & E1000_TCTL_MULR) 1475 reg_tarc1 &= ~(1 << 28); 1476 else 1477 reg_tarc1 |= (1 << 28); 1478 1479 E1000_WRITE_REG(hw, TARC1, reg_tarc1); 1480 break; 1481 case e1000_82573: 1482 case e1000_82574: 1483 reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 1484 reg_ctrl_ext &= ~(1 << 23); 1485 reg_ctrl_ext |= (1 << 22); 1486 1487 /* TX byte count fix */ 1488 reg_ctrl = E1000_READ_REG(hw, CTRL); 1489 reg_ctrl &= ~(1 << 29); 1490 1491 E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext); 1492 E1000_WRITE_REG(hw, CTRL, reg_ctrl); 1493 break; 1494 case e1000_80003es2lan: 1495 /* improve small packet performace for fiber/serdes */ 1496 if ((hw->media_type == e1000_media_type_fiber) 1497 || (hw->media_type == 1498 e1000_media_type_internal_serdes)) { 1499 reg_tarc0 &= ~(1 << 20); 1500 } 1501 1502 /* Multiple read bit is reversed polarity */ 1503 reg_tctl = E1000_READ_REG(hw, TCTL); 1504 reg_tarc1 = E1000_READ_REG(hw, TARC1); 1505 if (reg_tctl & E1000_TCTL_MULR) 1506 reg_tarc1 &= ~(1 << 28); 1507 else 1508 reg_tarc1 |= (1 << 28); 1509 1510 E1000_WRITE_REG(hw, TARC1, reg_tarc1); 1511 break; 1512 case e1000_ich8lan: 1513 /* Reduce concurrent DMA requests to 3 from 4 */ 1514 if ((hw->revision_id < 3) || 1515 ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) && 1516 (hw->device_id != E1000_DEV_ID_ICH8_IGP_M))) 1517 reg_tarc0 |= ((1 << 29)|(1 << 28)); 1518 1519 reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 1520 reg_ctrl_ext |= (1 << 22); 1521 E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext); 1522 1523 /* workaround TX hang with TSO=on */ 1524 reg_tarc0 |= ((1 << 27)|(1 << 26)|(1 << 24)|(1 << 23)); 1525 1526 /* Multiple read bit is reversed polarity */ 1527 reg_tctl = E1000_READ_REG(hw, TCTL); 1528 reg_tarc1 = E1000_READ_REG(hw, TARC1); 1529 if (reg_tctl & E1000_TCTL_MULR) 1530 reg_tarc1 &= ~(1 << 28); 1531 else 1532 reg_tarc1 |= (1 << 28); 1533 1534 /* workaround TX hang with TSO=on */ 1535 reg_tarc1 |= ((1 << 30)|(1 << 26)|(1 << 24)); 1536 1537 E1000_WRITE_REG(hw, TARC1, reg_tarc1); 1538 break; 1539 default: 1540 break; 1541 } 1542 1543 E1000_WRITE_REG(hw, TARC0, reg_tarc0); 1544 } 1545 } 1546 1547 /****************************************************************************** 1548 * Performs basic configuration of the adapter. 1549 * 1550 * hw - Struct containing variables accessed by shared code 1551 * 1552 * Assumes that the controller has previously been reset and is in a 1553 * post-reset uninitialized state. Initializes the receive address registers, 1554 * multicast table, and VLAN filter table. Calls routines to setup link 1555 * configuration and flow control settings. Clears all on-chip counters. Leaves 1556 * the transmit and receive units disabled and uninitialized. 1557 *****************************************************************************/ 1558 static int 1559 e1000_init_hw(struct eth_device *nic) 1560 { 1561 struct e1000_hw *hw = nic->priv; 1562 uint32_t ctrl; 1563 uint32_t i; 1564 int32_t ret_val; 1565 uint16_t pcix_cmd_word; 1566 uint16_t pcix_stat_hi_word; 1567 uint16_t cmd_mmrbc; 1568 uint16_t stat_mmrbc; 1569 uint32_t mta_size; 1570 uint32_t reg_data; 1571 uint32_t ctrl_ext; 1572 DEBUGFUNC(); 1573 /* force full DMA clock frequency for 10/100 on ICH8 A0-B0 */ 1574 if ((hw->mac_type == e1000_ich8lan) && 1575 ((hw->revision_id < 3) || 1576 ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) && 1577 (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))) { 1578 reg_data = E1000_READ_REG(hw, STATUS); 1579 reg_data &= ~0x80000000; 1580 E1000_WRITE_REG(hw, STATUS, reg_data); 1581 } 1582 /* Do not need initialize Identification LED */ 1583 1584 /* Set the media type and TBI compatibility */ 1585 e1000_set_media_type(hw); 1586 1587 /* Must be called after e1000_set_media_type 1588 * because media_type is used */ 1589 e1000_initialize_hardware_bits(hw); 1590 1591 /* Disabling VLAN filtering. */ 1592 DEBUGOUT("Initializing the IEEE VLAN\n"); 1593 /* VET hardcoded to standard value and VFTA removed in ICH8 LAN */ 1594 if (hw->mac_type != e1000_ich8lan) { 1595 if (hw->mac_type < e1000_82545_rev_3) 1596 E1000_WRITE_REG(hw, VET, 0); 1597 e1000_clear_vfta(hw); 1598 } 1599 1600 /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */ 1601 if (hw->mac_type == e1000_82542_rev2_0) { 1602 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n"); 1603 pci_write_config_word(hw->pdev, PCI_COMMAND, 1604 hw-> 1605 pci_cmd_word & ~PCI_COMMAND_INVALIDATE); 1606 E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST); 1607 E1000_WRITE_FLUSH(hw); 1608 mdelay(5); 1609 } 1610 1611 /* Setup the receive address. This involves initializing all of the Receive 1612 * Address Registers (RARs 0 - 15). 1613 */ 1614 e1000_init_rx_addrs(nic); 1615 1616 /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */ 1617 if (hw->mac_type == e1000_82542_rev2_0) { 1618 E1000_WRITE_REG(hw, RCTL, 0); 1619 E1000_WRITE_FLUSH(hw); 1620 mdelay(1); 1621 pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word); 1622 } 1623 1624 /* Zero out the Multicast HASH table */ 1625 DEBUGOUT("Zeroing the MTA\n"); 1626 mta_size = E1000_MC_TBL_SIZE; 1627 if (hw->mac_type == e1000_ich8lan) 1628 mta_size = E1000_MC_TBL_SIZE_ICH8LAN; 1629 for (i = 0; i < mta_size; i++) { 1630 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0); 1631 /* use write flush to prevent Memory Write Block (MWB) from 1632 * occuring when accessing our register space */ 1633 E1000_WRITE_FLUSH(hw); 1634 } 1635 #if 0 1636 /* Set the PCI priority bit correctly in the CTRL register. This 1637 * determines if the adapter gives priority to receives, or if it 1638 * gives equal priority to transmits and receives. Valid only on 1639 * 82542 and 82543 silicon. 1640 */ 1641 if (hw->dma_fairness && hw->mac_type <= e1000_82543) { 1642 ctrl = E1000_READ_REG(hw, CTRL); 1643 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR); 1644 } 1645 #endif 1646 switch (hw->mac_type) { 1647 case e1000_82545_rev_3: 1648 case e1000_82546_rev_3: 1649 break; 1650 default: 1651 /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */ 1652 if (hw->bus_type == e1000_bus_type_pcix) { 1653 pci_read_config_word(hw->pdev, PCIX_COMMAND_REGISTER, 1654 &pcix_cmd_word); 1655 pci_read_config_word(hw->pdev, PCIX_STATUS_REGISTER_HI, 1656 &pcix_stat_hi_word); 1657 cmd_mmrbc = 1658 (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) >> 1659 PCIX_COMMAND_MMRBC_SHIFT; 1660 stat_mmrbc = 1661 (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >> 1662 PCIX_STATUS_HI_MMRBC_SHIFT; 1663 if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K) 1664 stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K; 1665 if (cmd_mmrbc > stat_mmrbc) { 1666 pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK; 1667 pcix_cmd_word |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT; 1668 pci_write_config_word(hw->pdev, PCIX_COMMAND_REGISTER, 1669 pcix_cmd_word); 1670 } 1671 } 1672 break; 1673 } 1674 1675 /* More time needed for PHY to initialize */ 1676 if (hw->mac_type == e1000_ich8lan) 1677 mdelay(15); 1678 1679 /* Call a subroutine to configure the link and setup flow control. */ 1680 ret_val = e1000_setup_link(nic); 1681 1682 /* Set the transmit descriptor write-back policy */ 1683 if (hw->mac_type > e1000_82544) { 1684 ctrl = E1000_READ_REG(hw, TXDCTL); 1685 ctrl = 1686 (ctrl & ~E1000_TXDCTL_WTHRESH) | 1687 E1000_TXDCTL_FULL_TX_DESC_WB; 1688 E1000_WRITE_REG(hw, TXDCTL, ctrl); 1689 } 1690 1691 /* Set the receive descriptor write back policy */ 1692 1693 if (hw->mac_type >= e1000_82571) { 1694 ctrl = E1000_READ_REG(hw, RXDCTL); 1695 ctrl = 1696 (ctrl & ~E1000_RXDCTL_WTHRESH) | 1697 E1000_RXDCTL_FULL_RX_DESC_WB; 1698 E1000_WRITE_REG(hw, RXDCTL, ctrl); 1699 } 1700 1701 switch (hw->mac_type) { 1702 default: 1703 break; 1704 case e1000_80003es2lan: 1705 /* Enable retransmit on late collisions */ 1706 reg_data = E1000_READ_REG(hw, TCTL); 1707 reg_data |= E1000_TCTL_RTLC; 1708 E1000_WRITE_REG(hw, TCTL, reg_data); 1709 1710 /* Configure Gigabit Carry Extend Padding */ 1711 reg_data = E1000_READ_REG(hw, TCTL_EXT); 1712 reg_data &= ~E1000_TCTL_EXT_GCEX_MASK; 1713 reg_data |= DEFAULT_80003ES2LAN_TCTL_EXT_GCEX; 1714 E1000_WRITE_REG(hw, TCTL_EXT, reg_data); 1715 1716 /* Configure Transmit Inter-Packet Gap */ 1717 reg_data = E1000_READ_REG(hw, TIPG); 1718 reg_data &= ~E1000_TIPG_IPGT_MASK; 1719 reg_data |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000; 1720 E1000_WRITE_REG(hw, TIPG, reg_data); 1721 1722 reg_data = E1000_READ_REG_ARRAY(hw, FFLT, 0x0001); 1723 reg_data &= ~0x00100000; 1724 E1000_WRITE_REG_ARRAY(hw, FFLT, 0x0001, reg_data); 1725 /* Fall through */ 1726 case e1000_82571: 1727 case e1000_82572: 1728 case e1000_ich8lan: 1729 ctrl = E1000_READ_REG(hw, TXDCTL1); 1730 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) 1731 | E1000_TXDCTL_FULL_TX_DESC_WB; 1732 E1000_WRITE_REG(hw, TXDCTL1, ctrl); 1733 break; 1734 case e1000_82573: 1735 case e1000_82574: 1736 reg_data = E1000_READ_REG(hw, GCR); 1737 reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX; 1738 E1000_WRITE_REG(hw, GCR, reg_data); 1739 } 1740 1741 #if 0 1742 /* Clear all of the statistics registers (clear on read). It is 1743 * important that we do this after we have tried to establish link 1744 * because the symbol error count will increment wildly if there 1745 * is no link. 1746 */ 1747 e1000_clear_hw_cntrs(hw); 1748 1749 /* ICH8 No-snoop bits are opposite polarity. 1750 * Set to snoop by default after reset. */ 1751 if (hw->mac_type == e1000_ich8lan) 1752 e1000_set_pci_ex_no_snoop(hw, PCI_EX_82566_SNOOP_ALL); 1753 #endif 1754 1755 if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER || 1756 hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) { 1757 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 1758 /* Relaxed ordering must be disabled to avoid a parity 1759 * error crash in a PCI slot. */ 1760 ctrl_ext |= E1000_CTRL_EXT_RO_DIS; 1761 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 1762 } 1763 1764 return ret_val; 1765 } 1766 1767 /****************************************************************************** 1768 * Configures flow control and link settings. 1769 * 1770 * hw - Struct containing variables accessed by shared code 1771 * 1772 * Determines which flow control settings to use. Calls the apropriate media- 1773 * specific link configuration function. Configures the flow control settings. 1774 * Assuming the adapter has a valid link partner, a valid link should be 1775 * established. Assumes the hardware has previously been reset and the 1776 * transmitter and receiver are not enabled. 1777 *****************************************************************************/ 1778 static int 1779 e1000_setup_link(struct eth_device *nic) 1780 { 1781 struct e1000_hw *hw = nic->priv; 1782 uint32_t ctrl_ext; 1783 int32_t ret_val; 1784 uint16_t eeprom_data; 1785 1786 DEBUGFUNC(); 1787 1788 /* In the case of the phy reset being blocked, we already have a link. 1789 * We do not have to set it up again. */ 1790 if (e1000_check_phy_reset_block(hw)) 1791 return E1000_SUCCESS; 1792 1793 /* Read and store word 0x0F of the EEPROM. This word contains bits 1794 * that determine the hardware's default PAUSE (flow control) mode, 1795 * a bit that determines whether the HW defaults to enabling or 1796 * disabling auto-negotiation, and the direction of the 1797 * SW defined pins. If there is no SW over-ride of the flow 1798 * control setting, then the variable hw->fc will 1799 * be initialized based on a value in the EEPROM. 1800 */ 1801 if (e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, 1, 1802 &eeprom_data) < 0) { 1803 DEBUGOUT("EEPROM Read Error\n"); 1804 return -E1000_ERR_EEPROM; 1805 } 1806 1807 if (hw->fc == e1000_fc_default) { 1808 switch (hw->mac_type) { 1809 case e1000_ich8lan: 1810 case e1000_82573: 1811 case e1000_82574: 1812 hw->fc = e1000_fc_full; 1813 break; 1814 default: 1815 ret_val = e1000_read_eeprom(hw, 1816 EEPROM_INIT_CONTROL2_REG, 1, &eeprom_data); 1817 if (ret_val) { 1818 DEBUGOUT("EEPROM Read Error\n"); 1819 return -E1000_ERR_EEPROM; 1820 } 1821 if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0) 1822 hw->fc = e1000_fc_none; 1823 else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 1824 EEPROM_WORD0F_ASM_DIR) 1825 hw->fc = e1000_fc_tx_pause; 1826 else 1827 hw->fc = e1000_fc_full; 1828 break; 1829 } 1830 } 1831 1832 /* We want to save off the original Flow Control configuration just 1833 * in case we get disconnected and then reconnected into a different 1834 * hub or switch with different Flow Control capabilities. 1835 */ 1836 if (hw->mac_type == e1000_82542_rev2_0) 1837 hw->fc &= (~e1000_fc_tx_pause); 1838 1839 if ((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1)) 1840 hw->fc &= (~e1000_fc_rx_pause); 1841 1842 hw->original_fc = hw->fc; 1843 1844 DEBUGOUT("After fix-ups FlowControl is now = %x\n", hw->fc); 1845 1846 /* Take the 4 bits from EEPROM word 0x0F that determine the initial 1847 * polarity value for the SW controlled pins, and setup the 1848 * Extended Device Control reg with that info. 1849 * This is needed because one of the SW controlled pins is used for 1850 * signal detection. So this should be done before e1000_setup_pcs_link() 1851 * or e1000_phy_setup() is called. 1852 */ 1853 if (hw->mac_type == e1000_82543) { 1854 ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) << 1855 SWDPIO__EXT_SHIFT); 1856 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 1857 } 1858 1859 /* Call the necessary subroutine to configure the link. */ 1860 ret_val = (hw->media_type == e1000_media_type_fiber) ? 1861 e1000_setup_fiber_link(nic) : e1000_setup_copper_link(nic); 1862 if (ret_val < 0) { 1863 return ret_val; 1864 } 1865 1866 /* Initialize the flow control address, type, and PAUSE timer 1867 * registers to their default values. This is done even if flow 1868 * control is disabled, because it does not hurt anything to 1869 * initialize these registers. 1870 */ 1871 DEBUGOUT("Initializing the Flow Control address, type" 1872 "and timer regs\n"); 1873 1874 /* FCAL/H and FCT are hardcoded to standard values in e1000_ich8lan. */ 1875 if (hw->mac_type != e1000_ich8lan) { 1876 E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE); 1877 E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH); 1878 E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW); 1879 } 1880 1881 E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time); 1882 1883 /* Set the flow control receive threshold registers. Normally, 1884 * these registers will be set to a default threshold that may be 1885 * adjusted later by the driver's runtime code. However, if the 1886 * ability to transmit pause frames in not enabled, then these 1887 * registers will be set to 0. 1888 */ 1889 if (!(hw->fc & e1000_fc_tx_pause)) { 1890 E1000_WRITE_REG(hw, FCRTL, 0); 1891 E1000_WRITE_REG(hw, FCRTH, 0); 1892 } else { 1893 /* We need to set up the Receive Threshold high and low water marks 1894 * as well as (optionally) enabling the transmission of XON frames. 1895 */ 1896 if (hw->fc_send_xon) { 1897 E1000_WRITE_REG(hw, FCRTL, 1898 (hw->fc_low_water | E1000_FCRTL_XONE)); 1899 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water); 1900 } else { 1901 E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water); 1902 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water); 1903 } 1904 } 1905 return ret_val; 1906 } 1907 1908 /****************************************************************************** 1909 * Sets up link for a fiber based adapter 1910 * 1911 * hw - Struct containing variables accessed by shared code 1912 * 1913 * Manipulates Physical Coding Sublayer functions in order to configure 1914 * link. Assumes the hardware has been previously reset and the transmitter 1915 * and receiver are not enabled. 1916 *****************************************************************************/ 1917 static int 1918 e1000_setup_fiber_link(struct eth_device *nic) 1919 { 1920 struct e1000_hw *hw = nic->priv; 1921 uint32_t ctrl; 1922 uint32_t status; 1923 uint32_t txcw = 0; 1924 uint32_t i; 1925 uint32_t signal; 1926 int32_t ret_val; 1927 1928 DEBUGFUNC(); 1929 /* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be 1930 * set when the optics detect a signal. On older adapters, it will be 1931 * cleared when there is a signal 1932 */ 1933 ctrl = E1000_READ_REG(hw, CTRL); 1934 if ((hw->mac_type > e1000_82544) && !(ctrl & E1000_CTRL_ILOS)) 1935 signal = E1000_CTRL_SWDPIN1; 1936 else 1937 signal = 0; 1938 1939 printf("signal for %s is %x (ctrl %08x)!!!!\n", nic->name, signal, 1940 ctrl); 1941 /* Take the link out of reset */ 1942 ctrl &= ~(E1000_CTRL_LRST); 1943 1944 e1000_config_collision_dist(hw); 1945 1946 /* Check for a software override of the flow control settings, and setup 1947 * the device accordingly. If auto-negotiation is enabled, then software 1948 * will have to set the "PAUSE" bits to the correct value in the Tranmsit 1949 * Config Word Register (TXCW) and re-start auto-negotiation. However, if 1950 * auto-negotiation is disabled, then software will have to manually 1951 * configure the two flow control enable bits in the CTRL register. 1952 * 1953 * The possible values of the "fc" parameter are: 1954 * 0: Flow control is completely disabled 1955 * 1: Rx flow control is enabled (we can receive pause frames, but 1956 * not send pause frames). 1957 * 2: Tx flow control is enabled (we can send pause frames but we do 1958 * not support receiving pause frames). 1959 * 3: Both Rx and TX flow control (symmetric) are enabled. 1960 */ 1961 switch (hw->fc) { 1962 case e1000_fc_none: 1963 /* Flow control is completely disabled by a software over-ride. */ 1964 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD); 1965 break; 1966 case e1000_fc_rx_pause: 1967 /* RX Flow control is enabled and TX Flow control is disabled by a 1968 * software over-ride. Since there really isn't a way to advertise 1969 * that we are capable of RX Pause ONLY, we will advertise that we 1970 * support both symmetric and asymmetric RX PAUSE. Later, we will 1971 * disable the adapter's ability to send PAUSE frames. 1972 */ 1973 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); 1974 break; 1975 case e1000_fc_tx_pause: 1976 /* TX Flow control is enabled, and RX Flow control is disabled, by a 1977 * software over-ride. 1978 */ 1979 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR); 1980 break; 1981 case e1000_fc_full: 1982 /* Flow control (both RX and TX) is enabled by a software over-ride. */ 1983 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); 1984 break; 1985 default: 1986 DEBUGOUT("Flow control param set incorrectly\n"); 1987 return -E1000_ERR_CONFIG; 1988 break; 1989 } 1990 1991 /* Since auto-negotiation is enabled, take the link out of reset (the link 1992 * will be in reset, because we previously reset the chip). This will 1993 * restart auto-negotiation. If auto-neogtiation is successful then the 1994 * link-up status bit will be set and the flow control enable bits (RFCE 1995 * and TFCE) will be set according to their negotiated value. 1996 */ 1997 DEBUGOUT("Auto-negotiation enabled (%#x)\n", txcw); 1998 1999 E1000_WRITE_REG(hw, TXCW, txcw); 2000 E1000_WRITE_REG(hw, CTRL, ctrl); 2001 E1000_WRITE_FLUSH(hw); 2002 2003 hw->txcw = txcw; 2004 mdelay(1); 2005 2006 /* If we have a signal (the cable is plugged in) then poll for a "Link-Up" 2007 * indication in the Device Status Register. Time-out if a link isn't 2008 * seen in 500 milliseconds seconds (Auto-negotiation should complete in 2009 * less than 500 milliseconds even if the other end is doing it in SW). 2010 */ 2011 if ((E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) { 2012 DEBUGOUT("Looking for Link\n"); 2013 for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) { 2014 mdelay(10); 2015 status = E1000_READ_REG(hw, STATUS); 2016 if (status & E1000_STATUS_LU) 2017 break; 2018 } 2019 if (i == (LINK_UP_TIMEOUT / 10)) { 2020 /* AutoNeg failed to achieve a link, so we'll call 2021 * e1000_check_for_link. This routine will force the link up if we 2022 * detect a signal. This will allow us to communicate with 2023 * non-autonegotiating link partners. 2024 */ 2025 DEBUGOUT("Never got a valid link from auto-neg!!!\n"); 2026 hw->autoneg_failed = 1; 2027 ret_val = e1000_check_for_link(nic); 2028 if (ret_val < 0) { 2029 DEBUGOUT("Error while checking for link\n"); 2030 return ret_val; 2031 } 2032 hw->autoneg_failed = 0; 2033 } else { 2034 hw->autoneg_failed = 0; 2035 DEBUGOUT("Valid Link Found\n"); 2036 } 2037 } else { 2038 DEBUGOUT("No Signal Detected\n"); 2039 return -E1000_ERR_NOLINK; 2040 } 2041 return 0; 2042 } 2043 2044 /****************************************************************************** 2045 * Make sure we have a valid PHY and change PHY mode before link setup. 2046 * 2047 * hw - Struct containing variables accessed by shared code 2048 ******************************************************************************/ 2049 static int32_t 2050 e1000_copper_link_preconfig(struct e1000_hw *hw) 2051 { 2052 uint32_t ctrl; 2053 int32_t ret_val; 2054 uint16_t phy_data; 2055 2056 DEBUGFUNC(); 2057 2058 ctrl = E1000_READ_REG(hw, CTRL); 2059 /* With 82543, we need to force speed and duplex on the MAC equal to what 2060 * the PHY speed and duplex configuration is. In addition, we need to 2061 * perform a hardware reset on the PHY to take it out of reset. 2062 */ 2063 if (hw->mac_type > e1000_82543) { 2064 ctrl |= E1000_CTRL_SLU; 2065 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 2066 E1000_WRITE_REG(hw, CTRL, ctrl); 2067 } else { 2068 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX 2069 | E1000_CTRL_SLU); 2070 E1000_WRITE_REG(hw, CTRL, ctrl); 2071 ret_val = e1000_phy_hw_reset(hw); 2072 if (ret_val) 2073 return ret_val; 2074 } 2075 2076 /* Make sure we have a valid PHY */ 2077 ret_val = e1000_detect_gig_phy(hw); 2078 if (ret_val) { 2079 DEBUGOUT("Error, did not detect valid phy.\n"); 2080 return ret_val; 2081 } 2082 DEBUGOUT("Phy ID = %x \n", hw->phy_id); 2083 2084 /* Set PHY to class A mode (if necessary) */ 2085 ret_val = e1000_set_phy_mode(hw); 2086 if (ret_val) 2087 return ret_val; 2088 if ((hw->mac_type == e1000_82545_rev_3) || 2089 (hw->mac_type == e1000_82546_rev_3)) { 2090 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 2091 &phy_data); 2092 phy_data |= 0x00000008; 2093 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 2094 phy_data); 2095 } 2096 2097 if (hw->mac_type <= e1000_82543 || 2098 hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 || 2099 hw->mac_type == e1000_82541_rev_2 2100 || hw->mac_type == e1000_82547_rev_2) 2101 hw->phy_reset_disable = FALSE; 2102 2103 return E1000_SUCCESS; 2104 } 2105 2106 /***************************************************************************** 2107 * 2108 * This function sets the lplu state according to the active flag. When 2109 * activating lplu this function also disables smart speed and vise versa. 2110 * lplu will not be activated unless the device autonegotiation advertisment 2111 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes. 2112 * hw: Struct containing variables accessed by shared code 2113 * active - true to enable lplu false to disable lplu. 2114 * 2115 * returns: - E1000_ERR_PHY if fail to read/write the PHY 2116 * E1000_SUCCESS at any other case. 2117 * 2118 ****************************************************************************/ 2119 2120 static int32_t 2121 e1000_set_d3_lplu_state(struct e1000_hw *hw, boolean_t active) 2122 { 2123 uint32_t phy_ctrl = 0; 2124 int32_t ret_val; 2125 uint16_t phy_data; 2126 DEBUGFUNC(); 2127 2128 if (hw->phy_type != e1000_phy_igp && hw->phy_type != e1000_phy_igp_2 2129 && hw->phy_type != e1000_phy_igp_3) 2130 return E1000_SUCCESS; 2131 2132 /* During driver activity LPLU should not be used or it will attain link 2133 * from the lowest speeds starting from 10Mbps. The capability is used 2134 * for Dx transitions and states */ 2135 if (hw->mac_type == e1000_82541_rev_2 2136 || hw->mac_type == e1000_82547_rev_2) { 2137 ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, 2138 &phy_data); 2139 if (ret_val) 2140 return ret_val; 2141 } else if (hw->mac_type == e1000_ich8lan) { 2142 /* MAC writes into PHY register based on the state transition 2143 * and start auto-negotiation. SW driver can overwrite the 2144 * settings in CSR PHY power control E1000_PHY_CTRL register. */ 2145 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL); 2146 } else { 2147 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, 2148 &phy_data); 2149 if (ret_val) 2150 return ret_val; 2151 } 2152 2153 if (!active) { 2154 if (hw->mac_type == e1000_82541_rev_2 || 2155 hw->mac_type == e1000_82547_rev_2) { 2156 phy_data &= ~IGP01E1000_GMII_FLEX_SPD; 2157 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, 2158 phy_data); 2159 if (ret_val) 2160 return ret_val; 2161 } else { 2162 if (hw->mac_type == e1000_ich8lan) { 2163 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU; 2164 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); 2165 } else { 2166 phy_data &= ~IGP02E1000_PM_D3_LPLU; 2167 ret_val = e1000_write_phy_reg(hw, 2168 IGP02E1000_PHY_POWER_MGMT, phy_data); 2169 if (ret_val) 2170 return ret_val; 2171 } 2172 } 2173 2174 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during 2175 * Dx states where the power conservation is most important. During 2176 * driver activity we should enable SmartSpeed, so performance is 2177 * maintained. */ 2178 if (hw->smart_speed == e1000_smart_speed_on) { 2179 ret_val = e1000_read_phy_reg(hw, 2180 IGP01E1000_PHY_PORT_CONFIG, &phy_data); 2181 if (ret_val) 2182 return ret_val; 2183 2184 phy_data |= IGP01E1000_PSCFR_SMART_SPEED; 2185 ret_val = e1000_write_phy_reg(hw, 2186 IGP01E1000_PHY_PORT_CONFIG, phy_data); 2187 if (ret_val) 2188 return ret_val; 2189 } else if (hw->smart_speed == e1000_smart_speed_off) { 2190 ret_val = e1000_read_phy_reg(hw, 2191 IGP01E1000_PHY_PORT_CONFIG, &phy_data); 2192 if (ret_val) 2193 return ret_val; 2194 2195 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 2196 ret_val = e1000_write_phy_reg(hw, 2197 IGP01E1000_PHY_PORT_CONFIG, phy_data); 2198 if (ret_val) 2199 return ret_val; 2200 } 2201 2202 } else if ((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT) 2203 || (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL) || 2204 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) { 2205 2206 if (hw->mac_type == e1000_82541_rev_2 || 2207 hw->mac_type == e1000_82547_rev_2) { 2208 phy_data |= IGP01E1000_GMII_FLEX_SPD; 2209 ret_val = e1000_write_phy_reg(hw, 2210 IGP01E1000_GMII_FIFO, phy_data); 2211 if (ret_val) 2212 return ret_val; 2213 } else { 2214 if (hw->mac_type == e1000_ich8lan) { 2215 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU; 2216 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); 2217 } else { 2218 phy_data |= IGP02E1000_PM_D3_LPLU; 2219 ret_val = e1000_write_phy_reg(hw, 2220 IGP02E1000_PHY_POWER_MGMT, phy_data); 2221 if (ret_val) 2222 return ret_val; 2223 } 2224 } 2225 2226 /* When LPLU is enabled we should disable SmartSpeed */ 2227 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 2228 &phy_data); 2229 if (ret_val) 2230 return ret_val; 2231 2232 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 2233 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 2234 phy_data); 2235 if (ret_val) 2236 return ret_val; 2237 } 2238 return E1000_SUCCESS; 2239 } 2240 2241 /***************************************************************************** 2242 * 2243 * This function sets the lplu d0 state according to the active flag. When 2244 * activating lplu this function also disables smart speed and vise versa. 2245 * lplu will not be activated unless the device autonegotiation advertisment 2246 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes. 2247 * hw: Struct containing variables accessed by shared code 2248 * active - true to enable lplu false to disable lplu. 2249 * 2250 * returns: - E1000_ERR_PHY if fail to read/write the PHY 2251 * E1000_SUCCESS at any other case. 2252 * 2253 ****************************************************************************/ 2254 2255 static int32_t 2256 e1000_set_d0_lplu_state(struct e1000_hw *hw, boolean_t active) 2257 { 2258 uint32_t phy_ctrl = 0; 2259 int32_t ret_val; 2260 uint16_t phy_data; 2261 DEBUGFUNC(); 2262 2263 if (hw->mac_type <= e1000_82547_rev_2) 2264 return E1000_SUCCESS; 2265 2266 if (hw->mac_type == e1000_ich8lan) { 2267 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL); 2268 } else { 2269 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, 2270 &phy_data); 2271 if (ret_val) 2272 return ret_val; 2273 } 2274 2275 if (!active) { 2276 if (hw->mac_type == e1000_ich8lan) { 2277 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU; 2278 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); 2279 } else { 2280 phy_data &= ~IGP02E1000_PM_D0_LPLU; 2281 ret_val = e1000_write_phy_reg(hw, 2282 IGP02E1000_PHY_POWER_MGMT, phy_data); 2283 if (ret_val) 2284 return ret_val; 2285 } 2286 2287 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during 2288 * Dx states where the power conservation is most important. During 2289 * driver activity we should enable SmartSpeed, so performance is 2290 * maintained. */ 2291 if (hw->smart_speed == e1000_smart_speed_on) { 2292 ret_val = e1000_read_phy_reg(hw, 2293 IGP01E1000_PHY_PORT_CONFIG, &phy_data); 2294 if (ret_val) 2295 return ret_val; 2296 2297 phy_data |= IGP01E1000_PSCFR_SMART_SPEED; 2298 ret_val = e1000_write_phy_reg(hw, 2299 IGP01E1000_PHY_PORT_CONFIG, phy_data); 2300 if (ret_val) 2301 return ret_val; 2302 } else if (hw->smart_speed == e1000_smart_speed_off) { 2303 ret_val = e1000_read_phy_reg(hw, 2304 IGP01E1000_PHY_PORT_CONFIG, &phy_data); 2305 if (ret_val) 2306 return ret_val; 2307 2308 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 2309 ret_val = e1000_write_phy_reg(hw, 2310 IGP01E1000_PHY_PORT_CONFIG, phy_data); 2311 if (ret_val) 2312 return ret_val; 2313 } 2314 2315 2316 } else { 2317 2318 if (hw->mac_type == e1000_ich8lan) { 2319 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU; 2320 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); 2321 } else { 2322 phy_data |= IGP02E1000_PM_D0_LPLU; 2323 ret_val = e1000_write_phy_reg(hw, 2324 IGP02E1000_PHY_POWER_MGMT, phy_data); 2325 if (ret_val) 2326 return ret_val; 2327 } 2328 2329 /* When LPLU is enabled we should disable SmartSpeed */ 2330 ret_val = e1000_read_phy_reg(hw, 2331 IGP01E1000_PHY_PORT_CONFIG, &phy_data); 2332 if (ret_val) 2333 return ret_val; 2334 2335 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 2336 ret_val = e1000_write_phy_reg(hw, 2337 IGP01E1000_PHY_PORT_CONFIG, phy_data); 2338 if (ret_val) 2339 return ret_val; 2340 2341 } 2342 return E1000_SUCCESS; 2343 } 2344 2345 /******************************************************************** 2346 * Copper link setup for e1000_phy_igp series. 2347 * 2348 * hw - Struct containing variables accessed by shared code 2349 *********************************************************************/ 2350 static int32_t 2351 e1000_copper_link_igp_setup(struct e1000_hw *hw) 2352 { 2353 uint32_t led_ctrl; 2354 int32_t ret_val; 2355 uint16_t phy_data; 2356 2357 DEBUGFUNC(); 2358 2359 if (hw->phy_reset_disable) 2360 return E1000_SUCCESS; 2361 2362 ret_val = e1000_phy_reset(hw); 2363 if (ret_val) { 2364 DEBUGOUT("Error Resetting the PHY\n"); 2365 return ret_val; 2366 } 2367 2368 /* Wait 15ms for MAC to configure PHY from eeprom settings */ 2369 mdelay(15); 2370 if (hw->mac_type != e1000_ich8lan) { 2371 /* Configure activity LED after PHY reset */ 2372 led_ctrl = E1000_READ_REG(hw, LEDCTL); 2373 led_ctrl &= IGP_ACTIVITY_LED_MASK; 2374 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); 2375 E1000_WRITE_REG(hw, LEDCTL, led_ctrl); 2376 } 2377 2378 /* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */ 2379 if (hw->phy_type == e1000_phy_igp) { 2380 /* disable lplu d3 during driver init */ 2381 ret_val = e1000_set_d3_lplu_state(hw, FALSE); 2382 if (ret_val) { 2383 DEBUGOUT("Error Disabling LPLU D3\n"); 2384 return ret_val; 2385 } 2386 } 2387 2388 /* disable lplu d0 during driver init */ 2389 ret_val = e1000_set_d0_lplu_state(hw, FALSE); 2390 if (ret_val) { 2391 DEBUGOUT("Error Disabling LPLU D0\n"); 2392 return ret_val; 2393 } 2394 /* Configure mdi-mdix settings */ 2395 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); 2396 if (ret_val) 2397 return ret_val; 2398 2399 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { 2400 hw->dsp_config_state = e1000_dsp_config_disabled; 2401 /* Force MDI for earlier revs of the IGP PHY */ 2402 phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX 2403 | IGP01E1000_PSCR_FORCE_MDI_MDIX); 2404 hw->mdix = 1; 2405 2406 } else { 2407 hw->dsp_config_state = e1000_dsp_config_enabled; 2408 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; 2409 2410 switch (hw->mdix) { 2411 case 1: 2412 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; 2413 break; 2414 case 2: 2415 phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX; 2416 break; 2417 case 0: 2418 default: 2419 phy_data |= IGP01E1000_PSCR_AUTO_MDIX; 2420 break; 2421 } 2422 } 2423 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); 2424 if (ret_val) 2425 return ret_val; 2426 2427 /* set auto-master slave resolution settings */ 2428 if (hw->autoneg) { 2429 e1000_ms_type phy_ms_setting = hw->master_slave; 2430 2431 if (hw->ffe_config_state == e1000_ffe_config_active) 2432 hw->ffe_config_state = e1000_ffe_config_enabled; 2433 2434 if (hw->dsp_config_state == e1000_dsp_config_activated) 2435 hw->dsp_config_state = e1000_dsp_config_enabled; 2436 2437 /* when autonegotiation advertisment is only 1000Mbps then we 2438 * should disable SmartSpeed and enable Auto MasterSlave 2439 * resolution as hardware default. */ 2440 if (hw->autoneg_advertised == ADVERTISE_1000_FULL) { 2441 /* Disable SmartSpeed */ 2442 ret_val = e1000_read_phy_reg(hw, 2443 IGP01E1000_PHY_PORT_CONFIG, &phy_data); 2444 if (ret_val) 2445 return ret_val; 2446 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 2447 ret_val = e1000_write_phy_reg(hw, 2448 IGP01E1000_PHY_PORT_CONFIG, phy_data); 2449 if (ret_val) 2450 return ret_val; 2451 /* Set auto Master/Slave resolution process */ 2452 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, 2453 &phy_data); 2454 if (ret_val) 2455 return ret_val; 2456 phy_data &= ~CR_1000T_MS_ENABLE; 2457 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, 2458 phy_data); 2459 if (ret_val) 2460 return ret_val; 2461 } 2462 2463 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data); 2464 if (ret_val) 2465 return ret_val; 2466 2467 /* load defaults for future use */ 2468 hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ? 2469 ((phy_data & CR_1000T_MS_VALUE) ? 2470 e1000_ms_force_master : 2471 e1000_ms_force_slave) : 2472 e1000_ms_auto; 2473 2474 switch (phy_ms_setting) { 2475 case e1000_ms_force_master: 2476 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE); 2477 break; 2478 case e1000_ms_force_slave: 2479 phy_data |= CR_1000T_MS_ENABLE; 2480 phy_data &= ~(CR_1000T_MS_VALUE); 2481 break; 2482 case e1000_ms_auto: 2483 phy_data &= ~CR_1000T_MS_ENABLE; 2484 default: 2485 break; 2486 } 2487 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data); 2488 if (ret_val) 2489 return ret_val; 2490 } 2491 2492 return E1000_SUCCESS; 2493 } 2494 2495 /***************************************************************************** 2496 * This function checks the mode of the firmware. 2497 * 2498 * returns - TRUE when the mode is IAMT or FALSE. 2499 ****************************************************************************/ 2500 boolean_t 2501 e1000_check_mng_mode(struct e1000_hw *hw) 2502 { 2503 uint32_t fwsm; 2504 DEBUGFUNC(); 2505 2506 fwsm = E1000_READ_REG(hw, FWSM); 2507 2508 if (hw->mac_type == e1000_ich8lan) { 2509 if ((fwsm & E1000_FWSM_MODE_MASK) == 2510 (E1000_MNG_ICH_IAMT_MODE << E1000_FWSM_MODE_SHIFT)) 2511 return TRUE; 2512 } else if ((fwsm & E1000_FWSM_MODE_MASK) == 2513 (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT)) 2514 return TRUE; 2515 2516 return FALSE; 2517 } 2518 2519 static int32_t 2520 e1000_write_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t data) 2521 { 2522 uint16_t swfw = E1000_SWFW_PHY0_SM; 2523 uint32_t reg_val; 2524 DEBUGFUNC(); 2525 2526 if (e1000_is_second_port(hw)) 2527 swfw = E1000_SWFW_PHY1_SM; 2528 2529 if (e1000_swfw_sync_acquire(hw, swfw)) 2530 return -E1000_ERR_SWFW_SYNC; 2531 2532 reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) 2533 & E1000_KUMCTRLSTA_OFFSET) | data; 2534 E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val); 2535 udelay(2); 2536 2537 return E1000_SUCCESS; 2538 } 2539 2540 static int32_t 2541 e1000_read_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *data) 2542 { 2543 uint16_t swfw = E1000_SWFW_PHY0_SM; 2544 uint32_t reg_val; 2545 DEBUGFUNC(); 2546 2547 if (e1000_is_second_port(hw)) 2548 swfw = E1000_SWFW_PHY1_SM; 2549 2550 if (e1000_swfw_sync_acquire(hw, swfw)) 2551 return -E1000_ERR_SWFW_SYNC; 2552 2553 /* Write register address */ 2554 reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) & 2555 E1000_KUMCTRLSTA_OFFSET) | E1000_KUMCTRLSTA_REN; 2556 E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val); 2557 udelay(2); 2558 2559 /* Read the data returned */ 2560 reg_val = E1000_READ_REG(hw, KUMCTRLSTA); 2561 *data = (uint16_t)reg_val; 2562 2563 return E1000_SUCCESS; 2564 } 2565 2566 /******************************************************************** 2567 * Copper link setup for e1000_phy_gg82563 series. 2568 * 2569 * hw - Struct containing variables accessed by shared code 2570 *********************************************************************/ 2571 static int32_t 2572 e1000_copper_link_ggp_setup(struct e1000_hw *hw) 2573 { 2574 int32_t ret_val; 2575 uint16_t phy_data; 2576 uint32_t reg_data; 2577 2578 DEBUGFUNC(); 2579 2580 if (!hw->phy_reset_disable) { 2581 /* Enable CRS on TX for half-duplex operation. */ 2582 ret_val = e1000_read_phy_reg(hw, 2583 GG82563_PHY_MAC_SPEC_CTRL, &phy_data); 2584 if (ret_val) 2585 return ret_val; 2586 2587 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX; 2588 /* Use 25MHz for both link down and 1000BASE-T for Tx clock */ 2589 phy_data |= GG82563_MSCR_TX_CLK_1000MBPS_25MHZ; 2590 2591 ret_val = e1000_write_phy_reg(hw, 2592 GG82563_PHY_MAC_SPEC_CTRL, phy_data); 2593 if (ret_val) 2594 return ret_val; 2595 2596 /* Options: 2597 * MDI/MDI-X = 0 (default) 2598 * 0 - Auto for all speeds 2599 * 1 - MDI mode 2600 * 2 - MDI-X mode 2601 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) 2602 */ 2603 ret_val = e1000_read_phy_reg(hw, 2604 GG82563_PHY_SPEC_CTRL, &phy_data); 2605 if (ret_val) 2606 return ret_val; 2607 2608 phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK; 2609 2610 switch (hw->mdix) { 2611 case 1: 2612 phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDI; 2613 break; 2614 case 2: 2615 phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDIX; 2616 break; 2617 case 0: 2618 default: 2619 phy_data |= GG82563_PSCR_CROSSOVER_MODE_AUTO; 2620 break; 2621 } 2622 2623 /* Options: 2624 * disable_polarity_correction = 0 (default) 2625 * Automatic Correction for Reversed Cable Polarity 2626 * 0 - Disabled 2627 * 1 - Enabled 2628 */ 2629 phy_data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE; 2630 ret_val = e1000_write_phy_reg(hw, 2631 GG82563_PHY_SPEC_CTRL, phy_data); 2632 2633 if (ret_val) 2634 return ret_val; 2635 2636 /* SW Reset the PHY so all changes take effect */ 2637 ret_val = e1000_phy_reset(hw); 2638 if (ret_val) { 2639 DEBUGOUT("Error Resetting the PHY\n"); 2640 return ret_val; 2641 } 2642 } /* phy_reset_disable */ 2643 2644 if (hw->mac_type == e1000_80003es2lan) { 2645 /* Bypass RX and TX FIFO's */ 2646 ret_val = e1000_write_kmrn_reg(hw, 2647 E1000_KUMCTRLSTA_OFFSET_FIFO_CTRL, 2648 E1000_KUMCTRLSTA_FIFO_CTRL_RX_BYPASS 2649 | E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS); 2650 if (ret_val) 2651 return ret_val; 2652 2653 ret_val = e1000_read_phy_reg(hw, 2654 GG82563_PHY_SPEC_CTRL_2, &phy_data); 2655 if (ret_val) 2656 return ret_val; 2657 2658 phy_data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG; 2659 ret_val = e1000_write_phy_reg(hw, 2660 GG82563_PHY_SPEC_CTRL_2, phy_data); 2661 2662 if (ret_val) 2663 return ret_val; 2664 2665 reg_data = E1000_READ_REG(hw, CTRL_EXT); 2666 reg_data &= ~(E1000_CTRL_EXT_LINK_MODE_MASK); 2667 E1000_WRITE_REG(hw, CTRL_EXT, reg_data); 2668 2669 ret_val = e1000_read_phy_reg(hw, 2670 GG82563_PHY_PWR_MGMT_CTRL, &phy_data); 2671 if (ret_val) 2672 return ret_val; 2673 2674 /* Do not init these registers when the HW is in IAMT mode, since the 2675 * firmware will have already initialized them. We only initialize 2676 * them if the HW is not in IAMT mode. 2677 */ 2678 if (e1000_check_mng_mode(hw) == FALSE) { 2679 /* Enable Electrical Idle on the PHY */ 2680 phy_data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE; 2681 ret_val = e1000_write_phy_reg(hw, 2682 GG82563_PHY_PWR_MGMT_CTRL, phy_data); 2683 if (ret_val) 2684 return ret_val; 2685 2686 ret_val = e1000_read_phy_reg(hw, 2687 GG82563_PHY_KMRN_MODE_CTRL, &phy_data); 2688 if (ret_val) 2689 return ret_val; 2690 2691 phy_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; 2692 ret_val = e1000_write_phy_reg(hw, 2693 GG82563_PHY_KMRN_MODE_CTRL, phy_data); 2694 2695 if (ret_val) 2696 return ret_val; 2697 } 2698 2699 /* Workaround: Disable padding in Kumeran interface in the MAC 2700 * and in the PHY to avoid CRC errors. 2701 */ 2702 ret_val = e1000_read_phy_reg(hw, 2703 GG82563_PHY_INBAND_CTRL, &phy_data); 2704 if (ret_val) 2705 return ret_val; 2706 phy_data |= GG82563_ICR_DIS_PADDING; 2707 ret_val = e1000_write_phy_reg(hw, 2708 GG82563_PHY_INBAND_CTRL, phy_data); 2709 if (ret_val) 2710 return ret_val; 2711 } 2712 return E1000_SUCCESS; 2713 } 2714 2715 /******************************************************************** 2716 * Copper link setup for e1000_phy_m88 series. 2717 * 2718 * hw - Struct containing variables accessed by shared code 2719 *********************************************************************/ 2720 static int32_t 2721 e1000_copper_link_mgp_setup(struct e1000_hw *hw) 2722 { 2723 int32_t ret_val; 2724 uint16_t phy_data; 2725 2726 DEBUGFUNC(); 2727 2728 if (hw->phy_reset_disable) 2729 return E1000_SUCCESS; 2730 2731 /* Enable CRS on TX. This must be set for half-duplex operation. */ 2732 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 2733 if (ret_val) 2734 return ret_val; 2735 2736 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; 2737 2738 /* Options: 2739 * MDI/MDI-X = 0 (default) 2740 * 0 - Auto for all speeds 2741 * 1 - MDI mode 2742 * 2 - MDI-X mode 2743 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) 2744 */ 2745 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 2746 2747 switch (hw->mdix) { 2748 case 1: 2749 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; 2750 break; 2751 case 2: 2752 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; 2753 break; 2754 case 3: 2755 phy_data |= M88E1000_PSCR_AUTO_X_1000T; 2756 break; 2757 case 0: 2758 default: 2759 phy_data |= M88E1000_PSCR_AUTO_X_MODE; 2760 break; 2761 } 2762 2763 /* Options: 2764 * disable_polarity_correction = 0 (default) 2765 * Automatic Correction for Reversed Cable Polarity 2766 * 0 - Disabled 2767 * 1 - Enabled 2768 */ 2769 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; 2770 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 2771 if (ret_val) 2772 return ret_val; 2773 2774 if (hw->phy_revision < M88E1011_I_REV_4) { 2775 /* Force TX_CLK in the Extended PHY Specific Control Register 2776 * to 25MHz clock. 2777 */ 2778 ret_val = e1000_read_phy_reg(hw, 2779 M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); 2780 if (ret_val) 2781 return ret_val; 2782 2783 phy_data |= M88E1000_EPSCR_TX_CLK_25; 2784 2785 if ((hw->phy_revision == E1000_REVISION_2) && 2786 (hw->phy_id == M88E1111_I_PHY_ID)) { 2787 /* Vidalia Phy, set the downshift counter to 5x */ 2788 phy_data &= ~(M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK); 2789 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X; 2790 ret_val = e1000_write_phy_reg(hw, 2791 M88E1000_EXT_PHY_SPEC_CTRL, phy_data); 2792 if (ret_val) 2793 return ret_val; 2794 } else { 2795 /* Configure Master and Slave downshift values */ 2796 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 2797 | M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK); 2798 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X 2799 | M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X); 2800 ret_val = e1000_write_phy_reg(hw, 2801 M88E1000_EXT_PHY_SPEC_CTRL, phy_data); 2802 if (ret_val) 2803 return ret_val; 2804 } 2805 } 2806 2807 /* SW Reset the PHY so all changes take effect */ 2808 ret_val = e1000_phy_reset(hw); 2809 if (ret_val) { 2810 DEBUGOUT("Error Resetting the PHY\n"); 2811 return ret_val; 2812 } 2813 2814 return E1000_SUCCESS; 2815 } 2816 2817 /******************************************************************** 2818 * Setup auto-negotiation and flow control advertisements, 2819 * and then perform auto-negotiation. 2820 * 2821 * hw - Struct containing variables accessed by shared code 2822 *********************************************************************/ 2823 static int32_t 2824 e1000_copper_link_autoneg(struct e1000_hw *hw) 2825 { 2826 int32_t ret_val; 2827 uint16_t phy_data; 2828 2829 DEBUGFUNC(); 2830 2831 /* Perform some bounds checking on the hw->autoneg_advertised 2832 * parameter. If this variable is zero, then set it to the default. 2833 */ 2834 hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT; 2835 2836 /* If autoneg_advertised is zero, we assume it was not defaulted 2837 * by the calling code so we set to advertise full capability. 2838 */ 2839 if (hw->autoneg_advertised == 0) 2840 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT; 2841 2842 /* IFE phy only supports 10/100 */ 2843 if (hw->phy_type == e1000_phy_ife) 2844 hw->autoneg_advertised &= AUTONEG_ADVERTISE_10_100_ALL; 2845 2846 DEBUGOUT("Reconfiguring auto-neg advertisement params\n"); 2847 ret_val = e1000_phy_setup_autoneg(hw); 2848 if (ret_val) { 2849 DEBUGOUT("Error Setting up Auto-Negotiation\n"); 2850 return ret_val; 2851 } 2852 DEBUGOUT("Restarting Auto-Neg\n"); 2853 2854 /* Restart auto-negotiation by setting the Auto Neg Enable bit and 2855 * the Auto Neg Restart bit in the PHY control register. 2856 */ 2857 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data); 2858 if (ret_val) 2859 return ret_val; 2860 2861 phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); 2862 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data); 2863 if (ret_val) 2864 return ret_val; 2865 2866 /* Does the user want to wait for Auto-Neg to complete here, or 2867 * check at a later time (for example, callback routine). 2868 */ 2869 /* If we do not wait for autonegtation to complete I 2870 * do not see a valid link status. 2871 * wait_autoneg_complete = 1 . 2872 */ 2873 if (hw->wait_autoneg_complete) { 2874 ret_val = e1000_wait_autoneg(hw); 2875 if (ret_val) { 2876 DEBUGOUT("Error while waiting for autoneg" 2877 "to complete\n"); 2878 return ret_val; 2879 } 2880 } 2881 2882 hw->get_link_status = TRUE; 2883 2884 return E1000_SUCCESS; 2885 } 2886 2887 /****************************************************************************** 2888 * Config the MAC and the PHY after link is up. 2889 * 1) Set up the MAC to the current PHY speed/duplex 2890 * if we are on 82543. If we 2891 * are on newer silicon, we only need to configure 2892 * collision distance in the Transmit Control Register. 2893 * 2) Set up flow control on the MAC to that established with 2894 * the link partner. 2895 * 3) Config DSP to improve Gigabit link quality for some PHY revisions. 2896 * 2897 * hw - Struct containing variables accessed by shared code 2898 ******************************************************************************/ 2899 static int32_t 2900 e1000_copper_link_postconfig(struct e1000_hw *hw) 2901 { 2902 int32_t ret_val; 2903 DEBUGFUNC(); 2904 2905 if (hw->mac_type >= e1000_82544) { 2906 e1000_config_collision_dist(hw); 2907 } else { 2908 ret_val = e1000_config_mac_to_phy(hw); 2909 if (ret_val) { 2910 DEBUGOUT("Error configuring MAC to PHY settings\n"); 2911 return ret_val; 2912 } 2913 } 2914 ret_val = e1000_config_fc_after_link_up(hw); 2915 if (ret_val) { 2916 DEBUGOUT("Error Configuring Flow Control\n"); 2917 return ret_val; 2918 } 2919 return E1000_SUCCESS; 2920 } 2921 2922 /****************************************************************************** 2923 * Detects which PHY is present and setup the speed and duplex 2924 * 2925 * hw - Struct containing variables accessed by shared code 2926 ******************************************************************************/ 2927 static int 2928 e1000_setup_copper_link(struct eth_device *nic) 2929 { 2930 struct e1000_hw *hw = nic->priv; 2931 int32_t ret_val; 2932 uint16_t i; 2933 uint16_t phy_data; 2934 uint16_t reg_data; 2935 2936 DEBUGFUNC(); 2937 2938 switch (hw->mac_type) { 2939 case e1000_80003es2lan: 2940 case e1000_ich8lan: 2941 /* Set the mac to wait the maximum time between each 2942 * iteration and increase the max iterations when 2943 * polling the phy; this fixes erroneous timeouts at 10Mbps. */ 2944 ret_val = e1000_write_kmrn_reg(hw, 2945 GG82563_REG(0x34, 4), 0xFFFF); 2946 if (ret_val) 2947 return ret_val; 2948 ret_val = e1000_read_kmrn_reg(hw, 2949 GG82563_REG(0x34, 9), ®_data); 2950 if (ret_val) 2951 return ret_val; 2952 reg_data |= 0x3F; 2953 ret_val = e1000_write_kmrn_reg(hw, 2954 GG82563_REG(0x34, 9), reg_data); 2955 if (ret_val) 2956 return ret_val; 2957 default: 2958 break; 2959 } 2960 2961 /* Check if it is a valid PHY and set PHY mode if necessary. */ 2962 ret_val = e1000_copper_link_preconfig(hw); 2963 if (ret_val) 2964 return ret_val; 2965 switch (hw->mac_type) { 2966 case e1000_80003es2lan: 2967 /* Kumeran registers are written-only */ 2968 reg_data = 2969 E1000_KUMCTRLSTA_INB_CTRL_LINK_STATUS_TX_TIMEOUT_DEFAULT; 2970 reg_data |= E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING; 2971 ret_val = e1000_write_kmrn_reg(hw, 2972 E1000_KUMCTRLSTA_OFFSET_INB_CTRL, reg_data); 2973 if (ret_val) 2974 return ret_val; 2975 break; 2976 default: 2977 break; 2978 } 2979 2980 if (hw->phy_type == e1000_phy_igp || 2981 hw->phy_type == e1000_phy_igp_3 || 2982 hw->phy_type == e1000_phy_igp_2) { 2983 ret_val = e1000_copper_link_igp_setup(hw); 2984 if (ret_val) 2985 return ret_val; 2986 } else if (hw->phy_type == e1000_phy_m88) { 2987 ret_val = e1000_copper_link_mgp_setup(hw); 2988 if (ret_val) 2989 return ret_val; 2990 } else if (hw->phy_type == e1000_phy_gg82563) { 2991 ret_val = e1000_copper_link_ggp_setup(hw); 2992 if (ret_val) 2993 return ret_val; 2994 } 2995 2996 /* always auto */ 2997 /* Setup autoneg and flow control advertisement 2998 * and perform autonegotiation */ 2999 ret_val = e1000_copper_link_autoneg(hw); 3000 if (ret_val) 3001 return ret_val; 3002 3003 /* Check link status. Wait up to 100 microseconds for link to become 3004 * valid. 3005 */ 3006 for (i = 0; i < 10; i++) { 3007 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); 3008 if (ret_val) 3009 return ret_val; 3010 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); 3011 if (ret_val) 3012 return ret_val; 3013 3014 if (phy_data & MII_SR_LINK_STATUS) { 3015 /* Config the MAC and PHY after link is up */ 3016 ret_val = e1000_copper_link_postconfig(hw); 3017 if (ret_val) 3018 return ret_val; 3019 3020 DEBUGOUT("Valid link established!!!\n"); 3021 return E1000_SUCCESS; 3022 } 3023 udelay(10); 3024 } 3025 3026 DEBUGOUT("Unable to establish link!!!\n"); 3027 return E1000_SUCCESS; 3028 } 3029 3030 /****************************************************************************** 3031 * Configures PHY autoneg and flow control advertisement settings 3032 * 3033 * hw - Struct containing variables accessed by shared code 3034 ******************************************************************************/ 3035 int32_t 3036 e1000_phy_setup_autoneg(struct e1000_hw *hw) 3037 { 3038 int32_t ret_val; 3039 uint16_t mii_autoneg_adv_reg; 3040 uint16_t mii_1000t_ctrl_reg; 3041 3042 DEBUGFUNC(); 3043 3044 /* Read the MII Auto-Neg Advertisement Register (Address 4). */ 3045 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg); 3046 if (ret_val) 3047 return ret_val; 3048 3049 if (hw->phy_type != e1000_phy_ife) { 3050 /* Read the MII 1000Base-T Control Register (Address 9). */ 3051 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, 3052 &mii_1000t_ctrl_reg); 3053 if (ret_val) 3054 return ret_val; 3055 } else 3056 mii_1000t_ctrl_reg = 0; 3057 3058 /* Need to parse both autoneg_advertised and fc and set up 3059 * the appropriate PHY registers. First we will parse for 3060 * autoneg_advertised software override. Since we can advertise 3061 * a plethora of combinations, we need to check each bit 3062 * individually. 3063 */ 3064 3065 /* First we clear all the 10/100 mb speed bits in the Auto-Neg 3066 * Advertisement Register (Address 4) and the 1000 mb speed bits in 3067 * the 1000Base-T Control Register (Address 9). 3068 */ 3069 mii_autoneg_adv_reg &= ~REG4_SPEED_MASK; 3070 mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK; 3071 3072 DEBUGOUT("autoneg_advertised %x\n", hw->autoneg_advertised); 3073 3074 /* Do we want to advertise 10 Mb Half Duplex? */ 3075 if (hw->autoneg_advertised & ADVERTISE_10_HALF) { 3076 DEBUGOUT("Advertise 10mb Half duplex\n"); 3077 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS; 3078 } 3079 3080 /* Do we want to advertise 10 Mb Full Duplex? */ 3081 if (hw->autoneg_advertised & ADVERTISE_10_FULL) { 3082 DEBUGOUT("Advertise 10mb Full duplex\n"); 3083 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS; 3084 } 3085 3086 /* Do we want to advertise 100 Mb Half Duplex? */ 3087 if (hw->autoneg_advertised & ADVERTISE_100_HALF) { 3088 DEBUGOUT("Advertise 100mb Half duplex\n"); 3089 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS; 3090 } 3091 3092 /* Do we want to advertise 100 Mb Full Duplex? */ 3093 if (hw->autoneg_advertised & ADVERTISE_100_FULL) { 3094 DEBUGOUT("Advertise 100mb Full duplex\n"); 3095 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS; 3096 } 3097 3098 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */ 3099 if (hw->autoneg_advertised & ADVERTISE_1000_HALF) { 3100 DEBUGOUT 3101 ("Advertise 1000mb Half duplex requested, request denied!\n"); 3102 } 3103 3104 /* Do we want to advertise 1000 Mb Full Duplex? */ 3105 if (hw->autoneg_advertised & ADVERTISE_1000_FULL) { 3106 DEBUGOUT("Advertise 1000mb Full duplex\n"); 3107 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS; 3108 } 3109 3110 /* Check for a software override of the flow control settings, and 3111 * setup the PHY advertisement registers accordingly. If 3112 * auto-negotiation is enabled, then software will have to set the 3113 * "PAUSE" bits to the correct value in the Auto-Negotiation 3114 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation. 3115 * 3116 * The possible values of the "fc" parameter are: 3117 * 0: Flow control is completely disabled 3118 * 1: Rx flow control is enabled (we can receive pause frames 3119 * but not send pause frames). 3120 * 2: Tx flow control is enabled (we can send pause frames 3121 * but we do not support receiving pause frames). 3122 * 3: Both Rx and TX flow control (symmetric) are enabled. 3123 * other: No software override. The flow control configuration 3124 * in the EEPROM is used. 3125 */ 3126 switch (hw->fc) { 3127 case e1000_fc_none: /* 0 */ 3128 /* Flow control (RX & TX) is completely disabled by a 3129 * software over-ride. 3130 */ 3131 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 3132 break; 3133 case e1000_fc_rx_pause: /* 1 */ 3134 /* RX Flow control is enabled, and TX Flow control is 3135 * disabled, by a software over-ride. 3136 */ 3137 /* Since there really isn't a way to advertise that we are 3138 * capable of RX Pause ONLY, we will advertise that we 3139 * support both symmetric and asymmetric RX PAUSE. Later 3140 * (in e1000_config_fc_after_link_up) we will disable the 3141 *hw's ability to send PAUSE frames. 3142 */ 3143 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 3144 break; 3145 case e1000_fc_tx_pause: /* 2 */ 3146 /* TX Flow control is enabled, and RX Flow control is 3147 * disabled, by a software over-ride. 3148 */ 3149 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR; 3150 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE; 3151 break; 3152 case e1000_fc_full: /* 3 */ 3153 /* Flow control (both RX and TX) is enabled by a software 3154 * over-ride. 3155 */ 3156 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 3157 break; 3158 default: 3159 DEBUGOUT("Flow control param set incorrectly\n"); 3160 return -E1000_ERR_CONFIG; 3161 } 3162 3163 ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg); 3164 if (ret_val) 3165 return ret_val; 3166 3167 DEBUGOUT("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); 3168 3169 if (hw->phy_type != e1000_phy_ife) { 3170 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, 3171 mii_1000t_ctrl_reg); 3172 if (ret_val) 3173 return ret_val; 3174 } 3175 3176 return E1000_SUCCESS; 3177 } 3178 3179 /****************************************************************************** 3180 * Sets the collision distance in the Transmit Control register 3181 * 3182 * hw - Struct containing variables accessed by shared code 3183 * 3184 * Link should have been established previously. Reads the speed and duplex 3185 * information from the Device Status register. 3186 ******************************************************************************/ 3187 static void 3188 e1000_config_collision_dist(struct e1000_hw *hw) 3189 { 3190 uint32_t tctl, coll_dist; 3191 3192 DEBUGFUNC(); 3193 3194 if (hw->mac_type < e1000_82543) 3195 coll_dist = E1000_COLLISION_DISTANCE_82542; 3196 else 3197 coll_dist = E1000_COLLISION_DISTANCE; 3198 3199 tctl = E1000_READ_REG(hw, TCTL); 3200 3201 tctl &= ~E1000_TCTL_COLD; 3202 tctl |= coll_dist << E1000_COLD_SHIFT; 3203 3204 E1000_WRITE_REG(hw, TCTL, tctl); 3205 E1000_WRITE_FLUSH(hw); 3206 } 3207 3208 /****************************************************************************** 3209 * Sets MAC speed and duplex settings to reflect the those in the PHY 3210 * 3211 * hw - Struct containing variables accessed by shared code 3212 * mii_reg - data to write to the MII control register 3213 * 3214 * The contents of the PHY register containing the needed information need to 3215 * be passed in. 3216 ******************************************************************************/ 3217 static int 3218 e1000_config_mac_to_phy(struct e1000_hw *hw) 3219 { 3220 uint32_t ctrl; 3221 uint16_t phy_data; 3222 3223 DEBUGFUNC(); 3224 3225 /* Read the Device Control Register and set the bits to Force Speed 3226 * and Duplex. 3227 */ 3228 ctrl = E1000_READ_REG(hw, CTRL); 3229 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 3230 ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS); 3231 3232 /* Set up duplex in the Device Control and Transmit Control 3233 * registers depending on negotiated values. 3234 */ 3235 if (e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data) < 0) { 3236 DEBUGOUT("PHY Read Error\n"); 3237 return -E1000_ERR_PHY; 3238 } 3239 if (phy_data & M88E1000_PSSR_DPLX) 3240 ctrl |= E1000_CTRL_FD; 3241 else 3242 ctrl &= ~E1000_CTRL_FD; 3243 3244 e1000_config_collision_dist(hw); 3245 3246 /* Set up speed in the Device Control register depending on 3247 * negotiated values. 3248 */ 3249 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) 3250 ctrl |= E1000_CTRL_SPD_1000; 3251 else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS) 3252 ctrl |= E1000_CTRL_SPD_100; 3253 /* Write the configured values back to the Device Control Reg. */ 3254 E1000_WRITE_REG(hw, CTRL, ctrl); 3255 return 0; 3256 } 3257 3258 /****************************************************************************** 3259 * Forces the MAC's flow control settings. 3260 * 3261 * hw - Struct containing variables accessed by shared code 3262 * 3263 * Sets the TFCE and RFCE bits in the device control register to reflect 3264 * the adapter settings. TFCE and RFCE need to be explicitly set by 3265 * software when a Copper PHY is used because autonegotiation is managed 3266 * by the PHY rather than the MAC. Software must also configure these 3267 * bits when link is forced on a fiber connection. 3268 *****************************************************************************/ 3269 static int 3270 e1000_force_mac_fc(struct e1000_hw *hw) 3271 { 3272 uint32_t ctrl; 3273 3274 DEBUGFUNC(); 3275 3276 /* Get the current configuration of the Device Control Register */ 3277 ctrl = E1000_READ_REG(hw, CTRL); 3278 3279 /* Because we didn't get link via the internal auto-negotiation 3280 * mechanism (we either forced link or we got link via PHY 3281 * auto-neg), we have to manually enable/disable transmit an 3282 * receive flow control. 3283 * 3284 * The "Case" statement below enables/disable flow control 3285 * according to the "hw->fc" parameter. 3286 * 3287 * The possible values of the "fc" parameter are: 3288 * 0: Flow control is completely disabled 3289 * 1: Rx flow control is enabled (we can receive pause 3290 * frames but not send pause frames). 3291 * 2: Tx flow control is enabled (we can send pause frames 3292 * frames but we do not receive pause frames). 3293 * 3: Both Rx and TX flow control (symmetric) is enabled. 3294 * other: No other values should be possible at this point. 3295 */ 3296 3297 switch (hw->fc) { 3298 case e1000_fc_none: 3299 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE)); 3300 break; 3301 case e1000_fc_rx_pause: 3302 ctrl &= (~E1000_CTRL_TFCE); 3303 ctrl |= E1000_CTRL_RFCE; 3304 break; 3305 case e1000_fc_tx_pause: 3306 ctrl &= (~E1000_CTRL_RFCE); 3307 ctrl |= E1000_CTRL_TFCE; 3308 break; 3309 case e1000_fc_full: 3310 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE); 3311 break; 3312 default: 3313 DEBUGOUT("Flow control param set incorrectly\n"); 3314 return -E1000_ERR_CONFIG; 3315 } 3316 3317 /* Disable TX Flow Control for 82542 (rev 2.0) */ 3318 if (hw->mac_type == e1000_82542_rev2_0) 3319 ctrl &= (~E1000_CTRL_TFCE); 3320 3321 E1000_WRITE_REG(hw, CTRL, ctrl); 3322 return 0; 3323 } 3324 3325 /****************************************************************************** 3326 * Configures flow control settings after link is established 3327 * 3328 * hw - Struct containing variables accessed by shared code 3329 * 3330 * Should be called immediately after a valid link has been established. 3331 * Forces MAC flow control settings if link was forced. When in MII/GMII mode 3332 * and autonegotiation is enabled, the MAC flow control settings will be set 3333 * based on the flow control negotiated by the PHY. In TBI mode, the TFCE 3334 * and RFCE bits will be automaticaly set to the negotiated flow control mode. 3335 *****************************************************************************/ 3336 static int32_t 3337 e1000_config_fc_after_link_up(struct e1000_hw *hw) 3338 { 3339 int32_t ret_val; 3340 uint16_t mii_status_reg; 3341 uint16_t mii_nway_adv_reg; 3342 uint16_t mii_nway_lp_ability_reg; 3343 uint16_t speed; 3344 uint16_t duplex; 3345 3346 DEBUGFUNC(); 3347 3348 /* Check for the case where we have fiber media and auto-neg failed 3349 * so we had to force link. In this case, we need to force the 3350 * configuration of the MAC to match the "fc" parameter. 3351 */ 3352 if (((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed)) 3353 || ((hw->media_type == e1000_media_type_internal_serdes) 3354 && (hw->autoneg_failed)) 3355 || ((hw->media_type == e1000_media_type_copper) 3356 && (!hw->autoneg))) { 3357 ret_val = e1000_force_mac_fc(hw); 3358 if (ret_val < 0) { 3359 DEBUGOUT("Error forcing flow control settings\n"); 3360 return ret_val; 3361 } 3362 } 3363 3364 /* Check for the case where we have copper media and auto-neg is 3365 * enabled. In this case, we need to check and see if Auto-Neg 3366 * has completed, and if so, how the PHY and link partner has 3367 * flow control configured. 3368 */ 3369 if (hw->media_type == e1000_media_type_copper) { 3370 /* Read the MII Status Register and check to see if AutoNeg 3371 * has completed. We read this twice because this reg has 3372 * some "sticky" (latched) bits. 3373 */ 3374 if (e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) { 3375 DEBUGOUT("PHY Read Error \n"); 3376 return -E1000_ERR_PHY; 3377 } 3378 if (e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) { 3379 DEBUGOUT("PHY Read Error \n"); 3380 return -E1000_ERR_PHY; 3381 } 3382 3383 if (mii_status_reg & MII_SR_AUTONEG_COMPLETE) { 3384 /* The AutoNeg process has completed, so we now need to 3385 * read both the Auto Negotiation Advertisement Register 3386 * (Address 4) and the Auto_Negotiation Base Page Ability 3387 * Register (Address 5) to determine how flow control was 3388 * negotiated. 3389 */ 3390 if (e1000_read_phy_reg 3391 (hw, PHY_AUTONEG_ADV, &mii_nway_adv_reg) < 0) { 3392 DEBUGOUT("PHY Read Error\n"); 3393 return -E1000_ERR_PHY; 3394 } 3395 if (e1000_read_phy_reg 3396 (hw, PHY_LP_ABILITY, 3397 &mii_nway_lp_ability_reg) < 0) { 3398 DEBUGOUT("PHY Read Error\n"); 3399 return -E1000_ERR_PHY; 3400 } 3401 3402 /* Two bits in the Auto Negotiation Advertisement Register 3403 * (Address 4) and two bits in the Auto Negotiation Base 3404 * Page Ability Register (Address 5) determine flow control 3405 * for both the PHY and the link partner. The following 3406 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25, 3407 * 1999, describes these PAUSE resolution bits and how flow 3408 * control is determined based upon these settings. 3409 * NOTE: DC = Don't Care 3410 * 3411 * LOCAL DEVICE | LINK PARTNER 3412 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution 3413 *-------|---------|-------|---------|-------------------- 3414 * 0 | 0 | DC | DC | e1000_fc_none 3415 * 0 | 1 | 0 | DC | e1000_fc_none 3416 * 0 | 1 | 1 | 0 | e1000_fc_none 3417 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 3418 * 1 | 0 | 0 | DC | e1000_fc_none 3419 * 1 | DC | 1 | DC | e1000_fc_full 3420 * 1 | 1 | 0 | 0 | e1000_fc_none 3421 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 3422 * 3423 */ 3424 /* Are both PAUSE bits set to 1? If so, this implies 3425 * Symmetric Flow Control is enabled at both ends. The 3426 * ASM_DIR bits are irrelevant per the spec. 3427 * 3428 * For Symmetric Flow Control: 3429 * 3430 * LOCAL DEVICE | LINK PARTNER 3431 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 3432 *-------|---------|-------|---------|-------------------- 3433 * 1 | DC | 1 | DC | e1000_fc_full 3434 * 3435 */ 3436 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 3437 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) { 3438 /* Now we need to check if the user selected RX ONLY 3439 * of pause frames. In this case, we had to advertise 3440 * FULL flow control because we could not advertise RX 3441 * ONLY. Hence, we must now check to see if we need to 3442 * turn OFF the TRANSMISSION of PAUSE frames. 3443 */ 3444 if (hw->original_fc == e1000_fc_full) { 3445 hw->fc = e1000_fc_full; 3446 DEBUGOUT("Flow Control = FULL.\r\n"); 3447 } else { 3448 hw->fc = e1000_fc_rx_pause; 3449 DEBUGOUT 3450 ("Flow Control = RX PAUSE frames only.\r\n"); 3451 } 3452 } 3453 /* For receiving PAUSE frames ONLY. 3454 * 3455 * LOCAL DEVICE | LINK PARTNER 3456 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 3457 *-------|---------|-------|---------|-------------------- 3458 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 3459 * 3460 */ 3461 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) && 3462 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 3463 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 3464 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) 3465 { 3466 hw->fc = e1000_fc_tx_pause; 3467 DEBUGOUT 3468 ("Flow Control = TX PAUSE frames only.\r\n"); 3469 } 3470 /* For transmitting PAUSE frames ONLY. 3471 * 3472 * LOCAL DEVICE | LINK PARTNER 3473 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 3474 *-------|---------|-------|---------|-------------------- 3475 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 3476 * 3477 */ 3478 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 3479 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 3480 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 3481 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) 3482 { 3483 hw->fc = e1000_fc_rx_pause; 3484 DEBUGOUT 3485 ("Flow Control = RX PAUSE frames only.\r\n"); 3486 } 3487 /* Per the IEEE spec, at this point flow control should be 3488 * disabled. However, we want to consider that we could 3489 * be connected to a legacy switch that doesn't advertise 3490 * desired flow control, but can be forced on the link 3491 * partner. So if we advertised no flow control, that is 3492 * what we will resolve to. If we advertised some kind of 3493 * receive capability (Rx Pause Only or Full Flow Control) 3494 * and the link partner advertised none, we will configure 3495 * ourselves to enable Rx Flow Control only. We can do 3496 * this safely for two reasons: If the link partner really 3497 * didn't want flow control enabled, and we enable Rx, no 3498 * harm done since we won't be receiving any PAUSE frames 3499 * anyway. If the intent on the link partner was to have 3500 * flow control enabled, then by us enabling RX only, we 3501 * can at least receive pause frames and process them. 3502 * This is a good idea because in most cases, since we are 3503 * predominantly a server NIC, more times than not we will 3504 * be asked to delay transmission of packets than asking 3505 * our link partner to pause transmission of frames. 3506 */ 3507 else if (hw->original_fc == e1000_fc_none || 3508 hw->original_fc == e1000_fc_tx_pause) { 3509 hw->fc = e1000_fc_none; 3510 DEBUGOUT("Flow Control = NONE.\r\n"); 3511 } else { 3512 hw->fc = e1000_fc_rx_pause; 3513 DEBUGOUT 3514 ("Flow Control = RX PAUSE frames only.\r\n"); 3515 } 3516 3517 /* Now we need to do one last check... If we auto- 3518 * negotiated to HALF DUPLEX, flow control should not be 3519 * enabled per IEEE 802.3 spec. 3520 */ 3521 e1000_get_speed_and_duplex(hw, &speed, &duplex); 3522 3523 if (duplex == HALF_DUPLEX) 3524 hw->fc = e1000_fc_none; 3525 3526 /* Now we call a subroutine to actually force the MAC 3527 * controller to use the correct flow control settings. 3528 */ 3529 ret_val = e1000_force_mac_fc(hw); 3530 if (ret_val < 0) { 3531 DEBUGOUT 3532 ("Error forcing flow control settings\n"); 3533 return ret_val; 3534 } 3535 } else { 3536 DEBUGOUT 3537 ("Copper PHY and Auto Neg has not completed.\r\n"); 3538 } 3539 } 3540 return E1000_SUCCESS; 3541 } 3542 3543 /****************************************************************************** 3544 * Checks to see if the link status of the hardware has changed. 3545 * 3546 * hw - Struct containing variables accessed by shared code 3547 * 3548 * Called by any function that needs to check the link status of the adapter. 3549 *****************************************************************************/ 3550 static int 3551 e1000_check_for_link(struct eth_device *nic) 3552 { 3553 struct e1000_hw *hw = nic->priv; 3554 uint32_t rxcw; 3555 uint32_t ctrl; 3556 uint32_t status; 3557 uint32_t rctl; 3558 uint32_t signal; 3559 int32_t ret_val; 3560 uint16_t phy_data; 3561 uint16_t lp_capability; 3562 3563 DEBUGFUNC(); 3564 3565 /* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be 3566 * set when the optics detect a signal. On older adapters, it will be 3567 * cleared when there is a signal 3568 */ 3569 ctrl = E1000_READ_REG(hw, CTRL); 3570 if ((hw->mac_type > e1000_82544) && !(ctrl & E1000_CTRL_ILOS)) 3571 signal = E1000_CTRL_SWDPIN1; 3572 else 3573 signal = 0; 3574 3575 status = E1000_READ_REG(hw, STATUS); 3576 rxcw = E1000_READ_REG(hw, RXCW); 3577 DEBUGOUT("ctrl: %#08x status %#08x rxcw %#08x\n", ctrl, status, rxcw); 3578 3579 /* If we have a copper PHY then we only want to go out to the PHY 3580 * registers to see if Auto-Neg has completed and/or if our link 3581 * status has changed. The get_link_status flag will be set if we 3582 * receive a Link Status Change interrupt or we have Rx Sequence 3583 * Errors. 3584 */ 3585 if ((hw->media_type == e1000_media_type_copper) && hw->get_link_status) { 3586 /* First we want to see if the MII Status Register reports 3587 * link. If so, then we want to get the current speed/duplex 3588 * of the PHY. 3589 * Read the register twice since the link bit is sticky. 3590 */ 3591 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) { 3592 DEBUGOUT("PHY Read Error\n"); 3593 return -E1000_ERR_PHY; 3594 } 3595 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) { 3596 DEBUGOUT("PHY Read Error\n"); 3597 return -E1000_ERR_PHY; 3598 } 3599 3600 if (phy_data & MII_SR_LINK_STATUS) { 3601 hw->get_link_status = FALSE; 3602 } else { 3603 /* No link detected */ 3604 return -E1000_ERR_NOLINK; 3605 } 3606 3607 /* We have a M88E1000 PHY and Auto-Neg is enabled. If we 3608 * have Si on board that is 82544 or newer, Auto 3609 * Speed Detection takes care of MAC speed/duplex 3610 * configuration. So we only need to configure Collision 3611 * Distance in the MAC. Otherwise, we need to force 3612 * speed/duplex on the MAC to the current PHY speed/duplex 3613 * settings. 3614 */ 3615 if (hw->mac_type >= e1000_82544) 3616 e1000_config_collision_dist(hw); 3617 else { 3618 ret_val = e1000_config_mac_to_phy(hw); 3619 if (ret_val < 0) { 3620 DEBUGOUT 3621 ("Error configuring MAC to PHY settings\n"); 3622 return ret_val; 3623 } 3624 } 3625 3626 /* Configure Flow Control now that Auto-Neg has completed. First, we 3627 * need to restore the desired flow control settings because we may 3628 * have had to re-autoneg with a different link partner. 3629 */ 3630 ret_val = e1000_config_fc_after_link_up(hw); 3631 if (ret_val < 0) { 3632 DEBUGOUT("Error configuring flow control\n"); 3633 return ret_val; 3634 } 3635 3636 /* At this point we know that we are on copper and we have 3637 * auto-negotiated link. These are conditions for checking the link 3638 * parter capability register. We use the link partner capability to 3639 * determine if TBI Compatibility needs to be turned on or off. If 3640 * the link partner advertises any speed in addition to Gigabit, then 3641 * we assume that they are GMII-based, and TBI compatibility is not 3642 * needed. If no other speeds are advertised, we assume the link 3643 * partner is TBI-based, and we turn on TBI Compatibility. 3644 */ 3645 if (hw->tbi_compatibility_en) { 3646 if (e1000_read_phy_reg 3647 (hw, PHY_LP_ABILITY, &lp_capability) < 0) { 3648 DEBUGOUT("PHY Read Error\n"); 3649 return -E1000_ERR_PHY; 3650 } 3651 if (lp_capability & (NWAY_LPAR_10T_HD_CAPS | 3652 NWAY_LPAR_10T_FD_CAPS | 3653 NWAY_LPAR_100TX_HD_CAPS | 3654 NWAY_LPAR_100TX_FD_CAPS | 3655 NWAY_LPAR_100T4_CAPS)) { 3656 /* If our link partner advertises anything in addition to 3657 * gigabit, we do not need to enable TBI compatibility. 3658 */ 3659 if (hw->tbi_compatibility_on) { 3660 /* If we previously were in the mode, turn it off. */ 3661 rctl = E1000_READ_REG(hw, RCTL); 3662 rctl &= ~E1000_RCTL_SBP; 3663 E1000_WRITE_REG(hw, RCTL, rctl); 3664 hw->tbi_compatibility_on = FALSE; 3665 } 3666 } else { 3667 /* If TBI compatibility is was previously off, turn it on. For 3668 * compatibility with a TBI link partner, we will store bad 3669 * packets. Some frames have an additional byte on the end and 3670 * will look like CRC errors to to the hardware. 3671 */ 3672 if (!hw->tbi_compatibility_on) { 3673 hw->tbi_compatibility_on = TRUE; 3674 rctl = E1000_READ_REG(hw, RCTL); 3675 rctl |= E1000_RCTL_SBP; 3676 E1000_WRITE_REG(hw, RCTL, rctl); 3677 } 3678 } 3679 } 3680 } 3681 /* If we don't have link (auto-negotiation failed or link partner cannot 3682 * auto-negotiate), the cable is plugged in (we have signal), and our 3683 * link partner is not trying to auto-negotiate with us (we are receiving 3684 * idles or data), we need to force link up. We also need to give 3685 * auto-negotiation time to complete, in case the cable was just plugged 3686 * in. The autoneg_failed flag does this. 3687 */ 3688 else if ((hw->media_type == e1000_media_type_fiber) && 3689 (!(status & E1000_STATUS_LU)) && 3690 ((ctrl & E1000_CTRL_SWDPIN1) == signal) && 3691 (!(rxcw & E1000_RXCW_C))) { 3692 if (hw->autoneg_failed == 0) { 3693 hw->autoneg_failed = 1; 3694 return 0; 3695 } 3696 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\r\n"); 3697 3698 /* Disable auto-negotiation in the TXCW register */ 3699 E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE)); 3700 3701 /* Force link-up and also force full-duplex. */ 3702 ctrl = E1000_READ_REG(hw, CTRL); 3703 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 3704 E1000_WRITE_REG(hw, CTRL, ctrl); 3705 3706 /* Configure Flow Control after forcing link up. */ 3707 ret_val = e1000_config_fc_after_link_up(hw); 3708 if (ret_val < 0) { 3709 DEBUGOUT("Error configuring flow control\n"); 3710 return ret_val; 3711 } 3712 } 3713 /* If we are forcing link and we are receiving /C/ ordered sets, re-enable 3714 * auto-negotiation in the TXCW register and disable forced link in the 3715 * Device Control register in an attempt to auto-negotiate with our link 3716 * partner. 3717 */ 3718 else if ((hw->media_type == e1000_media_type_fiber) && 3719 (ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { 3720 DEBUGOUT 3721 ("RXing /C/, enable AutoNeg and stop forcing link.\r\n"); 3722 E1000_WRITE_REG(hw, TXCW, hw->txcw); 3723 E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU)); 3724 } 3725 return 0; 3726 } 3727 3728 /****************************************************************************** 3729 * Configure the MAC-to-PHY interface for 10/100Mbps 3730 * 3731 * hw - Struct containing variables accessed by shared code 3732 ******************************************************************************/ 3733 static int32_t 3734 e1000_configure_kmrn_for_10_100(struct e1000_hw *hw, uint16_t duplex) 3735 { 3736 int32_t ret_val = E1000_SUCCESS; 3737 uint32_t tipg; 3738 uint16_t reg_data; 3739 3740 DEBUGFUNC(); 3741 3742 reg_data = E1000_KUMCTRLSTA_HD_CTRL_10_100_DEFAULT; 3743 ret_val = e1000_write_kmrn_reg(hw, 3744 E1000_KUMCTRLSTA_OFFSET_HD_CTRL, reg_data); 3745 if (ret_val) 3746 return ret_val; 3747 3748 /* Configure Transmit Inter-Packet Gap */ 3749 tipg = E1000_READ_REG(hw, TIPG); 3750 tipg &= ~E1000_TIPG_IPGT_MASK; 3751 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_10_100; 3752 E1000_WRITE_REG(hw, TIPG, tipg); 3753 3754 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data); 3755 3756 if (ret_val) 3757 return ret_val; 3758 3759 if (duplex == HALF_DUPLEX) 3760 reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER; 3761 else 3762 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; 3763 3764 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data); 3765 3766 return ret_val; 3767 } 3768 3769 static int32_t 3770 e1000_configure_kmrn_for_1000(struct e1000_hw *hw) 3771 { 3772 int32_t ret_val = E1000_SUCCESS; 3773 uint16_t reg_data; 3774 uint32_t tipg; 3775 3776 DEBUGFUNC(); 3777 3778 reg_data = E1000_KUMCTRLSTA_HD_CTRL_1000_DEFAULT; 3779 ret_val = e1000_write_kmrn_reg(hw, 3780 E1000_KUMCTRLSTA_OFFSET_HD_CTRL, reg_data); 3781 if (ret_val) 3782 return ret_val; 3783 3784 /* Configure Transmit Inter-Packet Gap */ 3785 tipg = E1000_READ_REG(hw, TIPG); 3786 tipg &= ~E1000_TIPG_IPGT_MASK; 3787 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000; 3788 E1000_WRITE_REG(hw, TIPG, tipg); 3789 3790 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data); 3791 3792 if (ret_val) 3793 return ret_val; 3794 3795 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; 3796 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data); 3797 3798 return ret_val; 3799 } 3800 3801 /****************************************************************************** 3802 * Detects the current speed and duplex settings of the hardware. 3803 * 3804 * hw - Struct containing variables accessed by shared code 3805 * speed - Speed of the connection 3806 * duplex - Duplex setting of the connection 3807 *****************************************************************************/ 3808 static int 3809 e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t *speed, 3810 uint16_t *duplex) 3811 { 3812 uint32_t status; 3813 int32_t ret_val; 3814 uint16_t phy_data; 3815 3816 DEBUGFUNC(); 3817 3818 if (hw->mac_type >= e1000_82543) { 3819 status = E1000_READ_REG(hw, STATUS); 3820 if (status & E1000_STATUS_SPEED_1000) { 3821 *speed = SPEED_1000; 3822 DEBUGOUT("1000 Mbs, "); 3823 } else if (status & E1000_STATUS_SPEED_100) { 3824 *speed = SPEED_100; 3825 DEBUGOUT("100 Mbs, "); 3826 } else { 3827 *speed = SPEED_10; 3828 DEBUGOUT("10 Mbs, "); 3829 } 3830 3831 if (status & E1000_STATUS_FD) { 3832 *duplex = FULL_DUPLEX; 3833 DEBUGOUT("Full Duplex\r\n"); 3834 } else { 3835 *duplex = HALF_DUPLEX; 3836 DEBUGOUT(" Half Duplex\r\n"); 3837 } 3838 } else { 3839 DEBUGOUT("1000 Mbs, Full Duplex\r\n"); 3840 *speed = SPEED_1000; 3841 *duplex = FULL_DUPLEX; 3842 } 3843 3844 /* IGP01 PHY may advertise full duplex operation after speed downgrade 3845 * even if it is operating at half duplex. Here we set the duplex 3846 * settings to match the duplex in the link partner's capabilities. 3847 */ 3848 if (hw->phy_type == e1000_phy_igp && hw->speed_downgraded) { 3849 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data); 3850 if (ret_val) 3851 return ret_val; 3852 3853 if (!(phy_data & NWAY_ER_LP_NWAY_CAPS)) 3854 *duplex = HALF_DUPLEX; 3855 else { 3856 ret_val = e1000_read_phy_reg(hw, 3857 PHY_LP_ABILITY, &phy_data); 3858 if (ret_val) 3859 return ret_val; 3860 if ((*speed == SPEED_100 && 3861 !(phy_data & NWAY_LPAR_100TX_FD_CAPS)) 3862 || (*speed == SPEED_10 3863 && !(phy_data & NWAY_LPAR_10T_FD_CAPS))) 3864 *duplex = HALF_DUPLEX; 3865 } 3866 } 3867 3868 if ((hw->mac_type == e1000_80003es2lan) && 3869 (hw->media_type == e1000_media_type_copper)) { 3870 if (*speed == SPEED_1000) 3871 ret_val = e1000_configure_kmrn_for_1000(hw); 3872 else 3873 ret_val = e1000_configure_kmrn_for_10_100(hw, *duplex); 3874 if (ret_val) 3875 return ret_val; 3876 } 3877 return E1000_SUCCESS; 3878 } 3879 3880 /****************************************************************************** 3881 * Blocks until autoneg completes or times out (~4.5 seconds) 3882 * 3883 * hw - Struct containing variables accessed by shared code 3884 ******************************************************************************/ 3885 static int 3886 e1000_wait_autoneg(struct e1000_hw *hw) 3887 { 3888 uint16_t i; 3889 uint16_t phy_data; 3890 3891 DEBUGFUNC(); 3892 DEBUGOUT("Waiting for Auto-Neg to complete.\n"); 3893 3894 /* We will wait for autoneg to complete or 4.5 seconds to expire. */ 3895 for (i = PHY_AUTO_NEG_TIME; i > 0; i--) { 3896 /* Read the MII Status Register and wait for Auto-Neg 3897 * Complete bit to be set. 3898 */ 3899 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) { 3900 DEBUGOUT("PHY Read Error\n"); 3901 return -E1000_ERR_PHY; 3902 } 3903 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) { 3904 DEBUGOUT("PHY Read Error\n"); 3905 return -E1000_ERR_PHY; 3906 } 3907 if (phy_data & MII_SR_AUTONEG_COMPLETE) { 3908 DEBUGOUT("Auto-Neg complete.\n"); 3909 return 0; 3910 } 3911 mdelay(100); 3912 } 3913 DEBUGOUT("Auto-Neg timedout.\n"); 3914 return -E1000_ERR_TIMEOUT; 3915 } 3916 3917 /****************************************************************************** 3918 * Raises the Management Data Clock 3919 * 3920 * hw - Struct containing variables accessed by shared code 3921 * ctrl - Device control register's current value 3922 ******************************************************************************/ 3923 static void 3924 e1000_raise_mdi_clk(struct e1000_hw *hw, uint32_t * ctrl) 3925 { 3926 /* Raise the clock input to the Management Data Clock (by setting the MDC 3927 * bit), and then delay 2 microseconds. 3928 */ 3929 E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC)); 3930 E1000_WRITE_FLUSH(hw); 3931 udelay(2); 3932 } 3933 3934 /****************************************************************************** 3935 * Lowers the Management Data Clock 3936 * 3937 * hw - Struct containing variables accessed by shared code 3938 * ctrl - Device control register's current value 3939 ******************************************************************************/ 3940 static void 3941 e1000_lower_mdi_clk(struct e1000_hw *hw, uint32_t * ctrl) 3942 { 3943 /* Lower the clock input to the Management Data Clock (by clearing the MDC 3944 * bit), and then delay 2 microseconds. 3945 */ 3946 E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC)); 3947 E1000_WRITE_FLUSH(hw); 3948 udelay(2); 3949 } 3950 3951 /****************************************************************************** 3952 * Shifts data bits out to the PHY 3953 * 3954 * hw - Struct containing variables accessed by shared code 3955 * data - Data to send out to the PHY 3956 * count - Number of bits to shift out 3957 * 3958 * Bits are shifted out in MSB to LSB order. 3959 ******************************************************************************/ 3960 static void 3961 e1000_shift_out_mdi_bits(struct e1000_hw *hw, uint32_t data, uint16_t count) 3962 { 3963 uint32_t ctrl; 3964 uint32_t mask; 3965 3966 /* We need to shift "count" number of bits out to the PHY. So, the value 3967 * in the "data" parameter will be shifted out to the PHY one bit at a 3968 * time. In order to do this, "data" must be broken down into bits. 3969 */ 3970 mask = 0x01; 3971 mask <<= (count - 1); 3972 3973 ctrl = E1000_READ_REG(hw, CTRL); 3974 3975 /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */ 3976 ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR); 3977 3978 while (mask) { 3979 /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and 3980 * then raising and lowering the Management Data Clock. A "0" is 3981 * shifted out to the PHY by setting the MDIO bit to "0" and then 3982 * raising and lowering the clock. 3983 */ 3984 if (data & mask) 3985 ctrl |= E1000_CTRL_MDIO; 3986 else 3987 ctrl &= ~E1000_CTRL_MDIO; 3988 3989 E1000_WRITE_REG(hw, CTRL, ctrl); 3990 E1000_WRITE_FLUSH(hw); 3991 3992 udelay(2); 3993 3994 e1000_raise_mdi_clk(hw, &ctrl); 3995 e1000_lower_mdi_clk(hw, &ctrl); 3996 3997 mask = mask >> 1; 3998 } 3999 } 4000 4001 /****************************************************************************** 4002 * Shifts data bits in from the PHY 4003 * 4004 * hw - Struct containing variables accessed by shared code 4005 * 4006 * Bits are shifted in in MSB to LSB order. 4007 ******************************************************************************/ 4008 static uint16_t 4009 e1000_shift_in_mdi_bits(struct e1000_hw *hw) 4010 { 4011 uint32_t ctrl; 4012 uint16_t data = 0; 4013 uint8_t i; 4014 4015 /* In order to read a register from the PHY, we need to shift in a total 4016 * of 18 bits from the PHY. The first two bit (turnaround) times are used 4017 * to avoid contention on the MDIO pin when a read operation is performed. 4018 * These two bits are ignored by us and thrown away. Bits are "shifted in" 4019 * by raising the input to the Management Data Clock (setting the MDC bit), 4020 * and then reading the value of the MDIO bit. 4021 */ 4022 ctrl = E1000_READ_REG(hw, CTRL); 4023 4024 /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */ 4025 ctrl &= ~E1000_CTRL_MDIO_DIR; 4026 ctrl &= ~E1000_CTRL_MDIO; 4027 4028 E1000_WRITE_REG(hw, CTRL, ctrl); 4029 E1000_WRITE_FLUSH(hw); 4030 4031 /* Raise and Lower the clock before reading in the data. This accounts for 4032 * the turnaround bits. The first clock occurred when we clocked out the 4033 * last bit of the Register Address. 4034 */ 4035 e1000_raise_mdi_clk(hw, &ctrl); 4036 e1000_lower_mdi_clk(hw, &ctrl); 4037 4038 for (data = 0, i = 0; i < 16; i++) { 4039 data = data << 1; 4040 e1000_raise_mdi_clk(hw, &ctrl); 4041 ctrl = E1000_READ_REG(hw, CTRL); 4042 /* Check to see if we shifted in a "1". */ 4043 if (ctrl & E1000_CTRL_MDIO) 4044 data |= 1; 4045 e1000_lower_mdi_clk(hw, &ctrl); 4046 } 4047 4048 e1000_raise_mdi_clk(hw, &ctrl); 4049 e1000_lower_mdi_clk(hw, &ctrl); 4050 4051 return data; 4052 } 4053 4054 /***************************************************************************** 4055 * Reads the value from a PHY register 4056 * 4057 * hw - Struct containing variables accessed by shared code 4058 * reg_addr - address of the PHY register to read 4059 ******************************************************************************/ 4060 static int 4061 e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t * phy_data) 4062 { 4063 uint32_t i; 4064 uint32_t mdic = 0; 4065 const uint32_t phy_addr = 1; 4066 4067 if (reg_addr > MAX_PHY_REG_ADDRESS) { 4068 DEBUGOUT("PHY Address %d is out of range\n", reg_addr); 4069 return -E1000_ERR_PARAM; 4070 } 4071 4072 if (hw->mac_type > e1000_82543) { 4073 /* Set up Op-code, Phy Address, and register address in the MDI 4074 * Control register. The MAC will take care of interfacing with the 4075 * PHY to retrieve the desired data. 4076 */ 4077 mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) | 4078 (phy_addr << E1000_MDIC_PHY_SHIFT) | 4079 (E1000_MDIC_OP_READ)); 4080 4081 E1000_WRITE_REG(hw, MDIC, mdic); 4082 4083 /* Poll the ready bit to see if the MDI read completed */ 4084 for (i = 0; i < 64; i++) { 4085 udelay(10); 4086 mdic = E1000_READ_REG(hw, MDIC); 4087 if (mdic & E1000_MDIC_READY) 4088 break; 4089 } 4090 if (!(mdic & E1000_MDIC_READY)) { 4091 DEBUGOUT("MDI Read did not complete\n"); 4092 return -E1000_ERR_PHY; 4093 } 4094 if (mdic & E1000_MDIC_ERROR) { 4095 DEBUGOUT("MDI Error\n"); 4096 return -E1000_ERR_PHY; 4097 } 4098 *phy_data = (uint16_t) mdic; 4099 } else { 4100 /* We must first send a preamble through the MDIO pin to signal the 4101 * beginning of an MII instruction. This is done by sending 32 4102 * consecutive "1" bits. 4103 */ 4104 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); 4105 4106 /* Now combine the next few fields that are required for a read 4107 * operation. We use this method instead of calling the 4108 * e1000_shift_out_mdi_bits routine five different times. The format of 4109 * a MII read instruction consists of a shift out of 14 bits and is 4110 * defined as follows: 4111 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr> 4112 * followed by a shift in of 18 bits. This first two bits shifted in 4113 * are TurnAround bits used to avoid contention on the MDIO pin when a 4114 * READ operation is performed. These two bits are thrown away 4115 * followed by a shift in of 16 bits which contains the desired data. 4116 */ 4117 mdic = ((reg_addr) | (phy_addr << 5) | 4118 (PHY_OP_READ << 10) | (PHY_SOF << 12)); 4119 4120 e1000_shift_out_mdi_bits(hw, mdic, 14); 4121 4122 /* Now that we've shifted out the read command to the MII, we need to 4123 * "shift in" the 16-bit value (18 total bits) of the requested PHY 4124 * register address. 4125 */ 4126 *phy_data = e1000_shift_in_mdi_bits(hw); 4127 } 4128 return 0; 4129 } 4130 4131 /****************************************************************************** 4132 * Writes a value to a PHY register 4133 * 4134 * hw - Struct containing variables accessed by shared code 4135 * reg_addr - address of the PHY register to write 4136 * data - data to write to the PHY 4137 ******************************************************************************/ 4138 static int 4139 e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t phy_data) 4140 { 4141 uint32_t i; 4142 uint32_t mdic = 0; 4143 const uint32_t phy_addr = 1; 4144 4145 if (reg_addr > MAX_PHY_REG_ADDRESS) { 4146 DEBUGOUT("PHY Address %d is out of range\n", reg_addr); 4147 return -E1000_ERR_PARAM; 4148 } 4149 4150 if (hw->mac_type > e1000_82543) { 4151 /* Set up Op-code, Phy Address, register address, and data intended 4152 * for the PHY register in the MDI Control register. The MAC will take 4153 * care of interfacing with the PHY to send the desired data. 4154 */ 4155 mdic = (((uint32_t) phy_data) | 4156 (reg_addr << E1000_MDIC_REG_SHIFT) | 4157 (phy_addr << E1000_MDIC_PHY_SHIFT) | 4158 (E1000_MDIC_OP_WRITE)); 4159 4160 E1000_WRITE_REG(hw, MDIC, mdic); 4161 4162 /* Poll the ready bit to see if the MDI read completed */ 4163 for (i = 0; i < 64; i++) { 4164 udelay(10); 4165 mdic = E1000_READ_REG(hw, MDIC); 4166 if (mdic & E1000_MDIC_READY) 4167 break; 4168 } 4169 if (!(mdic & E1000_MDIC_READY)) { 4170 DEBUGOUT("MDI Write did not complete\n"); 4171 return -E1000_ERR_PHY; 4172 } 4173 } else { 4174 /* We'll need to use the SW defined pins to shift the write command 4175 * out to the PHY. We first send a preamble to the PHY to signal the 4176 * beginning of the MII instruction. This is done by sending 32 4177 * consecutive "1" bits. 4178 */ 4179 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); 4180 4181 /* Now combine the remaining required fields that will indicate a 4182 * write operation. We use this method instead of calling the 4183 * e1000_shift_out_mdi_bits routine for each field in the command. The 4184 * format of a MII write instruction is as follows: 4185 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>. 4186 */ 4187 mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) | 4188 (PHY_OP_WRITE << 12) | (PHY_SOF << 14)); 4189 mdic <<= 16; 4190 mdic |= (uint32_t) phy_data; 4191 4192 e1000_shift_out_mdi_bits(hw, mdic, 32); 4193 } 4194 return 0; 4195 } 4196 4197 /****************************************************************************** 4198 * Checks if PHY reset is blocked due to SOL/IDER session, for example. 4199 * Returning E1000_BLK_PHY_RESET isn't necessarily an error. But it's up to 4200 * the caller to figure out how to deal with it. 4201 * 4202 * hw - Struct containing variables accessed by shared code 4203 * 4204 * returns: - E1000_BLK_PHY_RESET 4205 * E1000_SUCCESS 4206 * 4207 *****************************************************************************/ 4208 int32_t 4209 e1000_check_phy_reset_block(struct e1000_hw *hw) 4210 { 4211 uint32_t manc = 0; 4212 uint32_t fwsm = 0; 4213 4214 if (hw->mac_type == e1000_ich8lan) { 4215 fwsm = E1000_READ_REG(hw, FWSM); 4216 return (fwsm & E1000_FWSM_RSPCIPHY) ? E1000_SUCCESS 4217 : E1000_BLK_PHY_RESET; 4218 } 4219 4220 if (hw->mac_type > e1000_82547_rev_2) 4221 manc = E1000_READ_REG(hw, MANC); 4222 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ? 4223 E1000_BLK_PHY_RESET : E1000_SUCCESS; 4224 } 4225 4226 /*************************************************************************** 4227 * Checks if the PHY configuration is done 4228 * 4229 * hw: Struct containing variables accessed by shared code 4230 * 4231 * returns: - E1000_ERR_RESET if fail to reset MAC 4232 * E1000_SUCCESS at any other case. 4233 * 4234 ***************************************************************************/ 4235 static int32_t 4236 e1000_get_phy_cfg_done(struct e1000_hw *hw) 4237 { 4238 int32_t timeout = PHY_CFG_TIMEOUT; 4239 uint32_t cfg_mask = E1000_EEPROM_CFG_DONE; 4240 4241 DEBUGFUNC(); 4242 4243 switch (hw->mac_type) { 4244 default: 4245 mdelay(10); 4246 break; 4247 4248 case e1000_80003es2lan: 4249 /* Separate *_CFG_DONE_* bit for each port */ 4250 if (e1000_is_second_port(hw)) 4251 cfg_mask = E1000_EEPROM_CFG_DONE_PORT_1; 4252 /* Fall Through */ 4253 4254 case e1000_82571: 4255 case e1000_82572: 4256 while (timeout) { 4257 if (E1000_READ_REG(hw, EEMNGCTL) & cfg_mask) 4258 break; 4259 else 4260 mdelay(1); 4261 timeout--; 4262 } 4263 if (!timeout) { 4264 DEBUGOUT("MNG configuration cycle has not " 4265 "completed.\n"); 4266 return -E1000_ERR_RESET; 4267 } 4268 break; 4269 } 4270 4271 return E1000_SUCCESS; 4272 } 4273 4274 /****************************************************************************** 4275 * Returns the PHY to the power-on reset state 4276 * 4277 * hw - Struct containing variables accessed by shared code 4278 ******************************************************************************/ 4279 int32_t 4280 e1000_phy_hw_reset(struct e1000_hw *hw) 4281 { 4282 uint16_t swfw = E1000_SWFW_PHY0_SM; 4283 uint32_t ctrl, ctrl_ext; 4284 uint32_t led_ctrl; 4285 int32_t ret_val; 4286 4287 DEBUGFUNC(); 4288 4289 /* In the case of the phy reset being blocked, it's not an error, we 4290 * simply return success without performing the reset. */ 4291 ret_val = e1000_check_phy_reset_block(hw); 4292 if (ret_val) 4293 return E1000_SUCCESS; 4294 4295 DEBUGOUT("Resetting Phy...\n"); 4296 4297 if (hw->mac_type > e1000_82543) { 4298 if (e1000_is_second_port(hw)) 4299 swfw = E1000_SWFW_PHY1_SM; 4300 4301 if (e1000_swfw_sync_acquire(hw, swfw)) { 4302 DEBUGOUT("Unable to acquire swfw sync\n"); 4303 return -E1000_ERR_SWFW_SYNC; 4304 } 4305 4306 /* Read the device control register and assert the E1000_CTRL_PHY_RST 4307 * bit. Then, take it out of reset. 4308 */ 4309 ctrl = E1000_READ_REG(hw, CTRL); 4310 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST); 4311 E1000_WRITE_FLUSH(hw); 4312 4313 if (hw->mac_type < e1000_82571) 4314 udelay(10); 4315 else 4316 udelay(100); 4317 4318 E1000_WRITE_REG(hw, CTRL, ctrl); 4319 E1000_WRITE_FLUSH(hw); 4320 4321 if (hw->mac_type >= e1000_82571) 4322 mdelay(10); 4323 4324 } else { 4325 /* Read the Extended Device Control Register, assert the PHY_RESET_DIR 4326 * bit to put the PHY into reset. Then, take it out of reset. 4327 */ 4328 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 4329 ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR; 4330 ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA; 4331 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 4332 E1000_WRITE_FLUSH(hw); 4333 mdelay(10); 4334 ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA; 4335 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 4336 E1000_WRITE_FLUSH(hw); 4337 } 4338 udelay(150); 4339 4340 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { 4341 /* Configure activity LED after PHY reset */ 4342 led_ctrl = E1000_READ_REG(hw, LEDCTL); 4343 led_ctrl &= IGP_ACTIVITY_LED_MASK; 4344 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); 4345 E1000_WRITE_REG(hw, LEDCTL, led_ctrl); 4346 } 4347 4348 /* Wait for FW to finish PHY configuration. */ 4349 ret_val = e1000_get_phy_cfg_done(hw); 4350 if (ret_val != E1000_SUCCESS) 4351 return ret_val; 4352 4353 return ret_val; 4354 } 4355 4356 /****************************************************************************** 4357 * IGP phy init script - initializes the GbE PHY 4358 * 4359 * hw - Struct containing variables accessed by shared code 4360 *****************************************************************************/ 4361 static void 4362 e1000_phy_init_script(struct e1000_hw *hw) 4363 { 4364 uint32_t ret_val; 4365 uint16_t phy_saved_data; 4366 DEBUGFUNC(); 4367 4368 if (hw->phy_init_script) { 4369 mdelay(20); 4370 4371 /* Save off the current value of register 0x2F5B to be 4372 * restored at the end of this routine. */ 4373 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data); 4374 4375 /* Disabled the PHY transmitter */ 4376 e1000_write_phy_reg(hw, 0x2F5B, 0x0003); 4377 4378 mdelay(20); 4379 4380 e1000_write_phy_reg(hw, 0x0000, 0x0140); 4381 4382 mdelay(5); 4383 4384 switch (hw->mac_type) { 4385 case e1000_82541: 4386 case e1000_82547: 4387 e1000_write_phy_reg(hw, 0x1F95, 0x0001); 4388 4389 e1000_write_phy_reg(hw, 0x1F71, 0xBD21); 4390 4391 e1000_write_phy_reg(hw, 0x1F79, 0x0018); 4392 4393 e1000_write_phy_reg(hw, 0x1F30, 0x1600); 4394 4395 e1000_write_phy_reg(hw, 0x1F31, 0x0014); 4396 4397 e1000_write_phy_reg(hw, 0x1F32, 0x161C); 4398 4399 e1000_write_phy_reg(hw, 0x1F94, 0x0003); 4400 4401 e1000_write_phy_reg(hw, 0x1F96, 0x003F); 4402 4403 e1000_write_phy_reg(hw, 0x2010, 0x0008); 4404 break; 4405 4406 case e1000_82541_rev_2: 4407 case e1000_82547_rev_2: 4408 e1000_write_phy_reg(hw, 0x1F73, 0x0099); 4409 break; 4410 default: 4411 break; 4412 } 4413 4414 e1000_write_phy_reg(hw, 0x0000, 0x3300); 4415 4416 mdelay(20); 4417 4418 /* Now enable the transmitter */ 4419 if (!ret_val) 4420 e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data); 4421 4422 if (hw->mac_type == e1000_82547) { 4423 uint16_t fused, fine, coarse; 4424 4425 /* Move to analog registers page */ 4426 e1000_read_phy_reg(hw, 4427 IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused); 4428 4429 if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) { 4430 e1000_read_phy_reg(hw, 4431 IGP01E1000_ANALOG_FUSE_STATUS, &fused); 4432 4433 fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK; 4434 coarse = fused 4435 & IGP01E1000_ANALOG_FUSE_COARSE_MASK; 4436 4437 if (coarse > 4438 IGP01E1000_ANALOG_FUSE_COARSE_THRESH) { 4439 coarse -= 4440 IGP01E1000_ANALOG_FUSE_COARSE_10; 4441 fine -= IGP01E1000_ANALOG_FUSE_FINE_1; 4442 } else if (coarse 4443 == IGP01E1000_ANALOG_FUSE_COARSE_THRESH) 4444 fine -= IGP01E1000_ANALOG_FUSE_FINE_10; 4445 4446 fused = (fused 4447 & IGP01E1000_ANALOG_FUSE_POLY_MASK) | 4448 (fine 4449 & IGP01E1000_ANALOG_FUSE_FINE_MASK) | 4450 (coarse 4451 & IGP01E1000_ANALOG_FUSE_COARSE_MASK); 4452 4453 e1000_write_phy_reg(hw, 4454 IGP01E1000_ANALOG_FUSE_CONTROL, fused); 4455 e1000_write_phy_reg(hw, 4456 IGP01E1000_ANALOG_FUSE_BYPASS, 4457 IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL); 4458 } 4459 } 4460 } 4461 } 4462 4463 /****************************************************************************** 4464 * Resets the PHY 4465 * 4466 * hw - Struct containing variables accessed by shared code 4467 * 4468 * Sets bit 15 of the MII Control register 4469 ******************************************************************************/ 4470 int32_t 4471 e1000_phy_reset(struct e1000_hw *hw) 4472 { 4473 int32_t ret_val; 4474 uint16_t phy_data; 4475 4476 DEBUGFUNC(); 4477 4478 /* In the case of the phy reset being blocked, it's not an error, we 4479 * simply return success without performing the reset. */ 4480 ret_val = e1000_check_phy_reset_block(hw); 4481 if (ret_val) 4482 return E1000_SUCCESS; 4483 4484 switch (hw->phy_type) { 4485 case e1000_phy_igp: 4486 case e1000_phy_igp_2: 4487 case e1000_phy_igp_3: 4488 case e1000_phy_ife: 4489 ret_val = e1000_phy_hw_reset(hw); 4490 if (ret_val) 4491 return ret_val; 4492 break; 4493 default: 4494 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data); 4495 if (ret_val) 4496 return ret_val; 4497 4498 phy_data |= MII_CR_RESET; 4499 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data); 4500 if (ret_val) 4501 return ret_val; 4502 4503 udelay(1); 4504 break; 4505 } 4506 4507 if (hw->phy_type == e1000_phy_igp || hw->phy_type == e1000_phy_igp_2) 4508 e1000_phy_init_script(hw); 4509 4510 return E1000_SUCCESS; 4511 } 4512 4513 static int e1000_set_phy_type (struct e1000_hw *hw) 4514 { 4515 DEBUGFUNC (); 4516 4517 if (hw->mac_type == e1000_undefined) 4518 return -E1000_ERR_PHY_TYPE; 4519 4520 switch (hw->phy_id) { 4521 case M88E1000_E_PHY_ID: 4522 case M88E1000_I_PHY_ID: 4523 case M88E1011_I_PHY_ID: 4524 case M88E1111_I_PHY_ID: 4525 hw->phy_type = e1000_phy_m88; 4526 break; 4527 case IGP01E1000_I_PHY_ID: 4528 if (hw->mac_type == e1000_82541 || 4529 hw->mac_type == e1000_82541_rev_2 || 4530 hw->mac_type == e1000_82547 || 4531 hw->mac_type == e1000_82547_rev_2) { 4532 hw->phy_type = e1000_phy_igp; 4533 hw->phy_type = e1000_phy_igp; 4534 break; 4535 } 4536 case IGP03E1000_E_PHY_ID: 4537 hw->phy_type = e1000_phy_igp_3; 4538 break; 4539 case IFE_E_PHY_ID: 4540 case IFE_PLUS_E_PHY_ID: 4541 case IFE_C_E_PHY_ID: 4542 hw->phy_type = e1000_phy_ife; 4543 break; 4544 case GG82563_E_PHY_ID: 4545 if (hw->mac_type == e1000_80003es2lan) { 4546 hw->phy_type = e1000_phy_gg82563; 4547 break; 4548 } 4549 case BME1000_E_PHY_ID: 4550 hw->phy_type = e1000_phy_bm; 4551 break; 4552 /* Fall Through */ 4553 default: 4554 /* Should never have loaded on this device */ 4555 hw->phy_type = e1000_phy_undefined; 4556 return -E1000_ERR_PHY_TYPE; 4557 } 4558 4559 return E1000_SUCCESS; 4560 } 4561 4562 /****************************************************************************** 4563 * Probes the expected PHY address for known PHY IDs 4564 * 4565 * hw - Struct containing variables accessed by shared code 4566 ******************************************************************************/ 4567 static int32_t 4568 e1000_detect_gig_phy(struct e1000_hw *hw) 4569 { 4570 int32_t phy_init_status, ret_val; 4571 uint16_t phy_id_high, phy_id_low; 4572 boolean_t match = FALSE; 4573 4574 DEBUGFUNC(); 4575 4576 /* The 82571 firmware may still be configuring the PHY. In this 4577 * case, we cannot access the PHY until the configuration is done. So 4578 * we explicitly set the PHY values. */ 4579 if (hw->mac_type == e1000_82571 || 4580 hw->mac_type == e1000_82572) { 4581 hw->phy_id = IGP01E1000_I_PHY_ID; 4582 hw->phy_type = e1000_phy_igp_2; 4583 return E1000_SUCCESS; 4584 } 4585 4586 /* ESB-2 PHY reads require e1000_phy_gg82563 to be set because of a 4587 * work- around that forces PHY page 0 to be set or the reads fail. 4588 * The rest of the code in this routine uses e1000_read_phy_reg to 4589 * read the PHY ID. So for ESB-2 we need to have this set so our 4590 * reads won't fail. If the attached PHY is not a e1000_phy_gg82563, 4591 * the routines below will figure this out as well. */ 4592 if (hw->mac_type == e1000_80003es2lan) 4593 hw->phy_type = e1000_phy_gg82563; 4594 4595 /* Read the PHY ID Registers to identify which PHY is onboard. */ 4596 ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high); 4597 if (ret_val) 4598 return ret_val; 4599 4600 hw->phy_id = (uint32_t) (phy_id_high << 16); 4601 udelay(20); 4602 ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low); 4603 if (ret_val) 4604 return ret_val; 4605 4606 hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK); 4607 hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK; 4608 4609 switch (hw->mac_type) { 4610 case e1000_82543: 4611 if (hw->phy_id == M88E1000_E_PHY_ID) 4612 match = TRUE; 4613 break; 4614 case e1000_82544: 4615 if (hw->phy_id == M88E1000_I_PHY_ID) 4616 match = TRUE; 4617 break; 4618 case e1000_82540: 4619 case e1000_82545: 4620 case e1000_82545_rev_3: 4621 case e1000_82546: 4622 case e1000_82546_rev_3: 4623 if (hw->phy_id == M88E1011_I_PHY_ID) 4624 match = TRUE; 4625 break; 4626 case e1000_82541: 4627 case e1000_82541_rev_2: 4628 case e1000_82547: 4629 case e1000_82547_rev_2: 4630 if(hw->phy_id == IGP01E1000_I_PHY_ID) 4631 match = TRUE; 4632 4633 break; 4634 case e1000_82573: 4635 if (hw->phy_id == M88E1111_I_PHY_ID) 4636 match = TRUE; 4637 break; 4638 case e1000_82574: 4639 if (hw->phy_id == BME1000_E_PHY_ID) 4640 match = TRUE; 4641 break; 4642 case e1000_80003es2lan: 4643 if (hw->phy_id == GG82563_E_PHY_ID) 4644 match = TRUE; 4645 break; 4646 case e1000_ich8lan: 4647 if (hw->phy_id == IGP03E1000_E_PHY_ID) 4648 match = TRUE; 4649 if (hw->phy_id == IFE_E_PHY_ID) 4650 match = TRUE; 4651 if (hw->phy_id == IFE_PLUS_E_PHY_ID) 4652 match = TRUE; 4653 if (hw->phy_id == IFE_C_E_PHY_ID) 4654 match = TRUE; 4655 break; 4656 default: 4657 DEBUGOUT("Invalid MAC type %d\n", hw->mac_type); 4658 return -E1000_ERR_CONFIG; 4659 } 4660 4661 phy_init_status = e1000_set_phy_type(hw); 4662 4663 if ((match) && (phy_init_status == E1000_SUCCESS)) { 4664 DEBUGOUT("PHY ID 0x%X detected\n", hw->phy_id); 4665 return 0; 4666 } 4667 DEBUGOUT("Invalid PHY ID 0x%X\n", hw->phy_id); 4668 return -E1000_ERR_PHY; 4669 } 4670 4671 /***************************************************************************** 4672 * Set media type and TBI compatibility. 4673 * 4674 * hw - Struct containing variables accessed by shared code 4675 * **************************************************************************/ 4676 void 4677 e1000_set_media_type(struct e1000_hw *hw) 4678 { 4679 uint32_t status; 4680 4681 DEBUGFUNC(); 4682 4683 if (hw->mac_type != e1000_82543) { 4684 /* tbi_compatibility is only valid on 82543 */ 4685 hw->tbi_compatibility_en = FALSE; 4686 } 4687 4688 switch (hw->device_id) { 4689 case E1000_DEV_ID_82545GM_SERDES: 4690 case E1000_DEV_ID_82546GB_SERDES: 4691 case E1000_DEV_ID_82571EB_SERDES: 4692 case E1000_DEV_ID_82571EB_SERDES_DUAL: 4693 case E1000_DEV_ID_82571EB_SERDES_QUAD: 4694 case E1000_DEV_ID_82572EI_SERDES: 4695 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT: 4696 hw->media_type = e1000_media_type_internal_serdes; 4697 break; 4698 default: 4699 switch (hw->mac_type) { 4700 case e1000_82542_rev2_0: 4701 case e1000_82542_rev2_1: 4702 hw->media_type = e1000_media_type_fiber; 4703 break; 4704 case e1000_ich8lan: 4705 case e1000_82573: 4706 case e1000_82574: 4707 /* The STATUS_TBIMODE bit is reserved or reused 4708 * for the this device. 4709 */ 4710 hw->media_type = e1000_media_type_copper; 4711 break; 4712 default: 4713 status = E1000_READ_REG(hw, STATUS); 4714 if (status & E1000_STATUS_TBIMODE) { 4715 hw->media_type = e1000_media_type_fiber; 4716 /* tbi_compatibility not valid on fiber */ 4717 hw->tbi_compatibility_en = FALSE; 4718 } else { 4719 hw->media_type = e1000_media_type_copper; 4720 } 4721 break; 4722 } 4723 } 4724 } 4725 4726 /** 4727 * e1000_sw_init - Initialize general software structures (struct e1000_adapter) 4728 * 4729 * e1000_sw_init initializes the Adapter private data structure. 4730 * Fields are initialized based on PCI device information and 4731 * OS network device settings (MTU size). 4732 **/ 4733 4734 static int 4735 e1000_sw_init(struct eth_device *nic) 4736 { 4737 struct e1000_hw *hw = (typeof(hw)) nic->priv; 4738 int result; 4739 4740 /* PCI config space info */ 4741 pci_read_config_word(hw->pdev, PCI_VENDOR_ID, &hw->vendor_id); 4742 pci_read_config_word(hw->pdev, PCI_DEVICE_ID, &hw->device_id); 4743 pci_read_config_word(hw->pdev, PCI_SUBSYSTEM_VENDOR_ID, 4744 &hw->subsystem_vendor_id); 4745 pci_read_config_word(hw->pdev, PCI_SUBSYSTEM_ID, &hw->subsystem_id); 4746 4747 pci_read_config_byte(hw->pdev, PCI_REVISION_ID, &hw->revision_id); 4748 pci_read_config_word(hw->pdev, PCI_COMMAND, &hw->pci_cmd_word); 4749 4750 /* identify the MAC */ 4751 result = e1000_set_mac_type(hw); 4752 if (result) { 4753 E1000_ERR(hw->nic, "Unknown MAC Type\n"); 4754 return result; 4755 } 4756 4757 switch (hw->mac_type) { 4758 default: 4759 break; 4760 case e1000_82541: 4761 case e1000_82547: 4762 case e1000_82541_rev_2: 4763 case e1000_82547_rev_2: 4764 hw->phy_init_script = 1; 4765 break; 4766 } 4767 4768 /* flow control settings */ 4769 hw->fc_high_water = E1000_FC_HIGH_THRESH; 4770 hw->fc_low_water = E1000_FC_LOW_THRESH; 4771 hw->fc_pause_time = E1000_FC_PAUSE_TIME; 4772 hw->fc_send_xon = 1; 4773 4774 /* Media type - copper or fiber */ 4775 e1000_set_media_type(hw); 4776 4777 if (hw->mac_type >= e1000_82543) { 4778 uint32_t status = E1000_READ_REG(hw, STATUS); 4779 4780 if (status & E1000_STATUS_TBIMODE) { 4781 DEBUGOUT("fiber interface\n"); 4782 hw->media_type = e1000_media_type_fiber; 4783 } else { 4784 DEBUGOUT("copper interface\n"); 4785 hw->media_type = e1000_media_type_copper; 4786 } 4787 } else { 4788 hw->media_type = e1000_media_type_fiber; 4789 } 4790 4791 hw->tbi_compatibility_en = TRUE; 4792 hw->wait_autoneg_complete = TRUE; 4793 if (hw->mac_type < e1000_82543) 4794 hw->report_tx_early = 0; 4795 else 4796 hw->report_tx_early = 1; 4797 4798 return E1000_SUCCESS; 4799 } 4800 4801 void 4802 fill_rx(struct e1000_hw *hw) 4803 { 4804 struct e1000_rx_desc *rd; 4805 4806 rx_last = rx_tail; 4807 rd = rx_base + rx_tail; 4808 rx_tail = (rx_tail + 1) % 8; 4809 memset(rd, 0, 16); 4810 rd->buffer_addr = cpu_to_le64((u32) & packet); 4811 E1000_WRITE_REG(hw, RDT, rx_tail); 4812 } 4813 4814 /** 4815 * e1000_configure_tx - Configure 8254x Transmit Unit after Reset 4816 * @adapter: board private structure 4817 * 4818 * Configure the Tx unit of the MAC after a reset. 4819 **/ 4820 4821 static void 4822 e1000_configure_tx(struct e1000_hw *hw) 4823 { 4824 unsigned long ptr; 4825 unsigned long tctl; 4826 unsigned long tipg, tarc; 4827 uint32_t ipgr1, ipgr2; 4828 4829 ptr = (u32) tx_pool; 4830 if (ptr & 0xf) 4831 ptr = (ptr + 0x10) & (~0xf); 4832 4833 tx_base = (typeof(tx_base)) ptr; 4834 4835 E1000_WRITE_REG(hw, TDBAL, (u32) tx_base); 4836 E1000_WRITE_REG(hw, TDBAH, 0); 4837 4838 E1000_WRITE_REG(hw, TDLEN, 128); 4839 4840 /* Setup the HW Tx Head and Tail descriptor pointers */ 4841 E1000_WRITE_REG(hw, TDH, 0); 4842 E1000_WRITE_REG(hw, TDT, 0); 4843 tx_tail = 0; 4844 4845 /* Set the default values for the Tx Inter Packet Gap timer */ 4846 if (hw->mac_type <= e1000_82547_rev_2 && 4847 (hw->media_type == e1000_media_type_fiber || 4848 hw->media_type == e1000_media_type_internal_serdes)) 4849 tipg = DEFAULT_82543_TIPG_IPGT_FIBER; 4850 else 4851 tipg = DEFAULT_82543_TIPG_IPGT_COPPER; 4852 4853 /* Set the default values for the Tx Inter Packet Gap timer */ 4854 switch (hw->mac_type) { 4855 case e1000_82542_rev2_0: 4856 case e1000_82542_rev2_1: 4857 tipg = DEFAULT_82542_TIPG_IPGT; 4858 ipgr1 = DEFAULT_82542_TIPG_IPGR1; 4859 ipgr2 = DEFAULT_82542_TIPG_IPGR2; 4860 break; 4861 case e1000_80003es2lan: 4862 ipgr1 = DEFAULT_82543_TIPG_IPGR1; 4863 ipgr2 = DEFAULT_80003ES2LAN_TIPG_IPGR2; 4864 break; 4865 default: 4866 ipgr1 = DEFAULT_82543_TIPG_IPGR1; 4867 ipgr2 = DEFAULT_82543_TIPG_IPGR2; 4868 break; 4869 } 4870 tipg |= ipgr1 << E1000_TIPG_IPGR1_SHIFT; 4871 tipg |= ipgr2 << E1000_TIPG_IPGR2_SHIFT; 4872 E1000_WRITE_REG(hw, TIPG, tipg); 4873 /* Program the Transmit Control Register */ 4874 tctl = E1000_READ_REG(hw, TCTL); 4875 tctl &= ~E1000_TCTL_CT; 4876 tctl |= E1000_TCTL_EN | E1000_TCTL_PSP | 4877 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); 4878 4879 if (hw->mac_type == e1000_82571 || hw->mac_type == e1000_82572) { 4880 tarc = E1000_READ_REG(hw, TARC0); 4881 /* set the speed mode bit, we'll clear it if we're not at 4882 * gigabit link later */ 4883 /* git bit can be set to 1*/ 4884 } else if (hw->mac_type == e1000_80003es2lan) { 4885 tarc = E1000_READ_REG(hw, TARC0); 4886 tarc |= 1; 4887 E1000_WRITE_REG(hw, TARC0, tarc); 4888 tarc = E1000_READ_REG(hw, TARC1); 4889 tarc |= 1; 4890 E1000_WRITE_REG(hw, TARC1, tarc); 4891 } 4892 4893 4894 e1000_config_collision_dist(hw); 4895 /* Setup Transmit Descriptor Settings for eop descriptor */ 4896 hw->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS; 4897 4898 /* Need to set up RS bit */ 4899 if (hw->mac_type < e1000_82543) 4900 hw->txd_cmd |= E1000_TXD_CMD_RPS; 4901 else 4902 hw->txd_cmd |= E1000_TXD_CMD_RS; 4903 E1000_WRITE_REG(hw, TCTL, tctl); 4904 } 4905 4906 /** 4907 * e1000_setup_rctl - configure the receive control register 4908 * @adapter: Board private structure 4909 **/ 4910 static void 4911 e1000_setup_rctl(struct e1000_hw *hw) 4912 { 4913 uint32_t rctl; 4914 4915 rctl = E1000_READ_REG(hw, RCTL); 4916 4917 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 4918 4919 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO 4920 | E1000_RCTL_RDMTS_HALF; /* | 4921 (hw.mc_filter_type << E1000_RCTL_MO_SHIFT); */ 4922 4923 if (hw->tbi_compatibility_on == 1) 4924 rctl |= E1000_RCTL_SBP; 4925 else 4926 rctl &= ~E1000_RCTL_SBP; 4927 4928 rctl &= ~(E1000_RCTL_SZ_4096); 4929 rctl |= E1000_RCTL_SZ_2048; 4930 rctl &= ~(E1000_RCTL_BSEX | E1000_RCTL_LPE); 4931 E1000_WRITE_REG(hw, RCTL, rctl); 4932 } 4933 4934 /** 4935 * e1000_configure_rx - Configure 8254x Receive Unit after Reset 4936 * @adapter: board private structure 4937 * 4938 * Configure the Rx unit of the MAC after a reset. 4939 **/ 4940 static void 4941 e1000_configure_rx(struct e1000_hw *hw) 4942 { 4943 unsigned long ptr; 4944 unsigned long rctl, ctrl_ext; 4945 rx_tail = 0; 4946 /* make sure receives are disabled while setting up the descriptors */ 4947 rctl = E1000_READ_REG(hw, RCTL); 4948 E1000_WRITE_REG(hw, RCTL, rctl & ~E1000_RCTL_EN); 4949 if (hw->mac_type >= e1000_82540) { 4950 /* Set the interrupt throttling rate. Value is calculated 4951 * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns) */ 4952 #define MAX_INTS_PER_SEC 8000 4953 #define DEFAULT_ITR 1000000000/(MAX_INTS_PER_SEC * 256) 4954 E1000_WRITE_REG(hw, ITR, DEFAULT_ITR); 4955 } 4956 4957 if (hw->mac_type >= e1000_82571) { 4958 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 4959 /* Reset delay timers after every interrupt */ 4960 ctrl_ext |= E1000_CTRL_EXT_INT_TIMER_CLR; 4961 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 4962 E1000_WRITE_FLUSH(hw); 4963 } 4964 /* Setup the Base and Length of the Rx Descriptor Ring */ 4965 ptr = (u32) rx_pool; 4966 if (ptr & 0xf) 4967 ptr = (ptr + 0x10) & (~0xf); 4968 rx_base = (typeof(rx_base)) ptr; 4969 E1000_WRITE_REG(hw, RDBAL, (u32) rx_base); 4970 E1000_WRITE_REG(hw, RDBAH, 0); 4971 4972 E1000_WRITE_REG(hw, RDLEN, 128); 4973 4974 /* Setup the HW Rx Head and Tail Descriptor Pointers */ 4975 E1000_WRITE_REG(hw, RDH, 0); 4976 E1000_WRITE_REG(hw, RDT, 0); 4977 /* Enable Receives */ 4978 4979 E1000_WRITE_REG(hw, RCTL, rctl); 4980 fill_rx(hw); 4981 } 4982 4983 /************************************************************************** 4984 POLL - Wait for a frame 4985 ***************************************************************************/ 4986 static int 4987 e1000_poll(struct eth_device *nic) 4988 { 4989 struct e1000_hw *hw = nic->priv; 4990 struct e1000_rx_desc *rd; 4991 /* return true if there's an ethernet packet ready to read */ 4992 rd = rx_base + rx_last; 4993 if (!(le32_to_cpu(rd->status)) & E1000_RXD_STAT_DD) 4994 return 0; 4995 /*DEBUGOUT("recv: packet len=%d \n", rd->length); */ 4996 NetReceive((uchar *)packet, le32_to_cpu(rd->length)); 4997 fill_rx(hw); 4998 return 1; 4999 } 5000 5001 /************************************************************************** 5002 TRANSMIT - Transmit a frame 5003 ***************************************************************************/ 5004 static int e1000_transmit(struct eth_device *nic, void *packet, int length) 5005 { 5006 void *nv_packet = (void *)packet; 5007 struct e1000_hw *hw = nic->priv; 5008 struct e1000_tx_desc *txp; 5009 int i = 0; 5010 5011 txp = tx_base + tx_tail; 5012 tx_tail = (tx_tail + 1) % 8; 5013 5014 txp->buffer_addr = cpu_to_le64(virt_to_bus(hw->pdev, nv_packet)); 5015 txp->lower.data = cpu_to_le32(hw->txd_cmd | length); 5016 txp->upper.data = 0; 5017 E1000_WRITE_REG(hw, TDT, tx_tail); 5018 5019 E1000_WRITE_FLUSH(hw); 5020 while (!(le32_to_cpu(txp->upper.data) & E1000_TXD_STAT_DD)) { 5021 if (i++ > TOUT_LOOP) { 5022 DEBUGOUT("e1000: tx timeout\n"); 5023 return 0; 5024 } 5025 udelay(10); /* give the nic a chance to write to the register */ 5026 } 5027 return 1; 5028 } 5029 5030 /*reset function*/ 5031 static inline int 5032 e1000_reset(struct eth_device *nic) 5033 { 5034 struct e1000_hw *hw = nic->priv; 5035 5036 e1000_reset_hw(hw); 5037 if (hw->mac_type >= e1000_82544) { 5038 E1000_WRITE_REG(hw, WUC, 0); 5039 } 5040 return e1000_init_hw(nic); 5041 } 5042 5043 /************************************************************************** 5044 DISABLE - Turn off ethernet interface 5045 ***************************************************************************/ 5046 static void 5047 e1000_disable(struct eth_device *nic) 5048 { 5049 struct e1000_hw *hw = nic->priv; 5050 5051 /* Turn off the ethernet interface */ 5052 E1000_WRITE_REG(hw, RCTL, 0); 5053 E1000_WRITE_REG(hw, TCTL, 0); 5054 5055 /* Clear the transmit ring */ 5056 E1000_WRITE_REG(hw, TDH, 0); 5057 E1000_WRITE_REG(hw, TDT, 0); 5058 5059 /* Clear the receive ring */ 5060 E1000_WRITE_REG(hw, RDH, 0); 5061 E1000_WRITE_REG(hw, RDT, 0); 5062 5063 /* put the card in its initial state */ 5064 #if 0 5065 E1000_WRITE_REG(hw, CTRL, E1000_CTRL_RST); 5066 #endif 5067 mdelay(10); 5068 5069 } 5070 5071 /************************************************************************** 5072 INIT - set up ethernet interface(s) 5073 ***************************************************************************/ 5074 static int 5075 e1000_init(struct eth_device *nic, bd_t * bis) 5076 { 5077 struct e1000_hw *hw = nic->priv; 5078 int ret_val = 0; 5079 5080 ret_val = e1000_reset(nic); 5081 if (ret_val < 0) { 5082 if ((ret_val == -E1000_ERR_NOLINK) || 5083 (ret_val == -E1000_ERR_TIMEOUT)) { 5084 E1000_ERR(hw->nic, "Valid Link not detected\n"); 5085 } else { 5086 E1000_ERR(hw->nic, "Hardware Initialization Failed\n"); 5087 } 5088 return 0; 5089 } 5090 e1000_configure_tx(hw); 5091 e1000_setup_rctl(hw); 5092 e1000_configure_rx(hw); 5093 return 1; 5094 } 5095 5096 /****************************************************************************** 5097 * Gets the current PCI bus type of hardware 5098 * 5099 * hw - Struct containing variables accessed by shared code 5100 *****************************************************************************/ 5101 void e1000_get_bus_type(struct e1000_hw *hw) 5102 { 5103 uint32_t status; 5104 5105 switch (hw->mac_type) { 5106 case e1000_82542_rev2_0: 5107 case e1000_82542_rev2_1: 5108 hw->bus_type = e1000_bus_type_pci; 5109 break; 5110 case e1000_82571: 5111 case e1000_82572: 5112 case e1000_82573: 5113 case e1000_82574: 5114 case e1000_80003es2lan: 5115 hw->bus_type = e1000_bus_type_pci_express; 5116 break; 5117 case e1000_ich8lan: 5118 hw->bus_type = e1000_bus_type_pci_express; 5119 break; 5120 default: 5121 status = E1000_READ_REG(hw, STATUS); 5122 hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ? 5123 e1000_bus_type_pcix : e1000_bus_type_pci; 5124 break; 5125 } 5126 } 5127 5128 /* A list of all registered e1000 devices */ 5129 static LIST_HEAD(e1000_hw_list); 5130 5131 /************************************************************************** 5132 PROBE - Look for an adapter, this routine's visible to the outside 5133 You should omit the last argument struct pci_device * for a non-PCI NIC 5134 ***************************************************************************/ 5135 int 5136 e1000_initialize(bd_t * bis) 5137 { 5138 unsigned int i; 5139 pci_dev_t devno; 5140 5141 DEBUGFUNC(); 5142 5143 /* Find and probe all the matching PCI devices */ 5144 for (i = 0; (devno = pci_find_devices(e1000_supported, i)) >= 0; i++) { 5145 u32 val; 5146 5147 /* 5148 * These will never get freed due to errors, this allows us to 5149 * perform SPI EEPROM programming from U-boot, for example. 5150 */ 5151 struct eth_device *nic = malloc(sizeof(*nic)); 5152 struct e1000_hw *hw = malloc(sizeof(*hw)); 5153 if (!nic || !hw) { 5154 printf("e1000#%u: Out of Memory!\n", i); 5155 free(nic); 5156 free(hw); 5157 continue; 5158 } 5159 5160 /* Make sure all of the fields are initially zeroed */ 5161 memset(nic, 0, sizeof(*nic)); 5162 memset(hw, 0, sizeof(*hw)); 5163 5164 /* Assign the passed-in values */ 5165 hw->cardnum = i; 5166 hw->pdev = devno; 5167 hw->nic = nic; 5168 nic->priv = hw; 5169 5170 /* Generate a card name */ 5171 sprintf(nic->name, "e1000#%u", hw->cardnum); 5172 5173 /* Print a debug message with the IO base address */ 5174 pci_read_config_dword(devno, PCI_BASE_ADDRESS_0, &val); 5175 E1000_DBG(nic, "iobase 0x%08x\n", val & 0xfffffff0); 5176 5177 /* Try to enable I/O accesses and bus-mastering */ 5178 val = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; 5179 pci_write_config_dword(devno, PCI_COMMAND, val); 5180 5181 /* Make sure it worked */ 5182 pci_read_config_dword(devno, PCI_COMMAND, &val); 5183 if (!(val & PCI_COMMAND_MEMORY)) { 5184 E1000_ERR(nic, "Can't enable I/O memory\n"); 5185 continue; 5186 } 5187 if (!(val & PCI_COMMAND_MASTER)) { 5188 E1000_ERR(nic, "Can't enable bus-mastering\n"); 5189 continue; 5190 } 5191 5192 /* Are these variables needed? */ 5193 hw->fc = e1000_fc_default; 5194 hw->original_fc = e1000_fc_default; 5195 hw->autoneg_failed = 0; 5196 hw->autoneg = 1; 5197 hw->get_link_status = TRUE; 5198 hw->hw_addr = pci_map_bar(devno, PCI_BASE_ADDRESS_0, 5199 PCI_REGION_MEM); 5200 hw->mac_type = e1000_undefined; 5201 5202 /* MAC and Phy settings */ 5203 if (e1000_sw_init(nic) < 0) { 5204 E1000_ERR(nic, "Software init failed\n"); 5205 continue; 5206 } 5207 if (e1000_check_phy_reset_block(hw)) 5208 E1000_ERR(nic, "PHY Reset is blocked!\n"); 5209 5210 /* Basic init was OK, reset the hardware and allow SPI access */ 5211 e1000_reset_hw(hw); 5212 list_add_tail(&hw->list_node, &e1000_hw_list); 5213 5214 /* Validate the EEPROM and get chipset information */ 5215 #if !defined(CONFIG_MVBC_1G) 5216 if (e1000_init_eeprom_params(hw)) { 5217 E1000_ERR(nic, "EEPROM is invalid!\n"); 5218 continue; 5219 } 5220 if (e1000_validate_eeprom_checksum(hw)) 5221 continue; 5222 #endif 5223 e1000_read_mac_addr(nic); 5224 e1000_get_bus_type(hw); 5225 5226 printf("e1000: %02x:%02x:%02x:%02x:%02x:%02x\n ", 5227 nic->enetaddr[0], nic->enetaddr[1], nic->enetaddr[2], 5228 nic->enetaddr[3], nic->enetaddr[4], nic->enetaddr[5]); 5229 5230 /* Set up the function pointers and register the device */ 5231 nic->init = e1000_init; 5232 nic->recv = e1000_poll; 5233 nic->send = e1000_transmit; 5234 nic->halt = e1000_disable; 5235 eth_register(nic); 5236 } 5237 5238 return i; 5239 } 5240 5241 struct e1000_hw *e1000_find_card(unsigned int cardnum) 5242 { 5243 struct e1000_hw *hw; 5244 5245 list_for_each_entry(hw, &e1000_hw_list, list_node) 5246 if (hw->cardnum == cardnum) 5247 return hw; 5248 5249 return NULL; 5250 } 5251 5252 #ifdef CONFIG_CMD_E1000 5253 static int do_e1000(cmd_tbl_t *cmdtp, int flag, 5254 int argc, char * const argv[]) 5255 { 5256 struct e1000_hw *hw; 5257 5258 if (argc < 3) { 5259 cmd_usage(cmdtp); 5260 return 1; 5261 } 5262 5263 /* Make sure we can find the requested e1000 card */ 5264 hw = e1000_find_card(simple_strtoul(argv[1], NULL, 10)); 5265 if (!hw) { 5266 printf("e1000: ERROR: No such device: e1000#%s\n", argv[1]); 5267 return 1; 5268 } 5269 5270 if (!strcmp(argv[2], "print-mac-address")) { 5271 unsigned char *mac = hw->nic->enetaddr; 5272 printf("%02x:%02x:%02x:%02x:%02x:%02x\n", 5273 mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]); 5274 return 0; 5275 } 5276 5277 #ifdef CONFIG_E1000_SPI 5278 /* Handle the "SPI" subcommand */ 5279 if (!strcmp(argv[2], "spi")) 5280 return do_e1000_spi(cmdtp, hw, argc - 3, argv + 3); 5281 #endif 5282 5283 cmd_usage(cmdtp); 5284 return 1; 5285 } 5286 5287 U_BOOT_CMD( 5288 e1000, 7, 0, do_e1000, 5289 "Intel e1000 controller management", 5290 /* */"<card#> print-mac-address\n" 5291 #ifdef CONFIG_E1000_SPI 5292 "e1000 <card#> spi show [<offset> [<length>]]\n" 5293 "e1000 <card#> spi dump <addr> <offset> <length>\n" 5294 "e1000 <card#> spi program <addr> <offset> <length>\n" 5295 "e1000 <card#> spi checksum [update]\n" 5296 #endif 5297 " - Manage the Intel E1000 PCI device" 5298 ); 5299 #endif /* not CONFIG_CMD_E1000 */ 5300