1 /************************************************************************** 2 Intel Pro 1000 for ppcboot/das-u-boot 3 Drivers are port from Intel's Linux driver e1000-4.3.15 4 and from Etherboot pro 1000 driver by mrakes at vivato dot net 5 tested on both gig copper and gig fiber boards 6 ***************************************************************************/ 7 /******************************************************************************* 8 9 10 Copyright(c) 1999 - 2002 Intel Corporation. All rights reserved. 11 12 * SPDX-License-Identifier: GPL-2.0+ 13 14 Contact Information: 15 Linux NICS <linux.nics@intel.com> 16 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 17 18 *******************************************************************************/ 19 /* 20 * Copyright (C) Archway Digital Solutions. 21 * 22 * written by Chrsitopher Li <cli at arcyway dot com> or <chrisl at gnuchina dot org> 23 * 2/9/2002 24 * 25 * Copyright (C) Linux Networx. 26 * Massive upgrade to work with the new intel gigabit NICs. 27 * <ebiederman at lnxi dot com> 28 * 29 * Copyright 2011 Freescale Semiconductor, Inc. 30 */ 31 32 #include <common.h> 33 #include <dm.h> 34 #include <errno.h> 35 #include <pci.h> 36 #include "e1000.h" 37 38 #define TOUT_LOOP 100000 39 40 #define virt_to_bus(devno, v) pci_virt_to_mem(devno, (void *) (v)) 41 #define bus_to_phys(devno, a) pci_mem_to_phys(devno, a) 42 43 #define E1000_DEFAULT_PCI_PBA 0x00000030 44 #define E1000_DEFAULT_PCIE_PBA 0x000a0026 45 46 /* NIC specific static variables go here */ 47 48 /* Intel i210 needs the DMA descriptor rings aligned to 128b */ 49 #define E1000_BUFFER_ALIGN 128 50 51 /* 52 * TODO(sjg@chromium.org): Even with driver model we share these buffers. 53 * Concurrent receiving on multiple active Ethernet devices will not work. 54 * Normally U-Boot does not support this anyway. To fix it in this driver, 55 * move these buffers and the tx/rx pointers to struct e1000_hw. 56 */ 57 DEFINE_ALIGN_BUFFER(struct e1000_tx_desc, tx_base, 16, E1000_BUFFER_ALIGN); 58 DEFINE_ALIGN_BUFFER(struct e1000_rx_desc, rx_base, 16, E1000_BUFFER_ALIGN); 59 DEFINE_ALIGN_BUFFER(unsigned char, packet, 4096, E1000_BUFFER_ALIGN); 60 61 static int tx_tail; 62 static int rx_tail, rx_last; 63 #ifdef CONFIG_DM_ETH 64 static int num_cards; /* Number of E1000 devices seen so far */ 65 #endif 66 67 static struct pci_device_id e1000_supported[] = { 68 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82542) }, 69 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82543GC_FIBER) }, 70 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82543GC_COPPER) }, 71 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544EI_COPPER) }, 72 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544EI_FIBER) }, 73 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544GC_COPPER) }, 74 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544GC_LOM) }, 75 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82540EM) }, 76 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545EM_COPPER) }, 77 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545GM_COPPER) }, 78 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_COPPER) }, 79 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545EM_FIBER) }, 80 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_FIBER) }, 81 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546GB_COPPER) }, 82 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82540EM_LOM) }, 83 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82541ER) }, 84 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82541GI_LF) }, 85 /* E1000 PCIe card */ 86 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_COPPER) }, 87 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_FIBER) }, 88 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES) }, 89 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_COPPER) }, 90 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571PT_QUAD_COPPER) }, 91 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_FIBER) }, 92 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_COPPER_LOWPROFILE) }, 93 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES_DUAL) }, 94 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES_QUAD) }, 95 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_COPPER) }, 96 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_FIBER) }, 97 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_SERDES) }, 98 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI) }, 99 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573E) }, 100 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573E_IAMT) }, 101 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573L) }, 102 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82574L) }, 103 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546GB_QUAD_COPPER_KSP3) }, 104 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_COPPER_DPT) }, 105 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_SERDES_DPT) }, 106 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_COPPER_SPT) }, 107 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_SERDES_SPT) }, 108 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_UNPROGRAMMED) }, 109 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I211_UNPROGRAMMED) }, 110 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_COPPER) }, 111 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I211_COPPER) }, 112 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_COPPER_FLASHLESS) }, 113 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_SERDES) }, 114 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_SERDES_FLASHLESS) }, 115 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_1000BASEKX) }, 116 117 {} 118 }; 119 120 /* Function forward declarations */ 121 static int e1000_setup_link(struct e1000_hw *hw); 122 static int e1000_setup_fiber_link(struct e1000_hw *hw); 123 static int e1000_setup_copper_link(struct e1000_hw *hw); 124 static int e1000_phy_setup_autoneg(struct e1000_hw *hw); 125 static void e1000_config_collision_dist(struct e1000_hw *hw); 126 static int e1000_config_mac_to_phy(struct e1000_hw *hw); 127 static int e1000_config_fc_after_link_up(struct e1000_hw *hw); 128 static int e1000_check_for_link(struct e1000_hw *hw); 129 static int e1000_wait_autoneg(struct e1000_hw *hw); 130 static int e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t * speed, 131 uint16_t * duplex); 132 static int e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, 133 uint16_t * phy_data); 134 static int e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, 135 uint16_t phy_data); 136 static int32_t e1000_phy_hw_reset(struct e1000_hw *hw); 137 static int e1000_phy_reset(struct e1000_hw *hw); 138 static int e1000_detect_gig_phy(struct e1000_hw *hw); 139 static void e1000_set_media_type(struct e1000_hw *hw); 140 141 static int32_t e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask); 142 static void e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask); 143 static int32_t e1000_check_phy_reset_block(struct e1000_hw *hw); 144 145 #ifndef CONFIG_E1000_NO_NVM 146 static void e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw); 147 static int32_t e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset, 148 uint16_t words, 149 uint16_t *data); 150 /****************************************************************************** 151 * Raises the EEPROM's clock input. 152 * 153 * hw - Struct containing variables accessed by shared code 154 * eecd - EECD's current value 155 *****************************************************************************/ 156 void e1000_raise_ee_clk(struct e1000_hw *hw, uint32_t * eecd) 157 { 158 /* Raise the clock input to the EEPROM (by setting the SK bit), and then 159 * wait 50 microseconds. 160 */ 161 *eecd = *eecd | E1000_EECD_SK; 162 E1000_WRITE_REG(hw, EECD, *eecd); 163 E1000_WRITE_FLUSH(hw); 164 udelay(50); 165 } 166 167 /****************************************************************************** 168 * Lowers the EEPROM's clock input. 169 * 170 * hw - Struct containing variables accessed by shared code 171 * eecd - EECD's current value 172 *****************************************************************************/ 173 void e1000_lower_ee_clk(struct e1000_hw *hw, uint32_t * eecd) 174 { 175 /* Lower the clock input to the EEPROM (by clearing the SK bit), and then 176 * wait 50 microseconds. 177 */ 178 *eecd = *eecd & ~E1000_EECD_SK; 179 E1000_WRITE_REG(hw, EECD, *eecd); 180 E1000_WRITE_FLUSH(hw); 181 udelay(50); 182 } 183 184 /****************************************************************************** 185 * Shift data bits out to the EEPROM. 186 * 187 * hw - Struct containing variables accessed by shared code 188 * data - data to send to the EEPROM 189 * count - number of bits to shift out 190 *****************************************************************************/ 191 static void 192 e1000_shift_out_ee_bits(struct e1000_hw *hw, uint16_t data, uint16_t count) 193 { 194 uint32_t eecd; 195 uint32_t mask; 196 197 /* We need to shift "count" bits out to the EEPROM. So, value in the 198 * "data" parameter will be shifted out to the EEPROM one bit at a time. 199 * In order to do this, "data" must be broken down into bits. 200 */ 201 mask = 0x01 << (count - 1); 202 eecd = E1000_READ_REG(hw, EECD); 203 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI); 204 do { 205 /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1", 206 * and then raising and then lowering the clock (the SK bit controls 207 * the clock input to the EEPROM). A "0" is shifted out to the EEPROM 208 * by setting "DI" to "0" and then raising and then lowering the clock. 209 */ 210 eecd &= ~E1000_EECD_DI; 211 212 if (data & mask) 213 eecd |= E1000_EECD_DI; 214 215 E1000_WRITE_REG(hw, EECD, eecd); 216 E1000_WRITE_FLUSH(hw); 217 218 udelay(50); 219 220 e1000_raise_ee_clk(hw, &eecd); 221 e1000_lower_ee_clk(hw, &eecd); 222 223 mask = mask >> 1; 224 225 } while (mask); 226 227 /* We leave the "DI" bit set to "0" when we leave this routine. */ 228 eecd &= ~E1000_EECD_DI; 229 E1000_WRITE_REG(hw, EECD, eecd); 230 } 231 232 /****************************************************************************** 233 * Shift data bits in from the EEPROM 234 * 235 * hw - Struct containing variables accessed by shared code 236 *****************************************************************************/ 237 static uint16_t 238 e1000_shift_in_ee_bits(struct e1000_hw *hw, uint16_t count) 239 { 240 uint32_t eecd; 241 uint32_t i; 242 uint16_t data; 243 244 /* In order to read a register from the EEPROM, we need to shift 'count' 245 * bits in from the EEPROM. Bits are "shifted in" by raising the clock 246 * input to the EEPROM (setting the SK bit), and then reading the 247 * value of the "DO" bit. During this "shifting in" process the 248 * "DI" bit should always be clear. 249 */ 250 251 eecd = E1000_READ_REG(hw, EECD); 252 253 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI); 254 data = 0; 255 256 for (i = 0; i < count; i++) { 257 data = data << 1; 258 e1000_raise_ee_clk(hw, &eecd); 259 260 eecd = E1000_READ_REG(hw, EECD); 261 262 eecd &= ~(E1000_EECD_DI); 263 if (eecd & E1000_EECD_DO) 264 data |= 1; 265 266 e1000_lower_ee_clk(hw, &eecd); 267 } 268 269 return data; 270 } 271 272 /****************************************************************************** 273 * Returns EEPROM to a "standby" state 274 * 275 * hw - Struct containing variables accessed by shared code 276 *****************************************************************************/ 277 void e1000_standby_eeprom(struct e1000_hw *hw) 278 { 279 struct e1000_eeprom_info *eeprom = &hw->eeprom; 280 uint32_t eecd; 281 282 eecd = E1000_READ_REG(hw, EECD); 283 284 if (eeprom->type == e1000_eeprom_microwire) { 285 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); 286 E1000_WRITE_REG(hw, EECD, eecd); 287 E1000_WRITE_FLUSH(hw); 288 udelay(eeprom->delay_usec); 289 290 /* Clock high */ 291 eecd |= E1000_EECD_SK; 292 E1000_WRITE_REG(hw, EECD, eecd); 293 E1000_WRITE_FLUSH(hw); 294 udelay(eeprom->delay_usec); 295 296 /* Select EEPROM */ 297 eecd |= E1000_EECD_CS; 298 E1000_WRITE_REG(hw, EECD, eecd); 299 E1000_WRITE_FLUSH(hw); 300 udelay(eeprom->delay_usec); 301 302 /* Clock low */ 303 eecd &= ~E1000_EECD_SK; 304 E1000_WRITE_REG(hw, EECD, eecd); 305 E1000_WRITE_FLUSH(hw); 306 udelay(eeprom->delay_usec); 307 } else if (eeprom->type == e1000_eeprom_spi) { 308 /* Toggle CS to flush commands */ 309 eecd |= E1000_EECD_CS; 310 E1000_WRITE_REG(hw, EECD, eecd); 311 E1000_WRITE_FLUSH(hw); 312 udelay(eeprom->delay_usec); 313 eecd &= ~E1000_EECD_CS; 314 E1000_WRITE_REG(hw, EECD, eecd); 315 E1000_WRITE_FLUSH(hw); 316 udelay(eeprom->delay_usec); 317 } 318 } 319 320 /*************************************************************************** 321 * Description: Determines if the onboard NVM is FLASH or EEPROM. 322 * 323 * hw - Struct containing variables accessed by shared code 324 ****************************************************************************/ 325 static bool e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw) 326 { 327 uint32_t eecd = 0; 328 329 DEBUGFUNC(); 330 331 if (hw->mac_type == e1000_ich8lan) 332 return false; 333 334 if (hw->mac_type == e1000_82573 || hw->mac_type == e1000_82574) { 335 eecd = E1000_READ_REG(hw, EECD); 336 337 /* Isolate bits 15 & 16 */ 338 eecd = ((eecd >> 15) & 0x03); 339 340 /* If both bits are set, device is Flash type */ 341 if (eecd == 0x03) 342 return false; 343 } 344 return true; 345 } 346 347 /****************************************************************************** 348 * Prepares EEPROM for access 349 * 350 * hw - Struct containing variables accessed by shared code 351 * 352 * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This 353 * function should be called before issuing a command to the EEPROM. 354 *****************************************************************************/ 355 int32_t e1000_acquire_eeprom(struct e1000_hw *hw) 356 { 357 struct e1000_eeprom_info *eeprom = &hw->eeprom; 358 uint32_t eecd, i = 0; 359 360 DEBUGFUNC(); 361 362 if (e1000_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM)) 363 return -E1000_ERR_SWFW_SYNC; 364 eecd = E1000_READ_REG(hw, EECD); 365 366 if (hw->mac_type != e1000_82573 && hw->mac_type != e1000_82574) { 367 /* Request EEPROM Access */ 368 if (hw->mac_type > e1000_82544) { 369 eecd |= E1000_EECD_REQ; 370 E1000_WRITE_REG(hw, EECD, eecd); 371 eecd = E1000_READ_REG(hw, EECD); 372 while ((!(eecd & E1000_EECD_GNT)) && 373 (i < E1000_EEPROM_GRANT_ATTEMPTS)) { 374 i++; 375 udelay(5); 376 eecd = E1000_READ_REG(hw, EECD); 377 } 378 if (!(eecd & E1000_EECD_GNT)) { 379 eecd &= ~E1000_EECD_REQ; 380 E1000_WRITE_REG(hw, EECD, eecd); 381 DEBUGOUT("Could not acquire EEPROM grant\n"); 382 return -E1000_ERR_EEPROM; 383 } 384 } 385 } 386 387 /* Setup EEPROM for Read/Write */ 388 389 if (eeprom->type == e1000_eeprom_microwire) { 390 /* Clear SK and DI */ 391 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK); 392 E1000_WRITE_REG(hw, EECD, eecd); 393 394 /* Set CS */ 395 eecd |= E1000_EECD_CS; 396 E1000_WRITE_REG(hw, EECD, eecd); 397 } else if (eeprom->type == e1000_eeprom_spi) { 398 /* Clear SK and CS */ 399 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); 400 E1000_WRITE_REG(hw, EECD, eecd); 401 udelay(1); 402 } 403 404 return E1000_SUCCESS; 405 } 406 407 /****************************************************************************** 408 * Sets up eeprom variables in the hw struct. Must be called after mac_type 409 * is configured. Additionally, if this is ICH8, the flash controller GbE 410 * registers must be mapped, or this will crash. 411 * 412 * hw - Struct containing variables accessed by shared code 413 *****************************************************************************/ 414 static int32_t e1000_init_eeprom_params(struct e1000_hw *hw) 415 { 416 struct e1000_eeprom_info *eeprom = &hw->eeprom; 417 uint32_t eecd; 418 int32_t ret_val = E1000_SUCCESS; 419 uint16_t eeprom_size; 420 421 if (hw->mac_type == e1000_igb) 422 eecd = E1000_READ_REG(hw, I210_EECD); 423 else 424 eecd = E1000_READ_REG(hw, EECD); 425 426 DEBUGFUNC(); 427 428 switch (hw->mac_type) { 429 case e1000_82542_rev2_0: 430 case e1000_82542_rev2_1: 431 case e1000_82543: 432 case e1000_82544: 433 eeprom->type = e1000_eeprom_microwire; 434 eeprom->word_size = 64; 435 eeprom->opcode_bits = 3; 436 eeprom->address_bits = 6; 437 eeprom->delay_usec = 50; 438 eeprom->use_eerd = false; 439 eeprom->use_eewr = false; 440 break; 441 case e1000_82540: 442 case e1000_82545: 443 case e1000_82545_rev_3: 444 case e1000_82546: 445 case e1000_82546_rev_3: 446 eeprom->type = e1000_eeprom_microwire; 447 eeprom->opcode_bits = 3; 448 eeprom->delay_usec = 50; 449 if (eecd & E1000_EECD_SIZE) { 450 eeprom->word_size = 256; 451 eeprom->address_bits = 8; 452 } else { 453 eeprom->word_size = 64; 454 eeprom->address_bits = 6; 455 } 456 eeprom->use_eerd = false; 457 eeprom->use_eewr = false; 458 break; 459 case e1000_82541: 460 case e1000_82541_rev_2: 461 case e1000_82547: 462 case e1000_82547_rev_2: 463 if (eecd & E1000_EECD_TYPE) { 464 eeprom->type = e1000_eeprom_spi; 465 eeprom->opcode_bits = 8; 466 eeprom->delay_usec = 1; 467 if (eecd & E1000_EECD_ADDR_BITS) { 468 eeprom->page_size = 32; 469 eeprom->address_bits = 16; 470 } else { 471 eeprom->page_size = 8; 472 eeprom->address_bits = 8; 473 } 474 } else { 475 eeprom->type = e1000_eeprom_microwire; 476 eeprom->opcode_bits = 3; 477 eeprom->delay_usec = 50; 478 if (eecd & E1000_EECD_ADDR_BITS) { 479 eeprom->word_size = 256; 480 eeprom->address_bits = 8; 481 } else { 482 eeprom->word_size = 64; 483 eeprom->address_bits = 6; 484 } 485 } 486 eeprom->use_eerd = false; 487 eeprom->use_eewr = false; 488 break; 489 case e1000_82571: 490 case e1000_82572: 491 eeprom->type = e1000_eeprom_spi; 492 eeprom->opcode_bits = 8; 493 eeprom->delay_usec = 1; 494 if (eecd & E1000_EECD_ADDR_BITS) { 495 eeprom->page_size = 32; 496 eeprom->address_bits = 16; 497 } else { 498 eeprom->page_size = 8; 499 eeprom->address_bits = 8; 500 } 501 eeprom->use_eerd = false; 502 eeprom->use_eewr = false; 503 break; 504 case e1000_82573: 505 case e1000_82574: 506 eeprom->type = e1000_eeprom_spi; 507 eeprom->opcode_bits = 8; 508 eeprom->delay_usec = 1; 509 if (eecd & E1000_EECD_ADDR_BITS) { 510 eeprom->page_size = 32; 511 eeprom->address_bits = 16; 512 } else { 513 eeprom->page_size = 8; 514 eeprom->address_bits = 8; 515 } 516 if (e1000_is_onboard_nvm_eeprom(hw) == false) { 517 eeprom->use_eerd = true; 518 eeprom->use_eewr = true; 519 520 eeprom->type = e1000_eeprom_flash; 521 eeprom->word_size = 2048; 522 523 /* Ensure that the Autonomous FLASH update bit is cleared due to 524 * Flash update issue on parts which use a FLASH for NVM. */ 525 eecd &= ~E1000_EECD_AUPDEN; 526 E1000_WRITE_REG(hw, EECD, eecd); 527 } 528 break; 529 case e1000_80003es2lan: 530 eeprom->type = e1000_eeprom_spi; 531 eeprom->opcode_bits = 8; 532 eeprom->delay_usec = 1; 533 if (eecd & E1000_EECD_ADDR_BITS) { 534 eeprom->page_size = 32; 535 eeprom->address_bits = 16; 536 } else { 537 eeprom->page_size = 8; 538 eeprom->address_bits = 8; 539 } 540 eeprom->use_eerd = true; 541 eeprom->use_eewr = false; 542 break; 543 case e1000_igb: 544 /* i210 has 4k of iNVM mapped as EEPROM */ 545 eeprom->type = e1000_eeprom_invm; 546 eeprom->opcode_bits = 8; 547 eeprom->delay_usec = 1; 548 eeprom->page_size = 32; 549 eeprom->address_bits = 16; 550 eeprom->use_eerd = true; 551 eeprom->use_eewr = false; 552 break; 553 554 /* ich8lan does not support currently. if needed, please 555 * add corresponding code and functions. 556 */ 557 #if 0 558 case e1000_ich8lan: 559 { 560 int32_t i = 0; 561 562 eeprom->type = e1000_eeprom_ich8; 563 eeprom->use_eerd = false; 564 eeprom->use_eewr = false; 565 eeprom->word_size = E1000_SHADOW_RAM_WORDS; 566 uint32_t flash_size = E1000_READ_ICH_FLASH_REG(hw, 567 ICH_FLASH_GFPREG); 568 /* Zero the shadow RAM structure. But don't load it from NVM 569 * so as to save time for driver init */ 570 if (hw->eeprom_shadow_ram != NULL) { 571 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) { 572 hw->eeprom_shadow_ram[i].modified = false; 573 hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF; 574 } 575 } 576 577 hw->flash_base_addr = (flash_size & ICH_GFPREG_BASE_MASK) * 578 ICH_FLASH_SECTOR_SIZE; 579 580 hw->flash_bank_size = ((flash_size >> 16) 581 & ICH_GFPREG_BASE_MASK) + 1; 582 hw->flash_bank_size -= (flash_size & ICH_GFPREG_BASE_MASK); 583 584 hw->flash_bank_size *= ICH_FLASH_SECTOR_SIZE; 585 586 hw->flash_bank_size /= 2 * sizeof(uint16_t); 587 break; 588 } 589 #endif 590 default: 591 break; 592 } 593 594 if (eeprom->type == e1000_eeprom_spi || 595 eeprom->type == e1000_eeprom_invm) { 596 /* eeprom_size will be an enum [0..8] that maps 597 * to eeprom sizes 128B to 598 * 32KB (incremented by powers of 2). 599 */ 600 if (hw->mac_type <= e1000_82547_rev_2) { 601 /* Set to default value for initial eeprom read. */ 602 eeprom->word_size = 64; 603 ret_val = e1000_read_eeprom(hw, EEPROM_CFG, 1, 604 &eeprom_size); 605 if (ret_val) 606 return ret_val; 607 eeprom_size = (eeprom_size & EEPROM_SIZE_MASK) 608 >> EEPROM_SIZE_SHIFT; 609 /* 256B eeprom size was not supported in earlier 610 * hardware, so we bump eeprom_size up one to 611 * ensure that "1" (which maps to 256B) is never 612 * the result used in the shifting logic below. */ 613 if (eeprom_size) 614 eeprom_size++; 615 } else { 616 eeprom_size = (uint16_t)((eecd & 617 E1000_EECD_SIZE_EX_MASK) >> 618 E1000_EECD_SIZE_EX_SHIFT); 619 } 620 621 eeprom->word_size = 1 << (eeprom_size + EEPROM_WORD_SIZE_SHIFT); 622 } 623 return ret_val; 624 } 625 626 /****************************************************************************** 627 * Polls the status bit (bit 1) of the EERD to determine when the read is done. 628 * 629 * hw - Struct containing variables accessed by shared code 630 *****************************************************************************/ 631 static int32_t 632 e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd) 633 { 634 uint32_t attempts = 100000; 635 uint32_t i, reg = 0; 636 int32_t done = E1000_ERR_EEPROM; 637 638 for (i = 0; i < attempts; i++) { 639 if (eerd == E1000_EEPROM_POLL_READ) { 640 if (hw->mac_type == e1000_igb) 641 reg = E1000_READ_REG(hw, I210_EERD); 642 else 643 reg = E1000_READ_REG(hw, EERD); 644 } else { 645 if (hw->mac_type == e1000_igb) 646 reg = E1000_READ_REG(hw, I210_EEWR); 647 else 648 reg = E1000_READ_REG(hw, EEWR); 649 } 650 651 if (reg & E1000_EEPROM_RW_REG_DONE) { 652 done = E1000_SUCCESS; 653 break; 654 } 655 udelay(5); 656 } 657 658 return done; 659 } 660 661 /****************************************************************************** 662 * Reads a 16 bit word from the EEPROM using the EERD register. 663 * 664 * hw - Struct containing variables accessed by shared code 665 * offset - offset of word in the EEPROM to read 666 * data - word read from the EEPROM 667 * words - number of words to read 668 *****************************************************************************/ 669 static int32_t 670 e1000_read_eeprom_eerd(struct e1000_hw *hw, 671 uint16_t offset, 672 uint16_t words, 673 uint16_t *data) 674 { 675 uint32_t i, eerd = 0; 676 int32_t error = 0; 677 678 for (i = 0; i < words; i++) { 679 eerd = ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) + 680 E1000_EEPROM_RW_REG_START; 681 682 if (hw->mac_type == e1000_igb) 683 E1000_WRITE_REG(hw, I210_EERD, eerd); 684 else 685 E1000_WRITE_REG(hw, EERD, eerd); 686 687 error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_READ); 688 689 if (error) 690 break; 691 692 if (hw->mac_type == e1000_igb) { 693 data[i] = (E1000_READ_REG(hw, I210_EERD) >> 694 E1000_EEPROM_RW_REG_DATA); 695 } else { 696 data[i] = (E1000_READ_REG(hw, EERD) >> 697 E1000_EEPROM_RW_REG_DATA); 698 } 699 700 } 701 702 return error; 703 } 704 705 void e1000_release_eeprom(struct e1000_hw *hw) 706 { 707 uint32_t eecd; 708 709 DEBUGFUNC(); 710 711 eecd = E1000_READ_REG(hw, EECD); 712 713 if (hw->eeprom.type == e1000_eeprom_spi) { 714 eecd |= E1000_EECD_CS; /* Pull CS high */ 715 eecd &= ~E1000_EECD_SK; /* Lower SCK */ 716 717 E1000_WRITE_REG(hw, EECD, eecd); 718 719 udelay(hw->eeprom.delay_usec); 720 } else if (hw->eeprom.type == e1000_eeprom_microwire) { 721 /* cleanup eeprom */ 722 723 /* CS on Microwire is active-high */ 724 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI); 725 726 E1000_WRITE_REG(hw, EECD, eecd); 727 728 /* Rising edge of clock */ 729 eecd |= E1000_EECD_SK; 730 E1000_WRITE_REG(hw, EECD, eecd); 731 E1000_WRITE_FLUSH(hw); 732 udelay(hw->eeprom.delay_usec); 733 734 /* Falling edge of clock */ 735 eecd &= ~E1000_EECD_SK; 736 E1000_WRITE_REG(hw, EECD, eecd); 737 E1000_WRITE_FLUSH(hw); 738 udelay(hw->eeprom.delay_usec); 739 } 740 741 /* Stop requesting EEPROM access */ 742 if (hw->mac_type > e1000_82544) { 743 eecd &= ~E1000_EECD_REQ; 744 E1000_WRITE_REG(hw, EECD, eecd); 745 } 746 747 e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM); 748 } 749 750 /****************************************************************************** 751 * Reads a 16 bit word from the EEPROM. 752 * 753 * hw - Struct containing variables accessed by shared code 754 *****************************************************************************/ 755 static int32_t 756 e1000_spi_eeprom_ready(struct e1000_hw *hw) 757 { 758 uint16_t retry_count = 0; 759 uint8_t spi_stat_reg; 760 761 DEBUGFUNC(); 762 763 /* Read "Status Register" repeatedly until the LSB is cleared. The 764 * EEPROM will signal that the command has been completed by clearing 765 * bit 0 of the internal status register. If it's not cleared within 766 * 5 milliseconds, then error out. 767 */ 768 retry_count = 0; 769 do { 770 e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI, 771 hw->eeprom.opcode_bits); 772 spi_stat_reg = (uint8_t)e1000_shift_in_ee_bits(hw, 8); 773 if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI)) 774 break; 775 776 udelay(5); 777 retry_count += 5; 778 779 e1000_standby_eeprom(hw); 780 } while (retry_count < EEPROM_MAX_RETRY_SPI); 781 782 /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and 783 * only 0-5mSec on 5V devices) 784 */ 785 if (retry_count >= EEPROM_MAX_RETRY_SPI) { 786 DEBUGOUT("SPI EEPROM Status error\n"); 787 return -E1000_ERR_EEPROM; 788 } 789 790 return E1000_SUCCESS; 791 } 792 793 /****************************************************************************** 794 * Reads a 16 bit word from the EEPROM. 795 * 796 * hw - Struct containing variables accessed by shared code 797 * offset - offset of word in the EEPROM to read 798 * data - word read from the EEPROM 799 *****************************************************************************/ 800 static int32_t 801 e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset, 802 uint16_t words, uint16_t *data) 803 { 804 struct e1000_eeprom_info *eeprom = &hw->eeprom; 805 uint32_t i = 0; 806 807 DEBUGFUNC(); 808 809 /* If eeprom is not yet detected, do so now */ 810 if (eeprom->word_size == 0) 811 e1000_init_eeprom_params(hw); 812 813 /* A check for invalid values: offset too large, too many words, 814 * and not enough words. 815 */ 816 if ((offset >= eeprom->word_size) || 817 (words > eeprom->word_size - offset) || 818 (words == 0)) { 819 DEBUGOUT("\"words\" parameter out of bounds." 820 "Words = %d, size = %d\n", offset, eeprom->word_size); 821 return -E1000_ERR_EEPROM; 822 } 823 824 /* EEPROM's that don't use EERD to read require us to bit-bang the SPI 825 * directly. In this case, we need to acquire the EEPROM so that 826 * FW or other port software does not interrupt. 827 */ 828 if (e1000_is_onboard_nvm_eeprom(hw) == true && 829 hw->eeprom.use_eerd == false) { 830 831 /* Prepare the EEPROM for bit-bang reading */ 832 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS) 833 return -E1000_ERR_EEPROM; 834 } 835 836 /* Eerd register EEPROM access requires no eeprom aquire/release */ 837 if (eeprom->use_eerd == true) 838 return e1000_read_eeprom_eerd(hw, offset, words, data); 839 840 /* ich8lan does not support currently. if needed, please 841 * add corresponding code and functions. 842 */ 843 #if 0 844 /* ICH EEPROM access is done via the ICH flash controller */ 845 if (eeprom->type == e1000_eeprom_ich8) 846 return e1000_read_eeprom_ich8(hw, offset, words, data); 847 #endif 848 /* Set up the SPI or Microwire EEPROM for bit-bang reading. We have 849 * acquired the EEPROM at this point, so any returns should relase it */ 850 if (eeprom->type == e1000_eeprom_spi) { 851 uint16_t word_in; 852 uint8_t read_opcode = EEPROM_READ_OPCODE_SPI; 853 854 if (e1000_spi_eeprom_ready(hw)) { 855 e1000_release_eeprom(hw); 856 return -E1000_ERR_EEPROM; 857 } 858 859 e1000_standby_eeprom(hw); 860 861 /* Some SPI eeproms use the 8th address bit embedded in 862 * the opcode */ 863 if ((eeprom->address_bits == 8) && (offset >= 128)) 864 read_opcode |= EEPROM_A8_OPCODE_SPI; 865 866 /* Send the READ command (opcode + addr) */ 867 e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits); 868 e1000_shift_out_ee_bits(hw, (uint16_t)(offset*2), 869 eeprom->address_bits); 870 871 /* Read the data. The address of the eeprom internally 872 * increments with each byte (spi) being read, saving on the 873 * overhead of eeprom setup and tear-down. The address 874 * counter will roll over if reading beyond the size of 875 * the eeprom, thus allowing the entire memory to be read 876 * starting from any offset. */ 877 for (i = 0; i < words; i++) { 878 word_in = e1000_shift_in_ee_bits(hw, 16); 879 data[i] = (word_in >> 8) | (word_in << 8); 880 } 881 } else if (eeprom->type == e1000_eeprom_microwire) { 882 for (i = 0; i < words; i++) { 883 /* Send the READ command (opcode + addr) */ 884 e1000_shift_out_ee_bits(hw, 885 EEPROM_READ_OPCODE_MICROWIRE, 886 eeprom->opcode_bits); 887 e1000_shift_out_ee_bits(hw, (uint16_t)(offset + i), 888 eeprom->address_bits); 889 890 /* Read the data. For microwire, each word requires 891 * the overhead of eeprom setup and tear-down. */ 892 data[i] = e1000_shift_in_ee_bits(hw, 16); 893 e1000_standby_eeprom(hw); 894 } 895 } 896 897 /* End this read operation */ 898 e1000_release_eeprom(hw); 899 900 return E1000_SUCCESS; 901 } 902 903 /****************************************************************************** 904 * Verifies that the EEPROM has a valid checksum 905 * 906 * hw - Struct containing variables accessed by shared code 907 * 908 * Reads the first 64 16 bit words of the EEPROM and sums the values read. 909 * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is 910 * valid. 911 *****************************************************************************/ 912 static int e1000_validate_eeprom_checksum(struct e1000_hw *hw) 913 { 914 uint16_t i, checksum, checksum_reg, *buf; 915 916 DEBUGFUNC(); 917 918 /* Allocate a temporary buffer */ 919 buf = malloc(sizeof(buf[0]) * (EEPROM_CHECKSUM_REG + 1)); 920 if (!buf) { 921 E1000_ERR(hw, "Unable to allocate EEPROM buffer!\n"); 922 return -E1000_ERR_EEPROM; 923 } 924 925 /* Read the EEPROM */ 926 if (e1000_read_eeprom(hw, 0, EEPROM_CHECKSUM_REG + 1, buf) < 0) { 927 E1000_ERR(hw, "Unable to read EEPROM!\n"); 928 return -E1000_ERR_EEPROM; 929 } 930 931 /* Compute the checksum */ 932 checksum = 0; 933 for (i = 0; i < EEPROM_CHECKSUM_REG; i++) 934 checksum += buf[i]; 935 checksum = ((uint16_t)EEPROM_SUM) - checksum; 936 checksum_reg = buf[i]; 937 938 /* Verify it! */ 939 if (checksum == checksum_reg) 940 return 0; 941 942 /* Hrm, verification failed, print an error */ 943 E1000_ERR(hw, "EEPROM checksum is incorrect!\n"); 944 E1000_ERR(hw, " ...register was 0x%04hx, calculated 0x%04hx\n", 945 checksum_reg, checksum); 946 947 return -E1000_ERR_EEPROM; 948 } 949 #endif /* CONFIG_E1000_NO_NVM */ 950 951 /***************************************************************************** 952 * Set PHY to class A mode 953 * Assumes the following operations will follow to enable the new class mode. 954 * 1. Do a PHY soft reset 955 * 2. Restart auto-negotiation or force link. 956 * 957 * hw - Struct containing variables accessed by shared code 958 ****************************************************************************/ 959 static int32_t 960 e1000_set_phy_mode(struct e1000_hw *hw) 961 { 962 #ifndef CONFIG_E1000_NO_NVM 963 int32_t ret_val; 964 uint16_t eeprom_data; 965 966 DEBUGFUNC(); 967 968 if ((hw->mac_type == e1000_82545_rev_3) && 969 (hw->media_type == e1000_media_type_copper)) { 970 ret_val = e1000_read_eeprom(hw, EEPROM_PHY_CLASS_WORD, 971 1, &eeprom_data); 972 if (ret_val) 973 return ret_val; 974 975 if ((eeprom_data != EEPROM_RESERVED_WORD) && 976 (eeprom_data & EEPROM_PHY_CLASS_A)) { 977 ret_val = e1000_write_phy_reg(hw, 978 M88E1000_PHY_PAGE_SELECT, 0x000B); 979 if (ret_val) 980 return ret_val; 981 ret_val = e1000_write_phy_reg(hw, 982 M88E1000_PHY_GEN_CONTROL, 0x8104); 983 if (ret_val) 984 return ret_val; 985 986 hw->phy_reset_disable = false; 987 } 988 } 989 #endif 990 return E1000_SUCCESS; 991 } 992 993 #ifndef CONFIG_E1000_NO_NVM 994 /*************************************************************************** 995 * 996 * Obtaining software semaphore bit (SMBI) before resetting PHY. 997 * 998 * hw: Struct containing variables accessed by shared code 999 * 1000 * returns: - E1000_ERR_RESET if fail to obtain semaphore. 1001 * E1000_SUCCESS at any other case. 1002 * 1003 ***************************************************************************/ 1004 static int32_t 1005 e1000_get_software_semaphore(struct e1000_hw *hw) 1006 { 1007 int32_t timeout = hw->eeprom.word_size + 1; 1008 uint32_t swsm; 1009 1010 DEBUGFUNC(); 1011 1012 if (hw->mac_type != e1000_80003es2lan) 1013 return E1000_SUCCESS; 1014 1015 while (timeout) { 1016 swsm = E1000_READ_REG(hw, SWSM); 1017 /* If SMBI bit cleared, it is now set and we hold 1018 * the semaphore */ 1019 if (!(swsm & E1000_SWSM_SMBI)) 1020 break; 1021 mdelay(1); 1022 timeout--; 1023 } 1024 1025 if (!timeout) { 1026 DEBUGOUT("Driver can't access device - SMBI bit is set.\n"); 1027 return -E1000_ERR_RESET; 1028 } 1029 1030 return E1000_SUCCESS; 1031 } 1032 #endif 1033 1034 /*************************************************************************** 1035 * This function clears HW semaphore bits. 1036 * 1037 * hw: Struct containing variables accessed by shared code 1038 * 1039 * returns: - None. 1040 * 1041 ***************************************************************************/ 1042 static void 1043 e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw) 1044 { 1045 #ifndef CONFIG_E1000_NO_NVM 1046 uint32_t swsm; 1047 1048 DEBUGFUNC(); 1049 1050 if (!hw->eeprom_semaphore_present) 1051 return; 1052 1053 swsm = E1000_READ_REG(hw, SWSM); 1054 if (hw->mac_type == e1000_80003es2lan) { 1055 /* Release both semaphores. */ 1056 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI); 1057 } else 1058 swsm &= ~(E1000_SWSM_SWESMBI); 1059 E1000_WRITE_REG(hw, SWSM, swsm); 1060 #endif 1061 } 1062 1063 /*************************************************************************** 1064 * 1065 * Using the combination of SMBI and SWESMBI semaphore bits when resetting 1066 * adapter or Eeprom access. 1067 * 1068 * hw: Struct containing variables accessed by shared code 1069 * 1070 * returns: - E1000_ERR_EEPROM if fail to access EEPROM. 1071 * E1000_SUCCESS at any other case. 1072 * 1073 ***************************************************************************/ 1074 static int32_t 1075 e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw) 1076 { 1077 #ifndef CONFIG_E1000_NO_NVM 1078 int32_t timeout; 1079 uint32_t swsm; 1080 1081 DEBUGFUNC(); 1082 1083 if (!hw->eeprom_semaphore_present) 1084 return E1000_SUCCESS; 1085 1086 if (hw->mac_type == e1000_80003es2lan) { 1087 /* Get the SW semaphore. */ 1088 if (e1000_get_software_semaphore(hw) != E1000_SUCCESS) 1089 return -E1000_ERR_EEPROM; 1090 } 1091 1092 /* Get the FW semaphore. */ 1093 timeout = hw->eeprom.word_size + 1; 1094 while (timeout) { 1095 swsm = E1000_READ_REG(hw, SWSM); 1096 swsm |= E1000_SWSM_SWESMBI; 1097 E1000_WRITE_REG(hw, SWSM, swsm); 1098 /* if we managed to set the bit we got the semaphore. */ 1099 swsm = E1000_READ_REG(hw, SWSM); 1100 if (swsm & E1000_SWSM_SWESMBI) 1101 break; 1102 1103 udelay(50); 1104 timeout--; 1105 } 1106 1107 if (!timeout) { 1108 /* Release semaphores */ 1109 e1000_put_hw_eeprom_semaphore(hw); 1110 DEBUGOUT("Driver can't access the Eeprom - " 1111 "SWESMBI bit is set.\n"); 1112 return -E1000_ERR_EEPROM; 1113 } 1114 #endif 1115 return E1000_SUCCESS; 1116 } 1117 1118 /* Take ownership of the PHY */ 1119 static int32_t 1120 e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask) 1121 { 1122 uint32_t swfw_sync = 0; 1123 uint32_t swmask = mask; 1124 uint32_t fwmask = mask << 16; 1125 int32_t timeout = 200; 1126 1127 DEBUGFUNC(); 1128 while (timeout) { 1129 if (e1000_get_hw_eeprom_semaphore(hw)) 1130 return -E1000_ERR_SWFW_SYNC; 1131 1132 swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC); 1133 if (!(swfw_sync & (fwmask | swmask))) 1134 break; 1135 1136 /* firmware currently using resource (fwmask) */ 1137 /* or other software thread currently using resource (swmask) */ 1138 e1000_put_hw_eeprom_semaphore(hw); 1139 mdelay(5); 1140 timeout--; 1141 } 1142 1143 if (!timeout) { 1144 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n"); 1145 return -E1000_ERR_SWFW_SYNC; 1146 } 1147 1148 swfw_sync |= swmask; 1149 E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync); 1150 1151 e1000_put_hw_eeprom_semaphore(hw); 1152 return E1000_SUCCESS; 1153 } 1154 1155 static void e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask) 1156 { 1157 uint32_t swfw_sync = 0; 1158 1159 DEBUGFUNC(); 1160 while (e1000_get_hw_eeprom_semaphore(hw)) 1161 ; /* Empty */ 1162 1163 swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC); 1164 swfw_sync &= ~mask; 1165 E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync); 1166 1167 e1000_put_hw_eeprom_semaphore(hw); 1168 } 1169 1170 static bool e1000_is_second_port(struct e1000_hw *hw) 1171 { 1172 switch (hw->mac_type) { 1173 case e1000_80003es2lan: 1174 case e1000_82546: 1175 case e1000_82571: 1176 if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1) 1177 return true; 1178 /* Fallthrough */ 1179 default: 1180 return false; 1181 } 1182 } 1183 1184 #ifndef CONFIG_E1000_NO_NVM 1185 /****************************************************************************** 1186 * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the 1187 * second function of dual function devices 1188 * 1189 * nic - Struct containing variables accessed by shared code 1190 *****************************************************************************/ 1191 static int 1192 e1000_read_mac_addr(struct e1000_hw *hw, unsigned char enetaddr[6]) 1193 { 1194 uint16_t offset; 1195 uint16_t eeprom_data; 1196 uint32_t reg_data = 0; 1197 int i; 1198 1199 DEBUGFUNC(); 1200 1201 for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) { 1202 offset = i >> 1; 1203 if (hw->mac_type == e1000_igb) { 1204 /* i210 preloads MAC address into RAL/RAH registers */ 1205 if (offset == 0) 1206 reg_data = E1000_READ_REG_ARRAY(hw, RA, 0); 1207 else if (offset == 1) 1208 reg_data >>= 16; 1209 else if (offset == 2) 1210 reg_data = E1000_READ_REG_ARRAY(hw, RA, 1); 1211 eeprom_data = reg_data & 0xffff; 1212 } else if (e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) { 1213 DEBUGOUT("EEPROM Read Error\n"); 1214 return -E1000_ERR_EEPROM; 1215 } 1216 enetaddr[i] = eeprom_data & 0xff; 1217 enetaddr[i + 1] = (eeprom_data >> 8) & 0xff; 1218 } 1219 1220 /* Invert the last bit if this is the second device */ 1221 if (e1000_is_second_port(hw)) 1222 enetaddr[5] ^= 1; 1223 1224 return 0; 1225 } 1226 #endif 1227 1228 /****************************************************************************** 1229 * Initializes receive address filters. 1230 * 1231 * hw - Struct containing variables accessed by shared code 1232 * 1233 * Places the MAC address in receive address register 0 and clears the rest 1234 * of the receive addresss registers. Clears the multicast table. Assumes 1235 * the receiver is in reset when the routine is called. 1236 *****************************************************************************/ 1237 static void 1238 e1000_init_rx_addrs(struct e1000_hw *hw, unsigned char enetaddr[6]) 1239 { 1240 uint32_t i; 1241 uint32_t addr_low; 1242 uint32_t addr_high; 1243 1244 DEBUGFUNC(); 1245 1246 /* Setup the receive address. */ 1247 DEBUGOUT("Programming MAC Address into RAR[0]\n"); 1248 addr_low = (enetaddr[0] | 1249 (enetaddr[1] << 8) | 1250 (enetaddr[2] << 16) | (enetaddr[3] << 24)); 1251 1252 addr_high = (enetaddr[4] | (enetaddr[5] << 8) | E1000_RAH_AV); 1253 1254 E1000_WRITE_REG_ARRAY(hw, RA, 0, addr_low); 1255 E1000_WRITE_REG_ARRAY(hw, RA, 1, addr_high); 1256 1257 /* Zero out the other 15 receive addresses. */ 1258 DEBUGOUT("Clearing RAR[1-15]\n"); 1259 for (i = 1; i < E1000_RAR_ENTRIES; i++) { 1260 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0); 1261 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0); 1262 } 1263 } 1264 1265 /****************************************************************************** 1266 * Clears the VLAN filer table 1267 * 1268 * hw - Struct containing variables accessed by shared code 1269 *****************************************************************************/ 1270 static void 1271 e1000_clear_vfta(struct e1000_hw *hw) 1272 { 1273 uint32_t offset; 1274 1275 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) 1276 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, 0); 1277 } 1278 1279 /****************************************************************************** 1280 * Set the mac type member in the hw struct. 1281 * 1282 * hw - Struct containing variables accessed by shared code 1283 *****************************************************************************/ 1284 int32_t 1285 e1000_set_mac_type(struct e1000_hw *hw) 1286 { 1287 DEBUGFUNC(); 1288 1289 switch (hw->device_id) { 1290 case E1000_DEV_ID_82542: 1291 switch (hw->revision_id) { 1292 case E1000_82542_2_0_REV_ID: 1293 hw->mac_type = e1000_82542_rev2_0; 1294 break; 1295 case E1000_82542_2_1_REV_ID: 1296 hw->mac_type = e1000_82542_rev2_1; 1297 break; 1298 default: 1299 /* Invalid 82542 revision ID */ 1300 return -E1000_ERR_MAC_TYPE; 1301 } 1302 break; 1303 case E1000_DEV_ID_82543GC_FIBER: 1304 case E1000_DEV_ID_82543GC_COPPER: 1305 hw->mac_type = e1000_82543; 1306 break; 1307 case E1000_DEV_ID_82544EI_COPPER: 1308 case E1000_DEV_ID_82544EI_FIBER: 1309 case E1000_DEV_ID_82544GC_COPPER: 1310 case E1000_DEV_ID_82544GC_LOM: 1311 hw->mac_type = e1000_82544; 1312 break; 1313 case E1000_DEV_ID_82540EM: 1314 case E1000_DEV_ID_82540EM_LOM: 1315 case E1000_DEV_ID_82540EP: 1316 case E1000_DEV_ID_82540EP_LOM: 1317 case E1000_DEV_ID_82540EP_LP: 1318 hw->mac_type = e1000_82540; 1319 break; 1320 case E1000_DEV_ID_82545EM_COPPER: 1321 case E1000_DEV_ID_82545EM_FIBER: 1322 hw->mac_type = e1000_82545; 1323 break; 1324 case E1000_DEV_ID_82545GM_COPPER: 1325 case E1000_DEV_ID_82545GM_FIBER: 1326 case E1000_DEV_ID_82545GM_SERDES: 1327 hw->mac_type = e1000_82545_rev_3; 1328 break; 1329 case E1000_DEV_ID_82546EB_COPPER: 1330 case E1000_DEV_ID_82546EB_FIBER: 1331 case E1000_DEV_ID_82546EB_QUAD_COPPER: 1332 hw->mac_type = e1000_82546; 1333 break; 1334 case E1000_DEV_ID_82546GB_COPPER: 1335 case E1000_DEV_ID_82546GB_FIBER: 1336 case E1000_DEV_ID_82546GB_SERDES: 1337 case E1000_DEV_ID_82546GB_PCIE: 1338 case E1000_DEV_ID_82546GB_QUAD_COPPER: 1339 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3: 1340 hw->mac_type = e1000_82546_rev_3; 1341 break; 1342 case E1000_DEV_ID_82541EI: 1343 case E1000_DEV_ID_82541EI_MOBILE: 1344 case E1000_DEV_ID_82541ER_LOM: 1345 hw->mac_type = e1000_82541; 1346 break; 1347 case E1000_DEV_ID_82541ER: 1348 case E1000_DEV_ID_82541GI: 1349 case E1000_DEV_ID_82541GI_LF: 1350 case E1000_DEV_ID_82541GI_MOBILE: 1351 hw->mac_type = e1000_82541_rev_2; 1352 break; 1353 case E1000_DEV_ID_82547EI: 1354 case E1000_DEV_ID_82547EI_MOBILE: 1355 hw->mac_type = e1000_82547; 1356 break; 1357 case E1000_DEV_ID_82547GI: 1358 hw->mac_type = e1000_82547_rev_2; 1359 break; 1360 case E1000_DEV_ID_82571EB_COPPER: 1361 case E1000_DEV_ID_82571EB_FIBER: 1362 case E1000_DEV_ID_82571EB_SERDES: 1363 case E1000_DEV_ID_82571EB_SERDES_DUAL: 1364 case E1000_DEV_ID_82571EB_SERDES_QUAD: 1365 case E1000_DEV_ID_82571EB_QUAD_COPPER: 1366 case E1000_DEV_ID_82571PT_QUAD_COPPER: 1367 case E1000_DEV_ID_82571EB_QUAD_FIBER: 1368 case E1000_DEV_ID_82571EB_QUAD_COPPER_LOWPROFILE: 1369 hw->mac_type = e1000_82571; 1370 break; 1371 case E1000_DEV_ID_82572EI_COPPER: 1372 case E1000_DEV_ID_82572EI_FIBER: 1373 case E1000_DEV_ID_82572EI_SERDES: 1374 case E1000_DEV_ID_82572EI: 1375 hw->mac_type = e1000_82572; 1376 break; 1377 case E1000_DEV_ID_82573E: 1378 case E1000_DEV_ID_82573E_IAMT: 1379 case E1000_DEV_ID_82573L: 1380 hw->mac_type = e1000_82573; 1381 break; 1382 case E1000_DEV_ID_82574L: 1383 hw->mac_type = e1000_82574; 1384 break; 1385 case E1000_DEV_ID_80003ES2LAN_COPPER_SPT: 1386 case E1000_DEV_ID_80003ES2LAN_SERDES_SPT: 1387 case E1000_DEV_ID_80003ES2LAN_COPPER_DPT: 1388 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT: 1389 hw->mac_type = e1000_80003es2lan; 1390 break; 1391 case E1000_DEV_ID_ICH8_IGP_M_AMT: 1392 case E1000_DEV_ID_ICH8_IGP_AMT: 1393 case E1000_DEV_ID_ICH8_IGP_C: 1394 case E1000_DEV_ID_ICH8_IFE: 1395 case E1000_DEV_ID_ICH8_IFE_GT: 1396 case E1000_DEV_ID_ICH8_IFE_G: 1397 case E1000_DEV_ID_ICH8_IGP_M: 1398 hw->mac_type = e1000_ich8lan; 1399 break; 1400 case PCI_DEVICE_ID_INTEL_I210_UNPROGRAMMED: 1401 case PCI_DEVICE_ID_INTEL_I211_UNPROGRAMMED: 1402 case PCI_DEVICE_ID_INTEL_I210_COPPER: 1403 case PCI_DEVICE_ID_INTEL_I211_COPPER: 1404 case PCI_DEVICE_ID_INTEL_I210_COPPER_FLASHLESS: 1405 case PCI_DEVICE_ID_INTEL_I210_SERDES: 1406 case PCI_DEVICE_ID_INTEL_I210_SERDES_FLASHLESS: 1407 case PCI_DEVICE_ID_INTEL_I210_1000BASEKX: 1408 hw->mac_type = e1000_igb; 1409 break; 1410 default: 1411 /* Should never have loaded on this device */ 1412 return -E1000_ERR_MAC_TYPE; 1413 } 1414 return E1000_SUCCESS; 1415 } 1416 1417 /****************************************************************************** 1418 * Reset the transmit and receive units; mask and clear all interrupts. 1419 * 1420 * hw - Struct containing variables accessed by shared code 1421 *****************************************************************************/ 1422 void 1423 e1000_reset_hw(struct e1000_hw *hw) 1424 { 1425 uint32_t ctrl; 1426 uint32_t ctrl_ext; 1427 uint32_t manc; 1428 uint32_t pba = 0; 1429 uint32_t reg; 1430 1431 DEBUGFUNC(); 1432 1433 /* get the correct pba value for both PCI and PCIe*/ 1434 if (hw->mac_type < e1000_82571) 1435 pba = E1000_DEFAULT_PCI_PBA; 1436 else 1437 pba = E1000_DEFAULT_PCIE_PBA; 1438 1439 /* For 82542 (rev 2.0), disable MWI before issuing a device reset */ 1440 if (hw->mac_type == e1000_82542_rev2_0) { 1441 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n"); 1442 pci_write_config_word(hw->pdev, PCI_COMMAND, 1443 hw->pci_cmd_word & ~PCI_COMMAND_INVALIDATE); 1444 } 1445 1446 /* Clear interrupt mask to stop board from generating interrupts */ 1447 DEBUGOUT("Masking off all interrupts\n"); 1448 if (hw->mac_type == e1000_igb) 1449 E1000_WRITE_REG(hw, I210_IAM, 0); 1450 E1000_WRITE_REG(hw, IMC, 0xffffffff); 1451 1452 /* Disable the Transmit and Receive units. Then delay to allow 1453 * any pending transactions to complete before we hit the MAC with 1454 * the global reset. 1455 */ 1456 E1000_WRITE_REG(hw, RCTL, 0); 1457 E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP); 1458 E1000_WRITE_FLUSH(hw); 1459 1460 /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */ 1461 hw->tbi_compatibility_on = false; 1462 1463 /* Delay to allow any outstanding PCI transactions to complete before 1464 * resetting the device 1465 */ 1466 mdelay(10); 1467 1468 /* Issue a global reset to the MAC. This will reset the chip's 1469 * transmit, receive, DMA, and link units. It will not effect 1470 * the current PCI configuration. The global reset bit is self- 1471 * clearing, and should clear within a microsecond. 1472 */ 1473 DEBUGOUT("Issuing a global reset to MAC\n"); 1474 ctrl = E1000_READ_REG(hw, CTRL); 1475 1476 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST)); 1477 1478 /* Force a reload from the EEPROM if necessary */ 1479 if (hw->mac_type == e1000_igb) { 1480 mdelay(20); 1481 reg = E1000_READ_REG(hw, STATUS); 1482 if (reg & E1000_STATUS_PF_RST_DONE) 1483 DEBUGOUT("PF OK\n"); 1484 reg = E1000_READ_REG(hw, I210_EECD); 1485 if (reg & E1000_EECD_AUTO_RD) 1486 DEBUGOUT("EEC OK\n"); 1487 } else if (hw->mac_type < e1000_82540) { 1488 /* Wait for reset to complete */ 1489 udelay(10); 1490 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 1491 ctrl_ext |= E1000_CTRL_EXT_EE_RST; 1492 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 1493 E1000_WRITE_FLUSH(hw); 1494 /* Wait for EEPROM reload */ 1495 mdelay(2); 1496 } else { 1497 /* Wait for EEPROM reload (it happens automatically) */ 1498 mdelay(4); 1499 /* Dissable HW ARPs on ASF enabled adapters */ 1500 manc = E1000_READ_REG(hw, MANC); 1501 manc &= ~(E1000_MANC_ARP_EN); 1502 E1000_WRITE_REG(hw, MANC, manc); 1503 } 1504 1505 /* Clear interrupt mask to stop board from generating interrupts */ 1506 DEBUGOUT("Masking off all interrupts\n"); 1507 if (hw->mac_type == e1000_igb) 1508 E1000_WRITE_REG(hw, I210_IAM, 0); 1509 E1000_WRITE_REG(hw, IMC, 0xffffffff); 1510 1511 /* Clear any pending interrupt events. */ 1512 E1000_READ_REG(hw, ICR); 1513 1514 /* If MWI was previously enabled, reenable it. */ 1515 if (hw->mac_type == e1000_82542_rev2_0) { 1516 pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word); 1517 } 1518 if (hw->mac_type != e1000_igb) 1519 E1000_WRITE_REG(hw, PBA, pba); 1520 } 1521 1522 /****************************************************************************** 1523 * 1524 * Initialize a number of hardware-dependent bits 1525 * 1526 * hw: Struct containing variables accessed by shared code 1527 * 1528 * This function contains hardware limitation workarounds for PCI-E adapters 1529 * 1530 *****************************************************************************/ 1531 static void 1532 e1000_initialize_hardware_bits(struct e1000_hw *hw) 1533 { 1534 if ((hw->mac_type >= e1000_82571) && 1535 (!hw->initialize_hw_bits_disable)) { 1536 /* Settings common to all PCI-express silicon */ 1537 uint32_t reg_ctrl, reg_ctrl_ext; 1538 uint32_t reg_tarc0, reg_tarc1; 1539 uint32_t reg_tctl; 1540 uint32_t reg_txdctl, reg_txdctl1; 1541 1542 /* link autonegotiation/sync workarounds */ 1543 reg_tarc0 = E1000_READ_REG(hw, TARC0); 1544 reg_tarc0 &= ~((1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)); 1545 1546 /* Enable not-done TX descriptor counting */ 1547 reg_txdctl = E1000_READ_REG(hw, TXDCTL); 1548 reg_txdctl |= E1000_TXDCTL_COUNT_DESC; 1549 E1000_WRITE_REG(hw, TXDCTL, reg_txdctl); 1550 1551 reg_txdctl1 = E1000_READ_REG(hw, TXDCTL1); 1552 reg_txdctl1 |= E1000_TXDCTL_COUNT_DESC; 1553 E1000_WRITE_REG(hw, TXDCTL1, reg_txdctl1); 1554 1555 /* IGB is cool */ 1556 if (hw->mac_type == e1000_igb) 1557 return; 1558 1559 switch (hw->mac_type) { 1560 case e1000_82571: 1561 case e1000_82572: 1562 /* Clear PHY TX compatible mode bits */ 1563 reg_tarc1 = E1000_READ_REG(hw, TARC1); 1564 reg_tarc1 &= ~((1 << 30)|(1 << 29)); 1565 1566 /* link autonegotiation/sync workarounds */ 1567 reg_tarc0 |= ((1 << 26)|(1 << 25)|(1 << 24)|(1 << 23)); 1568 1569 /* TX ring control fixes */ 1570 reg_tarc1 |= ((1 << 26)|(1 << 25)|(1 << 24)); 1571 1572 /* Multiple read bit is reversed polarity */ 1573 reg_tctl = E1000_READ_REG(hw, TCTL); 1574 if (reg_tctl & E1000_TCTL_MULR) 1575 reg_tarc1 &= ~(1 << 28); 1576 else 1577 reg_tarc1 |= (1 << 28); 1578 1579 E1000_WRITE_REG(hw, TARC1, reg_tarc1); 1580 break; 1581 case e1000_82573: 1582 case e1000_82574: 1583 reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 1584 reg_ctrl_ext &= ~(1 << 23); 1585 reg_ctrl_ext |= (1 << 22); 1586 1587 /* TX byte count fix */ 1588 reg_ctrl = E1000_READ_REG(hw, CTRL); 1589 reg_ctrl &= ~(1 << 29); 1590 1591 E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext); 1592 E1000_WRITE_REG(hw, CTRL, reg_ctrl); 1593 break; 1594 case e1000_80003es2lan: 1595 /* improve small packet performace for fiber/serdes */ 1596 if ((hw->media_type == e1000_media_type_fiber) 1597 || (hw->media_type == 1598 e1000_media_type_internal_serdes)) { 1599 reg_tarc0 &= ~(1 << 20); 1600 } 1601 1602 /* Multiple read bit is reversed polarity */ 1603 reg_tctl = E1000_READ_REG(hw, TCTL); 1604 reg_tarc1 = E1000_READ_REG(hw, TARC1); 1605 if (reg_tctl & E1000_TCTL_MULR) 1606 reg_tarc1 &= ~(1 << 28); 1607 else 1608 reg_tarc1 |= (1 << 28); 1609 1610 E1000_WRITE_REG(hw, TARC1, reg_tarc1); 1611 break; 1612 case e1000_ich8lan: 1613 /* Reduce concurrent DMA requests to 3 from 4 */ 1614 if ((hw->revision_id < 3) || 1615 ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) && 1616 (hw->device_id != E1000_DEV_ID_ICH8_IGP_M))) 1617 reg_tarc0 |= ((1 << 29)|(1 << 28)); 1618 1619 reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 1620 reg_ctrl_ext |= (1 << 22); 1621 E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext); 1622 1623 /* workaround TX hang with TSO=on */ 1624 reg_tarc0 |= ((1 << 27)|(1 << 26)|(1 << 24)|(1 << 23)); 1625 1626 /* Multiple read bit is reversed polarity */ 1627 reg_tctl = E1000_READ_REG(hw, TCTL); 1628 reg_tarc1 = E1000_READ_REG(hw, TARC1); 1629 if (reg_tctl & E1000_TCTL_MULR) 1630 reg_tarc1 &= ~(1 << 28); 1631 else 1632 reg_tarc1 |= (1 << 28); 1633 1634 /* workaround TX hang with TSO=on */ 1635 reg_tarc1 |= ((1 << 30)|(1 << 26)|(1 << 24)); 1636 1637 E1000_WRITE_REG(hw, TARC1, reg_tarc1); 1638 break; 1639 default: 1640 break; 1641 } 1642 1643 E1000_WRITE_REG(hw, TARC0, reg_tarc0); 1644 } 1645 } 1646 1647 /****************************************************************************** 1648 * Performs basic configuration of the adapter. 1649 * 1650 * hw - Struct containing variables accessed by shared code 1651 * 1652 * Assumes that the controller has previously been reset and is in a 1653 * post-reset uninitialized state. Initializes the receive address registers, 1654 * multicast table, and VLAN filter table. Calls routines to setup link 1655 * configuration and flow control settings. Clears all on-chip counters. Leaves 1656 * the transmit and receive units disabled and uninitialized. 1657 *****************************************************************************/ 1658 static int 1659 e1000_init_hw(struct e1000_hw *hw, unsigned char enetaddr[6]) 1660 { 1661 uint32_t ctrl; 1662 uint32_t i; 1663 int32_t ret_val; 1664 uint16_t pcix_cmd_word; 1665 uint16_t pcix_stat_hi_word; 1666 uint16_t cmd_mmrbc; 1667 uint16_t stat_mmrbc; 1668 uint32_t mta_size; 1669 uint32_t reg_data; 1670 uint32_t ctrl_ext; 1671 DEBUGFUNC(); 1672 /* force full DMA clock frequency for 10/100 on ICH8 A0-B0 */ 1673 if ((hw->mac_type == e1000_ich8lan) && 1674 ((hw->revision_id < 3) || 1675 ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) && 1676 (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))) { 1677 reg_data = E1000_READ_REG(hw, STATUS); 1678 reg_data &= ~0x80000000; 1679 E1000_WRITE_REG(hw, STATUS, reg_data); 1680 } 1681 /* Do not need initialize Identification LED */ 1682 1683 /* Set the media type and TBI compatibility */ 1684 e1000_set_media_type(hw); 1685 1686 /* Must be called after e1000_set_media_type 1687 * because media_type is used */ 1688 e1000_initialize_hardware_bits(hw); 1689 1690 /* Disabling VLAN filtering. */ 1691 DEBUGOUT("Initializing the IEEE VLAN\n"); 1692 /* VET hardcoded to standard value and VFTA removed in ICH8 LAN */ 1693 if (hw->mac_type != e1000_ich8lan) { 1694 if (hw->mac_type < e1000_82545_rev_3) 1695 E1000_WRITE_REG(hw, VET, 0); 1696 e1000_clear_vfta(hw); 1697 } 1698 1699 /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */ 1700 if (hw->mac_type == e1000_82542_rev2_0) { 1701 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n"); 1702 pci_write_config_word(hw->pdev, PCI_COMMAND, 1703 hw-> 1704 pci_cmd_word & ~PCI_COMMAND_INVALIDATE); 1705 E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST); 1706 E1000_WRITE_FLUSH(hw); 1707 mdelay(5); 1708 } 1709 1710 /* Setup the receive address. This involves initializing all of the Receive 1711 * Address Registers (RARs 0 - 15). 1712 */ 1713 e1000_init_rx_addrs(hw, enetaddr); 1714 1715 /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */ 1716 if (hw->mac_type == e1000_82542_rev2_0) { 1717 E1000_WRITE_REG(hw, RCTL, 0); 1718 E1000_WRITE_FLUSH(hw); 1719 mdelay(1); 1720 pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word); 1721 } 1722 1723 /* Zero out the Multicast HASH table */ 1724 DEBUGOUT("Zeroing the MTA\n"); 1725 mta_size = E1000_MC_TBL_SIZE; 1726 if (hw->mac_type == e1000_ich8lan) 1727 mta_size = E1000_MC_TBL_SIZE_ICH8LAN; 1728 for (i = 0; i < mta_size; i++) { 1729 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0); 1730 /* use write flush to prevent Memory Write Block (MWB) from 1731 * occuring when accessing our register space */ 1732 E1000_WRITE_FLUSH(hw); 1733 } 1734 #if 0 1735 /* Set the PCI priority bit correctly in the CTRL register. This 1736 * determines if the adapter gives priority to receives, or if it 1737 * gives equal priority to transmits and receives. Valid only on 1738 * 82542 and 82543 silicon. 1739 */ 1740 if (hw->dma_fairness && hw->mac_type <= e1000_82543) { 1741 ctrl = E1000_READ_REG(hw, CTRL); 1742 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR); 1743 } 1744 #endif 1745 switch (hw->mac_type) { 1746 case e1000_82545_rev_3: 1747 case e1000_82546_rev_3: 1748 case e1000_igb: 1749 break; 1750 default: 1751 /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */ 1752 if (hw->bus_type == e1000_bus_type_pcix) { 1753 pci_read_config_word(hw->pdev, PCIX_COMMAND_REGISTER, 1754 &pcix_cmd_word); 1755 pci_read_config_word(hw->pdev, PCIX_STATUS_REGISTER_HI, 1756 &pcix_stat_hi_word); 1757 cmd_mmrbc = 1758 (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) >> 1759 PCIX_COMMAND_MMRBC_SHIFT; 1760 stat_mmrbc = 1761 (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >> 1762 PCIX_STATUS_HI_MMRBC_SHIFT; 1763 if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K) 1764 stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K; 1765 if (cmd_mmrbc > stat_mmrbc) { 1766 pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK; 1767 pcix_cmd_word |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT; 1768 pci_write_config_word(hw->pdev, PCIX_COMMAND_REGISTER, 1769 pcix_cmd_word); 1770 } 1771 } 1772 break; 1773 } 1774 1775 /* More time needed for PHY to initialize */ 1776 if (hw->mac_type == e1000_ich8lan) 1777 mdelay(15); 1778 if (hw->mac_type == e1000_igb) 1779 mdelay(15); 1780 1781 /* Call a subroutine to configure the link and setup flow control. */ 1782 ret_val = e1000_setup_link(hw); 1783 1784 /* Set the transmit descriptor write-back policy */ 1785 if (hw->mac_type > e1000_82544) { 1786 ctrl = E1000_READ_REG(hw, TXDCTL); 1787 ctrl = 1788 (ctrl & ~E1000_TXDCTL_WTHRESH) | 1789 E1000_TXDCTL_FULL_TX_DESC_WB; 1790 E1000_WRITE_REG(hw, TXDCTL, ctrl); 1791 } 1792 1793 /* Set the receive descriptor write back policy */ 1794 if (hw->mac_type >= e1000_82571) { 1795 ctrl = E1000_READ_REG(hw, RXDCTL); 1796 ctrl = 1797 (ctrl & ~E1000_RXDCTL_WTHRESH) | 1798 E1000_RXDCTL_FULL_RX_DESC_WB; 1799 E1000_WRITE_REG(hw, RXDCTL, ctrl); 1800 } 1801 1802 switch (hw->mac_type) { 1803 default: 1804 break; 1805 case e1000_80003es2lan: 1806 /* Enable retransmit on late collisions */ 1807 reg_data = E1000_READ_REG(hw, TCTL); 1808 reg_data |= E1000_TCTL_RTLC; 1809 E1000_WRITE_REG(hw, TCTL, reg_data); 1810 1811 /* Configure Gigabit Carry Extend Padding */ 1812 reg_data = E1000_READ_REG(hw, TCTL_EXT); 1813 reg_data &= ~E1000_TCTL_EXT_GCEX_MASK; 1814 reg_data |= DEFAULT_80003ES2LAN_TCTL_EXT_GCEX; 1815 E1000_WRITE_REG(hw, TCTL_EXT, reg_data); 1816 1817 /* Configure Transmit Inter-Packet Gap */ 1818 reg_data = E1000_READ_REG(hw, TIPG); 1819 reg_data &= ~E1000_TIPG_IPGT_MASK; 1820 reg_data |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000; 1821 E1000_WRITE_REG(hw, TIPG, reg_data); 1822 1823 reg_data = E1000_READ_REG_ARRAY(hw, FFLT, 0x0001); 1824 reg_data &= ~0x00100000; 1825 E1000_WRITE_REG_ARRAY(hw, FFLT, 0x0001, reg_data); 1826 /* Fall through */ 1827 case e1000_82571: 1828 case e1000_82572: 1829 case e1000_ich8lan: 1830 ctrl = E1000_READ_REG(hw, TXDCTL1); 1831 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) 1832 | E1000_TXDCTL_FULL_TX_DESC_WB; 1833 E1000_WRITE_REG(hw, TXDCTL1, ctrl); 1834 break; 1835 case e1000_82573: 1836 case e1000_82574: 1837 reg_data = E1000_READ_REG(hw, GCR); 1838 reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX; 1839 E1000_WRITE_REG(hw, GCR, reg_data); 1840 case e1000_igb: 1841 break; 1842 } 1843 1844 #if 0 1845 /* Clear all of the statistics registers (clear on read). It is 1846 * important that we do this after we have tried to establish link 1847 * because the symbol error count will increment wildly if there 1848 * is no link. 1849 */ 1850 e1000_clear_hw_cntrs(hw); 1851 1852 /* ICH8 No-snoop bits are opposite polarity. 1853 * Set to snoop by default after reset. */ 1854 if (hw->mac_type == e1000_ich8lan) 1855 e1000_set_pci_ex_no_snoop(hw, PCI_EX_82566_SNOOP_ALL); 1856 #endif 1857 1858 if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER || 1859 hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) { 1860 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 1861 /* Relaxed ordering must be disabled to avoid a parity 1862 * error crash in a PCI slot. */ 1863 ctrl_ext |= E1000_CTRL_EXT_RO_DIS; 1864 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 1865 } 1866 1867 return ret_val; 1868 } 1869 1870 /****************************************************************************** 1871 * Configures flow control and link settings. 1872 * 1873 * hw - Struct containing variables accessed by shared code 1874 * 1875 * Determines which flow control settings to use. Calls the apropriate media- 1876 * specific link configuration function. Configures the flow control settings. 1877 * Assuming the adapter has a valid link partner, a valid link should be 1878 * established. Assumes the hardware has previously been reset and the 1879 * transmitter and receiver are not enabled. 1880 *****************************************************************************/ 1881 static int 1882 e1000_setup_link(struct e1000_hw *hw) 1883 { 1884 int32_t ret_val; 1885 #ifndef CONFIG_E1000_NO_NVM 1886 uint32_t ctrl_ext; 1887 uint16_t eeprom_data; 1888 #endif 1889 1890 DEBUGFUNC(); 1891 1892 /* In the case of the phy reset being blocked, we already have a link. 1893 * We do not have to set it up again. */ 1894 if (e1000_check_phy_reset_block(hw)) 1895 return E1000_SUCCESS; 1896 1897 #ifndef CONFIG_E1000_NO_NVM 1898 /* Read and store word 0x0F of the EEPROM. This word contains bits 1899 * that determine the hardware's default PAUSE (flow control) mode, 1900 * a bit that determines whether the HW defaults to enabling or 1901 * disabling auto-negotiation, and the direction of the 1902 * SW defined pins. If there is no SW over-ride of the flow 1903 * control setting, then the variable hw->fc will 1904 * be initialized based on a value in the EEPROM. 1905 */ 1906 if (e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, 1, 1907 &eeprom_data) < 0) { 1908 DEBUGOUT("EEPROM Read Error\n"); 1909 return -E1000_ERR_EEPROM; 1910 } 1911 #endif 1912 if (hw->fc == e1000_fc_default) { 1913 switch (hw->mac_type) { 1914 case e1000_ich8lan: 1915 case e1000_82573: 1916 case e1000_82574: 1917 case e1000_igb: 1918 hw->fc = e1000_fc_full; 1919 break; 1920 default: 1921 #ifndef CONFIG_E1000_NO_NVM 1922 ret_val = e1000_read_eeprom(hw, 1923 EEPROM_INIT_CONTROL2_REG, 1, &eeprom_data); 1924 if (ret_val) { 1925 DEBUGOUT("EEPROM Read Error\n"); 1926 return -E1000_ERR_EEPROM; 1927 } 1928 if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0) 1929 hw->fc = e1000_fc_none; 1930 else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 1931 EEPROM_WORD0F_ASM_DIR) 1932 hw->fc = e1000_fc_tx_pause; 1933 else 1934 #endif 1935 hw->fc = e1000_fc_full; 1936 break; 1937 } 1938 } 1939 1940 /* We want to save off the original Flow Control configuration just 1941 * in case we get disconnected and then reconnected into a different 1942 * hub or switch with different Flow Control capabilities. 1943 */ 1944 if (hw->mac_type == e1000_82542_rev2_0) 1945 hw->fc &= (~e1000_fc_tx_pause); 1946 1947 if ((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1)) 1948 hw->fc &= (~e1000_fc_rx_pause); 1949 1950 hw->original_fc = hw->fc; 1951 1952 DEBUGOUT("After fix-ups FlowControl is now = %x\n", hw->fc); 1953 1954 #ifndef CONFIG_E1000_NO_NVM 1955 /* Take the 4 bits from EEPROM word 0x0F that determine the initial 1956 * polarity value for the SW controlled pins, and setup the 1957 * Extended Device Control reg with that info. 1958 * This is needed because one of the SW controlled pins is used for 1959 * signal detection. So this should be done before e1000_setup_pcs_link() 1960 * or e1000_phy_setup() is called. 1961 */ 1962 if (hw->mac_type == e1000_82543) { 1963 ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) << 1964 SWDPIO__EXT_SHIFT); 1965 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 1966 } 1967 #endif 1968 1969 /* Call the necessary subroutine to configure the link. */ 1970 ret_val = (hw->media_type == e1000_media_type_fiber) ? 1971 e1000_setup_fiber_link(hw) : e1000_setup_copper_link(hw); 1972 if (ret_val < 0) { 1973 return ret_val; 1974 } 1975 1976 /* Initialize the flow control address, type, and PAUSE timer 1977 * registers to their default values. This is done even if flow 1978 * control is disabled, because it does not hurt anything to 1979 * initialize these registers. 1980 */ 1981 DEBUGOUT("Initializing the Flow Control address, type" 1982 "and timer regs\n"); 1983 1984 /* FCAL/H and FCT are hardcoded to standard values in e1000_ich8lan. */ 1985 if (hw->mac_type != e1000_ich8lan) { 1986 E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE); 1987 E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH); 1988 E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW); 1989 } 1990 1991 E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time); 1992 1993 /* Set the flow control receive threshold registers. Normally, 1994 * these registers will be set to a default threshold that may be 1995 * adjusted later by the driver's runtime code. However, if the 1996 * ability to transmit pause frames in not enabled, then these 1997 * registers will be set to 0. 1998 */ 1999 if (!(hw->fc & e1000_fc_tx_pause)) { 2000 E1000_WRITE_REG(hw, FCRTL, 0); 2001 E1000_WRITE_REG(hw, FCRTH, 0); 2002 } else { 2003 /* We need to set up the Receive Threshold high and low water marks 2004 * as well as (optionally) enabling the transmission of XON frames. 2005 */ 2006 if (hw->fc_send_xon) { 2007 E1000_WRITE_REG(hw, FCRTL, 2008 (hw->fc_low_water | E1000_FCRTL_XONE)); 2009 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water); 2010 } else { 2011 E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water); 2012 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water); 2013 } 2014 } 2015 return ret_val; 2016 } 2017 2018 /****************************************************************************** 2019 * Sets up link for a fiber based adapter 2020 * 2021 * hw - Struct containing variables accessed by shared code 2022 * 2023 * Manipulates Physical Coding Sublayer functions in order to configure 2024 * link. Assumes the hardware has been previously reset and the transmitter 2025 * and receiver are not enabled. 2026 *****************************************************************************/ 2027 static int 2028 e1000_setup_fiber_link(struct e1000_hw *hw) 2029 { 2030 uint32_t ctrl; 2031 uint32_t status; 2032 uint32_t txcw = 0; 2033 uint32_t i; 2034 uint32_t signal; 2035 int32_t ret_val; 2036 2037 DEBUGFUNC(); 2038 /* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be 2039 * set when the optics detect a signal. On older adapters, it will be 2040 * cleared when there is a signal 2041 */ 2042 ctrl = E1000_READ_REG(hw, CTRL); 2043 if ((hw->mac_type > e1000_82544) && !(ctrl & E1000_CTRL_ILOS)) 2044 signal = E1000_CTRL_SWDPIN1; 2045 else 2046 signal = 0; 2047 2048 printf("signal for %s is %x (ctrl %08x)!!!!\n", hw->name, signal, 2049 ctrl); 2050 /* Take the link out of reset */ 2051 ctrl &= ~(E1000_CTRL_LRST); 2052 2053 e1000_config_collision_dist(hw); 2054 2055 /* Check for a software override of the flow control settings, and setup 2056 * the device accordingly. If auto-negotiation is enabled, then software 2057 * will have to set the "PAUSE" bits to the correct value in the Tranmsit 2058 * Config Word Register (TXCW) and re-start auto-negotiation. However, if 2059 * auto-negotiation is disabled, then software will have to manually 2060 * configure the two flow control enable bits in the CTRL register. 2061 * 2062 * The possible values of the "fc" parameter are: 2063 * 0: Flow control is completely disabled 2064 * 1: Rx flow control is enabled (we can receive pause frames, but 2065 * not send pause frames). 2066 * 2: Tx flow control is enabled (we can send pause frames but we do 2067 * not support receiving pause frames). 2068 * 3: Both Rx and TX flow control (symmetric) are enabled. 2069 */ 2070 switch (hw->fc) { 2071 case e1000_fc_none: 2072 /* Flow control is completely disabled by a software over-ride. */ 2073 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD); 2074 break; 2075 case e1000_fc_rx_pause: 2076 /* RX Flow control is enabled and TX Flow control is disabled by a 2077 * software over-ride. Since there really isn't a way to advertise 2078 * that we are capable of RX Pause ONLY, we will advertise that we 2079 * support both symmetric and asymmetric RX PAUSE. Later, we will 2080 * disable the adapter's ability to send PAUSE frames. 2081 */ 2082 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); 2083 break; 2084 case e1000_fc_tx_pause: 2085 /* TX Flow control is enabled, and RX Flow control is disabled, by a 2086 * software over-ride. 2087 */ 2088 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR); 2089 break; 2090 case e1000_fc_full: 2091 /* Flow control (both RX and TX) is enabled by a software over-ride. */ 2092 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); 2093 break; 2094 default: 2095 DEBUGOUT("Flow control param set incorrectly\n"); 2096 return -E1000_ERR_CONFIG; 2097 break; 2098 } 2099 2100 /* Since auto-negotiation is enabled, take the link out of reset (the link 2101 * will be in reset, because we previously reset the chip). This will 2102 * restart auto-negotiation. If auto-neogtiation is successful then the 2103 * link-up status bit will be set and the flow control enable bits (RFCE 2104 * and TFCE) will be set according to their negotiated value. 2105 */ 2106 DEBUGOUT("Auto-negotiation enabled (%#x)\n", txcw); 2107 2108 E1000_WRITE_REG(hw, TXCW, txcw); 2109 E1000_WRITE_REG(hw, CTRL, ctrl); 2110 E1000_WRITE_FLUSH(hw); 2111 2112 hw->txcw = txcw; 2113 mdelay(1); 2114 2115 /* If we have a signal (the cable is plugged in) then poll for a "Link-Up" 2116 * indication in the Device Status Register. Time-out if a link isn't 2117 * seen in 500 milliseconds seconds (Auto-negotiation should complete in 2118 * less than 500 milliseconds even if the other end is doing it in SW). 2119 */ 2120 if ((E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) { 2121 DEBUGOUT("Looking for Link\n"); 2122 for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) { 2123 mdelay(10); 2124 status = E1000_READ_REG(hw, STATUS); 2125 if (status & E1000_STATUS_LU) 2126 break; 2127 } 2128 if (i == (LINK_UP_TIMEOUT / 10)) { 2129 /* AutoNeg failed to achieve a link, so we'll call 2130 * e1000_check_for_link. This routine will force the link up if we 2131 * detect a signal. This will allow us to communicate with 2132 * non-autonegotiating link partners. 2133 */ 2134 DEBUGOUT("Never got a valid link from auto-neg!!!\n"); 2135 hw->autoneg_failed = 1; 2136 ret_val = e1000_check_for_link(hw); 2137 if (ret_val < 0) { 2138 DEBUGOUT("Error while checking for link\n"); 2139 return ret_val; 2140 } 2141 hw->autoneg_failed = 0; 2142 } else { 2143 hw->autoneg_failed = 0; 2144 DEBUGOUT("Valid Link Found\n"); 2145 } 2146 } else { 2147 DEBUGOUT("No Signal Detected\n"); 2148 return -E1000_ERR_NOLINK; 2149 } 2150 return 0; 2151 } 2152 2153 /****************************************************************************** 2154 * Make sure we have a valid PHY and change PHY mode before link setup. 2155 * 2156 * hw - Struct containing variables accessed by shared code 2157 ******************************************************************************/ 2158 static int32_t 2159 e1000_copper_link_preconfig(struct e1000_hw *hw) 2160 { 2161 uint32_t ctrl; 2162 int32_t ret_val; 2163 uint16_t phy_data; 2164 2165 DEBUGFUNC(); 2166 2167 ctrl = E1000_READ_REG(hw, CTRL); 2168 /* With 82543, we need to force speed and duplex on the MAC equal to what 2169 * the PHY speed and duplex configuration is. In addition, we need to 2170 * perform a hardware reset on the PHY to take it out of reset. 2171 */ 2172 if (hw->mac_type > e1000_82543) { 2173 ctrl |= E1000_CTRL_SLU; 2174 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 2175 E1000_WRITE_REG(hw, CTRL, ctrl); 2176 } else { 2177 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX 2178 | E1000_CTRL_SLU); 2179 E1000_WRITE_REG(hw, CTRL, ctrl); 2180 ret_val = e1000_phy_hw_reset(hw); 2181 if (ret_val) 2182 return ret_val; 2183 } 2184 2185 /* Make sure we have a valid PHY */ 2186 ret_val = e1000_detect_gig_phy(hw); 2187 if (ret_val) { 2188 DEBUGOUT("Error, did not detect valid phy.\n"); 2189 return ret_val; 2190 } 2191 DEBUGOUT("Phy ID = %x\n", hw->phy_id); 2192 2193 /* Set PHY to class A mode (if necessary) */ 2194 ret_val = e1000_set_phy_mode(hw); 2195 if (ret_val) 2196 return ret_val; 2197 if ((hw->mac_type == e1000_82545_rev_3) || 2198 (hw->mac_type == e1000_82546_rev_3)) { 2199 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 2200 &phy_data); 2201 phy_data |= 0x00000008; 2202 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 2203 phy_data); 2204 } 2205 2206 if (hw->mac_type <= e1000_82543 || 2207 hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 || 2208 hw->mac_type == e1000_82541_rev_2 2209 || hw->mac_type == e1000_82547_rev_2) 2210 hw->phy_reset_disable = false; 2211 2212 return E1000_SUCCESS; 2213 } 2214 2215 /***************************************************************************** 2216 * 2217 * This function sets the lplu state according to the active flag. When 2218 * activating lplu this function also disables smart speed and vise versa. 2219 * lplu will not be activated unless the device autonegotiation advertisment 2220 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes. 2221 * hw: Struct containing variables accessed by shared code 2222 * active - true to enable lplu false to disable lplu. 2223 * 2224 * returns: - E1000_ERR_PHY if fail to read/write the PHY 2225 * E1000_SUCCESS at any other case. 2226 * 2227 ****************************************************************************/ 2228 2229 static int32_t 2230 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active) 2231 { 2232 uint32_t phy_ctrl = 0; 2233 int32_t ret_val; 2234 uint16_t phy_data; 2235 DEBUGFUNC(); 2236 2237 if (hw->phy_type != e1000_phy_igp && hw->phy_type != e1000_phy_igp_2 2238 && hw->phy_type != e1000_phy_igp_3) 2239 return E1000_SUCCESS; 2240 2241 /* During driver activity LPLU should not be used or it will attain link 2242 * from the lowest speeds starting from 10Mbps. The capability is used 2243 * for Dx transitions and states */ 2244 if (hw->mac_type == e1000_82541_rev_2 2245 || hw->mac_type == e1000_82547_rev_2) { 2246 ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, 2247 &phy_data); 2248 if (ret_val) 2249 return ret_val; 2250 } else if (hw->mac_type == e1000_ich8lan) { 2251 /* MAC writes into PHY register based on the state transition 2252 * and start auto-negotiation. SW driver can overwrite the 2253 * settings in CSR PHY power control E1000_PHY_CTRL register. */ 2254 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL); 2255 } else { 2256 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, 2257 &phy_data); 2258 if (ret_val) 2259 return ret_val; 2260 } 2261 2262 if (!active) { 2263 if (hw->mac_type == e1000_82541_rev_2 || 2264 hw->mac_type == e1000_82547_rev_2) { 2265 phy_data &= ~IGP01E1000_GMII_FLEX_SPD; 2266 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, 2267 phy_data); 2268 if (ret_val) 2269 return ret_val; 2270 } else { 2271 if (hw->mac_type == e1000_ich8lan) { 2272 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU; 2273 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); 2274 } else { 2275 phy_data &= ~IGP02E1000_PM_D3_LPLU; 2276 ret_val = e1000_write_phy_reg(hw, 2277 IGP02E1000_PHY_POWER_MGMT, phy_data); 2278 if (ret_val) 2279 return ret_val; 2280 } 2281 } 2282 2283 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during 2284 * Dx states where the power conservation is most important. During 2285 * driver activity we should enable SmartSpeed, so performance is 2286 * maintained. */ 2287 if (hw->smart_speed == e1000_smart_speed_on) { 2288 ret_val = e1000_read_phy_reg(hw, 2289 IGP01E1000_PHY_PORT_CONFIG, &phy_data); 2290 if (ret_val) 2291 return ret_val; 2292 2293 phy_data |= IGP01E1000_PSCFR_SMART_SPEED; 2294 ret_val = e1000_write_phy_reg(hw, 2295 IGP01E1000_PHY_PORT_CONFIG, phy_data); 2296 if (ret_val) 2297 return ret_val; 2298 } else if (hw->smart_speed == e1000_smart_speed_off) { 2299 ret_val = e1000_read_phy_reg(hw, 2300 IGP01E1000_PHY_PORT_CONFIG, &phy_data); 2301 if (ret_val) 2302 return ret_val; 2303 2304 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 2305 ret_val = e1000_write_phy_reg(hw, 2306 IGP01E1000_PHY_PORT_CONFIG, phy_data); 2307 if (ret_val) 2308 return ret_val; 2309 } 2310 2311 } else if ((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT) 2312 || (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL) || 2313 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) { 2314 2315 if (hw->mac_type == e1000_82541_rev_2 || 2316 hw->mac_type == e1000_82547_rev_2) { 2317 phy_data |= IGP01E1000_GMII_FLEX_SPD; 2318 ret_val = e1000_write_phy_reg(hw, 2319 IGP01E1000_GMII_FIFO, phy_data); 2320 if (ret_val) 2321 return ret_val; 2322 } else { 2323 if (hw->mac_type == e1000_ich8lan) { 2324 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU; 2325 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); 2326 } else { 2327 phy_data |= IGP02E1000_PM_D3_LPLU; 2328 ret_val = e1000_write_phy_reg(hw, 2329 IGP02E1000_PHY_POWER_MGMT, phy_data); 2330 if (ret_val) 2331 return ret_val; 2332 } 2333 } 2334 2335 /* When LPLU is enabled we should disable SmartSpeed */ 2336 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 2337 &phy_data); 2338 if (ret_val) 2339 return ret_val; 2340 2341 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 2342 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 2343 phy_data); 2344 if (ret_val) 2345 return ret_val; 2346 } 2347 return E1000_SUCCESS; 2348 } 2349 2350 /***************************************************************************** 2351 * 2352 * This function sets the lplu d0 state according to the active flag. When 2353 * activating lplu this function also disables smart speed and vise versa. 2354 * lplu will not be activated unless the device autonegotiation advertisment 2355 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes. 2356 * hw: Struct containing variables accessed by shared code 2357 * active - true to enable lplu false to disable lplu. 2358 * 2359 * returns: - E1000_ERR_PHY if fail to read/write the PHY 2360 * E1000_SUCCESS at any other case. 2361 * 2362 ****************************************************************************/ 2363 2364 static int32_t 2365 e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active) 2366 { 2367 uint32_t phy_ctrl = 0; 2368 int32_t ret_val; 2369 uint16_t phy_data; 2370 DEBUGFUNC(); 2371 2372 if (hw->mac_type <= e1000_82547_rev_2) 2373 return E1000_SUCCESS; 2374 2375 if (hw->mac_type == e1000_ich8lan) { 2376 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL); 2377 } else if (hw->mac_type == e1000_igb) { 2378 phy_ctrl = E1000_READ_REG(hw, I210_PHY_CTRL); 2379 } else { 2380 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, 2381 &phy_data); 2382 if (ret_val) 2383 return ret_val; 2384 } 2385 2386 if (!active) { 2387 if (hw->mac_type == e1000_ich8lan) { 2388 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU; 2389 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); 2390 } else if (hw->mac_type == e1000_igb) { 2391 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU; 2392 E1000_WRITE_REG(hw, I210_PHY_CTRL, phy_ctrl); 2393 } else { 2394 phy_data &= ~IGP02E1000_PM_D0_LPLU; 2395 ret_val = e1000_write_phy_reg(hw, 2396 IGP02E1000_PHY_POWER_MGMT, phy_data); 2397 if (ret_val) 2398 return ret_val; 2399 } 2400 2401 if (hw->mac_type == e1000_igb) 2402 return E1000_SUCCESS; 2403 2404 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during 2405 * Dx states where the power conservation is most important. During 2406 * driver activity we should enable SmartSpeed, so performance is 2407 * maintained. */ 2408 if (hw->smart_speed == e1000_smart_speed_on) { 2409 ret_val = e1000_read_phy_reg(hw, 2410 IGP01E1000_PHY_PORT_CONFIG, &phy_data); 2411 if (ret_val) 2412 return ret_val; 2413 2414 phy_data |= IGP01E1000_PSCFR_SMART_SPEED; 2415 ret_val = e1000_write_phy_reg(hw, 2416 IGP01E1000_PHY_PORT_CONFIG, phy_data); 2417 if (ret_val) 2418 return ret_val; 2419 } else if (hw->smart_speed == e1000_smart_speed_off) { 2420 ret_val = e1000_read_phy_reg(hw, 2421 IGP01E1000_PHY_PORT_CONFIG, &phy_data); 2422 if (ret_val) 2423 return ret_val; 2424 2425 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 2426 ret_val = e1000_write_phy_reg(hw, 2427 IGP01E1000_PHY_PORT_CONFIG, phy_data); 2428 if (ret_val) 2429 return ret_val; 2430 } 2431 2432 2433 } else { 2434 2435 if (hw->mac_type == e1000_ich8lan) { 2436 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU; 2437 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); 2438 } else if (hw->mac_type == e1000_igb) { 2439 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU; 2440 E1000_WRITE_REG(hw, I210_PHY_CTRL, phy_ctrl); 2441 } else { 2442 phy_data |= IGP02E1000_PM_D0_LPLU; 2443 ret_val = e1000_write_phy_reg(hw, 2444 IGP02E1000_PHY_POWER_MGMT, phy_data); 2445 if (ret_val) 2446 return ret_val; 2447 } 2448 2449 if (hw->mac_type == e1000_igb) 2450 return E1000_SUCCESS; 2451 2452 /* When LPLU is enabled we should disable SmartSpeed */ 2453 ret_val = e1000_read_phy_reg(hw, 2454 IGP01E1000_PHY_PORT_CONFIG, &phy_data); 2455 if (ret_val) 2456 return ret_val; 2457 2458 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 2459 ret_val = e1000_write_phy_reg(hw, 2460 IGP01E1000_PHY_PORT_CONFIG, phy_data); 2461 if (ret_val) 2462 return ret_val; 2463 2464 } 2465 return E1000_SUCCESS; 2466 } 2467 2468 /******************************************************************** 2469 * Copper link setup for e1000_phy_igp series. 2470 * 2471 * hw - Struct containing variables accessed by shared code 2472 *********************************************************************/ 2473 static int32_t 2474 e1000_copper_link_igp_setup(struct e1000_hw *hw) 2475 { 2476 uint32_t led_ctrl; 2477 int32_t ret_val; 2478 uint16_t phy_data; 2479 2480 DEBUGFUNC(); 2481 2482 if (hw->phy_reset_disable) 2483 return E1000_SUCCESS; 2484 2485 ret_val = e1000_phy_reset(hw); 2486 if (ret_val) { 2487 DEBUGOUT("Error Resetting the PHY\n"); 2488 return ret_val; 2489 } 2490 2491 /* Wait 15ms for MAC to configure PHY from eeprom settings */ 2492 mdelay(15); 2493 if (hw->mac_type != e1000_ich8lan) { 2494 /* Configure activity LED after PHY reset */ 2495 led_ctrl = E1000_READ_REG(hw, LEDCTL); 2496 led_ctrl &= IGP_ACTIVITY_LED_MASK; 2497 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); 2498 E1000_WRITE_REG(hw, LEDCTL, led_ctrl); 2499 } 2500 2501 /* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */ 2502 if (hw->phy_type == e1000_phy_igp) { 2503 /* disable lplu d3 during driver init */ 2504 ret_val = e1000_set_d3_lplu_state(hw, false); 2505 if (ret_val) { 2506 DEBUGOUT("Error Disabling LPLU D3\n"); 2507 return ret_val; 2508 } 2509 } 2510 2511 /* disable lplu d0 during driver init */ 2512 ret_val = e1000_set_d0_lplu_state(hw, false); 2513 if (ret_val) { 2514 DEBUGOUT("Error Disabling LPLU D0\n"); 2515 return ret_val; 2516 } 2517 /* Configure mdi-mdix settings */ 2518 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); 2519 if (ret_val) 2520 return ret_val; 2521 2522 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { 2523 hw->dsp_config_state = e1000_dsp_config_disabled; 2524 /* Force MDI for earlier revs of the IGP PHY */ 2525 phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX 2526 | IGP01E1000_PSCR_FORCE_MDI_MDIX); 2527 hw->mdix = 1; 2528 2529 } else { 2530 hw->dsp_config_state = e1000_dsp_config_enabled; 2531 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; 2532 2533 switch (hw->mdix) { 2534 case 1: 2535 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; 2536 break; 2537 case 2: 2538 phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX; 2539 break; 2540 case 0: 2541 default: 2542 phy_data |= IGP01E1000_PSCR_AUTO_MDIX; 2543 break; 2544 } 2545 } 2546 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); 2547 if (ret_val) 2548 return ret_val; 2549 2550 /* set auto-master slave resolution settings */ 2551 if (hw->autoneg) { 2552 e1000_ms_type phy_ms_setting = hw->master_slave; 2553 2554 if (hw->ffe_config_state == e1000_ffe_config_active) 2555 hw->ffe_config_state = e1000_ffe_config_enabled; 2556 2557 if (hw->dsp_config_state == e1000_dsp_config_activated) 2558 hw->dsp_config_state = e1000_dsp_config_enabled; 2559 2560 /* when autonegotiation advertisment is only 1000Mbps then we 2561 * should disable SmartSpeed and enable Auto MasterSlave 2562 * resolution as hardware default. */ 2563 if (hw->autoneg_advertised == ADVERTISE_1000_FULL) { 2564 /* Disable SmartSpeed */ 2565 ret_val = e1000_read_phy_reg(hw, 2566 IGP01E1000_PHY_PORT_CONFIG, &phy_data); 2567 if (ret_val) 2568 return ret_val; 2569 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 2570 ret_val = e1000_write_phy_reg(hw, 2571 IGP01E1000_PHY_PORT_CONFIG, phy_data); 2572 if (ret_val) 2573 return ret_val; 2574 /* Set auto Master/Slave resolution process */ 2575 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, 2576 &phy_data); 2577 if (ret_val) 2578 return ret_val; 2579 phy_data &= ~CR_1000T_MS_ENABLE; 2580 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, 2581 phy_data); 2582 if (ret_val) 2583 return ret_val; 2584 } 2585 2586 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data); 2587 if (ret_val) 2588 return ret_val; 2589 2590 /* load defaults for future use */ 2591 hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ? 2592 ((phy_data & CR_1000T_MS_VALUE) ? 2593 e1000_ms_force_master : 2594 e1000_ms_force_slave) : 2595 e1000_ms_auto; 2596 2597 switch (phy_ms_setting) { 2598 case e1000_ms_force_master: 2599 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE); 2600 break; 2601 case e1000_ms_force_slave: 2602 phy_data |= CR_1000T_MS_ENABLE; 2603 phy_data &= ~(CR_1000T_MS_VALUE); 2604 break; 2605 case e1000_ms_auto: 2606 phy_data &= ~CR_1000T_MS_ENABLE; 2607 default: 2608 break; 2609 } 2610 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data); 2611 if (ret_val) 2612 return ret_val; 2613 } 2614 2615 return E1000_SUCCESS; 2616 } 2617 2618 /***************************************************************************** 2619 * This function checks the mode of the firmware. 2620 * 2621 * returns - true when the mode is IAMT or false. 2622 ****************************************************************************/ 2623 bool 2624 e1000_check_mng_mode(struct e1000_hw *hw) 2625 { 2626 uint32_t fwsm; 2627 DEBUGFUNC(); 2628 2629 fwsm = E1000_READ_REG(hw, FWSM); 2630 2631 if (hw->mac_type == e1000_ich8lan) { 2632 if ((fwsm & E1000_FWSM_MODE_MASK) == 2633 (E1000_MNG_ICH_IAMT_MODE << E1000_FWSM_MODE_SHIFT)) 2634 return true; 2635 } else if ((fwsm & E1000_FWSM_MODE_MASK) == 2636 (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT)) 2637 return true; 2638 2639 return false; 2640 } 2641 2642 static int32_t 2643 e1000_write_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t data) 2644 { 2645 uint16_t swfw = E1000_SWFW_PHY0_SM; 2646 uint32_t reg_val; 2647 DEBUGFUNC(); 2648 2649 if (e1000_is_second_port(hw)) 2650 swfw = E1000_SWFW_PHY1_SM; 2651 2652 if (e1000_swfw_sync_acquire(hw, swfw)) 2653 return -E1000_ERR_SWFW_SYNC; 2654 2655 reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) 2656 & E1000_KUMCTRLSTA_OFFSET) | data; 2657 E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val); 2658 udelay(2); 2659 2660 return E1000_SUCCESS; 2661 } 2662 2663 static int32_t 2664 e1000_read_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *data) 2665 { 2666 uint16_t swfw = E1000_SWFW_PHY0_SM; 2667 uint32_t reg_val; 2668 DEBUGFUNC(); 2669 2670 if (e1000_is_second_port(hw)) 2671 swfw = E1000_SWFW_PHY1_SM; 2672 2673 if (e1000_swfw_sync_acquire(hw, swfw)) { 2674 debug("%s[%i]\n", __func__, __LINE__); 2675 return -E1000_ERR_SWFW_SYNC; 2676 } 2677 2678 /* Write register address */ 2679 reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) & 2680 E1000_KUMCTRLSTA_OFFSET) | E1000_KUMCTRLSTA_REN; 2681 E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val); 2682 udelay(2); 2683 2684 /* Read the data returned */ 2685 reg_val = E1000_READ_REG(hw, KUMCTRLSTA); 2686 *data = (uint16_t)reg_val; 2687 2688 return E1000_SUCCESS; 2689 } 2690 2691 /******************************************************************** 2692 * Copper link setup for e1000_phy_gg82563 series. 2693 * 2694 * hw - Struct containing variables accessed by shared code 2695 *********************************************************************/ 2696 static int32_t 2697 e1000_copper_link_ggp_setup(struct e1000_hw *hw) 2698 { 2699 int32_t ret_val; 2700 uint16_t phy_data; 2701 uint32_t reg_data; 2702 2703 DEBUGFUNC(); 2704 2705 if (!hw->phy_reset_disable) { 2706 /* Enable CRS on TX for half-duplex operation. */ 2707 ret_val = e1000_read_phy_reg(hw, 2708 GG82563_PHY_MAC_SPEC_CTRL, &phy_data); 2709 if (ret_val) 2710 return ret_val; 2711 2712 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX; 2713 /* Use 25MHz for both link down and 1000BASE-T for Tx clock */ 2714 phy_data |= GG82563_MSCR_TX_CLK_1000MBPS_25MHZ; 2715 2716 ret_val = e1000_write_phy_reg(hw, 2717 GG82563_PHY_MAC_SPEC_CTRL, phy_data); 2718 if (ret_val) 2719 return ret_val; 2720 2721 /* Options: 2722 * MDI/MDI-X = 0 (default) 2723 * 0 - Auto for all speeds 2724 * 1 - MDI mode 2725 * 2 - MDI-X mode 2726 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) 2727 */ 2728 ret_val = e1000_read_phy_reg(hw, 2729 GG82563_PHY_SPEC_CTRL, &phy_data); 2730 if (ret_val) 2731 return ret_val; 2732 2733 phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK; 2734 2735 switch (hw->mdix) { 2736 case 1: 2737 phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDI; 2738 break; 2739 case 2: 2740 phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDIX; 2741 break; 2742 case 0: 2743 default: 2744 phy_data |= GG82563_PSCR_CROSSOVER_MODE_AUTO; 2745 break; 2746 } 2747 2748 /* Options: 2749 * disable_polarity_correction = 0 (default) 2750 * Automatic Correction for Reversed Cable Polarity 2751 * 0 - Disabled 2752 * 1 - Enabled 2753 */ 2754 phy_data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE; 2755 ret_val = e1000_write_phy_reg(hw, 2756 GG82563_PHY_SPEC_CTRL, phy_data); 2757 2758 if (ret_val) 2759 return ret_val; 2760 2761 /* SW Reset the PHY so all changes take effect */ 2762 ret_val = e1000_phy_reset(hw); 2763 if (ret_val) { 2764 DEBUGOUT("Error Resetting the PHY\n"); 2765 return ret_val; 2766 } 2767 } /* phy_reset_disable */ 2768 2769 if (hw->mac_type == e1000_80003es2lan) { 2770 /* Bypass RX and TX FIFO's */ 2771 ret_val = e1000_write_kmrn_reg(hw, 2772 E1000_KUMCTRLSTA_OFFSET_FIFO_CTRL, 2773 E1000_KUMCTRLSTA_FIFO_CTRL_RX_BYPASS 2774 | E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS); 2775 if (ret_val) 2776 return ret_val; 2777 2778 ret_val = e1000_read_phy_reg(hw, 2779 GG82563_PHY_SPEC_CTRL_2, &phy_data); 2780 if (ret_val) 2781 return ret_val; 2782 2783 phy_data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG; 2784 ret_val = e1000_write_phy_reg(hw, 2785 GG82563_PHY_SPEC_CTRL_2, phy_data); 2786 2787 if (ret_val) 2788 return ret_val; 2789 2790 reg_data = E1000_READ_REG(hw, CTRL_EXT); 2791 reg_data &= ~(E1000_CTRL_EXT_LINK_MODE_MASK); 2792 E1000_WRITE_REG(hw, CTRL_EXT, reg_data); 2793 2794 ret_val = e1000_read_phy_reg(hw, 2795 GG82563_PHY_PWR_MGMT_CTRL, &phy_data); 2796 if (ret_val) 2797 return ret_val; 2798 2799 /* Do not init these registers when the HW is in IAMT mode, since the 2800 * firmware will have already initialized them. We only initialize 2801 * them if the HW is not in IAMT mode. 2802 */ 2803 if (e1000_check_mng_mode(hw) == false) { 2804 /* Enable Electrical Idle on the PHY */ 2805 phy_data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE; 2806 ret_val = e1000_write_phy_reg(hw, 2807 GG82563_PHY_PWR_MGMT_CTRL, phy_data); 2808 if (ret_val) 2809 return ret_val; 2810 2811 ret_val = e1000_read_phy_reg(hw, 2812 GG82563_PHY_KMRN_MODE_CTRL, &phy_data); 2813 if (ret_val) 2814 return ret_val; 2815 2816 phy_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; 2817 ret_val = e1000_write_phy_reg(hw, 2818 GG82563_PHY_KMRN_MODE_CTRL, phy_data); 2819 2820 if (ret_val) 2821 return ret_val; 2822 } 2823 2824 /* Workaround: Disable padding in Kumeran interface in the MAC 2825 * and in the PHY to avoid CRC errors. 2826 */ 2827 ret_val = e1000_read_phy_reg(hw, 2828 GG82563_PHY_INBAND_CTRL, &phy_data); 2829 if (ret_val) 2830 return ret_val; 2831 phy_data |= GG82563_ICR_DIS_PADDING; 2832 ret_val = e1000_write_phy_reg(hw, 2833 GG82563_PHY_INBAND_CTRL, phy_data); 2834 if (ret_val) 2835 return ret_val; 2836 } 2837 return E1000_SUCCESS; 2838 } 2839 2840 /******************************************************************** 2841 * Copper link setup for e1000_phy_m88 series. 2842 * 2843 * hw - Struct containing variables accessed by shared code 2844 *********************************************************************/ 2845 static int32_t 2846 e1000_copper_link_mgp_setup(struct e1000_hw *hw) 2847 { 2848 int32_t ret_val; 2849 uint16_t phy_data; 2850 2851 DEBUGFUNC(); 2852 2853 if (hw->phy_reset_disable) 2854 return E1000_SUCCESS; 2855 2856 /* Enable CRS on TX. This must be set for half-duplex operation. */ 2857 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 2858 if (ret_val) 2859 return ret_val; 2860 2861 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; 2862 2863 /* Options: 2864 * MDI/MDI-X = 0 (default) 2865 * 0 - Auto for all speeds 2866 * 1 - MDI mode 2867 * 2 - MDI-X mode 2868 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) 2869 */ 2870 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 2871 2872 switch (hw->mdix) { 2873 case 1: 2874 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; 2875 break; 2876 case 2: 2877 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; 2878 break; 2879 case 3: 2880 phy_data |= M88E1000_PSCR_AUTO_X_1000T; 2881 break; 2882 case 0: 2883 default: 2884 phy_data |= M88E1000_PSCR_AUTO_X_MODE; 2885 break; 2886 } 2887 2888 /* Options: 2889 * disable_polarity_correction = 0 (default) 2890 * Automatic Correction for Reversed Cable Polarity 2891 * 0 - Disabled 2892 * 1 - Enabled 2893 */ 2894 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; 2895 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 2896 if (ret_val) 2897 return ret_val; 2898 2899 if (hw->phy_revision < M88E1011_I_REV_4) { 2900 /* Force TX_CLK in the Extended PHY Specific Control Register 2901 * to 25MHz clock. 2902 */ 2903 ret_val = e1000_read_phy_reg(hw, 2904 M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); 2905 if (ret_val) 2906 return ret_val; 2907 2908 phy_data |= M88E1000_EPSCR_TX_CLK_25; 2909 2910 if ((hw->phy_revision == E1000_REVISION_2) && 2911 (hw->phy_id == M88E1111_I_PHY_ID)) { 2912 /* Vidalia Phy, set the downshift counter to 5x */ 2913 phy_data &= ~(M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK); 2914 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X; 2915 ret_val = e1000_write_phy_reg(hw, 2916 M88E1000_EXT_PHY_SPEC_CTRL, phy_data); 2917 if (ret_val) 2918 return ret_val; 2919 } else { 2920 /* Configure Master and Slave downshift values */ 2921 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 2922 | M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK); 2923 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X 2924 | M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X); 2925 ret_val = e1000_write_phy_reg(hw, 2926 M88E1000_EXT_PHY_SPEC_CTRL, phy_data); 2927 if (ret_val) 2928 return ret_val; 2929 } 2930 } 2931 2932 /* SW Reset the PHY so all changes take effect */ 2933 ret_val = e1000_phy_reset(hw); 2934 if (ret_val) { 2935 DEBUGOUT("Error Resetting the PHY\n"); 2936 return ret_val; 2937 } 2938 2939 return E1000_SUCCESS; 2940 } 2941 2942 /******************************************************************** 2943 * Setup auto-negotiation and flow control advertisements, 2944 * and then perform auto-negotiation. 2945 * 2946 * hw - Struct containing variables accessed by shared code 2947 *********************************************************************/ 2948 static int32_t 2949 e1000_copper_link_autoneg(struct e1000_hw *hw) 2950 { 2951 int32_t ret_val; 2952 uint16_t phy_data; 2953 2954 DEBUGFUNC(); 2955 2956 /* Perform some bounds checking on the hw->autoneg_advertised 2957 * parameter. If this variable is zero, then set it to the default. 2958 */ 2959 hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT; 2960 2961 /* If autoneg_advertised is zero, we assume it was not defaulted 2962 * by the calling code so we set to advertise full capability. 2963 */ 2964 if (hw->autoneg_advertised == 0) 2965 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT; 2966 2967 /* IFE phy only supports 10/100 */ 2968 if (hw->phy_type == e1000_phy_ife) 2969 hw->autoneg_advertised &= AUTONEG_ADVERTISE_10_100_ALL; 2970 2971 DEBUGOUT("Reconfiguring auto-neg advertisement params\n"); 2972 ret_val = e1000_phy_setup_autoneg(hw); 2973 if (ret_val) { 2974 DEBUGOUT("Error Setting up Auto-Negotiation\n"); 2975 return ret_val; 2976 } 2977 DEBUGOUT("Restarting Auto-Neg\n"); 2978 2979 /* Restart auto-negotiation by setting the Auto Neg Enable bit and 2980 * the Auto Neg Restart bit in the PHY control register. 2981 */ 2982 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data); 2983 if (ret_val) 2984 return ret_val; 2985 2986 phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); 2987 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data); 2988 if (ret_val) 2989 return ret_val; 2990 2991 /* Does the user want to wait for Auto-Neg to complete here, or 2992 * check at a later time (for example, callback routine). 2993 */ 2994 /* If we do not wait for autonegtation to complete I 2995 * do not see a valid link status. 2996 * wait_autoneg_complete = 1 . 2997 */ 2998 if (hw->wait_autoneg_complete) { 2999 ret_val = e1000_wait_autoneg(hw); 3000 if (ret_val) { 3001 DEBUGOUT("Error while waiting for autoneg" 3002 "to complete\n"); 3003 return ret_val; 3004 } 3005 } 3006 3007 hw->get_link_status = true; 3008 3009 return E1000_SUCCESS; 3010 } 3011 3012 /****************************************************************************** 3013 * Config the MAC and the PHY after link is up. 3014 * 1) Set up the MAC to the current PHY speed/duplex 3015 * if we are on 82543. If we 3016 * are on newer silicon, we only need to configure 3017 * collision distance in the Transmit Control Register. 3018 * 2) Set up flow control on the MAC to that established with 3019 * the link partner. 3020 * 3) Config DSP to improve Gigabit link quality for some PHY revisions. 3021 * 3022 * hw - Struct containing variables accessed by shared code 3023 ******************************************************************************/ 3024 static int32_t 3025 e1000_copper_link_postconfig(struct e1000_hw *hw) 3026 { 3027 int32_t ret_val; 3028 DEBUGFUNC(); 3029 3030 if (hw->mac_type >= e1000_82544) { 3031 e1000_config_collision_dist(hw); 3032 } else { 3033 ret_val = e1000_config_mac_to_phy(hw); 3034 if (ret_val) { 3035 DEBUGOUT("Error configuring MAC to PHY settings\n"); 3036 return ret_val; 3037 } 3038 } 3039 ret_val = e1000_config_fc_after_link_up(hw); 3040 if (ret_val) { 3041 DEBUGOUT("Error Configuring Flow Control\n"); 3042 return ret_val; 3043 } 3044 return E1000_SUCCESS; 3045 } 3046 3047 /****************************************************************************** 3048 * Detects which PHY is present and setup the speed and duplex 3049 * 3050 * hw - Struct containing variables accessed by shared code 3051 ******************************************************************************/ 3052 static int 3053 e1000_setup_copper_link(struct e1000_hw *hw) 3054 { 3055 int32_t ret_val; 3056 uint16_t i; 3057 uint16_t phy_data; 3058 uint16_t reg_data; 3059 3060 DEBUGFUNC(); 3061 3062 switch (hw->mac_type) { 3063 case e1000_80003es2lan: 3064 case e1000_ich8lan: 3065 /* Set the mac to wait the maximum time between each 3066 * iteration and increase the max iterations when 3067 * polling the phy; this fixes erroneous timeouts at 10Mbps. */ 3068 ret_val = e1000_write_kmrn_reg(hw, 3069 GG82563_REG(0x34, 4), 0xFFFF); 3070 if (ret_val) 3071 return ret_val; 3072 ret_val = e1000_read_kmrn_reg(hw, 3073 GG82563_REG(0x34, 9), ®_data); 3074 if (ret_val) 3075 return ret_val; 3076 reg_data |= 0x3F; 3077 ret_val = e1000_write_kmrn_reg(hw, 3078 GG82563_REG(0x34, 9), reg_data); 3079 if (ret_val) 3080 return ret_val; 3081 default: 3082 break; 3083 } 3084 3085 /* Check if it is a valid PHY and set PHY mode if necessary. */ 3086 ret_val = e1000_copper_link_preconfig(hw); 3087 if (ret_val) 3088 return ret_val; 3089 switch (hw->mac_type) { 3090 case e1000_80003es2lan: 3091 /* Kumeran registers are written-only */ 3092 reg_data = 3093 E1000_KUMCTRLSTA_INB_CTRL_LINK_STATUS_TX_TIMEOUT_DEFAULT; 3094 reg_data |= E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING; 3095 ret_val = e1000_write_kmrn_reg(hw, 3096 E1000_KUMCTRLSTA_OFFSET_INB_CTRL, reg_data); 3097 if (ret_val) 3098 return ret_val; 3099 break; 3100 default: 3101 break; 3102 } 3103 3104 if (hw->phy_type == e1000_phy_igp || 3105 hw->phy_type == e1000_phy_igp_3 || 3106 hw->phy_type == e1000_phy_igp_2) { 3107 ret_val = e1000_copper_link_igp_setup(hw); 3108 if (ret_val) 3109 return ret_val; 3110 } else if (hw->phy_type == e1000_phy_m88 || 3111 hw->phy_type == e1000_phy_igb) { 3112 ret_val = e1000_copper_link_mgp_setup(hw); 3113 if (ret_val) 3114 return ret_val; 3115 } else if (hw->phy_type == e1000_phy_gg82563) { 3116 ret_val = e1000_copper_link_ggp_setup(hw); 3117 if (ret_val) 3118 return ret_val; 3119 } 3120 3121 /* always auto */ 3122 /* Setup autoneg and flow control advertisement 3123 * and perform autonegotiation */ 3124 ret_val = e1000_copper_link_autoneg(hw); 3125 if (ret_val) 3126 return ret_val; 3127 3128 /* Check link status. Wait up to 100 microseconds for link to become 3129 * valid. 3130 */ 3131 for (i = 0; i < 10; i++) { 3132 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); 3133 if (ret_val) 3134 return ret_val; 3135 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); 3136 if (ret_val) 3137 return ret_val; 3138 3139 if (phy_data & MII_SR_LINK_STATUS) { 3140 /* Config the MAC and PHY after link is up */ 3141 ret_val = e1000_copper_link_postconfig(hw); 3142 if (ret_val) 3143 return ret_val; 3144 3145 DEBUGOUT("Valid link established!!!\n"); 3146 return E1000_SUCCESS; 3147 } 3148 udelay(10); 3149 } 3150 3151 DEBUGOUT("Unable to establish link!!!\n"); 3152 return E1000_SUCCESS; 3153 } 3154 3155 /****************************************************************************** 3156 * Configures PHY autoneg and flow control advertisement settings 3157 * 3158 * hw - Struct containing variables accessed by shared code 3159 ******************************************************************************/ 3160 int32_t 3161 e1000_phy_setup_autoneg(struct e1000_hw *hw) 3162 { 3163 int32_t ret_val; 3164 uint16_t mii_autoneg_adv_reg; 3165 uint16_t mii_1000t_ctrl_reg; 3166 3167 DEBUGFUNC(); 3168 3169 /* Read the MII Auto-Neg Advertisement Register (Address 4). */ 3170 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg); 3171 if (ret_val) 3172 return ret_val; 3173 3174 if (hw->phy_type != e1000_phy_ife) { 3175 /* Read the MII 1000Base-T Control Register (Address 9). */ 3176 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, 3177 &mii_1000t_ctrl_reg); 3178 if (ret_val) 3179 return ret_val; 3180 } else 3181 mii_1000t_ctrl_reg = 0; 3182 3183 /* Need to parse both autoneg_advertised and fc and set up 3184 * the appropriate PHY registers. First we will parse for 3185 * autoneg_advertised software override. Since we can advertise 3186 * a plethora of combinations, we need to check each bit 3187 * individually. 3188 */ 3189 3190 /* First we clear all the 10/100 mb speed bits in the Auto-Neg 3191 * Advertisement Register (Address 4) and the 1000 mb speed bits in 3192 * the 1000Base-T Control Register (Address 9). 3193 */ 3194 mii_autoneg_adv_reg &= ~REG4_SPEED_MASK; 3195 mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK; 3196 3197 DEBUGOUT("autoneg_advertised %x\n", hw->autoneg_advertised); 3198 3199 /* Do we want to advertise 10 Mb Half Duplex? */ 3200 if (hw->autoneg_advertised & ADVERTISE_10_HALF) { 3201 DEBUGOUT("Advertise 10mb Half duplex\n"); 3202 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS; 3203 } 3204 3205 /* Do we want to advertise 10 Mb Full Duplex? */ 3206 if (hw->autoneg_advertised & ADVERTISE_10_FULL) { 3207 DEBUGOUT("Advertise 10mb Full duplex\n"); 3208 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS; 3209 } 3210 3211 /* Do we want to advertise 100 Mb Half Duplex? */ 3212 if (hw->autoneg_advertised & ADVERTISE_100_HALF) { 3213 DEBUGOUT("Advertise 100mb Half duplex\n"); 3214 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS; 3215 } 3216 3217 /* Do we want to advertise 100 Mb Full Duplex? */ 3218 if (hw->autoneg_advertised & ADVERTISE_100_FULL) { 3219 DEBUGOUT("Advertise 100mb Full duplex\n"); 3220 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS; 3221 } 3222 3223 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */ 3224 if (hw->autoneg_advertised & ADVERTISE_1000_HALF) { 3225 DEBUGOUT 3226 ("Advertise 1000mb Half duplex requested, request denied!\n"); 3227 } 3228 3229 /* Do we want to advertise 1000 Mb Full Duplex? */ 3230 if (hw->autoneg_advertised & ADVERTISE_1000_FULL) { 3231 DEBUGOUT("Advertise 1000mb Full duplex\n"); 3232 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS; 3233 } 3234 3235 /* Check for a software override of the flow control settings, and 3236 * setup the PHY advertisement registers accordingly. If 3237 * auto-negotiation is enabled, then software will have to set the 3238 * "PAUSE" bits to the correct value in the Auto-Negotiation 3239 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation. 3240 * 3241 * The possible values of the "fc" parameter are: 3242 * 0: Flow control is completely disabled 3243 * 1: Rx flow control is enabled (we can receive pause frames 3244 * but not send pause frames). 3245 * 2: Tx flow control is enabled (we can send pause frames 3246 * but we do not support receiving pause frames). 3247 * 3: Both Rx and TX flow control (symmetric) are enabled. 3248 * other: No software override. The flow control configuration 3249 * in the EEPROM is used. 3250 */ 3251 switch (hw->fc) { 3252 case e1000_fc_none: /* 0 */ 3253 /* Flow control (RX & TX) is completely disabled by a 3254 * software over-ride. 3255 */ 3256 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 3257 break; 3258 case e1000_fc_rx_pause: /* 1 */ 3259 /* RX Flow control is enabled, and TX Flow control is 3260 * disabled, by a software over-ride. 3261 */ 3262 /* Since there really isn't a way to advertise that we are 3263 * capable of RX Pause ONLY, we will advertise that we 3264 * support both symmetric and asymmetric RX PAUSE. Later 3265 * (in e1000_config_fc_after_link_up) we will disable the 3266 *hw's ability to send PAUSE frames. 3267 */ 3268 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 3269 break; 3270 case e1000_fc_tx_pause: /* 2 */ 3271 /* TX Flow control is enabled, and RX Flow control is 3272 * disabled, by a software over-ride. 3273 */ 3274 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR; 3275 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE; 3276 break; 3277 case e1000_fc_full: /* 3 */ 3278 /* Flow control (both RX and TX) is enabled by a software 3279 * over-ride. 3280 */ 3281 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 3282 break; 3283 default: 3284 DEBUGOUT("Flow control param set incorrectly\n"); 3285 return -E1000_ERR_CONFIG; 3286 } 3287 3288 ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg); 3289 if (ret_val) 3290 return ret_val; 3291 3292 DEBUGOUT("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); 3293 3294 if (hw->phy_type != e1000_phy_ife) { 3295 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, 3296 mii_1000t_ctrl_reg); 3297 if (ret_val) 3298 return ret_val; 3299 } 3300 3301 return E1000_SUCCESS; 3302 } 3303 3304 /****************************************************************************** 3305 * Sets the collision distance in the Transmit Control register 3306 * 3307 * hw - Struct containing variables accessed by shared code 3308 * 3309 * Link should have been established previously. Reads the speed and duplex 3310 * information from the Device Status register. 3311 ******************************************************************************/ 3312 static void 3313 e1000_config_collision_dist(struct e1000_hw *hw) 3314 { 3315 uint32_t tctl, coll_dist; 3316 3317 DEBUGFUNC(); 3318 3319 if (hw->mac_type < e1000_82543) 3320 coll_dist = E1000_COLLISION_DISTANCE_82542; 3321 else 3322 coll_dist = E1000_COLLISION_DISTANCE; 3323 3324 tctl = E1000_READ_REG(hw, TCTL); 3325 3326 tctl &= ~E1000_TCTL_COLD; 3327 tctl |= coll_dist << E1000_COLD_SHIFT; 3328 3329 E1000_WRITE_REG(hw, TCTL, tctl); 3330 E1000_WRITE_FLUSH(hw); 3331 } 3332 3333 /****************************************************************************** 3334 * Sets MAC speed and duplex settings to reflect the those in the PHY 3335 * 3336 * hw - Struct containing variables accessed by shared code 3337 * mii_reg - data to write to the MII control register 3338 * 3339 * The contents of the PHY register containing the needed information need to 3340 * be passed in. 3341 ******************************************************************************/ 3342 static int 3343 e1000_config_mac_to_phy(struct e1000_hw *hw) 3344 { 3345 uint32_t ctrl; 3346 uint16_t phy_data; 3347 3348 DEBUGFUNC(); 3349 3350 /* Read the Device Control Register and set the bits to Force Speed 3351 * and Duplex. 3352 */ 3353 ctrl = E1000_READ_REG(hw, CTRL); 3354 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 3355 ctrl &= ~(E1000_CTRL_ILOS); 3356 ctrl |= (E1000_CTRL_SPD_SEL); 3357 3358 /* Set up duplex in the Device Control and Transmit Control 3359 * registers depending on negotiated values. 3360 */ 3361 if (e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data) < 0) { 3362 DEBUGOUT("PHY Read Error\n"); 3363 return -E1000_ERR_PHY; 3364 } 3365 if (phy_data & M88E1000_PSSR_DPLX) 3366 ctrl |= E1000_CTRL_FD; 3367 else 3368 ctrl &= ~E1000_CTRL_FD; 3369 3370 e1000_config_collision_dist(hw); 3371 3372 /* Set up speed in the Device Control register depending on 3373 * negotiated values. 3374 */ 3375 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) 3376 ctrl |= E1000_CTRL_SPD_1000; 3377 else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS) 3378 ctrl |= E1000_CTRL_SPD_100; 3379 /* Write the configured values back to the Device Control Reg. */ 3380 E1000_WRITE_REG(hw, CTRL, ctrl); 3381 return 0; 3382 } 3383 3384 /****************************************************************************** 3385 * Forces the MAC's flow control settings. 3386 * 3387 * hw - Struct containing variables accessed by shared code 3388 * 3389 * Sets the TFCE and RFCE bits in the device control register to reflect 3390 * the adapter settings. TFCE and RFCE need to be explicitly set by 3391 * software when a Copper PHY is used because autonegotiation is managed 3392 * by the PHY rather than the MAC. Software must also configure these 3393 * bits when link is forced on a fiber connection. 3394 *****************************************************************************/ 3395 static int 3396 e1000_force_mac_fc(struct e1000_hw *hw) 3397 { 3398 uint32_t ctrl; 3399 3400 DEBUGFUNC(); 3401 3402 /* Get the current configuration of the Device Control Register */ 3403 ctrl = E1000_READ_REG(hw, CTRL); 3404 3405 /* Because we didn't get link via the internal auto-negotiation 3406 * mechanism (we either forced link or we got link via PHY 3407 * auto-neg), we have to manually enable/disable transmit an 3408 * receive flow control. 3409 * 3410 * The "Case" statement below enables/disable flow control 3411 * according to the "hw->fc" parameter. 3412 * 3413 * The possible values of the "fc" parameter are: 3414 * 0: Flow control is completely disabled 3415 * 1: Rx flow control is enabled (we can receive pause 3416 * frames but not send pause frames). 3417 * 2: Tx flow control is enabled (we can send pause frames 3418 * frames but we do not receive pause frames). 3419 * 3: Both Rx and TX flow control (symmetric) is enabled. 3420 * other: No other values should be possible at this point. 3421 */ 3422 3423 switch (hw->fc) { 3424 case e1000_fc_none: 3425 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE)); 3426 break; 3427 case e1000_fc_rx_pause: 3428 ctrl &= (~E1000_CTRL_TFCE); 3429 ctrl |= E1000_CTRL_RFCE; 3430 break; 3431 case e1000_fc_tx_pause: 3432 ctrl &= (~E1000_CTRL_RFCE); 3433 ctrl |= E1000_CTRL_TFCE; 3434 break; 3435 case e1000_fc_full: 3436 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE); 3437 break; 3438 default: 3439 DEBUGOUT("Flow control param set incorrectly\n"); 3440 return -E1000_ERR_CONFIG; 3441 } 3442 3443 /* Disable TX Flow Control for 82542 (rev 2.0) */ 3444 if (hw->mac_type == e1000_82542_rev2_0) 3445 ctrl &= (~E1000_CTRL_TFCE); 3446 3447 E1000_WRITE_REG(hw, CTRL, ctrl); 3448 return 0; 3449 } 3450 3451 /****************************************************************************** 3452 * Configures flow control settings after link is established 3453 * 3454 * hw - Struct containing variables accessed by shared code 3455 * 3456 * Should be called immediately after a valid link has been established. 3457 * Forces MAC flow control settings if link was forced. When in MII/GMII mode 3458 * and autonegotiation is enabled, the MAC flow control settings will be set 3459 * based on the flow control negotiated by the PHY. In TBI mode, the TFCE 3460 * and RFCE bits will be automaticaly set to the negotiated flow control mode. 3461 *****************************************************************************/ 3462 static int32_t 3463 e1000_config_fc_after_link_up(struct e1000_hw *hw) 3464 { 3465 int32_t ret_val; 3466 uint16_t mii_status_reg; 3467 uint16_t mii_nway_adv_reg; 3468 uint16_t mii_nway_lp_ability_reg; 3469 uint16_t speed; 3470 uint16_t duplex; 3471 3472 DEBUGFUNC(); 3473 3474 /* Check for the case where we have fiber media and auto-neg failed 3475 * so we had to force link. In this case, we need to force the 3476 * configuration of the MAC to match the "fc" parameter. 3477 */ 3478 if (((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed)) 3479 || ((hw->media_type == e1000_media_type_internal_serdes) 3480 && (hw->autoneg_failed)) 3481 || ((hw->media_type == e1000_media_type_copper) 3482 && (!hw->autoneg))) { 3483 ret_val = e1000_force_mac_fc(hw); 3484 if (ret_val < 0) { 3485 DEBUGOUT("Error forcing flow control settings\n"); 3486 return ret_val; 3487 } 3488 } 3489 3490 /* Check for the case where we have copper media and auto-neg is 3491 * enabled. In this case, we need to check and see if Auto-Neg 3492 * has completed, and if so, how the PHY and link partner has 3493 * flow control configured. 3494 */ 3495 if (hw->media_type == e1000_media_type_copper) { 3496 /* Read the MII Status Register and check to see if AutoNeg 3497 * has completed. We read this twice because this reg has 3498 * some "sticky" (latched) bits. 3499 */ 3500 if (e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) { 3501 DEBUGOUT("PHY Read Error\n"); 3502 return -E1000_ERR_PHY; 3503 } 3504 if (e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) { 3505 DEBUGOUT("PHY Read Error\n"); 3506 return -E1000_ERR_PHY; 3507 } 3508 3509 if (mii_status_reg & MII_SR_AUTONEG_COMPLETE) { 3510 /* The AutoNeg process has completed, so we now need to 3511 * read both the Auto Negotiation Advertisement Register 3512 * (Address 4) and the Auto_Negotiation Base Page Ability 3513 * Register (Address 5) to determine how flow control was 3514 * negotiated. 3515 */ 3516 if (e1000_read_phy_reg 3517 (hw, PHY_AUTONEG_ADV, &mii_nway_adv_reg) < 0) { 3518 DEBUGOUT("PHY Read Error\n"); 3519 return -E1000_ERR_PHY; 3520 } 3521 if (e1000_read_phy_reg 3522 (hw, PHY_LP_ABILITY, 3523 &mii_nway_lp_ability_reg) < 0) { 3524 DEBUGOUT("PHY Read Error\n"); 3525 return -E1000_ERR_PHY; 3526 } 3527 3528 /* Two bits in the Auto Negotiation Advertisement Register 3529 * (Address 4) and two bits in the Auto Negotiation Base 3530 * Page Ability Register (Address 5) determine flow control 3531 * for both the PHY and the link partner. The following 3532 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25, 3533 * 1999, describes these PAUSE resolution bits and how flow 3534 * control is determined based upon these settings. 3535 * NOTE: DC = Don't Care 3536 * 3537 * LOCAL DEVICE | LINK PARTNER 3538 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution 3539 *-------|---------|-------|---------|-------------------- 3540 * 0 | 0 | DC | DC | e1000_fc_none 3541 * 0 | 1 | 0 | DC | e1000_fc_none 3542 * 0 | 1 | 1 | 0 | e1000_fc_none 3543 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 3544 * 1 | 0 | 0 | DC | e1000_fc_none 3545 * 1 | DC | 1 | DC | e1000_fc_full 3546 * 1 | 1 | 0 | 0 | e1000_fc_none 3547 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 3548 * 3549 */ 3550 /* Are both PAUSE bits set to 1? If so, this implies 3551 * Symmetric Flow Control is enabled at both ends. The 3552 * ASM_DIR bits are irrelevant per the spec. 3553 * 3554 * For Symmetric Flow Control: 3555 * 3556 * LOCAL DEVICE | LINK PARTNER 3557 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 3558 *-------|---------|-------|---------|-------------------- 3559 * 1 | DC | 1 | DC | e1000_fc_full 3560 * 3561 */ 3562 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 3563 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) { 3564 /* Now we need to check if the user selected RX ONLY 3565 * of pause frames. In this case, we had to advertise 3566 * FULL flow control because we could not advertise RX 3567 * ONLY. Hence, we must now check to see if we need to 3568 * turn OFF the TRANSMISSION of PAUSE frames. 3569 */ 3570 if (hw->original_fc == e1000_fc_full) { 3571 hw->fc = e1000_fc_full; 3572 DEBUGOUT("Flow Control = FULL.\r\n"); 3573 } else { 3574 hw->fc = e1000_fc_rx_pause; 3575 DEBUGOUT 3576 ("Flow Control = RX PAUSE frames only.\r\n"); 3577 } 3578 } 3579 /* For receiving PAUSE frames ONLY. 3580 * 3581 * LOCAL DEVICE | LINK PARTNER 3582 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 3583 *-------|---------|-------|---------|-------------------- 3584 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 3585 * 3586 */ 3587 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) && 3588 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 3589 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 3590 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) 3591 { 3592 hw->fc = e1000_fc_tx_pause; 3593 DEBUGOUT 3594 ("Flow Control = TX PAUSE frames only.\r\n"); 3595 } 3596 /* For transmitting PAUSE frames ONLY. 3597 * 3598 * LOCAL DEVICE | LINK PARTNER 3599 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 3600 *-------|---------|-------|---------|-------------------- 3601 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 3602 * 3603 */ 3604 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 3605 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 3606 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 3607 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) 3608 { 3609 hw->fc = e1000_fc_rx_pause; 3610 DEBUGOUT 3611 ("Flow Control = RX PAUSE frames only.\r\n"); 3612 } 3613 /* Per the IEEE spec, at this point flow control should be 3614 * disabled. However, we want to consider that we could 3615 * be connected to a legacy switch that doesn't advertise 3616 * desired flow control, but can be forced on the link 3617 * partner. So if we advertised no flow control, that is 3618 * what we will resolve to. If we advertised some kind of 3619 * receive capability (Rx Pause Only or Full Flow Control) 3620 * and the link partner advertised none, we will configure 3621 * ourselves to enable Rx Flow Control only. We can do 3622 * this safely for two reasons: If the link partner really 3623 * didn't want flow control enabled, and we enable Rx, no 3624 * harm done since we won't be receiving any PAUSE frames 3625 * anyway. If the intent on the link partner was to have 3626 * flow control enabled, then by us enabling RX only, we 3627 * can at least receive pause frames and process them. 3628 * This is a good idea because in most cases, since we are 3629 * predominantly a server NIC, more times than not we will 3630 * be asked to delay transmission of packets than asking 3631 * our link partner to pause transmission of frames. 3632 */ 3633 else if (hw->original_fc == e1000_fc_none || 3634 hw->original_fc == e1000_fc_tx_pause) { 3635 hw->fc = e1000_fc_none; 3636 DEBUGOUT("Flow Control = NONE.\r\n"); 3637 } else { 3638 hw->fc = e1000_fc_rx_pause; 3639 DEBUGOUT 3640 ("Flow Control = RX PAUSE frames only.\r\n"); 3641 } 3642 3643 /* Now we need to do one last check... If we auto- 3644 * negotiated to HALF DUPLEX, flow control should not be 3645 * enabled per IEEE 802.3 spec. 3646 */ 3647 e1000_get_speed_and_duplex(hw, &speed, &duplex); 3648 3649 if (duplex == HALF_DUPLEX) 3650 hw->fc = e1000_fc_none; 3651 3652 /* Now we call a subroutine to actually force the MAC 3653 * controller to use the correct flow control settings. 3654 */ 3655 ret_val = e1000_force_mac_fc(hw); 3656 if (ret_val < 0) { 3657 DEBUGOUT 3658 ("Error forcing flow control settings\n"); 3659 return ret_val; 3660 } 3661 } else { 3662 DEBUGOUT 3663 ("Copper PHY and Auto Neg has not completed.\r\n"); 3664 } 3665 } 3666 return E1000_SUCCESS; 3667 } 3668 3669 /****************************************************************************** 3670 * Checks to see if the link status of the hardware has changed. 3671 * 3672 * hw - Struct containing variables accessed by shared code 3673 * 3674 * Called by any function that needs to check the link status of the adapter. 3675 *****************************************************************************/ 3676 static int 3677 e1000_check_for_link(struct e1000_hw *hw) 3678 { 3679 uint32_t rxcw; 3680 uint32_t ctrl; 3681 uint32_t status; 3682 uint32_t rctl; 3683 uint32_t signal; 3684 int32_t ret_val; 3685 uint16_t phy_data; 3686 uint16_t lp_capability; 3687 3688 DEBUGFUNC(); 3689 3690 /* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be 3691 * set when the optics detect a signal. On older adapters, it will be 3692 * cleared when there is a signal 3693 */ 3694 ctrl = E1000_READ_REG(hw, CTRL); 3695 if ((hw->mac_type > e1000_82544) && !(ctrl & E1000_CTRL_ILOS)) 3696 signal = E1000_CTRL_SWDPIN1; 3697 else 3698 signal = 0; 3699 3700 status = E1000_READ_REG(hw, STATUS); 3701 rxcw = E1000_READ_REG(hw, RXCW); 3702 DEBUGOUT("ctrl: %#08x status %#08x rxcw %#08x\n", ctrl, status, rxcw); 3703 3704 /* If we have a copper PHY then we only want to go out to the PHY 3705 * registers to see if Auto-Neg has completed and/or if our link 3706 * status has changed. The get_link_status flag will be set if we 3707 * receive a Link Status Change interrupt or we have Rx Sequence 3708 * Errors. 3709 */ 3710 if ((hw->media_type == e1000_media_type_copper) && hw->get_link_status) { 3711 /* First we want to see if the MII Status Register reports 3712 * link. If so, then we want to get the current speed/duplex 3713 * of the PHY. 3714 * Read the register twice since the link bit is sticky. 3715 */ 3716 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) { 3717 DEBUGOUT("PHY Read Error\n"); 3718 return -E1000_ERR_PHY; 3719 } 3720 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) { 3721 DEBUGOUT("PHY Read Error\n"); 3722 return -E1000_ERR_PHY; 3723 } 3724 3725 if (phy_data & MII_SR_LINK_STATUS) { 3726 hw->get_link_status = false; 3727 } else { 3728 /* No link detected */ 3729 return -E1000_ERR_NOLINK; 3730 } 3731 3732 /* We have a M88E1000 PHY and Auto-Neg is enabled. If we 3733 * have Si on board that is 82544 or newer, Auto 3734 * Speed Detection takes care of MAC speed/duplex 3735 * configuration. So we only need to configure Collision 3736 * Distance in the MAC. Otherwise, we need to force 3737 * speed/duplex on the MAC to the current PHY speed/duplex 3738 * settings. 3739 */ 3740 if (hw->mac_type >= e1000_82544) 3741 e1000_config_collision_dist(hw); 3742 else { 3743 ret_val = e1000_config_mac_to_phy(hw); 3744 if (ret_val < 0) { 3745 DEBUGOUT 3746 ("Error configuring MAC to PHY settings\n"); 3747 return ret_val; 3748 } 3749 } 3750 3751 /* Configure Flow Control now that Auto-Neg has completed. First, we 3752 * need to restore the desired flow control settings because we may 3753 * have had to re-autoneg with a different link partner. 3754 */ 3755 ret_val = e1000_config_fc_after_link_up(hw); 3756 if (ret_val < 0) { 3757 DEBUGOUT("Error configuring flow control\n"); 3758 return ret_val; 3759 } 3760 3761 /* At this point we know that we are on copper and we have 3762 * auto-negotiated link. These are conditions for checking the link 3763 * parter capability register. We use the link partner capability to 3764 * determine if TBI Compatibility needs to be turned on or off. If 3765 * the link partner advertises any speed in addition to Gigabit, then 3766 * we assume that they are GMII-based, and TBI compatibility is not 3767 * needed. If no other speeds are advertised, we assume the link 3768 * partner is TBI-based, and we turn on TBI Compatibility. 3769 */ 3770 if (hw->tbi_compatibility_en) { 3771 if (e1000_read_phy_reg 3772 (hw, PHY_LP_ABILITY, &lp_capability) < 0) { 3773 DEBUGOUT("PHY Read Error\n"); 3774 return -E1000_ERR_PHY; 3775 } 3776 if (lp_capability & (NWAY_LPAR_10T_HD_CAPS | 3777 NWAY_LPAR_10T_FD_CAPS | 3778 NWAY_LPAR_100TX_HD_CAPS | 3779 NWAY_LPAR_100TX_FD_CAPS | 3780 NWAY_LPAR_100T4_CAPS)) { 3781 /* If our link partner advertises anything in addition to 3782 * gigabit, we do not need to enable TBI compatibility. 3783 */ 3784 if (hw->tbi_compatibility_on) { 3785 /* If we previously were in the mode, turn it off. */ 3786 rctl = E1000_READ_REG(hw, RCTL); 3787 rctl &= ~E1000_RCTL_SBP; 3788 E1000_WRITE_REG(hw, RCTL, rctl); 3789 hw->tbi_compatibility_on = false; 3790 } 3791 } else { 3792 /* If TBI compatibility is was previously off, turn it on. For 3793 * compatibility with a TBI link partner, we will store bad 3794 * packets. Some frames have an additional byte on the end and 3795 * will look like CRC errors to to the hardware. 3796 */ 3797 if (!hw->tbi_compatibility_on) { 3798 hw->tbi_compatibility_on = true; 3799 rctl = E1000_READ_REG(hw, RCTL); 3800 rctl |= E1000_RCTL_SBP; 3801 E1000_WRITE_REG(hw, RCTL, rctl); 3802 } 3803 } 3804 } 3805 } 3806 /* If we don't have link (auto-negotiation failed or link partner cannot 3807 * auto-negotiate), the cable is plugged in (we have signal), and our 3808 * link partner is not trying to auto-negotiate with us (we are receiving 3809 * idles or data), we need to force link up. We also need to give 3810 * auto-negotiation time to complete, in case the cable was just plugged 3811 * in. The autoneg_failed flag does this. 3812 */ 3813 else if ((hw->media_type == e1000_media_type_fiber) && 3814 (!(status & E1000_STATUS_LU)) && 3815 ((ctrl & E1000_CTRL_SWDPIN1) == signal) && 3816 (!(rxcw & E1000_RXCW_C))) { 3817 if (hw->autoneg_failed == 0) { 3818 hw->autoneg_failed = 1; 3819 return 0; 3820 } 3821 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\r\n"); 3822 3823 /* Disable auto-negotiation in the TXCW register */ 3824 E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE)); 3825 3826 /* Force link-up and also force full-duplex. */ 3827 ctrl = E1000_READ_REG(hw, CTRL); 3828 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 3829 E1000_WRITE_REG(hw, CTRL, ctrl); 3830 3831 /* Configure Flow Control after forcing link up. */ 3832 ret_val = e1000_config_fc_after_link_up(hw); 3833 if (ret_val < 0) { 3834 DEBUGOUT("Error configuring flow control\n"); 3835 return ret_val; 3836 } 3837 } 3838 /* If we are forcing link and we are receiving /C/ ordered sets, re-enable 3839 * auto-negotiation in the TXCW register and disable forced link in the 3840 * Device Control register in an attempt to auto-negotiate with our link 3841 * partner. 3842 */ 3843 else if ((hw->media_type == e1000_media_type_fiber) && 3844 (ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { 3845 DEBUGOUT 3846 ("RXing /C/, enable AutoNeg and stop forcing link.\r\n"); 3847 E1000_WRITE_REG(hw, TXCW, hw->txcw); 3848 E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU)); 3849 } 3850 return 0; 3851 } 3852 3853 /****************************************************************************** 3854 * Configure the MAC-to-PHY interface for 10/100Mbps 3855 * 3856 * hw - Struct containing variables accessed by shared code 3857 ******************************************************************************/ 3858 static int32_t 3859 e1000_configure_kmrn_for_10_100(struct e1000_hw *hw, uint16_t duplex) 3860 { 3861 int32_t ret_val = E1000_SUCCESS; 3862 uint32_t tipg; 3863 uint16_t reg_data; 3864 3865 DEBUGFUNC(); 3866 3867 reg_data = E1000_KUMCTRLSTA_HD_CTRL_10_100_DEFAULT; 3868 ret_val = e1000_write_kmrn_reg(hw, 3869 E1000_KUMCTRLSTA_OFFSET_HD_CTRL, reg_data); 3870 if (ret_val) 3871 return ret_val; 3872 3873 /* Configure Transmit Inter-Packet Gap */ 3874 tipg = E1000_READ_REG(hw, TIPG); 3875 tipg &= ~E1000_TIPG_IPGT_MASK; 3876 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_10_100; 3877 E1000_WRITE_REG(hw, TIPG, tipg); 3878 3879 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data); 3880 3881 if (ret_val) 3882 return ret_val; 3883 3884 if (duplex == HALF_DUPLEX) 3885 reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER; 3886 else 3887 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; 3888 3889 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data); 3890 3891 return ret_val; 3892 } 3893 3894 static int32_t 3895 e1000_configure_kmrn_for_1000(struct e1000_hw *hw) 3896 { 3897 int32_t ret_val = E1000_SUCCESS; 3898 uint16_t reg_data; 3899 uint32_t tipg; 3900 3901 DEBUGFUNC(); 3902 3903 reg_data = E1000_KUMCTRLSTA_HD_CTRL_1000_DEFAULT; 3904 ret_val = e1000_write_kmrn_reg(hw, 3905 E1000_KUMCTRLSTA_OFFSET_HD_CTRL, reg_data); 3906 if (ret_val) 3907 return ret_val; 3908 3909 /* Configure Transmit Inter-Packet Gap */ 3910 tipg = E1000_READ_REG(hw, TIPG); 3911 tipg &= ~E1000_TIPG_IPGT_MASK; 3912 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000; 3913 E1000_WRITE_REG(hw, TIPG, tipg); 3914 3915 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data); 3916 3917 if (ret_val) 3918 return ret_val; 3919 3920 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; 3921 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data); 3922 3923 return ret_val; 3924 } 3925 3926 /****************************************************************************** 3927 * Detects the current speed and duplex settings of the hardware. 3928 * 3929 * hw - Struct containing variables accessed by shared code 3930 * speed - Speed of the connection 3931 * duplex - Duplex setting of the connection 3932 *****************************************************************************/ 3933 static int 3934 e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t *speed, 3935 uint16_t *duplex) 3936 { 3937 uint32_t status; 3938 int32_t ret_val; 3939 uint16_t phy_data; 3940 3941 DEBUGFUNC(); 3942 3943 if (hw->mac_type >= e1000_82543) { 3944 status = E1000_READ_REG(hw, STATUS); 3945 if (status & E1000_STATUS_SPEED_1000) { 3946 *speed = SPEED_1000; 3947 DEBUGOUT("1000 Mbs, "); 3948 } else if (status & E1000_STATUS_SPEED_100) { 3949 *speed = SPEED_100; 3950 DEBUGOUT("100 Mbs, "); 3951 } else { 3952 *speed = SPEED_10; 3953 DEBUGOUT("10 Mbs, "); 3954 } 3955 3956 if (status & E1000_STATUS_FD) { 3957 *duplex = FULL_DUPLEX; 3958 DEBUGOUT("Full Duplex\r\n"); 3959 } else { 3960 *duplex = HALF_DUPLEX; 3961 DEBUGOUT(" Half Duplex\r\n"); 3962 } 3963 } else { 3964 DEBUGOUT("1000 Mbs, Full Duplex\r\n"); 3965 *speed = SPEED_1000; 3966 *duplex = FULL_DUPLEX; 3967 } 3968 3969 /* IGP01 PHY may advertise full duplex operation after speed downgrade 3970 * even if it is operating at half duplex. Here we set the duplex 3971 * settings to match the duplex in the link partner's capabilities. 3972 */ 3973 if (hw->phy_type == e1000_phy_igp && hw->speed_downgraded) { 3974 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data); 3975 if (ret_val) 3976 return ret_val; 3977 3978 if (!(phy_data & NWAY_ER_LP_NWAY_CAPS)) 3979 *duplex = HALF_DUPLEX; 3980 else { 3981 ret_val = e1000_read_phy_reg(hw, 3982 PHY_LP_ABILITY, &phy_data); 3983 if (ret_val) 3984 return ret_val; 3985 if ((*speed == SPEED_100 && 3986 !(phy_data & NWAY_LPAR_100TX_FD_CAPS)) 3987 || (*speed == SPEED_10 3988 && !(phy_data & NWAY_LPAR_10T_FD_CAPS))) 3989 *duplex = HALF_DUPLEX; 3990 } 3991 } 3992 3993 if ((hw->mac_type == e1000_80003es2lan) && 3994 (hw->media_type == e1000_media_type_copper)) { 3995 if (*speed == SPEED_1000) 3996 ret_val = e1000_configure_kmrn_for_1000(hw); 3997 else 3998 ret_val = e1000_configure_kmrn_for_10_100(hw, *duplex); 3999 if (ret_val) 4000 return ret_val; 4001 } 4002 return E1000_SUCCESS; 4003 } 4004 4005 /****************************************************************************** 4006 * Blocks until autoneg completes or times out (~4.5 seconds) 4007 * 4008 * hw - Struct containing variables accessed by shared code 4009 ******************************************************************************/ 4010 static int 4011 e1000_wait_autoneg(struct e1000_hw *hw) 4012 { 4013 uint16_t i; 4014 uint16_t phy_data; 4015 4016 DEBUGFUNC(); 4017 DEBUGOUT("Waiting for Auto-Neg to complete.\n"); 4018 4019 /* We will wait for autoneg to complete or timeout to expire. */ 4020 for (i = PHY_AUTO_NEG_TIME; i > 0; i--) { 4021 /* Read the MII Status Register and wait for Auto-Neg 4022 * Complete bit to be set. 4023 */ 4024 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) { 4025 DEBUGOUT("PHY Read Error\n"); 4026 return -E1000_ERR_PHY; 4027 } 4028 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) { 4029 DEBUGOUT("PHY Read Error\n"); 4030 return -E1000_ERR_PHY; 4031 } 4032 if (phy_data & MII_SR_AUTONEG_COMPLETE) { 4033 DEBUGOUT("Auto-Neg complete.\n"); 4034 return 0; 4035 } 4036 mdelay(100); 4037 } 4038 DEBUGOUT("Auto-Neg timedout.\n"); 4039 return -E1000_ERR_TIMEOUT; 4040 } 4041 4042 /****************************************************************************** 4043 * Raises the Management Data Clock 4044 * 4045 * hw - Struct containing variables accessed by shared code 4046 * ctrl - Device control register's current value 4047 ******************************************************************************/ 4048 static void 4049 e1000_raise_mdi_clk(struct e1000_hw *hw, uint32_t * ctrl) 4050 { 4051 /* Raise the clock input to the Management Data Clock (by setting the MDC 4052 * bit), and then delay 2 microseconds. 4053 */ 4054 E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC)); 4055 E1000_WRITE_FLUSH(hw); 4056 udelay(2); 4057 } 4058 4059 /****************************************************************************** 4060 * Lowers the Management Data Clock 4061 * 4062 * hw - Struct containing variables accessed by shared code 4063 * ctrl - Device control register's current value 4064 ******************************************************************************/ 4065 static void 4066 e1000_lower_mdi_clk(struct e1000_hw *hw, uint32_t * ctrl) 4067 { 4068 /* Lower the clock input to the Management Data Clock (by clearing the MDC 4069 * bit), and then delay 2 microseconds. 4070 */ 4071 E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC)); 4072 E1000_WRITE_FLUSH(hw); 4073 udelay(2); 4074 } 4075 4076 /****************************************************************************** 4077 * Shifts data bits out to the PHY 4078 * 4079 * hw - Struct containing variables accessed by shared code 4080 * data - Data to send out to the PHY 4081 * count - Number of bits to shift out 4082 * 4083 * Bits are shifted out in MSB to LSB order. 4084 ******************************************************************************/ 4085 static void 4086 e1000_shift_out_mdi_bits(struct e1000_hw *hw, uint32_t data, uint16_t count) 4087 { 4088 uint32_t ctrl; 4089 uint32_t mask; 4090 4091 /* We need to shift "count" number of bits out to the PHY. So, the value 4092 * in the "data" parameter will be shifted out to the PHY one bit at a 4093 * time. In order to do this, "data" must be broken down into bits. 4094 */ 4095 mask = 0x01; 4096 mask <<= (count - 1); 4097 4098 ctrl = E1000_READ_REG(hw, CTRL); 4099 4100 /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */ 4101 ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR); 4102 4103 while (mask) { 4104 /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and 4105 * then raising and lowering the Management Data Clock. A "0" is 4106 * shifted out to the PHY by setting the MDIO bit to "0" and then 4107 * raising and lowering the clock. 4108 */ 4109 if (data & mask) 4110 ctrl |= E1000_CTRL_MDIO; 4111 else 4112 ctrl &= ~E1000_CTRL_MDIO; 4113 4114 E1000_WRITE_REG(hw, CTRL, ctrl); 4115 E1000_WRITE_FLUSH(hw); 4116 4117 udelay(2); 4118 4119 e1000_raise_mdi_clk(hw, &ctrl); 4120 e1000_lower_mdi_clk(hw, &ctrl); 4121 4122 mask = mask >> 1; 4123 } 4124 } 4125 4126 /****************************************************************************** 4127 * Shifts data bits in from the PHY 4128 * 4129 * hw - Struct containing variables accessed by shared code 4130 * 4131 * Bits are shifted in in MSB to LSB order. 4132 ******************************************************************************/ 4133 static uint16_t 4134 e1000_shift_in_mdi_bits(struct e1000_hw *hw) 4135 { 4136 uint32_t ctrl; 4137 uint16_t data = 0; 4138 uint8_t i; 4139 4140 /* In order to read a register from the PHY, we need to shift in a total 4141 * of 18 bits from the PHY. The first two bit (turnaround) times are used 4142 * to avoid contention on the MDIO pin when a read operation is performed. 4143 * These two bits are ignored by us and thrown away. Bits are "shifted in" 4144 * by raising the input to the Management Data Clock (setting the MDC bit), 4145 * and then reading the value of the MDIO bit. 4146 */ 4147 ctrl = E1000_READ_REG(hw, CTRL); 4148 4149 /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */ 4150 ctrl &= ~E1000_CTRL_MDIO_DIR; 4151 ctrl &= ~E1000_CTRL_MDIO; 4152 4153 E1000_WRITE_REG(hw, CTRL, ctrl); 4154 E1000_WRITE_FLUSH(hw); 4155 4156 /* Raise and Lower the clock before reading in the data. This accounts for 4157 * the turnaround bits. The first clock occurred when we clocked out the 4158 * last bit of the Register Address. 4159 */ 4160 e1000_raise_mdi_clk(hw, &ctrl); 4161 e1000_lower_mdi_clk(hw, &ctrl); 4162 4163 for (data = 0, i = 0; i < 16; i++) { 4164 data = data << 1; 4165 e1000_raise_mdi_clk(hw, &ctrl); 4166 ctrl = E1000_READ_REG(hw, CTRL); 4167 /* Check to see if we shifted in a "1". */ 4168 if (ctrl & E1000_CTRL_MDIO) 4169 data |= 1; 4170 e1000_lower_mdi_clk(hw, &ctrl); 4171 } 4172 4173 e1000_raise_mdi_clk(hw, &ctrl); 4174 e1000_lower_mdi_clk(hw, &ctrl); 4175 4176 return data; 4177 } 4178 4179 /***************************************************************************** 4180 * Reads the value from a PHY register 4181 * 4182 * hw - Struct containing variables accessed by shared code 4183 * reg_addr - address of the PHY register to read 4184 ******************************************************************************/ 4185 static int 4186 e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t * phy_data) 4187 { 4188 uint32_t i; 4189 uint32_t mdic = 0; 4190 const uint32_t phy_addr = 1; 4191 4192 if (reg_addr > MAX_PHY_REG_ADDRESS) { 4193 DEBUGOUT("PHY Address %d is out of range\n", reg_addr); 4194 return -E1000_ERR_PARAM; 4195 } 4196 4197 if (hw->mac_type > e1000_82543) { 4198 /* Set up Op-code, Phy Address, and register address in the MDI 4199 * Control register. The MAC will take care of interfacing with the 4200 * PHY to retrieve the desired data. 4201 */ 4202 mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) | 4203 (phy_addr << E1000_MDIC_PHY_SHIFT) | 4204 (E1000_MDIC_OP_READ)); 4205 4206 E1000_WRITE_REG(hw, MDIC, mdic); 4207 4208 /* Poll the ready bit to see if the MDI read completed */ 4209 for (i = 0; i < 64; i++) { 4210 udelay(10); 4211 mdic = E1000_READ_REG(hw, MDIC); 4212 if (mdic & E1000_MDIC_READY) 4213 break; 4214 } 4215 if (!(mdic & E1000_MDIC_READY)) { 4216 DEBUGOUT("MDI Read did not complete\n"); 4217 return -E1000_ERR_PHY; 4218 } 4219 if (mdic & E1000_MDIC_ERROR) { 4220 DEBUGOUT("MDI Error\n"); 4221 return -E1000_ERR_PHY; 4222 } 4223 *phy_data = (uint16_t) mdic; 4224 } else { 4225 /* We must first send a preamble through the MDIO pin to signal the 4226 * beginning of an MII instruction. This is done by sending 32 4227 * consecutive "1" bits. 4228 */ 4229 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); 4230 4231 /* Now combine the next few fields that are required for a read 4232 * operation. We use this method instead of calling the 4233 * e1000_shift_out_mdi_bits routine five different times. The format of 4234 * a MII read instruction consists of a shift out of 14 bits and is 4235 * defined as follows: 4236 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr> 4237 * followed by a shift in of 18 bits. This first two bits shifted in 4238 * are TurnAround bits used to avoid contention on the MDIO pin when a 4239 * READ operation is performed. These two bits are thrown away 4240 * followed by a shift in of 16 bits which contains the desired data. 4241 */ 4242 mdic = ((reg_addr) | (phy_addr << 5) | 4243 (PHY_OP_READ << 10) | (PHY_SOF << 12)); 4244 4245 e1000_shift_out_mdi_bits(hw, mdic, 14); 4246 4247 /* Now that we've shifted out the read command to the MII, we need to 4248 * "shift in" the 16-bit value (18 total bits) of the requested PHY 4249 * register address. 4250 */ 4251 *phy_data = e1000_shift_in_mdi_bits(hw); 4252 } 4253 return 0; 4254 } 4255 4256 /****************************************************************************** 4257 * Writes a value to a PHY register 4258 * 4259 * hw - Struct containing variables accessed by shared code 4260 * reg_addr - address of the PHY register to write 4261 * data - data to write to the PHY 4262 ******************************************************************************/ 4263 static int 4264 e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t phy_data) 4265 { 4266 uint32_t i; 4267 uint32_t mdic = 0; 4268 const uint32_t phy_addr = 1; 4269 4270 if (reg_addr > MAX_PHY_REG_ADDRESS) { 4271 DEBUGOUT("PHY Address %d is out of range\n", reg_addr); 4272 return -E1000_ERR_PARAM; 4273 } 4274 4275 if (hw->mac_type > e1000_82543) { 4276 /* Set up Op-code, Phy Address, register address, and data intended 4277 * for the PHY register in the MDI Control register. The MAC will take 4278 * care of interfacing with the PHY to send the desired data. 4279 */ 4280 mdic = (((uint32_t) phy_data) | 4281 (reg_addr << E1000_MDIC_REG_SHIFT) | 4282 (phy_addr << E1000_MDIC_PHY_SHIFT) | 4283 (E1000_MDIC_OP_WRITE)); 4284 4285 E1000_WRITE_REG(hw, MDIC, mdic); 4286 4287 /* Poll the ready bit to see if the MDI read completed */ 4288 for (i = 0; i < 64; i++) { 4289 udelay(10); 4290 mdic = E1000_READ_REG(hw, MDIC); 4291 if (mdic & E1000_MDIC_READY) 4292 break; 4293 } 4294 if (!(mdic & E1000_MDIC_READY)) { 4295 DEBUGOUT("MDI Write did not complete\n"); 4296 return -E1000_ERR_PHY; 4297 } 4298 } else { 4299 /* We'll need to use the SW defined pins to shift the write command 4300 * out to the PHY. We first send a preamble to the PHY to signal the 4301 * beginning of the MII instruction. This is done by sending 32 4302 * consecutive "1" bits. 4303 */ 4304 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); 4305 4306 /* Now combine the remaining required fields that will indicate a 4307 * write operation. We use this method instead of calling the 4308 * e1000_shift_out_mdi_bits routine for each field in the command. The 4309 * format of a MII write instruction is as follows: 4310 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>. 4311 */ 4312 mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) | 4313 (PHY_OP_WRITE << 12) | (PHY_SOF << 14)); 4314 mdic <<= 16; 4315 mdic |= (uint32_t) phy_data; 4316 4317 e1000_shift_out_mdi_bits(hw, mdic, 32); 4318 } 4319 return 0; 4320 } 4321 4322 /****************************************************************************** 4323 * Checks if PHY reset is blocked due to SOL/IDER session, for example. 4324 * Returning E1000_BLK_PHY_RESET isn't necessarily an error. But it's up to 4325 * the caller to figure out how to deal with it. 4326 * 4327 * hw - Struct containing variables accessed by shared code 4328 * 4329 * returns: - E1000_BLK_PHY_RESET 4330 * E1000_SUCCESS 4331 * 4332 *****************************************************************************/ 4333 int32_t 4334 e1000_check_phy_reset_block(struct e1000_hw *hw) 4335 { 4336 uint32_t manc = 0; 4337 uint32_t fwsm = 0; 4338 4339 if (hw->mac_type == e1000_ich8lan) { 4340 fwsm = E1000_READ_REG(hw, FWSM); 4341 return (fwsm & E1000_FWSM_RSPCIPHY) ? E1000_SUCCESS 4342 : E1000_BLK_PHY_RESET; 4343 } 4344 4345 if (hw->mac_type > e1000_82547_rev_2) 4346 manc = E1000_READ_REG(hw, MANC); 4347 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ? 4348 E1000_BLK_PHY_RESET : E1000_SUCCESS; 4349 } 4350 4351 /*************************************************************************** 4352 * Checks if the PHY configuration is done 4353 * 4354 * hw: Struct containing variables accessed by shared code 4355 * 4356 * returns: - E1000_ERR_RESET if fail to reset MAC 4357 * E1000_SUCCESS at any other case. 4358 * 4359 ***************************************************************************/ 4360 static int32_t 4361 e1000_get_phy_cfg_done(struct e1000_hw *hw) 4362 { 4363 int32_t timeout = PHY_CFG_TIMEOUT; 4364 uint32_t cfg_mask = E1000_EEPROM_CFG_DONE; 4365 4366 DEBUGFUNC(); 4367 4368 switch (hw->mac_type) { 4369 default: 4370 mdelay(10); 4371 break; 4372 4373 case e1000_80003es2lan: 4374 /* Separate *_CFG_DONE_* bit for each port */ 4375 if (e1000_is_second_port(hw)) 4376 cfg_mask = E1000_EEPROM_CFG_DONE_PORT_1; 4377 /* Fall Through */ 4378 4379 case e1000_82571: 4380 case e1000_82572: 4381 case e1000_igb: 4382 while (timeout) { 4383 if (hw->mac_type == e1000_igb) { 4384 if (E1000_READ_REG(hw, I210_EEMNGCTL) & cfg_mask) 4385 break; 4386 } else { 4387 if (E1000_READ_REG(hw, EEMNGCTL) & cfg_mask) 4388 break; 4389 } 4390 mdelay(1); 4391 timeout--; 4392 } 4393 if (!timeout) { 4394 DEBUGOUT("MNG configuration cycle has not " 4395 "completed.\n"); 4396 return -E1000_ERR_RESET; 4397 } 4398 break; 4399 } 4400 4401 return E1000_SUCCESS; 4402 } 4403 4404 /****************************************************************************** 4405 * Returns the PHY to the power-on reset state 4406 * 4407 * hw - Struct containing variables accessed by shared code 4408 ******************************************************************************/ 4409 int32_t 4410 e1000_phy_hw_reset(struct e1000_hw *hw) 4411 { 4412 uint16_t swfw = E1000_SWFW_PHY0_SM; 4413 uint32_t ctrl, ctrl_ext; 4414 uint32_t led_ctrl; 4415 int32_t ret_val; 4416 4417 DEBUGFUNC(); 4418 4419 /* In the case of the phy reset being blocked, it's not an error, we 4420 * simply return success without performing the reset. */ 4421 ret_val = e1000_check_phy_reset_block(hw); 4422 if (ret_val) 4423 return E1000_SUCCESS; 4424 4425 DEBUGOUT("Resetting Phy...\n"); 4426 4427 if (hw->mac_type > e1000_82543) { 4428 if (e1000_is_second_port(hw)) 4429 swfw = E1000_SWFW_PHY1_SM; 4430 4431 if (e1000_swfw_sync_acquire(hw, swfw)) { 4432 DEBUGOUT("Unable to acquire swfw sync\n"); 4433 return -E1000_ERR_SWFW_SYNC; 4434 } 4435 4436 /* Read the device control register and assert the E1000_CTRL_PHY_RST 4437 * bit. Then, take it out of reset. 4438 */ 4439 ctrl = E1000_READ_REG(hw, CTRL); 4440 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST); 4441 E1000_WRITE_FLUSH(hw); 4442 4443 if (hw->mac_type < e1000_82571) 4444 udelay(10); 4445 else 4446 udelay(100); 4447 4448 E1000_WRITE_REG(hw, CTRL, ctrl); 4449 E1000_WRITE_FLUSH(hw); 4450 4451 if (hw->mac_type >= e1000_82571) 4452 mdelay(10); 4453 4454 } else { 4455 /* Read the Extended Device Control Register, assert the PHY_RESET_DIR 4456 * bit to put the PHY into reset. Then, take it out of reset. 4457 */ 4458 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 4459 ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR; 4460 ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA; 4461 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 4462 E1000_WRITE_FLUSH(hw); 4463 mdelay(10); 4464 ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA; 4465 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 4466 E1000_WRITE_FLUSH(hw); 4467 } 4468 udelay(150); 4469 4470 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { 4471 /* Configure activity LED after PHY reset */ 4472 led_ctrl = E1000_READ_REG(hw, LEDCTL); 4473 led_ctrl &= IGP_ACTIVITY_LED_MASK; 4474 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); 4475 E1000_WRITE_REG(hw, LEDCTL, led_ctrl); 4476 } 4477 4478 e1000_swfw_sync_release(hw, swfw); 4479 4480 /* Wait for FW to finish PHY configuration. */ 4481 ret_val = e1000_get_phy_cfg_done(hw); 4482 if (ret_val != E1000_SUCCESS) 4483 return ret_val; 4484 4485 return ret_val; 4486 } 4487 4488 /****************************************************************************** 4489 * IGP phy init script - initializes the GbE PHY 4490 * 4491 * hw - Struct containing variables accessed by shared code 4492 *****************************************************************************/ 4493 static void 4494 e1000_phy_init_script(struct e1000_hw *hw) 4495 { 4496 uint32_t ret_val; 4497 uint16_t phy_saved_data; 4498 DEBUGFUNC(); 4499 4500 if (hw->phy_init_script) { 4501 mdelay(20); 4502 4503 /* Save off the current value of register 0x2F5B to be 4504 * restored at the end of this routine. */ 4505 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data); 4506 4507 /* Disabled the PHY transmitter */ 4508 e1000_write_phy_reg(hw, 0x2F5B, 0x0003); 4509 4510 mdelay(20); 4511 4512 e1000_write_phy_reg(hw, 0x0000, 0x0140); 4513 4514 mdelay(5); 4515 4516 switch (hw->mac_type) { 4517 case e1000_82541: 4518 case e1000_82547: 4519 e1000_write_phy_reg(hw, 0x1F95, 0x0001); 4520 4521 e1000_write_phy_reg(hw, 0x1F71, 0xBD21); 4522 4523 e1000_write_phy_reg(hw, 0x1F79, 0x0018); 4524 4525 e1000_write_phy_reg(hw, 0x1F30, 0x1600); 4526 4527 e1000_write_phy_reg(hw, 0x1F31, 0x0014); 4528 4529 e1000_write_phy_reg(hw, 0x1F32, 0x161C); 4530 4531 e1000_write_phy_reg(hw, 0x1F94, 0x0003); 4532 4533 e1000_write_phy_reg(hw, 0x1F96, 0x003F); 4534 4535 e1000_write_phy_reg(hw, 0x2010, 0x0008); 4536 break; 4537 4538 case e1000_82541_rev_2: 4539 case e1000_82547_rev_2: 4540 e1000_write_phy_reg(hw, 0x1F73, 0x0099); 4541 break; 4542 default: 4543 break; 4544 } 4545 4546 e1000_write_phy_reg(hw, 0x0000, 0x3300); 4547 4548 mdelay(20); 4549 4550 /* Now enable the transmitter */ 4551 if (!ret_val) 4552 e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data); 4553 4554 if (hw->mac_type == e1000_82547) { 4555 uint16_t fused, fine, coarse; 4556 4557 /* Move to analog registers page */ 4558 e1000_read_phy_reg(hw, 4559 IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused); 4560 4561 if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) { 4562 e1000_read_phy_reg(hw, 4563 IGP01E1000_ANALOG_FUSE_STATUS, &fused); 4564 4565 fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK; 4566 coarse = fused 4567 & IGP01E1000_ANALOG_FUSE_COARSE_MASK; 4568 4569 if (coarse > 4570 IGP01E1000_ANALOG_FUSE_COARSE_THRESH) { 4571 coarse -= 4572 IGP01E1000_ANALOG_FUSE_COARSE_10; 4573 fine -= IGP01E1000_ANALOG_FUSE_FINE_1; 4574 } else if (coarse 4575 == IGP01E1000_ANALOG_FUSE_COARSE_THRESH) 4576 fine -= IGP01E1000_ANALOG_FUSE_FINE_10; 4577 4578 fused = (fused 4579 & IGP01E1000_ANALOG_FUSE_POLY_MASK) | 4580 (fine 4581 & IGP01E1000_ANALOG_FUSE_FINE_MASK) | 4582 (coarse 4583 & IGP01E1000_ANALOG_FUSE_COARSE_MASK); 4584 4585 e1000_write_phy_reg(hw, 4586 IGP01E1000_ANALOG_FUSE_CONTROL, fused); 4587 e1000_write_phy_reg(hw, 4588 IGP01E1000_ANALOG_FUSE_BYPASS, 4589 IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL); 4590 } 4591 } 4592 } 4593 } 4594 4595 /****************************************************************************** 4596 * Resets the PHY 4597 * 4598 * hw - Struct containing variables accessed by shared code 4599 * 4600 * Sets bit 15 of the MII Control register 4601 ******************************************************************************/ 4602 int32_t 4603 e1000_phy_reset(struct e1000_hw *hw) 4604 { 4605 int32_t ret_val; 4606 uint16_t phy_data; 4607 4608 DEBUGFUNC(); 4609 4610 /* In the case of the phy reset being blocked, it's not an error, we 4611 * simply return success without performing the reset. */ 4612 ret_val = e1000_check_phy_reset_block(hw); 4613 if (ret_val) 4614 return E1000_SUCCESS; 4615 4616 switch (hw->phy_type) { 4617 case e1000_phy_igp: 4618 case e1000_phy_igp_2: 4619 case e1000_phy_igp_3: 4620 case e1000_phy_ife: 4621 case e1000_phy_igb: 4622 ret_val = e1000_phy_hw_reset(hw); 4623 if (ret_val) 4624 return ret_val; 4625 break; 4626 default: 4627 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data); 4628 if (ret_val) 4629 return ret_val; 4630 4631 phy_data |= MII_CR_RESET; 4632 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data); 4633 if (ret_val) 4634 return ret_val; 4635 4636 udelay(1); 4637 break; 4638 } 4639 4640 if (hw->phy_type == e1000_phy_igp || hw->phy_type == e1000_phy_igp_2) 4641 e1000_phy_init_script(hw); 4642 4643 return E1000_SUCCESS; 4644 } 4645 4646 static int e1000_set_phy_type (struct e1000_hw *hw) 4647 { 4648 DEBUGFUNC (); 4649 4650 if (hw->mac_type == e1000_undefined) 4651 return -E1000_ERR_PHY_TYPE; 4652 4653 switch (hw->phy_id) { 4654 case M88E1000_E_PHY_ID: 4655 case M88E1000_I_PHY_ID: 4656 case M88E1011_I_PHY_ID: 4657 case M88E1111_I_PHY_ID: 4658 hw->phy_type = e1000_phy_m88; 4659 break; 4660 case IGP01E1000_I_PHY_ID: 4661 if (hw->mac_type == e1000_82541 || 4662 hw->mac_type == e1000_82541_rev_2 || 4663 hw->mac_type == e1000_82547 || 4664 hw->mac_type == e1000_82547_rev_2) { 4665 hw->phy_type = e1000_phy_igp; 4666 break; 4667 } 4668 case IGP03E1000_E_PHY_ID: 4669 hw->phy_type = e1000_phy_igp_3; 4670 break; 4671 case IFE_E_PHY_ID: 4672 case IFE_PLUS_E_PHY_ID: 4673 case IFE_C_E_PHY_ID: 4674 hw->phy_type = e1000_phy_ife; 4675 break; 4676 case GG82563_E_PHY_ID: 4677 if (hw->mac_type == e1000_80003es2lan) { 4678 hw->phy_type = e1000_phy_gg82563; 4679 break; 4680 } 4681 case BME1000_E_PHY_ID: 4682 hw->phy_type = e1000_phy_bm; 4683 break; 4684 case I210_I_PHY_ID: 4685 hw->phy_type = e1000_phy_igb; 4686 break; 4687 /* Fall Through */ 4688 default: 4689 /* Should never have loaded on this device */ 4690 hw->phy_type = e1000_phy_undefined; 4691 return -E1000_ERR_PHY_TYPE; 4692 } 4693 4694 return E1000_SUCCESS; 4695 } 4696 4697 /****************************************************************************** 4698 * Probes the expected PHY address for known PHY IDs 4699 * 4700 * hw - Struct containing variables accessed by shared code 4701 ******************************************************************************/ 4702 static int32_t 4703 e1000_detect_gig_phy(struct e1000_hw *hw) 4704 { 4705 int32_t phy_init_status, ret_val; 4706 uint16_t phy_id_high, phy_id_low; 4707 bool match = false; 4708 4709 DEBUGFUNC(); 4710 4711 /* The 82571 firmware may still be configuring the PHY. In this 4712 * case, we cannot access the PHY until the configuration is done. So 4713 * we explicitly set the PHY values. */ 4714 if (hw->mac_type == e1000_82571 || 4715 hw->mac_type == e1000_82572) { 4716 hw->phy_id = IGP01E1000_I_PHY_ID; 4717 hw->phy_type = e1000_phy_igp_2; 4718 return E1000_SUCCESS; 4719 } 4720 4721 /* ESB-2 PHY reads require e1000_phy_gg82563 to be set because of a 4722 * work- around that forces PHY page 0 to be set or the reads fail. 4723 * The rest of the code in this routine uses e1000_read_phy_reg to 4724 * read the PHY ID. So for ESB-2 we need to have this set so our 4725 * reads won't fail. If the attached PHY is not a e1000_phy_gg82563, 4726 * the routines below will figure this out as well. */ 4727 if (hw->mac_type == e1000_80003es2lan) 4728 hw->phy_type = e1000_phy_gg82563; 4729 4730 /* Read the PHY ID Registers to identify which PHY is onboard. */ 4731 ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high); 4732 if (ret_val) 4733 return ret_val; 4734 4735 hw->phy_id = (uint32_t) (phy_id_high << 16); 4736 udelay(20); 4737 ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low); 4738 if (ret_val) 4739 return ret_val; 4740 4741 hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK); 4742 hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK; 4743 4744 switch (hw->mac_type) { 4745 case e1000_82543: 4746 if (hw->phy_id == M88E1000_E_PHY_ID) 4747 match = true; 4748 break; 4749 case e1000_82544: 4750 if (hw->phy_id == M88E1000_I_PHY_ID) 4751 match = true; 4752 break; 4753 case e1000_82540: 4754 case e1000_82545: 4755 case e1000_82545_rev_3: 4756 case e1000_82546: 4757 case e1000_82546_rev_3: 4758 if (hw->phy_id == M88E1011_I_PHY_ID) 4759 match = true; 4760 break; 4761 case e1000_82541: 4762 case e1000_82541_rev_2: 4763 case e1000_82547: 4764 case e1000_82547_rev_2: 4765 if(hw->phy_id == IGP01E1000_I_PHY_ID) 4766 match = true; 4767 4768 break; 4769 case e1000_82573: 4770 if (hw->phy_id == M88E1111_I_PHY_ID) 4771 match = true; 4772 break; 4773 case e1000_82574: 4774 if (hw->phy_id == BME1000_E_PHY_ID) 4775 match = true; 4776 break; 4777 case e1000_80003es2lan: 4778 if (hw->phy_id == GG82563_E_PHY_ID) 4779 match = true; 4780 break; 4781 case e1000_ich8lan: 4782 if (hw->phy_id == IGP03E1000_E_PHY_ID) 4783 match = true; 4784 if (hw->phy_id == IFE_E_PHY_ID) 4785 match = true; 4786 if (hw->phy_id == IFE_PLUS_E_PHY_ID) 4787 match = true; 4788 if (hw->phy_id == IFE_C_E_PHY_ID) 4789 match = true; 4790 break; 4791 case e1000_igb: 4792 if (hw->phy_id == I210_I_PHY_ID) 4793 match = true; 4794 break; 4795 default: 4796 DEBUGOUT("Invalid MAC type %d\n", hw->mac_type); 4797 return -E1000_ERR_CONFIG; 4798 } 4799 4800 phy_init_status = e1000_set_phy_type(hw); 4801 4802 if ((match) && (phy_init_status == E1000_SUCCESS)) { 4803 DEBUGOUT("PHY ID 0x%X detected\n", hw->phy_id); 4804 return 0; 4805 } 4806 DEBUGOUT("Invalid PHY ID 0x%X\n", hw->phy_id); 4807 return -E1000_ERR_PHY; 4808 } 4809 4810 /***************************************************************************** 4811 * Set media type and TBI compatibility. 4812 * 4813 * hw - Struct containing variables accessed by shared code 4814 * **************************************************************************/ 4815 void 4816 e1000_set_media_type(struct e1000_hw *hw) 4817 { 4818 uint32_t status; 4819 4820 DEBUGFUNC(); 4821 4822 if (hw->mac_type != e1000_82543) { 4823 /* tbi_compatibility is only valid on 82543 */ 4824 hw->tbi_compatibility_en = false; 4825 } 4826 4827 switch (hw->device_id) { 4828 case E1000_DEV_ID_82545GM_SERDES: 4829 case E1000_DEV_ID_82546GB_SERDES: 4830 case E1000_DEV_ID_82571EB_SERDES: 4831 case E1000_DEV_ID_82571EB_SERDES_DUAL: 4832 case E1000_DEV_ID_82571EB_SERDES_QUAD: 4833 case E1000_DEV_ID_82572EI_SERDES: 4834 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT: 4835 hw->media_type = e1000_media_type_internal_serdes; 4836 break; 4837 default: 4838 switch (hw->mac_type) { 4839 case e1000_82542_rev2_0: 4840 case e1000_82542_rev2_1: 4841 hw->media_type = e1000_media_type_fiber; 4842 break; 4843 case e1000_ich8lan: 4844 case e1000_82573: 4845 case e1000_82574: 4846 case e1000_igb: 4847 /* The STATUS_TBIMODE bit is reserved or reused 4848 * for the this device. 4849 */ 4850 hw->media_type = e1000_media_type_copper; 4851 break; 4852 default: 4853 status = E1000_READ_REG(hw, STATUS); 4854 if (status & E1000_STATUS_TBIMODE) { 4855 hw->media_type = e1000_media_type_fiber; 4856 /* tbi_compatibility not valid on fiber */ 4857 hw->tbi_compatibility_en = false; 4858 } else { 4859 hw->media_type = e1000_media_type_copper; 4860 } 4861 break; 4862 } 4863 } 4864 } 4865 4866 /** 4867 * e1000_sw_init - Initialize general software structures (struct e1000_adapter) 4868 * 4869 * e1000_sw_init initializes the Adapter private data structure. 4870 * Fields are initialized based on PCI device information and 4871 * OS network device settings (MTU size). 4872 **/ 4873 4874 static int 4875 e1000_sw_init(struct e1000_hw *hw) 4876 { 4877 int result; 4878 4879 /* PCI config space info */ 4880 pci_read_config_word(hw->pdev, PCI_VENDOR_ID, &hw->vendor_id); 4881 pci_read_config_word(hw->pdev, PCI_DEVICE_ID, &hw->device_id); 4882 pci_read_config_word(hw->pdev, PCI_SUBSYSTEM_VENDOR_ID, 4883 &hw->subsystem_vendor_id); 4884 pci_read_config_word(hw->pdev, PCI_SUBSYSTEM_ID, &hw->subsystem_id); 4885 4886 pci_read_config_byte(hw->pdev, PCI_REVISION_ID, &hw->revision_id); 4887 pci_read_config_word(hw->pdev, PCI_COMMAND, &hw->pci_cmd_word); 4888 4889 /* identify the MAC */ 4890 result = e1000_set_mac_type(hw); 4891 if (result) { 4892 E1000_ERR(hw, "Unknown MAC Type\n"); 4893 return result; 4894 } 4895 4896 switch (hw->mac_type) { 4897 default: 4898 break; 4899 case e1000_82541: 4900 case e1000_82547: 4901 case e1000_82541_rev_2: 4902 case e1000_82547_rev_2: 4903 hw->phy_init_script = 1; 4904 break; 4905 } 4906 4907 /* flow control settings */ 4908 hw->fc_high_water = E1000_FC_HIGH_THRESH; 4909 hw->fc_low_water = E1000_FC_LOW_THRESH; 4910 hw->fc_pause_time = E1000_FC_PAUSE_TIME; 4911 hw->fc_send_xon = 1; 4912 4913 /* Media type - copper or fiber */ 4914 hw->tbi_compatibility_en = true; 4915 e1000_set_media_type(hw); 4916 4917 if (hw->mac_type >= e1000_82543) { 4918 uint32_t status = E1000_READ_REG(hw, STATUS); 4919 4920 if (status & E1000_STATUS_TBIMODE) { 4921 DEBUGOUT("fiber interface\n"); 4922 hw->media_type = e1000_media_type_fiber; 4923 } else { 4924 DEBUGOUT("copper interface\n"); 4925 hw->media_type = e1000_media_type_copper; 4926 } 4927 } else { 4928 hw->media_type = e1000_media_type_fiber; 4929 } 4930 4931 hw->wait_autoneg_complete = true; 4932 if (hw->mac_type < e1000_82543) 4933 hw->report_tx_early = 0; 4934 else 4935 hw->report_tx_early = 1; 4936 4937 return E1000_SUCCESS; 4938 } 4939 4940 void 4941 fill_rx(struct e1000_hw *hw) 4942 { 4943 struct e1000_rx_desc *rd; 4944 unsigned long flush_start, flush_end; 4945 4946 rx_last = rx_tail; 4947 rd = rx_base + rx_tail; 4948 rx_tail = (rx_tail + 1) % 8; 4949 memset(rd, 0, 16); 4950 rd->buffer_addr = cpu_to_le64((unsigned long)packet); 4951 4952 /* 4953 * Make sure there are no stale data in WB over this area, which 4954 * might get written into the memory while the e1000 also writes 4955 * into the same memory area. 4956 */ 4957 invalidate_dcache_range((unsigned long)packet, 4958 (unsigned long)packet + 4096); 4959 /* Dump the DMA descriptor into RAM. */ 4960 flush_start = ((unsigned long)rd) & ~(ARCH_DMA_MINALIGN - 1); 4961 flush_end = flush_start + roundup(sizeof(*rd), ARCH_DMA_MINALIGN); 4962 flush_dcache_range(flush_start, flush_end); 4963 4964 E1000_WRITE_REG(hw, RDT, rx_tail); 4965 } 4966 4967 /** 4968 * e1000_configure_tx - Configure 8254x Transmit Unit after Reset 4969 * @adapter: board private structure 4970 * 4971 * Configure the Tx unit of the MAC after a reset. 4972 **/ 4973 4974 static void 4975 e1000_configure_tx(struct e1000_hw *hw) 4976 { 4977 unsigned long tctl; 4978 unsigned long tipg, tarc; 4979 uint32_t ipgr1, ipgr2; 4980 4981 E1000_WRITE_REG(hw, TDBAL, lower_32_bits((unsigned long)tx_base)); 4982 E1000_WRITE_REG(hw, TDBAH, upper_32_bits((unsigned long)tx_base)); 4983 4984 E1000_WRITE_REG(hw, TDLEN, 128); 4985 4986 /* Setup the HW Tx Head and Tail descriptor pointers */ 4987 E1000_WRITE_REG(hw, TDH, 0); 4988 E1000_WRITE_REG(hw, TDT, 0); 4989 tx_tail = 0; 4990 4991 /* Set the default values for the Tx Inter Packet Gap timer */ 4992 if (hw->mac_type <= e1000_82547_rev_2 && 4993 (hw->media_type == e1000_media_type_fiber || 4994 hw->media_type == e1000_media_type_internal_serdes)) 4995 tipg = DEFAULT_82543_TIPG_IPGT_FIBER; 4996 else 4997 tipg = DEFAULT_82543_TIPG_IPGT_COPPER; 4998 4999 /* Set the default values for the Tx Inter Packet Gap timer */ 5000 switch (hw->mac_type) { 5001 case e1000_82542_rev2_0: 5002 case e1000_82542_rev2_1: 5003 tipg = DEFAULT_82542_TIPG_IPGT; 5004 ipgr1 = DEFAULT_82542_TIPG_IPGR1; 5005 ipgr2 = DEFAULT_82542_TIPG_IPGR2; 5006 break; 5007 case e1000_80003es2lan: 5008 ipgr1 = DEFAULT_82543_TIPG_IPGR1; 5009 ipgr2 = DEFAULT_80003ES2LAN_TIPG_IPGR2; 5010 break; 5011 default: 5012 ipgr1 = DEFAULT_82543_TIPG_IPGR1; 5013 ipgr2 = DEFAULT_82543_TIPG_IPGR2; 5014 break; 5015 } 5016 tipg |= ipgr1 << E1000_TIPG_IPGR1_SHIFT; 5017 tipg |= ipgr2 << E1000_TIPG_IPGR2_SHIFT; 5018 E1000_WRITE_REG(hw, TIPG, tipg); 5019 /* Program the Transmit Control Register */ 5020 tctl = E1000_READ_REG(hw, TCTL); 5021 tctl &= ~E1000_TCTL_CT; 5022 tctl |= E1000_TCTL_EN | E1000_TCTL_PSP | 5023 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); 5024 5025 if (hw->mac_type == e1000_82571 || hw->mac_type == e1000_82572) { 5026 tarc = E1000_READ_REG(hw, TARC0); 5027 /* set the speed mode bit, we'll clear it if we're not at 5028 * gigabit link later */ 5029 /* git bit can be set to 1*/ 5030 } else if (hw->mac_type == e1000_80003es2lan) { 5031 tarc = E1000_READ_REG(hw, TARC0); 5032 tarc |= 1; 5033 E1000_WRITE_REG(hw, TARC0, tarc); 5034 tarc = E1000_READ_REG(hw, TARC1); 5035 tarc |= 1; 5036 E1000_WRITE_REG(hw, TARC1, tarc); 5037 } 5038 5039 5040 e1000_config_collision_dist(hw); 5041 /* Setup Transmit Descriptor Settings for eop descriptor */ 5042 hw->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS; 5043 5044 /* Need to set up RS bit */ 5045 if (hw->mac_type < e1000_82543) 5046 hw->txd_cmd |= E1000_TXD_CMD_RPS; 5047 else 5048 hw->txd_cmd |= E1000_TXD_CMD_RS; 5049 5050 5051 if (hw->mac_type == e1000_igb) { 5052 E1000_WRITE_REG(hw, TCTL_EXT, 0x42 << 10); 5053 5054 uint32_t reg_txdctl = E1000_READ_REG(hw, TXDCTL); 5055 reg_txdctl |= 1 << 25; 5056 E1000_WRITE_REG(hw, TXDCTL, reg_txdctl); 5057 mdelay(20); 5058 } 5059 5060 5061 5062 E1000_WRITE_REG(hw, TCTL, tctl); 5063 5064 5065 } 5066 5067 /** 5068 * e1000_setup_rctl - configure the receive control register 5069 * @adapter: Board private structure 5070 **/ 5071 static void 5072 e1000_setup_rctl(struct e1000_hw *hw) 5073 { 5074 uint32_t rctl; 5075 5076 rctl = E1000_READ_REG(hw, RCTL); 5077 5078 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 5079 5080 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO 5081 | E1000_RCTL_RDMTS_HALF; /* | 5082 (hw.mc_filter_type << E1000_RCTL_MO_SHIFT); */ 5083 5084 if (hw->tbi_compatibility_on == 1) 5085 rctl |= E1000_RCTL_SBP; 5086 else 5087 rctl &= ~E1000_RCTL_SBP; 5088 5089 rctl &= ~(E1000_RCTL_SZ_4096); 5090 rctl |= E1000_RCTL_SZ_2048; 5091 rctl &= ~(E1000_RCTL_BSEX | E1000_RCTL_LPE); 5092 E1000_WRITE_REG(hw, RCTL, rctl); 5093 } 5094 5095 /** 5096 * e1000_configure_rx - Configure 8254x Receive Unit after Reset 5097 * @adapter: board private structure 5098 * 5099 * Configure the Rx unit of the MAC after a reset. 5100 **/ 5101 static void 5102 e1000_configure_rx(struct e1000_hw *hw) 5103 { 5104 unsigned long rctl, ctrl_ext; 5105 rx_tail = 0; 5106 5107 /* make sure receives are disabled while setting up the descriptors */ 5108 rctl = E1000_READ_REG(hw, RCTL); 5109 E1000_WRITE_REG(hw, RCTL, rctl & ~E1000_RCTL_EN); 5110 if (hw->mac_type >= e1000_82540) { 5111 /* Set the interrupt throttling rate. Value is calculated 5112 * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns) */ 5113 #define MAX_INTS_PER_SEC 8000 5114 #define DEFAULT_ITR 1000000000/(MAX_INTS_PER_SEC * 256) 5115 E1000_WRITE_REG(hw, ITR, DEFAULT_ITR); 5116 } 5117 5118 if (hw->mac_type >= e1000_82571) { 5119 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 5120 /* Reset delay timers after every interrupt */ 5121 ctrl_ext |= E1000_CTRL_EXT_INT_TIMER_CLR; 5122 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 5123 E1000_WRITE_FLUSH(hw); 5124 } 5125 /* Setup the Base and Length of the Rx Descriptor Ring */ 5126 E1000_WRITE_REG(hw, RDBAL, lower_32_bits((unsigned long)rx_base)); 5127 E1000_WRITE_REG(hw, RDBAH, upper_32_bits((unsigned long)rx_base)); 5128 5129 E1000_WRITE_REG(hw, RDLEN, 128); 5130 5131 /* Setup the HW Rx Head and Tail Descriptor Pointers */ 5132 E1000_WRITE_REG(hw, RDH, 0); 5133 E1000_WRITE_REG(hw, RDT, 0); 5134 /* Enable Receives */ 5135 5136 if (hw->mac_type == e1000_igb) { 5137 5138 uint32_t reg_rxdctl = E1000_READ_REG(hw, RXDCTL); 5139 reg_rxdctl |= 1 << 25; 5140 E1000_WRITE_REG(hw, RXDCTL, reg_rxdctl); 5141 mdelay(20); 5142 } 5143 5144 E1000_WRITE_REG(hw, RCTL, rctl); 5145 5146 fill_rx(hw); 5147 } 5148 5149 /************************************************************************** 5150 POLL - Wait for a frame 5151 ***************************************************************************/ 5152 static int 5153 _e1000_poll(struct e1000_hw *hw) 5154 { 5155 struct e1000_rx_desc *rd; 5156 unsigned long inval_start, inval_end; 5157 uint32_t len; 5158 5159 /* return true if there's an ethernet packet ready to read */ 5160 rd = rx_base + rx_last; 5161 5162 /* Re-load the descriptor from RAM. */ 5163 inval_start = ((unsigned long)rd) & ~(ARCH_DMA_MINALIGN - 1); 5164 inval_end = inval_start + roundup(sizeof(*rd), ARCH_DMA_MINALIGN); 5165 invalidate_dcache_range(inval_start, inval_end); 5166 5167 if (!(le32_to_cpu(rd->status)) & E1000_RXD_STAT_DD) 5168 return 0; 5169 /* DEBUGOUT("recv: packet len=%d\n", rd->length); */ 5170 /* Packet received, make sure the data are re-loaded from RAM. */ 5171 len = le32_to_cpu(rd->length); 5172 invalidate_dcache_range((unsigned long)packet, 5173 (unsigned long)packet + 5174 roundup(len, ARCH_DMA_MINALIGN)); 5175 return len; 5176 } 5177 5178 static int _e1000_transmit(struct e1000_hw *hw, void *txpacket, int length) 5179 { 5180 void *nv_packet = (void *)txpacket; 5181 struct e1000_tx_desc *txp; 5182 int i = 0; 5183 unsigned long flush_start, flush_end; 5184 5185 txp = tx_base + tx_tail; 5186 tx_tail = (tx_tail + 1) % 8; 5187 5188 txp->buffer_addr = cpu_to_le64(virt_to_bus(hw->pdev, nv_packet)); 5189 txp->lower.data = cpu_to_le32(hw->txd_cmd | length); 5190 txp->upper.data = 0; 5191 5192 /* Dump the packet into RAM so e1000 can pick them. */ 5193 flush_dcache_range((unsigned long)nv_packet, 5194 (unsigned long)nv_packet + 5195 roundup(length, ARCH_DMA_MINALIGN)); 5196 /* Dump the descriptor into RAM as well. */ 5197 flush_start = ((unsigned long)txp) & ~(ARCH_DMA_MINALIGN - 1); 5198 flush_end = flush_start + roundup(sizeof(*txp), ARCH_DMA_MINALIGN); 5199 flush_dcache_range(flush_start, flush_end); 5200 5201 E1000_WRITE_REG(hw, TDT, tx_tail); 5202 5203 E1000_WRITE_FLUSH(hw); 5204 while (1) { 5205 invalidate_dcache_range(flush_start, flush_end); 5206 if (le32_to_cpu(txp->upper.data) & E1000_TXD_STAT_DD) 5207 break; 5208 if (i++ > TOUT_LOOP) { 5209 DEBUGOUT("e1000: tx timeout\n"); 5210 return 0; 5211 } 5212 udelay(10); /* give the nic a chance to write to the register */ 5213 } 5214 return 1; 5215 } 5216 5217 static void 5218 _e1000_disable(struct e1000_hw *hw) 5219 { 5220 /* Turn off the ethernet interface */ 5221 E1000_WRITE_REG(hw, RCTL, 0); 5222 E1000_WRITE_REG(hw, TCTL, 0); 5223 5224 /* Clear the transmit ring */ 5225 E1000_WRITE_REG(hw, TDH, 0); 5226 E1000_WRITE_REG(hw, TDT, 0); 5227 5228 /* Clear the receive ring */ 5229 E1000_WRITE_REG(hw, RDH, 0); 5230 E1000_WRITE_REG(hw, RDT, 0); 5231 5232 /* put the card in its initial state */ 5233 #if 0 5234 E1000_WRITE_REG(hw, CTRL, E1000_CTRL_RST); 5235 #endif 5236 mdelay(10); 5237 } 5238 5239 /*reset function*/ 5240 static inline int 5241 e1000_reset(struct e1000_hw *hw, unsigned char enetaddr[6]) 5242 { 5243 e1000_reset_hw(hw); 5244 if (hw->mac_type >= e1000_82544) 5245 E1000_WRITE_REG(hw, WUC, 0); 5246 5247 return e1000_init_hw(hw, enetaddr); 5248 } 5249 5250 static int 5251 _e1000_init(struct e1000_hw *hw, unsigned char enetaddr[6]) 5252 { 5253 int ret_val = 0; 5254 5255 ret_val = e1000_reset(hw, enetaddr); 5256 if (ret_val < 0) { 5257 if ((ret_val == -E1000_ERR_NOLINK) || 5258 (ret_val == -E1000_ERR_TIMEOUT)) { 5259 E1000_ERR(hw, "Valid Link not detected: %d\n", ret_val); 5260 } else { 5261 E1000_ERR(hw, "Hardware Initialization Failed\n"); 5262 } 5263 return ret_val; 5264 } 5265 e1000_configure_tx(hw); 5266 e1000_setup_rctl(hw); 5267 e1000_configure_rx(hw); 5268 return 0; 5269 } 5270 5271 /****************************************************************************** 5272 * Gets the current PCI bus type of hardware 5273 * 5274 * hw - Struct containing variables accessed by shared code 5275 *****************************************************************************/ 5276 void e1000_get_bus_type(struct e1000_hw *hw) 5277 { 5278 uint32_t status; 5279 5280 switch (hw->mac_type) { 5281 case e1000_82542_rev2_0: 5282 case e1000_82542_rev2_1: 5283 hw->bus_type = e1000_bus_type_pci; 5284 break; 5285 case e1000_82571: 5286 case e1000_82572: 5287 case e1000_82573: 5288 case e1000_82574: 5289 case e1000_80003es2lan: 5290 case e1000_ich8lan: 5291 case e1000_igb: 5292 hw->bus_type = e1000_bus_type_pci_express; 5293 break; 5294 default: 5295 status = E1000_READ_REG(hw, STATUS); 5296 hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ? 5297 e1000_bus_type_pcix : e1000_bus_type_pci; 5298 break; 5299 } 5300 } 5301 5302 #ifndef CONFIG_DM_ETH 5303 /* A list of all registered e1000 devices */ 5304 static LIST_HEAD(e1000_hw_list); 5305 #endif 5306 5307 static int e1000_init_one(struct e1000_hw *hw, int cardnum, pci_dev_t devno, 5308 unsigned char enetaddr[6]) 5309 { 5310 u32 val; 5311 5312 /* Assign the passed-in values */ 5313 hw->pdev = devno; 5314 hw->cardnum = cardnum; 5315 5316 /* Print a debug message with the IO base address */ 5317 pci_read_config_dword(devno, PCI_BASE_ADDRESS_0, &val); 5318 E1000_DBG(hw, "iobase 0x%08x\n", val & 0xfffffff0); 5319 5320 /* Try to enable I/O accesses and bus-mastering */ 5321 val = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; 5322 pci_write_config_dword(devno, PCI_COMMAND, val); 5323 5324 /* Make sure it worked */ 5325 pci_read_config_dword(devno, PCI_COMMAND, &val); 5326 if (!(val & PCI_COMMAND_MEMORY)) { 5327 E1000_ERR(hw, "Can't enable I/O memory\n"); 5328 return -ENOSPC; 5329 } 5330 if (!(val & PCI_COMMAND_MASTER)) { 5331 E1000_ERR(hw, "Can't enable bus-mastering\n"); 5332 return -EPERM; 5333 } 5334 5335 /* Are these variables needed? */ 5336 hw->fc = e1000_fc_default; 5337 hw->original_fc = e1000_fc_default; 5338 hw->autoneg_failed = 0; 5339 hw->autoneg = 1; 5340 hw->get_link_status = true; 5341 #ifndef CONFIG_E1000_NO_NVM 5342 hw->eeprom_semaphore_present = true; 5343 #endif 5344 hw->hw_addr = pci_map_bar(devno, PCI_BASE_ADDRESS_0, 5345 PCI_REGION_MEM); 5346 hw->mac_type = e1000_undefined; 5347 5348 /* MAC and Phy settings */ 5349 if (e1000_sw_init(hw) < 0) { 5350 E1000_ERR(hw, "Software init failed\n"); 5351 return -EIO; 5352 } 5353 if (e1000_check_phy_reset_block(hw)) 5354 E1000_ERR(hw, "PHY Reset is blocked!\n"); 5355 5356 /* Basic init was OK, reset the hardware and allow SPI access */ 5357 e1000_reset_hw(hw); 5358 5359 #ifndef CONFIG_E1000_NO_NVM 5360 /* Validate the EEPROM and get chipset information */ 5361 #if !defined(CONFIG_MVBC_1G) 5362 if (e1000_init_eeprom_params(hw)) { 5363 E1000_ERR(hw, "EEPROM is invalid!\n"); 5364 return -EINVAL; 5365 } 5366 if ((E1000_READ_REG(hw, I210_EECD) & E1000_EECD_FLUPD) && 5367 e1000_validate_eeprom_checksum(hw)) 5368 return -ENXIO; 5369 #endif 5370 e1000_read_mac_addr(hw, enetaddr); 5371 #endif 5372 e1000_get_bus_type(hw); 5373 5374 #ifndef CONFIG_E1000_NO_NVM 5375 printf("e1000: %02x:%02x:%02x:%02x:%02x:%02x\n ", 5376 enetaddr[0], enetaddr[1], enetaddr[2], 5377 enetaddr[3], enetaddr[4], enetaddr[5]); 5378 #else 5379 memset(enetaddr, 0, 6); 5380 printf("e1000: no NVM\n"); 5381 #endif 5382 5383 return 0; 5384 } 5385 5386 /* Put the name of a device in a string */ 5387 static void e1000_name(char *str, int cardnum) 5388 { 5389 sprintf(str, "e1000#%u", cardnum); 5390 } 5391 5392 #ifndef CONFIG_DM_ETH 5393 /************************************************************************** 5394 TRANSMIT - Transmit a frame 5395 ***************************************************************************/ 5396 static int e1000_transmit(struct eth_device *nic, void *txpacket, int length) 5397 { 5398 struct e1000_hw *hw = nic->priv; 5399 5400 return _e1000_transmit(hw, txpacket, length); 5401 } 5402 5403 /************************************************************************** 5404 DISABLE - Turn off ethernet interface 5405 ***************************************************************************/ 5406 static void 5407 e1000_disable(struct eth_device *nic) 5408 { 5409 struct e1000_hw *hw = nic->priv; 5410 5411 _e1000_disable(hw); 5412 } 5413 5414 /************************************************************************** 5415 INIT - set up ethernet interface(s) 5416 ***************************************************************************/ 5417 static int 5418 e1000_init(struct eth_device *nic, bd_t *bis) 5419 { 5420 struct e1000_hw *hw = nic->priv; 5421 5422 return _e1000_init(hw, nic->enetaddr); 5423 } 5424 5425 static int 5426 e1000_poll(struct eth_device *nic) 5427 { 5428 struct e1000_hw *hw = nic->priv; 5429 int len; 5430 5431 len = _e1000_poll(hw); 5432 if (len) { 5433 net_process_received_packet((uchar *)packet, len); 5434 fill_rx(hw); 5435 } 5436 5437 return len ? 1 : 0; 5438 } 5439 5440 /************************************************************************** 5441 PROBE - Look for an adapter, this routine's visible to the outside 5442 You should omit the last argument struct pci_device * for a non-PCI NIC 5443 ***************************************************************************/ 5444 int 5445 e1000_initialize(bd_t * bis) 5446 { 5447 unsigned int i; 5448 pci_dev_t devno; 5449 int ret; 5450 5451 DEBUGFUNC(); 5452 5453 /* Find and probe all the matching PCI devices */ 5454 for (i = 0; (devno = pci_find_devices(e1000_supported, i)) >= 0; i++) { 5455 /* 5456 * These will never get freed due to errors, this allows us to 5457 * perform SPI EEPROM programming from U-boot, for example. 5458 */ 5459 struct eth_device *nic = malloc(sizeof(*nic)); 5460 struct e1000_hw *hw = malloc(sizeof(*hw)); 5461 if (!nic || !hw) { 5462 printf("e1000#%u: Out of Memory!\n", i); 5463 free(nic); 5464 free(hw); 5465 continue; 5466 } 5467 5468 /* Make sure all of the fields are initially zeroed */ 5469 memset(nic, 0, sizeof(*nic)); 5470 memset(hw, 0, sizeof(*hw)); 5471 nic->priv = hw; 5472 5473 /* Generate a card name */ 5474 e1000_name(nic->name, i); 5475 hw->name = nic->name; 5476 5477 ret = e1000_init_one(hw, i, devno, nic->enetaddr); 5478 if (ret) 5479 continue; 5480 list_add_tail(&hw->list_node, &e1000_hw_list); 5481 5482 hw->nic = nic; 5483 5484 /* Set up the function pointers and register the device */ 5485 nic->init = e1000_init; 5486 nic->recv = e1000_poll; 5487 nic->send = e1000_transmit; 5488 nic->halt = e1000_disable; 5489 eth_register(nic); 5490 } 5491 5492 return i; 5493 } 5494 5495 struct e1000_hw *e1000_find_card(unsigned int cardnum) 5496 { 5497 struct e1000_hw *hw; 5498 5499 list_for_each_entry(hw, &e1000_hw_list, list_node) 5500 if (hw->cardnum == cardnum) 5501 return hw; 5502 5503 return NULL; 5504 } 5505 #endif /* !CONFIG_DM_ETH */ 5506 5507 #ifdef CONFIG_CMD_E1000 5508 static int do_e1000(cmd_tbl_t *cmdtp, int flag, 5509 int argc, char * const argv[]) 5510 { 5511 unsigned char *mac = NULL; 5512 #ifdef CONFIG_DM_ETH 5513 struct eth_pdata *plat; 5514 struct udevice *dev; 5515 char name[30]; 5516 int ret; 5517 #else 5518 struct e1000_hw *hw; 5519 #endif 5520 int cardnum; 5521 5522 if (argc < 3) { 5523 cmd_usage(cmdtp); 5524 return 1; 5525 } 5526 5527 /* Make sure we can find the requested e1000 card */ 5528 cardnum = simple_strtoul(argv[1], NULL, 10); 5529 #ifdef CONFIG_DM_ETH 5530 e1000_name(name, cardnum); 5531 ret = uclass_get_device_by_name(UCLASS_ETH, name, &dev); 5532 if (!ret) { 5533 plat = dev_get_platdata(dev); 5534 mac = plat->enetaddr; 5535 } 5536 #else 5537 hw = e1000_find_card(cardnum); 5538 if (hw) 5539 mac = hw->nic->enetaddr; 5540 #endif 5541 if (!mac) { 5542 printf("e1000: ERROR: No such device: e1000#%s\n", argv[1]); 5543 return 1; 5544 } 5545 5546 if (!strcmp(argv[2], "print-mac-address")) { 5547 printf("%02x:%02x:%02x:%02x:%02x:%02x\n", 5548 mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]); 5549 return 0; 5550 } 5551 5552 #ifdef CONFIG_E1000_SPI 5553 /* Handle the "SPI" subcommand */ 5554 if (!strcmp(argv[2], "spi")) 5555 return do_e1000_spi(cmdtp, hw, argc - 3, argv + 3); 5556 #endif 5557 5558 cmd_usage(cmdtp); 5559 return 1; 5560 } 5561 5562 U_BOOT_CMD( 5563 e1000, 7, 0, do_e1000, 5564 "Intel e1000 controller management", 5565 /* */"<card#> print-mac-address\n" 5566 #ifdef CONFIG_E1000_SPI 5567 "e1000 <card#> spi show [<offset> [<length>]]\n" 5568 "e1000 <card#> spi dump <addr> <offset> <length>\n" 5569 "e1000 <card#> spi program <addr> <offset> <length>\n" 5570 "e1000 <card#> spi checksum [update]\n" 5571 #endif 5572 " - Manage the Intel E1000 PCI device" 5573 ); 5574 #endif /* not CONFIG_CMD_E1000 */ 5575 5576 #ifdef CONFIG_DM_ETH 5577 static int e1000_eth_start(struct udevice *dev) 5578 { 5579 struct eth_pdata *plat = dev_get_platdata(dev); 5580 struct e1000_hw *hw = dev_get_priv(dev); 5581 5582 return _e1000_init(hw, plat->enetaddr); 5583 } 5584 5585 static void e1000_eth_stop(struct udevice *dev) 5586 { 5587 struct e1000_hw *hw = dev_get_priv(dev); 5588 5589 _e1000_disable(hw); 5590 } 5591 5592 static int e1000_eth_send(struct udevice *dev, void *packet, int length) 5593 { 5594 struct e1000_hw *hw = dev_get_priv(dev); 5595 int ret; 5596 5597 ret = _e1000_transmit(hw, packet, length); 5598 5599 return ret ? 0 : -ETIMEDOUT; 5600 } 5601 5602 static int e1000_eth_recv(struct udevice *dev, int flags, uchar **packetp) 5603 { 5604 struct e1000_hw *hw = dev_get_priv(dev); 5605 int len; 5606 5607 len = _e1000_poll(hw); 5608 if (len) 5609 *packetp = packet; 5610 5611 return len ? len : -EAGAIN; 5612 } 5613 5614 static int e1000_free_pkt(struct udevice *dev, uchar *packet, int length) 5615 { 5616 struct e1000_hw *hw = dev_get_priv(dev); 5617 5618 fill_rx(hw); 5619 5620 return 0; 5621 } 5622 5623 static int e1000_eth_probe(struct udevice *dev) 5624 { 5625 struct eth_pdata *plat = dev_get_platdata(dev); 5626 struct e1000_hw *hw = dev_get_priv(dev); 5627 int ret; 5628 5629 hw->name = dev->name; 5630 ret = e1000_init_one(hw, trailing_strtol(dev->name), pci_get_bdf(dev), 5631 plat->enetaddr); 5632 if (ret < 0) { 5633 printf(pr_fmt("failed to initialize card: %d\n"), ret); 5634 return ret; 5635 } 5636 5637 return 0; 5638 } 5639 5640 static int e1000_eth_bind(struct udevice *dev) 5641 { 5642 char name[20]; 5643 5644 /* 5645 * A simple way to number the devices. When device tree is used this 5646 * is unnecessary, but when the device is just discovered on the PCI 5647 * bus we need a name. We could instead have the uclass figure out 5648 * which devices are different and number them. 5649 */ 5650 e1000_name(name, num_cards++); 5651 5652 return device_set_name(dev, name); 5653 } 5654 5655 static const struct eth_ops e1000_eth_ops = { 5656 .start = e1000_eth_start, 5657 .send = e1000_eth_send, 5658 .recv = e1000_eth_recv, 5659 .stop = e1000_eth_stop, 5660 .free_pkt = e1000_free_pkt, 5661 }; 5662 5663 static const struct udevice_id e1000_eth_ids[] = { 5664 { .compatible = "intel,e1000" }, 5665 { } 5666 }; 5667 5668 U_BOOT_DRIVER(eth_e1000) = { 5669 .name = "eth_e1000", 5670 .id = UCLASS_ETH, 5671 .of_match = e1000_eth_ids, 5672 .bind = e1000_eth_bind, 5673 .probe = e1000_eth_probe, 5674 .ops = &e1000_eth_ops, 5675 .priv_auto_alloc_size = sizeof(struct e1000_hw), 5676 .platdata_auto_alloc_size = sizeof(struct eth_pdata), 5677 }; 5678 5679 U_BOOT_PCI_DEVICE(eth_e1000, e1000_supported); 5680 #endif 5681