1 /************************************************************************** 2 Intel Pro 1000 for ppcboot/das-u-boot 3 Drivers are port from Intel's Linux driver e1000-4.3.15 4 and from Etherboot pro 1000 driver by mrakes at vivato dot net 5 tested on both gig copper and gig fiber boards 6 ***************************************************************************/ 7 /******************************************************************************* 8 9 10 Copyright(c) 1999 - 2002 Intel Corporation. All rights reserved. 11 12 This program is free software; you can redistribute it and/or modify it 13 under the terms of the GNU General Public License as published by the Free 14 Software Foundation; either version 2 of the License, or (at your option) 15 any later version. 16 17 This program is distributed in the hope that it will be useful, but WITHOUT 18 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 19 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 20 more details. 21 22 You should have received a copy of the GNU General Public License along with 23 this program; if not, write to the Free Software Foundation, Inc., 59 24 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 25 26 The full GNU General Public License is included in this distribution in the 27 file called LICENSE. 28 29 Contact Information: 30 Linux NICS <linux.nics@intel.com> 31 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 32 33 *******************************************************************************/ 34 /* 35 * Copyright (C) Archway Digital Solutions. 36 * 37 * written by Chrsitopher Li <cli at arcyway dot com> or <chrisl at gnuchina dot org> 38 * 2/9/2002 39 * 40 * Copyright (C) Linux Networx. 41 * Massive upgrade to work with the new intel gigabit NICs. 42 * <ebiederman at lnxi dot com> 43 */ 44 45 #include "e1000.h" 46 47 #define TOUT_LOOP 100000 48 49 #undef virt_to_bus 50 #define virt_to_bus(x) ((unsigned long)x) 51 #define bus_to_phys(devno, a) pci_mem_to_phys(devno, a) 52 #define mdelay(n) udelay((n)*1000) 53 54 #define E1000_DEFAULT_PBA 0x00000030 55 56 /* NIC specific static variables go here */ 57 58 static char tx_pool[128 + 16]; 59 static char rx_pool[128 + 16]; 60 static char packet[2096]; 61 62 static struct e1000_tx_desc *tx_base; 63 static struct e1000_rx_desc *rx_base; 64 65 static int tx_tail; 66 static int rx_tail, rx_last; 67 68 static struct pci_device_id supported[] = { 69 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82542}, 70 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82543GC_FIBER}, 71 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82543GC_COPPER}, 72 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544EI_COPPER}, 73 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544EI_FIBER}, 74 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544GC_COPPER}, 75 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544GC_LOM}, 76 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82540EM}, 77 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545EM_COPPER}, 78 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545GM_COPPER}, 79 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_COPPER}, 80 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545EM_FIBER}, 81 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_FIBER}, 82 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82540EM_LOM}, 83 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82541ER}, 84 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82541GI_LF}, 85 }; 86 87 /* Function forward declarations */ 88 static int e1000_setup_link(struct eth_device *nic); 89 static int e1000_setup_fiber_link(struct eth_device *nic); 90 static int e1000_setup_copper_link(struct eth_device *nic); 91 static int e1000_phy_setup_autoneg(struct e1000_hw *hw); 92 static void e1000_config_collision_dist(struct e1000_hw *hw); 93 static int e1000_config_mac_to_phy(struct e1000_hw *hw); 94 static int e1000_config_fc_after_link_up(struct e1000_hw *hw); 95 static int e1000_check_for_link(struct eth_device *nic); 96 static int e1000_wait_autoneg(struct e1000_hw *hw); 97 static void e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t * speed, 98 uint16_t * duplex); 99 static int e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, 100 uint16_t * phy_data); 101 static int e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, 102 uint16_t phy_data); 103 static void e1000_phy_hw_reset(struct e1000_hw *hw); 104 static int e1000_phy_reset(struct e1000_hw *hw); 105 static int e1000_detect_gig_phy(struct e1000_hw *hw); 106 107 #define E1000_WRITE_REG(a, reg, value) (writel((value), ((a)->hw_addr + E1000_##reg))) 108 #define E1000_READ_REG(a, reg) (readl((a)->hw_addr + E1000_##reg)) 109 #define E1000_WRITE_REG_ARRAY(a, reg, offset, value) (\ 110 writel((value), ((a)->hw_addr + E1000_##reg + ((offset) << 2)))) 111 #define E1000_READ_REG_ARRAY(a, reg, offset) ( \ 112 readl((a)->hw_addr + E1000_##reg + ((offset) << 2))) 113 #define E1000_WRITE_FLUSH(a) {uint32_t x; x = E1000_READ_REG(a, STATUS);} 114 115 #ifndef CONFIG_AP1000 /* remove for warnings */ 116 /****************************************************************************** 117 * Raises the EEPROM's clock input. 118 * 119 * hw - Struct containing variables accessed by shared code 120 * eecd - EECD's current value 121 *****************************************************************************/ 122 static void 123 e1000_raise_ee_clk(struct e1000_hw *hw, uint32_t * eecd) 124 { 125 /* Raise the clock input to the EEPROM (by setting the SK bit), and then 126 * wait 50 microseconds. 127 */ 128 *eecd = *eecd | E1000_EECD_SK; 129 E1000_WRITE_REG(hw, EECD, *eecd); 130 E1000_WRITE_FLUSH(hw); 131 udelay(50); 132 } 133 134 /****************************************************************************** 135 * Lowers the EEPROM's clock input. 136 * 137 * hw - Struct containing variables accessed by shared code 138 * eecd - EECD's current value 139 *****************************************************************************/ 140 static void 141 e1000_lower_ee_clk(struct e1000_hw *hw, uint32_t * eecd) 142 { 143 /* Lower the clock input to the EEPROM (by clearing the SK bit), and then 144 * wait 50 microseconds. 145 */ 146 *eecd = *eecd & ~E1000_EECD_SK; 147 E1000_WRITE_REG(hw, EECD, *eecd); 148 E1000_WRITE_FLUSH(hw); 149 udelay(50); 150 } 151 152 /****************************************************************************** 153 * Shift data bits out to the EEPROM. 154 * 155 * hw - Struct containing variables accessed by shared code 156 * data - data to send to the EEPROM 157 * count - number of bits to shift out 158 *****************************************************************************/ 159 static void 160 e1000_shift_out_ee_bits(struct e1000_hw *hw, uint16_t data, uint16_t count) 161 { 162 uint32_t eecd; 163 uint32_t mask; 164 165 /* We need to shift "count" bits out to the EEPROM. So, value in the 166 * "data" parameter will be shifted out to the EEPROM one bit at a time. 167 * In order to do this, "data" must be broken down into bits. 168 */ 169 mask = 0x01 << (count - 1); 170 eecd = E1000_READ_REG(hw, EECD); 171 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI); 172 do { 173 /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1", 174 * and then raising and then lowering the clock (the SK bit controls 175 * the clock input to the EEPROM). A "0" is shifted out to the EEPROM 176 * by setting "DI" to "0" and then raising and then lowering the clock. 177 */ 178 eecd &= ~E1000_EECD_DI; 179 180 if (data & mask) 181 eecd |= E1000_EECD_DI; 182 183 E1000_WRITE_REG(hw, EECD, eecd); 184 E1000_WRITE_FLUSH(hw); 185 186 udelay(50); 187 188 e1000_raise_ee_clk(hw, &eecd); 189 e1000_lower_ee_clk(hw, &eecd); 190 191 mask = mask >> 1; 192 193 } while (mask); 194 195 /* We leave the "DI" bit set to "0" when we leave this routine. */ 196 eecd &= ~E1000_EECD_DI; 197 E1000_WRITE_REG(hw, EECD, eecd); 198 } 199 200 /****************************************************************************** 201 * Shift data bits in from the EEPROM 202 * 203 * hw - Struct containing variables accessed by shared code 204 *****************************************************************************/ 205 static uint16_t 206 e1000_shift_in_ee_bits(struct e1000_hw *hw) 207 { 208 uint32_t eecd; 209 uint32_t i; 210 uint16_t data; 211 212 /* In order to read a register from the EEPROM, we need to shift 16 bits 213 * in from the EEPROM. Bits are "shifted in" by raising the clock input to 214 * the EEPROM (setting the SK bit), and then reading the value of the "DO" 215 * bit. During this "shifting in" process the "DI" bit should always be 216 * clear.. 217 */ 218 219 eecd = E1000_READ_REG(hw, EECD); 220 221 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI); 222 data = 0; 223 224 for (i = 0; i < 16; i++) { 225 data = data << 1; 226 e1000_raise_ee_clk(hw, &eecd); 227 228 eecd = E1000_READ_REG(hw, EECD); 229 230 eecd &= ~(E1000_EECD_DI); 231 if (eecd & E1000_EECD_DO) 232 data |= 1; 233 234 e1000_lower_ee_clk(hw, &eecd); 235 } 236 237 return data; 238 } 239 240 /****************************************************************************** 241 * Prepares EEPROM for access 242 * 243 * hw - Struct containing variables accessed by shared code 244 * 245 * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This 246 * function should be called before issuing a command to the EEPROM. 247 *****************************************************************************/ 248 static void 249 e1000_setup_eeprom(struct e1000_hw *hw) 250 { 251 uint32_t eecd; 252 253 eecd = E1000_READ_REG(hw, EECD); 254 255 /* Clear SK and DI */ 256 eecd &= ~(E1000_EECD_SK | E1000_EECD_DI); 257 E1000_WRITE_REG(hw, EECD, eecd); 258 259 /* Set CS */ 260 eecd |= E1000_EECD_CS; 261 E1000_WRITE_REG(hw, EECD, eecd); 262 } 263 264 /****************************************************************************** 265 * Returns EEPROM to a "standby" state 266 * 267 * hw - Struct containing variables accessed by shared code 268 *****************************************************************************/ 269 static void 270 e1000_standby_eeprom(struct e1000_hw *hw) 271 { 272 uint32_t eecd; 273 274 eecd = E1000_READ_REG(hw, EECD); 275 276 /* Deselct EEPROM */ 277 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); 278 E1000_WRITE_REG(hw, EECD, eecd); 279 E1000_WRITE_FLUSH(hw); 280 udelay(50); 281 282 /* Clock high */ 283 eecd |= E1000_EECD_SK; 284 E1000_WRITE_REG(hw, EECD, eecd); 285 E1000_WRITE_FLUSH(hw); 286 udelay(50); 287 288 /* Select EEPROM */ 289 eecd |= E1000_EECD_CS; 290 E1000_WRITE_REG(hw, EECD, eecd); 291 E1000_WRITE_FLUSH(hw); 292 udelay(50); 293 294 /* Clock low */ 295 eecd &= ~E1000_EECD_SK; 296 E1000_WRITE_REG(hw, EECD, eecd); 297 E1000_WRITE_FLUSH(hw); 298 udelay(50); 299 } 300 301 /****************************************************************************** 302 * Reads a 16 bit word from the EEPROM. 303 * 304 * hw - Struct containing variables accessed by shared code 305 * offset - offset of word in the EEPROM to read 306 * data - word read from the EEPROM 307 *****************************************************************************/ 308 static int 309 e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset, uint16_t * data) 310 { 311 uint32_t eecd; 312 uint32_t i = 0; 313 int large_eeprom = FALSE; 314 315 /* Request EEPROM Access */ 316 if (hw->mac_type > e1000_82544) { 317 eecd = E1000_READ_REG(hw, EECD); 318 if (eecd & E1000_EECD_SIZE) 319 large_eeprom = TRUE; 320 eecd |= E1000_EECD_REQ; 321 E1000_WRITE_REG(hw, EECD, eecd); 322 eecd = E1000_READ_REG(hw, EECD); 323 while ((!(eecd & E1000_EECD_GNT)) && (i < 100)) { 324 i++; 325 udelay(10); 326 eecd = E1000_READ_REG(hw, EECD); 327 } 328 if (!(eecd & E1000_EECD_GNT)) { 329 eecd &= ~E1000_EECD_REQ; 330 E1000_WRITE_REG(hw, EECD, eecd); 331 DEBUGOUT("Could not acquire EEPROM grant\n"); 332 return -E1000_ERR_EEPROM; 333 } 334 } 335 336 /* Prepare the EEPROM for reading */ 337 e1000_setup_eeprom(hw); 338 339 /* Send the READ command (opcode + addr) */ 340 e1000_shift_out_ee_bits(hw, EEPROM_READ_OPCODE, 3); 341 e1000_shift_out_ee_bits(hw, offset, (large_eeprom) ? 8 : 6); 342 343 /* Read the data */ 344 *data = e1000_shift_in_ee_bits(hw); 345 346 /* End this read operation */ 347 e1000_standby_eeprom(hw); 348 349 /* Stop requesting EEPROM access */ 350 if (hw->mac_type > e1000_82544) { 351 eecd = E1000_READ_REG(hw, EECD); 352 eecd &= ~E1000_EECD_REQ; 353 E1000_WRITE_REG(hw, EECD, eecd); 354 } 355 356 return 0; 357 } 358 359 #if 0 360 static void 361 e1000_eeprom_cleanup(struct e1000_hw *hw) 362 { 363 uint32_t eecd; 364 365 eecd = E1000_READ_REG(hw, EECD); 366 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI); 367 E1000_WRITE_REG(hw, EECD, eecd); 368 e1000_raise_ee_clk(hw, &eecd); 369 e1000_lower_ee_clk(hw, &eecd); 370 } 371 372 static uint16_t 373 e1000_wait_eeprom_done(struct e1000_hw *hw) 374 { 375 uint32_t eecd; 376 uint32_t i; 377 378 e1000_standby_eeprom(hw); 379 for (i = 0; i < 200; i++) { 380 eecd = E1000_READ_REG(hw, EECD); 381 if (eecd & E1000_EECD_DO) 382 return (TRUE); 383 udelay(5); 384 } 385 return (FALSE); 386 } 387 388 static int 389 e1000_write_eeprom(struct e1000_hw *hw, uint16_t Reg, uint16_t Data) 390 { 391 uint32_t eecd; 392 int large_eeprom = FALSE; 393 int i = 0; 394 395 /* Request EEPROM Access */ 396 if (hw->mac_type > e1000_82544) { 397 eecd = E1000_READ_REG(hw, EECD); 398 if (eecd & E1000_EECD_SIZE) 399 large_eeprom = TRUE; 400 eecd |= E1000_EECD_REQ; 401 E1000_WRITE_REG(hw, EECD, eecd); 402 eecd = E1000_READ_REG(hw, EECD); 403 while ((!(eecd & E1000_EECD_GNT)) && (i < 100)) { 404 i++; 405 udelay(5); 406 eecd = E1000_READ_REG(hw, EECD); 407 } 408 if (!(eecd & E1000_EECD_GNT)) { 409 eecd &= ~E1000_EECD_REQ; 410 E1000_WRITE_REG(hw, EECD, eecd); 411 DEBUGOUT("Could not acquire EEPROM grant\n"); 412 return FALSE; 413 } 414 } 415 e1000_setup_eeprom(hw); 416 e1000_shift_out_ee_bits(hw, EEPROM_EWEN_OPCODE, 5); 417 e1000_shift_out_ee_bits(hw, Reg, (large_eeprom) ? 6 : 4); 418 e1000_standby_eeprom(hw); 419 e1000_shift_out_ee_bits(hw, EEPROM_WRITE_OPCODE, 3); 420 e1000_shift_out_ee_bits(hw, Reg, (large_eeprom) ? 8 : 6); 421 e1000_shift_out_ee_bits(hw, Data, 16); 422 if (!e1000_wait_eeprom_done(hw)) { 423 return FALSE; 424 } 425 e1000_shift_out_ee_bits(hw, EEPROM_EWDS_OPCODE, 5); 426 e1000_shift_out_ee_bits(hw, Reg, (large_eeprom) ? 6 : 4); 427 e1000_eeprom_cleanup(hw); 428 429 /* Stop requesting EEPROM access */ 430 if (hw->mac_type > e1000_82544) { 431 eecd = E1000_READ_REG(hw, EECD); 432 eecd &= ~E1000_EECD_REQ; 433 E1000_WRITE_REG(hw, EECD, eecd); 434 } 435 i = 0; 436 eecd = E1000_READ_REG(hw, EECD); 437 while (((eecd & E1000_EECD_GNT)) && (i < 500)) { 438 i++; 439 udelay(10); 440 eecd = E1000_READ_REG(hw, EECD); 441 } 442 if ((eecd & E1000_EECD_GNT)) { 443 DEBUGOUT("Could not release EEPROM grant\n"); 444 } 445 return TRUE; 446 } 447 #endif 448 449 /****************************************************************************** 450 * Verifies that the EEPROM has a valid checksum 451 * 452 * hw - Struct containing variables accessed by shared code 453 * 454 * Reads the first 64 16 bit words of the EEPROM and sums the values read. 455 * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is 456 * valid. 457 *****************************************************************************/ 458 static int 459 e1000_validate_eeprom_checksum(struct eth_device *nic) 460 { 461 struct e1000_hw *hw = nic->priv; 462 uint16_t checksum = 0; 463 uint16_t i, eeprom_data; 464 465 DEBUGFUNC(); 466 467 for (i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) { 468 if (e1000_read_eeprom(hw, i, &eeprom_data) < 0) { 469 DEBUGOUT("EEPROM Read Error\n"); 470 return -E1000_ERR_EEPROM; 471 } 472 checksum += eeprom_data; 473 } 474 475 if (checksum == (uint16_t) EEPROM_SUM) { 476 return 0; 477 } else { 478 DEBUGOUT("EEPROM Checksum Invalid\n"); 479 return -E1000_ERR_EEPROM; 480 } 481 } 482 #endif /* #ifndef CONFIG_AP1000 */ 483 484 /****************************************************************************** 485 * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the 486 * second function of dual function devices 487 * 488 * nic - Struct containing variables accessed by shared code 489 *****************************************************************************/ 490 static int 491 e1000_read_mac_addr(struct eth_device *nic) 492 { 493 #ifndef CONFIG_AP1000 494 struct e1000_hw *hw = nic->priv; 495 uint16_t offset; 496 uint16_t eeprom_data; 497 int i; 498 499 DEBUGFUNC(); 500 501 for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) { 502 offset = i >> 1; 503 if (e1000_read_eeprom(hw, offset, &eeprom_data) < 0) { 504 DEBUGOUT("EEPROM Read Error\n"); 505 return -E1000_ERR_EEPROM; 506 } 507 nic->enetaddr[i] = eeprom_data & 0xff; 508 nic->enetaddr[i + 1] = (eeprom_data >> 8) & 0xff; 509 } 510 if ((hw->mac_type == e1000_82546) && 511 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) { 512 /* Invert the last bit if this is the second device */ 513 nic->enetaddr[5] += 1; 514 } 515 #ifdef CONFIG_E1000_FALLBACK_MAC 516 if ( *(u32*)(nic->enetaddr) == 0 || *(u32*)(nic->enetaddr) == ~0 ) { 517 unsigned char fb_mac[NODE_ADDRESS_SIZE] = CONFIG_E1000_FALLBACK_MAC; 518 519 memcpy (nic->enetaddr, fb_mac, NODE_ADDRESS_SIZE); 520 } 521 #endif 522 #else 523 /* 524 * The AP1000's e1000 has no eeprom; the MAC address is stored in the 525 * environment variables. Currently this does not support the addition 526 * of a PMC e1000 card, which is certainly a possibility, so this should 527 * be updated to properly use the env variable only for the onboard e1000 528 */ 529 530 int ii; 531 char *s, *e; 532 533 DEBUGFUNC(); 534 535 s = getenv ("ethaddr"); 536 if (s == NULL) { 537 return -E1000_ERR_EEPROM; 538 } else { 539 for(ii = 0; ii < 6; ii++) { 540 nic->enetaddr[ii] = s ? simple_strtoul (s, &e, 16) : 0; 541 if (s){ 542 s = (*e) ? e + 1 : e; 543 } 544 } 545 } 546 #endif 547 return 0; 548 } 549 550 /****************************************************************************** 551 * Initializes receive address filters. 552 * 553 * hw - Struct containing variables accessed by shared code 554 * 555 * Places the MAC address in receive address register 0 and clears the rest 556 * of the receive addresss registers. Clears the multicast table. Assumes 557 * the receiver is in reset when the routine is called. 558 *****************************************************************************/ 559 static void 560 e1000_init_rx_addrs(struct eth_device *nic) 561 { 562 struct e1000_hw *hw = nic->priv; 563 uint32_t i; 564 uint32_t addr_low; 565 uint32_t addr_high; 566 567 DEBUGFUNC(); 568 569 /* Setup the receive address. */ 570 DEBUGOUT("Programming MAC Address into RAR[0]\n"); 571 addr_low = (nic->enetaddr[0] | 572 (nic->enetaddr[1] << 8) | 573 (nic->enetaddr[2] << 16) | (nic->enetaddr[3] << 24)); 574 575 addr_high = (nic->enetaddr[4] | (nic->enetaddr[5] << 8) | E1000_RAH_AV); 576 577 E1000_WRITE_REG_ARRAY(hw, RA, 0, addr_low); 578 E1000_WRITE_REG_ARRAY(hw, RA, 1, addr_high); 579 580 /* Zero out the other 15 receive addresses. */ 581 DEBUGOUT("Clearing RAR[1-15]\n"); 582 for (i = 1; i < E1000_RAR_ENTRIES; i++) { 583 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0); 584 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0); 585 } 586 } 587 588 /****************************************************************************** 589 * Clears the VLAN filer table 590 * 591 * hw - Struct containing variables accessed by shared code 592 *****************************************************************************/ 593 static void 594 e1000_clear_vfta(struct e1000_hw *hw) 595 { 596 uint32_t offset; 597 598 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) 599 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, 0); 600 } 601 602 /****************************************************************************** 603 * Set the mac type member in the hw struct. 604 * 605 * hw - Struct containing variables accessed by shared code 606 *****************************************************************************/ 607 static int 608 e1000_set_mac_type(struct e1000_hw *hw) 609 { 610 DEBUGFUNC(); 611 612 switch (hw->device_id) { 613 case E1000_DEV_ID_82542: 614 switch (hw->revision_id) { 615 case E1000_82542_2_0_REV_ID: 616 hw->mac_type = e1000_82542_rev2_0; 617 break; 618 case E1000_82542_2_1_REV_ID: 619 hw->mac_type = e1000_82542_rev2_1; 620 break; 621 default: 622 /* Invalid 82542 revision ID */ 623 return -E1000_ERR_MAC_TYPE; 624 } 625 break; 626 case E1000_DEV_ID_82543GC_FIBER: 627 case E1000_DEV_ID_82543GC_COPPER: 628 hw->mac_type = e1000_82543; 629 break; 630 case E1000_DEV_ID_82544EI_COPPER: 631 case E1000_DEV_ID_82544EI_FIBER: 632 case E1000_DEV_ID_82544GC_COPPER: 633 case E1000_DEV_ID_82544GC_LOM: 634 hw->mac_type = e1000_82544; 635 break; 636 case E1000_DEV_ID_82540EM: 637 case E1000_DEV_ID_82540EM_LOM: 638 hw->mac_type = e1000_82540; 639 break; 640 case E1000_DEV_ID_82545EM_COPPER: 641 case E1000_DEV_ID_82545GM_COPPER: 642 case E1000_DEV_ID_82545EM_FIBER: 643 hw->mac_type = e1000_82545; 644 break; 645 case E1000_DEV_ID_82546EB_COPPER: 646 case E1000_DEV_ID_82546EB_FIBER: 647 hw->mac_type = e1000_82546; 648 break; 649 case E1000_DEV_ID_82541ER: 650 case E1000_DEV_ID_82541GI_LF: 651 hw->mac_type = e1000_82541_rev_2; 652 break; 653 default: 654 /* Should never have loaded on this device */ 655 return -E1000_ERR_MAC_TYPE; 656 } 657 return E1000_SUCCESS; 658 } 659 660 /****************************************************************************** 661 * Reset the transmit and receive units; mask and clear all interrupts. 662 * 663 * hw - Struct containing variables accessed by shared code 664 *****************************************************************************/ 665 void 666 e1000_reset_hw(struct e1000_hw *hw) 667 { 668 uint32_t ctrl; 669 uint32_t ctrl_ext; 670 uint32_t icr; 671 uint32_t manc; 672 673 DEBUGFUNC(); 674 675 /* For 82542 (rev 2.0), disable MWI before issuing a device reset */ 676 if (hw->mac_type == e1000_82542_rev2_0) { 677 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n"); 678 pci_write_config_word(hw->pdev, PCI_COMMAND, 679 hw-> 680 pci_cmd_word & ~PCI_COMMAND_INVALIDATE); 681 } 682 683 /* Clear interrupt mask to stop board from generating interrupts */ 684 DEBUGOUT("Masking off all interrupts\n"); 685 E1000_WRITE_REG(hw, IMC, 0xffffffff); 686 687 /* Disable the Transmit and Receive units. Then delay to allow 688 * any pending transactions to complete before we hit the MAC with 689 * the global reset. 690 */ 691 E1000_WRITE_REG(hw, RCTL, 0); 692 E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP); 693 E1000_WRITE_FLUSH(hw); 694 695 /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */ 696 hw->tbi_compatibility_on = FALSE; 697 698 /* Delay to allow any outstanding PCI transactions to complete before 699 * resetting the device 700 */ 701 mdelay(10); 702 703 /* Issue a global reset to the MAC. This will reset the chip's 704 * transmit, receive, DMA, and link units. It will not effect 705 * the current PCI configuration. The global reset bit is self- 706 * clearing, and should clear within a microsecond. 707 */ 708 DEBUGOUT("Issuing a global reset to MAC\n"); 709 ctrl = E1000_READ_REG(hw, CTRL); 710 711 #if 0 712 if (hw->mac_type > e1000_82543) 713 E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST)); 714 else 715 #endif 716 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST)); 717 718 /* Force a reload from the EEPROM if necessary */ 719 if (hw->mac_type < e1000_82540) { 720 /* Wait for reset to complete */ 721 udelay(10); 722 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 723 ctrl_ext |= E1000_CTRL_EXT_EE_RST; 724 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 725 E1000_WRITE_FLUSH(hw); 726 /* Wait for EEPROM reload */ 727 mdelay(2); 728 } else { 729 /* Wait for EEPROM reload (it happens automatically) */ 730 mdelay(4); 731 /* Dissable HW ARPs on ASF enabled adapters */ 732 manc = E1000_READ_REG(hw, MANC); 733 manc &= ~(E1000_MANC_ARP_EN); 734 E1000_WRITE_REG(hw, MANC, manc); 735 } 736 737 /* Clear interrupt mask to stop board from generating interrupts */ 738 DEBUGOUT("Masking off all interrupts\n"); 739 E1000_WRITE_REG(hw, IMC, 0xffffffff); 740 741 /* Clear any pending interrupt events. */ 742 icr = E1000_READ_REG(hw, ICR); 743 744 /* If MWI was previously enabled, reenable it. */ 745 if (hw->mac_type == e1000_82542_rev2_0) { 746 pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word); 747 } 748 } 749 750 /****************************************************************************** 751 * Performs basic configuration of the adapter. 752 * 753 * hw - Struct containing variables accessed by shared code 754 * 755 * Assumes that the controller has previously been reset and is in a 756 * post-reset uninitialized state. Initializes the receive address registers, 757 * multicast table, and VLAN filter table. Calls routines to setup link 758 * configuration and flow control settings. Clears all on-chip counters. Leaves 759 * the transmit and receive units disabled and uninitialized. 760 *****************************************************************************/ 761 static int 762 e1000_init_hw(struct eth_device *nic) 763 { 764 struct e1000_hw *hw = nic->priv; 765 uint32_t ctrl, status; 766 uint32_t i; 767 int32_t ret_val; 768 uint16_t pcix_cmd_word; 769 uint16_t pcix_stat_hi_word; 770 uint16_t cmd_mmrbc; 771 uint16_t stat_mmrbc; 772 e1000_bus_type bus_type = e1000_bus_type_unknown; 773 774 DEBUGFUNC(); 775 #if 0 776 /* Initialize Identification LED */ 777 ret_val = e1000_id_led_init(hw); 778 if (ret_val < 0) { 779 DEBUGOUT("Error Initializing Identification LED\n"); 780 return ret_val; 781 } 782 #endif 783 /* Set the Media Type and exit with error if it is not valid. */ 784 if (hw->mac_type != e1000_82543) { 785 /* tbi_compatibility is only valid on 82543 */ 786 hw->tbi_compatibility_en = FALSE; 787 } 788 789 if (hw->mac_type >= e1000_82543) { 790 status = E1000_READ_REG(hw, STATUS); 791 if (status & E1000_STATUS_TBIMODE) { 792 hw->media_type = e1000_media_type_fiber; 793 /* tbi_compatibility not valid on fiber */ 794 hw->tbi_compatibility_en = FALSE; 795 } else { 796 hw->media_type = e1000_media_type_copper; 797 } 798 } else { 799 /* This is an 82542 (fiber only) */ 800 hw->media_type = e1000_media_type_fiber; 801 } 802 803 /* Disabling VLAN filtering. */ 804 DEBUGOUT("Initializing the IEEE VLAN\n"); 805 E1000_WRITE_REG(hw, VET, 0); 806 807 e1000_clear_vfta(hw); 808 809 /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */ 810 if (hw->mac_type == e1000_82542_rev2_0) { 811 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n"); 812 pci_write_config_word(hw->pdev, PCI_COMMAND, 813 hw-> 814 pci_cmd_word & ~PCI_COMMAND_INVALIDATE); 815 E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST); 816 E1000_WRITE_FLUSH(hw); 817 mdelay(5); 818 } 819 820 /* Setup the receive address. This involves initializing all of the Receive 821 * Address Registers (RARs 0 - 15). 822 */ 823 e1000_init_rx_addrs(nic); 824 825 /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */ 826 if (hw->mac_type == e1000_82542_rev2_0) { 827 E1000_WRITE_REG(hw, RCTL, 0); 828 E1000_WRITE_FLUSH(hw); 829 mdelay(1); 830 pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word); 831 } 832 833 /* Zero out the Multicast HASH table */ 834 DEBUGOUT("Zeroing the MTA\n"); 835 for (i = 0; i < E1000_MC_TBL_SIZE; i++) 836 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0); 837 838 #if 0 839 /* Set the PCI priority bit correctly in the CTRL register. This 840 * determines if the adapter gives priority to receives, or if it 841 * gives equal priority to transmits and receives. 842 */ 843 if (hw->dma_fairness) { 844 ctrl = E1000_READ_REG(hw, CTRL); 845 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR); 846 } 847 #endif 848 if (hw->mac_type >= e1000_82543) { 849 status = E1000_READ_REG(hw, STATUS); 850 bus_type = (status & E1000_STATUS_PCIX_MODE) ? 851 e1000_bus_type_pcix : e1000_bus_type_pci; 852 } 853 /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */ 854 if (bus_type == e1000_bus_type_pcix) { 855 pci_read_config_word(hw->pdev, PCIX_COMMAND_REGISTER, 856 &pcix_cmd_word); 857 pci_read_config_word(hw->pdev, PCIX_STATUS_REGISTER_HI, 858 &pcix_stat_hi_word); 859 cmd_mmrbc = 860 (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) >> 861 PCIX_COMMAND_MMRBC_SHIFT; 862 stat_mmrbc = 863 (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >> 864 PCIX_STATUS_HI_MMRBC_SHIFT; 865 if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K) 866 stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K; 867 if (cmd_mmrbc > stat_mmrbc) { 868 pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK; 869 pcix_cmd_word |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT; 870 pci_write_config_word(hw->pdev, PCIX_COMMAND_REGISTER, 871 pcix_cmd_word); 872 } 873 } 874 875 /* Call a subroutine to configure the link and setup flow control. */ 876 ret_val = e1000_setup_link(nic); 877 878 /* Set the transmit descriptor write-back policy */ 879 if (hw->mac_type > e1000_82544) { 880 ctrl = E1000_READ_REG(hw, TXDCTL); 881 ctrl = 882 (ctrl & ~E1000_TXDCTL_WTHRESH) | 883 E1000_TXDCTL_FULL_TX_DESC_WB; 884 E1000_WRITE_REG(hw, TXDCTL, ctrl); 885 } 886 #if 0 887 /* Clear all of the statistics registers (clear on read). It is 888 * important that we do this after we have tried to establish link 889 * because the symbol error count will increment wildly if there 890 * is no link. 891 */ 892 e1000_clear_hw_cntrs(hw); 893 #endif 894 895 return ret_val; 896 } 897 898 /****************************************************************************** 899 * Configures flow control and link settings. 900 * 901 * hw - Struct containing variables accessed by shared code 902 * 903 * Determines which flow control settings to use. Calls the apropriate media- 904 * specific link configuration function. Configures the flow control settings. 905 * Assuming the adapter has a valid link partner, a valid link should be 906 * established. Assumes the hardware has previously been reset and the 907 * transmitter and receiver are not enabled. 908 *****************************************************************************/ 909 static int 910 e1000_setup_link(struct eth_device *nic) 911 { 912 struct e1000_hw *hw = nic->priv; 913 uint32_t ctrl_ext; 914 int32_t ret_val; 915 uint16_t eeprom_data; 916 917 DEBUGFUNC(); 918 919 #ifndef CONFIG_AP1000 920 /* Read and store word 0x0F of the EEPROM. This word contains bits 921 * that determine the hardware's default PAUSE (flow control) mode, 922 * a bit that determines whether the HW defaults to enabling or 923 * disabling auto-negotiation, and the direction of the 924 * SW defined pins. If there is no SW over-ride of the flow 925 * control setting, then the variable hw->fc will 926 * be initialized based on a value in the EEPROM. 927 */ 928 if (e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, &eeprom_data) < 0) { 929 DEBUGOUT("EEPROM Read Error\n"); 930 return -E1000_ERR_EEPROM; 931 } 932 #else 933 /* we have to hardcode the proper value for our hardware. */ 934 /* this value is for the 82540EM pci card used for prototyping, and it works. */ 935 eeprom_data = 0xb220; 936 #endif 937 938 if (hw->fc == e1000_fc_default) { 939 if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0) 940 hw->fc = e1000_fc_none; 941 else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 942 EEPROM_WORD0F_ASM_DIR) 943 hw->fc = e1000_fc_tx_pause; 944 else 945 hw->fc = e1000_fc_full; 946 } 947 948 /* We want to save off the original Flow Control configuration just 949 * in case we get disconnected and then reconnected into a different 950 * hub or switch with different Flow Control capabilities. 951 */ 952 if (hw->mac_type == e1000_82542_rev2_0) 953 hw->fc &= (~e1000_fc_tx_pause); 954 955 if ((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1)) 956 hw->fc &= (~e1000_fc_rx_pause); 957 958 hw->original_fc = hw->fc; 959 960 DEBUGOUT("After fix-ups FlowControl is now = %x\n", hw->fc); 961 962 /* Take the 4 bits from EEPROM word 0x0F that determine the initial 963 * polarity value for the SW controlled pins, and setup the 964 * Extended Device Control reg with that info. 965 * This is needed because one of the SW controlled pins is used for 966 * signal detection. So this should be done before e1000_setup_pcs_link() 967 * or e1000_phy_setup() is called. 968 */ 969 if (hw->mac_type == e1000_82543) { 970 ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) << 971 SWDPIO__EXT_SHIFT); 972 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 973 } 974 975 /* Call the necessary subroutine to configure the link. */ 976 ret_val = (hw->media_type == e1000_media_type_fiber) ? 977 e1000_setup_fiber_link(nic) : e1000_setup_copper_link(nic); 978 if (ret_val < 0) { 979 return ret_val; 980 } 981 982 /* Initialize the flow control address, type, and PAUSE timer 983 * registers to their default values. This is done even if flow 984 * control is disabled, because it does not hurt anything to 985 * initialize these registers. 986 */ 987 DEBUGOUT 988 ("Initializing the Flow Control address, type and timer regs\n"); 989 990 E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW); 991 E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH); 992 E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE); 993 E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time); 994 995 /* Set the flow control receive threshold registers. Normally, 996 * these registers will be set to a default threshold that may be 997 * adjusted later by the driver's runtime code. However, if the 998 * ability to transmit pause frames in not enabled, then these 999 * registers will be set to 0. 1000 */ 1001 if (!(hw->fc & e1000_fc_tx_pause)) { 1002 E1000_WRITE_REG(hw, FCRTL, 0); 1003 E1000_WRITE_REG(hw, FCRTH, 0); 1004 } else { 1005 /* We need to set up the Receive Threshold high and low water marks 1006 * as well as (optionally) enabling the transmission of XON frames. 1007 */ 1008 if (hw->fc_send_xon) { 1009 E1000_WRITE_REG(hw, FCRTL, 1010 (hw->fc_low_water | E1000_FCRTL_XONE)); 1011 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water); 1012 } else { 1013 E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water); 1014 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water); 1015 } 1016 } 1017 return ret_val; 1018 } 1019 1020 /****************************************************************************** 1021 * Sets up link for a fiber based adapter 1022 * 1023 * hw - Struct containing variables accessed by shared code 1024 * 1025 * Manipulates Physical Coding Sublayer functions in order to configure 1026 * link. Assumes the hardware has been previously reset and the transmitter 1027 * and receiver are not enabled. 1028 *****************************************************************************/ 1029 static int 1030 e1000_setup_fiber_link(struct eth_device *nic) 1031 { 1032 struct e1000_hw *hw = nic->priv; 1033 uint32_t ctrl; 1034 uint32_t status; 1035 uint32_t txcw = 0; 1036 uint32_t i; 1037 uint32_t signal; 1038 int32_t ret_val; 1039 1040 DEBUGFUNC(); 1041 /* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be 1042 * set when the optics detect a signal. On older adapters, it will be 1043 * cleared when there is a signal 1044 */ 1045 ctrl = E1000_READ_REG(hw, CTRL); 1046 if ((hw->mac_type > e1000_82544) && !(ctrl & E1000_CTRL_ILOS)) 1047 signal = E1000_CTRL_SWDPIN1; 1048 else 1049 signal = 0; 1050 1051 printf("signal for %s is %x (ctrl %08x)!!!!\n", nic->name, signal, 1052 ctrl); 1053 /* Take the link out of reset */ 1054 ctrl &= ~(E1000_CTRL_LRST); 1055 1056 e1000_config_collision_dist(hw); 1057 1058 /* Check for a software override of the flow control settings, and setup 1059 * the device accordingly. If auto-negotiation is enabled, then software 1060 * will have to set the "PAUSE" bits to the correct value in the Tranmsit 1061 * Config Word Register (TXCW) and re-start auto-negotiation. However, if 1062 * auto-negotiation is disabled, then software will have to manually 1063 * configure the two flow control enable bits in the CTRL register. 1064 * 1065 * The possible values of the "fc" parameter are: 1066 * 0: Flow control is completely disabled 1067 * 1: Rx flow control is enabled (we can receive pause frames, but 1068 * not send pause frames). 1069 * 2: Tx flow control is enabled (we can send pause frames but we do 1070 * not support receiving pause frames). 1071 * 3: Both Rx and TX flow control (symmetric) are enabled. 1072 */ 1073 switch (hw->fc) { 1074 case e1000_fc_none: 1075 /* Flow control is completely disabled by a software over-ride. */ 1076 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD); 1077 break; 1078 case e1000_fc_rx_pause: 1079 /* RX Flow control is enabled and TX Flow control is disabled by a 1080 * software over-ride. Since there really isn't a way to advertise 1081 * that we are capable of RX Pause ONLY, we will advertise that we 1082 * support both symmetric and asymmetric RX PAUSE. Later, we will 1083 * disable the adapter's ability to send PAUSE frames. 1084 */ 1085 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); 1086 break; 1087 case e1000_fc_tx_pause: 1088 /* TX Flow control is enabled, and RX Flow control is disabled, by a 1089 * software over-ride. 1090 */ 1091 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR); 1092 break; 1093 case e1000_fc_full: 1094 /* Flow control (both RX and TX) is enabled by a software over-ride. */ 1095 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); 1096 break; 1097 default: 1098 DEBUGOUT("Flow control param set incorrectly\n"); 1099 return -E1000_ERR_CONFIG; 1100 break; 1101 } 1102 1103 /* Since auto-negotiation is enabled, take the link out of reset (the link 1104 * will be in reset, because we previously reset the chip). This will 1105 * restart auto-negotiation. If auto-neogtiation is successful then the 1106 * link-up status bit will be set and the flow control enable bits (RFCE 1107 * and TFCE) will be set according to their negotiated value. 1108 */ 1109 DEBUGOUT("Auto-negotiation enabled (%#x)\n", txcw); 1110 1111 E1000_WRITE_REG(hw, TXCW, txcw); 1112 E1000_WRITE_REG(hw, CTRL, ctrl); 1113 E1000_WRITE_FLUSH(hw); 1114 1115 hw->txcw = txcw; 1116 mdelay(1); 1117 1118 /* If we have a signal (the cable is plugged in) then poll for a "Link-Up" 1119 * indication in the Device Status Register. Time-out if a link isn't 1120 * seen in 500 milliseconds seconds (Auto-negotiation should complete in 1121 * less than 500 milliseconds even if the other end is doing it in SW). 1122 */ 1123 if ((E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) { 1124 DEBUGOUT("Looking for Link\n"); 1125 for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) { 1126 mdelay(10); 1127 status = E1000_READ_REG(hw, STATUS); 1128 if (status & E1000_STATUS_LU) 1129 break; 1130 } 1131 if (i == (LINK_UP_TIMEOUT / 10)) { 1132 /* AutoNeg failed to achieve a link, so we'll call 1133 * e1000_check_for_link. This routine will force the link up if we 1134 * detect a signal. This will allow us to communicate with 1135 * non-autonegotiating link partners. 1136 */ 1137 DEBUGOUT("Never got a valid link from auto-neg!!!\n"); 1138 hw->autoneg_failed = 1; 1139 ret_val = e1000_check_for_link(nic); 1140 if (ret_val < 0) { 1141 DEBUGOUT("Error while checking for link\n"); 1142 return ret_val; 1143 } 1144 hw->autoneg_failed = 0; 1145 } else { 1146 hw->autoneg_failed = 0; 1147 DEBUGOUT("Valid Link Found\n"); 1148 } 1149 } else { 1150 DEBUGOUT("No Signal Detected\n"); 1151 return -E1000_ERR_NOLINK; 1152 } 1153 return 0; 1154 } 1155 1156 /****************************************************************************** 1157 * Detects which PHY is present and the speed and duplex 1158 * 1159 * hw - Struct containing variables accessed by shared code 1160 ******************************************************************************/ 1161 static int 1162 e1000_setup_copper_link(struct eth_device *nic) 1163 { 1164 struct e1000_hw *hw = nic->priv; 1165 uint32_t ctrl; 1166 int32_t ret_val; 1167 uint16_t i; 1168 uint16_t phy_data; 1169 1170 DEBUGFUNC(); 1171 1172 ctrl = E1000_READ_REG(hw, CTRL); 1173 /* With 82543, we need to force speed and duplex on the MAC equal to what 1174 * the PHY speed and duplex configuration is. In addition, we need to 1175 * perform a hardware reset on the PHY to take it out of reset. 1176 */ 1177 if (hw->mac_type > e1000_82543) { 1178 ctrl |= E1000_CTRL_SLU; 1179 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1180 E1000_WRITE_REG(hw, CTRL, ctrl); 1181 } else { 1182 ctrl |= 1183 (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU); 1184 E1000_WRITE_REG(hw, CTRL, ctrl); 1185 e1000_phy_hw_reset(hw); 1186 } 1187 1188 /* Make sure we have a valid PHY */ 1189 ret_val = e1000_detect_gig_phy(hw); 1190 if (ret_val < 0) { 1191 DEBUGOUT("Error, did not detect valid phy.\n"); 1192 return ret_val; 1193 } 1194 DEBUGOUT("Phy ID = %x \n", hw->phy_id); 1195 1196 /* Enable CRS on TX. This must be set for half-duplex operation. */ 1197 if (e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data) < 0) { 1198 DEBUGOUT("PHY Read Error\n"); 1199 return -E1000_ERR_PHY; 1200 } 1201 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; 1202 1203 #if 0 1204 /* Options: 1205 * MDI/MDI-X = 0 (default) 1206 * 0 - Auto for all speeds 1207 * 1 - MDI mode 1208 * 2 - MDI-X mode 1209 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) 1210 */ 1211 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 1212 switch (hw->mdix) { 1213 case 1: 1214 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; 1215 break; 1216 case 2: 1217 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; 1218 break; 1219 case 3: 1220 phy_data |= M88E1000_PSCR_AUTO_X_1000T; 1221 break; 1222 case 0: 1223 default: 1224 phy_data |= M88E1000_PSCR_AUTO_X_MODE; 1225 break; 1226 } 1227 #else 1228 phy_data |= M88E1000_PSCR_AUTO_X_MODE; 1229 #endif 1230 1231 #if 0 1232 /* Options: 1233 * disable_polarity_correction = 0 (default) 1234 * Automatic Correction for Reversed Cable Polarity 1235 * 0 - Disabled 1236 * 1 - Enabled 1237 */ 1238 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; 1239 if (hw->disable_polarity_correction == 1) 1240 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL; 1241 #else 1242 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; 1243 #endif 1244 if (e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data) < 0) { 1245 DEBUGOUT("PHY Write Error\n"); 1246 return -E1000_ERR_PHY; 1247 } 1248 1249 /* Force TX_CLK in the Extended PHY Specific Control Register 1250 * to 25MHz clock. 1251 */ 1252 if (e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data) < 0) { 1253 DEBUGOUT("PHY Read Error\n"); 1254 return -E1000_ERR_PHY; 1255 } 1256 phy_data |= M88E1000_EPSCR_TX_CLK_25; 1257 /* Configure Master and Slave downshift values */ 1258 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK | 1259 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK); 1260 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X | 1261 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X); 1262 if (e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data) < 0) { 1263 DEBUGOUT("PHY Write Error\n"); 1264 return -E1000_ERR_PHY; 1265 } 1266 1267 /* SW Reset the PHY so all changes take effect */ 1268 ret_val = e1000_phy_reset(hw); 1269 if (ret_val < 0) { 1270 DEBUGOUT("Error Resetting the PHY\n"); 1271 return ret_val; 1272 } 1273 1274 /* Options: 1275 * autoneg = 1 (default) 1276 * PHY will advertise value(s) parsed from 1277 * autoneg_advertised and fc 1278 * autoneg = 0 1279 * PHY will be set to 10H, 10F, 100H, or 100F 1280 * depending on value parsed from forced_speed_duplex. 1281 */ 1282 1283 /* Is autoneg enabled? This is enabled by default or by software override. 1284 * If so, call e1000_phy_setup_autoneg routine to parse the 1285 * autoneg_advertised and fc options. If autoneg is NOT enabled, then the 1286 * user should have provided a speed/duplex override. If so, then call 1287 * e1000_phy_force_speed_duplex to parse and set this up. 1288 */ 1289 /* Perform some bounds checking on the hw->autoneg_advertised 1290 * parameter. If this variable is zero, then set it to the default. 1291 */ 1292 hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT; 1293 1294 /* If autoneg_advertised is zero, we assume it was not defaulted 1295 * by the calling code so we set to advertise full capability. 1296 */ 1297 if (hw->autoneg_advertised == 0) 1298 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT; 1299 1300 DEBUGOUT("Reconfiguring auto-neg advertisement params\n"); 1301 ret_val = e1000_phy_setup_autoneg(hw); 1302 if (ret_val < 0) { 1303 DEBUGOUT("Error Setting up Auto-Negotiation\n"); 1304 return ret_val; 1305 } 1306 DEBUGOUT("Restarting Auto-Neg\n"); 1307 1308 /* Restart auto-negotiation by setting the Auto Neg Enable bit and 1309 * the Auto Neg Restart bit in the PHY control register. 1310 */ 1311 if (e1000_read_phy_reg(hw, PHY_CTRL, &phy_data) < 0) { 1312 DEBUGOUT("PHY Read Error\n"); 1313 return -E1000_ERR_PHY; 1314 } 1315 phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); 1316 if (e1000_write_phy_reg(hw, PHY_CTRL, phy_data) < 0) { 1317 DEBUGOUT("PHY Write Error\n"); 1318 return -E1000_ERR_PHY; 1319 } 1320 #if 0 1321 /* Does the user want to wait for Auto-Neg to complete here, or 1322 * check at a later time (for example, callback routine). 1323 */ 1324 if (hw->wait_autoneg_complete) { 1325 ret_val = e1000_wait_autoneg(hw); 1326 if (ret_val < 0) { 1327 DEBUGOUT 1328 ("Error while waiting for autoneg to complete\n"); 1329 return ret_val; 1330 } 1331 } 1332 #else 1333 /* If we do not wait for autonegtation to complete I 1334 * do not see a valid link status. 1335 */ 1336 ret_val = e1000_wait_autoneg(hw); 1337 if (ret_val < 0) { 1338 DEBUGOUT("Error while waiting for autoneg to complete\n"); 1339 return ret_val; 1340 } 1341 #endif 1342 1343 /* Check link status. Wait up to 100 microseconds for link to become 1344 * valid. 1345 */ 1346 for (i = 0; i < 10; i++) { 1347 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) { 1348 DEBUGOUT("PHY Read Error\n"); 1349 return -E1000_ERR_PHY; 1350 } 1351 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) { 1352 DEBUGOUT("PHY Read Error\n"); 1353 return -E1000_ERR_PHY; 1354 } 1355 if (phy_data & MII_SR_LINK_STATUS) { 1356 /* We have link, so we need to finish the config process: 1357 * 1) Set up the MAC to the current PHY speed/duplex 1358 * if we are on 82543. If we 1359 * are on newer silicon, we only need to configure 1360 * collision distance in the Transmit Control Register. 1361 * 2) Set up flow control on the MAC to that established with 1362 * the link partner. 1363 */ 1364 if (hw->mac_type >= e1000_82544) { 1365 e1000_config_collision_dist(hw); 1366 } else { 1367 ret_val = e1000_config_mac_to_phy(hw); 1368 if (ret_val < 0) { 1369 DEBUGOUT 1370 ("Error configuring MAC to PHY settings\n"); 1371 return ret_val; 1372 } 1373 } 1374 ret_val = e1000_config_fc_after_link_up(hw); 1375 if (ret_val < 0) { 1376 DEBUGOUT("Error Configuring Flow Control\n"); 1377 return ret_val; 1378 } 1379 DEBUGOUT("Valid link established!!!\n"); 1380 return 0; 1381 } 1382 udelay(10); 1383 } 1384 1385 DEBUGOUT("Unable to establish link!!!\n"); 1386 return -E1000_ERR_NOLINK; 1387 } 1388 1389 /****************************************************************************** 1390 * Configures PHY autoneg and flow control advertisement settings 1391 * 1392 * hw - Struct containing variables accessed by shared code 1393 ******************************************************************************/ 1394 static int 1395 e1000_phy_setup_autoneg(struct e1000_hw *hw) 1396 { 1397 uint16_t mii_autoneg_adv_reg; 1398 uint16_t mii_1000t_ctrl_reg; 1399 1400 DEBUGFUNC(); 1401 1402 /* Read the MII Auto-Neg Advertisement Register (Address 4). */ 1403 if (e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg) < 0) { 1404 DEBUGOUT("PHY Read Error\n"); 1405 return -E1000_ERR_PHY; 1406 } 1407 1408 /* Read the MII 1000Base-T Control Register (Address 9). */ 1409 if (e1000_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg) < 0) { 1410 DEBUGOUT("PHY Read Error\n"); 1411 return -E1000_ERR_PHY; 1412 } 1413 1414 /* Need to parse both autoneg_advertised and fc and set up 1415 * the appropriate PHY registers. First we will parse for 1416 * autoneg_advertised software override. Since we can advertise 1417 * a plethora of combinations, we need to check each bit 1418 * individually. 1419 */ 1420 1421 /* First we clear all the 10/100 mb speed bits in the Auto-Neg 1422 * Advertisement Register (Address 4) and the 1000 mb speed bits in 1423 * the 1000Base-T Control Register (Address 9). 1424 */ 1425 mii_autoneg_adv_reg &= ~REG4_SPEED_MASK; 1426 mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK; 1427 1428 DEBUGOUT("autoneg_advertised %x\n", hw->autoneg_advertised); 1429 1430 /* Do we want to advertise 10 Mb Half Duplex? */ 1431 if (hw->autoneg_advertised & ADVERTISE_10_HALF) { 1432 DEBUGOUT("Advertise 10mb Half duplex\n"); 1433 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS; 1434 } 1435 1436 /* Do we want to advertise 10 Mb Full Duplex? */ 1437 if (hw->autoneg_advertised & ADVERTISE_10_FULL) { 1438 DEBUGOUT("Advertise 10mb Full duplex\n"); 1439 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS; 1440 } 1441 1442 /* Do we want to advertise 100 Mb Half Duplex? */ 1443 if (hw->autoneg_advertised & ADVERTISE_100_HALF) { 1444 DEBUGOUT("Advertise 100mb Half duplex\n"); 1445 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS; 1446 } 1447 1448 /* Do we want to advertise 100 Mb Full Duplex? */ 1449 if (hw->autoneg_advertised & ADVERTISE_100_FULL) { 1450 DEBUGOUT("Advertise 100mb Full duplex\n"); 1451 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS; 1452 } 1453 1454 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */ 1455 if (hw->autoneg_advertised & ADVERTISE_1000_HALF) { 1456 DEBUGOUT 1457 ("Advertise 1000mb Half duplex requested, request denied!\n"); 1458 } 1459 1460 /* Do we want to advertise 1000 Mb Full Duplex? */ 1461 if (hw->autoneg_advertised & ADVERTISE_1000_FULL) { 1462 DEBUGOUT("Advertise 1000mb Full duplex\n"); 1463 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS; 1464 } 1465 1466 /* Check for a software override of the flow control settings, and 1467 * setup the PHY advertisement registers accordingly. If 1468 * auto-negotiation is enabled, then software will have to set the 1469 * "PAUSE" bits to the correct value in the Auto-Negotiation 1470 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation. 1471 * 1472 * The possible values of the "fc" parameter are: 1473 * 0: Flow control is completely disabled 1474 * 1: Rx flow control is enabled (we can receive pause frames 1475 * but not send pause frames). 1476 * 2: Tx flow control is enabled (we can send pause frames 1477 * but we do not support receiving pause frames). 1478 * 3: Both Rx and TX flow control (symmetric) are enabled. 1479 * other: No software override. The flow control configuration 1480 * in the EEPROM is used. 1481 */ 1482 switch (hw->fc) { 1483 case e1000_fc_none: /* 0 */ 1484 /* Flow control (RX & TX) is completely disabled by a 1485 * software over-ride. 1486 */ 1487 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 1488 break; 1489 case e1000_fc_rx_pause: /* 1 */ 1490 /* RX Flow control is enabled, and TX Flow control is 1491 * disabled, by a software over-ride. 1492 */ 1493 /* Since there really isn't a way to advertise that we are 1494 * capable of RX Pause ONLY, we will advertise that we 1495 * support both symmetric and asymmetric RX PAUSE. Later 1496 * (in e1000_config_fc_after_link_up) we will disable the 1497 *hw's ability to send PAUSE frames. 1498 */ 1499 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 1500 break; 1501 case e1000_fc_tx_pause: /* 2 */ 1502 /* TX Flow control is enabled, and RX Flow control is 1503 * disabled, by a software over-ride. 1504 */ 1505 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR; 1506 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE; 1507 break; 1508 case e1000_fc_full: /* 3 */ 1509 /* Flow control (both RX and TX) is enabled by a software 1510 * over-ride. 1511 */ 1512 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 1513 break; 1514 default: 1515 DEBUGOUT("Flow control param set incorrectly\n"); 1516 return -E1000_ERR_CONFIG; 1517 } 1518 1519 if (e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg) < 0) { 1520 DEBUGOUT("PHY Write Error\n"); 1521 return -E1000_ERR_PHY; 1522 } 1523 1524 DEBUGOUT("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); 1525 1526 if (e1000_write_phy_reg(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg) < 0) { 1527 DEBUGOUT("PHY Write Error\n"); 1528 return -E1000_ERR_PHY; 1529 } 1530 return 0; 1531 } 1532 1533 /****************************************************************************** 1534 * Sets the collision distance in the Transmit Control register 1535 * 1536 * hw - Struct containing variables accessed by shared code 1537 * 1538 * Link should have been established previously. Reads the speed and duplex 1539 * information from the Device Status register. 1540 ******************************************************************************/ 1541 static void 1542 e1000_config_collision_dist(struct e1000_hw *hw) 1543 { 1544 uint32_t tctl; 1545 1546 tctl = E1000_READ_REG(hw, TCTL); 1547 1548 tctl &= ~E1000_TCTL_COLD; 1549 tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT; 1550 1551 E1000_WRITE_REG(hw, TCTL, tctl); 1552 E1000_WRITE_FLUSH(hw); 1553 } 1554 1555 /****************************************************************************** 1556 * Sets MAC speed and duplex settings to reflect the those in the PHY 1557 * 1558 * hw - Struct containing variables accessed by shared code 1559 * mii_reg - data to write to the MII control register 1560 * 1561 * The contents of the PHY register containing the needed information need to 1562 * be passed in. 1563 ******************************************************************************/ 1564 static int 1565 e1000_config_mac_to_phy(struct e1000_hw *hw) 1566 { 1567 uint32_t ctrl; 1568 uint16_t phy_data; 1569 1570 DEBUGFUNC(); 1571 1572 /* Read the Device Control Register and set the bits to Force Speed 1573 * and Duplex. 1574 */ 1575 ctrl = E1000_READ_REG(hw, CTRL); 1576 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1577 ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS); 1578 1579 /* Set up duplex in the Device Control and Transmit Control 1580 * registers depending on negotiated values. 1581 */ 1582 if (e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data) < 0) { 1583 DEBUGOUT("PHY Read Error\n"); 1584 return -E1000_ERR_PHY; 1585 } 1586 if (phy_data & M88E1000_PSSR_DPLX) 1587 ctrl |= E1000_CTRL_FD; 1588 else 1589 ctrl &= ~E1000_CTRL_FD; 1590 1591 e1000_config_collision_dist(hw); 1592 1593 /* Set up speed in the Device Control register depending on 1594 * negotiated values. 1595 */ 1596 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) 1597 ctrl |= E1000_CTRL_SPD_1000; 1598 else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS) 1599 ctrl |= E1000_CTRL_SPD_100; 1600 /* Write the configured values back to the Device Control Reg. */ 1601 E1000_WRITE_REG(hw, CTRL, ctrl); 1602 return 0; 1603 } 1604 1605 /****************************************************************************** 1606 * Forces the MAC's flow control settings. 1607 * 1608 * hw - Struct containing variables accessed by shared code 1609 * 1610 * Sets the TFCE and RFCE bits in the device control register to reflect 1611 * the adapter settings. TFCE and RFCE need to be explicitly set by 1612 * software when a Copper PHY is used because autonegotiation is managed 1613 * by the PHY rather than the MAC. Software must also configure these 1614 * bits when link is forced on a fiber connection. 1615 *****************************************************************************/ 1616 static int 1617 e1000_force_mac_fc(struct e1000_hw *hw) 1618 { 1619 uint32_t ctrl; 1620 1621 DEBUGFUNC(); 1622 1623 /* Get the current configuration of the Device Control Register */ 1624 ctrl = E1000_READ_REG(hw, CTRL); 1625 1626 /* Because we didn't get link via the internal auto-negotiation 1627 * mechanism (we either forced link or we got link via PHY 1628 * auto-neg), we have to manually enable/disable transmit an 1629 * receive flow control. 1630 * 1631 * The "Case" statement below enables/disable flow control 1632 * according to the "hw->fc" parameter. 1633 * 1634 * The possible values of the "fc" parameter are: 1635 * 0: Flow control is completely disabled 1636 * 1: Rx flow control is enabled (we can receive pause 1637 * frames but not send pause frames). 1638 * 2: Tx flow control is enabled (we can send pause frames 1639 * frames but we do not receive pause frames). 1640 * 3: Both Rx and TX flow control (symmetric) is enabled. 1641 * other: No other values should be possible at this point. 1642 */ 1643 1644 switch (hw->fc) { 1645 case e1000_fc_none: 1646 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE)); 1647 break; 1648 case e1000_fc_rx_pause: 1649 ctrl &= (~E1000_CTRL_TFCE); 1650 ctrl |= E1000_CTRL_RFCE; 1651 break; 1652 case e1000_fc_tx_pause: 1653 ctrl &= (~E1000_CTRL_RFCE); 1654 ctrl |= E1000_CTRL_TFCE; 1655 break; 1656 case e1000_fc_full: 1657 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE); 1658 break; 1659 default: 1660 DEBUGOUT("Flow control param set incorrectly\n"); 1661 return -E1000_ERR_CONFIG; 1662 } 1663 1664 /* Disable TX Flow Control for 82542 (rev 2.0) */ 1665 if (hw->mac_type == e1000_82542_rev2_0) 1666 ctrl &= (~E1000_CTRL_TFCE); 1667 1668 E1000_WRITE_REG(hw, CTRL, ctrl); 1669 return 0; 1670 } 1671 1672 /****************************************************************************** 1673 * Configures flow control settings after link is established 1674 * 1675 * hw - Struct containing variables accessed by shared code 1676 * 1677 * Should be called immediately after a valid link has been established. 1678 * Forces MAC flow control settings if link was forced. When in MII/GMII mode 1679 * and autonegotiation is enabled, the MAC flow control settings will be set 1680 * based on the flow control negotiated by the PHY. In TBI mode, the TFCE 1681 * and RFCE bits will be automaticaly set to the negotiated flow control mode. 1682 *****************************************************************************/ 1683 static int 1684 e1000_config_fc_after_link_up(struct e1000_hw *hw) 1685 { 1686 int32_t ret_val; 1687 uint16_t mii_status_reg; 1688 uint16_t mii_nway_adv_reg; 1689 uint16_t mii_nway_lp_ability_reg; 1690 uint16_t speed; 1691 uint16_t duplex; 1692 1693 DEBUGFUNC(); 1694 1695 /* Check for the case where we have fiber media and auto-neg failed 1696 * so we had to force link. In this case, we need to force the 1697 * configuration of the MAC to match the "fc" parameter. 1698 */ 1699 if ((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed)) { 1700 ret_val = e1000_force_mac_fc(hw); 1701 if (ret_val < 0) { 1702 DEBUGOUT("Error forcing flow control settings\n"); 1703 return ret_val; 1704 } 1705 } 1706 1707 /* Check for the case where we have copper media and auto-neg is 1708 * enabled. In this case, we need to check and see if Auto-Neg 1709 * has completed, and if so, how the PHY and link partner has 1710 * flow control configured. 1711 */ 1712 if (hw->media_type == e1000_media_type_copper) { 1713 /* Read the MII Status Register and check to see if AutoNeg 1714 * has completed. We read this twice because this reg has 1715 * some "sticky" (latched) bits. 1716 */ 1717 if (e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) { 1718 DEBUGOUT("PHY Read Error \n"); 1719 return -E1000_ERR_PHY; 1720 } 1721 if (e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) { 1722 DEBUGOUT("PHY Read Error \n"); 1723 return -E1000_ERR_PHY; 1724 } 1725 1726 if (mii_status_reg & MII_SR_AUTONEG_COMPLETE) { 1727 /* The AutoNeg process has completed, so we now need to 1728 * read both the Auto Negotiation Advertisement Register 1729 * (Address 4) and the Auto_Negotiation Base Page Ability 1730 * Register (Address 5) to determine how flow control was 1731 * negotiated. 1732 */ 1733 if (e1000_read_phy_reg 1734 (hw, PHY_AUTONEG_ADV, &mii_nway_adv_reg) < 0) { 1735 DEBUGOUT("PHY Read Error\n"); 1736 return -E1000_ERR_PHY; 1737 } 1738 if (e1000_read_phy_reg 1739 (hw, PHY_LP_ABILITY, 1740 &mii_nway_lp_ability_reg) < 0) { 1741 DEBUGOUT("PHY Read Error\n"); 1742 return -E1000_ERR_PHY; 1743 } 1744 1745 /* Two bits in the Auto Negotiation Advertisement Register 1746 * (Address 4) and two bits in the Auto Negotiation Base 1747 * Page Ability Register (Address 5) determine flow control 1748 * for both the PHY and the link partner. The following 1749 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25, 1750 * 1999, describes these PAUSE resolution bits and how flow 1751 * control is determined based upon these settings. 1752 * NOTE: DC = Don't Care 1753 * 1754 * LOCAL DEVICE | LINK PARTNER 1755 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution 1756 *-------|---------|-------|---------|-------------------- 1757 * 0 | 0 | DC | DC | e1000_fc_none 1758 * 0 | 1 | 0 | DC | e1000_fc_none 1759 * 0 | 1 | 1 | 0 | e1000_fc_none 1760 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 1761 * 1 | 0 | 0 | DC | e1000_fc_none 1762 * 1 | DC | 1 | DC | e1000_fc_full 1763 * 1 | 1 | 0 | 0 | e1000_fc_none 1764 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 1765 * 1766 */ 1767 /* Are both PAUSE bits set to 1? If so, this implies 1768 * Symmetric Flow Control is enabled at both ends. The 1769 * ASM_DIR bits are irrelevant per the spec. 1770 * 1771 * For Symmetric Flow Control: 1772 * 1773 * LOCAL DEVICE | LINK PARTNER 1774 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1775 *-------|---------|-------|---------|-------------------- 1776 * 1 | DC | 1 | DC | e1000_fc_full 1777 * 1778 */ 1779 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 1780 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) { 1781 /* Now we need to check if the user selected RX ONLY 1782 * of pause frames. In this case, we had to advertise 1783 * FULL flow control because we could not advertise RX 1784 * ONLY. Hence, we must now check to see if we need to 1785 * turn OFF the TRANSMISSION of PAUSE frames. 1786 */ 1787 if (hw->original_fc == e1000_fc_full) { 1788 hw->fc = e1000_fc_full; 1789 DEBUGOUT("Flow Control = FULL.\r\n"); 1790 } else { 1791 hw->fc = e1000_fc_rx_pause; 1792 DEBUGOUT 1793 ("Flow Control = RX PAUSE frames only.\r\n"); 1794 } 1795 } 1796 /* For receiving PAUSE frames ONLY. 1797 * 1798 * LOCAL DEVICE | LINK PARTNER 1799 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1800 *-------|---------|-------|---------|-------------------- 1801 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 1802 * 1803 */ 1804 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) && 1805 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 1806 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 1807 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) 1808 { 1809 hw->fc = e1000_fc_tx_pause; 1810 DEBUGOUT 1811 ("Flow Control = TX PAUSE frames only.\r\n"); 1812 } 1813 /* For transmitting PAUSE frames ONLY. 1814 * 1815 * LOCAL DEVICE | LINK PARTNER 1816 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1817 *-------|---------|-------|---------|-------------------- 1818 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 1819 * 1820 */ 1821 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 1822 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 1823 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 1824 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) 1825 { 1826 hw->fc = e1000_fc_rx_pause; 1827 DEBUGOUT 1828 ("Flow Control = RX PAUSE frames only.\r\n"); 1829 } 1830 /* Per the IEEE spec, at this point flow control should be 1831 * disabled. However, we want to consider that we could 1832 * be connected to a legacy switch that doesn't advertise 1833 * desired flow control, but can be forced on the link 1834 * partner. So if we advertised no flow control, that is 1835 * what we will resolve to. If we advertised some kind of 1836 * receive capability (Rx Pause Only or Full Flow Control) 1837 * and the link partner advertised none, we will configure 1838 * ourselves to enable Rx Flow Control only. We can do 1839 * this safely for two reasons: If the link partner really 1840 * didn't want flow control enabled, and we enable Rx, no 1841 * harm done since we won't be receiving any PAUSE frames 1842 * anyway. If the intent on the link partner was to have 1843 * flow control enabled, then by us enabling RX only, we 1844 * can at least receive pause frames and process them. 1845 * This is a good idea because in most cases, since we are 1846 * predominantly a server NIC, more times than not we will 1847 * be asked to delay transmission of packets than asking 1848 * our link partner to pause transmission of frames. 1849 */ 1850 else if (hw->original_fc == e1000_fc_none || 1851 hw->original_fc == e1000_fc_tx_pause) { 1852 hw->fc = e1000_fc_none; 1853 DEBUGOUT("Flow Control = NONE.\r\n"); 1854 } else { 1855 hw->fc = e1000_fc_rx_pause; 1856 DEBUGOUT 1857 ("Flow Control = RX PAUSE frames only.\r\n"); 1858 } 1859 1860 /* Now we need to do one last check... If we auto- 1861 * negotiated to HALF DUPLEX, flow control should not be 1862 * enabled per IEEE 802.3 spec. 1863 */ 1864 e1000_get_speed_and_duplex(hw, &speed, &duplex); 1865 1866 if (duplex == HALF_DUPLEX) 1867 hw->fc = e1000_fc_none; 1868 1869 /* Now we call a subroutine to actually force the MAC 1870 * controller to use the correct flow control settings. 1871 */ 1872 ret_val = e1000_force_mac_fc(hw); 1873 if (ret_val < 0) { 1874 DEBUGOUT 1875 ("Error forcing flow control settings\n"); 1876 return ret_val; 1877 } 1878 } else { 1879 DEBUGOUT 1880 ("Copper PHY and Auto Neg has not completed.\r\n"); 1881 } 1882 } 1883 return 0; 1884 } 1885 1886 /****************************************************************************** 1887 * Checks to see if the link status of the hardware has changed. 1888 * 1889 * hw - Struct containing variables accessed by shared code 1890 * 1891 * Called by any function that needs to check the link status of the adapter. 1892 *****************************************************************************/ 1893 static int 1894 e1000_check_for_link(struct eth_device *nic) 1895 { 1896 struct e1000_hw *hw = nic->priv; 1897 uint32_t rxcw; 1898 uint32_t ctrl; 1899 uint32_t status; 1900 uint32_t rctl; 1901 uint32_t signal; 1902 int32_t ret_val; 1903 uint16_t phy_data; 1904 uint16_t lp_capability; 1905 1906 DEBUGFUNC(); 1907 1908 /* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be 1909 * set when the optics detect a signal. On older adapters, it will be 1910 * cleared when there is a signal 1911 */ 1912 ctrl = E1000_READ_REG(hw, CTRL); 1913 if ((hw->mac_type > e1000_82544) && !(ctrl & E1000_CTRL_ILOS)) 1914 signal = E1000_CTRL_SWDPIN1; 1915 else 1916 signal = 0; 1917 1918 status = E1000_READ_REG(hw, STATUS); 1919 rxcw = E1000_READ_REG(hw, RXCW); 1920 DEBUGOUT("ctrl: %#08x status %#08x rxcw %#08x\n", ctrl, status, rxcw); 1921 1922 /* If we have a copper PHY then we only want to go out to the PHY 1923 * registers to see if Auto-Neg has completed and/or if our link 1924 * status has changed. The get_link_status flag will be set if we 1925 * receive a Link Status Change interrupt or we have Rx Sequence 1926 * Errors. 1927 */ 1928 if ((hw->media_type == e1000_media_type_copper) && hw->get_link_status) { 1929 /* First we want to see if the MII Status Register reports 1930 * link. If so, then we want to get the current speed/duplex 1931 * of the PHY. 1932 * Read the register twice since the link bit is sticky. 1933 */ 1934 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) { 1935 DEBUGOUT("PHY Read Error\n"); 1936 return -E1000_ERR_PHY; 1937 } 1938 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) { 1939 DEBUGOUT("PHY Read Error\n"); 1940 return -E1000_ERR_PHY; 1941 } 1942 1943 if (phy_data & MII_SR_LINK_STATUS) { 1944 hw->get_link_status = FALSE; 1945 } else { 1946 /* No link detected */ 1947 return -E1000_ERR_NOLINK; 1948 } 1949 1950 /* We have a M88E1000 PHY and Auto-Neg is enabled. If we 1951 * have Si on board that is 82544 or newer, Auto 1952 * Speed Detection takes care of MAC speed/duplex 1953 * configuration. So we only need to configure Collision 1954 * Distance in the MAC. Otherwise, we need to force 1955 * speed/duplex on the MAC to the current PHY speed/duplex 1956 * settings. 1957 */ 1958 if (hw->mac_type >= e1000_82544) 1959 e1000_config_collision_dist(hw); 1960 else { 1961 ret_val = e1000_config_mac_to_phy(hw); 1962 if (ret_val < 0) { 1963 DEBUGOUT 1964 ("Error configuring MAC to PHY settings\n"); 1965 return ret_val; 1966 } 1967 } 1968 1969 /* Configure Flow Control now that Auto-Neg has completed. First, we 1970 * need to restore the desired flow control settings because we may 1971 * have had to re-autoneg with a different link partner. 1972 */ 1973 ret_val = e1000_config_fc_after_link_up(hw); 1974 if (ret_val < 0) { 1975 DEBUGOUT("Error configuring flow control\n"); 1976 return ret_val; 1977 } 1978 1979 /* At this point we know that we are on copper and we have 1980 * auto-negotiated link. These are conditions for checking the link 1981 * parter capability register. We use the link partner capability to 1982 * determine if TBI Compatibility needs to be turned on or off. If 1983 * the link partner advertises any speed in addition to Gigabit, then 1984 * we assume that they are GMII-based, and TBI compatibility is not 1985 * needed. If no other speeds are advertised, we assume the link 1986 * partner is TBI-based, and we turn on TBI Compatibility. 1987 */ 1988 if (hw->tbi_compatibility_en) { 1989 if (e1000_read_phy_reg 1990 (hw, PHY_LP_ABILITY, &lp_capability) < 0) { 1991 DEBUGOUT("PHY Read Error\n"); 1992 return -E1000_ERR_PHY; 1993 } 1994 if (lp_capability & (NWAY_LPAR_10T_HD_CAPS | 1995 NWAY_LPAR_10T_FD_CAPS | 1996 NWAY_LPAR_100TX_HD_CAPS | 1997 NWAY_LPAR_100TX_FD_CAPS | 1998 NWAY_LPAR_100T4_CAPS)) { 1999 /* If our link partner advertises anything in addition to 2000 * gigabit, we do not need to enable TBI compatibility. 2001 */ 2002 if (hw->tbi_compatibility_on) { 2003 /* If we previously were in the mode, turn it off. */ 2004 rctl = E1000_READ_REG(hw, RCTL); 2005 rctl &= ~E1000_RCTL_SBP; 2006 E1000_WRITE_REG(hw, RCTL, rctl); 2007 hw->tbi_compatibility_on = FALSE; 2008 } 2009 } else { 2010 /* If TBI compatibility is was previously off, turn it on. For 2011 * compatibility with a TBI link partner, we will store bad 2012 * packets. Some frames have an additional byte on the end and 2013 * will look like CRC errors to to the hardware. 2014 */ 2015 if (!hw->tbi_compatibility_on) { 2016 hw->tbi_compatibility_on = TRUE; 2017 rctl = E1000_READ_REG(hw, RCTL); 2018 rctl |= E1000_RCTL_SBP; 2019 E1000_WRITE_REG(hw, RCTL, rctl); 2020 } 2021 } 2022 } 2023 } 2024 /* If we don't have link (auto-negotiation failed or link partner cannot 2025 * auto-negotiate), the cable is plugged in (we have signal), and our 2026 * link partner is not trying to auto-negotiate with us (we are receiving 2027 * idles or data), we need to force link up. We also need to give 2028 * auto-negotiation time to complete, in case the cable was just plugged 2029 * in. The autoneg_failed flag does this. 2030 */ 2031 else if ((hw->media_type == e1000_media_type_fiber) && 2032 (!(status & E1000_STATUS_LU)) && 2033 ((ctrl & E1000_CTRL_SWDPIN1) == signal) && 2034 (!(rxcw & E1000_RXCW_C))) { 2035 if (hw->autoneg_failed == 0) { 2036 hw->autoneg_failed = 1; 2037 return 0; 2038 } 2039 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\r\n"); 2040 2041 /* Disable auto-negotiation in the TXCW register */ 2042 E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE)); 2043 2044 /* Force link-up and also force full-duplex. */ 2045 ctrl = E1000_READ_REG(hw, CTRL); 2046 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 2047 E1000_WRITE_REG(hw, CTRL, ctrl); 2048 2049 /* Configure Flow Control after forcing link up. */ 2050 ret_val = e1000_config_fc_after_link_up(hw); 2051 if (ret_val < 0) { 2052 DEBUGOUT("Error configuring flow control\n"); 2053 return ret_val; 2054 } 2055 } 2056 /* If we are forcing link and we are receiving /C/ ordered sets, re-enable 2057 * auto-negotiation in the TXCW register and disable forced link in the 2058 * Device Control register in an attempt to auto-negotiate with our link 2059 * partner. 2060 */ 2061 else if ((hw->media_type == e1000_media_type_fiber) && 2062 (ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { 2063 DEBUGOUT 2064 ("RXing /C/, enable AutoNeg and stop forcing link.\r\n"); 2065 E1000_WRITE_REG(hw, TXCW, hw->txcw); 2066 E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU)); 2067 } 2068 return 0; 2069 } 2070 2071 /****************************************************************************** 2072 * Detects the current speed and duplex settings of the hardware. 2073 * 2074 * hw - Struct containing variables accessed by shared code 2075 * speed - Speed of the connection 2076 * duplex - Duplex setting of the connection 2077 *****************************************************************************/ 2078 static void 2079 e1000_get_speed_and_duplex(struct e1000_hw *hw, 2080 uint16_t * speed, uint16_t * duplex) 2081 { 2082 uint32_t status; 2083 2084 DEBUGFUNC(); 2085 2086 if (hw->mac_type >= e1000_82543) { 2087 status = E1000_READ_REG(hw, STATUS); 2088 if (status & E1000_STATUS_SPEED_1000) { 2089 *speed = SPEED_1000; 2090 DEBUGOUT("1000 Mbs, "); 2091 } else if (status & E1000_STATUS_SPEED_100) { 2092 *speed = SPEED_100; 2093 DEBUGOUT("100 Mbs, "); 2094 } else { 2095 *speed = SPEED_10; 2096 DEBUGOUT("10 Mbs, "); 2097 } 2098 2099 if (status & E1000_STATUS_FD) { 2100 *duplex = FULL_DUPLEX; 2101 DEBUGOUT("Full Duplex\r\n"); 2102 } else { 2103 *duplex = HALF_DUPLEX; 2104 DEBUGOUT(" Half Duplex\r\n"); 2105 } 2106 } else { 2107 DEBUGOUT("1000 Mbs, Full Duplex\r\n"); 2108 *speed = SPEED_1000; 2109 *duplex = FULL_DUPLEX; 2110 } 2111 } 2112 2113 /****************************************************************************** 2114 * Blocks until autoneg completes or times out (~4.5 seconds) 2115 * 2116 * hw - Struct containing variables accessed by shared code 2117 ******************************************************************************/ 2118 static int 2119 e1000_wait_autoneg(struct e1000_hw *hw) 2120 { 2121 uint16_t i; 2122 uint16_t phy_data; 2123 2124 DEBUGFUNC(); 2125 DEBUGOUT("Waiting for Auto-Neg to complete.\n"); 2126 2127 /* We will wait for autoneg to complete or 4.5 seconds to expire. */ 2128 for (i = PHY_AUTO_NEG_TIME; i > 0; i--) { 2129 /* Read the MII Status Register and wait for Auto-Neg 2130 * Complete bit to be set. 2131 */ 2132 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) { 2133 DEBUGOUT("PHY Read Error\n"); 2134 return -E1000_ERR_PHY; 2135 } 2136 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) { 2137 DEBUGOUT("PHY Read Error\n"); 2138 return -E1000_ERR_PHY; 2139 } 2140 if (phy_data & MII_SR_AUTONEG_COMPLETE) { 2141 DEBUGOUT("Auto-Neg complete.\n"); 2142 return 0; 2143 } 2144 mdelay(100); 2145 } 2146 DEBUGOUT("Auto-Neg timedout.\n"); 2147 return -E1000_ERR_TIMEOUT; 2148 } 2149 2150 /****************************************************************************** 2151 * Raises the Management Data Clock 2152 * 2153 * hw - Struct containing variables accessed by shared code 2154 * ctrl - Device control register's current value 2155 ******************************************************************************/ 2156 static void 2157 e1000_raise_mdi_clk(struct e1000_hw *hw, uint32_t * ctrl) 2158 { 2159 /* Raise the clock input to the Management Data Clock (by setting the MDC 2160 * bit), and then delay 2 microseconds. 2161 */ 2162 E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC)); 2163 E1000_WRITE_FLUSH(hw); 2164 udelay(2); 2165 } 2166 2167 /****************************************************************************** 2168 * Lowers the Management Data Clock 2169 * 2170 * hw - Struct containing variables accessed by shared code 2171 * ctrl - Device control register's current value 2172 ******************************************************************************/ 2173 static void 2174 e1000_lower_mdi_clk(struct e1000_hw *hw, uint32_t * ctrl) 2175 { 2176 /* Lower the clock input to the Management Data Clock (by clearing the MDC 2177 * bit), and then delay 2 microseconds. 2178 */ 2179 E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC)); 2180 E1000_WRITE_FLUSH(hw); 2181 udelay(2); 2182 } 2183 2184 /****************************************************************************** 2185 * Shifts data bits out to the PHY 2186 * 2187 * hw - Struct containing variables accessed by shared code 2188 * data - Data to send out to the PHY 2189 * count - Number of bits to shift out 2190 * 2191 * Bits are shifted out in MSB to LSB order. 2192 ******************************************************************************/ 2193 static void 2194 e1000_shift_out_mdi_bits(struct e1000_hw *hw, uint32_t data, uint16_t count) 2195 { 2196 uint32_t ctrl; 2197 uint32_t mask; 2198 2199 /* We need to shift "count" number of bits out to the PHY. So, the value 2200 * in the "data" parameter will be shifted out to the PHY one bit at a 2201 * time. In order to do this, "data" must be broken down into bits. 2202 */ 2203 mask = 0x01; 2204 mask <<= (count - 1); 2205 2206 ctrl = E1000_READ_REG(hw, CTRL); 2207 2208 /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */ 2209 ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR); 2210 2211 while (mask) { 2212 /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and 2213 * then raising and lowering the Management Data Clock. A "0" is 2214 * shifted out to the PHY by setting the MDIO bit to "0" and then 2215 * raising and lowering the clock. 2216 */ 2217 if (data & mask) 2218 ctrl |= E1000_CTRL_MDIO; 2219 else 2220 ctrl &= ~E1000_CTRL_MDIO; 2221 2222 E1000_WRITE_REG(hw, CTRL, ctrl); 2223 E1000_WRITE_FLUSH(hw); 2224 2225 udelay(2); 2226 2227 e1000_raise_mdi_clk(hw, &ctrl); 2228 e1000_lower_mdi_clk(hw, &ctrl); 2229 2230 mask = mask >> 1; 2231 } 2232 } 2233 2234 /****************************************************************************** 2235 * Shifts data bits in from the PHY 2236 * 2237 * hw - Struct containing variables accessed by shared code 2238 * 2239 * Bits are shifted in in MSB to LSB order. 2240 ******************************************************************************/ 2241 static uint16_t 2242 e1000_shift_in_mdi_bits(struct e1000_hw *hw) 2243 { 2244 uint32_t ctrl; 2245 uint16_t data = 0; 2246 uint8_t i; 2247 2248 /* In order to read a register from the PHY, we need to shift in a total 2249 * of 18 bits from the PHY. The first two bit (turnaround) times are used 2250 * to avoid contention on the MDIO pin when a read operation is performed. 2251 * These two bits are ignored by us and thrown away. Bits are "shifted in" 2252 * by raising the input to the Management Data Clock (setting the MDC bit), 2253 * and then reading the value of the MDIO bit. 2254 */ 2255 ctrl = E1000_READ_REG(hw, CTRL); 2256 2257 /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */ 2258 ctrl &= ~E1000_CTRL_MDIO_DIR; 2259 ctrl &= ~E1000_CTRL_MDIO; 2260 2261 E1000_WRITE_REG(hw, CTRL, ctrl); 2262 E1000_WRITE_FLUSH(hw); 2263 2264 /* Raise and Lower the clock before reading in the data. This accounts for 2265 * the turnaround bits. The first clock occurred when we clocked out the 2266 * last bit of the Register Address. 2267 */ 2268 e1000_raise_mdi_clk(hw, &ctrl); 2269 e1000_lower_mdi_clk(hw, &ctrl); 2270 2271 for (data = 0, i = 0; i < 16; i++) { 2272 data = data << 1; 2273 e1000_raise_mdi_clk(hw, &ctrl); 2274 ctrl = E1000_READ_REG(hw, CTRL); 2275 /* Check to see if we shifted in a "1". */ 2276 if (ctrl & E1000_CTRL_MDIO) 2277 data |= 1; 2278 e1000_lower_mdi_clk(hw, &ctrl); 2279 } 2280 2281 e1000_raise_mdi_clk(hw, &ctrl); 2282 e1000_lower_mdi_clk(hw, &ctrl); 2283 2284 return data; 2285 } 2286 2287 /***************************************************************************** 2288 * Reads the value from a PHY register 2289 * 2290 * hw - Struct containing variables accessed by shared code 2291 * reg_addr - address of the PHY register to read 2292 ******************************************************************************/ 2293 static int 2294 e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t * phy_data) 2295 { 2296 uint32_t i; 2297 uint32_t mdic = 0; 2298 const uint32_t phy_addr = 1; 2299 2300 if (reg_addr > MAX_PHY_REG_ADDRESS) { 2301 DEBUGOUT("PHY Address %d is out of range\n", reg_addr); 2302 return -E1000_ERR_PARAM; 2303 } 2304 2305 if (hw->mac_type > e1000_82543) { 2306 /* Set up Op-code, Phy Address, and register address in the MDI 2307 * Control register. The MAC will take care of interfacing with the 2308 * PHY to retrieve the desired data. 2309 */ 2310 mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) | 2311 (phy_addr << E1000_MDIC_PHY_SHIFT) | 2312 (E1000_MDIC_OP_READ)); 2313 2314 E1000_WRITE_REG(hw, MDIC, mdic); 2315 2316 /* Poll the ready bit to see if the MDI read completed */ 2317 for (i = 0; i < 64; i++) { 2318 udelay(10); 2319 mdic = E1000_READ_REG(hw, MDIC); 2320 if (mdic & E1000_MDIC_READY) 2321 break; 2322 } 2323 if (!(mdic & E1000_MDIC_READY)) { 2324 DEBUGOUT("MDI Read did not complete\n"); 2325 return -E1000_ERR_PHY; 2326 } 2327 if (mdic & E1000_MDIC_ERROR) { 2328 DEBUGOUT("MDI Error\n"); 2329 return -E1000_ERR_PHY; 2330 } 2331 *phy_data = (uint16_t) mdic; 2332 } else { 2333 /* We must first send a preamble through the MDIO pin to signal the 2334 * beginning of an MII instruction. This is done by sending 32 2335 * consecutive "1" bits. 2336 */ 2337 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); 2338 2339 /* Now combine the next few fields that are required for a read 2340 * operation. We use this method instead of calling the 2341 * e1000_shift_out_mdi_bits routine five different times. The format of 2342 * a MII read instruction consists of a shift out of 14 bits and is 2343 * defined as follows: 2344 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr> 2345 * followed by a shift in of 18 bits. This first two bits shifted in 2346 * are TurnAround bits used to avoid contention on the MDIO pin when a 2347 * READ operation is performed. These two bits are thrown away 2348 * followed by a shift in of 16 bits which contains the desired data. 2349 */ 2350 mdic = ((reg_addr) | (phy_addr << 5) | 2351 (PHY_OP_READ << 10) | (PHY_SOF << 12)); 2352 2353 e1000_shift_out_mdi_bits(hw, mdic, 14); 2354 2355 /* Now that we've shifted out the read command to the MII, we need to 2356 * "shift in" the 16-bit value (18 total bits) of the requested PHY 2357 * register address. 2358 */ 2359 *phy_data = e1000_shift_in_mdi_bits(hw); 2360 } 2361 return 0; 2362 } 2363 2364 /****************************************************************************** 2365 * Writes a value to a PHY register 2366 * 2367 * hw - Struct containing variables accessed by shared code 2368 * reg_addr - address of the PHY register to write 2369 * data - data to write to the PHY 2370 ******************************************************************************/ 2371 static int 2372 e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t phy_data) 2373 { 2374 uint32_t i; 2375 uint32_t mdic = 0; 2376 const uint32_t phy_addr = 1; 2377 2378 if (reg_addr > MAX_PHY_REG_ADDRESS) { 2379 DEBUGOUT("PHY Address %d is out of range\n", reg_addr); 2380 return -E1000_ERR_PARAM; 2381 } 2382 2383 if (hw->mac_type > e1000_82543) { 2384 /* Set up Op-code, Phy Address, register address, and data intended 2385 * for the PHY register in the MDI Control register. The MAC will take 2386 * care of interfacing with the PHY to send the desired data. 2387 */ 2388 mdic = (((uint32_t) phy_data) | 2389 (reg_addr << E1000_MDIC_REG_SHIFT) | 2390 (phy_addr << E1000_MDIC_PHY_SHIFT) | 2391 (E1000_MDIC_OP_WRITE)); 2392 2393 E1000_WRITE_REG(hw, MDIC, mdic); 2394 2395 /* Poll the ready bit to see if the MDI read completed */ 2396 for (i = 0; i < 64; i++) { 2397 udelay(10); 2398 mdic = E1000_READ_REG(hw, MDIC); 2399 if (mdic & E1000_MDIC_READY) 2400 break; 2401 } 2402 if (!(mdic & E1000_MDIC_READY)) { 2403 DEBUGOUT("MDI Write did not complete\n"); 2404 return -E1000_ERR_PHY; 2405 } 2406 } else { 2407 /* We'll need to use the SW defined pins to shift the write command 2408 * out to the PHY. We first send a preamble to the PHY to signal the 2409 * beginning of the MII instruction. This is done by sending 32 2410 * consecutive "1" bits. 2411 */ 2412 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); 2413 2414 /* Now combine the remaining required fields that will indicate a 2415 * write operation. We use this method instead of calling the 2416 * e1000_shift_out_mdi_bits routine for each field in the command. The 2417 * format of a MII write instruction is as follows: 2418 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>. 2419 */ 2420 mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) | 2421 (PHY_OP_WRITE << 12) | (PHY_SOF << 14)); 2422 mdic <<= 16; 2423 mdic |= (uint32_t) phy_data; 2424 2425 e1000_shift_out_mdi_bits(hw, mdic, 32); 2426 } 2427 return 0; 2428 } 2429 2430 /****************************************************************************** 2431 * Returns the PHY to the power-on reset state 2432 * 2433 * hw - Struct containing variables accessed by shared code 2434 ******************************************************************************/ 2435 static void 2436 e1000_phy_hw_reset(struct e1000_hw *hw) 2437 { 2438 uint32_t ctrl; 2439 uint32_t ctrl_ext; 2440 2441 DEBUGFUNC(); 2442 2443 DEBUGOUT("Resetting Phy...\n"); 2444 2445 if (hw->mac_type > e1000_82543) { 2446 /* Read the device control register and assert the E1000_CTRL_PHY_RST 2447 * bit. Then, take it out of reset. 2448 */ 2449 ctrl = E1000_READ_REG(hw, CTRL); 2450 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST); 2451 E1000_WRITE_FLUSH(hw); 2452 mdelay(10); 2453 E1000_WRITE_REG(hw, CTRL, ctrl); 2454 E1000_WRITE_FLUSH(hw); 2455 } else { 2456 /* Read the Extended Device Control Register, assert the PHY_RESET_DIR 2457 * bit to put the PHY into reset. Then, take it out of reset. 2458 */ 2459 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 2460 ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR; 2461 ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA; 2462 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 2463 E1000_WRITE_FLUSH(hw); 2464 mdelay(10); 2465 ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA; 2466 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 2467 E1000_WRITE_FLUSH(hw); 2468 } 2469 udelay(150); 2470 } 2471 2472 /****************************************************************************** 2473 * Resets the PHY 2474 * 2475 * hw - Struct containing variables accessed by shared code 2476 * 2477 * Sets bit 15 of the MII Control regiser 2478 ******************************************************************************/ 2479 static int 2480 e1000_phy_reset(struct e1000_hw *hw) 2481 { 2482 uint16_t phy_data; 2483 2484 DEBUGFUNC(); 2485 2486 if (e1000_read_phy_reg(hw, PHY_CTRL, &phy_data) < 0) { 2487 DEBUGOUT("PHY Read Error\n"); 2488 return -E1000_ERR_PHY; 2489 } 2490 phy_data |= MII_CR_RESET; 2491 if (e1000_write_phy_reg(hw, PHY_CTRL, phy_data) < 0) { 2492 DEBUGOUT("PHY Write Error\n"); 2493 return -E1000_ERR_PHY; 2494 } 2495 udelay(1); 2496 return 0; 2497 } 2498 2499 static int e1000_set_phy_type (struct e1000_hw *hw) 2500 { 2501 DEBUGFUNC (); 2502 2503 if (hw->mac_type == e1000_undefined) 2504 return -E1000_ERR_PHY_TYPE; 2505 2506 switch (hw->phy_id) { 2507 case M88E1000_E_PHY_ID: 2508 case M88E1000_I_PHY_ID: 2509 case M88E1011_I_PHY_ID: 2510 hw->phy_type = e1000_phy_m88; 2511 break; 2512 case IGP01E1000_I_PHY_ID: 2513 if (hw->mac_type == e1000_82541 || 2514 hw->mac_type == e1000_82541_rev_2) { 2515 hw->phy_type = e1000_phy_igp; 2516 break; 2517 } 2518 /* Fall Through */ 2519 default: 2520 /* Should never have loaded on this device */ 2521 hw->phy_type = e1000_phy_undefined; 2522 return -E1000_ERR_PHY_TYPE; 2523 } 2524 2525 return E1000_SUCCESS; 2526 } 2527 2528 /****************************************************************************** 2529 * Probes the expected PHY address for known PHY IDs 2530 * 2531 * hw - Struct containing variables accessed by shared code 2532 ******************************************************************************/ 2533 static int 2534 e1000_detect_gig_phy(struct e1000_hw *hw) 2535 { 2536 int32_t phy_init_status; 2537 uint16_t phy_id_high, phy_id_low; 2538 int match = FALSE; 2539 2540 DEBUGFUNC(); 2541 2542 /* Read the PHY ID Registers to identify which PHY is onboard. */ 2543 if (e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high) < 0) { 2544 DEBUGOUT("PHY Read Error\n"); 2545 return -E1000_ERR_PHY; 2546 } 2547 hw->phy_id = (uint32_t) (phy_id_high << 16); 2548 udelay(2); 2549 if (e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low) < 0) { 2550 DEBUGOUT("PHY Read Error\n"); 2551 return -E1000_ERR_PHY; 2552 } 2553 hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK); 2554 2555 switch (hw->mac_type) { 2556 case e1000_82543: 2557 if (hw->phy_id == M88E1000_E_PHY_ID) 2558 match = TRUE; 2559 break; 2560 case e1000_82544: 2561 if (hw->phy_id == M88E1000_I_PHY_ID) 2562 match = TRUE; 2563 break; 2564 case e1000_82540: 2565 case e1000_82545: 2566 case e1000_82546: 2567 if (hw->phy_id == M88E1011_I_PHY_ID) 2568 match = TRUE; 2569 break; 2570 case e1000_82541_rev_2: 2571 if(hw->phy_id == IGP01E1000_I_PHY_ID) 2572 match = TRUE; 2573 2574 break; 2575 default: 2576 DEBUGOUT("Invalid MAC type %d\n", hw->mac_type); 2577 return -E1000_ERR_CONFIG; 2578 } 2579 2580 phy_init_status = e1000_set_phy_type(hw); 2581 2582 if ((match) && (phy_init_status == E1000_SUCCESS)) { 2583 DEBUGOUT("PHY ID 0x%X detected\n", hw->phy_id); 2584 return 0; 2585 } 2586 DEBUGOUT("Invalid PHY ID 0x%X\n", hw->phy_id); 2587 return -E1000_ERR_PHY; 2588 } 2589 2590 /** 2591 * e1000_sw_init - Initialize general software structures (struct e1000_adapter) 2592 * 2593 * e1000_sw_init initializes the Adapter private data structure. 2594 * Fields are initialized based on PCI device information and 2595 * OS network device settings (MTU size). 2596 **/ 2597 2598 static int 2599 e1000_sw_init(struct eth_device *nic, int cardnum) 2600 { 2601 struct e1000_hw *hw = (typeof(hw)) nic->priv; 2602 int result; 2603 2604 /* PCI config space info */ 2605 pci_read_config_word(hw->pdev, PCI_VENDOR_ID, &hw->vendor_id); 2606 pci_read_config_word(hw->pdev, PCI_DEVICE_ID, &hw->device_id); 2607 pci_read_config_word(hw->pdev, PCI_SUBSYSTEM_VENDOR_ID, 2608 &hw->subsystem_vendor_id); 2609 pci_read_config_word(hw->pdev, PCI_SUBSYSTEM_ID, &hw->subsystem_id); 2610 2611 pci_read_config_byte(hw->pdev, PCI_REVISION_ID, &hw->revision_id); 2612 pci_read_config_word(hw->pdev, PCI_COMMAND, &hw->pci_cmd_word); 2613 2614 /* identify the MAC */ 2615 result = e1000_set_mac_type(hw); 2616 if (result) { 2617 E1000_ERR("Unknown MAC Type\n"); 2618 return result; 2619 } 2620 2621 /* lan a vs. lan b settings */ 2622 if (hw->mac_type == e1000_82546) 2623 /*this also works w/ multiple 82546 cards */ 2624 /*but not if they're intermingled /w other e1000s */ 2625 hw->lan_loc = (cardnum % 2) ? e1000_lan_b : e1000_lan_a; 2626 else 2627 hw->lan_loc = e1000_lan_a; 2628 2629 /* flow control settings */ 2630 hw->fc_high_water = E1000_FC_HIGH_THRESH; 2631 hw->fc_low_water = E1000_FC_LOW_THRESH; 2632 hw->fc_pause_time = E1000_FC_PAUSE_TIME; 2633 hw->fc_send_xon = 1; 2634 2635 /* Media type - copper or fiber */ 2636 2637 if (hw->mac_type >= e1000_82543) { 2638 uint32_t status = E1000_READ_REG(hw, STATUS); 2639 2640 if (status & E1000_STATUS_TBIMODE) { 2641 DEBUGOUT("fiber interface\n"); 2642 hw->media_type = e1000_media_type_fiber; 2643 } else { 2644 DEBUGOUT("copper interface\n"); 2645 hw->media_type = e1000_media_type_copper; 2646 } 2647 } else { 2648 hw->media_type = e1000_media_type_fiber; 2649 } 2650 2651 if (hw->mac_type < e1000_82543) 2652 hw->report_tx_early = 0; 2653 else 2654 hw->report_tx_early = 1; 2655 2656 hw->tbi_compatibility_en = TRUE; 2657 #if 0 2658 hw->wait_autoneg_complete = FALSE; 2659 hw->adaptive_ifs = TRUE; 2660 2661 /* Copper options */ 2662 if (hw->media_type == e1000_media_type_copper) { 2663 hw->mdix = AUTO_ALL_MODES; 2664 hw->disable_polarity_correction = FALSE; 2665 } 2666 #endif 2667 return E1000_SUCCESS; 2668 } 2669 2670 void 2671 fill_rx(struct e1000_hw *hw) 2672 { 2673 struct e1000_rx_desc *rd; 2674 2675 rx_last = rx_tail; 2676 rd = rx_base + rx_tail; 2677 rx_tail = (rx_tail + 1) % 8; 2678 memset(rd, 0, 16); 2679 rd->buffer_addr = cpu_to_le64((u32) & packet); 2680 E1000_WRITE_REG(hw, RDT, rx_tail); 2681 } 2682 2683 /** 2684 * e1000_configure_tx - Configure 8254x Transmit Unit after Reset 2685 * @adapter: board private structure 2686 * 2687 * Configure the Tx unit of the MAC after a reset. 2688 **/ 2689 2690 static void 2691 e1000_configure_tx(struct e1000_hw *hw) 2692 { 2693 unsigned long ptr; 2694 unsigned long tctl; 2695 unsigned long tipg; 2696 2697 ptr = (u32) tx_pool; 2698 if (ptr & 0xf) 2699 ptr = (ptr + 0x10) & (~0xf); 2700 2701 tx_base = (typeof(tx_base)) ptr; 2702 2703 E1000_WRITE_REG(hw, TDBAL, (u32) tx_base); 2704 E1000_WRITE_REG(hw, TDBAH, 0); 2705 2706 E1000_WRITE_REG(hw, TDLEN, 128); 2707 2708 /* Setup the HW Tx Head and Tail descriptor pointers */ 2709 E1000_WRITE_REG(hw, TDH, 0); 2710 E1000_WRITE_REG(hw, TDT, 0); 2711 tx_tail = 0; 2712 2713 /* Set the default values for the Tx Inter Packet Gap timer */ 2714 switch (hw->mac_type) { 2715 case e1000_82542_rev2_0: 2716 case e1000_82542_rev2_1: 2717 tipg = DEFAULT_82542_TIPG_IPGT; 2718 tipg |= DEFAULT_82542_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 2719 tipg |= DEFAULT_82542_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 2720 break; 2721 default: 2722 if (hw->media_type == e1000_media_type_fiber) 2723 tipg = DEFAULT_82543_TIPG_IPGT_FIBER; 2724 else 2725 tipg = DEFAULT_82543_TIPG_IPGT_COPPER; 2726 tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 2727 tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 2728 } 2729 E1000_WRITE_REG(hw, TIPG, tipg); 2730 #if 0 2731 /* Set the Tx Interrupt Delay register */ 2732 E1000_WRITE_REG(hw, TIDV, adapter->tx_int_delay); 2733 if (hw->mac_type >= e1000_82540) 2734 E1000_WRITE_REG(hw, TADV, adapter->tx_abs_int_delay); 2735 #endif 2736 /* Program the Transmit Control Register */ 2737 tctl = E1000_READ_REG(hw, TCTL); 2738 tctl &= ~E1000_TCTL_CT; 2739 tctl |= E1000_TCTL_EN | E1000_TCTL_PSP | 2740 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); 2741 E1000_WRITE_REG(hw, TCTL, tctl); 2742 2743 e1000_config_collision_dist(hw); 2744 #if 0 2745 /* Setup Transmit Descriptor Settings for this adapter */ 2746 adapter->txd_cmd = E1000_TXD_CMD_IFCS | E1000_TXD_CMD_IDE; 2747 2748 if (adapter->hw.report_tx_early == 1) 2749 adapter->txd_cmd |= E1000_TXD_CMD_RS; 2750 else 2751 adapter->txd_cmd |= E1000_TXD_CMD_RPS; 2752 #endif 2753 } 2754 2755 /** 2756 * e1000_setup_rctl - configure the receive control register 2757 * @adapter: Board private structure 2758 **/ 2759 static void 2760 e1000_setup_rctl(struct e1000_hw *hw) 2761 { 2762 uint32_t rctl; 2763 2764 rctl = E1000_READ_REG(hw, RCTL); 2765 2766 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 2767 2768 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF; /* | 2769 (hw.mc_filter_type << E1000_RCTL_MO_SHIFT); */ 2770 2771 if (hw->tbi_compatibility_on == 1) 2772 rctl |= E1000_RCTL_SBP; 2773 else 2774 rctl &= ~E1000_RCTL_SBP; 2775 2776 rctl &= ~(E1000_RCTL_SZ_4096); 2777 #if 0 2778 switch (adapter->rx_buffer_len) { 2779 case E1000_RXBUFFER_2048: 2780 default: 2781 #endif 2782 rctl |= E1000_RCTL_SZ_2048; 2783 rctl &= ~(E1000_RCTL_BSEX | E1000_RCTL_LPE); 2784 #if 0 2785 break; 2786 case E1000_RXBUFFER_4096: 2787 rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX | E1000_RCTL_LPE; 2788 break; 2789 case E1000_RXBUFFER_8192: 2790 rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX | E1000_RCTL_LPE; 2791 break; 2792 case E1000_RXBUFFER_16384: 2793 rctl |= E1000_RCTL_SZ_16384 | E1000_RCTL_BSEX | E1000_RCTL_LPE; 2794 break; 2795 } 2796 #endif 2797 E1000_WRITE_REG(hw, RCTL, rctl); 2798 } 2799 2800 /** 2801 * e1000_configure_rx - Configure 8254x Receive Unit after Reset 2802 * @adapter: board private structure 2803 * 2804 * Configure the Rx unit of the MAC after a reset. 2805 **/ 2806 static void 2807 e1000_configure_rx(struct e1000_hw *hw) 2808 { 2809 unsigned long ptr; 2810 unsigned long rctl; 2811 #if 0 2812 unsigned long rxcsum; 2813 #endif 2814 rx_tail = 0; 2815 /* make sure receives are disabled while setting up the descriptors */ 2816 rctl = E1000_READ_REG(hw, RCTL); 2817 E1000_WRITE_REG(hw, RCTL, rctl & ~E1000_RCTL_EN); 2818 #if 0 2819 /* set the Receive Delay Timer Register */ 2820 2821 E1000_WRITE_REG(hw, RDTR, adapter->rx_int_delay); 2822 #endif 2823 if (hw->mac_type >= e1000_82540) { 2824 #if 0 2825 E1000_WRITE_REG(hw, RADV, adapter->rx_abs_int_delay); 2826 #endif 2827 /* Set the interrupt throttling rate. Value is calculated 2828 * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns) */ 2829 #define MAX_INTS_PER_SEC 8000 2830 #define DEFAULT_ITR 1000000000/(MAX_INTS_PER_SEC * 256) 2831 E1000_WRITE_REG(hw, ITR, DEFAULT_ITR); 2832 } 2833 2834 /* Setup the Base and Length of the Rx Descriptor Ring */ 2835 ptr = (u32) rx_pool; 2836 if (ptr & 0xf) 2837 ptr = (ptr + 0x10) & (~0xf); 2838 rx_base = (typeof(rx_base)) ptr; 2839 E1000_WRITE_REG(hw, RDBAL, (u32) rx_base); 2840 E1000_WRITE_REG(hw, RDBAH, 0); 2841 2842 E1000_WRITE_REG(hw, RDLEN, 128); 2843 2844 /* Setup the HW Rx Head and Tail Descriptor Pointers */ 2845 E1000_WRITE_REG(hw, RDH, 0); 2846 E1000_WRITE_REG(hw, RDT, 0); 2847 #if 0 2848 /* Enable 82543 Receive Checksum Offload for TCP and UDP */ 2849 if ((adapter->hw.mac_type >= e1000_82543) && (adapter->rx_csum == TRUE)) { 2850 rxcsum = E1000_READ_REG(hw, RXCSUM); 2851 rxcsum |= E1000_RXCSUM_TUOFL; 2852 E1000_WRITE_REG(hw, RXCSUM, rxcsum); 2853 } 2854 #endif 2855 /* Enable Receives */ 2856 2857 E1000_WRITE_REG(hw, RCTL, rctl); 2858 fill_rx(hw); 2859 } 2860 2861 /************************************************************************** 2862 POLL - Wait for a frame 2863 ***************************************************************************/ 2864 static int 2865 e1000_poll(struct eth_device *nic) 2866 { 2867 struct e1000_hw *hw = nic->priv; 2868 struct e1000_rx_desc *rd; 2869 /* return true if there's an ethernet packet ready to read */ 2870 rd = rx_base + rx_last; 2871 if (!(le32_to_cpu(rd->status)) & E1000_RXD_STAT_DD) 2872 return 0; 2873 /*DEBUGOUT("recv: packet len=%d \n", rd->length); */ 2874 NetReceive((uchar *)packet, le32_to_cpu(rd->length)); 2875 fill_rx(hw); 2876 return 1; 2877 } 2878 2879 /************************************************************************** 2880 TRANSMIT - Transmit a frame 2881 ***************************************************************************/ 2882 static int 2883 e1000_transmit(struct eth_device *nic, volatile void *packet, int length) 2884 { 2885 struct e1000_hw *hw = nic->priv; 2886 struct e1000_tx_desc *txp; 2887 int i = 0; 2888 2889 txp = tx_base + tx_tail; 2890 tx_tail = (tx_tail + 1) % 8; 2891 2892 txp->buffer_addr = cpu_to_le64(virt_to_bus(packet)); 2893 txp->lower.data = cpu_to_le32(E1000_TXD_CMD_RPS | E1000_TXD_CMD_EOP | 2894 E1000_TXD_CMD_IFCS | length); 2895 txp->upper.data = 0; 2896 E1000_WRITE_REG(hw, TDT, tx_tail); 2897 2898 while (!(le32_to_cpu(txp->upper.data) & E1000_TXD_STAT_DD)) { 2899 if (i++ > TOUT_LOOP) { 2900 DEBUGOUT("e1000: tx timeout\n"); 2901 return 0; 2902 } 2903 udelay(10); /* give the nic a chance to write to the register */ 2904 } 2905 return 1; 2906 } 2907 2908 /*reset function*/ 2909 static inline int 2910 e1000_reset(struct eth_device *nic) 2911 { 2912 struct e1000_hw *hw = nic->priv; 2913 2914 e1000_reset_hw(hw); 2915 if (hw->mac_type >= e1000_82544) { 2916 E1000_WRITE_REG(hw, WUC, 0); 2917 } 2918 return e1000_init_hw(nic); 2919 } 2920 2921 /************************************************************************** 2922 DISABLE - Turn off ethernet interface 2923 ***************************************************************************/ 2924 static void 2925 e1000_disable(struct eth_device *nic) 2926 { 2927 struct e1000_hw *hw = nic->priv; 2928 2929 /* Turn off the ethernet interface */ 2930 E1000_WRITE_REG(hw, RCTL, 0); 2931 E1000_WRITE_REG(hw, TCTL, 0); 2932 2933 /* Clear the transmit ring */ 2934 E1000_WRITE_REG(hw, TDH, 0); 2935 E1000_WRITE_REG(hw, TDT, 0); 2936 2937 /* Clear the receive ring */ 2938 E1000_WRITE_REG(hw, RDH, 0); 2939 E1000_WRITE_REG(hw, RDT, 0); 2940 2941 /* put the card in its initial state */ 2942 #if 0 2943 E1000_WRITE_REG(hw, CTRL, E1000_CTRL_RST); 2944 #endif 2945 mdelay(10); 2946 2947 } 2948 2949 /************************************************************************** 2950 INIT - set up ethernet interface(s) 2951 ***************************************************************************/ 2952 static int 2953 e1000_init(struct eth_device *nic, bd_t * bis) 2954 { 2955 struct e1000_hw *hw = nic->priv; 2956 int ret_val = 0; 2957 2958 ret_val = e1000_reset(nic); 2959 if (ret_val < 0) { 2960 if ((ret_val == -E1000_ERR_NOLINK) || 2961 (ret_val == -E1000_ERR_TIMEOUT)) { 2962 E1000_ERR("Valid Link not detected\n"); 2963 } else { 2964 E1000_ERR("Hardware Initialization Failed\n"); 2965 } 2966 return 0; 2967 } 2968 e1000_configure_tx(hw); 2969 e1000_setup_rctl(hw); 2970 e1000_configure_rx(hw); 2971 return 1; 2972 } 2973 2974 /************************************************************************** 2975 PROBE - Look for an adapter, this routine's visible to the outside 2976 You should omit the last argument struct pci_device * for a non-PCI NIC 2977 ***************************************************************************/ 2978 int 2979 e1000_initialize(bd_t * bis) 2980 { 2981 pci_dev_t devno; 2982 int card_number = 0; 2983 struct eth_device *nic = NULL; 2984 struct e1000_hw *hw = NULL; 2985 u32 iobase; 2986 int idx = 0; 2987 u32 PciCommandWord; 2988 2989 while (1) { /* Find PCI device(s) */ 2990 if ((devno = pci_find_devices(supported, idx++)) < 0) { 2991 break; 2992 } 2993 2994 pci_read_config_dword(devno, PCI_BASE_ADDRESS_0, &iobase); 2995 iobase &= ~0xf; /* Mask the bits that say "this is an io addr" */ 2996 DEBUGOUT("e1000#%d: iobase 0x%08x\n", card_number, iobase); 2997 2998 pci_write_config_dword(devno, PCI_COMMAND, 2999 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); 3000 /* Check if I/O accesses and Bus Mastering are enabled. */ 3001 pci_read_config_dword(devno, PCI_COMMAND, &PciCommandWord); 3002 if (!(PciCommandWord & PCI_COMMAND_MEMORY)) { 3003 printf("Error: Can not enable MEM access.\n"); 3004 continue; 3005 } else if (!(PciCommandWord & PCI_COMMAND_MASTER)) { 3006 printf("Error: Can not enable Bus Mastering.\n"); 3007 continue; 3008 } 3009 3010 nic = (struct eth_device *) malloc(sizeof (*nic)); 3011 hw = (struct e1000_hw *) malloc(sizeof (*hw)); 3012 hw->pdev = devno; 3013 nic->priv = hw; 3014 nic->iobase = bus_to_phys(devno, iobase); 3015 3016 sprintf(nic->name, "e1000#%d", card_number); 3017 3018 /* Are these variables needed? */ 3019 #if 0 3020 hw->fc = e1000_fc_none; 3021 hw->original_fc = e1000_fc_none; 3022 #else 3023 hw->fc = e1000_fc_default; 3024 hw->original_fc = e1000_fc_default; 3025 #endif 3026 hw->autoneg_failed = 0; 3027 hw->get_link_status = TRUE; 3028 hw->hw_addr = (typeof(hw->hw_addr)) iobase; 3029 hw->mac_type = e1000_undefined; 3030 3031 /* MAC and Phy settings */ 3032 if (e1000_sw_init(nic, card_number) < 0) { 3033 free(hw); 3034 free(nic); 3035 return 0; 3036 } 3037 #if !(defined(CONFIG_AP1000) || defined(CONFIG_MVBC_1G)) 3038 if (e1000_validate_eeprom_checksum(nic) < 0) { 3039 printf("The EEPROM Checksum Is Not Valid\n"); 3040 free(hw); 3041 free(nic); 3042 return 0; 3043 } 3044 #endif 3045 e1000_read_mac_addr(nic); 3046 3047 E1000_WRITE_REG(hw, PBA, E1000_DEFAULT_PBA); 3048 3049 printf("e1000: %02x:%02x:%02x:%02x:%02x:%02x\n", 3050 nic->enetaddr[0], nic->enetaddr[1], nic->enetaddr[2], 3051 nic->enetaddr[3], nic->enetaddr[4], nic->enetaddr[5]); 3052 3053 nic->init = e1000_init; 3054 nic->recv = e1000_poll; 3055 nic->send = e1000_transmit; 3056 nic->halt = e1000_disable; 3057 3058 eth_register(nic); 3059 3060 card_number++; 3061 } 3062 return card_number; 3063 } 3064