1 /************************************************************************** 2 Intel Pro 1000 for ppcboot/das-u-boot 3 Drivers are port from Intel's Linux driver e1000-4.3.15 4 and from Etherboot pro 1000 driver by mrakes at vivato dot net 5 tested on both gig copper and gig fiber boards 6 ***************************************************************************/ 7 /******************************************************************************* 8 9 10 Copyright(c) 1999 - 2002 Intel Corporation. All rights reserved. 11 12 * SPDX-License-Identifier: GPL-2.0+ 13 14 Contact Information: 15 Linux NICS <linux.nics@intel.com> 16 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 17 18 *******************************************************************************/ 19 /* 20 * Copyright (C) Archway Digital Solutions. 21 * 22 * written by Chrsitopher Li <cli at arcyway dot com> or <chrisl at gnuchina dot org> 23 * 2/9/2002 24 * 25 * Copyright (C) Linux Networx. 26 * Massive upgrade to work with the new intel gigabit NICs. 27 * <ebiederman at lnxi dot com> 28 * 29 * Copyright 2011 Freescale Semiconductor, Inc. 30 */ 31 32 #include "e1000.h" 33 34 #define TOUT_LOOP 100000 35 36 #define virt_to_bus(devno, v) pci_virt_to_mem(devno, (void *) (v)) 37 #define bus_to_phys(devno, a) pci_mem_to_phys(devno, a) 38 39 #define E1000_DEFAULT_PCI_PBA 0x00000030 40 #define E1000_DEFAULT_PCIE_PBA 0x000a0026 41 42 /* NIC specific static variables go here */ 43 44 /* Intel i210 needs the DMA descriptor rings aligned to 128b */ 45 #define E1000_BUFFER_ALIGN 128 46 47 DEFINE_ALIGN_BUFFER(struct e1000_tx_desc, tx_base, 16, E1000_BUFFER_ALIGN); 48 DEFINE_ALIGN_BUFFER(struct e1000_rx_desc, rx_base, 16, E1000_BUFFER_ALIGN); 49 DEFINE_ALIGN_BUFFER(unsigned char, packet, 4096, E1000_BUFFER_ALIGN); 50 51 static int tx_tail; 52 static int rx_tail, rx_last; 53 54 static struct pci_device_id e1000_supported[] = { 55 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82542}, 56 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82543GC_FIBER}, 57 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82543GC_COPPER}, 58 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544EI_COPPER}, 59 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544EI_FIBER}, 60 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544GC_COPPER}, 61 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544GC_LOM}, 62 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82540EM}, 63 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545EM_COPPER}, 64 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545GM_COPPER}, 65 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_COPPER}, 66 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545EM_FIBER}, 67 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_FIBER}, 68 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546GB_COPPER}, 69 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82540EM_LOM}, 70 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82541ER}, 71 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82541GI_LF}, 72 /* E1000 PCIe card */ 73 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_COPPER}, 74 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_FIBER }, 75 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES }, 76 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_COPPER}, 77 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571PT_QUAD_COPPER}, 78 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_FIBER}, 79 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_COPPER_LOWPROFILE}, 80 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES_DUAL}, 81 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES_QUAD}, 82 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_COPPER}, 83 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_FIBER}, 84 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_SERDES}, 85 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI}, 86 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573E}, 87 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573E_IAMT}, 88 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573L}, 89 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82574L}, 90 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546GB_QUAD_COPPER_KSP3}, 91 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_COPPER_DPT}, 92 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_SERDES_DPT}, 93 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_COPPER_SPT}, 94 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_SERDES_SPT}, 95 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_UNPROGRAMMED}, 96 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I211_UNPROGRAMMED}, 97 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_COPPER}, 98 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I211_COPPER}, 99 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_COPPER_FLASHLESS}, 100 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_SERDES}, 101 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_SERDES_FLASHLESS}, 102 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_1000BASEKX}, 103 104 {} 105 }; 106 107 /* Function forward declarations */ 108 static int e1000_setup_link(struct eth_device *nic); 109 static int e1000_setup_fiber_link(struct eth_device *nic); 110 static int e1000_setup_copper_link(struct eth_device *nic); 111 static int e1000_phy_setup_autoneg(struct e1000_hw *hw); 112 static void e1000_config_collision_dist(struct e1000_hw *hw); 113 static int e1000_config_mac_to_phy(struct e1000_hw *hw); 114 static int e1000_config_fc_after_link_up(struct e1000_hw *hw); 115 static int e1000_check_for_link(struct eth_device *nic); 116 static int e1000_wait_autoneg(struct e1000_hw *hw); 117 static int e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t * speed, 118 uint16_t * duplex); 119 static int e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, 120 uint16_t * phy_data); 121 static int e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, 122 uint16_t phy_data); 123 static int32_t e1000_phy_hw_reset(struct e1000_hw *hw); 124 static int e1000_phy_reset(struct e1000_hw *hw); 125 static int e1000_detect_gig_phy(struct e1000_hw *hw); 126 static void e1000_set_media_type(struct e1000_hw *hw); 127 128 static int32_t e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask); 129 static void e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask); 130 static int32_t e1000_check_phy_reset_block(struct e1000_hw *hw); 131 132 #ifndef CONFIG_E1000_NO_NVM 133 static void e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw); 134 static int32_t e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset, 135 uint16_t words, 136 uint16_t *data); 137 /****************************************************************************** 138 * Raises the EEPROM's clock input. 139 * 140 * hw - Struct containing variables accessed by shared code 141 * eecd - EECD's current value 142 *****************************************************************************/ 143 void e1000_raise_ee_clk(struct e1000_hw *hw, uint32_t * eecd) 144 { 145 /* Raise the clock input to the EEPROM (by setting the SK bit), and then 146 * wait 50 microseconds. 147 */ 148 *eecd = *eecd | E1000_EECD_SK; 149 E1000_WRITE_REG(hw, EECD, *eecd); 150 E1000_WRITE_FLUSH(hw); 151 udelay(50); 152 } 153 154 /****************************************************************************** 155 * Lowers the EEPROM's clock input. 156 * 157 * hw - Struct containing variables accessed by shared code 158 * eecd - EECD's current value 159 *****************************************************************************/ 160 void e1000_lower_ee_clk(struct e1000_hw *hw, uint32_t * eecd) 161 { 162 /* Lower the clock input to the EEPROM (by clearing the SK bit), and then 163 * wait 50 microseconds. 164 */ 165 *eecd = *eecd & ~E1000_EECD_SK; 166 E1000_WRITE_REG(hw, EECD, *eecd); 167 E1000_WRITE_FLUSH(hw); 168 udelay(50); 169 } 170 171 /****************************************************************************** 172 * Shift data bits out to the EEPROM. 173 * 174 * hw - Struct containing variables accessed by shared code 175 * data - data to send to the EEPROM 176 * count - number of bits to shift out 177 *****************************************************************************/ 178 static void 179 e1000_shift_out_ee_bits(struct e1000_hw *hw, uint16_t data, uint16_t count) 180 { 181 uint32_t eecd; 182 uint32_t mask; 183 184 /* We need to shift "count" bits out to the EEPROM. So, value in the 185 * "data" parameter will be shifted out to the EEPROM one bit at a time. 186 * In order to do this, "data" must be broken down into bits. 187 */ 188 mask = 0x01 << (count - 1); 189 eecd = E1000_READ_REG(hw, EECD); 190 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI); 191 do { 192 /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1", 193 * and then raising and then lowering the clock (the SK bit controls 194 * the clock input to the EEPROM). A "0" is shifted out to the EEPROM 195 * by setting "DI" to "0" and then raising and then lowering the clock. 196 */ 197 eecd &= ~E1000_EECD_DI; 198 199 if (data & mask) 200 eecd |= E1000_EECD_DI; 201 202 E1000_WRITE_REG(hw, EECD, eecd); 203 E1000_WRITE_FLUSH(hw); 204 205 udelay(50); 206 207 e1000_raise_ee_clk(hw, &eecd); 208 e1000_lower_ee_clk(hw, &eecd); 209 210 mask = mask >> 1; 211 212 } while (mask); 213 214 /* We leave the "DI" bit set to "0" when we leave this routine. */ 215 eecd &= ~E1000_EECD_DI; 216 E1000_WRITE_REG(hw, EECD, eecd); 217 } 218 219 /****************************************************************************** 220 * Shift data bits in from the EEPROM 221 * 222 * hw - Struct containing variables accessed by shared code 223 *****************************************************************************/ 224 static uint16_t 225 e1000_shift_in_ee_bits(struct e1000_hw *hw, uint16_t count) 226 { 227 uint32_t eecd; 228 uint32_t i; 229 uint16_t data; 230 231 /* In order to read a register from the EEPROM, we need to shift 'count' 232 * bits in from the EEPROM. Bits are "shifted in" by raising the clock 233 * input to the EEPROM (setting the SK bit), and then reading the 234 * value of the "DO" bit. During this "shifting in" process the 235 * "DI" bit should always be clear. 236 */ 237 238 eecd = E1000_READ_REG(hw, EECD); 239 240 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI); 241 data = 0; 242 243 for (i = 0; i < count; i++) { 244 data = data << 1; 245 e1000_raise_ee_clk(hw, &eecd); 246 247 eecd = E1000_READ_REG(hw, EECD); 248 249 eecd &= ~(E1000_EECD_DI); 250 if (eecd & E1000_EECD_DO) 251 data |= 1; 252 253 e1000_lower_ee_clk(hw, &eecd); 254 } 255 256 return data; 257 } 258 259 /****************************************************************************** 260 * Returns EEPROM to a "standby" state 261 * 262 * hw - Struct containing variables accessed by shared code 263 *****************************************************************************/ 264 void e1000_standby_eeprom(struct e1000_hw *hw) 265 { 266 struct e1000_eeprom_info *eeprom = &hw->eeprom; 267 uint32_t eecd; 268 269 eecd = E1000_READ_REG(hw, EECD); 270 271 if (eeprom->type == e1000_eeprom_microwire) { 272 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); 273 E1000_WRITE_REG(hw, EECD, eecd); 274 E1000_WRITE_FLUSH(hw); 275 udelay(eeprom->delay_usec); 276 277 /* Clock high */ 278 eecd |= E1000_EECD_SK; 279 E1000_WRITE_REG(hw, EECD, eecd); 280 E1000_WRITE_FLUSH(hw); 281 udelay(eeprom->delay_usec); 282 283 /* Select EEPROM */ 284 eecd |= E1000_EECD_CS; 285 E1000_WRITE_REG(hw, EECD, eecd); 286 E1000_WRITE_FLUSH(hw); 287 udelay(eeprom->delay_usec); 288 289 /* Clock low */ 290 eecd &= ~E1000_EECD_SK; 291 E1000_WRITE_REG(hw, EECD, eecd); 292 E1000_WRITE_FLUSH(hw); 293 udelay(eeprom->delay_usec); 294 } else if (eeprom->type == e1000_eeprom_spi) { 295 /* Toggle CS to flush commands */ 296 eecd |= E1000_EECD_CS; 297 E1000_WRITE_REG(hw, EECD, eecd); 298 E1000_WRITE_FLUSH(hw); 299 udelay(eeprom->delay_usec); 300 eecd &= ~E1000_EECD_CS; 301 E1000_WRITE_REG(hw, EECD, eecd); 302 E1000_WRITE_FLUSH(hw); 303 udelay(eeprom->delay_usec); 304 } 305 } 306 307 /*************************************************************************** 308 * Description: Determines if the onboard NVM is FLASH or EEPROM. 309 * 310 * hw - Struct containing variables accessed by shared code 311 ****************************************************************************/ 312 static bool e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw) 313 { 314 uint32_t eecd = 0; 315 316 DEBUGFUNC(); 317 318 if (hw->mac_type == e1000_ich8lan) 319 return false; 320 321 if (hw->mac_type == e1000_82573 || hw->mac_type == e1000_82574) { 322 eecd = E1000_READ_REG(hw, EECD); 323 324 /* Isolate bits 15 & 16 */ 325 eecd = ((eecd >> 15) & 0x03); 326 327 /* If both bits are set, device is Flash type */ 328 if (eecd == 0x03) 329 return false; 330 } 331 return true; 332 } 333 334 /****************************************************************************** 335 * Prepares EEPROM for access 336 * 337 * hw - Struct containing variables accessed by shared code 338 * 339 * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This 340 * function should be called before issuing a command to the EEPROM. 341 *****************************************************************************/ 342 int32_t e1000_acquire_eeprom(struct e1000_hw *hw) 343 { 344 struct e1000_eeprom_info *eeprom = &hw->eeprom; 345 uint32_t eecd, i = 0; 346 347 DEBUGFUNC(); 348 349 if (e1000_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM)) 350 return -E1000_ERR_SWFW_SYNC; 351 eecd = E1000_READ_REG(hw, EECD); 352 353 if (hw->mac_type != e1000_82573 && hw->mac_type != e1000_82574) { 354 /* Request EEPROM Access */ 355 if (hw->mac_type > e1000_82544) { 356 eecd |= E1000_EECD_REQ; 357 E1000_WRITE_REG(hw, EECD, eecd); 358 eecd = E1000_READ_REG(hw, EECD); 359 while ((!(eecd & E1000_EECD_GNT)) && 360 (i < E1000_EEPROM_GRANT_ATTEMPTS)) { 361 i++; 362 udelay(5); 363 eecd = E1000_READ_REG(hw, EECD); 364 } 365 if (!(eecd & E1000_EECD_GNT)) { 366 eecd &= ~E1000_EECD_REQ; 367 E1000_WRITE_REG(hw, EECD, eecd); 368 DEBUGOUT("Could not acquire EEPROM grant\n"); 369 return -E1000_ERR_EEPROM; 370 } 371 } 372 } 373 374 /* Setup EEPROM for Read/Write */ 375 376 if (eeprom->type == e1000_eeprom_microwire) { 377 /* Clear SK and DI */ 378 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK); 379 E1000_WRITE_REG(hw, EECD, eecd); 380 381 /* Set CS */ 382 eecd |= E1000_EECD_CS; 383 E1000_WRITE_REG(hw, EECD, eecd); 384 } else if (eeprom->type == e1000_eeprom_spi) { 385 /* Clear SK and CS */ 386 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); 387 E1000_WRITE_REG(hw, EECD, eecd); 388 udelay(1); 389 } 390 391 return E1000_SUCCESS; 392 } 393 394 /****************************************************************************** 395 * Sets up eeprom variables in the hw struct. Must be called after mac_type 396 * is configured. Additionally, if this is ICH8, the flash controller GbE 397 * registers must be mapped, or this will crash. 398 * 399 * hw - Struct containing variables accessed by shared code 400 *****************************************************************************/ 401 static int32_t e1000_init_eeprom_params(struct e1000_hw *hw) 402 { 403 struct e1000_eeprom_info *eeprom = &hw->eeprom; 404 uint32_t eecd; 405 int32_t ret_val = E1000_SUCCESS; 406 uint16_t eeprom_size; 407 408 if (hw->mac_type == e1000_igb) 409 eecd = E1000_READ_REG(hw, I210_EECD); 410 else 411 eecd = E1000_READ_REG(hw, EECD); 412 413 DEBUGFUNC(); 414 415 switch (hw->mac_type) { 416 case e1000_82542_rev2_0: 417 case e1000_82542_rev2_1: 418 case e1000_82543: 419 case e1000_82544: 420 eeprom->type = e1000_eeprom_microwire; 421 eeprom->word_size = 64; 422 eeprom->opcode_bits = 3; 423 eeprom->address_bits = 6; 424 eeprom->delay_usec = 50; 425 eeprom->use_eerd = false; 426 eeprom->use_eewr = false; 427 break; 428 case e1000_82540: 429 case e1000_82545: 430 case e1000_82545_rev_3: 431 case e1000_82546: 432 case e1000_82546_rev_3: 433 eeprom->type = e1000_eeprom_microwire; 434 eeprom->opcode_bits = 3; 435 eeprom->delay_usec = 50; 436 if (eecd & E1000_EECD_SIZE) { 437 eeprom->word_size = 256; 438 eeprom->address_bits = 8; 439 } else { 440 eeprom->word_size = 64; 441 eeprom->address_bits = 6; 442 } 443 eeprom->use_eerd = false; 444 eeprom->use_eewr = false; 445 break; 446 case e1000_82541: 447 case e1000_82541_rev_2: 448 case e1000_82547: 449 case e1000_82547_rev_2: 450 if (eecd & E1000_EECD_TYPE) { 451 eeprom->type = e1000_eeprom_spi; 452 eeprom->opcode_bits = 8; 453 eeprom->delay_usec = 1; 454 if (eecd & E1000_EECD_ADDR_BITS) { 455 eeprom->page_size = 32; 456 eeprom->address_bits = 16; 457 } else { 458 eeprom->page_size = 8; 459 eeprom->address_bits = 8; 460 } 461 } else { 462 eeprom->type = e1000_eeprom_microwire; 463 eeprom->opcode_bits = 3; 464 eeprom->delay_usec = 50; 465 if (eecd & E1000_EECD_ADDR_BITS) { 466 eeprom->word_size = 256; 467 eeprom->address_bits = 8; 468 } else { 469 eeprom->word_size = 64; 470 eeprom->address_bits = 6; 471 } 472 } 473 eeprom->use_eerd = false; 474 eeprom->use_eewr = false; 475 break; 476 case e1000_82571: 477 case e1000_82572: 478 eeprom->type = e1000_eeprom_spi; 479 eeprom->opcode_bits = 8; 480 eeprom->delay_usec = 1; 481 if (eecd & E1000_EECD_ADDR_BITS) { 482 eeprom->page_size = 32; 483 eeprom->address_bits = 16; 484 } else { 485 eeprom->page_size = 8; 486 eeprom->address_bits = 8; 487 } 488 eeprom->use_eerd = false; 489 eeprom->use_eewr = false; 490 break; 491 case e1000_82573: 492 case e1000_82574: 493 eeprom->type = e1000_eeprom_spi; 494 eeprom->opcode_bits = 8; 495 eeprom->delay_usec = 1; 496 if (eecd & E1000_EECD_ADDR_BITS) { 497 eeprom->page_size = 32; 498 eeprom->address_bits = 16; 499 } else { 500 eeprom->page_size = 8; 501 eeprom->address_bits = 8; 502 } 503 if (e1000_is_onboard_nvm_eeprom(hw) == false) { 504 eeprom->use_eerd = true; 505 eeprom->use_eewr = true; 506 507 eeprom->type = e1000_eeprom_flash; 508 eeprom->word_size = 2048; 509 510 /* Ensure that the Autonomous FLASH update bit is cleared due to 511 * Flash update issue on parts which use a FLASH for NVM. */ 512 eecd &= ~E1000_EECD_AUPDEN; 513 E1000_WRITE_REG(hw, EECD, eecd); 514 } 515 break; 516 case e1000_80003es2lan: 517 eeprom->type = e1000_eeprom_spi; 518 eeprom->opcode_bits = 8; 519 eeprom->delay_usec = 1; 520 if (eecd & E1000_EECD_ADDR_BITS) { 521 eeprom->page_size = 32; 522 eeprom->address_bits = 16; 523 } else { 524 eeprom->page_size = 8; 525 eeprom->address_bits = 8; 526 } 527 eeprom->use_eerd = true; 528 eeprom->use_eewr = false; 529 break; 530 case e1000_igb: 531 /* i210 has 4k of iNVM mapped as EEPROM */ 532 eeprom->type = e1000_eeprom_invm; 533 eeprom->opcode_bits = 8; 534 eeprom->delay_usec = 1; 535 eeprom->page_size = 32; 536 eeprom->address_bits = 16; 537 eeprom->use_eerd = true; 538 eeprom->use_eewr = false; 539 break; 540 541 /* ich8lan does not support currently. if needed, please 542 * add corresponding code and functions. 543 */ 544 #if 0 545 case e1000_ich8lan: 546 { 547 int32_t i = 0; 548 549 eeprom->type = e1000_eeprom_ich8; 550 eeprom->use_eerd = false; 551 eeprom->use_eewr = false; 552 eeprom->word_size = E1000_SHADOW_RAM_WORDS; 553 uint32_t flash_size = E1000_READ_ICH_FLASH_REG(hw, 554 ICH_FLASH_GFPREG); 555 /* Zero the shadow RAM structure. But don't load it from NVM 556 * so as to save time for driver init */ 557 if (hw->eeprom_shadow_ram != NULL) { 558 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) { 559 hw->eeprom_shadow_ram[i].modified = false; 560 hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF; 561 } 562 } 563 564 hw->flash_base_addr = (flash_size & ICH_GFPREG_BASE_MASK) * 565 ICH_FLASH_SECTOR_SIZE; 566 567 hw->flash_bank_size = ((flash_size >> 16) 568 & ICH_GFPREG_BASE_MASK) + 1; 569 hw->flash_bank_size -= (flash_size & ICH_GFPREG_BASE_MASK); 570 571 hw->flash_bank_size *= ICH_FLASH_SECTOR_SIZE; 572 573 hw->flash_bank_size /= 2 * sizeof(uint16_t); 574 break; 575 } 576 #endif 577 default: 578 break; 579 } 580 581 if (eeprom->type == e1000_eeprom_spi || 582 eeprom->type == e1000_eeprom_invm) { 583 /* eeprom_size will be an enum [0..8] that maps 584 * to eeprom sizes 128B to 585 * 32KB (incremented by powers of 2). 586 */ 587 if (hw->mac_type <= e1000_82547_rev_2) { 588 /* Set to default value for initial eeprom read. */ 589 eeprom->word_size = 64; 590 ret_val = e1000_read_eeprom(hw, EEPROM_CFG, 1, 591 &eeprom_size); 592 if (ret_val) 593 return ret_val; 594 eeprom_size = (eeprom_size & EEPROM_SIZE_MASK) 595 >> EEPROM_SIZE_SHIFT; 596 /* 256B eeprom size was not supported in earlier 597 * hardware, so we bump eeprom_size up one to 598 * ensure that "1" (which maps to 256B) is never 599 * the result used in the shifting logic below. */ 600 if (eeprom_size) 601 eeprom_size++; 602 } else { 603 eeprom_size = (uint16_t)((eecd & 604 E1000_EECD_SIZE_EX_MASK) >> 605 E1000_EECD_SIZE_EX_SHIFT); 606 } 607 608 eeprom->word_size = 1 << (eeprom_size + EEPROM_WORD_SIZE_SHIFT); 609 } 610 return ret_val; 611 } 612 613 /****************************************************************************** 614 * Polls the status bit (bit 1) of the EERD to determine when the read is done. 615 * 616 * hw - Struct containing variables accessed by shared code 617 *****************************************************************************/ 618 static int32_t 619 e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd) 620 { 621 uint32_t attempts = 100000; 622 uint32_t i, reg = 0; 623 int32_t done = E1000_ERR_EEPROM; 624 625 for (i = 0; i < attempts; i++) { 626 if (eerd == E1000_EEPROM_POLL_READ) { 627 if (hw->mac_type == e1000_igb) 628 reg = E1000_READ_REG(hw, I210_EERD); 629 else 630 reg = E1000_READ_REG(hw, EERD); 631 } else { 632 if (hw->mac_type == e1000_igb) 633 reg = E1000_READ_REG(hw, I210_EEWR); 634 else 635 reg = E1000_READ_REG(hw, EEWR); 636 } 637 638 if (reg & E1000_EEPROM_RW_REG_DONE) { 639 done = E1000_SUCCESS; 640 break; 641 } 642 udelay(5); 643 } 644 645 return done; 646 } 647 648 /****************************************************************************** 649 * Reads a 16 bit word from the EEPROM using the EERD register. 650 * 651 * hw - Struct containing variables accessed by shared code 652 * offset - offset of word in the EEPROM to read 653 * data - word read from the EEPROM 654 * words - number of words to read 655 *****************************************************************************/ 656 static int32_t 657 e1000_read_eeprom_eerd(struct e1000_hw *hw, 658 uint16_t offset, 659 uint16_t words, 660 uint16_t *data) 661 { 662 uint32_t i, eerd = 0; 663 int32_t error = 0; 664 665 for (i = 0; i < words; i++) { 666 eerd = ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) + 667 E1000_EEPROM_RW_REG_START; 668 669 if (hw->mac_type == e1000_igb) 670 E1000_WRITE_REG(hw, I210_EERD, eerd); 671 else 672 E1000_WRITE_REG(hw, EERD, eerd); 673 674 error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_READ); 675 676 if (error) 677 break; 678 679 if (hw->mac_type == e1000_igb) { 680 data[i] = (E1000_READ_REG(hw, I210_EERD) >> 681 E1000_EEPROM_RW_REG_DATA); 682 } else { 683 data[i] = (E1000_READ_REG(hw, EERD) >> 684 E1000_EEPROM_RW_REG_DATA); 685 } 686 687 } 688 689 return error; 690 } 691 692 void e1000_release_eeprom(struct e1000_hw *hw) 693 { 694 uint32_t eecd; 695 696 DEBUGFUNC(); 697 698 eecd = E1000_READ_REG(hw, EECD); 699 700 if (hw->eeprom.type == e1000_eeprom_spi) { 701 eecd |= E1000_EECD_CS; /* Pull CS high */ 702 eecd &= ~E1000_EECD_SK; /* Lower SCK */ 703 704 E1000_WRITE_REG(hw, EECD, eecd); 705 706 udelay(hw->eeprom.delay_usec); 707 } else if (hw->eeprom.type == e1000_eeprom_microwire) { 708 /* cleanup eeprom */ 709 710 /* CS on Microwire is active-high */ 711 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI); 712 713 E1000_WRITE_REG(hw, EECD, eecd); 714 715 /* Rising edge of clock */ 716 eecd |= E1000_EECD_SK; 717 E1000_WRITE_REG(hw, EECD, eecd); 718 E1000_WRITE_FLUSH(hw); 719 udelay(hw->eeprom.delay_usec); 720 721 /* Falling edge of clock */ 722 eecd &= ~E1000_EECD_SK; 723 E1000_WRITE_REG(hw, EECD, eecd); 724 E1000_WRITE_FLUSH(hw); 725 udelay(hw->eeprom.delay_usec); 726 } 727 728 /* Stop requesting EEPROM access */ 729 if (hw->mac_type > e1000_82544) { 730 eecd &= ~E1000_EECD_REQ; 731 E1000_WRITE_REG(hw, EECD, eecd); 732 } 733 734 e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM); 735 } 736 737 /****************************************************************************** 738 * Reads a 16 bit word from the EEPROM. 739 * 740 * hw - Struct containing variables accessed by shared code 741 *****************************************************************************/ 742 static int32_t 743 e1000_spi_eeprom_ready(struct e1000_hw *hw) 744 { 745 uint16_t retry_count = 0; 746 uint8_t spi_stat_reg; 747 748 DEBUGFUNC(); 749 750 /* Read "Status Register" repeatedly until the LSB is cleared. The 751 * EEPROM will signal that the command has been completed by clearing 752 * bit 0 of the internal status register. If it's not cleared within 753 * 5 milliseconds, then error out. 754 */ 755 retry_count = 0; 756 do { 757 e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI, 758 hw->eeprom.opcode_bits); 759 spi_stat_reg = (uint8_t)e1000_shift_in_ee_bits(hw, 8); 760 if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI)) 761 break; 762 763 udelay(5); 764 retry_count += 5; 765 766 e1000_standby_eeprom(hw); 767 } while (retry_count < EEPROM_MAX_RETRY_SPI); 768 769 /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and 770 * only 0-5mSec on 5V devices) 771 */ 772 if (retry_count >= EEPROM_MAX_RETRY_SPI) { 773 DEBUGOUT("SPI EEPROM Status error\n"); 774 return -E1000_ERR_EEPROM; 775 } 776 777 return E1000_SUCCESS; 778 } 779 780 /****************************************************************************** 781 * Reads a 16 bit word from the EEPROM. 782 * 783 * hw - Struct containing variables accessed by shared code 784 * offset - offset of word in the EEPROM to read 785 * data - word read from the EEPROM 786 *****************************************************************************/ 787 static int32_t 788 e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset, 789 uint16_t words, uint16_t *data) 790 { 791 struct e1000_eeprom_info *eeprom = &hw->eeprom; 792 uint32_t i = 0; 793 794 DEBUGFUNC(); 795 796 /* If eeprom is not yet detected, do so now */ 797 if (eeprom->word_size == 0) 798 e1000_init_eeprom_params(hw); 799 800 /* A check for invalid values: offset too large, too many words, 801 * and not enough words. 802 */ 803 if ((offset >= eeprom->word_size) || 804 (words > eeprom->word_size - offset) || 805 (words == 0)) { 806 DEBUGOUT("\"words\" parameter out of bounds." 807 "Words = %d, size = %d\n", offset, eeprom->word_size); 808 return -E1000_ERR_EEPROM; 809 } 810 811 /* EEPROM's that don't use EERD to read require us to bit-bang the SPI 812 * directly. In this case, we need to acquire the EEPROM so that 813 * FW or other port software does not interrupt. 814 */ 815 if (e1000_is_onboard_nvm_eeprom(hw) == true && 816 hw->eeprom.use_eerd == false) { 817 818 /* Prepare the EEPROM for bit-bang reading */ 819 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS) 820 return -E1000_ERR_EEPROM; 821 } 822 823 /* Eerd register EEPROM access requires no eeprom aquire/release */ 824 if (eeprom->use_eerd == true) 825 return e1000_read_eeprom_eerd(hw, offset, words, data); 826 827 /* ich8lan does not support currently. if needed, please 828 * add corresponding code and functions. 829 */ 830 #if 0 831 /* ICH EEPROM access is done via the ICH flash controller */ 832 if (eeprom->type == e1000_eeprom_ich8) 833 return e1000_read_eeprom_ich8(hw, offset, words, data); 834 #endif 835 /* Set up the SPI or Microwire EEPROM for bit-bang reading. We have 836 * acquired the EEPROM at this point, so any returns should relase it */ 837 if (eeprom->type == e1000_eeprom_spi) { 838 uint16_t word_in; 839 uint8_t read_opcode = EEPROM_READ_OPCODE_SPI; 840 841 if (e1000_spi_eeprom_ready(hw)) { 842 e1000_release_eeprom(hw); 843 return -E1000_ERR_EEPROM; 844 } 845 846 e1000_standby_eeprom(hw); 847 848 /* Some SPI eeproms use the 8th address bit embedded in 849 * the opcode */ 850 if ((eeprom->address_bits == 8) && (offset >= 128)) 851 read_opcode |= EEPROM_A8_OPCODE_SPI; 852 853 /* Send the READ command (opcode + addr) */ 854 e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits); 855 e1000_shift_out_ee_bits(hw, (uint16_t)(offset*2), 856 eeprom->address_bits); 857 858 /* Read the data. The address of the eeprom internally 859 * increments with each byte (spi) being read, saving on the 860 * overhead of eeprom setup and tear-down. The address 861 * counter will roll over if reading beyond the size of 862 * the eeprom, thus allowing the entire memory to be read 863 * starting from any offset. */ 864 for (i = 0; i < words; i++) { 865 word_in = e1000_shift_in_ee_bits(hw, 16); 866 data[i] = (word_in >> 8) | (word_in << 8); 867 } 868 } else if (eeprom->type == e1000_eeprom_microwire) { 869 for (i = 0; i < words; i++) { 870 /* Send the READ command (opcode + addr) */ 871 e1000_shift_out_ee_bits(hw, 872 EEPROM_READ_OPCODE_MICROWIRE, 873 eeprom->opcode_bits); 874 e1000_shift_out_ee_bits(hw, (uint16_t)(offset + i), 875 eeprom->address_bits); 876 877 /* Read the data. For microwire, each word requires 878 * the overhead of eeprom setup and tear-down. */ 879 data[i] = e1000_shift_in_ee_bits(hw, 16); 880 e1000_standby_eeprom(hw); 881 } 882 } 883 884 /* End this read operation */ 885 e1000_release_eeprom(hw); 886 887 return E1000_SUCCESS; 888 } 889 890 /****************************************************************************** 891 * Verifies that the EEPROM has a valid checksum 892 * 893 * hw - Struct containing variables accessed by shared code 894 * 895 * Reads the first 64 16 bit words of the EEPROM and sums the values read. 896 * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is 897 * valid. 898 *****************************************************************************/ 899 static int e1000_validate_eeprom_checksum(struct e1000_hw *hw) 900 { 901 uint16_t i, checksum, checksum_reg, *buf; 902 903 DEBUGFUNC(); 904 905 /* Allocate a temporary buffer */ 906 buf = malloc(sizeof(buf[0]) * (EEPROM_CHECKSUM_REG + 1)); 907 if (!buf) { 908 E1000_ERR(hw->nic, "Unable to allocate EEPROM buffer!\n"); 909 return -E1000_ERR_EEPROM; 910 } 911 912 /* Read the EEPROM */ 913 if (e1000_read_eeprom(hw, 0, EEPROM_CHECKSUM_REG + 1, buf) < 0) { 914 E1000_ERR(hw->nic, "Unable to read EEPROM!\n"); 915 return -E1000_ERR_EEPROM; 916 } 917 918 /* Compute the checksum */ 919 checksum = 0; 920 for (i = 0; i < EEPROM_CHECKSUM_REG; i++) 921 checksum += buf[i]; 922 checksum = ((uint16_t)EEPROM_SUM) - checksum; 923 checksum_reg = buf[i]; 924 925 /* Verify it! */ 926 if (checksum == checksum_reg) 927 return 0; 928 929 /* Hrm, verification failed, print an error */ 930 E1000_ERR(hw->nic, "EEPROM checksum is incorrect!\n"); 931 E1000_ERR(hw->nic, " ...register was 0x%04hx, calculated 0x%04hx\n", 932 checksum_reg, checksum); 933 934 return -E1000_ERR_EEPROM; 935 } 936 #endif /* CONFIG_E1000_NO_NVM */ 937 938 /***************************************************************************** 939 * Set PHY to class A mode 940 * Assumes the following operations will follow to enable the new class mode. 941 * 1. Do a PHY soft reset 942 * 2. Restart auto-negotiation or force link. 943 * 944 * hw - Struct containing variables accessed by shared code 945 ****************************************************************************/ 946 static int32_t 947 e1000_set_phy_mode(struct e1000_hw *hw) 948 { 949 #ifndef CONFIG_E1000_NO_NVM 950 int32_t ret_val; 951 uint16_t eeprom_data; 952 953 DEBUGFUNC(); 954 955 if ((hw->mac_type == e1000_82545_rev_3) && 956 (hw->media_type == e1000_media_type_copper)) { 957 ret_val = e1000_read_eeprom(hw, EEPROM_PHY_CLASS_WORD, 958 1, &eeprom_data); 959 if (ret_val) 960 return ret_val; 961 962 if ((eeprom_data != EEPROM_RESERVED_WORD) && 963 (eeprom_data & EEPROM_PHY_CLASS_A)) { 964 ret_val = e1000_write_phy_reg(hw, 965 M88E1000_PHY_PAGE_SELECT, 0x000B); 966 if (ret_val) 967 return ret_val; 968 ret_val = e1000_write_phy_reg(hw, 969 M88E1000_PHY_GEN_CONTROL, 0x8104); 970 if (ret_val) 971 return ret_val; 972 973 hw->phy_reset_disable = false; 974 } 975 } 976 #endif 977 return E1000_SUCCESS; 978 } 979 980 #ifndef CONFIG_E1000_NO_NVM 981 /*************************************************************************** 982 * 983 * Obtaining software semaphore bit (SMBI) before resetting PHY. 984 * 985 * hw: Struct containing variables accessed by shared code 986 * 987 * returns: - E1000_ERR_RESET if fail to obtain semaphore. 988 * E1000_SUCCESS at any other case. 989 * 990 ***************************************************************************/ 991 static int32_t 992 e1000_get_software_semaphore(struct e1000_hw *hw) 993 { 994 int32_t timeout = hw->eeprom.word_size + 1; 995 uint32_t swsm; 996 997 DEBUGFUNC(); 998 999 if (hw->mac_type != e1000_80003es2lan) 1000 return E1000_SUCCESS; 1001 1002 while (timeout) { 1003 swsm = E1000_READ_REG(hw, SWSM); 1004 /* If SMBI bit cleared, it is now set and we hold 1005 * the semaphore */ 1006 if (!(swsm & E1000_SWSM_SMBI)) 1007 break; 1008 mdelay(1); 1009 timeout--; 1010 } 1011 1012 if (!timeout) { 1013 DEBUGOUT("Driver can't access device - SMBI bit is set.\n"); 1014 return -E1000_ERR_RESET; 1015 } 1016 1017 return E1000_SUCCESS; 1018 } 1019 #endif 1020 1021 /*************************************************************************** 1022 * This function clears HW semaphore bits. 1023 * 1024 * hw: Struct containing variables accessed by shared code 1025 * 1026 * returns: - None. 1027 * 1028 ***************************************************************************/ 1029 static void 1030 e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw) 1031 { 1032 #ifndef CONFIG_E1000_NO_NVM 1033 uint32_t swsm; 1034 1035 DEBUGFUNC(); 1036 1037 if (!hw->eeprom_semaphore_present) 1038 return; 1039 1040 swsm = E1000_READ_REG(hw, SWSM); 1041 if (hw->mac_type == e1000_80003es2lan) { 1042 /* Release both semaphores. */ 1043 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI); 1044 } else 1045 swsm &= ~(E1000_SWSM_SWESMBI); 1046 E1000_WRITE_REG(hw, SWSM, swsm); 1047 #endif 1048 } 1049 1050 /*************************************************************************** 1051 * 1052 * Using the combination of SMBI and SWESMBI semaphore bits when resetting 1053 * adapter or Eeprom access. 1054 * 1055 * hw: Struct containing variables accessed by shared code 1056 * 1057 * returns: - E1000_ERR_EEPROM if fail to access EEPROM. 1058 * E1000_SUCCESS at any other case. 1059 * 1060 ***************************************************************************/ 1061 static int32_t 1062 e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw) 1063 { 1064 #ifndef CONFIG_E1000_NO_NVM 1065 int32_t timeout; 1066 uint32_t swsm; 1067 1068 DEBUGFUNC(); 1069 1070 if (!hw->eeprom_semaphore_present) 1071 return E1000_SUCCESS; 1072 1073 if (hw->mac_type == e1000_80003es2lan) { 1074 /* Get the SW semaphore. */ 1075 if (e1000_get_software_semaphore(hw) != E1000_SUCCESS) 1076 return -E1000_ERR_EEPROM; 1077 } 1078 1079 /* Get the FW semaphore. */ 1080 timeout = hw->eeprom.word_size + 1; 1081 while (timeout) { 1082 swsm = E1000_READ_REG(hw, SWSM); 1083 swsm |= E1000_SWSM_SWESMBI; 1084 E1000_WRITE_REG(hw, SWSM, swsm); 1085 /* if we managed to set the bit we got the semaphore. */ 1086 swsm = E1000_READ_REG(hw, SWSM); 1087 if (swsm & E1000_SWSM_SWESMBI) 1088 break; 1089 1090 udelay(50); 1091 timeout--; 1092 } 1093 1094 if (!timeout) { 1095 /* Release semaphores */ 1096 e1000_put_hw_eeprom_semaphore(hw); 1097 DEBUGOUT("Driver can't access the Eeprom - " 1098 "SWESMBI bit is set.\n"); 1099 return -E1000_ERR_EEPROM; 1100 } 1101 #endif 1102 return E1000_SUCCESS; 1103 } 1104 1105 /* Take ownership of the PHY */ 1106 static int32_t 1107 e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask) 1108 { 1109 uint32_t swfw_sync = 0; 1110 uint32_t swmask = mask; 1111 uint32_t fwmask = mask << 16; 1112 int32_t timeout = 200; 1113 1114 DEBUGFUNC(); 1115 while (timeout) { 1116 if (e1000_get_hw_eeprom_semaphore(hw)) 1117 return -E1000_ERR_SWFW_SYNC; 1118 1119 swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC); 1120 if (!(swfw_sync & (fwmask | swmask))) 1121 break; 1122 1123 /* firmware currently using resource (fwmask) */ 1124 /* or other software thread currently using resource (swmask) */ 1125 e1000_put_hw_eeprom_semaphore(hw); 1126 mdelay(5); 1127 timeout--; 1128 } 1129 1130 if (!timeout) { 1131 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n"); 1132 return -E1000_ERR_SWFW_SYNC; 1133 } 1134 1135 swfw_sync |= swmask; 1136 E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync); 1137 1138 e1000_put_hw_eeprom_semaphore(hw); 1139 return E1000_SUCCESS; 1140 } 1141 1142 static void e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask) 1143 { 1144 uint32_t swfw_sync = 0; 1145 1146 DEBUGFUNC(); 1147 while (e1000_get_hw_eeprom_semaphore(hw)) 1148 ; /* Empty */ 1149 1150 swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC); 1151 swfw_sync &= ~mask; 1152 E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync); 1153 1154 e1000_put_hw_eeprom_semaphore(hw); 1155 } 1156 1157 static bool e1000_is_second_port(struct e1000_hw *hw) 1158 { 1159 switch (hw->mac_type) { 1160 case e1000_80003es2lan: 1161 case e1000_82546: 1162 case e1000_82571: 1163 if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1) 1164 return true; 1165 /* Fallthrough */ 1166 default: 1167 return false; 1168 } 1169 } 1170 1171 #ifndef CONFIG_E1000_NO_NVM 1172 /****************************************************************************** 1173 * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the 1174 * second function of dual function devices 1175 * 1176 * nic - Struct containing variables accessed by shared code 1177 *****************************************************************************/ 1178 static int 1179 e1000_read_mac_addr(struct eth_device *nic) 1180 { 1181 struct e1000_hw *hw = nic->priv; 1182 uint16_t offset; 1183 uint16_t eeprom_data; 1184 uint32_t reg_data = 0; 1185 int i; 1186 1187 DEBUGFUNC(); 1188 1189 for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) { 1190 offset = i >> 1; 1191 if (hw->mac_type == e1000_igb) { 1192 /* i210 preloads MAC address into RAL/RAH registers */ 1193 if (offset == 0) 1194 reg_data = E1000_READ_REG_ARRAY(hw, RA, 0); 1195 else if (offset == 1) 1196 reg_data >>= 16; 1197 else if (offset == 2) 1198 reg_data = E1000_READ_REG_ARRAY(hw, RA, 1); 1199 eeprom_data = reg_data & 0xffff; 1200 } else if (e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) { 1201 DEBUGOUT("EEPROM Read Error\n"); 1202 return -E1000_ERR_EEPROM; 1203 } 1204 nic->enetaddr[i] = eeprom_data & 0xff; 1205 nic->enetaddr[i + 1] = (eeprom_data >> 8) & 0xff; 1206 } 1207 1208 /* Invert the last bit if this is the second device */ 1209 if (e1000_is_second_port(hw)) 1210 nic->enetaddr[5] ^= 1; 1211 1212 #ifdef CONFIG_E1000_FALLBACK_MAC 1213 if (!is_valid_ethaddr(nic->enetaddr)) { 1214 unsigned char fb_mac[NODE_ADDRESS_SIZE] = CONFIG_E1000_FALLBACK_MAC; 1215 1216 memcpy (nic->enetaddr, fb_mac, NODE_ADDRESS_SIZE); 1217 } 1218 #endif 1219 return 0; 1220 } 1221 #endif 1222 1223 /****************************************************************************** 1224 * Initializes receive address filters. 1225 * 1226 * hw - Struct containing variables accessed by shared code 1227 * 1228 * Places the MAC address in receive address register 0 and clears the rest 1229 * of the receive addresss registers. Clears the multicast table. Assumes 1230 * the receiver is in reset when the routine is called. 1231 *****************************************************************************/ 1232 static void 1233 e1000_init_rx_addrs(struct eth_device *nic) 1234 { 1235 struct e1000_hw *hw = nic->priv; 1236 uint32_t i; 1237 uint32_t addr_low; 1238 uint32_t addr_high; 1239 1240 DEBUGFUNC(); 1241 1242 /* Setup the receive address. */ 1243 DEBUGOUT("Programming MAC Address into RAR[0]\n"); 1244 addr_low = (nic->enetaddr[0] | 1245 (nic->enetaddr[1] << 8) | 1246 (nic->enetaddr[2] << 16) | (nic->enetaddr[3] << 24)); 1247 1248 addr_high = (nic->enetaddr[4] | (nic->enetaddr[5] << 8) | E1000_RAH_AV); 1249 1250 E1000_WRITE_REG_ARRAY(hw, RA, 0, addr_low); 1251 E1000_WRITE_REG_ARRAY(hw, RA, 1, addr_high); 1252 1253 /* Zero out the other 15 receive addresses. */ 1254 DEBUGOUT("Clearing RAR[1-15]\n"); 1255 for (i = 1; i < E1000_RAR_ENTRIES; i++) { 1256 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0); 1257 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0); 1258 } 1259 } 1260 1261 /****************************************************************************** 1262 * Clears the VLAN filer table 1263 * 1264 * hw - Struct containing variables accessed by shared code 1265 *****************************************************************************/ 1266 static void 1267 e1000_clear_vfta(struct e1000_hw *hw) 1268 { 1269 uint32_t offset; 1270 1271 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) 1272 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, 0); 1273 } 1274 1275 /****************************************************************************** 1276 * Set the mac type member in the hw struct. 1277 * 1278 * hw - Struct containing variables accessed by shared code 1279 *****************************************************************************/ 1280 int32_t 1281 e1000_set_mac_type(struct e1000_hw *hw) 1282 { 1283 DEBUGFUNC(); 1284 1285 switch (hw->device_id) { 1286 case E1000_DEV_ID_82542: 1287 switch (hw->revision_id) { 1288 case E1000_82542_2_0_REV_ID: 1289 hw->mac_type = e1000_82542_rev2_0; 1290 break; 1291 case E1000_82542_2_1_REV_ID: 1292 hw->mac_type = e1000_82542_rev2_1; 1293 break; 1294 default: 1295 /* Invalid 82542 revision ID */ 1296 return -E1000_ERR_MAC_TYPE; 1297 } 1298 break; 1299 case E1000_DEV_ID_82543GC_FIBER: 1300 case E1000_DEV_ID_82543GC_COPPER: 1301 hw->mac_type = e1000_82543; 1302 break; 1303 case E1000_DEV_ID_82544EI_COPPER: 1304 case E1000_DEV_ID_82544EI_FIBER: 1305 case E1000_DEV_ID_82544GC_COPPER: 1306 case E1000_DEV_ID_82544GC_LOM: 1307 hw->mac_type = e1000_82544; 1308 break; 1309 case E1000_DEV_ID_82540EM: 1310 case E1000_DEV_ID_82540EM_LOM: 1311 case E1000_DEV_ID_82540EP: 1312 case E1000_DEV_ID_82540EP_LOM: 1313 case E1000_DEV_ID_82540EP_LP: 1314 hw->mac_type = e1000_82540; 1315 break; 1316 case E1000_DEV_ID_82545EM_COPPER: 1317 case E1000_DEV_ID_82545EM_FIBER: 1318 hw->mac_type = e1000_82545; 1319 break; 1320 case E1000_DEV_ID_82545GM_COPPER: 1321 case E1000_DEV_ID_82545GM_FIBER: 1322 case E1000_DEV_ID_82545GM_SERDES: 1323 hw->mac_type = e1000_82545_rev_3; 1324 break; 1325 case E1000_DEV_ID_82546EB_COPPER: 1326 case E1000_DEV_ID_82546EB_FIBER: 1327 case E1000_DEV_ID_82546EB_QUAD_COPPER: 1328 hw->mac_type = e1000_82546; 1329 break; 1330 case E1000_DEV_ID_82546GB_COPPER: 1331 case E1000_DEV_ID_82546GB_FIBER: 1332 case E1000_DEV_ID_82546GB_SERDES: 1333 case E1000_DEV_ID_82546GB_PCIE: 1334 case E1000_DEV_ID_82546GB_QUAD_COPPER: 1335 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3: 1336 hw->mac_type = e1000_82546_rev_3; 1337 break; 1338 case E1000_DEV_ID_82541EI: 1339 case E1000_DEV_ID_82541EI_MOBILE: 1340 case E1000_DEV_ID_82541ER_LOM: 1341 hw->mac_type = e1000_82541; 1342 break; 1343 case E1000_DEV_ID_82541ER: 1344 case E1000_DEV_ID_82541GI: 1345 case E1000_DEV_ID_82541GI_LF: 1346 case E1000_DEV_ID_82541GI_MOBILE: 1347 hw->mac_type = e1000_82541_rev_2; 1348 break; 1349 case E1000_DEV_ID_82547EI: 1350 case E1000_DEV_ID_82547EI_MOBILE: 1351 hw->mac_type = e1000_82547; 1352 break; 1353 case E1000_DEV_ID_82547GI: 1354 hw->mac_type = e1000_82547_rev_2; 1355 break; 1356 case E1000_DEV_ID_82571EB_COPPER: 1357 case E1000_DEV_ID_82571EB_FIBER: 1358 case E1000_DEV_ID_82571EB_SERDES: 1359 case E1000_DEV_ID_82571EB_SERDES_DUAL: 1360 case E1000_DEV_ID_82571EB_SERDES_QUAD: 1361 case E1000_DEV_ID_82571EB_QUAD_COPPER: 1362 case E1000_DEV_ID_82571PT_QUAD_COPPER: 1363 case E1000_DEV_ID_82571EB_QUAD_FIBER: 1364 case E1000_DEV_ID_82571EB_QUAD_COPPER_LOWPROFILE: 1365 hw->mac_type = e1000_82571; 1366 break; 1367 case E1000_DEV_ID_82572EI_COPPER: 1368 case E1000_DEV_ID_82572EI_FIBER: 1369 case E1000_DEV_ID_82572EI_SERDES: 1370 case E1000_DEV_ID_82572EI: 1371 hw->mac_type = e1000_82572; 1372 break; 1373 case E1000_DEV_ID_82573E: 1374 case E1000_DEV_ID_82573E_IAMT: 1375 case E1000_DEV_ID_82573L: 1376 hw->mac_type = e1000_82573; 1377 break; 1378 case E1000_DEV_ID_82574L: 1379 hw->mac_type = e1000_82574; 1380 break; 1381 case E1000_DEV_ID_80003ES2LAN_COPPER_SPT: 1382 case E1000_DEV_ID_80003ES2LAN_SERDES_SPT: 1383 case E1000_DEV_ID_80003ES2LAN_COPPER_DPT: 1384 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT: 1385 hw->mac_type = e1000_80003es2lan; 1386 break; 1387 case E1000_DEV_ID_ICH8_IGP_M_AMT: 1388 case E1000_DEV_ID_ICH8_IGP_AMT: 1389 case E1000_DEV_ID_ICH8_IGP_C: 1390 case E1000_DEV_ID_ICH8_IFE: 1391 case E1000_DEV_ID_ICH8_IFE_GT: 1392 case E1000_DEV_ID_ICH8_IFE_G: 1393 case E1000_DEV_ID_ICH8_IGP_M: 1394 hw->mac_type = e1000_ich8lan; 1395 break; 1396 case PCI_DEVICE_ID_INTEL_I210_UNPROGRAMMED: 1397 case PCI_DEVICE_ID_INTEL_I211_UNPROGRAMMED: 1398 case PCI_DEVICE_ID_INTEL_I210_COPPER: 1399 case PCI_DEVICE_ID_INTEL_I211_COPPER: 1400 case PCI_DEVICE_ID_INTEL_I210_COPPER_FLASHLESS: 1401 case PCI_DEVICE_ID_INTEL_I210_SERDES: 1402 case PCI_DEVICE_ID_INTEL_I210_SERDES_FLASHLESS: 1403 case PCI_DEVICE_ID_INTEL_I210_1000BASEKX: 1404 hw->mac_type = e1000_igb; 1405 break; 1406 default: 1407 /* Should never have loaded on this device */ 1408 return -E1000_ERR_MAC_TYPE; 1409 } 1410 return E1000_SUCCESS; 1411 } 1412 1413 /****************************************************************************** 1414 * Reset the transmit and receive units; mask and clear all interrupts. 1415 * 1416 * hw - Struct containing variables accessed by shared code 1417 *****************************************************************************/ 1418 void 1419 e1000_reset_hw(struct e1000_hw *hw) 1420 { 1421 uint32_t ctrl; 1422 uint32_t ctrl_ext; 1423 uint32_t manc; 1424 uint32_t pba = 0; 1425 uint32_t reg; 1426 1427 DEBUGFUNC(); 1428 1429 /* get the correct pba value for both PCI and PCIe*/ 1430 if (hw->mac_type < e1000_82571) 1431 pba = E1000_DEFAULT_PCI_PBA; 1432 else 1433 pba = E1000_DEFAULT_PCIE_PBA; 1434 1435 /* For 82542 (rev 2.0), disable MWI before issuing a device reset */ 1436 if (hw->mac_type == e1000_82542_rev2_0) { 1437 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n"); 1438 pci_write_config_word(hw->pdev, PCI_COMMAND, 1439 hw->pci_cmd_word & ~PCI_COMMAND_INVALIDATE); 1440 } 1441 1442 /* Clear interrupt mask to stop board from generating interrupts */ 1443 DEBUGOUT("Masking off all interrupts\n"); 1444 if (hw->mac_type == e1000_igb) 1445 E1000_WRITE_REG(hw, I210_IAM, 0); 1446 E1000_WRITE_REG(hw, IMC, 0xffffffff); 1447 1448 /* Disable the Transmit and Receive units. Then delay to allow 1449 * any pending transactions to complete before we hit the MAC with 1450 * the global reset. 1451 */ 1452 E1000_WRITE_REG(hw, RCTL, 0); 1453 E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP); 1454 E1000_WRITE_FLUSH(hw); 1455 1456 /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */ 1457 hw->tbi_compatibility_on = false; 1458 1459 /* Delay to allow any outstanding PCI transactions to complete before 1460 * resetting the device 1461 */ 1462 mdelay(10); 1463 1464 /* Issue a global reset to the MAC. This will reset the chip's 1465 * transmit, receive, DMA, and link units. It will not effect 1466 * the current PCI configuration. The global reset bit is self- 1467 * clearing, and should clear within a microsecond. 1468 */ 1469 DEBUGOUT("Issuing a global reset to MAC\n"); 1470 ctrl = E1000_READ_REG(hw, CTRL); 1471 1472 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST)); 1473 1474 /* Force a reload from the EEPROM if necessary */ 1475 if (hw->mac_type == e1000_igb) { 1476 mdelay(20); 1477 reg = E1000_READ_REG(hw, STATUS); 1478 if (reg & E1000_STATUS_PF_RST_DONE) 1479 DEBUGOUT("PF OK\n"); 1480 reg = E1000_READ_REG(hw, I210_EECD); 1481 if (reg & E1000_EECD_AUTO_RD) 1482 DEBUGOUT("EEC OK\n"); 1483 } else if (hw->mac_type < e1000_82540) { 1484 /* Wait for reset to complete */ 1485 udelay(10); 1486 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 1487 ctrl_ext |= E1000_CTRL_EXT_EE_RST; 1488 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 1489 E1000_WRITE_FLUSH(hw); 1490 /* Wait for EEPROM reload */ 1491 mdelay(2); 1492 } else { 1493 /* Wait for EEPROM reload (it happens automatically) */ 1494 mdelay(4); 1495 /* Dissable HW ARPs on ASF enabled adapters */ 1496 manc = E1000_READ_REG(hw, MANC); 1497 manc &= ~(E1000_MANC_ARP_EN); 1498 E1000_WRITE_REG(hw, MANC, manc); 1499 } 1500 1501 /* Clear interrupt mask to stop board from generating interrupts */ 1502 DEBUGOUT("Masking off all interrupts\n"); 1503 if (hw->mac_type == e1000_igb) 1504 E1000_WRITE_REG(hw, I210_IAM, 0); 1505 E1000_WRITE_REG(hw, IMC, 0xffffffff); 1506 1507 /* Clear any pending interrupt events. */ 1508 E1000_READ_REG(hw, ICR); 1509 1510 /* If MWI was previously enabled, reenable it. */ 1511 if (hw->mac_type == e1000_82542_rev2_0) { 1512 pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word); 1513 } 1514 if (hw->mac_type != e1000_igb) 1515 E1000_WRITE_REG(hw, PBA, pba); 1516 } 1517 1518 /****************************************************************************** 1519 * 1520 * Initialize a number of hardware-dependent bits 1521 * 1522 * hw: Struct containing variables accessed by shared code 1523 * 1524 * This function contains hardware limitation workarounds for PCI-E adapters 1525 * 1526 *****************************************************************************/ 1527 static void 1528 e1000_initialize_hardware_bits(struct e1000_hw *hw) 1529 { 1530 if ((hw->mac_type >= e1000_82571) && 1531 (!hw->initialize_hw_bits_disable)) { 1532 /* Settings common to all PCI-express silicon */ 1533 uint32_t reg_ctrl, reg_ctrl_ext; 1534 uint32_t reg_tarc0, reg_tarc1; 1535 uint32_t reg_tctl; 1536 uint32_t reg_txdctl, reg_txdctl1; 1537 1538 /* link autonegotiation/sync workarounds */ 1539 reg_tarc0 = E1000_READ_REG(hw, TARC0); 1540 reg_tarc0 &= ~((1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)); 1541 1542 /* Enable not-done TX descriptor counting */ 1543 reg_txdctl = E1000_READ_REG(hw, TXDCTL); 1544 reg_txdctl |= E1000_TXDCTL_COUNT_DESC; 1545 E1000_WRITE_REG(hw, TXDCTL, reg_txdctl); 1546 1547 reg_txdctl1 = E1000_READ_REG(hw, TXDCTL1); 1548 reg_txdctl1 |= E1000_TXDCTL_COUNT_DESC; 1549 E1000_WRITE_REG(hw, TXDCTL1, reg_txdctl1); 1550 1551 /* IGB is cool */ 1552 if (hw->mac_type == e1000_igb) 1553 return; 1554 1555 switch (hw->mac_type) { 1556 case e1000_82571: 1557 case e1000_82572: 1558 /* Clear PHY TX compatible mode bits */ 1559 reg_tarc1 = E1000_READ_REG(hw, TARC1); 1560 reg_tarc1 &= ~((1 << 30)|(1 << 29)); 1561 1562 /* link autonegotiation/sync workarounds */ 1563 reg_tarc0 |= ((1 << 26)|(1 << 25)|(1 << 24)|(1 << 23)); 1564 1565 /* TX ring control fixes */ 1566 reg_tarc1 |= ((1 << 26)|(1 << 25)|(1 << 24)); 1567 1568 /* Multiple read bit is reversed polarity */ 1569 reg_tctl = E1000_READ_REG(hw, TCTL); 1570 if (reg_tctl & E1000_TCTL_MULR) 1571 reg_tarc1 &= ~(1 << 28); 1572 else 1573 reg_tarc1 |= (1 << 28); 1574 1575 E1000_WRITE_REG(hw, TARC1, reg_tarc1); 1576 break; 1577 case e1000_82573: 1578 case e1000_82574: 1579 reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 1580 reg_ctrl_ext &= ~(1 << 23); 1581 reg_ctrl_ext |= (1 << 22); 1582 1583 /* TX byte count fix */ 1584 reg_ctrl = E1000_READ_REG(hw, CTRL); 1585 reg_ctrl &= ~(1 << 29); 1586 1587 E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext); 1588 E1000_WRITE_REG(hw, CTRL, reg_ctrl); 1589 break; 1590 case e1000_80003es2lan: 1591 /* improve small packet performace for fiber/serdes */ 1592 if ((hw->media_type == e1000_media_type_fiber) 1593 || (hw->media_type == 1594 e1000_media_type_internal_serdes)) { 1595 reg_tarc0 &= ~(1 << 20); 1596 } 1597 1598 /* Multiple read bit is reversed polarity */ 1599 reg_tctl = E1000_READ_REG(hw, TCTL); 1600 reg_tarc1 = E1000_READ_REG(hw, TARC1); 1601 if (reg_tctl & E1000_TCTL_MULR) 1602 reg_tarc1 &= ~(1 << 28); 1603 else 1604 reg_tarc1 |= (1 << 28); 1605 1606 E1000_WRITE_REG(hw, TARC1, reg_tarc1); 1607 break; 1608 case e1000_ich8lan: 1609 /* Reduce concurrent DMA requests to 3 from 4 */ 1610 if ((hw->revision_id < 3) || 1611 ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) && 1612 (hw->device_id != E1000_DEV_ID_ICH8_IGP_M))) 1613 reg_tarc0 |= ((1 << 29)|(1 << 28)); 1614 1615 reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 1616 reg_ctrl_ext |= (1 << 22); 1617 E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext); 1618 1619 /* workaround TX hang with TSO=on */ 1620 reg_tarc0 |= ((1 << 27)|(1 << 26)|(1 << 24)|(1 << 23)); 1621 1622 /* Multiple read bit is reversed polarity */ 1623 reg_tctl = E1000_READ_REG(hw, TCTL); 1624 reg_tarc1 = E1000_READ_REG(hw, TARC1); 1625 if (reg_tctl & E1000_TCTL_MULR) 1626 reg_tarc1 &= ~(1 << 28); 1627 else 1628 reg_tarc1 |= (1 << 28); 1629 1630 /* workaround TX hang with TSO=on */ 1631 reg_tarc1 |= ((1 << 30)|(1 << 26)|(1 << 24)); 1632 1633 E1000_WRITE_REG(hw, TARC1, reg_tarc1); 1634 break; 1635 default: 1636 break; 1637 } 1638 1639 E1000_WRITE_REG(hw, TARC0, reg_tarc0); 1640 } 1641 } 1642 1643 /****************************************************************************** 1644 * Performs basic configuration of the adapter. 1645 * 1646 * hw - Struct containing variables accessed by shared code 1647 * 1648 * Assumes that the controller has previously been reset and is in a 1649 * post-reset uninitialized state. Initializes the receive address registers, 1650 * multicast table, and VLAN filter table. Calls routines to setup link 1651 * configuration and flow control settings. Clears all on-chip counters. Leaves 1652 * the transmit and receive units disabled and uninitialized. 1653 *****************************************************************************/ 1654 static int 1655 e1000_init_hw(struct eth_device *nic) 1656 { 1657 struct e1000_hw *hw = nic->priv; 1658 uint32_t ctrl; 1659 uint32_t i; 1660 int32_t ret_val; 1661 uint16_t pcix_cmd_word; 1662 uint16_t pcix_stat_hi_word; 1663 uint16_t cmd_mmrbc; 1664 uint16_t stat_mmrbc; 1665 uint32_t mta_size; 1666 uint32_t reg_data; 1667 uint32_t ctrl_ext; 1668 DEBUGFUNC(); 1669 /* force full DMA clock frequency for 10/100 on ICH8 A0-B0 */ 1670 if ((hw->mac_type == e1000_ich8lan) && 1671 ((hw->revision_id < 3) || 1672 ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) && 1673 (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))) { 1674 reg_data = E1000_READ_REG(hw, STATUS); 1675 reg_data &= ~0x80000000; 1676 E1000_WRITE_REG(hw, STATUS, reg_data); 1677 } 1678 /* Do not need initialize Identification LED */ 1679 1680 /* Set the media type and TBI compatibility */ 1681 e1000_set_media_type(hw); 1682 1683 /* Must be called after e1000_set_media_type 1684 * because media_type is used */ 1685 e1000_initialize_hardware_bits(hw); 1686 1687 /* Disabling VLAN filtering. */ 1688 DEBUGOUT("Initializing the IEEE VLAN\n"); 1689 /* VET hardcoded to standard value and VFTA removed in ICH8 LAN */ 1690 if (hw->mac_type != e1000_ich8lan) { 1691 if (hw->mac_type < e1000_82545_rev_3) 1692 E1000_WRITE_REG(hw, VET, 0); 1693 e1000_clear_vfta(hw); 1694 } 1695 1696 /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */ 1697 if (hw->mac_type == e1000_82542_rev2_0) { 1698 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n"); 1699 pci_write_config_word(hw->pdev, PCI_COMMAND, 1700 hw-> 1701 pci_cmd_word & ~PCI_COMMAND_INVALIDATE); 1702 E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST); 1703 E1000_WRITE_FLUSH(hw); 1704 mdelay(5); 1705 } 1706 1707 /* Setup the receive address. This involves initializing all of the Receive 1708 * Address Registers (RARs 0 - 15). 1709 */ 1710 e1000_init_rx_addrs(nic); 1711 1712 /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */ 1713 if (hw->mac_type == e1000_82542_rev2_0) { 1714 E1000_WRITE_REG(hw, RCTL, 0); 1715 E1000_WRITE_FLUSH(hw); 1716 mdelay(1); 1717 pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word); 1718 } 1719 1720 /* Zero out the Multicast HASH table */ 1721 DEBUGOUT("Zeroing the MTA\n"); 1722 mta_size = E1000_MC_TBL_SIZE; 1723 if (hw->mac_type == e1000_ich8lan) 1724 mta_size = E1000_MC_TBL_SIZE_ICH8LAN; 1725 for (i = 0; i < mta_size; i++) { 1726 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0); 1727 /* use write flush to prevent Memory Write Block (MWB) from 1728 * occuring when accessing our register space */ 1729 E1000_WRITE_FLUSH(hw); 1730 } 1731 #if 0 1732 /* Set the PCI priority bit correctly in the CTRL register. This 1733 * determines if the adapter gives priority to receives, or if it 1734 * gives equal priority to transmits and receives. Valid only on 1735 * 82542 and 82543 silicon. 1736 */ 1737 if (hw->dma_fairness && hw->mac_type <= e1000_82543) { 1738 ctrl = E1000_READ_REG(hw, CTRL); 1739 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR); 1740 } 1741 #endif 1742 switch (hw->mac_type) { 1743 case e1000_82545_rev_3: 1744 case e1000_82546_rev_3: 1745 case e1000_igb: 1746 break; 1747 default: 1748 /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */ 1749 if (hw->bus_type == e1000_bus_type_pcix) { 1750 pci_read_config_word(hw->pdev, PCIX_COMMAND_REGISTER, 1751 &pcix_cmd_word); 1752 pci_read_config_word(hw->pdev, PCIX_STATUS_REGISTER_HI, 1753 &pcix_stat_hi_word); 1754 cmd_mmrbc = 1755 (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) >> 1756 PCIX_COMMAND_MMRBC_SHIFT; 1757 stat_mmrbc = 1758 (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >> 1759 PCIX_STATUS_HI_MMRBC_SHIFT; 1760 if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K) 1761 stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K; 1762 if (cmd_mmrbc > stat_mmrbc) { 1763 pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK; 1764 pcix_cmd_word |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT; 1765 pci_write_config_word(hw->pdev, PCIX_COMMAND_REGISTER, 1766 pcix_cmd_word); 1767 } 1768 } 1769 break; 1770 } 1771 1772 /* More time needed for PHY to initialize */ 1773 if (hw->mac_type == e1000_ich8lan) 1774 mdelay(15); 1775 if (hw->mac_type == e1000_igb) 1776 mdelay(15); 1777 1778 /* Call a subroutine to configure the link and setup flow control. */ 1779 ret_val = e1000_setup_link(nic); 1780 1781 /* Set the transmit descriptor write-back policy */ 1782 if (hw->mac_type > e1000_82544) { 1783 ctrl = E1000_READ_REG(hw, TXDCTL); 1784 ctrl = 1785 (ctrl & ~E1000_TXDCTL_WTHRESH) | 1786 E1000_TXDCTL_FULL_TX_DESC_WB; 1787 E1000_WRITE_REG(hw, TXDCTL, ctrl); 1788 } 1789 1790 /* Set the receive descriptor write back policy */ 1791 if (hw->mac_type >= e1000_82571) { 1792 ctrl = E1000_READ_REG(hw, RXDCTL); 1793 ctrl = 1794 (ctrl & ~E1000_RXDCTL_WTHRESH) | 1795 E1000_RXDCTL_FULL_RX_DESC_WB; 1796 E1000_WRITE_REG(hw, RXDCTL, ctrl); 1797 } 1798 1799 switch (hw->mac_type) { 1800 default: 1801 break; 1802 case e1000_80003es2lan: 1803 /* Enable retransmit on late collisions */ 1804 reg_data = E1000_READ_REG(hw, TCTL); 1805 reg_data |= E1000_TCTL_RTLC; 1806 E1000_WRITE_REG(hw, TCTL, reg_data); 1807 1808 /* Configure Gigabit Carry Extend Padding */ 1809 reg_data = E1000_READ_REG(hw, TCTL_EXT); 1810 reg_data &= ~E1000_TCTL_EXT_GCEX_MASK; 1811 reg_data |= DEFAULT_80003ES2LAN_TCTL_EXT_GCEX; 1812 E1000_WRITE_REG(hw, TCTL_EXT, reg_data); 1813 1814 /* Configure Transmit Inter-Packet Gap */ 1815 reg_data = E1000_READ_REG(hw, TIPG); 1816 reg_data &= ~E1000_TIPG_IPGT_MASK; 1817 reg_data |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000; 1818 E1000_WRITE_REG(hw, TIPG, reg_data); 1819 1820 reg_data = E1000_READ_REG_ARRAY(hw, FFLT, 0x0001); 1821 reg_data &= ~0x00100000; 1822 E1000_WRITE_REG_ARRAY(hw, FFLT, 0x0001, reg_data); 1823 /* Fall through */ 1824 case e1000_82571: 1825 case e1000_82572: 1826 case e1000_ich8lan: 1827 ctrl = E1000_READ_REG(hw, TXDCTL1); 1828 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) 1829 | E1000_TXDCTL_FULL_TX_DESC_WB; 1830 E1000_WRITE_REG(hw, TXDCTL1, ctrl); 1831 break; 1832 case e1000_82573: 1833 case e1000_82574: 1834 reg_data = E1000_READ_REG(hw, GCR); 1835 reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX; 1836 E1000_WRITE_REG(hw, GCR, reg_data); 1837 case e1000_igb: 1838 break; 1839 } 1840 1841 #if 0 1842 /* Clear all of the statistics registers (clear on read). It is 1843 * important that we do this after we have tried to establish link 1844 * because the symbol error count will increment wildly if there 1845 * is no link. 1846 */ 1847 e1000_clear_hw_cntrs(hw); 1848 1849 /* ICH8 No-snoop bits are opposite polarity. 1850 * Set to snoop by default after reset. */ 1851 if (hw->mac_type == e1000_ich8lan) 1852 e1000_set_pci_ex_no_snoop(hw, PCI_EX_82566_SNOOP_ALL); 1853 #endif 1854 1855 if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER || 1856 hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) { 1857 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 1858 /* Relaxed ordering must be disabled to avoid a parity 1859 * error crash in a PCI slot. */ 1860 ctrl_ext |= E1000_CTRL_EXT_RO_DIS; 1861 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 1862 } 1863 1864 return ret_val; 1865 } 1866 1867 /****************************************************************************** 1868 * Configures flow control and link settings. 1869 * 1870 * hw - Struct containing variables accessed by shared code 1871 * 1872 * Determines which flow control settings to use. Calls the apropriate media- 1873 * specific link configuration function. Configures the flow control settings. 1874 * Assuming the adapter has a valid link partner, a valid link should be 1875 * established. Assumes the hardware has previously been reset and the 1876 * transmitter and receiver are not enabled. 1877 *****************************************************************************/ 1878 static int 1879 e1000_setup_link(struct eth_device *nic) 1880 { 1881 struct e1000_hw *hw = nic->priv; 1882 int32_t ret_val; 1883 #ifndef CONFIG_E1000_NO_NVM 1884 uint32_t ctrl_ext; 1885 uint16_t eeprom_data; 1886 #endif 1887 1888 DEBUGFUNC(); 1889 1890 /* In the case of the phy reset being blocked, we already have a link. 1891 * We do not have to set it up again. */ 1892 if (e1000_check_phy_reset_block(hw)) 1893 return E1000_SUCCESS; 1894 1895 #ifndef CONFIG_E1000_NO_NVM 1896 /* Read and store word 0x0F of the EEPROM. This word contains bits 1897 * that determine the hardware's default PAUSE (flow control) mode, 1898 * a bit that determines whether the HW defaults to enabling or 1899 * disabling auto-negotiation, and the direction of the 1900 * SW defined pins. If there is no SW over-ride of the flow 1901 * control setting, then the variable hw->fc will 1902 * be initialized based on a value in the EEPROM. 1903 */ 1904 if (e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, 1, 1905 &eeprom_data) < 0) { 1906 DEBUGOUT("EEPROM Read Error\n"); 1907 return -E1000_ERR_EEPROM; 1908 } 1909 #endif 1910 if (hw->fc == e1000_fc_default) { 1911 switch (hw->mac_type) { 1912 case e1000_ich8lan: 1913 case e1000_82573: 1914 case e1000_82574: 1915 case e1000_igb: 1916 hw->fc = e1000_fc_full; 1917 break; 1918 default: 1919 #ifndef CONFIG_E1000_NO_NVM 1920 ret_val = e1000_read_eeprom(hw, 1921 EEPROM_INIT_CONTROL2_REG, 1, &eeprom_data); 1922 if (ret_val) { 1923 DEBUGOUT("EEPROM Read Error\n"); 1924 return -E1000_ERR_EEPROM; 1925 } 1926 if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0) 1927 hw->fc = e1000_fc_none; 1928 else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 1929 EEPROM_WORD0F_ASM_DIR) 1930 hw->fc = e1000_fc_tx_pause; 1931 else 1932 #endif 1933 hw->fc = e1000_fc_full; 1934 break; 1935 } 1936 } 1937 1938 /* We want to save off the original Flow Control configuration just 1939 * in case we get disconnected and then reconnected into a different 1940 * hub or switch with different Flow Control capabilities. 1941 */ 1942 if (hw->mac_type == e1000_82542_rev2_0) 1943 hw->fc &= (~e1000_fc_tx_pause); 1944 1945 if ((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1)) 1946 hw->fc &= (~e1000_fc_rx_pause); 1947 1948 hw->original_fc = hw->fc; 1949 1950 DEBUGOUT("After fix-ups FlowControl is now = %x\n", hw->fc); 1951 1952 #ifndef CONFIG_E1000_NO_NVM 1953 /* Take the 4 bits from EEPROM word 0x0F that determine the initial 1954 * polarity value for the SW controlled pins, and setup the 1955 * Extended Device Control reg with that info. 1956 * This is needed because one of the SW controlled pins is used for 1957 * signal detection. So this should be done before e1000_setup_pcs_link() 1958 * or e1000_phy_setup() is called. 1959 */ 1960 if (hw->mac_type == e1000_82543) { 1961 ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) << 1962 SWDPIO__EXT_SHIFT); 1963 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 1964 } 1965 #endif 1966 1967 /* Call the necessary subroutine to configure the link. */ 1968 ret_val = (hw->media_type == e1000_media_type_fiber) ? 1969 e1000_setup_fiber_link(nic) : e1000_setup_copper_link(nic); 1970 if (ret_val < 0) { 1971 return ret_val; 1972 } 1973 1974 /* Initialize the flow control address, type, and PAUSE timer 1975 * registers to their default values. This is done even if flow 1976 * control is disabled, because it does not hurt anything to 1977 * initialize these registers. 1978 */ 1979 DEBUGOUT("Initializing the Flow Control address, type" 1980 "and timer regs\n"); 1981 1982 /* FCAL/H and FCT are hardcoded to standard values in e1000_ich8lan. */ 1983 if (hw->mac_type != e1000_ich8lan) { 1984 E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE); 1985 E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH); 1986 E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW); 1987 } 1988 1989 E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time); 1990 1991 /* Set the flow control receive threshold registers. Normally, 1992 * these registers will be set to a default threshold that may be 1993 * adjusted later by the driver's runtime code. However, if the 1994 * ability to transmit pause frames in not enabled, then these 1995 * registers will be set to 0. 1996 */ 1997 if (!(hw->fc & e1000_fc_tx_pause)) { 1998 E1000_WRITE_REG(hw, FCRTL, 0); 1999 E1000_WRITE_REG(hw, FCRTH, 0); 2000 } else { 2001 /* We need to set up the Receive Threshold high and low water marks 2002 * as well as (optionally) enabling the transmission of XON frames. 2003 */ 2004 if (hw->fc_send_xon) { 2005 E1000_WRITE_REG(hw, FCRTL, 2006 (hw->fc_low_water | E1000_FCRTL_XONE)); 2007 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water); 2008 } else { 2009 E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water); 2010 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water); 2011 } 2012 } 2013 return ret_val; 2014 } 2015 2016 /****************************************************************************** 2017 * Sets up link for a fiber based adapter 2018 * 2019 * hw - Struct containing variables accessed by shared code 2020 * 2021 * Manipulates Physical Coding Sublayer functions in order to configure 2022 * link. Assumes the hardware has been previously reset and the transmitter 2023 * and receiver are not enabled. 2024 *****************************************************************************/ 2025 static int 2026 e1000_setup_fiber_link(struct eth_device *nic) 2027 { 2028 struct e1000_hw *hw = nic->priv; 2029 uint32_t ctrl; 2030 uint32_t status; 2031 uint32_t txcw = 0; 2032 uint32_t i; 2033 uint32_t signal; 2034 int32_t ret_val; 2035 2036 DEBUGFUNC(); 2037 /* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be 2038 * set when the optics detect a signal. On older adapters, it will be 2039 * cleared when there is a signal 2040 */ 2041 ctrl = E1000_READ_REG(hw, CTRL); 2042 if ((hw->mac_type > e1000_82544) && !(ctrl & E1000_CTRL_ILOS)) 2043 signal = E1000_CTRL_SWDPIN1; 2044 else 2045 signal = 0; 2046 2047 printf("signal for %s is %x (ctrl %08x)!!!!\n", nic->name, signal, 2048 ctrl); 2049 /* Take the link out of reset */ 2050 ctrl &= ~(E1000_CTRL_LRST); 2051 2052 e1000_config_collision_dist(hw); 2053 2054 /* Check for a software override of the flow control settings, and setup 2055 * the device accordingly. If auto-negotiation is enabled, then software 2056 * will have to set the "PAUSE" bits to the correct value in the Tranmsit 2057 * Config Word Register (TXCW) and re-start auto-negotiation. However, if 2058 * auto-negotiation is disabled, then software will have to manually 2059 * configure the two flow control enable bits in the CTRL register. 2060 * 2061 * The possible values of the "fc" parameter are: 2062 * 0: Flow control is completely disabled 2063 * 1: Rx flow control is enabled (we can receive pause frames, but 2064 * not send pause frames). 2065 * 2: Tx flow control is enabled (we can send pause frames but we do 2066 * not support receiving pause frames). 2067 * 3: Both Rx and TX flow control (symmetric) are enabled. 2068 */ 2069 switch (hw->fc) { 2070 case e1000_fc_none: 2071 /* Flow control is completely disabled by a software over-ride. */ 2072 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD); 2073 break; 2074 case e1000_fc_rx_pause: 2075 /* RX Flow control is enabled and TX Flow control is disabled by a 2076 * software over-ride. Since there really isn't a way to advertise 2077 * that we are capable of RX Pause ONLY, we will advertise that we 2078 * support both symmetric and asymmetric RX PAUSE. Later, we will 2079 * disable the adapter's ability to send PAUSE frames. 2080 */ 2081 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); 2082 break; 2083 case e1000_fc_tx_pause: 2084 /* TX Flow control is enabled, and RX Flow control is disabled, by a 2085 * software over-ride. 2086 */ 2087 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR); 2088 break; 2089 case e1000_fc_full: 2090 /* Flow control (both RX and TX) is enabled by a software over-ride. */ 2091 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); 2092 break; 2093 default: 2094 DEBUGOUT("Flow control param set incorrectly\n"); 2095 return -E1000_ERR_CONFIG; 2096 break; 2097 } 2098 2099 /* Since auto-negotiation is enabled, take the link out of reset (the link 2100 * will be in reset, because we previously reset the chip). This will 2101 * restart auto-negotiation. If auto-neogtiation is successful then the 2102 * link-up status bit will be set and the flow control enable bits (RFCE 2103 * and TFCE) will be set according to their negotiated value. 2104 */ 2105 DEBUGOUT("Auto-negotiation enabled (%#x)\n", txcw); 2106 2107 E1000_WRITE_REG(hw, TXCW, txcw); 2108 E1000_WRITE_REG(hw, CTRL, ctrl); 2109 E1000_WRITE_FLUSH(hw); 2110 2111 hw->txcw = txcw; 2112 mdelay(1); 2113 2114 /* If we have a signal (the cable is plugged in) then poll for a "Link-Up" 2115 * indication in the Device Status Register. Time-out if a link isn't 2116 * seen in 500 milliseconds seconds (Auto-negotiation should complete in 2117 * less than 500 milliseconds even if the other end is doing it in SW). 2118 */ 2119 if ((E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) { 2120 DEBUGOUT("Looking for Link\n"); 2121 for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) { 2122 mdelay(10); 2123 status = E1000_READ_REG(hw, STATUS); 2124 if (status & E1000_STATUS_LU) 2125 break; 2126 } 2127 if (i == (LINK_UP_TIMEOUT / 10)) { 2128 /* AutoNeg failed to achieve a link, so we'll call 2129 * e1000_check_for_link. This routine will force the link up if we 2130 * detect a signal. This will allow us to communicate with 2131 * non-autonegotiating link partners. 2132 */ 2133 DEBUGOUT("Never got a valid link from auto-neg!!!\n"); 2134 hw->autoneg_failed = 1; 2135 ret_val = e1000_check_for_link(nic); 2136 if (ret_val < 0) { 2137 DEBUGOUT("Error while checking for link\n"); 2138 return ret_val; 2139 } 2140 hw->autoneg_failed = 0; 2141 } else { 2142 hw->autoneg_failed = 0; 2143 DEBUGOUT("Valid Link Found\n"); 2144 } 2145 } else { 2146 DEBUGOUT("No Signal Detected\n"); 2147 return -E1000_ERR_NOLINK; 2148 } 2149 return 0; 2150 } 2151 2152 /****************************************************************************** 2153 * Make sure we have a valid PHY and change PHY mode before link setup. 2154 * 2155 * hw - Struct containing variables accessed by shared code 2156 ******************************************************************************/ 2157 static int32_t 2158 e1000_copper_link_preconfig(struct e1000_hw *hw) 2159 { 2160 uint32_t ctrl; 2161 int32_t ret_val; 2162 uint16_t phy_data; 2163 2164 DEBUGFUNC(); 2165 2166 ctrl = E1000_READ_REG(hw, CTRL); 2167 /* With 82543, we need to force speed and duplex on the MAC equal to what 2168 * the PHY speed and duplex configuration is. In addition, we need to 2169 * perform a hardware reset on the PHY to take it out of reset. 2170 */ 2171 if (hw->mac_type > e1000_82543) { 2172 ctrl |= E1000_CTRL_SLU; 2173 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 2174 E1000_WRITE_REG(hw, CTRL, ctrl); 2175 } else { 2176 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX 2177 | E1000_CTRL_SLU); 2178 E1000_WRITE_REG(hw, CTRL, ctrl); 2179 ret_val = e1000_phy_hw_reset(hw); 2180 if (ret_val) 2181 return ret_val; 2182 } 2183 2184 /* Make sure we have a valid PHY */ 2185 ret_val = e1000_detect_gig_phy(hw); 2186 if (ret_val) { 2187 DEBUGOUT("Error, did not detect valid phy.\n"); 2188 return ret_val; 2189 } 2190 DEBUGOUT("Phy ID = %x\n", hw->phy_id); 2191 2192 /* Set PHY to class A mode (if necessary) */ 2193 ret_val = e1000_set_phy_mode(hw); 2194 if (ret_val) 2195 return ret_val; 2196 if ((hw->mac_type == e1000_82545_rev_3) || 2197 (hw->mac_type == e1000_82546_rev_3)) { 2198 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 2199 &phy_data); 2200 phy_data |= 0x00000008; 2201 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 2202 phy_data); 2203 } 2204 2205 if (hw->mac_type <= e1000_82543 || 2206 hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 || 2207 hw->mac_type == e1000_82541_rev_2 2208 || hw->mac_type == e1000_82547_rev_2) 2209 hw->phy_reset_disable = false; 2210 2211 return E1000_SUCCESS; 2212 } 2213 2214 /***************************************************************************** 2215 * 2216 * This function sets the lplu state according to the active flag. When 2217 * activating lplu this function also disables smart speed and vise versa. 2218 * lplu will not be activated unless the device autonegotiation advertisment 2219 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes. 2220 * hw: Struct containing variables accessed by shared code 2221 * active - true to enable lplu false to disable lplu. 2222 * 2223 * returns: - E1000_ERR_PHY if fail to read/write the PHY 2224 * E1000_SUCCESS at any other case. 2225 * 2226 ****************************************************************************/ 2227 2228 static int32_t 2229 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active) 2230 { 2231 uint32_t phy_ctrl = 0; 2232 int32_t ret_val; 2233 uint16_t phy_data; 2234 DEBUGFUNC(); 2235 2236 if (hw->phy_type != e1000_phy_igp && hw->phy_type != e1000_phy_igp_2 2237 && hw->phy_type != e1000_phy_igp_3) 2238 return E1000_SUCCESS; 2239 2240 /* During driver activity LPLU should not be used or it will attain link 2241 * from the lowest speeds starting from 10Mbps. The capability is used 2242 * for Dx transitions and states */ 2243 if (hw->mac_type == e1000_82541_rev_2 2244 || hw->mac_type == e1000_82547_rev_2) { 2245 ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, 2246 &phy_data); 2247 if (ret_val) 2248 return ret_val; 2249 } else if (hw->mac_type == e1000_ich8lan) { 2250 /* MAC writes into PHY register based on the state transition 2251 * and start auto-negotiation. SW driver can overwrite the 2252 * settings in CSR PHY power control E1000_PHY_CTRL register. */ 2253 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL); 2254 } else { 2255 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, 2256 &phy_data); 2257 if (ret_val) 2258 return ret_val; 2259 } 2260 2261 if (!active) { 2262 if (hw->mac_type == e1000_82541_rev_2 || 2263 hw->mac_type == e1000_82547_rev_2) { 2264 phy_data &= ~IGP01E1000_GMII_FLEX_SPD; 2265 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, 2266 phy_data); 2267 if (ret_val) 2268 return ret_val; 2269 } else { 2270 if (hw->mac_type == e1000_ich8lan) { 2271 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU; 2272 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); 2273 } else { 2274 phy_data &= ~IGP02E1000_PM_D3_LPLU; 2275 ret_val = e1000_write_phy_reg(hw, 2276 IGP02E1000_PHY_POWER_MGMT, phy_data); 2277 if (ret_val) 2278 return ret_val; 2279 } 2280 } 2281 2282 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during 2283 * Dx states where the power conservation is most important. During 2284 * driver activity we should enable SmartSpeed, so performance is 2285 * maintained. */ 2286 if (hw->smart_speed == e1000_smart_speed_on) { 2287 ret_val = e1000_read_phy_reg(hw, 2288 IGP01E1000_PHY_PORT_CONFIG, &phy_data); 2289 if (ret_val) 2290 return ret_val; 2291 2292 phy_data |= IGP01E1000_PSCFR_SMART_SPEED; 2293 ret_val = e1000_write_phy_reg(hw, 2294 IGP01E1000_PHY_PORT_CONFIG, phy_data); 2295 if (ret_val) 2296 return ret_val; 2297 } else if (hw->smart_speed == e1000_smart_speed_off) { 2298 ret_val = e1000_read_phy_reg(hw, 2299 IGP01E1000_PHY_PORT_CONFIG, &phy_data); 2300 if (ret_val) 2301 return ret_val; 2302 2303 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 2304 ret_val = e1000_write_phy_reg(hw, 2305 IGP01E1000_PHY_PORT_CONFIG, phy_data); 2306 if (ret_val) 2307 return ret_val; 2308 } 2309 2310 } else if ((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT) 2311 || (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL) || 2312 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) { 2313 2314 if (hw->mac_type == e1000_82541_rev_2 || 2315 hw->mac_type == e1000_82547_rev_2) { 2316 phy_data |= IGP01E1000_GMII_FLEX_SPD; 2317 ret_val = e1000_write_phy_reg(hw, 2318 IGP01E1000_GMII_FIFO, phy_data); 2319 if (ret_val) 2320 return ret_val; 2321 } else { 2322 if (hw->mac_type == e1000_ich8lan) { 2323 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU; 2324 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); 2325 } else { 2326 phy_data |= IGP02E1000_PM_D3_LPLU; 2327 ret_val = e1000_write_phy_reg(hw, 2328 IGP02E1000_PHY_POWER_MGMT, phy_data); 2329 if (ret_val) 2330 return ret_val; 2331 } 2332 } 2333 2334 /* When LPLU is enabled we should disable SmartSpeed */ 2335 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 2336 &phy_data); 2337 if (ret_val) 2338 return ret_val; 2339 2340 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 2341 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 2342 phy_data); 2343 if (ret_val) 2344 return ret_val; 2345 } 2346 return E1000_SUCCESS; 2347 } 2348 2349 /***************************************************************************** 2350 * 2351 * This function sets the lplu d0 state according to the active flag. When 2352 * activating lplu this function also disables smart speed and vise versa. 2353 * lplu will not be activated unless the device autonegotiation advertisment 2354 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes. 2355 * hw: Struct containing variables accessed by shared code 2356 * active - true to enable lplu false to disable lplu. 2357 * 2358 * returns: - E1000_ERR_PHY if fail to read/write the PHY 2359 * E1000_SUCCESS at any other case. 2360 * 2361 ****************************************************************************/ 2362 2363 static int32_t 2364 e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active) 2365 { 2366 uint32_t phy_ctrl = 0; 2367 int32_t ret_val; 2368 uint16_t phy_data; 2369 DEBUGFUNC(); 2370 2371 if (hw->mac_type <= e1000_82547_rev_2) 2372 return E1000_SUCCESS; 2373 2374 if (hw->mac_type == e1000_ich8lan) { 2375 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL); 2376 } else if (hw->mac_type == e1000_igb) { 2377 phy_ctrl = E1000_READ_REG(hw, I210_PHY_CTRL); 2378 } else { 2379 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, 2380 &phy_data); 2381 if (ret_val) 2382 return ret_val; 2383 } 2384 2385 if (!active) { 2386 if (hw->mac_type == e1000_ich8lan) { 2387 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU; 2388 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); 2389 } else if (hw->mac_type == e1000_igb) { 2390 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU; 2391 E1000_WRITE_REG(hw, I210_PHY_CTRL, phy_ctrl); 2392 } else { 2393 phy_data &= ~IGP02E1000_PM_D0_LPLU; 2394 ret_val = e1000_write_phy_reg(hw, 2395 IGP02E1000_PHY_POWER_MGMT, phy_data); 2396 if (ret_val) 2397 return ret_val; 2398 } 2399 2400 if (hw->mac_type == e1000_igb) 2401 return E1000_SUCCESS; 2402 2403 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during 2404 * Dx states where the power conservation is most important. During 2405 * driver activity we should enable SmartSpeed, so performance is 2406 * maintained. */ 2407 if (hw->smart_speed == e1000_smart_speed_on) { 2408 ret_val = e1000_read_phy_reg(hw, 2409 IGP01E1000_PHY_PORT_CONFIG, &phy_data); 2410 if (ret_val) 2411 return ret_val; 2412 2413 phy_data |= IGP01E1000_PSCFR_SMART_SPEED; 2414 ret_val = e1000_write_phy_reg(hw, 2415 IGP01E1000_PHY_PORT_CONFIG, phy_data); 2416 if (ret_val) 2417 return ret_val; 2418 } else if (hw->smart_speed == e1000_smart_speed_off) { 2419 ret_val = e1000_read_phy_reg(hw, 2420 IGP01E1000_PHY_PORT_CONFIG, &phy_data); 2421 if (ret_val) 2422 return ret_val; 2423 2424 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 2425 ret_val = e1000_write_phy_reg(hw, 2426 IGP01E1000_PHY_PORT_CONFIG, phy_data); 2427 if (ret_val) 2428 return ret_val; 2429 } 2430 2431 2432 } else { 2433 2434 if (hw->mac_type == e1000_ich8lan) { 2435 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU; 2436 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); 2437 } else if (hw->mac_type == e1000_igb) { 2438 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU; 2439 E1000_WRITE_REG(hw, I210_PHY_CTRL, phy_ctrl); 2440 } else { 2441 phy_data |= IGP02E1000_PM_D0_LPLU; 2442 ret_val = e1000_write_phy_reg(hw, 2443 IGP02E1000_PHY_POWER_MGMT, phy_data); 2444 if (ret_val) 2445 return ret_val; 2446 } 2447 2448 if (hw->mac_type == e1000_igb) 2449 return E1000_SUCCESS; 2450 2451 /* When LPLU is enabled we should disable SmartSpeed */ 2452 ret_val = e1000_read_phy_reg(hw, 2453 IGP01E1000_PHY_PORT_CONFIG, &phy_data); 2454 if (ret_val) 2455 return ret_val; 2456 2457 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 2458 ret_val = e1000_write_phy_reg(hw, 2459 IGP01E1000_PHY_PORT_CONFIG, phy_data); 2460 if (ret_val) 2461 return ret_val; 2462 2463 } 2464 return E1000_SUCCESS; 2465 } 2466 2467 /******************************************************************** 2468 * Copper link setup for e1000_phy_igp series. 2469 * 2470 * hw - Struct containing variables accessed by shared code 2471 *********************************************************************/ 2472 static int32_t 2473 e1000_copper_link_igp_setup(struct e1000_hw *hw) 2474 { 2475 uint32_t led_ctrl; 2476 int32_t ret_val; 2477 uint16_t phy_data; 2478 2479 DEBUGFUNC(); 2480 2481 if (hw->phy_reset_disable) 2482 return E1000_SUCCESS; 2483 2484 ret_val = e1000_phy_reset(hw); 2485 if (ret_val) { 2486 DEBUGOUT("Error Resetting the PHY\n"); 2487 return ret_val; 2488 } 2489 2490 /* Wait 15ms for MAC to configure PHY from eeprom settings */ 2491 mdelay(15); 2492 if (hw->mac_type != e1000_ich8lan) { 2493 /* Configure activity LED after PHY reset */ 2494 led_ctrl = E1000_READ_REG(hw, LEDCTL); 2495 led_ctrl &= IGP_ACTIVITY_LED_MASK; 2496 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); 2497 E1000_WRITE_REG(hw, LEDCTL, led_ctrl); 2498 } 2499 2500 /* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */ 2501 if (hw->phy_type == e1000_phy_igp) { 2502 /* disable lplu d3 during driver init */ 2503 ret_val = e1000_set_d3_lplu_state(hw, false); 2504 if (ret_val) { 2505 DEBUGOUT("Error Disabling LPLU D3\n"); 2506 return ret_val; 2507 } 2508 } 2509 2510 /* disable lplu d0 during driver init */ 2511 ret_val = e1000_set_d0_lplu_state(hw, false); 2512 if (ret_val) { 2513 DEBUGOUT("Error Disabling LPLU D0\n"); 2514 return ret_val; 2515 } 2516 /* Configure mdi-mdix settings */ 2517 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); 2518 if (ret_val) 2519 return ret_val; 2520 2521 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { 2522 hw->dsp_config_state = e1000_dsp_config_disabled; 2523 /* Force MDI for earlier revs of the IGP PHY */ 2524 phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX 2525 | IGP01E1000_PSCR_FORCE_MDI_MDIX); 2526 hw->mdix = 1; 2527 2528 } else { 2529 hw->dsp_config_state = e1000_dsp_config_enabled; 2530 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; 2531 2532 switch (hw->mdix) { 2533 case 1: 2534 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; 2535 break; 2536 case 2: 2537 phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX; 2538 break; 2539 case 0: 2540 default: 2541 phy_data |= IGP01E1000_PSCR_AUTO_MDIX; 2542 break; 2543 } 2544 } 2545 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); 2546 if (ret_val) 2547 return ret_val; 2548 2549 /* set auto-master slave resolution settings */ 2550 if (hw->autoneg) { 2551 e1000_ms_type phy_ms_setting = hw->master_slave; 2552 2553 if (hw->ffe_config_state == e1000_ffe_config_active) 2554 hw->ffe_config_state = e1000_ffe_config_enabled; 2555 2556 if (hw->dsp_config_state == e1000_dsp_config_activated) 2557 hw->dsp_config_state = e1000_dsp_config_enabled; 2558 2559 /* when autonegotiation advertisment is only 1000Mbps then we 2560 * should disable SmartSpeed and enable Auto MasterSlave 2561 * resolution as hardware default. */ 2562 if (hw->autoneg_advertised == ADVERTISE_1000_FULL) { 2563 /* Disable SmartSpeed */ 2564 ret_val = e1000_read_phy_reg(hw, 2565 IGP01E1000_PHY_PORT_CONFIG, &phy_data); 2566 if (ret_val) 2567 return ret_val; 2568 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 2569 ret_val = e1000_write_phy_reg(hw, 2570 IGP01E1000_PHY_PORT_CONFIG, phy_data); 2571 if (ret_val) 2572 return ret_val; 2573 /* Set auto Master/Slave resolution process */ 2574 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, 2575 &phy_data); 2576 if (ret_val) 2577 return ret_val; 2578 phy_data &= ~CR_1000T_MS_ENABLE; 2579 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, 2580 phy_data); 2581 if (ret_val) 2582 return ret_val; 2583 } 2584 2585 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data); 2586 if (ret_val) 2587 return ret_val; 2588 2589 /* load defaults for future use */ 2590 hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ? 2591 ((phy_data & CR_1000T_MS_VALUE) ? 2592 e1000_ms_force_master : 2593 e1000_ms_force_slave) : 2594 e1000_ms_auto; 2595 2596 switch (phy_ms_setting) { 2597 case e1000_ms_force_master: 2598 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE); 2599 break; 2600 case e1000_ms_force_slave: 2601 phy_data |= CR_1000T_MS_ENABLE; 2602 phy_data &= ~(CR_1000T_MS_VALUE); 2603 break; 2604 case e1000_ms_auto: 2605 phy_data &= ~CR_1000T_MS_ENABLE; 2606 default: 2607 break; 2608 } 2609 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data); 2610 if (ret_val) 2611 return ret_val; 2612 } 2613 2614 return E1000_SUCCESS; 2615 } 2616 2617 /***************************************************************************** 2618 * This function checks the mode of the firmware. 2619 * 2620 * returns - true when the mode is IAMT or false. 2621 ****************************************************************************/ 2622 bool 2623 e1000_check_mng_mode(struct e1000_hw *hw) 2624 { 2625 uint32_t fwsm; 2626 DEBUGFUNC(); 2627 2628 fwsm = E1000_READ_REG(hw, FWSM); 2629 2630 if (hw->mac_type == e1000_ich8lan) { 2631 if ((fwsm & E1000_FWSM_MODE_MASK) == 2632 (E1000_MNG_ICH_IAMT_MODE << E1000_FWSM_MODE_SHIFT)) 2633 return true; 2634 } else if ((fwsm & E1000_FWSM_MODE_MASK) == 2635 (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT)) 2636 return true; 2637 2638 return false; 2639 } 2640 2641 static int32_t 2642 e1000_write_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t data) 2643 { 2644 uint16_t swfw = E1000_SWFW_PHY0_SM; 2645 uint32_t reg_val; 2646 DEBUGFUNC(); 2647 2648 if (e1000_is_second_port(hw)) 2649 swfw = E1000_SWFW_PHY1_SM; 2650 2651 if (e1000_swfw_sync_acquire(hw, swfw)) 2652 return -E1000_ERR_SWFW_SYNC; 2653 2654 reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) 2655 & E1000_KUMCTRLSTA_OFFSET) | data; 2656 E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val); 2657 udelay(2); 2658 2659 return E1000_SUCCESS; 2660 } 2661 2662 static int32_t 2663 e1000_read_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *data) 2664 { 2665 uint16_t swfw = E1000_SWFW_PHY0_SM; 2666 uint32_t reg_val; 2667 DEBUGFUNC(); 2668 2669 if (e1000_is_second_port(hw)) 2670 swfw = E1000_SWFW_PHY1_SM; 2671 2672 if (e1000_swfw_sync_acquire(hw, swfw)) { 2673 debug("%s[%i]\n", __func__, __LINE__); 2674 return -E1000_ERR_SWFW_SYNC; 2675 } 2676 2677 /* Write register address */ 2678 reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) & 2679 E1000_KUMCTRLSTA_OFFSET) | E1000_KUMCTRLSTA_REN; 2680 E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val); 2681 udelay(2); 2682 2683 /* Read the data returned */ 2684 reg_val = E1000_READ_REG(hw, KUMCTRLSTA); 2685 *data = (uint16_t)reg_val; 2686 2687 return E1000_SUCCESS; 2688 } 2689 2690 /******************************************************************** 2691 * Copper link setup for e1000_phy_gg82563 series. 2692 * 2693 * hw - Struct containing variables accessed by shared code 2694 *********************************************************************/ 2695 static int32_t 2696 e1000_copper_link_ggp_setup(struct e1000_hw *hw) 2697 { 2698 int32_t ret_val; 2699 uint16_t phy_data; 2700 uint32_t reg_data; 2701 2702 DEBUGFUNC(); 2703 2704 if (!hw->phy_reset_disable) { 2705 /* Enable CRS on TX for half-duplex operation. */ 2706 ret_val = e1000_read_phy_reg(hw, 2707 GG82563_PHY_MAC_SPEC_CTRL, &phy_data); 2708 if (ret_val) 2709 return ret_val; 2710 2711 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX; 2712 /* Use 25MHz for both link down and 1000BASE-T for Tx clock */ 2713 phy_data |= GG82563_MSCR_TX_CLK_1000MBPS_25MHZ; 2714 2715 ret_val = e1000_write_phy_reg(hw, 2716 GG82563_PHY_MAC_SPEC_CTRL, phy_data); 2717 if (ret_val) 2718 return ret_val; 2719 2720 /* Options: 2721 * MDI/MDI-X = 0 (default) 2722 * 0 - Auto for all speeds 2723 * 1 - MDI mode 2724 * 2 - MDI-X mode 2725 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) 2726 */ 2727 ret_val = e1000_read_phy_reg(hw, 2728 GG82563_PHY_SPEC_CTRL, &phy_data); 2729 if (ret_val) 2730 return ret_val; 2731 2732 phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK; 2733 2734 switch (hw->mdix) { 2735 case 1: 2736 phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDI; 2737 break; 2738 case 2: 2739 phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDIX; 2740 break; 2741 case 0: 2742 default: 2743 phy_data |= GG82563_PSCR_CROSSOVER_MODE_AUTO; 2744 break; 2745 } 2746 2747 /* Options: 2748 * disable_polarity_correction = 0 (default) 2749 * Automatic Correction for Reversed Cable Polarity 2750 * 0 - Disabled 2751 * 1 - Enabled 2752 */ 2753 phy_data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE; 2754 ret_val = e1000_write_phy_reg(hw, 2755 GG82563_PHY_SPEC_CTRL, phy_data); 2756 2757 if (ret_val) 2758 return ret_val; 2759 2760 /* SW Reset the PHY so all changes take effect */ 2761 ret_val = e1000_phy_reset(hw); 2762 if (ret_val) { 2763 DEBUGOUT("Error Resetting the PHY\n"); 2764 return ret_val; 2765 } 2766 } /* phy_reset_disable */ 2767 2768 if (hw->mac_type == e1000_80003es2lan) { 2769 /* Bypass RX and TX FIFO's */ 2770 ret_val = e1000_write_kmrn_reg(hw, 2771 E1000_KUMCTRLSTA_OFFSET_FIFO_CTRL, 2772 E1000_KUMCTRLSTA_FIFO_CTRL_RX_BYPASS 2773 | E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS); 2774 if (ret_val) 2775 return ret_val; 2776 2777 ret_val = e1000_read_phy_reg(hw, 2778 GG82563_PHY_SPEC_CTRL_2, &phy_data); 2779 if (ret_val) 2780 return ret_val; 2781 2782 phy_data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG; 2783 ret_val = e1000_write_phy_reg(hw, 2784 GG82563_PHY_SPEC_CTRL_2, phy_data); 2785 2786 if (ret_val) 2787 return ret_val; 2788 2789 reg_data = E1000_READ_REG(hw, CTRL_EXT); 2790 reg_data &= ~(E1000_CTRL_EXT_LINK_MODE_MASK); 2791 E1000_WRITE_REG(hw, CTRL_EXT, reg_data); 2792 2793 ret_val = e1000_read_phy_reg(hw, 2794 GG82563_PHY_PWR_MGMT_CTRL, &phy_data); 2795 if (ret_val) 2796 return ret_val; 2797 2798 /* Do not init these registers when the HW is in IAMT mode, since the 2799 * firmware will have already initialized them. We only initialize 2800 * them if the HW is not in IAMT mode. 2801 */ 2802 if (e1000_check_mng_mode(hw) == false) { 2803 /* Enable Electrical Idle on the PHY */ 2804 phy_data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE; 2805 ret_val = e1000_write_phy_reg(hw, 2806 GG82563_PHY_PWR_MGMT_CTRL, phy_data); 2807 if (ret_val) 2808 return ret_val; 2809 2810 ret_val = e1000_read_phy_reg(hw, 2811 GG82563_PHY_KMRN_MODE_CTRL, &phy_data); 2812 if (ret_val) 2813 return ret_val; 2814 2815 phy_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; 2816 ret_val = e1000_write_phy_reg(hw, 2817 GG82563_PHY_KMRN_MODE_CTRL, phy_data); 2818 2819 if (ret_val) 2820 return ret_val; 2821 } 2822 2823 /* Workaround: Disable padding in Kumeran interface in the MAC 2824 * and in the PHY to avoid CRC errors. 2825 */ 2826 ret_val = e1000_read_phy_reg(hw, 2827 GG82563_PHY_INBAND_CTRL, &phy_data); 2828 if (ret_val) 2829 return ret_val; 2830 phy_data |= GG82563_ICR_DIS_PADDING; 2831 ret_val = e1000_write_phy_reg(hw, 2832 GG82563_PHY_INBAND_CTRL, phy_data); 2833 if (ret_val) 2834 return ret_val; 2835 } 2836 return E1000_SUCCESS; 2837 } 2838 2839 /******************************************************************** 2840 * Copper link setup for e1000_phy_m88 series. 2841 * 2842 * hw - Struct containing variables accessed by shared code 2843 *********************************************************************/ 2844 static int32_t 2845 e1000_copper_link_mgp_setup(struct e1000_hw *hw) 2846 { 2847 int32_t ret_val; 2848 uint16_t phy_data; 2849 2850 DEBUGFUNC(); 2851 2852 if (hw->phy_reset_disable) 2853 return E1000_SUCCESS; 2854 2855 /* Enable CRS on TX. This must be set for half-duplex operation. */ 2856 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 2857 if (ret_val) 2858 return ret_val; 2859 2860 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; 2861 2862 /* Options: 2863 * MDI/MDI-X = 0 (default) 2864 * 0 - Auto for all speeds 2865 * 1 - MDI mode 2866 * 2 - MDI-X mode 2867 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) 2868 */ 2869 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 2870 2871 switch (hw->mdix) { 2872 case 1: 2873 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; 2874 break; 2875 case 2: 2876 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; 2877 break; 2878 case 3: 2879 phy_data |= M88E1000_PSCR_AUTO_X_1000T; 2880 break; 2881 case 0: 2882 default: 2883 phy_data |= M88E1000_PSCR_AUTO_X_MODE; 2884 break; 2885 } 2886 2887 /* Options: 2888 * disable_polarity_correction = 0 (default) 2889 * Automatic Correction for Reversed Cable Polarity 2890 * 0 - Disabled 2891 * 1 - Enabled 2892 */ 2893 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; 2894 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 2895 if (ret_val) 2896 return ret_val; 2897 2898 if (hw->phy_revision < M88E1011_I_REV_4) { 2899 /* Force TX_CLK in the Extended PHY Specific Control Register 2900 * to 25MHz clock. 2901 */ 2902 ret_val = e1000_read_phy_reg(hw, 2903 M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); 2904 if (ret_val) 2905 return ret_val; 2906 2907 phy_data |= M88E1000_EPSCR_TX_CLK_25; 2908 2909 if ((hw->phy_revision == E1000_REVISION_2) && 2910 (hw->phy_id == M88E1111_I_PHY_ID)) { 2911 /* Vidalia Phy, set the downshift counter to 5x */ 2912 phy_data &= ~(M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK); 2913 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X; 2914 ret_val = e1000_write_phy_reg(hw, 2915 M88E1000_EXT_PHY_SPEC_CTRL, phy_data); 2916 if (ret_val) 2917 return ret_val; 2918 } else { 2919 /* Configure Master and Slave downshift values */ 2920 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 2921 | M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK); 2922 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X 2923 | M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X); 2924 ret_val = e1000_write_phy_reg(hw, 2925 M88E1000_EXT_PHY_SPEC_CTRL, phy_data); 2926 if (ret_val) 2927 return ret_val; 2928 } 2929 } 2930 2931 /* SW Reset the PHY so all changes take effect */ 2932 ret_val = e1000_phy_reset(hw); 2933 if (ret_val) { 2934 DEBUGOUT("Error Resetting the PHY\n"); 2935 return ret_val; 2936 } 2937 2938 return E1000_SUCCESS; 2939 } 2940 2941 /******************************************************************** 2942 * Setup auto-negotiation and flow control advertisements, 2943 * and then perform auto-negotiation. 2944 * 2945 * hw - Struct containing variables accessed by shared code 2946 *********************************************************************/ 2947 static int32_t 2948 e1000_copper_link_autoneg(struct e1000_hw *hw) 2949 { 2950 int32_t ret_val; 2951 uint16_t phy_data; 2952 2953 DEBUGFUNC(); 2954 2955 /* Perform some bounds checking on the hw->autoneg_advertised 2956 * parameter. If this variable is zero, then set it to the default. 2957 */ 2958 hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT; 2959 2960 /* If autoneg_advertised is zero, we assume it was not defaulted 2961 * by the calling code so we set to advertise full capability. 2962 */ 2963 if (hw->autoneg_advertised == 0) 2964 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT; 2965 2966 /* IFE phy only supports 10/100 */ 2967 if (hw->phy_type == e1000_phy_ife) 2968 hw->autoneg_advertised &= AUTONEG_ADVERTISE_10_100_ALL; 2969 2970 DEBUGOUT("Reconfiguring auto-neg advertisement params\n"); 2971 ret_val = e1000_phy_setup_autoneg(hw); 2972 if (ret_val) { 2973 DEBUGOUT("Error Setting up Auto-Negotiation\n"); 2974 return ret_val; 2975 } 2976 DEBUGOUT("Restarting Auto-Neg\n"); 2977 2978 /* Restart auto-negotiation by setting the Auto Neg Enable bit and 2979 * the Auto Neg Restart bit in the PHY control register. 2980 */ 2981 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data); 2982 if (ret_val) 2983 return ret_val; 2984 2985 phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); 2986 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data); 2987 if (ret_val) 2988 return ret_val; 2989 2990 /* Does the user want to wait for Auto-Neg to complete here, or 2991 * check at a later time (for example, callback routine). 2992 */ 2993 /* If we do not wait for autonegtation to complete I 2994 * do not see a valid link status. 2995 * wait_autoneg_complete = 1 . 2996 */ 2997 if (hw->wait_autoneg_complete) { 2998 ret_val = e1000_wait_autoneg(hw); 2999 if (ret_val) { 3000 DEBUGOUT("Error while waiting for autoneg" 3001 "to complete\n"); 3002 return ret_val; 3003 } 3004 } 3005 3006 hw->get_link_status = true; 3007 3008 return E1000_SUCCESS; 3009 } 3010 3011 /****************************************************************************** 3012 * Config the MAC and the PHY after link is up. 3013 * 1) Set up the MAC to the current PHY speed/duplex 3014 * if we are on 82543. If we 3015 * are on newer silicon, we only need to configure 3016 * collision distance in the Transmit Control Register. 3017 * 2) Set up flow control on the MAC to that established with 3018 * the link partner. 3019 * 3) Config DSP to improve Gigabit link quality for some PHY revisions. 3020 * 3021 * hw - Struct containing variables accessed by shared code 3022 ******************************************************************************/ 3023 static int32_t 3024 e1000_copper_link_postconfig(struct e1000_hw *hw) 3025 { 3026 int32_t ret_val; 3027 DEBUGFUNC(); 3028 3029 if (hw->mac_type >= e1000_82544) { 3030 e1000_config_collision_dist(hw); 3031 } else { 3032 ret_val = e1000_config_mac_to_phy(hw); 3033 if (ret_val) { 3034 DEBUGOUT("Error configuring MAC to PHY settings\n"); 3035 return ret_val; 3036 } 3037 } 3038 ret_val = e1000_config_fc_after_link_up(hw); 3039 if (ret_val) { 3040 DEBUGOUT("Error Configuring Flow Control\n"); 3041 return ret_val; 3042 } 3043 return E1000_SUCCESS; 3044 } 3045 3046 /****************************************************************************** 3047 * Detects which PHY is present and setup the speed and duplex 3048 * 3049 * hw - Struct containing variables accessed by shared code 3050 ******************************************************************************/ 3051 static int 3052 e1000_setup_copper_link(struct eth_device *nic) 3053 { 3054 struct e1000_hw *hw = nic->priv; 3055 int32_t ret_val; 3056 uint16_t i; 3057 uint16_t phy_data; 3058 uint16_t reg_data; 3059 3060 DEBUGFUNC(); 3061 3062 switch (hw->mac_type) { 3063 case e1000_80003es2lan: 3064 case e1000_ich8lan: 3065 /* Set the mac to wait the maximum time between each 3066 * iteration and increase the max iterations when 3067 * polling the phy; this fixes erroneous timeouts at 10Mbps. */ 3068 ret_val = e1000_write_kmrn_reg(hw, 3069 GG82563_REG(0x34, 4), 0xFFFF); 3070 if (ret_val) 3071 return ret_val; 3072 ret_val = e1000_read_kmrn_reg(hw, 3073 GG82563_REG(0x34, 9), ®_data); 3074 if (ret_val) 3075 return ret_val; 3076 reg_data |= 0x3F; 3077 ret_val = e1000_write_kmrn_reg(hw, 3078 GG82563_REG(0x34, 9), reg_data); 3079 if (ret_val) 3080 return ret_val; 3081 default: 3082 break; 3083 } 3084 3085 /* Check if it is a valid PHY and set PHY mode if necessary. */ 3086 ret_val = e1000_copper_link_preconfig(hw); 3087 if (ret_val) 3088 return ret_val; 3089 switch (hw->mac_type) { 3090 case e1000_80003es2lan: 3091 /* Kumeran registers are written-only */ 3092 reg_data = 3093 E1000_KUMCTRLSTA_INB_CTRL_LINK_STATUS_TX_TIMEOUT_DEFAULT; 3094 reg_data |= E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING; 3095 ret_val = e1000_write_kmrn_reg(hw, 3096 E1000_KUMCTRLSTA_OFFSET_INB_CTRL, reg_data); 3097 if (ret_val) 3098 return ret_val; 3099 break; 3100 default: 3101 break; 3102 } 3103 3104 if (hw->phy_type == e1000_phy_igp || 3105 hw->phy_type == e1000_phy_igp_3 || 3106 hw->phy_type == e1000_phy_igp_2) { 3107 ret_val = e1000_copper_link_igp_setup(hw); 3108 if (ret_val) 3109 return ret_val; 3110 } else if (hw->phy_type == e1000_phy_m88 || 3111 hw->phy_type == e1000_phy_igb) { 3112 ret_val = e1000_copper_link_mgp_setup(hw); 3113 if (ret_val) 3114 return ret_val; 3115 } else if (hw->phy_type == e1000_phy_gg82563) { 3116 ret_val = e1000_copper_link_ggp_setup(hw); 3117 if (ret_val) 3118 return ret_val; 3119 } 3120 3121 /* always auto */ 3122 /* Setup autoneg and flow control advertisement 3123 * and perform autonegotiation */ 3124 ret_val = e1000_copper_link_autoneg(hw); 3125 if (ret_val) 3126 return ret_val; 3127 3128 /* Check link status. Wait up to 100 microseconds for link to become 3129 * valid. 3130 */ 3131 for (i = 0; i < 10; i++) { 3132 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); 3133 if (ret_val) 3134 return ret_val; 3135 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); 3136 if (ret_val) 3137 return ret_val; 3138 3139 if (phy_data & MII_SR_LINK_STATUS) { 3140 /* Config the MAC and PHY after link is up */ 3141 ret_val = e1000_copper_link_postconfig(hw); 3142 if (ret_val) 3143 return ret_val; 3144 3145 DEBUGOUT("Valid link established!!!\n"); 3146 return E1000_SUCCESS; 3147 } 3148 udelay(10); 3149 } 3150 3151 DEBUGOUT("Unable to establish link!!!\n"); 3152 return E1000_SUCCESS; 3153 } 3154 3155 /****************************************************************************** 3156 * Configures PHY autoneg and flow control advertisement settings 3157 * 3158 * hw - Struct containing variables accessed by shared code 3159 ******************************************************************************/ 3160 int32_t 3161 e1000_phy_setup_autoneg(struct e1000_hw *hw) 3162 { 3163 int32_t ret_val; 3164 uint16_t mii_autoneg_adv_reg; 3165 uint16_t mii_1000t_ctrl_reg; 3166 3167 DEBUGFUNC(); 3168 3169 /* Read the MII Auto-Neg Advertisement Register (Address 4). */ 3170 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg); 3171 if (ret_val) 3172 return ret_val; 3173 3174 if (hw->phy_type != e1000_phy_ife) { 3175 /* Read the MII 1000Base-T Control Register (Address 9). */ 3176 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, 3177 &mii_1000t_ctrl_reg); 3178 if (ret_val) 3179 return ret_val; 3180 } else 3181 mii_1000t_ctrl_reg = 0; 3182 3183 /* Need to parse both autoneg_advertised and fc and set up 3184 * the appropriate PHY registers. First we will parse for 3185 * autoneg_advertised software override. Since we can advertise 3186 * a plethora of combinations, we need to check each bit 3187 * individually. 3188 */ 3189 3190 /* First we clear all the 10/100 mb speed bits in the Auto-Neg 3191 * Advertisement Register (Address 4) and the 1000 mb speed bits in 3192 * the 1000Base-T Control Register (Address 9). 3193 */ 3194 mii_autoneg_adv_reg &= ~REG4_SPEED_MASK; 3195 mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK; 3196 3197 DEBUGOUT("autoneg_advertised %x\n", hw->autoneg_advertised); 3198 3199 /* Do we want to advertise 10 Mb Half Duplex? */ 3200 if (hw->autoneg_advertised & ADVERTISE_10_HALF) { 3201 DEBUGOUT("Advertise 10mb Half duplex\n"); 3202 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS; 3203 } 3204 3205 /* Do we want to advertise 10 Mb Full Duplex? */ 3206 if (hw->autoneg_advertised & ADVERTISE_10_FULL) { 3207 DEBUGOUT("Advertise 10mb Full duplex\n"); 3208 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS; 3209 } 3210 3211 /* Do we want to advertise 100 Mb Half Duplex? */ 3212 if (hw->autoneg_advertised & ADVERTISE_100_HALF) { 3213 DEBUGOUT("Advertise 100mb Half duplex\n"); 3214 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS; 3215 } 3216 3217 /* Do we want to advertise 100 Mb Full Duplex? */ 3218 if (hw->autoneg_advertised & ADVERTISE_100_FULL) { 3219 DEBUGOUT("Advertise 100mb Full duplex\n"); 3220 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS; 3221 } 3222 3223 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */ 3224 if (hw->autoneg_advertised & ADVERTISE_1000_HALF) { 3225 DEBUGOUT 3226 ("Advertise 1000mb Half duplex requested, request denied!\n"); 3227 } 3228 3229 /* Do we want to advertise 1000 Mb Full Duplex? */ 3230 if (hw->autoneg_advertised & ADVERTISE_1000_FULL) { 3231 DEBUGOUT("Advertise 1000mb Full duplex\n"); 3232 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS; 3233 } 3234 3235 /* Check for a software override of the flow control settings, and 3236 * setup the PHY advertisement registers accordingly. If 3237 * auto-negotiation is enabled, then software will have to set the 3238 * "PAUSE" bits to the correct value in the Auto-Negotiation 3239 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation. 3240 * 3241 * The possible values of the "fc" parameter are: 3242 * 0: Flow control is completely disabled 3243 * 1: Rx flow control is enabled (we can receive pause frames 3244 * but not send pause frames). 3245 * 2: Tx flow control is enabled (we can send pause frames 3246 * but we do not support receiving pause frames). 3247 * 3: Both Rx and TX flow control (symmetric) are enabled. 3248 * other: No software override. The flow control configuration 3249 * in the EEPROM is used. 3250 */ 3251 switch (hw->fc) { 3252 case e1000_fc_none: /* 0 */ 3253 /* Flow control (RX & TX) is completely disabled by a 3254 * software over-ride. 3255 */ 3256 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 3257 break; 3258 case e1000_fc_rx_pause: /* 1 */ 3259 /* RX Flow control is enabled, and TX Flow control is 3260 * disabled, by a software over-ride. 3261 */ 3262 /* Since there really isn't a way to advertise that we are 3263 * capable of RX Pause ONLY, we will advertise that we 3264 * support both symmetric and asymmetric RX PAUSE. Later 3265 * (in e1000_config_fc_after_link_up) we will disable the 3266 *hw's ability to send PAUSE frames. 3267 */ 3268 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 3269 break; 3270 case e1000_fc_tx_pause: /* 2 */ 3271 /* TX Flow control is enabled, and RX Flow control is 3272 * disabled, by a software over-ride. 3273 */ 3274 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR; 3275 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE; 3276 break; 3277 case e1000_fc_full: /* 3 */ 3278 /* Flow control (both RX and TX) is enabled by a software 3279 * over-ride. 3280 */ 3281 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 3282 break; 3283 default: 3284 DEBUGOUT("Flow control param set incorrectly\n"); 3285 return -E1000_ERR_CONFIG; 3286 } 3287 3288 ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg); 3289 if (ret_val) 3290 return ret_val; 3291 3292 DEBUGOUT("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); 3293 3294 if (hw->phy_type != e1000_phy_ife) { 3295 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, 3296 mii_1000t_ctrl_reg); 3297 if (ret_val) 3298 return ret_val; 3299 } 3300 3301 return E1000_SUCCESS; 3302 } 3303 3304 /****************************************************************************** 3305 * Sets the collision distance in the Transmit Control register 3306 * 3307 * hw - Struct containing variables accessed by shared code 3308 * 3309 * Link should have been established previously. Reads the speed and duplex 3310 * information from the Device Status register. 3311 ******************************************************************************/ 3312 static void 3313 e1000_config_collision_dist(struct e1000_hw *hw) 3314 { 3315 uint32_t tctl, coll_dist; 3316 3317 DEBUGFUNC(); 3318 3319 if (hw->mac_type < e1000_82543) 3320 coll_dist = E1000_COLLISION_DISTANCE_82542; 3321 else 3322 coll_dist = E1000_COLLISION_DISTANCE; 3323 3324 tctl = E1000_READ_REG(hw, TCTL); 3325 3326 tctl &= ~E1000_TCTL_COLD; 3327 tctl |= coll_dist << E1000_COLD_SHIFT; 3328 3329 E1000_WRITE_REG(hw, TCTL, tctl); 3330 E1000_WRITE_FLUSH(hw); 3331 } 3332 3333 /****************************************************************************** 3334 * Sets MAC speed and duplex settings to reflect the those in the PHY 3335 * 3336 * hw - Struct containing variables accessed by shared code 3337 * mii_reg - data to write to the MII control register 3338 * 3339 * The contents of the PHY register containing the needed information need to 3340 * be passed in. 3341 ******************************************************************************/ 3342 static int 3343 e1000_config_mac_to_phy(struct e1000_hw *hw) 3344 { 3345 uint32_t ctrl; 3346 uint16_t phy_data; 3347 3348 DEBUGFUNC(); 3349 3350 /* Read the Device Control Register and set the bits to Force Speed 3351 * and Duplex. 3352 */ 3353 ctrl = E1000_READ_REG(hw, CTRL); 3354 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 3355 ctrl &= ~(E1000_CTRL_ILOS); 3356 ctrl |= (E1000_CTRL_SPD_SEL); 3357 3358 /* Set up duplex in the Device Control and Transmit Control 3359 * registers depending on negotiated values. 3360 */ 3361 if (e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data) < 0) { 3362 DEBUGOUT("PHY Read Error\n"); 3363 return -E1000_ERR_PHY; 3364 } 3365 if (phy_data & M88E1000_PSSR_DPLX) 3366 ctrl |= E1000_CTRL_FD; 3367 else 3368 ctrl &= ~E1000_CTRL_FD; 3369 3370 e1000_config_collision_dist(hw); 3371 3372 /* Set up speed in the Device Control register depending on 3373 * negotiated values. 3374 */ 3375 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) 3376 ctrl |= E1000_CTRL_SPD_1000; 3377 else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS) 3378 ctrl |= E1000_CTRL_SPD_100; 3379 /* Write the configured values back to the Device Control Reg. */ 3380 E1000_WRITE_REG(hw, CTRL, ctrl); 3381 return 0; 3382 } 3383 3384 /****************************************************************************** 3385 * Forces the MAC's flow control settings. 3386 * 3387 * hw - Struct containing variables accessed by shared code 3388 * 3389 * Sets the TFCE and RFCE bits in the device control register to reflect 3390 * the adapter settings. TFCE and RFCE need to be explicitly set by 3391 * software when a Copper PHY is used because autonegotiation is managed 3392 * by the PHY rather than the MAC. Software must also configure these 3393 * bits when link is forced on a fiber connection. 3394 *****************************************************************************/ 3395 static int 3396 e1000_force_mac_fc(struct e1000_hw *hw) 3397 { 3398 uint32_t ctrl; 3399 3400 DEBUGFUNC(); 3401 3402 /* Get the current configuration of the Device Control Register */ 3403 ctrl = E1000_READ_REG(hw, CTRL); 3404 3405 /* Because we didn't get link via the internal auto-negotiation 3406 * mechanism (we either forced link or we got link via PHY 3407 * auto-neg), we have to manually enable/disable transmit an 3408 * receive flow control. 3409 * 3410 * The "Case" statement below enables/disable flow control 3411 * according to the "hw->fc" parameter. 3412 * 3413 * The possible values of the "fc" parameter are: 3414 * 0: Flow control is completely disabled 3415 * 1: Rx flow control is enabled (we can receive pause 3416 * frames but not send pause frames). 3417 * 2: Tx flow control is enabled (we can send pause frames 3418 * frames but we do not receive pause frames). 3419 * 3: Both Rx and TX flow control (symmetric) is enabled. 3420 * other: No other values should be possible at this point. 3421 */ 3422 3423 switch (hw->fc) { 3424 case e1000_fc_none: 3425 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE)); 3426 break; 3427 case e1000_fc_rx_pause: 3428 ctrl &= (~E1000_CTRL_TFCE); 3429 ctrl |= E1000_CTRL_RFCE; 3430 break; 3431 case e1000_fc_tx_pause: 3432 ctrl &= (~E1000_CTRL_RFCE); 3433 ctrl |= E1000_CTRL_TFCE; 3434 break; 3435 case e1000_fc_full: 3436 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE); 3437 break; 3438 default: 3439 DEBUGOUT("Flow control param set incorrectly\n"); 3440 return -E1000_ERR_CONFIG; 3441 } 3442 3443 /* Disable TX Flow Control for 82542 (rev 2.0) */ 3444 if (hw->mac_type == e1000_82542_rev2_0) 3445 ctrl &= (~E1000_CTRL_TFCE); 3446 3447 E1000_WRITE_REG(hw, CTRL, ctrl); 3448 return 0; 3449 } 3450 3451 /****************************************************************************** 3452 * Configures flow control settings after link is established 3453 * 3454 * hw - Struct containing variables accessed by shared code 3455 * 3456 * Should be called immediately after a valid link has been established. 3457 * Forces MAC flow control settings if link was forced. When in MII/GMII mode 3458 * and autonegotiation is enabled, the MAC flow control settings will be set 3459 * based on the flow control negotiated by the PHY. In TBI mode, the TFCE 3460 * and RFCE bits will be automaticaly set to the negotiated flow control mode. 3461 *****************************************************************************/ 3462 static int32_t 3463 e1000_config_fc_after_link_up(struct e1000_hw *hw) 3464 { 3465 int32_t ret_val; 3466 uint16_t mii_status_reg; 3467 uint16_t mii_nway_adv_reg; 3468 uint16_t mii_nway_lp_ability_reg; 3469 uint16_t speed; 3470 uint16_t duplex; 3471 3472 DEBUGFUNC(); 3473 3474 /* Check for the case where we have fiber media and auto-neg failed 3475 * so we had to force link. In this case, we need to force the 3476 * configuration of the MAC to match the "fc" parameter. 3477 */ 3478 if (((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed)) 3479 || ((hw->media_type == e1000_media_type_internal_serdes) 3480 && (hw->autoneg_failed)) 3481 || ((hw->media_type == e1000_media_type_copper) 3482 && (!hw->autoneg))) { 3483 ret_val = e1000_force_mac_fc(hw); 3484 if (ret_val < 0) { 3485 DEBUGOUT("Error forcing flow control settings\n"); 3486 return ret_val; 3487 } 3488 } 3489 3490 /* Check for the case where we have copper media and auto-neg is 3491 * enabled. In this case, we need to check and see if Auto-Neg 3492 * has completed, and if so, how the PHY and link partner has 3493 * flow control configured. 3494 */ 3495 if (hw->media_type == e1000_media_type_copper) { 3496 /* Read the MII Status Register and check to see if AutoNeg 3497 * has completed. We read this twice because this reg has 3498 * some "sticky" (latched) bits. 3499 */ 3500 if (e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) { 3501 DEBUGOUT("PHY Read Error\n"); 3502 return -E1000_ERR_PHY; 3503 } 3504 if (e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) { 3505 DEBUGOUT("PHY Read Error\n"); 3506 return -E1000_ERR_PHY; 3507 } 3508 3509 if (mii_status_reg & MII_SR_AUTONEG_COMPLETE) { 3510 /* The AutoNeg process has completed, so we now need to 3511 * read both the Auto Negotiation Advertisement Register 3512 * (Address 4) and the Auto_Negotiation Base Page Ability 3513 * Register (Address 5) to determine how flow control was 3514 * negotiated. 3515 */ 3516 if (e1000_read_phy_reg 3517 (hw, PHY_AUTONEG_ADV, &mii_nway_adv_reg) < 0) { 3518 DEBUGOUT("PHY Read Error\n"); 3519 return -E1000_ERR_PHY; 3520 } 3521 if (e1000_read_phy_reg 3522 (hw, PHY_LP_ABILITY, 3523 &mii_nway_lp_ability_reg) < 0) { 3524 DEBUGOUT("PHY Read Error\n"); 3525 return -E1000_ERR_PHY; 3526 } 3527 3528 /* Two bits in the Auto Negotiation Advertisement Register 3529 * (Address 4) and two bits in the Auto Negotiation Base 3530 * Page Ability Register (Address 5) determine flow control 3531 * for both the PHY and the link partner. The following 3532 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25, 3533 * 1999, describes these PAUSE resolution bits and how flow 3534 * control is determined based upon these settings. 3535 * NOTE: DC = Don't Care 3536 * 3537 * LOCAL DEVICE | LINK PARTNER 3538 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution 3539 *-------|---------|-------|---------|-------------------- 3540 * 0 | 0 | DC | DC | e1000_fc_none 3541 * 0 | 1 | 0 | DC | e1000_fc_none 3542 * 0 | 1 | 1 | 0 | e1000_fc_none 3543 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 3544 * 1 | 0 | 0 | DC | e1000_fc_none 3545 * 1 | DC | 1 | DC | e1000_fc_full 3546 * 1 | 1 | 0 | 0 | e1000_fc_none 3547 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 3548 * 3549 */ 3550 /* Are both PAUSE bits set to 1? If so, this implies 3551 * Symmetric Flow Control is enabled at both ends. The 3552 * ASM_DIR bits are irrelevant per the spec. 3553 * 3554 * For Symmetric Flow Control: 3555 * 3556 * LOCAL DEVICE | LINK PARTNER 3557 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 3558 *-------|---------|-------|---------|-------------------- 3559 * 1 | DC | 1 | DC | e1000_fc_full 3560 * 3561 */ 3562 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 3563 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) { 3564 /* Now we need to check if the user selected RX ONLY 3565 * of pause frames. In this case, we had to advertise 3566 * FULL flow control because we could not advertise RX 3567 * ONLY. Hence, we must now check to see if we need to 3568 * turn OFF the TRANSMISSION of PAUSE frames. 3569 */ 3570 if (hw->original_fc == e1000_fc_full) { 3571 hw->fc = e1000_fc_full; 3572 DEBUGOUT("Flow Control = FULL.\r\n"); 3573 } else { 3574 hw->fc = e1000_fc_rx_pause; 3575 DEBUGOUT 3576 ("Flow Control = RX PAUSE frames only.\r\n"); 3577 } 3578 } 3579 /* For receiving PAUSE frames ONLY. 3580 * 3581 * LOCAL DEVICE | LINK PARTNER 3582 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 3583 *-------|---------|-------|---------|-------------------- 3584 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 3585 * 3586 */ 3587 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) && 3588 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 3589 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 3590 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) 3591 { 3592 hw->fc = e1000_fc_tx_pause; 3593 DEBUGOUT 3594 ("Flow Control = TX PAUSE frames only.\r\n"); 3595 } 3596 /* For transmitting PAUSE frames ONLY. 3597 * 3598 * LOCAL DEVICE | LINK PARTNER 3599 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 3600 *-------|---------|-------|---------|-------------------- 3601 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 3602 * 3603 */ 3604 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 3605 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 3606 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 3607 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) 3608 { 3609 hw->fc = e1000_fc_rx_pause; 3610 DEBUGOUT 3611 ("Flow Control = RX PAUSE frames only.\r\n"); 3612 } 3613 /* Per the IEEE spec, at this point flow control should be 3614 * disabled. However, we want to consider that we could 3615 * be connected to a legacy switch that doesn't advertise 3616 * desired flow control, but can be forced on the link 3617 * partner. So if we advertised no flow control, that is 3618 * what we will resolve to. If we advertised some kind of 3619 * receive capability (Rx Pause Only or Full Flow Control) 3620 * and the link partner advertised none, we will configure 3621 * ourselves to enable Rx Flow Control only. We can do 3622 * this safely for two reasons: If the link partner really 3623 * didn't want flow control enabled, and we enable Rx, no 3624 * harm done since we won't be receiving any PAUSE frames 3625 * anyway. If the intent on the link partner was to have 3626 * flow control enabled, then by us enabling RX only, we 3627 * can at least receive pause frames and process them. 3628 * This is a good idea because in most cases, since we are 3629 * predominantly a server NIC, more times than not we will 3630 * be asked to delay transmission of packets than asking 3631 * our link partner to pause transmission of frames. 3632 */ 3633 else if (hw->original_fc == e1000_fc_none || 3634 hw->original_fc == e1000_fc_tx_pause) { 3635 hw->fc = e1000_fc_none; 3636 DEBUGOUT("Flow Control = NONE.\r\n"); 3637 } else { 3638 hw->fc = e1000_fc_rx_pause; 3639 DEBUGOUT 3640 ("Flow Control = RX PAUSE frames only.\r\n"); 3641 } 3642 3643 /* Now we need to do one last check... If we auto- 3644 * negotiated to HALF DUPLEX, flow control should not be 3645 * enabled per IEEE 802.3 spec. 3646 */ 3647 e1000_get_speed_and_duplex(hw, &speed, &duplex); 3648 3649 if (duplex == HALF_DUPLEX) 3650 hw->fc = e1000_fc_none; 3651 3652 /* Now we call a subroutine to actually force the MAC 3653 * controller to use the correct flow control settings. 3654 */ 3655 ret_val = e1000_force_mac_fc(hw); 3656 if (ret_val < 0) { 3657 DEBUGOUT 3658 ("Error forcing flow control settings\n"); 3659 return ret_val; 3660 } 3661 } else { 3662 DEBUGOUT 3663 ("Copper PHY and Auto Neg has not completed.\r\n"); 3664 } 3665 } 3666 return E1000_SUCCESS; 3667 } 3668 3669 /****************************************************************************** 3670 * Checks to see if the link status of the hardware has changed. 3671 * 3672 * hw - Struct containing variables accessed by shared code 3673 * 3674 * Called by any function that needs to check the link status of the adapter. 3675 *****************************************************************************/ 3676 static int 3677 e1000_check_for_link(struct eth_device *nic) 3678 { 3679 struct e1000_hw *hw = nic->priv; 3680 uint32_t rxcw; 3681 uint32_t ctrl; 3682 uint32_t status; 3683 uint32_t rctl; 3684 uint32_t signal; 3685 int32_t ret_val; 3686 uint16_t phy_data; 3687 uint16_t lp_capability; 3688 3689 DEBUGFUNC(); 3690 3691 /* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be 3692 * set when the optics detect a signal. On older adapters, it will be 3693 * cleared when there is a signal 3694 */ 3695 ctrl = E1000_READ_REG(hw, CTRL); 3696 if ((hw->mac_type > e1000_82544) && !(ctrl & E1000_CTRL_ILOS)) 3697 signal = E1000_CTRL_SWDPIN1; 3698 else 3699 signal = 0; 3700 3701 status = E1000_READ_REG(hw, STATUS); 3702 rxcw = E1000_READ_REG(hw, RXCW); 3703 DEBUGOUT("ctrl: %#08x status %#08x rxcw %#08x\n", ctrl, status, rxcw); 3704 3705 /* If we have a copper PHY then we only want to go out to the PHY 3706 * registers to see if Auto-Neg has completed and/or if our link 3707 * status has changed. The get_link_status flag will be set if we 3708 * receive a Link Status Change interrupt or we have Rx Sequence 3709 * Errors. 3710 */ 3711 if ((hw->media_type == e1000_media_type_copper) && hw->get_link_status) { 3712 /* First we want to see if the MII Status Register reports 3713 * link. If so, then we want to get the current speed/duplex 3714 * of the PHY. 3715 * Read the register twice since the link bit is sticky. 3716 */ 3717 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) { 3718 DEBUGOUT("PHY Read Error\n"); 3719 return -E1000_ERR_PHY; 3720 } 3721 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) { 3722 DEBUGOUT("PHY Read Error\n"); 3723 return -E1000_ERR_PHY; 3724 } 3725 3726 if (phy_data & MII_SR_LINK_STATUS) { 3727 hw->get_link_status = false; 3728 } else { 3729 /* No link detected */ 3730 return -E1000_ERR_NOLINK; 3731 } 3732 3733 /* We have a M88E1000 PHY and Auto-Neg is enabled. If we 3734 * have Si on board that is 82544 or newer, Auto 3735 * Speed Detection takes care of MAC speed/duplex 3736 * configuration. So we only need to configure Collision 3737 * Distance in the MAC. Otherwise, we need to force 3738 * speed/duplex on the MAC to the current PHY speed/duplex 3739 * settings. 3740 */ 3741 if (hw->mac_type >= e1000_82544) 3742 e1000_config_collision_dist(hw); 3743 else { 3744 ret_val = e1000_config_mac_to_phy(hw); 3745 if (ret_val < 0) { 3746 DEBUGOUT 3747 ("Error configuring MAC to PHY settings\n"); 3748 return ret_val; 3749 } 3750 } 3751 3752 /* Configure Flow Control now that Auto-Neg has completed. First, we 3753 * need to restore the desired flow control settings because we may 3754 * have had to re-autoneg with a different link partner. 3755 */ 3756 ret_val = e1000_config_fc_after_link_up(hw); 3757 if (ret_val < 0) { 3758 DEBUGOUT("Error configuring flow control\n"); 3759 return ret_val; 3760 } 3761 3762 /* At this point we know that we are on copper and we have 3763 * auto-negotiated link. These are conditions for checking the link 3764 * parter capability register. We use the link partner capability to 3765 * determine if TBI Compatibility needs to be turned on or off. If 3766 * the link partner advertises any speed in addition to Gigabit, then 3767 * we assume that they are GMII-based, and TBI compatibility is not 3768 * needed. If no other speeds are advertised, we assume the link 3769 * partner is TBI-based, and we turn on TBI Compatibility. 3770 */ 3771 if (hw->tbi_compatibility_en) { 3772 if (e1000_read_phy_reg 3773 (hw, PHY_LP_ABILITY, &lp_capability) < 0) { 3774 DEBUGOUT("PHY Read Error\n"); 3775 return -E1000_ERR_PHY; 3776 } 3777 if (lp_capability & (NWAY_LPAR_10T_HD_CAPS | 3778 NWAY_LPAR_10T_FD_CAPS | 3779 NWAY_LPAR_100TX_HD_CAPS | 3780 NWAY_LPAR_100TX_FD_CAPS | 3781 NWAY_LPAR_100T4_CAPS)) { 3782 /* If our link partner advertises anything in addition to 3783 * gigabit, we do not need to enable TBI compatibility. 3784 */ 3785 if (hw->tbi_compatibility_on) { 3786 /* If we previously were in the mode, turn it off. */ 3787 rctl = E1000_READ_REG(hw, RCTL); 3788 rctl &= ~E1000_RCTL_SBP; 3789 E1000_WRITE_REG(hw, RCTL, rctl); 3790 hw->tbi_compatibility_on = false; 3791 } 3792 } else { 3793 /* If TBI compatibility is was previously off, turn it on. For 3794 * compatibility with a TBI link partner, we will store bad 3795 * packets. Some frames have an additional byte on the end and 3796 * will look like CRC errors to to the hardware. 3797 */ 3798 if (!hw->tbi_compatibility_on) { 3799 hw->tbi_compatibility_on = true; 3800 rctl = E1000_READ_REG(hw, RCTL); 3801 rctl |= E1000_RCTL_SBP; 3802 E1000_WRITE_REG(hw, RCTL, rctl); 3803 } 3804 } 3805 } 3806 } 3807 /* If we don't have link (auto-negotiation failed or link partner cannot 3808 * auto-negotiate), the cable is plugged in (we have signal), and our 3809 * link partner is not trying to auto-negotiate with us (we are receiving 3810 * idles or data), we need to force link up. We also need to give 3811 * auto-negotiation time to complete, in case the cable was just plugged 3812 * in. The autoneg_failed flag does this. 3813 */ 3814 else if ((hw->media_type == e1000_media_type_fiber) && 3815 (!(status & E1000_STATUS_LU)) && 3816 ((ctrl & E1000_CTRL_SWDPIN1) == signal) && 3817 (!(rxcw & E1000_RXCW_C))) { 3818 if (hw->autoneg_failed == 0) { 3819 hw->autoneg_failed = 1; 3820 return 0; 3821 } 3822 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\r\n"); 3823 3824 /* Disable auto-negotiation in the TXCW register */ 3825 E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE)); 3826 3827 /* Force link-up and also force full-duplex. */ 3828 ctrl = E1000_READ_REG(hw, CTRL); 3829 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 3830 E1000_WRITE_REG(hw, CTRL, ctrl); 3831 3832 /* Configure Flow Control after forcing link up. */ 3833 ret_val = e1000_config_fc_after_link_up(hw); 3834 if (ret_val < 0) { 3835 DEBUGOUT("Error configuring flow control\n"); 3836 return ret_val; 3837 } 3838 } 3839 /* If we are forcing link and we are receiving /C/ ordered sets, re-enable 3840 * auto-negotiation in the TXCW register and disable forced link in the 3841 * Device Control register in an attempt to auto-negotiate with our link 3842 * partner. 3843 */ 3844 else if ((hw->media_type == e1000_media_type_fiber) && 3845 (ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { 3846 DEBUGOUT 3847 ("RXing /C/, enable AutoNeg and stop forcing link.\r\n"); 3848 E1000_WRITE_REG(hw, TXCW, hw->txcw); 3849 E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU)); 3850 } 3851 return 0; 3852 } 3853 3854 /****************************************************************************** 3855 * Configure the MAC-to-PHY interface for 10/100Mbps 3856 * 3857 * hw - Struct containing variables accessed by shared code 3858 ******************************************************************************/ 3859 static int32_t 3860 e1000_configure_kmrn_for_10_100(struct e1000_hw *hw, uint16_t duplex) 3861 { 3862 int32_t ret_val = E1000_SUCCESS; 3863 uint32_t tipg; 3864 uint16_t reg_data; 3865 3866 DEBUGFUNC(); 3867 3868 reg_data = E1000_KUMCTRLSTA_HD_CTRL_10_100_DEFAULT; 3869 ret_val = e1000_write_kmrn_reg(hw, 3870 E1000_KUMCTRLSTA_OFFSET_HD_CTRL, reg_data); 3871 if (ret_val) 3872 return ret_val; 3873 3874 /* Configure Transmit Inter-Packet Gap */ 3875 tipg = E1000_READ_REG(hw, TIPG); 3876 tipg &= ~E1000_TIPG_IPGT_MASK; 3877 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_10_100; 3878 E1000_WRITE_REG(hw, TIPG, tipg); 3879 3880 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data); 3881 3882 if (ret_val) 3883 return ret_val; 3884 3885 if (duplex == HALF_DUPLEX) 3886 reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER; 3887 else 3888 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; 3889 3890 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data); 3891 3892 return ret_val; 3893 } 3894 3895 static int32_t 3896 e1000_configure_kmrn_for_1000(struct e1000_hw *hw) 3897 { 3898 int32_t ret_val = E1000_SUCCESS; 3899 uint16_t reg_data; 3900 uint32_t tipg; 3901 3902 DEBUGFUNC(); 3903 3904 reg_data = E1000_KUMCTRLSTA_HD_CTRL_1000_DEFAULT; 3905 ret_val = e1000_write_kmrn_reg(hw, 3906 E1000_KUMCTRLSTA_OFFSET_HD_CTRL, reg_data); 3907 if (ret_val) 3908 return ret_val; 3909 3910 /* Configure Transmit Inter-Packet Gap */ 3911 tipg = E1000_READ_REG(hw, TIPG); 3912 tipg &= ~E1000_TIPG_IPGT_MASK; 3913 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000; 3914 E1000_WRITE_REG(hw, TIPG, tipg); 3915 3916 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data); 3917 3918 if (ret_val) 3919 return ret_val; 3920 3921 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; 3922 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data); 3923 3924 return ret_val; 3925 } 3926 3927 /****************************************************************************** 3928 * Detects the current speed and duplex settings of the hardware. 3929 * 3930 * hw - Struct containing variables accessed by shared code 3931 * speed - Speed of the connection 3932 * duplex - Duplex setting of the connection 3933 *****************************************************************************/ 3934 static int 3935 e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t *speed, 3936 uint16_t *duplex) 3937 { 3938 uint32_t status; 3939 int32_t ret_val; 3940 uint16_t phy_data; 3941 3942 DEBUGFUNC(); 3943 3944 if (hw->mac_type >= e1000_82543) { 3945 status = E1000_READ_REG(hw, STATUS); 3946 if (status & E1000_STATUS_SPEED_1000) { 3947 *speed = SPEED_1000; 3948 DEBUGOUT("1000 Mbs, "); 3949 } else if (status & E1000_STATUS_SPEED_100) { 3950 *speed = SPEED_100; 3951 DEBUGOUT("100 Mbs, "); 3952 } else { 3953 *speed = SPEED_10; 3954 DEBUGOUT("10 Mbs, "); 3955 } 3956 3957 if (status & E1000_STATUS_FD) { 3958 *duplex = FULL_DUPLEX; 3959 DEBUGOUT("Full Duplex\r\n"); 3960 } else { 3961 *duplex = HALF_DUPLEX; 3962 DEBUGOUT(" Half Duplex\r\n"); 3963 } 3964 } else { 3965 DEBUGOUT("1000 Mbs, Full Duplex\r\n"); 3966 *speed = SPEED_1000; 3967 *duplex = FULL_DUPLEX; 3968 } 3969 3970 /* IGP01 PHY may advertise full duplex operation after speed downgrade 3971 * even if it is operating at half duplex. Here we set the duplex 3972 * settings to match the duplex in the link partner's capabilities. 3973 */ 3974 if (hw->phy_type == e1000_phy_igp && hw->speed_downgraded) { 3975 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data); 3976 if (ret_val) 3977 return ret_val; 3978 3979 if (!(phy_data & NWAY_ER_LP_NWAY_CAPS)) 3980 *duplex = HALF_DUPLEX; 3981 else { 3982 ret_val = e1000_read_phy_reg(hw, 3983 PHY_LP_ABILITY, &phy_data); 3984 if (ret_val) 3985 return ret_val; 3986 if ((*speed == SPEED_100 && 3987 !(phy_data & NWAY_LPAR_100TX_FD_CAPS)) 3988 || (*speed == SPEED_10 3989 && !(phy_data & NWAY_LPAR_10T_FD_CAPS))) 3990 *duplex = HALF_DUPLEX; 3991 } 3992 } 3993 3994 if ((hw->mac_type == e1000_80003es2lan) && 3995 (hw->media_type == e1000_media_type_copper)) { 3996 if (*speed == SPEED_1000) 3997 ret_val = e1000_configure_kmrn_for_1000(hw); 3998 else 3999 ret_val = e1000_configure_kmrn_for_10_100(hw, *duplex); 4000 if (ret_val) 4001 return ret_val; 4002 } 4003 return E1000_SUCCESS; 4004 } 4005 4006 /****************************************************************************** 4007 * Blocks until autoneg completes or times out (~4.5 seconds) 4008 * 4009 * hw - Struct containing variables accessed by shared code 4010 ******************************************************************************/ 4011 static int 4012 e1000_wait_autoneg(struct e1000_hw *hw) 4013 { 4014 uint16_t i; 4015 uint16_t phy_data; 4016 4017 DEBUGFUNC(); 4018 DEBUGOUT("Waiting for Auto-Neg to complete.\n"); 4019 4020 /* We will wait for autoneg to complete or timeout to expire. */ 4021 for (i = PHY_AUTO_NEG_TIME; i > 0; i--) { 4022 /* Read the MII Status Register and wait for Auto-Neg 4023 * Complete bit to be set. 4024 */ 4025 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) { 4026 DEBUGOUT("PHY Read Error\n"); 4027 return -E1000_ERR_PHY; 4028 } 4029 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) { 4030 DEBUGOUT("PHY Read Error\n"); 4031 return -E1000_ERR_PHY; 4032 } 4033 if (phy_data & MII_SR_AUTONEG_COMPLETE) { 4034 DEBUGOUT("Auto-Neg complete.\n"); 4035 return 0; 4036 } 4037 mdelay(100); 4038 } 4039 DEBUGOUT("Auto-Neg timedout.\n"); 4040 return -E1000_ERR_TIMEOUT; 4041 } 4042 4043 /****************************************************************************** 4044 * Raises the Management Data Clock 4045 * 4046 * hw - Struct containing variables accessed by shared code 4047 * ctrl - Device control register's current value 4048 ******************************************************************************/ 4049 static void 4050 e1000_raise_mdi_clk(struct e1000_hw *hw, uint32_t * ctrl) 4051 { 4052 /* Raise the clock input to the Management Data Clock (by setting the MDC 4053 * bit), and then delay 2 microseconds. 4054 */ 4055 E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC)); 4056 E1000_WRITE_FLUSH(hw); 4057 udelay(2); 4058 } 4059 4060 /****************************************************************************** 4061 * Lowers the Management Data Clock 4062 * 4063 * hw - Struct containing variables accessed by shared code 4064 * ctrl - Device control register's current value 4065 ******************************************************************************/ 4066 static void 4067 e1000_lower_mdi_clk(struct e1000_hw *hw, uint32_t * ctrl) 4068 { 4069 /* Lower the clock input to the Management Data Clock (by clearing the MDC 4070 * bit), and then delay 2 microseconds. 4071 */ 4072 E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC)); 4073 E1000_WRITE_FLUSH(hw); 4074 udelay(2); 4075 } 4076 4077 /****************************************************************************** 4078 * Shifts data bits out to the PHY 4079 * 4080 * hw - Struct containing variables accessed by shared code 4081 * data - Data to send out to the PHY 4082 * count - Number of bits to shift out 4083 * 4084 * Bits are shifted out in MSB to LSB order. 4085 ******************************************************************************/ 4086 static void 4087 e1000_shift_out_mdi_bits(struct e1000_hw *hw, uint32_t data, uint16_t count) 4088 { 4089 uint32_t ctrl; 4090 uint32_t mask; 4091 4092 /* We need to shift "count" number of bits out to the PHY. So, the value 4093 * in the "data" parameter will be shifted out to the PHY one bit at a 4094 * time. In order to do this, "data" must be broken down into bits. 4095 */ 4096 mask = 0x01; 4097 mask <<= (count - 1); 4098 4099 ctrl = E1000_READ_REG(hw, CTRL); 4100 4101 /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */ 4102 ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR); 4103 4104 while (mask) { 4105 /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and 4106 * then raising and lowering the Management Data Clock. A "0" is 4107 * shifted out to the PHY by setting the MDIO bit to "0" and then 4108 * raising and lowering the clock. 4109 */ 4110 if (data & mask) 4111 ctrl |= E1000_CTRL_MDIO; 4112 else 4113 ctrl &= ~E1000_CTRL_MDIO; 4114 4115 E1000_WRITE_REG(hw, CTRL, ctrl); 4116 E1000_WRITE_FLUSH(hw); 4117 4118 udelay(2); 4119 4120 e1000_raise_mdi_clk(hw, &ctrl); 4121 e1000_lower_mdi_clk(hw, &ctrl); 4122 4123 mask = mask >> 1; 4124 } 4125 } 4126 4127 /****************************************************************************** 4128 * Shifts data bits in from the PHY 4129 * 4130 * hw - Struct containing variables accessed by shared code 4131 * 4132 * Bits are shifted in in MSB to LSB order. 4133 ******************************************************************************/ 4134 static uint16_t 4135 e1000_shift_in_mdi_bits(struct e1000_hw *hw) 4136 { 4137 uint32_t ctrl; 4138 uint16_t data = 0; 4139 uint8_t i; 4140 4141 /* In order to read a register from the PHY, we need to shift in a total 4142 * of 18 bits from the PHY. The first two bit (turnaround) times are used 4143 * to avoid contention on the MDIO pin when a read operation is performed. 4144 * These two bits are ignored by us and thrown away. Bits are "shifted in" 4145 * by raising the input to the Management Data Clock (setting the MDC bit), 4146 * and then reading the value of the MDIO bit. 4147 */ 4148 ctrl = E1000_READ_REG(hw, CTRL); 4149 4150 /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */ 4151 ctrl &= ~E1000_CTRL_MDIO_DIR; 4152 ctrl &= ~E1000_CTRL_MDIO; 4153 4154 E1000_WRITE_REG(hw, CTRL, ctrl); 4155 E1000_WRITE_FLUSH(hw); 4156 4157 /* Raise and Lower the clock before reading in the data. This accounts for 4158 * the turnaround bits. The first clock occurred when we clocked out the 4159 * last bit of the Register Address. 4160 */ 4161 e1000_raise_mdi_clk(hw, &ctrl); 4162 e1000_lower_mdi_clk(hw, &ctrl); 4163 4164 for (data = 0, i = 0; i < 16; i++) { 4165 data = data << 1; 4166 e1000_raise_mdi_clk(hw, &ctrl); 4167 ctrl = E1000_READ_REG(hw, CTRL); 4168 /* Check to see if we shifted in a "1". */ 4169 if (ctrl & E1000_CTRL_MDIO) 4170 data |= 1; 4171 e1000_lower_mdi_clk(hw, &ctrl); 4172 } 4173 4174 e1000_raise_mdi_clk(hw, &ctrl); 4175 e1000_lower_mdi_clk(hw, &ctrl); 4176 4177 return data; 4178 } 4179 4180 /***************************************************************************** 4181 * Reads the value from a PHY register 4182 * 4183 * hw - Struct containing variables accessed by shared code 4184 * reg_addr - address of the PHY register to read 4185 ******************************************************************************/ 4186 static int 4187 e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t * phy_data) 4188 { 4189 uint32_t i; 4190 uint32_t mdic = 0; 4191 const uint32_t phy_addr = 1; 4192 4193 if (reg_addr > MAX_PHY_REG_ADDRESS) { 4194 DEBUGOUT("PHY Address %d is out of range\n", reg_addr); 4195 return -E1000_ERR_PARAM; 4196 } 4197 4198 if (hw->mac_type > e1000_82543) { 4199 /* Set up Op-code, Phy Address, and register address in the MDI 4200 * Control register. The MAC will take care of interfacing with the 4201 * PHY to retrieve the desired data. 4202 */ 4203 mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) | 4204 (phy_addr << E1000_MDIC_PHY_SHIFT) | 4205 (E1000_MDIC_OP_READ)); 4206 4207 E1000_WRITE_REG(hw, MDIC, mdic); 4208 4209 /* Poll the ready bit to see if the MDI read completed */ 4210 for (i = 0; i < 64; i++) { 4211 udelay(10); 4212 mdic = E1000_READ_REG(hw, MDIC); 4213 if (mdic & E1000_MDIC_READY) 4214 break; 4215 } 4216 if (!(mdic & E1000_MDIC_READY)) { 4217 DEBUGOUT("MDI Read did not complete\n"); 4218 return -E1000_ERR_PHY; 4219 } 4220 if (mdic & E1000_MDIC_ERROR) { 4221 DEBUGOUT("MDI Error\n"); 4222 return -E1000_ERR_PHY; 4223 } 4224 *phy_data = (uint16_t) mdic; 4225 } else { 4226 /* We must first send a preamble through the MDIO pin to signal the 4227 * beginning of an MII instruction. This is done by sending 32 4228 * consecutive "1" bits. 4229 */ 4230 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); 4231 4232 /* Now combine the next few fields that are required for a read 4233 * operation. We use this method instead of calling the 4234 * e1000_shift_out_mdi_bits routine five different times. The format of 4235 * a MII read instruction consists of a shift out of 14 bits and is 4236 * defined as follows: 4237 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr> 4238 * followed by a shift in of 18 bits. This first two bits shifted in 4239 * are TurnAround bits used to avoid contention on the MDIO pin when a 4240 * READ operation is performed. These two bits are thrown away 4241 * followed by a shift in of 16 bits which contains the desired data. 4242 */ 4243 mdic = ((reg_addr) | (phy_addr << 5) | 4244 (PHY_OP_READ << 10) | (PHY_SOF << 12)); 4245 4246 e1000_shift_out_mdi_bits(hw, mdic, 14); 4247 4248 /* Now that we've shifted out the read command to the MII, we need to 4249 * "shift in" the 16-bit value (18 total bits) of the requested PHY 4250 * register address. 4251 */ 4252 *phy_data = e1000_shift_in_mdi_bits(hw); 4253 } 4254 return 0; 4255 } 4256 4257 /****************************************************************************** 4258 * Writes a value to a PHY register 4259 * 4260 * hw - Struct containing variables accessed by shared code 4261 * reg_addr - address of the PHY register to write 4262 * data - data to write to the PHY 4263 ******************************************************************************/ 4264 static int 4265 e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t phy_data) 4266 { 4267 uint32_t i; 4268 uint32_t mdic = 0; 4269 const uint32_t phy_addr = 1; 4270 4271 if (reg_addr > MAX_PHY_REG_ADDRESS) { 4272 DEBUGOUT("PHY Address %d is out of range\n", reg_addr); 4273 return -E1000_ERR_PARAM; 4274 } 4275 4276 if (hw->mac_type > e1000_82543) { 4277 /* Set up Op-code, Phy Address, register address, and data intended 4278 * for the PHY register in the MDI Control register. The MAC will take 4279 * care of interfacing with the PHY to send the desired data. 4280 */ 4281 mdic = (((uint32_t) phy_data) | 4282 (reg_addr << E1000_MDIC_REG_SHIFT) | 4283 (phy_addr << E1000_MDIC_PHY_SHIFT) | 4284 (E1000_MDIC_OP_WRITE)); 4285 4286 E1000_WRITE_REG(hw, MDIC, mdic); 4287 4288 /* Poll the ready bit to see if the MDI read completed */ 4289 for (i = 0; i < 64; i++) { 4290 udelay(10); 4291 mdic = E1000_READ_REG(hw, MDIC); 4292 if (mdic & E1000_MDIC_READY) 4293 break; 4294 } 4295 if (!(mdic & E1000_MDIC_READY)) { 4296 DEBUGOUT("MDI Write did not complete\n"); 4297 return -E1000_ERR_PHY; 4298 } 4299 } else { 4300 /* We'll need to use the SW defined pins to shift the write command 4301 * out to the PHY. We first send a preamble to the PHY to signal the 4302 * beginning of the MII instruction. This is done by sending 32 4303 * consecutive "1" bits. 4304 */ 4305 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); 4306 4307 /* Now combine the remaining required fields that will indicate a 4308 * write operation. We use this method instead of calling the 4309 * e1000_shift_out_mdi_bits routine for each field in the command. The 4310 * format of a MII write instruction is as follows: 4311 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>. 4312 */ 4313 mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) | 4314 (PHY_OP_WRITE << 12) | (PHY_SOF << 14)); 4315 mdic <<= 16; 4316 mdic |= (uint32_t) phy_data; 4317 4318 e1000_shift_out_mdi_bits(hw, mdic, 32); 4319 } 4320 return 0; 4321 } 4322 4323 /****************************************************************************** 4324 * Checks if PHY reset is blocked due to SOL/IDER session, for example. 4325 * Returning E1000_BLK_PHY_RESET isn't necessarily an error. But it's up to 4326 * the caller to figure out how to deal with it. 4327 * 4328 * hw - Struct containing variables accessed by shared code 4329 * 4330 * returns: - E1000_BLK_PHY_RESET 4331 * E1000_SUCCESS 4332 * 4333 *****************************************************************************/ 4334 int32_t 4335 e1000_check_phy_reset_block(struct e1000_hw *hw) 4336 { 4337 uint32_t manc = 0; 4338 uint32_t fwsm = 0; 4339 4340 if (hw->mac_type == e1000_ich8lan) { 4341 fwsm = E1000_READ_REG(hw, FWSM); 4342 return (fwsm & E1000_FWSM_RSPCIPHY) ? E1000_SUCCESS 4343 : E1000_BLK_PHY_RESET; 4344 } 4345 4346 if (hw->mac_type > e1000_82547_rev_2) 4347 manc = E1000_READ_REG(hw, MANC); 4348 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ? 4349 E1000_BLK_PHY_RESET : E1000_SUCCESS; 4350 } 4351 4352 /*************************************************************************** 4353 * Checks if the PHY configuration is done 4354 * 4355 * hw: Struct containing variables accessed by shared code 4356 * 4357 * returns: - E1000_ERR_RESET if fail to reset MAC 4358 * E1000_SUCCESS at any other case. 4359 * 4360 ***************************************************************************/ 4361 static int32_t 4362 e1000_get_phy_cfg_done(struct e1000_hw *hw) 4363 { 4364 int32_t timeout = PHY_CFG_TIMEOUT; 4365 uint32_t cfg_mask = E1000_EEPROM_CFG_DONE; 4366 4367 DEBUGFUNC(); 4368 4369 switch (hw->mac_type) { 4370 default: 4371 mdelay(10); 4372 break; 4373 4374 case e1000_80003es2lan: 4375 /* Separate *_CFG_DONE_* bit for each port */ 4376 if (e1000_is_second_port(hw)) 4377 cfg_mask = E1000_EEPROM_CFG_DONE_PORT_1; 4378 /* Fall Through */ 4379 4380 case e1000_82571: 4381 case e1000_82572: 4382 case e1000_igb: 4383 while (timeout) { 4384 if (hw->mac_type == e1000_igb) { 4385 if (E1000_READ_REG(hw, I210_EEMNGCTL) & cfg_mask) 4386 break; 4387 } else { 4388 if (E1000_READ_REG(hw, EEMNGCTL) & cfg_mask) 4389 break; 4390 } 4391 mdelay(1); 4392 timeout--; 4393 } 4394 if (!timeout) { 4395 DEBUGOUT("MNG configuration cycle has not " 4396 "completed.\n"); 4397 return -E1000_ERR_RESET; 4398 } 4399 break; 4400 } 4401 4402 return E1000_SUCCESS; 4403 } 4404 4405 /****************************************************************************** 4406 * Returns the PHY to the power-on reset state 4407 * 4408 * hw - Struct containing variables accessed by shared code 4409 ******************************************************************************/ 4410 int32_t 4411 e1000_phy_hw_reset(struct e1000_hw *hw) 4412 { 4413 uint16_t swfw = E1000_SWFW_PHY0_SM; 4414 uint32_t ctrl, ctrl_ext; 4415 uint32_t led_ctrl; 4416 int32_t ret_val; 4417 4418 DEBUGFUNC(); 4419 4420 /* In the case of the phy reset being blocked, it's not an error, we 4421 * simply return success without performing the reset. */ 4422 ret_val = e1000_check_phy_reset_block(hw); 4423 if (ret_val) 4424 return E1000_SUCCESS; 4425 4426 DEBUGOUT("Resetting Phy...\n"); 4427 4428 if (hw->mac_type > e1000_82543) { 4429 if (e1000_is_second_port(hw)) 4430 swfw = E1000_SWFW_PHY1_SM; 4431 4432 if (e1000_swfw_sync_acquire(hw, swfw)) { 4433 DEBUGOUT("Unable to acquire swfw sync\n"); 4434 return -E1000_ERR_SWFW_SYNC; 4435 } 4436 4437 /* Read the device control register and assert the E1000_CTRL_PHY_RST 4438 * bit. Then, take it out of reset. 4439 */ 4440 ctrl = E1000_READ_REG(hw, CTRL); 4441 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST); 4442 E1000_WRITE_FLUSH(hw); 4443 4444 if (hw->mac_type < e1000_82571) 4445 udelay(10); 4446 else 4447 udelay(100); 4448 4449 E1000_WRITE_REG(hw, CTRL, ctrl); 4450 E1000_WRITE_FLUSH(hw); 4451 4452 if (hw->mac_type >= e1000_82571) 4453 mdelay(10); 4454 4455 } else { 4456 /* Read the Extended Device Control Register, assert the PHY_RESET_DIR 4457 * bit to put the PHY into reset. Then, take it out of reset. 4458 */ 4459 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 4460 ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR; 4461 ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA; 4462 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 4463 E1000_WRITE_FLUSH(hw); 4464 mdelay(10); 4465 ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA; 4466 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 4467 E1000_WRITE_FLUSH(hw); 4468 } 4469 udelay(150); 4470 4471 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { 4472 /* Configure activity LED after PHY reset */ 4473 led_ctrl = E1000_READ_REG(hw, LEDCTL); 4474 led_ctrl &= IGP_ACTIVITY_LED_MASK; 4475 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); 4476 E1000_WRITE_REG(hw, LEDCTL, led_ctrl); 4477 } 4478 4479 e1000_swfw_sync_release(hw, swfw); 4480 4481 /* Wait for FW to finish PHY configuration. */ 4482 ret_val = e1000_get_phy_cfg_done(hw); 4483 if (ret_val != E1000_SUCCESS) 4484 return ret_val; 4485 4486 return ret_val; 4487 } 4488 4489 /****************************************************************************** 4490 * IGP phy init script - initializes the GbE PHY 4491 * 4492 * hw - Struct containing variables accessed by shared code 4493 *****************************************************************************/ 4494 static void 4495 e1000_phy_init_script(struct e1000_hw *hw) 4496 { 4497 uint32_t ret_val; 4498 uint16_t phy_saved_data; 4499 DEBUGFUNC(); 4500 4501 if (hw->phy_init_script) { 4502 mdelay(20); 4503 4504 /* Save off the current value of register 0x2F5B to be 4505 * restored at the end of this routine. */ 4506 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data); 4507 4508 /* Disabled the PHY transmitter */ 4509 e1000_write_phy_reg(hw, 0x2F5B, 0x0003); 4510 4511 mdelay(20); 4512 4513 e1000_write_phy_reg(hw, 0x0000, 0x0140); 4514 4515 mdelay(5); 4516 4517 switch (hw->mac_type) { 4518 case e1000_82541: 4519 case e1000_82547: 4520 e1000_write_phy_reg(hw, 0x1F95, 0x0001); 4521 4522 e1000_write_phy_reg(hw, 0x1F71, 0xBD21); 4523 4524 e1000_write_phy_reg(hw, 0x1F79, 0x0018); 4525 4526 e1000_write_phy_reg(hw, 0x1F30, 0x1600); 4527 4528 e1000_write_phy_reg(hw, 0x1F31, 0x0014); 4529 4530 e1000_write_phy_reg(hw, 0x1F32, 0x161C); 4531 4532 e1000_write_phy_reg(hw, 0x1F94, 0x0003); 4533 4534 e1000_write_phy_reg(hw, 0x1F96, 0x003F); 4535 4536 e1000_write_phy_reg(hw, 0x2010, 0x0008); 4537 break; 4538 4539 case e1000_82541_rev_2: 4540 case e1000_82547_rev_2: 4541 e1000_write_phy_reg(hw, 0x1F73, 0x0099); 4542 break; 4543 default: 4544 break; 4545 } 4546 4547 e1000_write_phy_reg(hw, 0x0000, 0x3300); 4548 4549 mdelay(20); 4550 4551 /* Now enable the transmitter */ 4552 if (!ret_val) 4553 e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data); 4554 4555 if (hw->mac_type == e1000_82547) { 4556 uint16_t fused, fine, coarse; 4557 4558 /* Move to analog registers page */ 4559 e1000_read_phy_reg(hw, 4560 IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused); 4561 4562 if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) { 4563 e1000_read_phy_reg(hw, 4564 IGP01E1000_ANALOG_FUSE_STATUS, &fused); 4565 4566 fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK; 4567 coarse = fused 4568 & IGP01E1000_ANALOG_FUSE_COARSE_MASK; 4569 4570 if (coarse > 4571 IGP01E1000_ANALOG_FUSE_COARSE_THRESH) { 4572 coarse -= 4573 IGP01E1000_ANALOG_FUSE_COARSE_10; 4574 fine -= IGP01E1000_ANALOG_FUSE_FINE_1; 4575 } else if (coarse 4576 == IGP01E1000_ANALOG_FUSE_COARSE_THRESH) 4577 fine -= IGP01E1000_ANALOG_FUSE_FINE_10; 4578 4579 fused = (fused 4580 & IGP01E1000_ANALOG_FUSE_POLY_MASK) | 4581 (fine 4582 & IGP01E1000_ANALOG_FUSE_FINE_MASK) | 4583 (coarse 4584 & IGP01E1000_ANALOG_FUSE_COARSE_MASK); 4585 4586 e1000_write_phy_reg(hw, 4587 IGP01E1000_ANALOG_FUSE_CONTROL, fused); 4588 e1000_write_phy_reg(hw, 4589 IGP01E1000_ANALOG_FUSE_BYPASS, 4590 IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL); 4591 } 4592 } 4593 } 4594 } 4595 4596 /****************************************************************************** 4597 * Resets the PHY 4598 * 4599 * hw - Struct containing variables accessed by shared code 4600 * 4601 * Sets bit 15 of the MII Control register 4602 ******************************************************************************/ 4603 int32_t 4604 e1000_phy_reset(struct e1000_hw *hw) 4605 { 4606 int32_t ret_val; 4607 uint16_t phy_data; 4608 4609 DEBUGFUNC(); 4610 4611 /* In the case of the phy reset being blocked, it's not an error, we 4612 * simply return success without performing the reset. */ 4613 ret_val = e1000_check_phy_reset_block(hw); 4614 if (ret_val) 4615 return E1000_SUCCESS; 4616 4617 switch (hw->phy_type) { 4618 case e1000_phy_igp: 4619 case e1000_phy_igp_2: 4620 case e1000_phy_igp_3: 4621 case e1000_phy_ife: 4622 case e1000_phy_igb: 4623 ret_val = e1000_phy_hw_reset(hw); 4624 if (ret_val) 4625 return ret_val; 4626 break; 4627 default: 4628 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data); 4629 if (ret_val) 4630 return ret_val; 4631 4632 phy_data |= MII_CR_RESET; 4633 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data); 4634 if (ret_val) 4635 return ret_val; 4636 4637 udelay(1); 4638 break; 4639 } 4640 4641 if (hw->phy_type == e1000_phy_igp || hw->phy_type == e1000_phy_igp_2) 4642 e1000_phy_init_script(hw); 4643 4644 return E1000_SUCCESS; 4645 } 4646 4647 static int e1000_set_phy_type (struct e1000_hw *hw) 4648 { 4649 DEBUGFUNC (); 4650 4651 if (hw->mac_type == e1000_undefined) 4652 return -E1000_ERR_PHY_TYPE; 4653 4654 switch (hw->phy_id) { 4655 case M88E1000_E_PHY_ID: 4656 case M88E1000_I_PHY_ID: 4657 case M88E1011_I_PHY_ID: 4658 case M88E1111_I_PHY_ID: 4659 hw->phy_type = e1000_phy_m88; 4660 break; 4661 case IGP01E1000_I_PHY_ID: 4662 if (hw->mac_type == e1000_82541 || 4663 hw->mac_type == e1000_82541_rev_2 || 4664 hw->mac_type == e1000_82547 || 4665 hw->mac_type == e1000_82547_rev_2) { 4666 hw->phy_type = e1000_phy_igp; 4667 break; 4668 } 4669 case IGP03E1000_E_PHY_ID: 4670 hw->phy_type = e1000_phy_igp_3; 4671 break; 4672 case IFE_E_PHY_ID: 4673 case IFE_PLUS_E_PHY_ID: 4674 case IFE_C_E_PHY_ID: 4675 hw->phy_type = e1000_phy_ife; 4676 break; 4677 case GG82563_E_PHY_ID: 4678 if (hw->mac_type == e1000_80003es2lan) { 4679 hw->phy_type = e1000_phy_gg82563; 4680 break; 4681 } 4682 case BME1000_E_PHY_ID: 4683 hw->phy_type = e1000_phy_bm; 4684 break; 4685 case I210_I_PHY_ID: 4686 hw->phy_type = e1000_phy_igb; 4687 break; 4688 /* Fall Through */ 4689 default: 4690 /* Should never have loaded on this device */ 4691 hw->phy_type = e1000_phy_undefined; 4692 return -E1000_ERR_PHY_TYPE; 4693 } 4694 4695 return E1000_SUCCESS; 4696 } 4697 4698 /****************************************************************************** 4699 * Probes the expected PHY address for known PHY IDs 4700 * 4701 * hw - Struct containing variables accessed by shared code 4702 ******************************************************************************/ 4703 static int32_t 4704 e1000_detect_gig_phy(struct e1000_hw *hw) 4705 { 4706 int32_t phy_init_status, ret_val; 4707 uint16_t phy_id_high, phy_id_low; 4708 bool match = false; 4709 4710 DEBUGFUNC(); 4711 4712 /* The 82571 firmware may still be configuring the PHY. In this 4713 * case, we cannot access the PHY until the configuration is done. So 4714 * we explicitly set the PHY values. */ 4715 if (hw->mac_type == e1000_82571 || 4716 hw->mac_type == e1000_82572) { 4717 hw->phy_id = IGP01E1000_I_PHY_ID; 4718 hw->phy_type = e1000_phy_igp_2; 4719 return E1000_SUCCESS; 4720 } 4721 4722 /* ESB-2 PHY reads require e1000_phy_gg82563 to be set because of a 4723 * work- around that forces PHY page 0 to be set or the reads fail. 4724 * The rest of the code in this routine uses e1000_read_phy_reg to 4725 * read the PHY ID. So for ESB-2 we need to have this set so our 4726 * reads won't fail. If the attached PHY is not a e1000_phy_gg82563, 4727 * the routines below will figure this out as well. */ 4728 if (hw->mac_type == e1000_80003es2lan) 4729 hw->phy_type = e1000_phy_gg82563; 4730 4731 /* Read the PHY ID Registers to identify which PHY is onboard. */ 4732 ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high); 4733 if (ret_val) 4734 return ret_val; 4735 4736 hw->phy_id = (uint32_t) (phy_id_high << 16); 4737 udelay(20); 4738 ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low); 4739 if (ret_val) 4740 return ret_val; 4741 4742 hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK); 4743 hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK; 4744 4745 switch (hw->mac_type) { 4746 case e1000_82543: 4747 if (hw->phy_id == M88E1000_E_PHY_ID) 4748 match = true; 4749 break; 4750 case e1000_82544: 4751 if (hw->phy_id == M88E1000_I_PHY_ID) 4752 match = true; 4753 break; 4754 case e1000_82540: 4755 case e1000_82545: 4756 case e1000_82545_rev_3: 4757 case e1000_82546: 4758 case e1000_82546_rev_3: 4759 if (hw->phy_id == M88E1011_I_PHY_ID) 4760 match = true; 4761 break; 4762 case e1000_82541: 4763 case e1000_82541_rev_2: 4764 case e1000_82547: 4765 case e1000_82547_rev_2: 4766 if(hw->phy_id == IGP01E1000_I_PHY_ID) 4767 match = true; 4768 4769 break; 4770 case e1000_82573: 4771 if (hw->phy_id == M88E1111_I_PHY_ID) 4772 match = true; 4773 break; 4774 case e1000_82574: 4775 if (hw->phy_id == BME1000_E_PHY_ID) 4776 match = true; 4777 break; 4778 case e1000_80003es2lan: 4779 if (hw->phy_id == GG82563_E_PHY_ID) 4780 match = true; 4781 break; 4782 case e1000_ich8lan: 4783 if (hw->phy_id == IGP03E1000_E_PHY_ID) 4784 match = true; 4785 if (hw->phy_id == IFE_E_PHY_ID) 4786 match = true; 4787 if (hw->phy_id == IFE_PLUS_E_PHY_ID) 4788 match = true; 4789 if (hw->phy_id == IFE_C_E_PHY_ID) 4790 match = true; 4791 break; 4792 case e1000_igb: 4793 if (hw->phy_id == I210_I_PHY_ID) 4794 match = true; 4795 break; 4796 default: 4797 DEBUGOUT("Invalid MAC type %d\n", hw->mac_type); 4798 return -E1000_ERR_CONFIG; 4799 } 4800 4801 phy_init_status = e1000_set_phy_type(hw); 4802 4803 if ((match) && (phy_init_status == E1000_SUCCESS)) { 4804 DEBUGOUT("PHY ID 0x%X detected\n", hw->phy_id); 4805 return 0; 4806 } 4807 DEBUGOUT("Invalid PHY ID 0x%X\n", hw->phy_id); 4808 return -E1000_ERR_PHY; 4809 } 4810 4811 /***************************************************************************** 4812 * Set media type and TBI compatibility. 4813 * 4814 * hw - Struct containing variables accessed by shared code 4815 * **************************************************************************/ 4816 void 4817 e1000_set_media_type(struct e1000_hw *hw) 4818 { 4819 uint32_t status; 4820 4821 DEBUGFUNC(); 4822 4823 if (hw->mac_type != e1000_82543) { 4824 /* tbi_compatibility is only valid on 82543 */ 4825 hw->tbi_compatibility_en = false; 4826 } 4827 4828 switch (hw->device_id) { 4829 case E1000_DEV_ID_82545GM_SERDES: 4830 case E1000_DEV_ID_82546GB_SERDES: 4831 case E1000_DEV_ID_82571EB_SERDES: 4832 case E1000_DEV_ID_82571EB_SERDES_DUAL: 4833 case E1000_DEV_ID_82571EB_SERDES_QUAD: 4834 case E1000_DEV_ID_82572EI_SERDES: 4835 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT: 4836 hw->media_type = e1000_media_type_internal_serdes; 4837 break; 4838 default: 4839 switch (hw->mac_type) { 4840 case e1000_82542_rev2_0: 4841 case e1000_82542_rev2_1: 4842 hw->media_type = e1000_media_type_fiber; 4843 break; 4844 case e1000_ich8lan: 4845 case e1000_82573: 4846 case e1000_82574: 4847 case e1000_igb: 4848 /* The STATUS_TBIMODE bit is reserved or reused 4849 * for the this device. 4850 */ 4851 hw->media_type = e1000_media_type_copper; 4852 break; 4853 default: 4854 status = E1000_READ_REG(hw, STATUS); 4855 if (status & E1000_STATUS_TBIMODE) { 4856 hw->media_type = e1000_media_type_fiber; 4857 /* tbi_compatibility not valid on fiber */ 4858 hw->tbi_compatibility_en = false; 4859 } else { 4860 hw->media_type = e1000_media_type_copper; 4861 } 4862 break; 4863 } 4864 } 4865 } 4866 4867 /** 4868 * e1000_sw_init - Initialize general software structures (struct e1000_adapter) 4869 * 4870 * e1000_sw_init initializes the Adapter private data structure. 4871 * Fields are initialized based on PCI device information and 4872 * OS network device settings (MTU size). 4873 **/ 4874 4875 static int 4876 e1000_sw_init(struct eth_device *nic) 4877 { 4878 struct e1000_hw *hw = (typeof(hw)) nic->priv; 4879 int result; 4880 4881 /* PCI config space info */ 4882 pci_read_config_word(hw->pdev, PCI_VENDOR_ID, &hw->vendor_id); 4883 pci_read_config_word(hw->pdev, PCI_DEVICE_ID, &hw->device_id); 4884 pci_read_config_word(hw->pdev, PCI_SUBSYSTEM_VENDOR_ID, 4885 &hw->subsystem_vendor_id); 4886 pci_read_config_word(hw->pdev, PCI_SUBSYSTEM_ID, &hw->subsystem_id); 4887 4888 pci_read_config_byte(hw->pdev, PCI_REVISION_ID, &hw->revision_id); 4889 pci_read_config_word(hw->pdev, PCI_COMMAND, &hw->pci_cmd_word); 4890 4891 /* identify the MAC */ 4892 result = e1000_set_mac_type(hw); 4893 if (result) { 4894 E1000_ERR(hw->nic, "Unknown MAC Type\n"); 4895 return result; 4896 } 4897 4898 switch (hw->mac_type) { 4899 default: 4900 break; 4901 case e1000_82541: 4902 case e1000_82547: 4903 case e1000_82541_rev_2: 4904 case e1000_82547_rev_2: 4905 hw->phy_init_script = 1; 4906 break; 4907 } 4908 4909 /* flow control settings */ 4910 hw->fc_high_water = E1000_FC_HIGH_THRESH; 4911 hw->fc_low_water = E1000_FC_LOW_THRESH; 4912 hw->fc_pause_time = E1000_FC_PAUSE_TIME; 4913 hw->fc_send_xon = 1; 4914 4915 /* Media type - copper or fiber */ 4916 hw->tbi_compatibility_en = true; 4917 e1000_set_media_type(hw); 4918 4919 if (hw->mac_type >= e1000_82543) { 4920 uint32_t status = E1000_READ_REG(hw, STATUS); 4921 4922 if (status & E1000_STATUS_TBIMODE) { 4923 DEBUGOUT("fiber interface\n"); 4924 hw->media_type = e1000_media_type_fiber; 4925 } else { 4926 DEBUGOUT("copper interface\n"); 4927 hw->media_type = e1000_media_type_copper; 4928 } 4929 } else { 4930 hw->media_type = e1000_media_type_fiber; 4931 } 4932 4933 hw->wait_autoneg_complete = true; 4934 if (hw->mac_type < e1000_82543) 4935 hw->report_tx_early = 0; 4936 else 4937 hw->report_tx_early = 1; 4938 4939 return E1000_SUCCESS; 4940 } 4941 4942 void 4943 fill_rx(struct e1000_hw *hw) 4944 { 4945 struct e1000_rx_desc *rd; 4946 unsigned long flush_start, flush_end; 4947 4948 rx_last = rx_tail; 4949 rd = rx_base + rx_tail; 4950 rx_tail = (rx_tail + 1) % 8; 4951 memset(rd, 0, 16); 4952 rd->buffer_addr = cpu_to_le64((unsigned long)packet); 4953 4954 /* 4955 * Make sure there are no stale data in WB over this area, which 4956 * might get written into the memory while the e1000 also writes 4957 * into the same memory area. 4958 */ 4959 invalidate_dcache_range((unsigned long)packet, 4960 (unsigned long)packet + 4096); 4961 /* Dump the DMA descriptor into RAM. */ 4962 flush_start = ((unsigned long)rd) & ~(ARCH_DMA_MINALIGN - 1); 4963 flush_end = flush_start + roundup(sizeof(*rd), ARCH_DMA_MINALIGN); 4964 flush_dcache_range(flush_start, flush_end); 4965 4966 E1000_WRITE_REG(hw, RDT, rx_tail); 4967 } 4968 4969 /** 4970 * e1000_configure_tx - Configure 8254x Transmit Unit after Reset 4971 * @adapter: board private structure 4972 * 4973 * Configure the Tx unit of the MAC after a reset. 4974 **/ 4975 4976 static void 4977 e1000_configure_tx(struct e1000_hw *hw) 4978 { 4979 unsigned long tctl; 4980 unsigned long tipg, tarc; 4981 uint32_t ipgr1, ipgr2; 4982 4983 E1000_WRITE_REG(hw, TDBAL, (unsigned long)tx_base); 4984 E1000_WRITE_REG(hw, TDBAH, 0); 4985 4986 E1000_WRITE_REG(hw, TDLEN, 128); 4987 4988 /* Setup the HW Tx Head and Tail descriptor pointers */ 4989 E1000_WRITE_REG(hw, TDH, 0); 4990 E1000_WRITE_REG(hw, TDT, 0); 4991 tx_tail = 0; 4992 4993 /* Set the default values for the Tx Inter Packet Gap timer */ 4994 if (hw->mac_type <= e1000_82547_rev_2 && 4995 (hw->media_type == e1000_media_type_fiber || 4996 hw->media_type == e1000_media_type_internal_serdes)) 4997 tipg = DEFAULT_82543_TIPG_IPGT_FIBER; 4998 else 4999 tipg = DEFAULT_82543_TIPG_IPGT_COPPER; 5000 5001 /* Set the default values for the Tx Inter Packet Gap timer */ 5002 switch (hw->mac_type) { 5003 case e1000_82542_rev2_0: 5004 case e1000_82542_rev2_1: 5005 tipg = DEFAULT_82542_TIPG_IPGT; 5006 ipgr1 = DEFAULT_82542_TIPG_IPGR1; 5007 ipgr2 = DEFAULT_82542_TIPG_IPGR2; 5008 break; 5009 case e1000_80003es2lan: 5010 ipgr1 = DEFAULT_82543_TIPG_IPGR1; 5011 ipgr2 = DEFAULT_80003ES2LAN_TIPG_IPGR2; 5012 break; 5013 default: 5014 ipgr1 = DEFAULT_82543_TIPG_IPGR1; 5015 ipgr2 = DEFAULT_82543_TIPG_IPGR2; 5016 break; 5017 } 5018 tipg |= ipgr1 << E1000_TIPG_IPGR1_SHIFT; 5019 tipg |= ipgr2 << E1000_TIPG_IPGR2_SHIFT; 5020 E1000_WRITE_REG(hw, TIPG, tipg); 5021 /* Program the Transmit Control Register */ 5022 tctl = E1000_READ_REG(hw, TCTL); 5023 tctl &= ~E1000_TCTL_CT; 5024 tctl |= E1000_TCTL_EN | E1000_TCTL_PSP | 5025 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); 5026 5027 if (hw->mac_type == e1000_82571 || hw->mac_type == e1000_82572) { 5028 tarc = E1000_READ_REG(hw, TARC0); 5029 /* set the speed mode bit, we'll clear it if we're not at 5030 * gigabit link later */ 5031 /* git bit can be set to 1*/ 5032 } else if (hw->mac_type == e1000_80003es2lan) { 5033 tarc = E1000_READ_REG(hw, TARC0); 5034 tarc |= 1; 5035 E1000_WRITE_REG(hw, TARC0, tarc); 5036 tarc = E1000_READ_REG(hw, TARC1); 5037 tarc |= 1; 5038 E1000_WRITE_REG(hw, TARC1, tarc); 5039 } 5040 5041 5042 e1000_config_collision_dist(hw); 5043 /* Setup Transmit Descriptor Settings for eop descriptor */ 5044 hw->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS; 5045 5046 /* Need to set up RS bit */ 5047 if (hw->mac_type < e1000_82543) 5048 hw->txd_cmd |= E1000_TXD_CMD_RPS; 5049 else 5050 hw->txd_cmd |= E1000_TXD_CMD_RS; 5051 5052 5053 if (hw->mac_type == e1000_igb) { 5054 E1000_WRITE_REG(hw, TCTL_EXT, 0x42 << 10); 5055 5056 uint32_t reg_txdctl = E1000_READ_REG(hw, TXDCTL); 5057 reg_txdctl |= 1 << 25; 5058 E1000_WRITE_REG(hw, TXDCTL, reg_txdctl); 5059 mdelay(20); 5060 } 5061 5062 5063 5064 E1000_WRITE_REG(hw, TCTL, tctl); 5065 5066 5067 } 5068 5069 /** 5070 * e1000_setup_rctl - configure the receive control register 5071 * @adapter: Board private structure 5072 **/ 5073 static void 5074 e1000_setup_rctl(struct e1000_hw *hw) 5075 { 5076 uint32_t rctl; 5077 5078 rctl = E1000_READ_REG(hw, RCTL); 5079 5080 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 5081 5082 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO 5083 | E1000_RCTL_RDMTS_HALF; /* | 5084 (hw.mc_filter_type << E1000_RCTL_MO_SHIFT); */ 5085 5086 if (hw->tbi_compatibility_on == 1) 5087 rctl |= E1000_RCTL_SBP; 5088 else 5089 rctl &= ~E1000_RCTL_SBP; 5090 5091 rctl &= ~(E1000_RCTL_SZ_4096); 5092 rctl |= E1000_RCTL_SZ_2048; 5093 rctl &= ~(E1000_RCTL_BSEX | E1000_RCTL_LPE); 5094 E1000_WRITE_REG(hw, RCTL, rctl); 5095 } 5096 5097 /** 5098 * e1000_configure_rx - Configure 8254x Receive Unit after Reset 5099 * @adapter: board private structure 5100 * 5101 * Configure the Rx unit of the MAC after a reset. 5102 **/ 5103 static void 5104 e1000_configure_rx(struct e1000_hw *hw) 5105 { 5106 unsigned long rctl, ctrl_ext; 5107 rx_tail = 0; 5108 /* make sure receives are disabled while setting up the descriptors */ 5109 rctl = E1000_READ_REG(hw, RCTL); 5110 E1000_WRITE_REG(hw, RCTL, rctl & ~E1000_RCTL_EN); 5111 if (hw->mac_type >= e1000_82540) { 5112 /* Set the interrupt throttling rate. Value is calculated 5113 * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns) */ 5114 #define MAX_INTS_PER_SEC 8000 5115 #define DEFAULT_ITR 1000000000/(MAX_INTS_PER_SEC * 256) 5116 E1000_WRITE_REG(hw, ITR, DEFAULT_ITR); 5117 } 5118 5119 if (hw->mac_type >= e1000_82571) { 5120 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 5121 /* Reset delay timers after every interrupt */ 5122 ctrl_ext |= E1000_CTRL_EXT_INT_TIMER_CLR; 5123 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 5124 E1000_WRITE_FLUSH(hw); 5125 } 5126 /* Setup the Base and Length of the Rx Descriptor Ring */ 5127 E1000_WRITE_REG(hw, RDBAL, (unsigned long)rx_base); 5128 E1000_WRITE_REG(hw, RDBAH, 0); 5129 5130 E1000_WRITE_REG(hw, RDLEN, 128); 5131 5132 /* Setup the HW Rx Head and Tail Descriptor Pointers */ 5133 E1000_WRITE_REG(hw, RDH, 0); 5134 E1000_WRITE_REG(hw, RDT, 0); 5135 /* Enable Receives */ 5136 5137 if (hw->mac_type == e1000_igb) { 5138 5139 uint32_t reg_rxdctl = E1000_READ_REG(hw, RXDCTL); 5140 reg_rxdctl |= 1 << 25; 5141 E1000_WRITE_REG(hw, RXDCTL, reg_rxdctl); 5142 mdelay(20); 5143 } 5144 5145 E1000_WRITE_REG(hw, RCTL, rctl); 5146 5147 fill_rx(hw); 5148 } 5149 5150 /************************************************************************** 5151 POLL - Wait for a frame 5152 ***************************************************************************/ 5153 static int 5154 e1000_poll(struct eth_device *nic) 5155 { 5156 struct e1000_hw *hw = nic->priv; 5157 struct e1000_rx_desc *rd; 5158 unsigned long inval_start, inval_end; 5159 uint32_t len; 5160 5161 /* return true if there's an ethernet packet ready to read */ 5162 rd = rx_base + rx_last; 5163 5164 /* Re-load the descriptor from RAM. */ 5165 inval_start = ((unsigned long)rd) & ~(ARCH_DMA_MINALIGN - 1); 5166 inval_end = inval_start + roundup(sizeof(*rd), ARCH_DMA_MINALIGN); 5167 invalidate_dcache_range(inval_start, inval_end); 5168 5169 if (!(le32_to_cpu(rd->status)) & E1000_RXD_STAT_DD) 5170 return 0; 5171 /* DEBUGOUT("recv: packet len=%d\n", rd->length); */ 5172 /* Packet received, make sure the data are re-loaded from RAM. */ 5173 len = le32_to_cpu(rd->length); 5174 invalidate_dcache_range((unsigned long)packet, 5175 (unsigned long)packet + 5176 roundup(len, ARCH_DMA_MINALIGN)); 5177 net_process_received_packet((uchar *)packet, len); 5178 fill_rx(hw); 5179 return 1; 5180 } 5181 5182 /************************************************************************** 5183 TRANSMIT - Transmit a frame 5184 ***************************************************************************/ 5185 static int e1000_transmit(struct eth_device *nic, void *txpacket, int length) 5186 { 5187 void *nv_packet = (void *)txpacket; 5188 struct e1000_hw *hw = nic->priv; 5189 struct e1000_tx_desc *txp; 5190 int i = 0; 5191 unsigned long flush_start, flush_end; 5192 5193 txp = tx_base + tx_tail; 5194 tx_tail = (tx_tail + 1) % 8; 5195 5196 txp->buffer_addr = cpu_to_le64(virt_to_bus(hw->pdev, nv_packet)); 5197 txp->lower.data = cpu_to_le32(hw->txd_cmd | length); 5198 txp->upper.data = 0; 5199 5200 /* Dump the packet into RAM so e1000 can pick them. */ 5201 flush_dcache_range((unsigned long)nv_packet, 5202 (unsigned long)nv_packet + 5203 roundup(length, ARCH_DMA_MINALIGN)); 5204 /* Dump the descriptor into RAM as well. */ 5205 flush_start = ((unsigned long)txp) & ~(ARCH_DMA_MINALIGN - 1); 5206 flush_end = flush_start + roundup(sizeof(*txp), ARCH_DMA_MINALIGN); 5207 flush_dcache_range(flush_start, flush_end); 5208 5209 E1000_WRITE_REG(hw, TDT, tx_tail); 5210 5211 E1000_WRITE_FLUSH(hw); 5212 while (1) { 5213 invalidate_dcache_range(flush_start, flush_end); 5214 if (le32_to_cpu(txp->upper.data) & E1000_TXD_STAT_DD) 5215 break; 5216 if (i++ > TOUT_LOOP) { 5217 DEBUGOUT("e1000: tx timeout\n"); 5218 return 0; 5219 } 5220 udelay(10); /* give the nic a chance to write to the register */ 5221 } 5222 return 1; 5223 } 5224 5225 /*reset function*/ 5226 static inline int 5227 e1000_reset(struct eth_device *nic) 5228 { 5229 struct e1000_hw *hw = nic->priv; 5230 5231 e1000_reset_hw(hw); 5232 if (hw->mac_type >= e1000_82544) { 5233 E1000_WRITE_REG(hw, WUC, 0); 5234 } 5235 return e1000_init_hw(nic); 5236 } 5237 5238 /************************************************************************** 5239 DISABLE - Turn off ethernet interface 5240 ***************************************************************************/ 5241 static void 5242 e1000_disable(struct eth_device *nic) 5243 { 5244 struct e1000_hw *hw = nic->priv; 5245 5246 /* Turn off the ethernet interface */ 5247 E1000_WRITE_REG(hw, RCTL, 0); 5248 E1000_WRITE_REG(hw, TCTL, 0); 5249 5250 /* Clear the transmit ring */ 5251 E1000_WRITE_REG(hw, TDH, 0); 5252 E1000_WRITE_REG(hw, TDT, 0); 5253 5254 /* Clear the receive ring */ 5255 E1000_WRITE_REG(hw, RDH, 0); 5256 E1000_WRITE_REG(hw, RDT, 0); 5257 5258 /* put the card in its initial state */ 5259 #if 0 5260 E1000_WRITE_REG(hw, CTRL, E1000_CTRL_RST); 5261 #endif 5262 mdelay(10); 5263 5264 } 5265 5266 /************************************************************************** 5267 INIT - set up ethernet interface(s) 5268 ***************************************************************************/ 5269 static int 5270 e1000_init(struct eth_device *nic, bd_t * bis) 5271 { 5272 struct e1000_hw *hw = nic->priv; 5273 int ret_val = 0; 5274 5275 ret_val = e1000_reset(nic); 5276 if (ret_val < 0) { 5277 if ((ret_val == -E1000_ERR_NOLINK) || 5278 (ret_val == -E1000_ERR_TIMEOUT)) { 5279 E1000_ERR(hw->nic, "Valid Link not detected\n"); 5280 } else { 5281 E1000_ERR(hw->nic, "Hardware Initialization Failed\n"); 5282 } 5283 return 0; 5284 } 5285 e1000_configure_tx(hw); 5286 e1000_setup_rctl(hw); 5287 e1000_configure_rx(hw); 5288 return 1; 5289 } 5290 5291 /****************************************************************************** 5292 * Gets the current PCI bus type of hardware 5293 * 5294 * hw - Struct containing variables accessed by shared code 5295 *****************************************************************************/ 5296 void e1000_get_bus_type(struct e1000_hw *hw) 5297 { 5298 uint32_t status; 5299 5300 switch (hw->mac_type) { 5301 case e1000_82542_rev2_0: 5302 case e1000_82542_rev2_1: 5303 hw->bus_type = e1000_bus_type_pci; 5304 break; 5305 case e1000_82571: 5306 case e1000_82572: 5307 case e1000_82573: 5308 case e1000_82574: 5309 case e1000_80003es2lan: 5310 case e1000_ich8lan: 5311 case e1000_igb: 5312 hw->bus_type = e1000_bus_type_pci_express; 5313 break; 5314 default: 5315 status = E1000_READ_REG(hw, STATUS); 5316 hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ? 5317 e1000_bus_type_pcix : e1000_bus_type_pci; 5318 break; 5319 } 5320 } 5321 5322 /* A list of all registered e1000 devices */ 5323 static LIST_HEAD(e1000_hw_list); 5324 5325 /************************************************************************** 5326 PROBE - Look for an adapter, this routine's visible to the outside 5327 You should omit the last argument struct pci_device * for a non-PCI NIC 5328 ***************************************************************************/ 5329 int 5330 e1000_initialize(bd_t * bis) 5331 { 5332 unsigned int i; 5333 pci_dev_t devno; 5334 5335 DEBUGFUNC(); 5336 5337 /* Find and probe all the matching PCI devices */ 5338 for (i = 0; (devno = pci_find_devices(e1000_supported, i)) >= 0; i++) { 5339 u32 val; 5340 5341 /* 5342 * These will never get freed due to errors, this allows us to 5343 * perform SPI EEPROM programming from U-boot, for example. 5344 */ 5345 struct eth_device *nic = malloc(sizeof(*nic)); 5346 struct e1000_hw *hw = malloc(sizeof(*hw)); 5347 if (!nic || !hw) { 5348 printf("e1000#%u: Out of Memory!\n", i); 5349 free(nic); 5350 free(hw); 5351 continue; 5352 } 5353 5354 /* Make sure all of the fields are initially zeroed */ 5355 memset(nic, 0, sizeof(*nic)); 5356 memset(hw, 0, sizeof(*hw)); 5357 5358 /* Assign the passed-in values */ 5359 hw->cardnum = i; 5360 hw->pdev = devno; 5361 hw->nic = nic; 5362 nic->priv = hw; 5363 5364 /* Generate a card name */ 5365 sprintf(nic->name, "e1000#%u", hw->cardnum); 5366 5367 /* Print a debug message with the IO base address */ 5368 pci_read_config_dword(devno, PCI_BASE_ADDRESS_0, &val); 5369 E1000_DBG(nic, "iobase 0x%08x\n", val & 0xfffffff0); 5370 5371 /* Try to enable I/O accesses and bus-mastering */ 5372 val = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; 5373 pci_write_config_dword(devno, PCI_COMMAND, val); 5374 5375 /* Make sure it worked */ 5376 pci_read_config_dword(devno, PCI_COMMAND, &val); 5377 if (!(val & PCI_COMMAND_MEMORY)) { 5378 E1000_ERR(nic, "Can't enable I/O memory\n"); 5379 continue; 5380 } 5381 if (!(val & PCI_COMMAND_MASTER)) { 5382 E1000_ERR(nic, "Can't enable bus-mastering\n"); 5383 continue; 5384 } 5385 5386 /* Are these variables needed? */ 5387 hw->fc = e1000_fc_default; 5388 hw->original_fc = e1000_fc_default; 5389 hw->autoneg_failed = 0; 5390 hw->autoneg = 1; 5391 hw->get_link_status = true; 5392 #ifndef CONFIG_E1000_NO_NVM 5393 hw->eeprom_semaphore_present = true; 5394 #endif 5395 hw->hw_addr = pci_map_bar(devno, PCI_BASE_ADDRESS_0, 5396 PCI_REGION_MEM); 5397 hw->mac_type = e1000_undefined; 5398 5399 /* MAC and Phy settings */ 5400 if (e1000_sw_init(nic) < 0) { 5401 E1000_ERR(nic, "Software init failed\n"); 5402 continue; 5403 } 5404 if (e1000_check_phy_reset_block(hw)) 5405 E1000_ERR(nic, "PHY Reset is blocked!\n"); 5406 5407 /* Basic init was OK, reset the hardware and allow SPI access */ 5408 e1000_reset_hw(hw); 5409 list_add_tail(&hw->list_node, &e1000_hw_list); 5410 5411 #ifndef CONFIG_E1000_NO_NVM 5412 /* Validate the EEPROM and get chipset information */ 5413 #if !defined(CONFIG_MVBC_1G) 5414 if (e1000_init_eeprom_params(hw)) { 5415 E1000_ERR(nic, "EEPROM is invalid!\n"); 5416 continue; 5417 } 5418 if ((E1000_READ_REG(hw, I210_EECD) & E1000_EECD_FLUPD) && 5419 e1000_validate_eeprom_checksum(hw)) 5420 continue; 5421 #endif 5422 e1000_read_mac_addr(nic); 5423 #endif 5424 e1000_get_bus_type(hw); 5425 5426 #ifndef CONFIG_E1000_NO_NVM 5427 printf("e1000: %02x:%02x:%02x:%02x:%02x:%02x\n ", 5428 nic->enetaddr[0], nic->enetaddr[1], nic->enetaddr[2], 5429 nic->enetaddr[3], nic->enetaddr[4], nic->enetaddr[5]); 5430 #else 5431 memset(nic->enetaddr, 0, 6); 5432 printf("e1000: no NVM\n"); 5433 #endif 5434 5435 /* Set up the function pointers and register the device */ 5436 nic->init = e1000_init; 5437 nic->recv = e1000_poll; 5438 nic->send = e1000_transmit; 5439 nic->halt = e1000_disable; 5440 eth_register(nic); 5441 } 5442 5443 return i; 5444 } 5445 5446 struct e1000_hw *e1000_find_card(unsigned int cardnum) 5447 { 5448 struct e1000_hw *hw; 5449 5450 list_for_each_entry(hw, &e1000_hw_list, list_node) 5451 if (hw->cardnum == cardnum) 5452 return hw; 5453 5454 return NULL; 5455 } 5456 5457 #ifdef CONFIG_CMD_E1000 5458 static int do_e1000(cmd_tbl_t *cmdtp, int flag, 5459 int argc, char * const argv[]) 5460 { 5461 struct e1000_hw *hw; 5462 5463 if (argc < 3) { 5464 cmd_usage(cmdtp); 5465 return 1; 5466 } 5467 5468 /* Make sure we can find the requested e1000 card */ 5469 hw = e1000_find_card(simple_strtoul(argv[1], NULL, 10)); 5470 if (!hw) { 5471 printf("e1000: ERROR: No such device: e1000#%s\n", argv[1]); 5472 return 1; 5473 } 5474 5475 if (!strcmp(argv[2], "print-mac-address")) { 5476 unsigned char *mac = hw->nic->enetaddr; 5477 printf("%02x:%02x:%02x:%02x:%02x:%02x\n", 5478 mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]); 5479 return 0; 5480 } 5481 5482 #ifdef CONFIG_E1000_SPI 5483 /* Handle the "SPI" subcommand */ 5484 if (!strcmp(argv[2], "spi")) 5485 return do_e1000_spi(cmdtp, hw, argc - 3, argv + 3); 5486 #endif 5487 5488 cmd_usage(cmdtp); 5489 return 1; 5490 } 5491 5492 U_BOOT_CMD( 5493 e1000, 7, 0, do_e1000, 5494 "Intel e1000 controller management", 5495 /* */"<card#> print-mac-address\n" 5496 #ifdef CONFIG_E1000_SPI 5497 "e1000 <card#> spi show [<offset> [<length>]]\n" 5498 "e1000 <card#> spi dump <addr> <offset> <length>\n" 5499 "e1000 <card#> spi program <addr> <offset> <length>\n" 5500 "e1000 <card#> spi checksum [update]\n" 5501 #endif 5502 " - Manage the Intel E1000 PCI device" 5503 ); 5504 #endif /* not CONFIG_CMD_E1000 */ 5505