12439e4bfSJean-Christophe PLAGNIOL-VILLARD /************************************************************************** 2ac3315c2SAndre Schwarz Intel Pro 1000 for ppcboot/das-u-boot 32439e4bfSJean-Christophe PLAGNIOL-VILLARD Drivers are port from Intel's Linux driver e1000-4.3.15 42439e4bfSJean-Christophe PLAGNIOL-VILLARD and from Etherboot pro 1000 driver by mrakes at vivato dot net 52439e4bfSJean-Christophe PLAGNIOL-VILLARD tested on both gig copper and gig fiber boards 62439e4bfSJean-Christophe PLAGNIOL-VILLARD ***************************************************************************/ 72439e4bfSJean-Christophe PLAGNIOL-VILLARD /******************************************************************************* 82439e4bfSJean-Christophe PLAGNIOL-VILLARD 92439e4bfSJean-Christophe PLAGNIOL-VILLARD 102439e4bfSJean-Christophe PLAGNIOL-VILLARD Copyright(c) 1999 - 2002 Intel Corporation. All rights reserved. 112439e4bfSJean-Christophe PLAGNIOL-VILLARD 121a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 132439e4bfSJean-Christophe PLAGNIOL-VILLARD 142439e4bfSJean-Christophe PLAGNIOL-VILLARD Contact Information: 152439e4bfSJean-Christophe PLAGNIOL-VILLARD Linux NICS <linux.nics@intel.com> 162439e4bfSJean-Christophe PLAGNIOL-VILLARD Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 172439e4bfSJean-Christophe PLAGNIOL-VILLARD 182439e4bfSJean-Christophe PLAGNIOL-VILLARD *******************************************************************************/ 192439e4bfSJean-Christophe PLAGNIOL-VILLARD /* 202439e4bfSJean-Christophe PLAGNIOL-VILLARD * Copyright (C) Archway Digital Solutions. 212439e4bfSJean-Christophe PLAGNIOL-VILLARD * 222439e4bfSJean-Christophe PLAGNIOL-VILLARD * written by Chrsitopher Li <cli at arcyway dot com> or <chrisl at gnuchina dot org> 232439e4bfSJean-Christophe PLAGNIOL-VILLARD * 2/9/2002 242439e4bfSJean-Christophe PLAGNIOL-VILLARD * 252439e4bfSJean-Christophe PLAGNIOL-VILLARD * Copyright (C) Linux Networx. 262439e4bfSJean-Christophe PLAGNIOL-VILLARD * Massive upgrade to work with the new intel gigabit NICs. 272439e4bfSJean-Christophe PLAGNIOL-VILLARD * <ebiederman at lnxi dot com> 282c2668f9SRoy Zang * 292c2668f9SRoy Zang * Copyright 2011 Freescale Semiconductor, Inc. 302439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 312439e4bfSJean-Christophe PLAGNIOL-VILLARD 32c752cd2aSSimon Glass #include <common.h> 33c6d80a15SSimon Glass #include <dm.h> 345c5e707aSSimon Glass #include <errno.h> 35cf92e05cSSimon Glass #include <memalign.h> 365c5e707aSSimon Glass #include <pci.h> 372439e4bfSJean-Christophe PLAGNIOL-VILLARD #include "e1000.h" 382439e4bfSJean-Christophe PLAGNIOL-VILLARD 392439e4bfSJean-Christophe PLAGNIOL-VILLARD #define TOUT_LOOP 100000 402439e4bfSJean-Christophe PLAGNIOL-VILLARD 41f81ecb5dSTimur Tabi #define virt_to_bus(devno, v) pci_virt_to_mem(devno, (void *) (v)) 422439e4bfSJean-Christophe PLAGNIOL-VILLARD #define bus_to_phys(devno, a) pci_mem_to_phys(devno, a) 432439e4bfSJean-Christophe PLAGNIOL-VILLARD 449ea005fbSRoy Zang #define E1000_DEFAULT_PCI_PBA 0x00000030 459ea005fbSRoy Zang #define E1000_DEFAULT_PCIE_PBA 0x000a0026 462439e4bfSJean-Christophe PLAGNIOL-VILLARD 472439e4bfSJean-Christophe PLAGNIOL-VILLARD /* NIC specific static variables go here */ 482439e4bfSJean-Christophe PLAGNIOL-VILLARD 49873e8e01SMarek Vasut /* Intel i210 needs the DMA descriptor rings aligned to 128b */ 50873e8e01SMarek Vasut #define E1000_BUFFER_ALIGN 128 512439e4bfSJean-Christophe PLAGNIOL-VILLARD 52c6d80a15SSimon Glass /* 53c6d80a15SSimon Glass * TODO(sjg@chromium.org): Even with driver model we share these buffers. 54c6d80a15SSimon Glass * Concurrent receiving on multiple active Ethernet devices will not work. 55c6d80a15SSimon Glass * Normally U-Boot does not support this anyway. To fix it in this driver, 56c6d80a15SSimon Glass * move these buffers and the tx/rx pointers to struct e1000_hw. 57c6d80a15SSimon Glass */ 58873e8e01SMarek Vasut DEFINE_ALIGN_BUFFER(struct e1000_tx_desc, tx_base, 16, E1000_BUFFER_ALIGN); 59873e8e01SMarek Vasut DEFINE_ALIGN_BUFFER(struct e1000_rx_desc, rx_base, 16, E1000_BUFFER_ALIGN); 60873e8e01SMarek Vasut DEFINE_ALIGN_BUFFER(unsigned char, packet, 4096, E1000_BUFFER_ALIGN); 612439e4bfSJean-Christophe PLAGNIOL-VILLARD 622439e4bfSJean-Christophe PLAGNIOL-VILLARD static int tx_tail; 632439e4bfSJean-Christophe PLAGNIOL-VILLARD static int rx_tail, rx_last; 64c6d80a15SSimon Glass #ifdef CONFIG_DM_ETH 65c6d80a15SSimon Glass static int num_cards; /* Number of E1000 devices seen so far */ 66c6d80a15SSimon Glass #endif 672439e4bfSJean-Christophe PLAGNIOL-VILLARD 68d60626f8SKyle Moffett static struct pci_device_id e1000_supported[] = { 695c5e707aSSimon Glass { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82542) }, 705c5e707aSSimon Glass { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82543GC_FIBER) }, 715c5e707aSSimon Glass { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82543GC_COPPER) }, 725c5e707aSSimon Glass { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544EI_COPPER) }, 735c5e707aSSimon Glass { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544EI_FIBER) }, 745c5e707aSSimon Glass { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544GC_COPPER) }, 755c5e707aSSimon Glass { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544GC_LOM) }, 765c5e707aSSimon Glass { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82540EM) }, 775c5e707aSSimon Glass { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545EM_COPPER) }, 785c5e707aSSimon Glass { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545GM_COPPER) }, 795c5e707aSSimon Glass { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_COPPER) }, 805c5e707aSSimon Glass { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545EM_FIBER) }, 815c5e707aSSimon Glass { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_FIBER) }, 825c5e707aSSimon Glass { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546GB_COPPER) }, 835c5e707aSSimon Glass { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82540EM_LOM) }, 845c5e707aSSimon Glass { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82541ER) }, 855c5e707aSSimon Glass { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82541GI_LF) }, 86aa070789SRoy Zang /* E1000 PCIe card */ 875c5e707aSSimon Glass { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_COPPER) }, 885c5e707aSSimon Glass { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_FIBER) }, 895c5e707aSSimon Glass { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES) }, 905c5e707aSSimon Glass { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_COPPER) }, 915c5e707aSSimon Glass { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571PT_QUAD_COPPER) }, 925c5e707aSSimon Glass { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_FIBER) }, 935c5e707aSSimon Glass { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_COPPER_LOWPROFILE) }, 945c5e707aSSimon Glass { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES_DUAL) }, 955c5e707aSSimon Glass { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES_QUAD) }, 965c5e707aSSimon Glass { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_COPPER) }, 975c5e707aSSimon Glass { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_FIBER) }, 985c5e707aSSimon Glass { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_SERDES) }, 995c5e707aSSimon Glass { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI) }, 1005c5e707aSSimon Glass { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573E) }, 1015c5e707aSSimon Glass { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573E_IAMT) }, 1025c5e707aSSimon Glass { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573L) }, 1035c5e707aSSimon Glass { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82574L) }, 1045c5e707aSSimon Glass { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546GB_QUAD_COPPER_KSP3) }, 1055c5e707aSSimon Glass { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_COPPER_DPT) }, 1065c5e707aSSimon Glass { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_SERDES_DPT) }, 1075c5e707aSSimon Glass { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_COPPER_SPT) }, 1085c5e707aSSimon Glass { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_SERDES_SPT) }, 1095c5e707aSSimon Glass { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_UNPROGRAMMED) }, 1105c5e707aSSimon Glass { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I211_UNPROGRAMMED) }, 1115c5e707aSSimon Glass { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_COPPER) }, 1125c5e707aSSimon Glass { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I211_COPPER) }, 1135c5e707aSSimon Glass { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_COPPER_FLASHLESS) }, 1145c5e707aSSimon Glass { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_SERDES) }, 1155c5e707aSSimon Glass { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_SERDES_FLASHLESS) }, 1165c5e707aSSimon Glass { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_1000BASEKX) }, 11795186063SMarek Vasut 1181bc43437SStefan Althoefer {} 1192439e4bfSJean-Christophe PLAGNIOL-VILLARD }; 1202439e4bfSJean-Christophe PLAGNIOL-VILLARD 1212439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Function forward declarations */ 1225c5e707aSSimon Glass static int e1000_setup_link(struct e1000_hw *hw); 1235c5e707aSSimon Glass static int e1000_setup_fiber_link(struct e1000_hw *hw); 1245c5e707aSSimon Glass static int e1000_setup_copper_link(struct e1000_hw *hw); 1252439e4bfSJean-Christophe PLAGNIOL-VILLARD static int e1000_phy_setup_autoneg(struct e1000_hw *hw); 1262439e4bfSJean-Christophe PLAGNIOL-VILLARD static void e1000_config_collision_dist(struct e1000_hw *hw); 1272439e4bfSJean-Christophe PLAGNIOL-VILLARD static int e1000_config_mac_to_phy(struct e1000_hw *hw); 1282439e4bfSJean-Christophe PLAGNIOL-VILLARD static int e1000_config_fc_after_link_up(struct e1000_hw *hw); 1295c5e707aSSimon Glass static int e1000_check_for_link(struct e1000_hw *hw); 1302439e4bfSJean-Christophe PLAGNIOL-VILLARD static int e1000_wait_autoneg(struct e1000_hw *hw); 131aa070789SRoy Zang static int e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t * speed, 1322439e4bfSJean-Christophe PLAGNIOL-VILLARD uint16_t * duplex); 1332439e4bfSJean-Christophe PLAGNIOL-VILLARD static int e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, 1342439e4bfSJean-Christophe PLAGNIOL-VILLARD uint16_t * phy_data); 1352439e4bfSJean-Christophe PLAGNIOL-VILLARD static int e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, 1362439e4bfSJean-Christophe PLAGNIOL-VILLARD uint16_t phy_data); 137aa070789SRoy Zang static int32_t e1000_phy_hw_reset(struct e1000_hw *hw); 1382439e4bfSJean-Christophe PLAGNIOL-VILLARD static int e1000_phy_reset(struct e1000_hw *hw); 1392439e4bfSJean-Christophe PLAGNIOL-VILLARD static int e1000_detect_gig_phy(struct e1000_hw *hw); 140aa070789SRoy Zang static void e1000_set_media_type(struct e1000_hw *hw); 1412439e4bfSJean-Christophe PLAGNIOL-VILLARD 142aa070789SRoy Zang static int32_t e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask); 1437e2d991dSTim Harvey static void e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask); 144aa070789SRoy Zang static int32_t e1000_check_phy_reset_block(struct e1000_hw *hw); 1452439e4bfSJean-Christophe PLAGNIOL-VILLARD 1468712adfdSRojhalat Ibrahim #ifndef CONFIG_E1000_NO_NVM 1478712adfdSRojhalat Ibrahim static void e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw); 148ecbd2078SRoy Zang static int32_t e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset, 149ecbd2078SRoy Zang uint16_t words, 150ecbd2078SRoy Zang uint16_t *data); 1512439e4bfSJean-Christophe PLAGNIOL-VILLARD /****************************************************************************** 1522439e4bfSJean-Christophe PLAGNIOL-VILLARD * Raises the EEPROM's clock input. 1532439e4bfSJean-Christophe PLAGNIOL-VILLARD * 1542439e4bfSJean-Christophe PLAGNIOL-VILLARD * hw - Struct containing variables accessed by shared code 1552439e4bfSJean-Christophe PLAGNIOL-VILLARD * eecd - EECD's current value 1562439e4bfSJean-Christophe PLAGNIOL-VILLARD *****************************************************************************/ 1572326a94dSKyle Moffett void e1000_raise_ee_clk(struct e1000_hw *hw, uint32_t * eecd) 1582439e4bfSJean-Christophe PLAGNIOL-VILLARD { 1592439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Raise the clock input to the EEPROM (by setting the SK bit), and then 1602439e4bfSJean-Christophe PLAGNIOL-VILLARD * wait 50 microseconds. 1612439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 1622439e4bfSJean-Christophe PLAGNIOL-VILLARD *eecd = *eecd | E1000_EECD_SK; 1632439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, EECD, *eecd); 1642439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_FLUSH(hw); 1652439e4bfSJean-Christophe PLAGNIOL-VILLARD udelay(50); 1662439e4bfSJean-Christophe PLAGNIOL-VILLARD } 1672439e4bfSJean-Christophe PLAGNIOL-VILLARD 1682439e4bfSJean-Christophe PLAGNIOL-VILLARD /****************************************************************************** 1692439e4bfSJean-Christophe PLAGNIOL-VILLARD * Lowers the EEPROM's clock input. 1702439e4bfSJean-Christophe PLAGNIOL-VILLARD * 1712439e4bfSJean-Christophe PLAGNIOL-VILLARD * hw - Struct containing variables accessed by shared code 1722439e4bfSJean-Christophe PLAGNIOL-VILLARD * eecd - EECD's current value 1732439e4bfSJean-Christophe PLAGNIOL-VILLARD *****************************************************************************/ 1742326a94dSKyle Moffett void e1000_lower_ee_clk(struct e1000_hw *hw, uint32_t * eecd) 1752439e4bfSJean-Christophe PLAGNIOL-VILLARD { 1762439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Lower the clock input to the EEPROM (by clearing the SK bit), and then 1772439e4bfSJean-Christophe PLAGNIOL-VILLARD * wait 50 microseconds. 1782439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 1792439e4bfSJean-Christophe PLAGNIOL-VILLARD *eecd = *eecd & ~E1000_EECD_SK; 1802439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, EECD, *eecd); 1812439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_FLUSH(hw); 1822439e4bfSJean-Christophe PLAGNIOL-VILLARD udelay(50); 1832439e4bfSJean-Christophe PLAGNIOL-VILLARD } 1842439e4bfSJean-Christophe PLAGNIOL-VILLARD 1852439e4bfSJean-Christophe PLAGNIOL-VILLARD /****************************************************************************** 1862439e4bfSJean-Christophe PLAGNIOL-VILLARD * Shift data bits out to the EEPROM. 1872439e4bfSJean-Christophe PLAGNIOL-VILLARD * 1882439e4bfSJean-Christophe PLAGNIOL-VILLARD * hw - Struct containing variables accessed by shared code 1892439e4bfSJean-Christophe PLAGNIOL-VILLARD * data - data to send to the EEPROM 1902439e4bfSJean-Christophe PLAGNIOL-VILLARD * count - number of bits to shift out 1912439e4bfSJean-Christophe PLAGNIOL-VILLARD *****************************************************************************/ 1922439e4bfSJean-Christophe PLAGNIOL-VILLARD static void 1932439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_shift_out_ee_bits(struct e1000_hw *hw, uint16_t data, uint16_t count) 1942439e4bfSJean-Christophe PLAGNIOL-VILLARD { 1952439e4bfSJean-Christophe PLAGNIOL-VILLARD uint32_t eecd; 1962439e4bfSJean-Christophe PLAGNIOL-VILLARD uint32_t mask; 1972439e4bfSJean-Christophe PLAGNIOL-VILLARD 1982439e4bfSJean-Christophe PLAGNIOL-VILLARD /* We need to shift "count" bits out to the EEPROM. So, value in the 1992439e4bfSJean-Christophe PLAGNIOL-VILLARD * "data" parameter will be shifted out to the EEPROM one bit at a time. 2002439e4bfSJean-Christophe PLAGNIOL-VILLARD * In order to do this, "data" must be broken down into bits. 2012439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 2022439e4bfSJean-Christophe PLAGNIOL-VILLARD mask = 0x01 << (count - 1); 2032439e4bfSJean-Christophe PLAGNIOL-VILLARD eecd = E1000_READ_REG(hw, EECD); 2042439e4bfSJean-Christophe PLAGNIOL-VILLARD eecd &= ~(E1000_EECD_DO | E1000_EECD_DI); 2052439e4bfSJean-Christophe PLAGNIOL-VILLARD do { 2062439e4bfSJean-Christophe PLAGNIOL-VILLARD /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1", 2072439e4bfSJean-Christophe PLAGNIOL-VILLARD * and then raising and then lowering the clock (the SK bit controls 2082439e4bfSJean-Christophe PLAGNIOL-VILLARD * the clock input to the EEPROM). A "0" is shifted out to the EEPROM 2092439e4bfSJean-Christophe PLAGNIOL-VILLARD * by setting "DI" to "0" and then raising and then lowering the clock. 2102439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 2112439e4bfSJean-Christophe PLAGNIOL-VILLARD eecd &= ~E1000_EECD_DI; 2122439e4bfSJean-Christophe PLAGNIOL-VILLARD 2132439e4bfSJean-Christophe PLAGNIOL-VILLARD if (data & mask) 2142439e4bfSJean-Christophe PLAGNIOL-VILLARD eecd |= E1000_EECD_DI; 2152439e4bfSJean-Christophe PLAGNIOL-VILLARD 2162439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, EECD, eecd); 2172439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_FLUSH(hw); 2182439e4bfSJean-Christophe PLAGNIOL-VILLARD 2192439e4bfSJean-Christophe PLAGNIOL-VILLARD udelay(50); 2202439e4bfSJean-Christophe PLAGNIOL-VILLARD 2212439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_raise_ee_clk(hw, &eecd); 2222439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_lower_ee_clk(hw, &eecd); 2232439e4bfSJean-Christophe PLAGNIOL-VILLARD 2242439e4bfSJean-Christophe PLAGNIOL-VILLARD mask = mask >> 1; 2252439e4bfSJean-Christophe PLAGNIOL-VILLARD 2262439e4bfSJean-Christophe PLAGNIOL-VILLARD } while (mask); 2272439e4bfSJean-Christophe PLAGNIOL-VILLARD 2282439e4bfSJean-Christophe PLAGNIOL-VILLARD /* We leave the "DI" bit set to "0" when we leave this routine. */ 2292439e4bfSJean-Christophe PLAGNIOL-VILLARD eecd &= ~E1000_EECD_DI; 2302439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, EECD, eecd); 2312439e4bfSJean-Christophe PLAGNIOL-VILLARD } 2322439e4bfSJean-Christophe PLAGNIOL-VILLARD 2332439e4bfSJean-Christophe PLAGNIOL-VILLARD /****************************************************************************** 2342439e4bfSJean-Christophe PLAGNIOL-VILLARD * Shift data bits in from the EEPROM 2352439e4bfSJean-Christophe PLAGNIOL-VILLARD * 2362439e4bfSJean-Christophe PLAGNIOL-VILLARD * hw - Struct containing variables accessed by shared code 2372439e4bfSJean-Christophe PLAGNIOL-VILLARD *****************************************************************************/ 2382439e4bfSJean-Christophe PLAGNIOL-VILLARD static uint16_t 239aa070789SRoy Zang e1000_shift_in_ee_bits(struct e1000_hw *hw, uint16_t count) 2402439e4bfSJean-Christophe PLAGNIOL-VILLARD { 2412439e4bfSJean-Christophe PLAGNIOL-VILLARD uint32_t eecd; 2422439e4bfSJean-Christophe PLAGNIOL-VILLARD uint32_t i; 2432439e4bfSJean-Christophe PLAGNIOL-VILLARD uint16_t data; 2442439e4bfSJean-Christophe PLAGNIOL-VILLARD 245aa070789SRoy Zang /* In order to read a register from the EEPROM, we need to shift 'count' 246aa070789SRoy Zang * bits in from the EEPROM. Bits are "shifted in" by raising the clock 247aa070789SRoy Zang * input to the EEPROM (setting the SK bit), and then reading the 248aa070789SRoy Zang * value of the "DO" bit. During this "shifting in" process the 249aa070789SRoy Zang * "DI" bit should always be clear. 2502439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 2512439e4bfSJean-Christophe PLAGNIOL-VILLARD 2522439e4bfSJean-Christophe PLAGNIOL-VILLARD eecd = E1000_READ_REG(hw, EECD); 2532439e4bfSJean-Christophe PLAGNIOL-VILLARD 2542439e4bfSJean-Christophe PLAGNIOL-VILLARD eecd &= ~(E1000_EECD_DO | E1000_EECD_DI); 2552439e4bfSJean-Christophe PLAGNIOL-VILLARD data = 0; 2562439e4bfSJean-Christophe PLAGNIOL-VILLARD 257aa070789SRoy Zang for (i = 0; i < count; i++) { 2582439e4bfSJean-Christophe PLAGNIOL-VILLARD data = data << 1; 2592439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_raise_ee_clk(hw, &eecd); 2602439e4bfSJean-Christophe PLAGNIOL-VILLARD 2612439e4bfSJean-Christophe PLAGNIOL-VILLARD eecd = E1000_READ_REG(hw, EECD); 2622439e4bfSJean-Christophe PLAGNIOL-VILLARD 2632439e4bfSJean-Christophe PLAGNIOL-VILLARD eecd &= ~(E1000_EECD_DI); 2642439e4bfSJean-Christophe PLAGNIOL-VILLARD if (eecd & E1000_EECD_DO) 2652439e4bfSJean-Christophe PLAGNIOL-VILLARD data |= 1; 2662439e4bfSJean-Christophe PLAGNIOL-VILLARD 2672439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_lower_ee_clk(hw, &eecd); 2682439e4bfSJean-Christophe PLAGNIOL-VILLARD } 2692439e4bfSJean-Christophe PLAGNIOL-VILLARD 2702439e4bfSJean-Christophe PLAGNIOL-VILLARD return data; 2712439e4bfSJean-Christophe PLAGNIOL-VILLARD } 2722439e4bfSJean-Christophe PLAGNIOL-VILLARD 2732439e4bfSJean-Christophe PLAGNIOL-VILLARD /****************************************************************************** 2742439e4bfSJean-Christophe PLAGNIOL-VILLARD * Returns EEPROM to a "standby" state 2752439e4bfSJean-Christophe PLAGNIOL-VILLARD * 2762439e4bfSJean-Christophe PLAGNIOL-VILLARD * hw - Struct containing variables accessed by shared code 2772439e4bfSJean-Christophe PLAGNIOL-VILLARD *****************************************************************************/ 2782326a94dSKyle Moffett void e1000_standby_eeprom(struct e1000_hw *hw) 2792439e4bfSJean-Christophe PLAGNIOL-VILLARD { 280aa070789SRoy Zang struct e1000_eeprom_info *eeprom = &hw->eeprom; 2812439e4bfSJean-Christophe PLAGNIOL-VILLARD uint32_t eecd; 2822439e4bfSJean-Christophe PLAGNIOL-VILLARD 2832439e4bfSJean-Christophe PLAGNIOL-VILLARD eecd = E1000_READ_REG(hw, EECD); 2842439e4bfSJean-Christophe PLAGNIOL-VILLARD 285aa070789SRoy Zang if (eeprom->type == e1000_eeprom_microwire) { 2862439e4bfSJean-Christophe PLAGNIOL-VILLARD eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); 2872439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, EECD, eecd); 2882439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_FLUSH(hw); 289aa070789SRoy Zang udelay(eeprom->delay_usec); 2902439e4bfSJean-Christophe PLAGNIOL-VILLARD 2912439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Clock high */ 2922439e4bfSJean-Christophe PLAGNIOL-VILLARD eecd |= E1000_EECD_SK; 2932439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, EECD, eecd); 2942439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_FLUSH(hw); 295aa070789SRoy Zang udelay(eeprom->delay_usec); 2962439e4bfSJean-Christophe PLAGNIOL-VILLARD 2972439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Select EEPROM */ 2982439e4bfSJean-Christophe PLAGNIOL-VILLARD eecd |= E1000_EECD_CS; 2992439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, EECD, eecd); 3002439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_FLUSH(hw); 301aa070789SRoy Zang udelay(eeprom->delay_usec); 3022439e4bfSJean-Christophe PLAGNIOL-VILLARD 3032439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Clock low */ 3042439e4bfSJean-Christophe PLAGNIOL-VILLARD eecd &= ~E1000_EECD_SK; 3052439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, EECD, eecd); 3062439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_FLUSH(hw); 307aa070789SRoy Zang udelay(eeprom->delay_usec); 308aa070789SRoy Zang } else if (eeprom->type == e1000_eeprom_spi) { 309aa070789SRoy Zang /* Toggle CS to flush commands */ 310aa070789SRoy Zang eecd |= E1000_EECD_CS; 311aa070789SRoy Zang E1000_WRITE_REG(hw, EECD, eecd); 312aa070789SRoy Zang E1000_WRITE_FLUSH(hw); 313aa070789SRoy Zang udelay(eeprom->delay_usec); 314aa070789SRoy Zang eecd &= ~E1000_EECD_CS; 315aa070789SRoy Zang E1000_WRITE_REG(hw, EECD, eecd); 316aa070789SRoy Zang E1000_WRITE_FLUSH(hw); 317aa070789SRoy Zang udelay(eeprom->delay_usec); 318aa070789SRoy Zang } 319aa070789SRoy Zang } 320aa070789SRoy Zang 321aa070789SRoy Zang /*************************************************************************** 322aa070789SRoy Zang * Description: Determines if the onboard NVM is FLASH or EEPROM. 323aa070789SRoy Zang * 324aa070789SRoy Zang * hw - Struct containing variables accessed by shared code 325aa070789SRoy Zang ****************************************************************************/ 326472d5460SYork Sun static bool e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw) 327aa070789SRoy Zang { 328aa070789SRoy Zang uint32_t eecd = 0; 329aa070789SRoy Zang 330aa070789SRoy Zang DEBUGFUNC(); 331aa070789SRoy Zang 332aa070789SRoy Zang if (hw->mac_type == e1000_ich8lan) 333472d5460SYork Sun return false; 334aa070789SRoy Zang 3352c2668f9SRoy Zang if (hw->mac_type == e1000_82573 || hw->mac_type == e1000_82574) { 336aa070789SRoy Zang eecd = E1000_READ_REG(hw, EECD); 337aa070789SRoy Zang 338aa070789SRoy Zang /* Isolate bits 15 & 16 */ 339aa070789SRoy Zang eecd = ((eecd >> 15) & 0x03); 340aa070789SRoy Zang 341aa070789SRoy Zang /* If both bits are set, device is Flash type */ 342aa070789SRoy Zang if (eecd == 0x03) 343472d5460SYork Sun return false; 344aa070789SRoy Zang } 345472d5460SYork Sun return true; 3462439e4bfSJean-Christophe PLAGNIOL-VILLARD } 3472439e4bfSJean-Christophe PLAGNIOL-VILLARD 3482439e4bfSJean-Christophe PLAGNIOL-VILLARD /****************************************************************************** 349aa070789SRoy Zang * Prepares EEPROM for access 3502439e4bfSJean-Christophe PLAGNIOL-VILLARD * 3512439e4bfSJean-Christophe PLAGNIOL-VILLARD * hw - Struct containing variables accessed by shared code 352aa070789SRoy Zang * 353aa070789SRoy Zang * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This 354aa070789SRoy Zang * function should be called before issuing a command to the EEPROM. 3552439e4bfSJean-Christophe PLAGNIOL-VILLARD *****************************************************************************/ 3562326a94dSKyle Moffett int32_t e1000_acquire_eeprom(struct e1000_hw *hw) 3572439e4bfSJean-Christophe PLAGNIOL-VILLARD { 358aa070789SRoy Zang struct e1000_eeprom_info *eeprom = &hw->eeprom; 359aa070789SRoy Zang uint32_t eecd, i = 0; 3602439e4bfSJean-Christophe PLAGNIOL-VILLARD 361f81ecb5dSTimur Tabi DEBUGFUNC(); 362aa070789SRoy Zang 363aa070789SRoy Zang if (e1000_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM)) 364aa070789SRoy Zang return -E1000_ERR_SWFW_SYNC; 365aa070789SRoy Zang eecd = E1000_READ_REG(hw, EECD); 366aa070789SRoy Zang 36795186063SMarek Vasut if (hw->mac_type != e1000_82573 && hw->mac_type != e1000_82574) { 3682439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Request EEPROM Access */ 3692439e4bfSJean-Christophe PLAGNIOL-VILLARD if (hw->mac_type > e1000_82544) { 3702439e4bfSJean-Christophe PLAGNIOL-VILLARD eecd |= E1000_EECD_REQ; 3712439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, EECD, eecd); 3722439e4bfSJean-Christophe PLAGNIOL-VILLARD eecd = E1000_READ_REG(hw, EECD); 373aa070789SRoy Zang while ((!(eecd & E1000_EECD_GNT)) && 374aa070789SRoy Zang (i < E1000_EEPROM_GRANT_ATTEMPTS)) { 3752439e4bfSJean-Christophe PLAGNIOL-VILLARD i++; 376aa070789SRoy Zang udelay(5); 3772439e4bfSJean-Christophe PLAGNIOL-VILLARD eecd = E1000_READ_REG(hw, EECD); 3782439e4bfSJean-Christophe PLAGNIOL-VILLARD } 3792439e4bfSJean-Christophe PLAGNIOL-VILLARD if (!(eecd & E1000_EECD_GNT)) { 3802439e4bfSJean-Christophe PLAGNIOL-VILLARD eecd &= ~E1000_EECD_REQ; 3812439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, EECD, eecd); 3822439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("Could not acquire EEPROM grant\n"); 3832439e4bfSJean-Christophe PLAGNIOL-VILLARD return -E1000_ERR_EEPROM; 3842439e4bfSJean-Christophe PLAGNIOL-VILLARD } 3852439e4bfSJean-Christophe PLAGNIOL-VILLARD } 386aa070789SRoy Zang } 3872439e4bfSJean-Christophe PLAGNIOL-VILLARD 388aa070789SRoy Zang /* Setup EEPROM for Read/Write */ 3892439e4bfSJean-Christophe PLAGNIOL-VILLARD 390aa070789SRoy Zang if (eeprom->type == e1000_eeprom_microwire) { 391aa070789SRoy Zang /* Clear SK and DI */ 392aa070789SRoy Zang eecd &= ~(E1000_EECD_DI | E1000_EECD_SK); 393aa070789SRoy Zang E1000_WRITE_REG(hw, EECD, eecd); 3942439e4bfSJean-Christophe PLAGNIOL-VILLARD 395aa070789SRoy Zang /* Set CS */ 396aa070789SRoy Zang eecd |= E1000_EECD_CS; 397aa070789SRoy Zang E1000_WRITE_REG(hw, EECD, eecd); 398aa070789SRoy Zang } else if (eeprom->type == e1000_eeprom_spi) { 399aa070789SRoy Zang /* Clear SK and CS */ 400aa070789SRoy Zang eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); 401aa070789SRoy Zang E1000_WRITE_REG(hw, EECD, eecd); 402aa070789SRoy Zang udelay(1); 403aa070789SRoy Zang } 4042439e4bfSJean-Christophe PLAGNIOL-VILLARD 405aa070789SRoy Zang return E1000_SUCCESS; 406aa070789SRoy Zang } 4072439e4bfSJean-Christophe PLAGNIOL-VILLARD 408aa070789SRoy Zang /****************************************************************************** 409aa070789SRoy Zang * Sets up eeprom variables in the hw struct. Must be called after mac_type 410aa070789SRoy Zang * is configured. Additionally, if this is ICH8, the flash controller GbE 411aa070789SRoy Zang * registers must be mapped, or this will crash. 412aa070789SRoy Zang * 413aa070789SRoy Zang * hw - Struct containing variables accessed by shared code 414aa070789SRoy Zang *****************************************************************************/ 415aa070789SRoy Zang static int32_t e1000_init_eeprom_params(struct e1000_hw *hw) 416aa070789SRoy Zang { 417aa070789SRoy Zang struct e1000_eeprom_info *eeprom = &hw->eeprom; 41895186063SMarek Vasut uint32_t eecd; 419aa070789SRoy Zang int32_t ret_val = E1000_SUCCESS; 420aa070789SRoy Zang uint16_t eeprom_size; 421aa070789SRoy Zang 42295186063SMarek Vasut if (hw->mac_type == e1000_igb) 42395186063SMarek Vasut eecd = E1000_READ_REG(hw, I210_EECD); 42495186063SMarek Vasut else 42595186063SMarek Vasut eecd = E1000_READ_REG(hw, EECD); 42695186063SMarek Vasut 427f81ecb5dSTimur Tabi DEBUGFUNC(); 428aa070789SRoy Zang 429aa070789SRoy Zang switch (hw->mac_type) { 430aa070789SRoy Zang case e1000_82542_rev2_0: 431aa070789SRoy Zang case e1000_82542_rev2_1: 432aa070789SRoy Zang case e1000_82543: 433aa070789SRoy Zang case e1000_82544: 434aa070789SRoy Zang eeprom->type = e1000_eeprom_microwire; 435aa070789SRoy Zang eeprom->word_size = 64; 436aa070789SRoy Zang eeprom->opcode_bits = 3; 437aa070789SRoy Zang eeprom->address_bits = 6; 438aa070789SRoy Zang eeprom->delay_usec = 50; 439472d5460SYork Sun eeprom->use_eerd = false; 440472d5460SYork Sun eeprom->use_eewr = false; 441aa070789SRoy Zang break; 442aa070789SRoy Zang case e1000_82540: 443aa070789SRoy Zang case e1000_82545: 444aa070789SRoy Zang case e1000_82545_rev_3: 445aa070789SRoy Zang case e1000_82546: 446aa070789SRoy Zang case e1000_82546_rev_3: 447aa070789SRoy Zang eeprom->type = e1000_eeprom_microwire; 448aa070789SRoy Zang eeprom->opcode_bits = 3; 449aa070789SRoy Zang eeprom->delay_usec = 50; 450aa070789SRoy Zang if (eecd & E1000_EECD_SIZE) { 451aa070789SRoy Zang eeprom->word_size = 256; 452aa070789SRoy Zang eeprom->address_bits = 8; 453aa070789SRoy Zang } else { 454aa070789SRoy Zang eeprom->word_size = 64; 455aa070789SRoy Zang eeprom->address_bits = 6; 456aa070789SRoy Zang } 457472d5460SYork Sun eeprom->use_eerd = false; 458472d5460SYork Sun eeprom->use_eewr = false; 459aa070789SRoy Zang break; 460aa070789SRoy Zang case e1000_82541: 461aa070789SRoy Zang case e1000_82541_rev_2: 462aa070789SRoy Zang case e1000_82547: 463aa070789SRoy Zang case e1000_82547_rev_2: 464aa070789SRoy Zang if (eecd & E1000_EECD_TYPE) { 465aa070789SRoy Zang eeprom->type = e1000_eeprom_spi; 466aa070789SRoy Zang eeprom->opcode_bits = 8; 467aa070789SRoy Zang eeprom->delay_usec = 1; 468aa070789SRoy Zang if (eecd & E1000_EECD_ADDR_BITS) { 469aa070789SRoy Zang eeprom->page_size = 32; 470aa070789SRoy Zang eeprom->address_bits = 16; 471aa070789SRoy Zang } else { 472aa070789SRoy Zang eeprom->page_size = 8; 473aa070789SRoy Zang eeprom->address_bits = 8; 474aa070789SRoy Zang } 475aa070789SRoy Zang } else { 476aa070789SRoy Zang eeprom->type = e1000_eeprom_microwire; 477aa070789SRoy Zang eeprom->opcode_bits = 3; 478aa070789SRoy Zang eeprom->delay_usec = 50; 479aa070789SRoy Zang if (eecd & E1000_EECD_ADDR_BITS) { 480aa070789SRoy Zang eeprom->word_size = 256; 481aa070789SRoy Zang eeprom->address_bits = 8; 482aa070789SRoy Zang } else { 483aa070789SRoy Zang eeprom->word_size = 64; 484aa070789SRoy Zang eeprom->address_bits = 6; 485aa070789SRoy Zang } 486aa070789SRoy Zang } 487472d5460SYork Sun eeprom->use_eerd = false; 488472d5460SYork Sun eeprom->use_eewr = false; 489aa070789SRoy Zang break; 490aa070789SRoy Zang case e1000_82571: 491aa070789SRoy Zang case e1000_82572: 492aa070789SRoy Zang eeprom->type = e1000_eeprom_spi; 493aa070789SRoy Zang eeprom->opcode_bits = 8; 494aa070789SRoy Zang eeprom->delay_usec = 1; 495aa070789SRoy Zang if (eecd & E1000_EECD_ADDR_BITS) { 496aa070789SRoy Zang eeprom->page_size = 32; 497aa070789SRoy Zang eeprom->address_bits = 16; 498aa070789SRoy Zang } else { 499aa070789SRoy Zang eeprom->page_size = 8; 500aa070789SRoy Zang eeprom->address_bits = 8; 501aa070789SRoy Zang } 502472d5460SYork Sun eeprom->use_eerd = false; 503472d5460SYork Sun eeprom->use_eewr = false; 504aa070789SRoy Zang break; 505aa070789SRoy Zang case e1000_82573: 5062c2668f9SRoy Zang case e1000_82574: 507aa070789SRoy Zang eeprom->type = e1000_eeprom_spi; 508aa070789SRoy Zang eeprom->opcode_bits = 8; 509aa070789SRoy Zang eeprom->delay_usec = 1; 510aa070789SRoy Zang if (eecd & E1000_EECD_ADDR_BITS) { 511aa070789SRoy Zang eeprom->page_size = 32; 512aa070789SRoy Zang eeprom->address_bits = 16; 513aa070789SRoy Zang } else { 514aa070789SRoy Zang eeprom->page_size = 8; 515aa070789SRoy Zang eeprom->address_bits = 8; 516aa070789SRoy Zang } 51795186063SMarek Vasut if (e1000_is_onboard_nvm_eeprom(hw) == false) { 518472d5460SYork Sun eeprom->use_eerd = true; 519472d5460SYork Sun eeprom->use_eewr = true; 52095186063SMarek Vasut 521aa070789SRoy Zang eeprom->type = e1000_eeprom_flash; 522aa070789SRoy Zang eeprom->word_size = 2048; 523aa070789SRoy Zang 524aa070789SRoy Zang /* Ensure that the Autonomous FLASH update bit is cleared due to 525aa070789SRoy Zang * Flash update issue on parts which use a FLASH for NVM. */ 526aa070789SRoy Zang eecd &= ~E1000_EECD_AUPDEN; 5272439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, EECD, eecd); 5282439e4bfSJean-Christophe PLAGNIOL-VILLARD } 529aa070789SRoy Zang break; 530aa070789SRoy Zang case e1000_80003es2lan: 531aa070789SRoy Zang eeprom->type = e1000_eeprom_spi; 532aa070789SRoy Zang eeprom->opcode_bits = 8; 533aa070789SRoy Zang eeprom->delay_usec = 1; 534aa070789SRoy Zang if (eecd & E1000_EECD_ADDR_BITS) { 535aa070789SRoy Zang eeprom->page_size = 32; 536aa070789SRoy Zang eeprom->address_bits = 16; 537aa070789SRoy Zang } else { 538aa070789SRoy Zang eeprom->page_size = 8; 539aa070789SRoy Zang eeprom->address_bits = 8; 5402439e4bfSJean-Christophe PLAGNIOL-VILLARD } 541472d5460SYork Sun eeprom->use_eerd = true; 542472d5460SYork Sun eeprom->use_eewr = false; 543aa070789SRoy Zang break; 54495186063SMarek Vasut case e1000_igb: 54595186063SMarek Vasut /* i210 has 4k of iNVM mapped as EEPROM */ 54695186063SMarek Vasut eeprom->type = e1000_eeprom_invm; 54795186063SMarek Vasut eeprom->opcode_bits = 8; 54895186063SMarek Vasut eeprom->delay_usec = 1; 54995186063SMarek Vasut eeprom->page_size = 32; 55095186063SMarek Vasut eeprom->address_bits = 16; 55195186063SMarek Vasut eeprom->use_eerd = true; 55295186063SMarek Vasut eeprom->use_eewr = false; 55395186063SMarek Vasut break; 5542439e4bfSJean-Christophe PLAGNIOL-VILLARD 555aa070789SRoy Zang /* ich8lan does not support currently. if needed, please 556aa070789SRoy Zang * add corresponding code and functions. 557aa070789SRoy Zang */ 5582439e4bfSJean-Christophe PLAGNIOL-VILLARD #if 0 559aa070789SRoy Zang case e1000_ich8lan: 5602439e4bfSJean-Christophe PLAGNIOL-VILLARD { 561aa070789SRoy Zang int32_t i = 0; 5622439e4bfSJean-Christophe PLAGNIOL-VILLARD 563aa070789SRoy Zang eeprom->type = e1000_eeprom_ich8; 564472d5460SYork Sun eeprom->use_eerd = false; 565472d5460SYork Sun eeprom->use_eewr = false; 566aa070789SRoy Zang eeprom->word_size = E1000_SHADOW_RAM_WORDS; 567aa070789SRoy Zang uint32_t flash_size = E1000_READ_ICH_FLASH_REG(hw, 568aa070789SRoy Zang ICH_FLASH_GFPREG); 569aa070789SRoy Zang /* Zero the shadow RAM structure. But don't load it from NVM 570aa070789SRoy Zang * so as to save time for driver init */ 571aa070789SRoy Zang if (hw->eeprom_shadow_ram != NULL) { 572aa070789SRoy Zang for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) { 573472d5460SYork Sun hw->eeprom_shadow_ram[i].modified = false; 574aa070789SRoy Zang hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF; 575aa070789SRoy Zang } 5762439e4bfSJean-Christophe PLAGNIOL-VILLARD } 5772439e4bfSJean-Christophe PLAGNIOL-VILLARD 578aa070789SRoy Zang hw->flash_base_addr = (flash_size & ICH_GFPREG_BASE_MASK) * 579aa070789SRoy Zang ICH_FLASH_SECTOR_SIZE; 5802439e4bfSJean-Christophe PLAGNIOL-VILLARD 581aa070789SRoy Zang hw->flash_bank_size = ((flash_size >> 16) 582aa070789SRoy Zang & ICH_GFPREG_BASE_MASK) + 1; 583aa070789SRoy Zang hw->flash_bank_size -= (flash_size & ICH_GFPREG_BASE_MASK); 5842439e4bfSJean-Christophe PLAGNIOL-VILLARD 585aa070789SRoy Zang hw->flash_bank_size *= ICH_FLASH_SECTOR_SIZE; 5862439e4bfSJean-Christophe PLAGNIOL-VILLARD 587aa070789SRoy Zang hw->flash_bank_size /= 2 * sizeof(uint16_t); 588aa070789SRoy Zang break; 5892439e4bfSJean-Christophe PLAGNIOL-VILLARD } 5902439e4bfSJean-Christophe PLAGNIOL-VILLARD #endif 591aa070789SRoy Zang default: 592aa070789SRoy Zang break; 593aa070789SRoy Zang } 594aa070789SRoy Zang 59595186063SMarek Vasut if (eeprom->type == e1000_eeprom_spi || 59695186063SMarek Vasut eeprom->type == e1000_eeprom_invm) { 597aa070789SRoy Zang /* eeprom_size will be an enum [0..8] that maps 598aa070789SRoy Zang * to eeprom sizes 128B to 599aa070789SRoy Zang * 32KB (incremented by powers of 2). 600aa070789SRoy Zang */ 601aa070789SRoy Zang if (hw->mac_type <= e1000_82547_rev_2) { 602aa070789SRoy Zang /* Set to default value for initial eeprom read. */ 603aa070789SRoy Zang eeprom->word_size = 64; 604aa070789SRoy Zang ret_val = e1000_read_eeprom(hw, EEPROM_CFG, 1, 605aa070789SRoy Zang &eeprom_size); 606aa070789SRoy Zang if (ret_val) 607aa070789SRoy Zang return ret_val; 608aa070789SRoy Zang eeprom_size = (eeprom_size & EEPROM_SIZE_MASK) 609aa070789SRoy Zang >> EEPROM_SIZE_SHIFT; 610aa070789SRoy Zang /* 256B eeprom size was not supported in earlier 611aa070789SRoy Zang * hardware, so we bump eeprom_size up one to 612aa070789SRoy Zang * ensure that "1" (which maps to 256B) is never 613aa070789SRoy Zang * the result used in the shifting logic below. */ 614aa070789SRoy Zang if (eeprom_size) 615aa070789SRoy Zang eeprom_size++; 616aa070789SRoy Zang } else { 617aa070789SRoy Zang eeprom_size = (uint16_t)((eecd & 618aa070789SRoy Zang E1000_EECD_SIZE_EX_MASK) >> 619aa070789SRoy Zang E1000_EECD_SIZE_EX_SHIFT); 620aa070789SRoy Zang } 621aa070789SRoy Zang 622aa070789SRoy Zang eeprom->word_size = 1 << (eeprom_size + EEPROM_WORD_SIZE_SHIFT); 623aa070789SRoy Zang } 624aa070789SRoy Zang return ret_val; 625aa070789SRoy Zang } 626aa070789SRoy Zang 627aa070789SRoy Zang /****************************************************************************** 628aa070789SRoy Zang * Polls the status bit (bit 1) of the EERD to determine when the read is done. 629aa070789SRoy Zang * 630aa070789SRoy Zang * hw - Struct containing variables accessed by shared code 631aa070789SRoy Zang *****************************************************************************/ 632aa070789SRoy Zang static int32_t 633aa070789SRoy Zang e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd) 634aa070789SRoy Zang { 635aa070789SRoy Zang uint32_t attempts = 100000; 636aa070789SRoy Zang uint32_t i, reg = 0; 637aa070789SRoy Zang int32_t done = E1000_ERR_EEPROM; 638aa070789SRoy Zang 639aa070789SRoy Zang for (i = 0; i < attempts; i++) { 64095186063SMarek Vasut if (eerd == E1000_EEPROM_POLL_READ) { 64195186063SMarek Vasut if (hw->mac_type == e1000_igb) 64295186063SMarek Vasut reg = E1000_READ_REG(hw, I210_EERD); 64395186063SMarek Vasut else 644aa070789SRoy Zang reg = E1000_READ_REG(hw, EERD); 64595186063SMarek Vasut } else { 64695186063SMarek Vasut if (hw->mac_type == e1000_igb) 64795186063SMarek Vasut reg = E1000_READ_REG(hw, I210_EEWR); 648aa070789SRoy Zang else 649aa070789SRoy Zang reg = E1000_READ_REG(hw, EEWR); 65095186063SMarek Vasut } 651aa070789SRoy Zang 652aa070789SRoy Zang if (reg & E1000_EEPROM_RW_REG_DONE) { 653aa070789SRoy Zang done = E1000_SUCCESS; 654aa070789SRoy Zang break; 655aa070789SRoy Zang } 656aa070789SRoy Zang udelay(5); 657aa070789SRoy Zang } 658aa070789SRoy Zang 659aa070789SRoy Zang return done; 660aa070789SRoy Zang } 661aa070789SRoy Zang 662aa070789SRoy Zang /****************************************************************************** 663aa070789SRoy Zang * Reads a 16 bit word from the EEPROM using the EERD register. 664aa070789SRoy Zang * 665aa070789SRoy Zang * hw - Struct containing variables accessed by shared code 666aa070789SRoy Zang * offset - offset of word in the EEPROM to read 667aa070789SRoy Zang * data - word read from the EEPROM 668aa070789SRoy Zang * words - number of words to read 669aa070789SRoy Zang *****************************************************************************/ 670aa070789SRoy Zang static int32_t 671aa070789SRoy Zang e1000_read_eeprom_eerd(struct e1000_hw *hw, 672aa070789SRoy Zang uint16_t offset, 673aa070789SRoy Zang uint16_t words, 674aa070789SRoy Zang uint16_t *data) 675aa070789SRoy Zang { 676aa070789SRoy Zang uint32_t i, eerd = 0; 677aa070789SRoy Zang int32_t error = 0; 678aa070789SRoy Zang 679aa070789SRoy Zang for (i = 0; i < words; i++) { 680aa070789SRoy Zang eerd = ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) + 681aa070789SRoy Zang E1000_EEPROM_RW_REG_START; 682aa070789SRoy Zang 68395186063SMarek Vasut if (hw->mac_type == e1000_igb) 68495186063SMarek Vasut E1000_WRITE_REG(hw, I210_EERD, eerd); 68595186063SMarek Vasut else 686aa070789SRoy Zang E1000_WRITE_REG(hw, EERD, eerd); 68795186063SMarek Vasut 688aa070789SRoy Zang error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_READ); 689aa070789SRoy Zang 690aa070789SRoy Zang if (error) 691aa070789SRoy Zang break; 69295186063SMarek Vasut 69395186063SMarek Vasut if (hw->mac_type == e1000_igb) { 69495186063SMarek Vasut data[i] = (E1000_READ_REG(hw, I210_EERD) >> 69595186063SMarek Vasut E1000_EEPROM_RW_REG_DATA); 69695186063SMarek Vasut } else { 697aa070789SRoy Zang data[i] = (E1000_READ_REG(hw, EERD) >> 698aa070789SRoy Zang E1000_EEPROM_RW_REG_DATA); 69995186063SMarek Vasut } 700aa070789SRoy Zang 701aa070789SRoy Zang } 702aa070789SRoy Zang 703aa070789SRoy Zang return error; 704aa070789SRoy Zang } 705aa070789SRoy Zang 7062326a94dSKyle Moffett void e1000_release_eeprom(struct e1000_hw *hw) 707aa070789SRoy Zang { 708aa070789SRoy Zang uint32_t eecd; 709aa070789SRoy Zang 710aa070789SRoy Zang DEBUGFUNC(); 711aa070789SRoy Zang 712aa070789SRoy Zang eecd = E1000_READ_REG(hw, EECD); 713aa070789SRoy Zang 714aa070789SRoy Zang if (hw->eeprom.type == e1000_eeprom_spi) { 715aa070789SRoy Zang eecd |= E1000_EECD_CS; /* Pull CS high */ 716aa070789SRoy Zang eecd &= ~E1000_EECD_SK; /* Lower SCK */ 717aa070789SRoy Zang 718aa070789SRoy Zang E1000_WRITE_REG(hw, EECD, eecd); 719aa070789SRoy Zang 720aa070789SRoy Zang udelay(hw->eeprom.delay_usec); 721aa070789SRoy Zang } else if (hw->eeprom.type == e1000_eeprom_microwire) { 722aa070789SRoy Zang /* cleanup eeprom */ 723aa070789SRoy Zang 724aa070789SRoy Zang /* CS on Microwire is active-high */ 725aa070789SRoy Zang eecd &= ~(E1000_EECD_CS | E1000_EECD_DI); 726aa070789SRoy Zang 727aa070789SRoy Zang E1000_WRITE_REG(hw, EECD, eecd); 728aa070789SRoy Zang 729aa070789SRoy Zang /* Rising edge of clock */ 730aa070789SRoy Zang eecd |= E1000_EECD_SK; 731aa070789SRoy Zang E1000_WRITE_REG(hw, EECD, eecd); 732aa070789SRoy Zang E1000_WRITE_FLUSH(hw); 733aa070789SRoy Zang udelay(hw->eeprom.delay_usec); 734aa070789SRoy Zang 735aa070789SRoy Zang /* Falling edge of clock */ 736aa070789SRoy Zang eecd &= ~E1000_EECD_SK; 737aa070789SRoy Zang E1000_WRITE_REG(hw, EECD, eecd); 738aa070789SRoy Zang E1000_WRITE_FLUSH(hw); 739aa070789SRoy Zang udelay(hw->eeprom.delay_usec); 740aa070789SRoy Zang } 741aa070789SRoy Zang 742aa070789SRoy Zang /* Stop requesting EEPROM access */ 743aa070789SRoy Zang if (hw->mac_type > e1000_82544) { 744aa070789SRoy Zang eecd &= ~E1000_EECD_REQ; 745aa070789SRoy Zang E1000_WRITE_REG(hw, EECD, eecd); 746aa070789SRoy Zang } 7477e2d991dSTim Harvey 7487e2d991dSTim Harvey e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM); 749aa070789SRoy Zang } 7507e2d991dSTim Harvey 751aa070789SRoy Zang /****************************************************************************** 752aa070789SRoy Zang * Reads a 16 bit word from the EEPROM. 753aa070789SRoy Zang * 754aa070789SRoy Zang * hw - Struct containing variables accessed by shared code 755aa070789SRoy Zang *****************************************************************************/ 756aa070789SRoy Zang static int32_t 757aa070789SRoy Zang e1000_spi_eeprom_ready(struct e1000_hw *hw) 758aa070789SRoy Zang { 759aa070789SRoy Zang uint16_t retry_count = 0; 760aa070789SRoy Zang uint8_t spi_stat_reg; 761aa070789SRoy Zang 762aa070789SRoy Zang DEBUGFUNC(); 763aa070789SRoy Zang 764aa070789SRoy Zang /* Read "Status Register" repeatedly until the LSB is cleared. The 765aa070789SRoy Zang * EEPROM will signal that the command has been completed by clearing 766aa070789SRoy Zang * bit 0 of the internal status register. If it's not cleared within 767aa070789SRoy Zang * 5 milliseconds, then error out. 768aa070789SRoy Zang */ 769aa070789SRoy Zang retry_count = 0; 770aa070789SRoy Zang do { 771aa070789SRoy Zang e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI, 772aa070789SRoy Zang hw->eeprom.opcode_bits); 773aa070789SRoy Zang spi_stat_reg = (uint8_t)e1000_shift_in_ee_bits(hw, 8); 774aa070789SRoy Zang if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI)) 775aa070789SRoy Zang break; 776aa070789SRoy Zang 777aa070789SRoy Zang udelay(5); 778aa070789SRoy Zang retry_count += 5; 779aa070789SRoy Zang 780aa070789SRoy Zang e1000_standby_eeprom(hw); 781aa070789SRoy Zang } while (retry_count < EEPROM_MAX_RETRY_SPI); 782aa070789SRoy Zang 783aa070789SRoy Zang /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and 784aa070789SRoy Zang * only 0-5mSec on 5V devices) 785aa070789SRoy Zang */ 786aa070789SRoy Zang if (retry_count >= EEPROM_MAX_RETRY_SPI) { 787aa070789SRoy Zang DEBUGOUT("SPI EEPROM Status error\n"); 788aa070789SRoy Zang return -E1000_ERR_EEPROM; 789aa070789SRoy Zang } 790aa070789SRoy Zang 791aa070789SRoy Zang return E1000_SUCCESS; 792aa070789SRoy Zang } 793aa070789SRoy Zang 794aa070789SRoy Zang /****************************************************************************** 795aa070789SRoy Zang * Reads a 16 bit word from the EEPROM. 796aa070789SRoy Zang * 797aa070789SRoy Zang * hw - Struct containing variables accessed by shared code 798aa070789SRoy Zang * offset - offset of word in the EEPROM to read 799aa070789SRoy Zang * data - word read from the EEPROM 800aa070789SRoy Zang *****************************************************************************/ 801aa070789SRoy Zang static int32_t 802aa070789SRoy Zang e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset, 803aa070789SRoy Zang uint16_t words, uint16_t *data) 804aa070789SRoy Zang { 805aa070789SRoy Zang struct e1000_eeprom_info *eeprom = &hw->eeprom; 806aa070789SRoy Zang uint32_t i = 0; 807aa070789SRoy Zang 808aa070789SRoy Zang DEBUGFUNC(); 809aa070789SRoy Zang 810aa070789SRoy Zang /* If eeprom is not yet detected, do so now */ 811aa070789SRoy Zang if (eeprom->word_size == 0) 812aa070789SRoy Zang e1000_init_eeprom_params(hw); 813aa070789SRoy Zang 814aa070789SRoy Zang /* A check for invalid values: offset too large, too many words, 815aa070789SRoy Zang * and not enough words. 816aa070789SRoy Zang */ 817aa070789SRoy Zang if ((offset >= eeprom->word_size) || 818aa070789SRoy Zang (words > eeprom->word_size - offset) || 819aa070789SRoy Zang (words == 0)) { 820aa070789SRoy Zang DEBUGOUT("\"words\" parameter out of bounds." 821aa070789SRoy Zang "Words = %d, size = %d\n", offset, eeprom->word_size); 822aa070789SRoy Zang return -E1000_ERR_EEPROM; 823aa070789SRoy Zang } 824aa070789SRoy Zang 825aa070789SRoy Zang /* EEPROM's that don't use EERD to read require us to bit-bang the SPI 826aa070789SRoy Zang * directly. In this case, we need to acquire the EEPROM so that 827aa070789SRoy Zang * FW or other port software does not interrupt. 828aa070789SRoy Zang */ 829472d5460SYork Sun if (e1000_is_onboard_nvm_eeprom(hw) == true && 830472d5460SYork Sun hw->eeprom.use_eerd == false) { 831aa070789SRoy Zang 832aa070789SRoy Zang /* Prepare the EEPROM for bit-bang reading */ 833aa070789SRoy Zang if (e1000_acquire_eeprom(hw) != E1000_SUCCESS) 834aa070789SRoy Zang return -E1000_ERR_EEPROM; 835aa070789SRoy Zang } 836aa070789SRoy Zang 837aa070789SRoy Zang /* Eerd register EEPROM access requires no eeprom aquire/release */ 838472d5460SYork Sun if (eeprom->use_eerd == true) 839aa070789SRoy Zang return e1000_read_eeprom_eerd(hw, offset, words, data); 840aa070789SRoy Zang 841aa070789SRoy Zang /* ich8lan does not support currently. if needed, please 842aa070789SRoy Zang * add corresponding code and functions. 843aa070789SRoy Zang */ 844aa070789SRoy Zang #if 0 845aa070789SRoy Zang /* ICH EEPROM access is done via the ICH flash controller */ 846aa070789SRoy Zang if (eeprom->type == e1000_eeprom_ich8) 847aa070789SRoy Zang return e1000_read_eeprom_ich8(hw, offset, words, data); 848aa070789SRoy Zang #endif 849aa070789SRoy Zang /* Set up the SPI or Microwire EEPROM for bit-bang reading. We have 850aa070789SRoy Zang * acquired the EEPROM at this point, so any returns should relase it */ 851aa070789SRoy Zang if (eeprom->type == e1000_eeprom_spi) { 852aa070789SRoy Zang uint16_t word_in; 853aa070789SRoy Zang uint8_t read_opcode = EEPROM_READ_OPCODE_SPI; 854aa070789SRoy Zang 855aa070789SRoy Zang if (e1000_spi_eeprom_ready(hw)) { 856aa070789SRoy Zang e1000_release_eeprom(hw); 857aa070789SRoy Zang return -E1000_ERR_EEPROM; 858aa070789SRoy Zang } 859aa070789SRoy Zang 860aa070789SRoy Zang e1000_standby_eeprom(hw); 861aa070789SRoy Zang 862aa070789SRoy Zang /* Some SPI eeproms use the 8th address bit embedded in 863aa070789SRoy Zang * the opcode */ 864aa070789SRoy Zang if ((eeprom->address_bits == 8) && (offset >= 128)) 865aa070789SRoy Zang read_opcode |= EEPROM_A8_OPCODE_SPI; 866aa070789SRoy Zang 867aa070789SRoy Zang /* Send the READ command (opcode + addr) */ 868aa070789SRoy Zang e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits); 869aa070789SRoy Zang e1000_shift_out_ee_bits(hw, (uint16_t)(offset*2), 870aa070789SRoy Zang eeprom->address_bits); 871aa070789SRoy Zang 872aa070789SRoy Zang /* Read the data. The address of the eeprom internally 873aa070789SRoy Zang * increments with each byte (spi) being read, saving on the 874aa070789SRoy Zang * overhead of eeprom setup and tear-down. The address 875aa070789SRoy Zang * counter will roll over if reading beyond the size of 876aa070789SRoy Zang * the eeprom, thus allowing the entire memory to be read 877aa070789SRoy Zang * starting from any offset. */ 878aa070789SRoy Zang for (i = 0; i < words; i++) { 879aa070789SRoy Zang word_in = e1000_shift_in_ee_bits(hw, 16); 880aa070789SRoy Zang data[i] = (word_in >> 8) | (word_in << 8); 881aa070789SRoy Zang } 882aa070789SRoy Zang } else if (eeprom->type == e1000_eeprom_microwire) { 883aa070789SRoy Zang for (i = 0; i < words; i++) { 884aa070789SRoy Zang /* Send the READ command (opcode + addr) */ 885aa070789SRoy Zang e1000_shift_out_ee_bits(hw, 886aa070789SRoy Zang EEPROM_READ_OPCODE_MICROWIRE, 887aa070789SRoy Zang eeprom->opcode_bits); 888aa070789SRoy Zang e1000_shift_out_ee_bits(hw, (uint16_t)(offset + i), 889aa070789SRoy Zang eeprom->address_bits); 890aa070789SRoy Zang 891aa070789SRoy Zang /* Read the data. For microwire, each word requires 892aa070789SRoy Zang * the overhead of eeprom setup and tear-down. */ 893aa070789SRoy Zang data[i] = e1000_shift_in_ee_bits(hw, 16); 894aa070789SRoy Zang e1000_standby_eeprom(hw); 895aa070789SRoy Zang } 896aa070789SRoy Zang } 897aa070789SRoy Zang 898aa070789SRoy Zang /* End this read operation */ 899aa070789SRoy Zang e1000_release_eeprom(hw); 900aa070789SRoy Zang 901aa070789SRoy Zang return E1000_SUCCESS; 902aa070789SRoy Zang } 9032439e4bfSJean-Christophe PLAGNIOL-VILLARD 9042439e4bfSJean-Christophe PLAGNIOL-VILLARD /****************************************************************************** 9052439e4bfSJean-Christophe PLAGNIOL-VILLARD * Verifies that the EEPROM has a valid checksum 9062439e4bfSJean-Christophe PLAGNIOL-VILLARD * 9072439e4bfSJean-Christophe PLAGNIOL-VILLARD * hw - Struct containing variables accessed by shared code 9082439e4bfSJean-Christophe PLAGNIOL-VILLARD * 9092439e4bfSJean-Christophe PLAGNIOL-VILLARD * Reads the first 64 16 bit words of the EEPROM and sums the values read. 9102439e4bfSJean-Christophe PLAGNIOL-VILLARD * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is 9112439e4bfSJean-Christophe PLAGNIOL-VILLARD * valid. 9122439e4bfSJean-Christophe PLAGNIOL-VILLARD *****************************************************************************/ 913114d7fc0SKyle Moffett static int e1000_validate_eeprom_checksum(struct e1000_hw *hw) 9142439e4bfSJean-Christophe PLAGNIOL-VILLARD { 915114d7fc0SKyle Moffett uint16_t i, checksum, checksum_reg, *buf; 9162439e4bfSJean-Christophe PLAGNIOL-VILLARD 9172439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGFUNC(); 9182439e4bfSJean-Christophe PLAGNIOL-VILLARD 919114d7fc0SKyle Moffett /* Allocate a temporary buffer */ 920114d7fc0SKyle Moffett buf = malloc(sizeof(buf[0]) * (EEPROM_CHECKSUM_REG + 1)); 921114d7fc0SKyle Moffett if (!buf) { 9225c5e707aSSimon Glass E1000_ERR(hw, "Unable to allocate EEPROM buffer!\n"); 9232439e4bfSJean-Christophe PLAGNIOL-VILLARD return -E1000_ERR_EEPROM; 9242439e4bfSJean-Christophe PLAGNIOL-VILLARD } 9252439e4bfSJean-Christophe PLAGNIOL-VILLARD 926114d7fc0SKyle Moffett /* Read the EEPROM */ 927114d7fc0SKyle Moffett if (e1000_read_eeprom(hw, 0, EEPROM_CHECKSUM_REG + 1, buf) < 0) { 9285c5e707aSSimon Glass E1000_ERR(hw, "Unable to read EEPROM!\n"); 9292439e4bfSJean-Christophe PLAGNIOL-VILLARD return -E1000_ERR_EEPROM; 9302439e4bfSJean-Christophe PLAGNIOL-VILLARD } 931114d7fc0SKyle Moffett 932114d7fc0SKyle Moffett /* Compute the checksum */ 9337a341066SWolfgang Denk checksum = 0; 934114d7fc0SKyle Moffett for (i = 0; i < EEPROM_CHECKSUM_REG; i++) 935114d7fc0SKyle Moffett checksum += buf[i]; 936114d7fc0SKyle Moffett checksum = ((uint16_t)EEPROM_SUM) - checksum; 937114d7fc0SKyle Moffett checksum_reg = buf[i]; 938114d7fc0SKyle Moffett 939114d7fc0SKyle Moffett /* Verify it! */ 940114d7fc0SKyle Moffett if (checksum == checksum_reg) 941114d7fc0SKyle Moffett return 0; 942114d7fc0SKyle Moffett 943114d7fc0SKyle Moffett /* Hrm, verification failed, print an error */ 9445c5e707aSSimon Glass E1000_ERR(hw, "EEPROM checksum is incorrect!\n"); 9455c5e707aSSimon Glass E1000_ERR(hw, " ...register was 0x%04hx, calculated 0x%04hx\n", 946114d7fc0SKyle Moffett checksum_reg, checksum); 947114d7fc0SKyle Moffett 948114d7fc0SKyle Moffett return -E1000_ERR_EEPROM; 9492439e4bfSJean-Christophe PLAGNIOL-VILLARD } 9508712adfdSRojhalat Ibrahim #endif /* CONFIG_E1000_NO_NVM */ 951ecbd2078SRoy Zang 952ecbd2078SRoy Zang /***************************************************************************** 953ecbd2078SRoy Zang * Set PHY to class A mode 954ecbd2078SRoy Zang * Assumes the following operations will follow to enable the new class mode. 955ecbd2078SRoy Zang * 1. Do a PHY soft reset 956ecbd2078SRoy Zang * 2. Restart auto-negotiation or force link. 957ecbd2078SRoy Zang * 958ecbd2078SRoy Zang * hw - Struct containing variables accessed by shared code 959ecbd2078SRoy Zang ****************************************************************************/ 960ecbd2078SRoy Zang static int32_t 961ecbd2078SRoy Zang e1000_set_phy_mode(struct e1000_hw *hw) 962ecbd2078SRoy Zang { 9638712adfdSRojhalat Ibrahim #ifndef CONFIG_E1000_NO_NVM 964ecbd2078SRoy Zang int32_t ret_val; 965ecbd2078SRoy Zang uint16_t eeprom_data; 966ecbd2078SRoy Zang 967ecbd2078SRoy Zang DEBUGFUNC(); 968ecbd2078SRoy Zang 969ecbd2078SRoy Zang if ((hw->mac_type == e1000_82545_rev_3) && 970ecbd2078SRoy Zang (hw->media_type == e1000_media_type_copper)) { 971ecbd2078SRoy Zang ret_val = e1000_read_eeprom(hw, EEPROM_PHY_CLASS_WORD, 972ecbd2078SRoy Zang 1, &eeprom_data); 973ecbd2078SRoy Zang if (ret_val) 974ecbd2078SRoy Zang return ret_val; 975ecbd2078SRoy Zang 976ecbd2078SRoy Zang if ((eeprom_data != EEPROM_RESERVED_WORD) && 977ecbd2078SRoy Zang (eeprom_data & EEPROM_PHY_CLASS_A)) { 978ecbd2078SRoy Zang ret_val = e1000_write_phy_reg(hw, 979ecbd2078SRoy Zang M88E1000_PHY_PAGE_SELECT, 0x000B); 980ecbd2078SRoy Zang if (ret_val) 981ecbd2078SRoy Zang return ret_val; 982ecbd2078SRoy Zang ret_val = e1000_write_phy_reg(hw, 983ecbd2078SRoy Zang M88E1000_PHY_GEN_CONTROL, 0x8104); 984ecbd2078SRoy Zang if (ret_val) 985ecbd2078SRoy Zang return ret_val; 986ecbd2078SRoy Zang 987472d5460SYork Sun hw->phy_reset_disable = false; 988ecbd2078SRoy Zang } 989ecbd2078SRoy Zang } 9908712adfdSRojhalat Ibrahim #endif 991ecbd2078SRoy Zang return E1000_SUCCESS; 992ecbd2078SRoy Zang } 9932439e4bfSJean-Christophe PLAGNIOL-VILLARD 9948712adfdSRojhalat Ibrahim #ifndef CONFIG_E1000_NO_NVM 995aa070789SRoy Zang /*************************************************************************** 996aa070789SRoy Zang * 997aa070789SRoy Zang * Obtaining software semaphore bit (SMBI) before resetting PHY. 998aa070789SRoy Zang * 999aa070789SRoy Zang * hw: Struct containing variables accessed by shared code 1000aa070789SRoy Zang * 1001aa070789SRoy Zang * returns: - E1000_ERR_RESET if fail to obtain semaphore. 1002aa070789SRoy Zang * E1000_SUCCESS at any other case. 1003aa070789SRoy Zang * 1004aa070789SRoy Zang ***************************************************************************/ 1005aa070789SRoy Zang static int32_t 1006aa070789SRoy Zang e1000_get_software_semaphore(struct e1000_hw *hw) 1007aa070789SRoy Zang { 1008aa070789SRoy Zang int32_t timeout = hw->eeprom.word_size + 1; 1009aa070789SRoy Zang uint32_t swsm; 1010aa070789SRoy Zang 1011aa070789SRoy Zang DEBUGFUNC(); 1012aa070789SRoy Zang 1013aa070789SRoy Zang if (hw->mac_type != e1000_80003es2lan) 1014aa070789SRoy Zang return E1000_SUCCESS; 1015aa070789SRoy Zang 1016aa070789SRoy Zang while (timeout) { 1017aa070789SRoy Zang swsm = E1000_READ_REG(hw, SWSM); 1018aa070789SRoy Zang /* If SMBI bit cleared, it is now set and we hold 1019aa070789SRoy Zang * the semaphore */ 1020aa070789SRoy Zang if (!(swsm & E1000_SWSM_SMBI)) 1021aa070789SRoy Zang break; 1022aa070789SRoy Zang mdelay(1); 1023aa070789SRoy Zang timeout--; 1024aa070789SRoy Zang } 1025aa070789SRoy Zang 1026aa070789SRoy Zang if (!timeout) { 1027aa070789SRoy Zang DEBUGOUT("Driver can't access device - SMBI bit is set.\n"); 1028aa070789SRoy Zang return -E1000_ERR_RESET; 1029aa070789SRoy Zang } 1030aa070789SRoy Zang 1031aa070789SRoy Zang return E1000_SUCCESS; 1032aa070789SRoy Zang } 10338712adfdSRojhalat Ibrahim #endif 1034aa070789SRoy Zang 1035aa070789SRoy Zang /*************************************************************************** 1036aa070789SRoy Zang * This function clears HW semaphore bits. 1037aa070789SRoy Zang * 1038aa070789SRoy Zang * hw: Struct containing variables accessed by shared code 1039aa070789SRoy Zang * 1040aa070789SRoy Zang * returns: - None. 1041aa070789SRoy Zang * 1042aa070789SRoy Zang ***************************************************************************/ 1043aa070789SRoy Zang static void 1044aa070789SRoy Zang e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw) 1045aa070789SRoy Zang { 10468712adfdSRojhalat Ibrahim #ifndef CONFIG_E1000_NO_NVM 1047aa070789SRoy Zang uint32_t swsm; 1048aa070789SRoy Zang 1049aa070789SRoy Zang DEBUGFUNC(); 1050aa070789SRoy Zang 1051aa070789SRoy Zang if (!hw->eeprom_semaphore_present) 1052aa070789SRoy Zang return; 1053aa070789SRoy Zang 1054aa070789SRoy Zang swsm = E1000_READ_REG(hw, SWSM); 1055aa070789SRoy Zang if (hw->mac_type == e1000_80003es2lan) { 1056aa070789SRoy Zang /* Release both semaphores. */ 1057aa070789SRoy Zang swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI); 1058aa070789SRoy Zang } else 1059aa070789SRoy Zang swsm &= ~(E1000_SWSM_SWESMBI); 1060aa070789SRoy Zang E1000_WRITE_REG(hw, SWSM, swsm); 10618712adfdSRojhalat Ibrahim #endif 1062aa070789SRoy Zang } 1063aa070789SRoy Zang 1064aa070789SRoy Zang /*************************************************************************** 1065aa070789SRoy Zang * 1066aa070789SRoy Zang * Using the combination of SMBI and SWESMBI semaphore bits when resetting 1067aa070789SRoy Zang * adapter or Eeprom access. 1068aa070789SRoy Zang * 1069aa070789SRoy Zang * hw: Struct containing variables accessed by shared code 1070aa070789SRoy Zang * 1071aa070789SRoy Zang * returns: - E1000_ERR_EEPROM if fail to access EEPROM. 1072aa070789SRoy Zang * E1000_SUCCESS at any other case. 1073aa070789SRoy Zang * 1074aa070789SRoy Zang ***************************************************************************/ 1075aa070789SRoy Zang static int32_t 1076aa070789SRoy Zang e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw) 1077aa070789SRoy Zang { 10788712adfdSRojhalat Ibrahim #ifndef CONFIG_E1000_NO_NVM 1079aa070789SRoy Zang int32_t timeout; 1080aa070789SRoy Zang uint32_t swsm; 1081aa070789SRoy Zang 1082aa070789SRoy Zang DEBUGFUNC(); 1083aa070789SRoy Zang 1084aa070789SRoy Zang if (!hw->eeprom_semaphore_present) 1085aa070789SRoy Zang return E1000_SUCCESS; 1086aa070789SRoy Zang 1087aa070789SRoy Zang if (hw->mac_type == e1000_80003es2lan) { 1088aa070789SRoy Zang /* Get the SW semaphore. */ 1089aa070789SRoy Zang if (e1000_get_software_semaphore(hw) != E1000_SUCCESS) 1090aa070789SRoy Zang return -E1000_ERR_EEPROM; 1091aa070789SRoy Zang } 1092aa070789SRoy Zang 1093aa070789SRoy Zang /* Get the FW semaphore. */ 1094aa070789SRoy Zang timeout = hw->eeprom.word_size + 1; 1095aa070789SRoy Zang while (timeout) { 1096aa070789SRoy Zang swsm = E1000_READ_REG(hw, SWSM); 1097aa070789SRoy Zang swsm |= E1000_SWSM_SWESMBI; 1098aa070789SRoy Zang E1000_WRITE_REG(hw, SWSM, swsm); 1099aa070789SRoy Zang /* if we managed to set the bit we got the semaphore. */ 1100aa070789SRoy Zang swsm = E1000_READ_REG(hw, SWSM); 1101aa070789SRoy Zang if (swsm & E1000_SWSM_SWESMBI) 1102aa070789SRoy Zang break; 1103aa070789SRoy Zang 1104aa070789SRoy Zang udelay(50); 1105aa070789SRoy Zang timeout--; 1106aa070789SRoy Zang } 1107aa070789SRoy Zang 1108aa070789SRoy Zang if (!timeout) { 1109aa070789SRoy Zang /* Release semaphores */ 1110aa070789SRoy Zang e1000_put_hw_eeprom_semaphore(hw); 1111aa070789SRoy Zang DEBUGOUT("Driver can't access the Eeprom - " 1112aa070789SRoy Zang "SWESMBI bit is set.\n"); 1113aa070789SRoy Zang return -E1000_ERR_EEPROM; 1114aa070789SRoy Zang } 11158712adfdSRojhalat Ibrahim #endif 1116aa070789SRoy Zang return E1000_SUCCESS; 1117aa070789SRoy Zang } 1118aa070789SRoy Zang 11197e2d991dSTim Harvey /* Take ownership of the PHY */ 1120aa070789SRoy Zang static int32_t 1121aa070789SRoy Zang e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask) 1122aa070789SRoy Zang { 1123aa070789SRoy Zang uint32_t swfw_sync = 0; 1124aa070789SRoy Zang uint32_t swmask = mask; 1125aa070789SRoy Zang uint32_t fwmask = mask << 16; 1126aa070789SRoy Zang int32_t timeout = 200; 1127aa070789SRoy Zang 1128aa070789SRoy Zang DEBUGFUNC(); 1129aa070789SRoy Zang while (timeout) { 1130aa070789SRoy Zang if (e1000_get_hw_eeprom_semaphore(hw)) 1131aa070789SRoy Zang return -E1000_ERR_SWFW_SYNC; 1132aa070789SRoy Zang 1133aa070789SRoy Zang swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC); 113476f8cdb2SYork Sun if (!(swfw_sync & (fwmask | swmask))) 1135aa070789SRoy Zang break; 1136aa070789SRoy Zang 1137aa070789SRoy Zang /* firmware currently using resource (fwmask) */ 1138aa070789SRoy Zang /* or other software thread currently using resource (swmask) */ 1139aa070789SRoy Zang e1000_put_hw_eeprom_semaphore(hw); 1140aa070789SRoy Zang mdelay(5); 1141aa070789SRoy Zang timeout--; 1142aa070789SRoy Zang } 1143aa070789SRoy Zang 1144aa070789SRoy Zang if (!timeout) { 1145aa070789SRoy Zang DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n"); 1146aa070789SRoy Zang return -E1000_ERR_SWFW_SYNC; 1147aa070789SRoy Zang } 1148aa070789SRoy Zang 1149aa070789SRoy Zang swfw_sync |= swmask; 1150aa070789SRoy Zang E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync); 1151aa070789SRoy Zang 1152aa070789SRoy Zang e1000_put_hw_eeprom_semaphore(hw); 1153aa070789SRoy Zang return E1000_SUCCESS; 1154aa070789SRoy Zang } 1155aa070789SRoy Zang 11567e2d991dSTim Harvey static void e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask) 11577e2d991dSTim Harvey { 11587e2d991dSTim Harvey uint32_t swfw_sync = 0; 11597e2d991dSTim Harvey 11607e2d991dSTim Harvey DEBUGFUNC(); 11617e2d991dSTim Harvey while (e1000_get_hw_eeprom_semaphore(hw)) 11627e2d991dSTim Harvey ; /* Empty */ 11637e2d991dSTim Harvey 11647e2d991dSTim Harvey swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC); 11657e2d991dSTim Harvey swfw_sync &= ~mask; 11667e2d991dSTim Harvey E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync); 11677e2d991dSTim Harvey 11687e2d991dSTim Harvey e1000_put_hw_eeprom_semaphore(hw); 11697e2d991dSTim Harvey } 11707e2d991dSTim Harvey 1171472d5460SYork Sun static bool e1000_is_second_port(struct e1000_hw *hw) 1172987b43a1SKyle Moffett { 1173987b43a1SKyle Moffett switch (hw->mac_type) { 1174987b43a1SKyle Moffett case e1000_80003es2lan: 1175987b43a1SKyle Moffett case e1000_82546: 1176987b43a1SKyle Moffett case e1000_82571: 1177987b43a1SKyle Moffett if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1) 1178472d5460SYork Sun return true; 1179987b43a1SKyle Moffett /* Fallthrough */ 1180987b43a1SKyle Moffett default: 1181472d5460SYork Sun return false; 1182987b43a1SKyle Moffett } 1183987b43a1SKyle Moffett } 1184987b43a1SKyle Moffett 11858712adfdSRojhalat Ibrahim #ifndef CONFIG_E1000_NO_NVM 11862439e4bfSJean-Christophe PLAGNIOL-VILLARD /****************************************************************************** 11872439e4bfSJean-Christophe PLAGNIOL-VILLARD * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the 11882439e4bfSJean-Christophe PLAGNIOL-VILLARD * second function of dual function devices 11892439e4bfSJean-Christophe PLAGNIOL-VILLARD * 11902439e4bfSJean-Christophe PLAGNIOL-VILLARD * nic - Struct containing variables accessed by shared code 11912439e4bfSJean-Christophe PLAGNIOL-VILLARD *****************************************************************************/ 11922439e4bfSJean-Christophe PLAGNIOL-VILLARD static int 11935c5e707aSSimon Glass e1000_read_mac_addr(struct e1000_hw *hw, unsigned char enetaddr[6]) 11942439e4bfSJean-Christophe PLAGNIOL-VILLARD { 11952439e4bfSJean-Christophe PLAGNIOL-VILLARD uint16_t offset; 11962439e4bfSJean-Christophe PLAGNIOL-VILLARD uint16_t eeprom_data; 119795186063SMarek Vasut uint32_t reg_data = 0; 11982439e4bfSJean-Christophe PLAGNIOL-VILLARD int i; 11992439e4bfSJean-Christophe PLAGNIOL-VILLARD 12002439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGFUNC(); 12012439e4bfSJean-Christophe PLAGNIOL-VILLARD 12022439e4bfSJean-Christophe PLAGNIOL-VILLARD for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) { 12032439e4bfSJean-Christophe PLAGNIOL-VILLARD offset = i >> 1; 120495186063SMarek Vasut if (hw->mac_type == e1000_igb) { 120595186063SMarek Vasut /* i210 preloads MAC address into RAL/RAH registers */ 120695186063SMarek Vasut if (offset == 0) 120795186063SMarek Vasut reg_data = E1000_READ_REG_ARRAY(hw, RA, 0); 120895186063SMarek Vasut else if (offset == 1) 120995186063SMarek Vasut reg_data >>= 16; 121095186063SMarek Vasut else if (offset == 2) 121195186063SMarek Vasut reg_data = E1000_READ_REG_ARRAY(hw, RA, 1); 121295186063SMarek Vasut eeprom_data = reg_data & 0xffff; 121395186063SMarek Vasut } else if (e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) { 12142439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("EEPROM Read Error\n"); 12152439e4bfSJean-Christophe PLAGNIOL-VILLARD return -E1000_ERR_EEPROM; 12162439e4bfSJean-Christophe PLAGNIOL-VILLARD } 12175c5e707aSSimon Glass enetaddr[i] = eeprom_data & 0xff; 12185c5e707aSSimon Glass enetaddr[i + 1] = (eeprom_data >> 8) & 0xff; 12192439e4bfSJean-Christophe PLAGNIOL-VILLARD } 1220987b43a1SKyle Moffett 12212439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Invert the last bit if this is the second device */ 1222987b43a1SKyle Moffett if (e1000_is_second_port(hw)) 12235c5e707aSSimon Glass enetaddr[5] ^= 1; 1224987b43a1SKyle Moffett 12252439e4bfSJean-Christophe PLAGNIOL-VILLARD return 0; 12262439e4bfSJean-Christophe PLAGNIOL-VILLARD } 12278712adfdSRojhalat Ibrahim #endif 12282439e4bfSJean-Christophe PLAGNIOL-VILLARD 12292439e4bfSJean-Christophe PLAGNIOL-VILLARD /****************************************************************************** 12302439e4bfSJean-Christophe PLAGNIOL-VILLARD * Initializes receive address filters. 12312439e4bfSJean-Christophe PLAGNIOL-VILLARD * 12322439e4bfSJean-Christophe PLAGNIOL-VILLARD * hw - Struct containing variables accessed by shared code 12332439e4bfSJean-Christophe PLAGNIOL-VILLARD * 12342439e4bfSJean-Christophe PLAGNIOL-VILLARD * Places the MAC address in receive address register 0 and clears the rest 12352439e4bfSJean-Christophe PLAGNIOL-VILLARD * of the receive addresss registers. Clears the multicast table. Assumes 12362439e4bfSJean-Christophe PLAGNIOL-VILLARD * the receiver is in reset when the routine is called. 12372439e4bfSJean-Christophe PLAGNIOL-VILLARD *****************************************************************************/ 12382439e4bfSJean-Christophe PLAGNIOL-VILLARD static void 12395c5e707aSSimon Glass e1000_init_rx_addrs(struct e1000_hw *hw, unsigned char enetaddr[6]) 12402439e4bfSJean-Christophe PLAGNIOL-VILLARD { 12412439e4bfSJean-Christophe PLAGNIOL-VILLARD uint32_t i; 12422439e4bfSJean-Christophe PLAGNIOL-VILLARD uint32_t addr_low; 12432439e4bfSJean-Christophe PLAGNIOL-VILLARD uint32_t addr_high; 12442439e4bfSJean-Christophe PLAGNIOL-VILLARD 12452439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGFUNC(); 12462439e4bfSJean-Christophe PLAGNIOL-VILLARD 12472439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Setup the receive address. */ 12482439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("Programming MAC Address into RAR[0]\n"); 12495c5e707aSSimon Glass addr_low = (enetaddr[0] | 12505c5e707aSSimon Glass (enetaddr[1] << 8) | 12515c5e707aSSimon Glass (enetaddr[2] << 16) | (enetaddr[3] << 24)); 12522439e4bfSJean-Christophe PLAGNIOL-VILLARD 12535c5e707aSSimon Glass addr_high = (enetaddr[4] | (enetaddr[5] << 8) | E1000_RAH_AV); 12542439e4bfSJean-Christophe PLAGNIOL-VILLARD 12552439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG_ARRAY(hw, RA, 0, addr_low); 12562439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG_ARRAY(hw, RA, 1, addr_high); 12572439e4bfSJean-Christophe PLAGNIOL-VILLARD 12582439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Zero out the other 15 receive addresses. */ 12592439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("Clearing RAR[1-15]\n"); 12602439e4bfSJean-Christophe PLAGNIOL-VILLARD for (i = 1; i < E1000_RAR_ENTRIES; i++) { 12612439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0); 12622439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0); 12632439e4bfSJean-Christophe PLAGNIOL-VILLARD } 12642439e4bfSJean-Christophe PLAGNIOL-VILLARD } 12652439e4bfSJean-Christophe PLAGNIOL-VILLARD 12662439e4bfSJean-Christophe PLAGNIOL-VILLARD /****************************************************************************** 12672439e4bfSJean-Christophe PLAGNIOL-VILLARD * Clears the VLAN filer table 12682439e4bfSJean-Christophe PLAGNIOL-VILLARD * 12692439e4bfSJean-Christophe PLAGNIOL-VILLARD * hw - Struct containing variables accessed by shared code 12702439e4bfSJean-Christophe PLAGNIOL-VILLARD *****************************************************************************/ 12712439e4bfSJean-Christophe PLAGNIOL-VILLARD static void 12722439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_clear_vfta(struct e1000_hw *hw) 12732439e4bfSJean-Christophe PLAGNIOL-VILLARD { 12742439e4bfSJean-Christophe PLAGNIOL-VILLARD uint32_t offset; 12752439e4bfSJean-Christophe PLAGNIOL-VILLARD 12762439e4bfSJean-Christophe PLAGNIOL-VILLARD for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) 12772439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG_ARRAY(hw, VFTA, offset, 0); 12782439e4bfSJean-Christophe PLAGNIOL-VILLARD } 12792439e4bfSJean-Christophe PLAGNIOL-VILLARD 12802439e4bfSJean-Christophe PLAGNIOL-VILLARD /****************************************************************************** 12812439e4bfSJean-Christophe PLAGNIOL-VILLARD * Set the mac type member in the hw struct. 12822439e4bfSJean-Christophe PLAGNIOL-VILLARD * 12832439e4bfSJean-Christophe PLAGNIOL-VILLARD * hw - Struct containing variables accessed by shared code 12842439e4bfSJean-Christophe PLAGNIOL-VILLARD *****************************************************************************/ 1285aa070789SRoy Zang int32_t 12862439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_set_mac_type(struct e1000_hw *hw) 12872439e4bfSJean-Christophe PLAGNIOL-VILLARD { 12882439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGFUNC(); 12892439e4bfSJean-Christophe PLAGNIOL-VILLARD 12902439e4bfSJean-Christophe PLAGNIOL-VILLARD switch (hw->device_id) { 12912439e4bfSJean-Christophe PLAGNIOL-VILLARD case E1000_DEV_ID_82542: 12922439e4bfSJean-Christophe PLAGNIOL-VILLARD switch (hw->revision_id) { 12932439e4bfSJean-Christophe PLAGNIOL-VILLARD case E1000_82542_2_0_REV_ID: 12942439e4bfSJean-Christophe PLAGNIOL-VILLARD hw->mac_type = e1000_82542_rev2_0; 12952439e4bfSJean-Christophe PLAGNIOL-VILLARD break; 12962439e4bfSJean-Christophe PLAGNIOL-VILLARD case E1000_82542_2_1_REV_ID: 12972439e4bfSJean-Christophe PLAGNIOL-VILLARD hw->mac_type = e1000_82542_rev2_1; 12982439e4bfSJean-Christophe PLAGNIOL-VILLARD break; 12992439e4bfSJean-Christophe PLAGNIOL-VILLARD default: 13002439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Invalid 82542 revision ID */ 13012439e4bfSJean-Christophe PLAGNIOL-VILLARD return -E1000_ERR_MAC_TYPE; 13022439e4bfSJean-Christophe PLAGNIOL-VILLARD } 13032439e4bfSJean-Christophe PLAGNIOL-VILLARD break; 13042439e4bfSJean-Christophe PLAGNIOL-VILLARD case E1000_DEV_ID_82543GC_FIBER: 13052439e4bfSJean-Christophe PLAGNIOL-VILLARD case E1000_DEV_ID_82543GC_COPPER: 13062439e4bfSJean-Christophe PLAGNIOL-VILLARD hw->mac_type = e1000_82543; 13072439e4bfSJean-Christophe PLAGNIOL-VILLARD break; 13082439e4bfSJean-Christophe PLAGNIOL-VILLARD case E1000_DEV_ID_82544EI_COPPER: 13092439e4bfSJean-Christophe PLAGNIOL-VILLARD case E1000_DEV_ID_82544EI_FIBER: 13102439e4bfSJean-Christophe PLAGNIOL-VILLARD case E1000_DEV_ID_82544GC_COPPER: 13112439e4bfSJean-Christophe PLAGNIOL-VILLARD case E1000_DEV_ID_82544GC_LOM: 13122439e4bfSJean-Christophe PLAGNIOL-VILLARD hw->mac_type = e1000_82544; 13132439e4bfSJean-Christophe PLAGNIOL-VILLARD break; 13142439e4bfSJean-Christophe PLAGNIOL-VILLARD case E1000_DEV_ID_82540EM: 13152439e4bfSJean-Christophe PLAGNIOL-VILLARD case E1000_DEV_ID_82540EM_LOM: 1316aa070789SRoy Zang case E1000_DEV_ID_82540EP: 1317aa070789SRoy Zang case E1000_DEV_ID_82540EP_LOM: 1318aa070789SRoy Zang case E1000_DEV_ID_82540EP_LP: 13192439e4bfSJean-Christophe PLAGNIOL-VILLARD hw->mac_type = e1000_82540; 13202439e4bfSJean-Christophe PLAGNIOL-VILLARD break; 13212439e4bfSJean-Christophe PLAGNIOL-VILLARD case E1000_DEV_ID_82545EM_COPPER: 13222439e4bfSJean-Christophe PLAGNIOL-VILLARD case E1000_DEV_ID_82545EM_FIBER: 13232439e4bfSJean-Christophe PLAGNIOL-VILLARD hw->mac_type = e1000_82545; 13242439e4bfSJean-Christophe PLAGNIOL-VILLARD break; 1325aa070789SRoy Zang case E1000_DEV_ID_82545GM_COPPER: 1326aa070789SRoy Zang case E1000_DEV_ID_82545GM_FIBER: 1327aa070789SRoy Zang case E1000_DEV_ID_82545GM_SERDES: 1328aa070789SRoy Zang hw->mac_type = e1000_82545_rev_3; 1329aa070789SRoy Zang break; 13302439e4bfSJean-Christophe PLAGNIOL-VILLARD case E1000_DEV_ID_82546EB_COPPER: 13312439e4bfSJean-Christophe PLAGNIOL-VILLARD case E1000_DEV_ID_82546EB_FIBER: 1332aa070789SRoy Zang case E1000_DEV_ID_82546EB_QUAD_COPPER: 13332439e4bfSJean-Christophe PLAGNIOL-VILLARD hw->mac_type = e1000_82546; 13342439e4bfSJean-Christophe PLAGNIOL-VILLARD break; 1335aa070789SRoy Zang case E1000_DEV_ID_82546GB_COPPER: 1336aa070789SRoy Zang case E1000_DEV_ID_82546GB_FIBER: 1337aa070789SRoy Zang case E1000_DEV_ID_82546GB_SERDES: 1338aa070789SRoy Zang case E1000_DEV_ID_82546GB_PCIE: 1339aa070789SRoy Zang case E1000_DEV_ID_82546GB_QUAD_COPPER: 1340aa070789SRoy Zang case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3: 1341aa070789SRoy Zang hw->mac_type = e1000_82546_rev_3; 1342aa070789SRoy Zang break; 1343aa070789SRoy Zang case E1000_DEV_ID_82541EI: 1344aa070789SRoy Zang case E1000_DEV_ID_82541EI_MOBILE: 1345aa070789SRoy Zang case E1000_DEV_ID_82541ER_LOM: 1346aa070789SRoy Zang hw->mac_type = e1000_82541; 1347aa070789SRoy Zang break; 1348ac3315c2SAndre Schwarz case E1000_DEV_ID_82541ER: 1349aa070789SRoy Zang case E1000_DEV_ID_82541GI: 1350aa3b8bf9SWolfgang Grandegger case E1000_DEV_ID_82541GI_LF: 1351aa070789SRoy Zang case E1000_DEV_ID_82541GI_MOBILE: 1352ac3315c2SAndre Schwarz hw->mac_type = e1000_82541_rev_2; 1353ac3315c2SAndre Schwarz break; 1354aa070789SRoy Zang case E1000_DEV_ID_82547EI: 1355aa070789SRoy Zang case E1000_DEV_ID_82547EI_MOBILE: 1356aa070789SRoy Zang hw->mac_type = e1000_82547; 1357aa070789SRoy Zang break; 1358aa070789SRoy Zang case E1000_DEV_ID_82547GI: 1359aa070789SRoy Zang hw->mac_type = e1000_82547_rev_2; 1360aa070789SRoy Zang break; 1361aa070789SRoy Zang case E1000_DEV_ID_82571EB_COPPER: 1362aa070789SRoy Zang case E1000_DEV_ID_82571EB_FIBER: 1363aa070789SRoy Zang case E1000_DEV_ID_82571EB_SERDES: 1364aa070789SRoy Zang case E1000_DEV_ID_82571EB_SERDES_DUAL: 1365aa070789SRoy Zang case E1000_DEV_ID_82571EB_SERDES_QUAD: 1366aa070789SRoy Zang case E1000_DEV_ID_82571EB_QUAD_COPPER: 1367aa070789SRoy Zang case E1000_DEV_ID_82571PT_QUAD_COPPER: 1368aa070789SRoy Zang case E1000_DEV_ID_82571EB_QUAD_FIBER: 1369aa070789SRoy Zang case E1000_DEV_ID_82571EB_QUAD_COPPER_LOWPROFILE: 1370aa070789SRoy Zang hw->mac_type = e1000_82571; 1371aa070789SRoy Zang break; 1372aa070789SRoy Zang case E1000_DEV_ID_82572EI_COPPER: 1373aa070789SRoy Zang case E1000_DEV_ID_82572EI_FIBER: 1374aa070789SRoy Zang case E1000_DEV_ID_82572EI_SERDES: 1375aa070789SRoy Zang case E1000_DEV_ID_82572EI: 1376aa070789SRoy Zang hw->mac_type = e1000_82572; 1377aa070789SRoy Zang break; 1378aa070789SRoy Zang case E1000_DEV_ID_82573E: 1379aa070789SRoy Zang case E1000_DEV_ID_82573E_IAMT: 1380aa070789SRoy Zang case E1000_DEV_ID_82573L: 1381aa070789SRoy Zang hw->mac_type = e1000_82573; 1382aa070789SRoy Zang break; 13832c2668f9SRoy Zang case E1000_DEV_ID_82574L: 13842c2668f9SRoy Zang hw->mac_type = e1000_82574; 13852c2668f9SRoy Zang break; 1386aa070789SRoy Zang case E1000_DEV_ID_80003ES2LAN_COPPER_SPT: 1387aa070789SRoy Zang case E1000_DEV_ID_80003ES2LAN_SERDES_SPT: 1388aa070789SRoy Zang case E1000_DEV_ID_80003ES2LAN_COPPER_DPT: 1389aa070789SRoy Zang case E1000_DEV_ID_80003ES2LAN_SERDES_DPT: 1390aa070789SRoy Zang hw->mac_type = e1000_80003es2lan; 1391aa070789SRoy Zang break; 1392aa070789SRoy Zang case E1000_DEV_ID_ICH8_IGP_M_AMT: 1393aa070789SRoy Zang case E1000_DEV_ID_ICH8_IGP_AMT: 1394aa070789SRoy Zang case E1000_DEV_ID_ICH8_IGP_C: 1395aa070789SRoy Zang case E1000_DEV_ID_ICH8_IFE: 1396aa070789SRoy Zang case E1000_DEV_ID_ICH8_IFE_GT: 1397aa070789SRoy Zang case E1000_DEV_ID_ICH8_IFE_G: 1398aa070789SRoy Zang case E1000_DEV_ID_ICH8_IGP_M: 1399aa070789SRoy Zang hw->mac_type = e1000_ich8lan; 1400aa070789SRoy Zang break; 14016c499abeSMarcel Ziswiler case PCI_DEVICE_ID_INTEL_I210_UNPROGRAMMED: 14026c499abeSMarcel Ziswiler case PCI_DEVICE_ID_INTEL_I211_UNPROGRAMMED: 140395186063SMarek Vasut case PCI_DEVICE_ID_INTEL_I210_COPPER: 14046c499abeSMarcel Ziswiler case PCI_DEVICE_ID_INTEL_I211_COPPER: 140595186063SMarek Vasut case PCI_DEVICE_ID_INTEL_I210_COPPER_FLASHLESS: 140695186063SMarek Vasut case PCI_DEVICE_ID_INTEL_I210_SERDES: 140795186063SMarek Vasut case PCI_DEVICE_ID_INTEL_I210_SERDES_FLASHLESS: 140895186063SMarek Vasut case PCI_DEVICE_ID_INTEL_I210_1000BASEKX: 140995186063SMarek Vasut hw->mac_type = e1000_igb; 141095186063SMarek Vasut break; 14112439e4bfSJean-Christophe PLAGNIOL-VILLARD default: 14122439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Should never have loaded on this device */ 14132439e4bfSJean-Christophe PLAGNIOL-VILLARD return -E1000_ERR_MAC_TYPE; 14142439e4bfSJean-Christophe PLAGNIOL-VILLARD } 14152439e4bfSJean-Christophe PLAGNIOL-VILLARD return E1000_SUCCESS; 14162439e4bfSJean-Christophe PLAGNIOL-VILLARD } 14172439e4bfSJean-Christophe PLAGNIOL-VILLARD 14182439e4bfSJean-Christophe PLAGNIOL-VILLARD /****************************************************************************** 14192439e4bfSJean-Christophe PLAGNIOL-VILLARD * Reset the transmit and receive units; mask and clear all interrupts. 14202439e4bfSJean-Christophe PLAGNIOL-VILLARD * 14212439e4bfSJean-Christophe PLAGNIOL-VILLARD * hw - Struct containing variables accessed by shared code 14222439e4bfSJean-Christophe PLAGNIOL-VILLARD *****************************************************************************/ 14232439e4bfSJean-Christophe PLAGNIOL-VILLARD void 14242439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_reset_hw(struct e1000_hw *hw) 14252439e4bfSJean-Christophe PLAGNIOL-VILLARD { 14262439e4bfSJean-Christophe PLAGNIOL-VILLARD uint32_t ctrl; 14272439e4bfSJean-Christophe PLAGNIOL-VILLARD uint32_t ctrl_ext; 14282439e4bfSJean-Christophe PLAGNIOL-VILLARD uint32_t manc; 14299ea005fbSRoy Zang uint32_t pba = 0; 143095186063SMarek Vasut uint32_t reg; 14312439e4bfSJean-Christophe PLAGNIOL-VILLARD 14322439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGFUNC(); 14332439e4bfSJean-Christophe PLAGNIOL-VILLARD 14349ea005fbSRoy Zang /* get the correct pba value for both PCI and PCIe*/ 14359ea005fbSRoy Zang if (hw->mac_type < e1000_82571) 14369ea005fbSRoy Zang pba = E1000_DEFAULT_PCI_PBA; 14379ea005fbSRoy Zang else 14389ea005fbSRoy Zang pba = E1000_DEFAULT_PCIE_PBA; 14399ea005fbSRoy Zang 14402439e4bfSJean-Christophe PLAGNIOL-VILLARD /* For 82542 (rev 2.0), disable MWI before issuing a device reset */ 14412439e4bfSJean-Christophe PLAGNIOL-VILLARD if (hw->mac_type == e1000_82542_rev2_0) { 14422439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("Disabling MWI on 82542 rev 2.0\n"); 14432439e4bfSJean-Christophe PLAGNIOL-VILLARD pci_write_config_word(hw->pdev, PCI_COMMAND, 1444aa070789SRoy Zang hw->pci_cmd_word & ~PCI_COMMAND_INVALIDATE); 14452439e4bfSJean-Christophe PLAGNIOL-VILLARD } 14462439e4bfSJean-Christophe PLAGNIOL-VILLARD 14472439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Clear interrupt mask to stop board from generating interrupts */ 14482439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("Masking off all interrupts\n"); 144995186063SMarek Vasut if (hw->mac_type == e1000_igb) 145095186063SMarek Vasut E1000_WRITE_REG(hw, I210_IAM, 0); 14512439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, IMC, 0xffffffff); 14522439e4bfSJean-Christophe PLAGNIOL-VILLARD 14532439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Disable the Transmit and Receive units. Then delay to allow 14542439e4bfSJean-Christophe PLAGNIOL-VILLARD * any pending transactions to complete before we hit the MAC with 14552439e4bfSJean-Christophe PLAGNIOL-VILLARD * the global reset. 14562439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 14572439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, RCTL, 0); 14582439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP); 14592439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_FLUSH(hw); 14602439e4bfSJean-Christophe PLAGNIOL-VILLARD 14612439e4bfSJean-Christophe PLAGNIOL-VILLARD /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */ 1462472d5460SYork Sun hw->tbi_compatibility_on = false; 14632439e4bfSJean-Christophe PLAGNIOL-VILLARD 14642439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Delay to allow any outstanding PCI transactions to complete before 14652439e4bfSJean-Christophe PLAGNIOL-VILLARD * resetting the device 14662439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 14672439e4bfSJean-Christophe PLAGNIOL-VILLARD mdelay(10); 14682439e4bfSJean-Christophe PLAGNIOL-VILLARD 14692439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Issue a global reset to the MAC. This will reset the chip's 14702439e4bfSJean-Christophe PLAGNIOL-VILLARD * transmit, receive, DMA, and link units. It will not effect 14712439e4bfSJean-Christophe PLAGNIOL-VILLARD * the current PCI configuration. The global reset bit is self- 14722439e4bfSJean-Christophe PLAGNIOL-VILLARD * clearing, and should clear within a microsecond. 14732439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 14742439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("Issuing a global reset to MAC\n"); 14752439e4bfSJean-Christophe PLAGNIOL-VILLARD ctrl = E1000_READ_REG(hw, CTRL); 14762439e4bfSJean-Christophe PLAGNIOL-VILLARD 14772439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST)); 14782439e4bfSJean-Christophe PLAGNIOL-VILLARD 14792439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Force a reload from the EEPROM if necessary */ 148095186063SMarek Vasut if (hw->mac_type == e1000_igb) { 148195186063SMarek Vasut mdelay(20); 148295186063SMarek Vasut reg = E1000_READ_REG(hw, STATUS); 148395186063SMarek Vasut if (reg & E1000_STATUS_PF_RST_DONE) 148495186063SMarek Vasut DEBUGOUT("PF OK\n"); 148595186063SMarek Vasut reg = E1000_READ_REG(hw, I210_EECD); 148695186063SMarek Vasut if (reg & E1000_EECD_AUTO_RD) 148795186063SMarek Vasut DEBUGOUT("EEC OK\n"); 148895186063SMarek Vasut } else if (hw->mac_type < e1000_82540) { 14892439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Wait for reset to complete */ 14902439e4bfSJean-Christophe PLAGNIOL-VILLARD udelay(10); 14912439e4bfSJean-Christophe PLAGNIOL-VILLARD ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 14922439e4bfSJean-Christophe PLAGNIOL-VILLARD ctrl_ext |= E1000_CTRL_EXT_EE_RST; 14932439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 14942439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_FLUSH(hw); 14952439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Wait for EEPROM reload */ 14962439e4bfSJean-Christophe PLAGNIOL-VILLARD mdelay(2); 14972439e4bfSJean-Christophe PLAGNIOL-VILLARD } else { 14982439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Wait for EEPROM reload (it happens automatically) */ 14992439e4bfSJean-Christophe PLAGNIOL-VILLARD mdelay(4); 15002439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Dissable HW ARPs on ASF enabled adapters */ 15012439e4bfSJean-Christophe PLAGNIOL-VILLARD manc = E1000_READ_REG(hw, MANC); 15022439e4bfSJean-Christophe PLAGNIOL-VILLARD manc &= ~(E1000_MANC_ARP_EN); 15032439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, MANC, manc); 15042439e4bfSJean-Christophe PLAGNIOL-VILLARD } 15052439e4bfSJean-Christophe PLAGNIOL-VILLARD 15062439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Clear interrupt mask to stop board from generating interrupts */ 15072439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("Masking off all interrupts\n"); 150895186063SMarek Vasut if (hw->mac_type == e1000_igb) 150995186063SMarek Vasut E1000_WRITE_REG(hw, I210_IAM, 0); 15102439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, IMC, 0xffffffff); 15112439e4bfSJean-Christophe PLAGNIOL-VILLARD 15122439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Clear any pending interrupt events. */ 151356b13b1eSZang Roy-R61911 E1000_READ_REG(hw, ICR); 15142439e4bfSJean-Christophe PLAGNIOL-VILLARD 15152439e4bfSJean-Christophe PLAGNIOL-VILLARD /* If MWI was previously enabled, reenable it. */ 15162439e4bfSJean-Christophe PLAGNIOL-VILLARD if (hw->mac_type == e1000_82542_rev2_0) { 15172439e4bfSJean-Christophe PLAGNIOL-VILLARD pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word); 15182439e4bfSJean-Christophe PLAGNIOL-VILLARD } 151995186063SMarek Vasut if (hw->mac_type != e1000_igb) 15209ea005fbSRoy Zang E1000_WRITE_REG(hw, PBA, pba); 1521aa070789SRoy Zang } 1522aa070789SRoy Zang 1523aa070789SRoy Zang /****************************************************************************** 1524aa070789SRoy Zang * 1525aa070789SRoy Zang * Initialize a number of hardware-dependent bits 1526aa070789SRoy Zang * 1527aa070789SRoy Zang * hw: Struct containing variables accessed by shared code 1528aa070789SRoy Zang * 1529aa070789SRoy Zang * This function contains hardware limitation workarounds for PCI-E adapters 1530aa070789SRoy Zang * 1531aa070789SRoy Zang *****************************************************************************/ 1532aa070789SRoy Zang static void 1533aa070789SRoy Zang e1000_initialize_hardware_bits(struct e1000_hw *hw) 1534aa070789SRoy Zang { 1535aa070789SRoy Zang if ((hw->mac_type >= e1000_82571) && 1536aa070789SRoy Zang (!hw->initialize_hw_bits_disable)) { 1537aa070789SRoy Zang /* Settings common to all PCI-express silicon */ 1538aa070789SRoy Zang uint32_t reg_ctrl, reg_ctrl_ext; 1539aa070789SRoy Zang uint32_t reg_tarc0, reg_tarc1; 1540aa070789SRoy Zang uint32_t reg_tctl; 1541aa070789SRoy Zang uint32_t reg_txdctl, reg_txdctl1; 1542aa070789SRoy Zang 1543aa070789SRoy Zang /* link autonegotiation/sync workarounds */ 1544aa070789SRoy Zang reg_tarc0 = E1000_READ_REG(hw, TARC0); 1545aa070789SRoy Zang reg_tarc0 &= ~((1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)); 1546aa070789SRoy Zang 1547aa070789SRoy Zang /* Enable not-done TX descriptor counting */ 1548aa070789SRoy Zang reg_txdctl = E1000_READ_REG(hw, TXDCTL); 1549aa070789SRoy Zang reg_txdctl |= E1000_TXDCTL_COUNT_DESC; 1550aa070789SRoy Zang E1000_WRITE_REG(hw, TXDCTL, reg_txdctl); 1551aa070789SRoy Zang 1552aa070789SRoy Zang reg_txdctl1 = E1000_READ_REG(hw, TXDCTL1); 1553aa070789SRoy Zang reg_txdctl1 |= E1000_TXDCTL_COUNT_DESC; 1554aa070789SRoy Zang E1000_WRITE_REG(hw, TXDCTL1, reg_txdctl1); 1555aa070789SRoy Zang 155695186063SMarek Vasut /* IGB is cool */ 155795186063SMarek Vasut if (hw->mac_type == e1000_igb) 155895186063SMarek Vasut return; 155995186063SMarek Vasut 1560aa070789SRoy Zang switch (hw->mac_type) { 1561aa070789SRoy Zang case e1000_82571: 1562aa070789SRoy Zang case e1000_82572: 1563aa070789SRoy Zang /* Clear PHY TX compatible mode bits */ 1564aa070789SRoy Zang reg_tarc1 = E1000_READ_REG(hw, TARC1); 1565aa070789SRoy Zang reg_tarc1 &= ~((1 << 30)|(1 << 29)); 1566aa070789SRoy Zang 1567aa070789SRoy Zang /* link autonegotiation/sync workarounds */ 1568aa070789SRoy Zang reg_tarc0 |= ((1 << 26)|(1 << 25)|(1 << 24)|(1 << 23)); 1569aa070789SRoy Zang 1570aa070789SRoy Zang /* TX ring control fixes */ 1571aa070789SRoy Zang reg_tarc1 |= ((1 << 26)|(1 << 25)|(1 << 24)); 1572aa070789SRoy Zang 1573aa070789SRoy Zang /* Multiple read bit is reversed polarity */ 1574aa070789SRoy Zang reg_tctl = E1000_READ_REG(hw, TCTL); 1575aa070789SRoy Zang if (reg_tctl & E1000_TCTL_MULR) 1576aa070789SRoy Zang reg_tarc1 &= ~(1 << 28); 1577aa070789SRoy Zang else 1578aa070789SRoy Zang reg_tarc1 |= (1 << 28); 1579aa070789SRoy Zang 1580aa070789SRoy Zang E1000_WRITE_REG(hw, TARC1, reg_tarc1); 1581aa070789SRoy Zang break; 1582aa070789SRoy Zang case e1000_82573: 15832c2668f9SRoy Zang case e1000_82574: 1584aa070789SRoy Zang reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 1585aa070789SRoy Zang reg_ctrl_ext &= ~(1 << 23); 1586aa070789SRoy Zang reg_ctrl_ext |= (1 << 22); 1587aa070789SRoy Zang 1588aa070789SRoy Zang /* TX byte count fix */ 1589aa070789SRoy Zang reg_ctrl = E1000_READ_REG(hw, CTRL); 1590aa070789SRoy Zang reg_ctrl &= ~(1 << 29); 1591aa070789SRoy Zang 1592aa070789SRoy Zang E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext); 1593aa070789SRoy Zang E1000_WRITE_REG(hw, CTRL, reg_ctrl); 1594aa070789SRoy Zang break; 1595aa070789SRoy Zang case e1000_80003es2lan: 1596aa070789SRoy Zang /* improve small packet performace for fiber/serdes */ 1597aa070789SRoy Zang if ((hw->media_type == e1000_media_type_fiber) 1598aa070789SRoy Zang || (hw->media_type == 1599aa070789SRoy Zang e1000_media_type_internal_serdes)) { 1600aa070789SRoy Zang reg_tarc0 &= ~(1 << 20); 1601aa070789SRoy Zang } 1602aa070789SRoy Zang 1603aa070789SRoy Zang /* Multiple read bit is reversed polarity */ 1604aa070789SRoy Zang reg_tctl = E1000_READ_REG(hw, TCTL); 1605aa070789SRoy Zang reg_tarc1 = E1000_READ_REG(hw, TARC1); 1606aa070789SRoy Zang if (reg_tctl & E1000_TCTL_MULR) 1607aa070789SRoy Zang reg_tarc1 &= ~(1 << 28); 1608aa070789SRoy Zang else 1609aa070789SRoy Zang reg_tarc1 |= (1 << 28); 1610aa070789SRoy Zang 1611aa070789SRoy Zang E1000_WRITE_REG(hw, TARC1, reg_tarc1); 1612aa070789SRoy Zang break; 1613aa070789SRoy Zang case e1000_ich8lan: 1614aa070789SRoy Zang /* Reduce concurrent DMA requests to 3 from 4 */ 1615aa070789SRoy Zang if ((hw->revision_id < 3) || 1616aa070789SRoy Zang ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) && 1617aa070789SRoy Zang (hw->device_id != E1000_DEV_ID_ICH8_IGP_M))) 1618aa070789SRoy Zang reg_tarc0 |= ((1 << 29)|(1 << 28)); 1619aa070789SRoy Zang 1620aa070789SRoy Zang reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 1621aa070789SRoy Zang reg_ctrl_ext |= (1 << 22); 1622aa070789SRoy Zang E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext); 1623aa070789SRoy Zang 1624aa070789SRoy Zang /* workaround TX hang with TSO=on */ 1625aa070789SRoy Zang reg_tarc0 |= ((1 << 27)|(1 << 26)|(1 << 24)|(1 << 23)); 1626aa070789SRoy Zang 1627aa070789SRoy Zang /* Multiple read bit is reversed polarity */ 1628aa070789SRoy Zang reg_tctl = E1000_READ_REG(hw, TCTL); 1629aa070789SRoy Zang reg_tarc1 = E1000_READ_REG(hw, TARC1); 1630aa070789SRoy Zang if (reg_tctl & E1000_TCTL_MULR) 1631aa070789SRoy Zang reg_tarc1 &= ~(1 << 28); 1632aa070789SRoy Zang else 1633aa070789SRoy Zang reg_tarc1 |= (1 << 28); 1634aa070789SRoy Zang 1635aa070789SRoy Zang /* workaround TX hang with TSO=on */ 1636aa070789SRoy Zang reg_tarc1 |= ((1 << 30)|(1 << 26)|(1 << 24)); 1637aa070789SRoy Zang 1638aa070789SRoy Zang E1000_WRITE_REG(hw, TARC1, reg_tarc1); 1639aa070789SRoy Zang break; 1640aa070789SRoy Zang default: 1641aa070789SRoy Zang break; 1642aa070789SRoy Zang } 1643aa070789SRoy Zang 1644aa070789SRoy Zang E1000_WRITE_REG(hw, TARC0, reg_tarc0); 1645aa070789SRoy Zang } 16462439e4bfSJean-Christophe PLAGNIOL-VILLARD } 16472439e4bfSJean-Christophe PLAGNIOL-VILLARD 16482439e4bfSJean-Christophe PLAGNIOL-VILLARD /****************************************************************************** 16492439e4bfSJean-Christophe PLAGNIOL-VILLARD * Performs basic configuration of the adapter. 16502439e4bfSJean-Christophe PLAGNIOL-VILLARD * 16512439e4bfSJean-Christophe PLAGNIOL-VILLARD * hw - Struct containing variables accessed by shared code 16522439e4bfSJean-Christophe PLAGNIOL-VILLARD * 16532439e4bfSJean-Christophe PLAGNIOL-VILLARD * Assumes that the controller has previously been reset and is in a 16542439e4bfSJean-Christophe PLAGNIOL-VILLARD * post-reset uninitialized state. Initializes the receive address registers, 16552439e4bfSJean-Christophe PLAGNIOL-VILLARD * multicast table, and VLAN filter table. Calls routines to setup link 16562439e4bfSJean-Christophe PLAGNIOL-VILLARD * configuration and flow control settings. Clears all on-chip counters. Leaves 16572439e4bfSJean-Christophe PLAGNIOL-VILLARD * the transmit and receive units disabled and uninitialized. 16582439e4bfSJean-Christophe PLAGNIOL-VILLARD *****************************************************************************/ 16592439e4bfSJean-Christophe PLAGNIOL-VILLARD static int 16605c5e707aSSimon Glass e1000_init_hw(struct e1000_hw *hw, unsigned char enetaddr[6]) 16612439e4bfSJean-Christophe PLAGNIOL-VILLARD { 1662aa070789SRoy Zang uint32_t ctrl; 16632439e4bfSJean-Christophe PLAGNIOL-VILLARD uint32_t i; 16642439e4bfSJean-Christophe PLAGNIOL-VILLARD int32_t ret_val; 16652439e4bfSJean-Christophe PLAGNIOL-VILLARD uint16_t pcix_cmd_word; 16662439e4bfSJean-Christophe PLAGNIOL-VILLARD uint16_t pcix_stat_hi_word; 16672439e4bfSJean-Christophe PLAGNIOL-VILLARD uint16_t cmd_mmrbc; 16682439e4bfSJean-Christophe PLAGNIOL-VILLARD uint16_t stat_mmrbc; 1669aa070789SRoy Zang uint32_t mta_size; 1670aa070789SRoy Zang uint32_t reg_data; 1671aa070789SRoy Zang uint32_t ctrl_ext; 16722439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGFUNC(); 1673aa070789SRoy Zang /* force full DMA clock frequency for 10/100 on ICH8 A0-B0 */ 1674aa070789SRoy Zang if ((hw->mac_type == e1000_ich8lan) && 1675aa070789SRoy Zang ((hw->revision_id < 3) || 1676aa070789SRoy Zang ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) && 1677aa070789SRoy Zang (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))) { 1678aa070789SRoy Zang reg_data = E1000_READ_REG(hw, STATUS); 1679aa070789SRoy Zang reg_data &= ~0x80000000; 1680aa070789SRoy Zang E1000_WRITE_REG(hw, STATUS, reg_data); 16812439e4bfSJean-Christophe PLAGNIOL-VILLARD } 1682aa070789SRoy Zang /* Do not need initialize Identification LED */ 16832439e4bfSJean-Christophe PLAGNIOL-VILLARD 1684aa070789SRoy Zang /* Set the media type and TBI compatibility */ 1685aa070789SRoy Zang e1000_set_media_type(hw); 1686aa070789SRoy Zang 1687aa070789SRoy Zang /* Must be called after e1000_set_media_type 1688aa070789SRoy Zang * because media_type is used */ 1689aa070789SRoy Zang e1000_initialize_hardware_bits(hw); 16902439e4bfSJean-Christophe PLAGNIOL-VILLARD 16912439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Disabling VLAN filtering. */ 16922439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("Initializing the IEEE VLAN\n"); 1693aa070789SRoy Zang /* VET hardcoded to standard value and VFTA removed in ICH8 LAN */ 1694aa070789SRoy Zang if (hw->mac_type != e1000_ich8lan) { 1695aa070789SRoy Zang if (hw->mac_type < e1000_82545_rev_3) 16962439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, VET, 0); 16972439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_clear_vfta(hw); 1698aa070789SRoy Zang } 16992439e4bfSJean-Christophe PLAGNIOL-VILLARD 17002439e4bfSJean-Christophe PLAGNIOL-VILLARD /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */ 17012439e4bfSJean-Christophe PLAGNIOL-VILLARD if (hw->mac_type == e1000_82542_rev2_0) { 17022439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("Disabling MWI on 82542 rev 2.0\n"); 17032439e4bfSJean-Christophe PLAGNIOL-VILLARD pci_write_config_word(hw->pdev, PCI_COMMAND, 17042439e4bfSJean-Christophe PLAGNIOL-VILLARD hw-> 17052439e4bfSJean-Christophe PLAGNIOL-VILLARD pci_cmd_word & ~PCI_COMMAND_INVALIDATE); 17062439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST); 17072439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_FLUSH(hw); 17082439e4bfSJean-Christophe PLAGNIOL-VILLARD mdelay(5); 17092439e4bfSJean-Christophe PLAGNIOL-VILLARD } 17102439e4bfSJean-Christophe PLAGNIOL-VILLARD 17112439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Setup the receive address. This involves initializing all of the Receive 17122439e4bfSJean-Christophe PLAGNIOL-VILLARD * Address Registers (RARs 0 - 15). 17132439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 17145c5e707aSSimon Glass e1000_init_rx_addrs(hw, enetaddr); 17152439e4bfSJean-Christophe PLAGNIOL-VILLARD 17162439e4bfSJean-Christophe PLAGNIOL-VILLARD /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */ 17172439e4bfSJean-Christophe PLAGNIOL-VILLARD if (hw->mac_type == e1000_82542_rev2_0) { 17182439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, RCTL, 0); 17192439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_FLUSH(hw); 17202439e4bfSJean-Christophe PLAGNIOL-VILLARD mdelay(1); 17212439e4bfSJean-Christophe PLAGNIOL-VILLARD pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word); 17222439e4bfSJean-Christophe PLAGNIOL-VILLARD } 17232439e4bfSJean-Christophe PLAGNIOL-VILLARD 17242439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Zero out the Multicast HASH table */ 17252439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("Zeroing the MTA\n"); 1726aa070789SRoy Zang mta_size = E1000_MC_TBL_SIZE; 1727aa070789SRoy Zang if (hw->mac_type == e1000_ich8lan) 1728aa070789SRoy Zang mta_size = E1000_MC_TBL_SIZE_ICH8LAN; 1729aa070789SRoy Zang for (i = 0; i < mta_size; i++) { 17302439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG_ARRAY(hw, MTA, i, 0); 1731aa070789SRoy Zang /* use write flush to prevent Memory Write Block (MWB) from 1732aa070789SRoy Zang * occuring when accessing our register space */ 1733aa070789SRoy Zang E1000_WRITE_FLUSH(hw); 1734aa070789SRoy Zang } 17352439e4bfSJean-Christophe PLAGNIOL-VILLARD #if 0 17362439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Set the PCI priority bit correctly in the CTRL register. This 17372439e4bfSJean-Christophe PLAGNIOL-VILLARD * determines if the adapter gives priority to receives, or if it 1738aa070789SRoy Zang * gives equal priority to transmits and receives. Valid only on 1739aa070789SRoy Zang * 82542 and 82543 silicon. 17402439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 1741aa070789SRoy Zang if (hw->dma_fairness && hw->mac_type <= e1000_82543) { 17422439e4bfSJean-Christophe PLAGNIOL-VILLARD ctrl = E1000_READ_REG(hw, CTRL); 17432439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR); 17442439e4bfSJean-Christophe PLAGNIOL-VILLARD } 17452439e4bfSJean-Christophe PLAGNIOL-VILLARD #endif 1746aa070789SRoy Zang switch (hw->mac_type) { 1747aa070789SRoy Zang case e1000_82545_rev_3: 1748aa070789SRoy Zang case e1000_82546_rev_3: 174995186063SMarek Vasut case e1000_igb: 1750aa070789SRoy Zang break; 1751aa070789SRoy Zang default: 17522439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */ 1753aa070789SRoy Zang if (hw->bus_type == e1000_bus_type_pcix) { 17542439e4bfSJean-Christophe PLAGNIOL-VILLARD pci_read_config_word(hw->pdev, PCIX_COMMAND_REGISTER, 17552439e4bfSJean-Christophe PLAGNIOL-VILLARD &pcix_cmd_word); 17562439e4bfSJean-Christophe PLAGNIOL-VILLARD pci_read_config_word(hw->pdev, PCIX_STATUS_REGISTER_HI, 17572439e4bfSJean-Christophe PLAGNIOL-VILLARD &pcix_stat_hi_word); 17582439e4bfSJean-Christophe PLAGNIOL-VILLARD cmd_mmrbc = 17592439e4bfSJean-Christophe PLAGNIOL-VILLARD (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) >> 17602439e4bfSJean-Christophe PLAGNIOL-VILLARD PCIX_COMMAND_MMRBC_SHIFT; 17612439e4bfSJean-Christophe PLAGNIOL-VILLARD stat_mmrbc = 17622439e4bfSJean-Christophe PLAGNIOL-VILLARD (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >> 17632439e4bfSJean-Christophe PLAGNIOL-VILLARD PCIX_STATUS_HI_MMRBC_SHIFT; 17642439e4bfSJean-Christophe PLAGNIOL-VILLARD if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K) 17652439e4bfSJean-Christophe PLAGNIOL-VILLARD stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K; 17662439e4bfSJean-Christophe PLAGNIOL-VILLARD if (cmd_mmrbc > stat_mmrbc) { 17672439e4bfSJean-Christophe PLAGNIOL-VILLARD pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK; 17682439e4bfSJean-Christophe PLAGNIOL-VILLARD pcix_cmd_word |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT; 17692439e4bfSJean-Christophe PLAGNIOL-VILLARD pci_write_config_word(hw->pdev, PCIX_COMMAND_REGISTER, 17702439e4bfSJean-Christophe PLAGNIOL-VILLARD pcix_cmd_word); 17712439e4bfSJean-Christophe PLAGNIOL-VILLARD } 17722439e4bfSJean-Christophe PLAGNIOL-VILLARD } 1773aa070789SRoy Zang break; 1774aa070789SRoy Zang } 1775aa070789SRoy Zang 1776aa070789SRoy Zang /* More time needed for PHY to initialize */ 1777aa070789SRoy Zang if (hw->mac_type == e1000_ich8lan) 1778aa070789SRoy Zang mdelay(15); 177995186063SMarek Vasut if (hw->mac_type == e1000_igb) 178095186063SMarek Vasut mdelay(15); 17812439e4bfSJean-Christophe PLAGNIOL-VILLARD 17822439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Call a subroutine to configure the link and setup flow control. */ 17835c5e707aSSimon Glass ret_val = e1000_setup_link(hw); 17842439e4bfSJean-Christophe PLAGNIOL-VILLARD 17852439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Set the transmit descriptor write-back policy */ 17862439e4bfSJean-Christophe PLAGNIOL-VILLARD if (hw->mac_type > e1000_82544) { 17872439e4bfSJean-Christophe PLAGNIOL-VILLARD ctrl = E1000_READ_REG(hw, TXDCTL); 17882439e4bfSJean-Christophe PLAGNIOL-VILLARD ctrl = 17892439e4bfSJean-Christophe PLAGNIOL-VILLARD (ctrl & ~E1000_TXDCTL_WTHRESH) | 17902439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_TXDCTL_FULL_TX_DESC_WB; 17912439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, TXDCTL, ctrl); 17922439e4bfSJean-Christophe PLAGNIOL-VILLARD } 1793aa070789SRoy Zang 1794776e66e8SRuchika Gupta /* Set the receive descriptor write back policy */ 1795776e66e8SRuchika Gupta if (hw->mac_type >= e1000_82571) { 1796776e66e8SRuchika Gupta ctrl = E1000_READ_REG(hw, RXDCTL); 1797776e66e8SRuchika Gupta ctrl = 1798776e66e8SRuchika Gupta (ctrl & ~E1000_RXDCTL_WTHRESH) | 1799776e66e8SRuchika Gupta E1000_RXDCTL_FULL_RX_DESC_WB; 1800776e66e8SRuchika Gupta E1000_WRITE_REG(hw, RXDCTL, ctrl); 1801776e66e8SRuchika Gupta } 1802776e66e8SRuchika Gupta 1803aa070789SRoy Zang switch (hw->mac_type) { 1804aa070789SRoy Zang default: 1805aa070789SRoy Zang break; 1806aa070789SRoy Zang case e1000_80003es2lan: 1807aa070789SRoy Zang /* Enable retransmit on late collisions */ 1808aa070789SRoy Zang reg_data = E1000_READ_REG(hw, TCTL); 1809aa070789SRoy Zang reg_data |= E1000_TCTL_RTLC; 1810aa070789SRoy Zang E1000_WRITE_REG(hw, TCTL, reg_data); 1811aa070789SRoy Zang 1812aa070789SRoy Zang /* Configure Gigabit Carry Extend Padding */ 1813aa070789SRoy Zang reg_data = E1000_READ_REG(hw, TCTL_EXT); 1814aa070789SRoy Zang reg_data &= ~E1000_TCTL_EXT_GCEX_MASK; 1815aa070789SRoy Zang reg_data |= DEFAULT_80003ES2LAN_TCTL_EXT_GCEX; 1816aa070789SRoy Zang E1000_WRITE_REG(hw, TCTL_EXT, reg_data); 1817aa070789SRoy Zang 1818aa070789SRoy Zang /* Configure Transmit Inter-Packet Gap */ 1819aa070789SRoy Zang reg_data = E1000_READ_REG(hw, TIPG); 1820aa070789SRoy Zang reg_data &= ~E1000_TIPG_IPGT_MASK; 1821aa070789SRoy Zang reg_data |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000; 1822aa070789SRoy Zang E1000_WRITE_REG(hw, TIPG, reg_data); 1823aa070789SRoy Zang 1824aa070789SRoy Zang reg_data = E1000_READ_REG_ARRAY(hw, FFLT, 0x0001); 1825aa070789SRoy Zang reg_data &= ~0x00100000; 1826aa070789SRoy Zang E1000_WRITE_REG_ARRAY(hw, FFLT, 0x0001, reg_data); 1827aa070789SRoy Zang /* Fall through */ 1828aa070789SRoy Zang case e1000_82571: 1829aa070789SRoy Zang case e1000_82572: 1830aa070789SRoy Zang case e1000_ich8lan: 1831aa070789SRoy Zang ctrl = E1000_READ_REG(hw, TXDCTL1); 1832aa070789SRoy Zang ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) 1833aa070789SRoy Zang | E1000_TXDCTL_FULL_TX_DESC_WB; 1834aa070789SRoy Zang E1000_WRITE_REG(hw, TXDCTL1, ctrl); 1835aa070789SRoy Zang break; 18362c2668f9SRoy Zang case e1000_82573: 18372c2668f9SRoy Zang case e1000_82574: 18382c2668f9SRoy Zang reg_data = E1000_READ_REG(hw, GCR); 18392c2668f9SRoy Zang reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX; 18402c2668f9SRoy Zang E1000_WRITE_REG(hw, GCR, reg_data); 184195186063SMarek Vasut case e1000_igb: 184295186063SMarek Vasut break; 1843aa070789SRoy Zang } 1844aa070789SRoy Zang 18452439e4bfSJean-Christophe PLAGNIOL-VILLARD #if 0 18462439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Clear all of the statistics registers (clear on read). It is 18472439e4bfSJean-Christophe PLAGNIOL-VILLARD * important that we do this after we have tried to establish link 18482439e4bfSJean-Christophe PLAGNIOL-VILLARD * because the symbol error count will increment wildly if there 18492439e4bfSJean-Christophe PLAGNIOL-VILLARD * is no link. 18502439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 18512439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_clear_hw_cntrs(hw); 1852aa070789SRoy Zang 1853aa070789SRoy Zang /* ICH8 No-snoop bits are opposite polarity. 1854aa070789SRoy Zang * Set to snoop by default after reset. */ 1855aa070789SRoy Zang if (hw->mac_type == e1000_ich8lan) 1856aa070789SRoy Zang e1000_set_pci_ex_no_snoop(hw, PCI_EX_82566_SNOOP_ALL); 18572439e4bfSJean-Christophe PLAGNIOL-VILLARD #endif 18582439e4bfSJean-Christophe PLAGNIOL-VILLARD 1859aa070789SRoy Zang if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER || 1860aa070789SRoy Zang hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) { 1861aa070789SRoy Zang ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 1862aa070789SRoy Zang /* Relaxed ordering must be disabled to avoid a parity 1863aa070789SRoy Zang * error crash in a PCI slot. */ 1864aa070789SRoy Zang ctrl_ext |= E1000_CTRL_EXT_RO_DIS; 1865aa070789SRoy Zang E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 1866aa070789SRoy Zang } 1867aa070789SRoy Zang 18682439e4bfSJean-Christophe PLAGNIOL-VILLARD return ret_val; 18692439e4bfSJean-Christophe PLAGNIOL-VILLARD } 18702439e4bfSJean-Christophe PLAGNIOL-VILLARD 18712439e4bfSJean-Christophe PLAGNIOL-VILLARD /****************************************************************************** 18722439e4bfSJean-Christophe PLAGNIOL-VILLARD * Configures flow control and link settings. 18732439e4bfSJean-Christophe PLAGNIOL-VILLARD * 18742439e4bfSJean-Christophe PLAGNIOL-VILLARD * hw - Struct containing variables accessed by shared code 18752439e4bfSJean-Christophe PLAGNIOL-VILLARD * 18762439e4bfSJean-Christophe PLAGNIOL-VILLARD * Determines which flow control settings to use. Calls the apropriate media- 18772439e4bfSJean-Christophe PLAGNIOL-VILLARD * specific link configuration function. Configures the flow control settings. 18782439e4bfSJean-Christophe PLAGNIOL-VILLARD * Assuming the adapter has a valid link partner, a valid link should be 18792439e4bfSJean-Christophe PLAGNIOL-VILLARD * established. Assumes the hardware has previously been reset and the 18802439e4bfSJean-Christophe PLAGNIOL-VILLARD * transmitter and receiver are not enabled. 18812439e4bfSJean-Christophe PLAGNIOL-VILLARD *****************************************************************************/ 18822439e4bfSJean-Christophe PLAGNIOL-VILLARD static int 18835c5e707aSSimon Glass e1000_setup_link(struct e1000_hw *hw) 18842439e4bfSJean-Christophe PLAGNIOL-VILLARD { 18852439e4bfSJean-Christophe PLAGNIOL-VILLARD int32_t ret_val; 18868712adfdSRojhalat Ibrahim #ifndef CONFIG_E1000_NO_NVM 18878712adfdSRojhalat Ibrahim uint32_t ctrl_ext; 18882439e4bfSJean-Christophe PLAGNIOL-VILLARD uint16_t eeprom_data; 18898712adfdSRojhalat Ibrahim #endif 18902439e4bfSJean-Christophe PLAGNIOL-VILLARD 18912439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGFUNC(); 18922439e4bfSJean-Christophe PLAGNIOL-VILLARD 1893aa070789SRoy Zang /* In the case of the phy reset being blocked, we already have a link. 1894aa070789SRoy Zang * We do not have to set it up again. */ 1895aa070789SRoy Zang if (e1000_check_phy_reset_block(hw)) 1896aa070789SRoy Zang return E1000_SUCCESS; 1897aa070789SRoy Zang 18988712adfdSRojhalat Ibrahim #ifndef CONFIG_E1000_NO_NVM 18992439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Read and store word 0x0F of the EEPROM. This word contains bits 19002439e4bfSJean-Christophe PLAGNIOL-VILLARD * that determine the hardware's default PAUSE (flow control) mode, 19012439e4bfSJean-Christophe PLAGNIOL-VILLARD * a bit that determines whether the HW defaults to enabling or 19022439e4bfSJean-Christophe PLAGNIOL-VILLARD * disabling auto-negotiation, and the direction of the 19032439e4bfSJean-Christophe PLAGNIOL-VILLARD * SW defined pins. If there is no SW over-ride of the flow 19042439e4bfSJean-Christophe PLAGNIOL-VILLARD * control setting, then the variable hw->fc will 19052439e4bfSJean-Christophe PLAGNIOL-VILLARD * be initialized based on a value in the EEPROM. 19062439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 1907aa070789SRoy Zang if (e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, 1, 1908aa070789SRoy Zang &eeprom_data) < 0) { 19092439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("EEPROM Read Error\n"); 19102439e4bfSJean-Christophe PLAGNIOL-VILLARD return -E1000_ERR_EEPROM; 19112439e4bfSJean-Christophe PLAGNIOL-VILLARD } 19128712adfdSRojhalat Ibrahim #endif 19132439e4bfSJean-Christophe PLAGNIOL-VILLARD if (hw->fc == e1000_fc_default) { 1914aa070789SRoy Zang switch (hw->mac_type) { 1915aa070789SRoy Zang case e1000_ich8lan: 1916aa070789SRoy Zang case e1000_82573: 19172c2668f9SRoy Zang case e1000_82574: 191895186063SMarek Vasut case e1000_igb: 1919aa070789SRoy Zang hw->fc = e1000_fc_full; 1920aa070789SRoy Zang break; 1921aa070789SRoy Zang default: 19228712adfdSRojhalat Ibrahim #ifndef CONFIG_E1000_NO_NVM 1923aa070789SRoy Zang ret_val = e1000_read_eeprom(hw, 1924aa070789SRoy Zang EEPROM_INIT_CONTROL2_REG, 1, &eeprom_data); 1925aa070789SRoy Zang if (ret_val) { 1926aa070789SRoy Zang DEBUGOUT("EEPROM Read Error\n"); 1927aa070789SRoy Zang return -E1000_ERR_EEPROM; 1928aa070789SRoy Zang } 19292439e4bfSJean-Christophe PLAGNIOL-VILLARD if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0) 19302439e4bfSJean-Christophe PLAGNIOL-VILLARD hw->fc = e1000_fc_none; 19312439e4bfSJean-Christophe PLAGNIOL-VILLARD else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 19322439e4bfSJean-Christophe PLAGNIOL-VILLARD EEPROM_WORD0F_ASM_DIR) 19332439e4bfSJean-Christophe PLAGNIOL-VILLARD hw->fc = e1000_fc_tx_pause; 19342439e4bfSJean-Christophe PLAGNIOL-VILLARD else 19358712adfdSRojhalat Ibrahim #endif 19362439e4bfSJean-Christophe PLAGNIOL-VILLARD hw->fc = e1000_fc_full; 1937aa070789SRoy Zang break; 1938aa070789SRoy Zang } 19392439e4bfSJean-Christophe PLAGNIOL-VILLARD } 19402439e4bfSJean-Christophe PLAGNIOL-VILLARD 19412439e4bfSJean-Christophe PLAGNIOL-VILLARD /* We want to save off the original Flow Control configuration just 19422439e4bfSJean-Christophe PLAGNIOL-VILLARD * in case we get disconnected and then reconnected into a different 19432439e4bfSJean-Christophe PLAGNIOL-VILLARD * hub or switch with different Flow Control capabilities. 19442439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 19452439e4bfSJean-Christophe PLAGNIOL-VILLARD if (hw->mac_type == e1000_82542_rev2_0) 19462439e4bfSJean-Christophe PLAGNIOL-VILLARD hw->fc &= (~e1000_fc_tx_pause); 19472439e4bfSJean-Christophe PLAGNIOL-VILLARD 19482439e4bfSJean-Christophe PLAGNIOL-VILLARD if ((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1)) 19492439e4bfSJean-Christophe PLAGNIOL-VILLARD hw->fc &= (~e1000_fc_rx_pause); 19502439e4bfSJean-Christophe PLAGNIOL-VILLARD 19512439e4bfSJean-Christophe PLAGNIOL-VILLARD hw->original_fc = hw->fc; 19522439e4bfSJean-Christophe PLAGNIOL-VILLARD 19532439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("After fix-ups FlowControl is now = %x\n", hw->fc); 19542439e4bfSJean-Christophe PLAGNIOL-VILLARD 19558712adfdSRojhalat Ibrahim #ifndef CONFIG_E1000_NO_NVM 19562439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Take the 4 bits from EEPROM word 0x0F that determine the initial 19572439e4bfSJean-Christophe PLAGNIOL-VILLARD * polarity value for the SW controlled pins, and setup the 19582439e4bfSJean-Christophe PLAGNIOL-VILLARD * Extended Device Control reg with that info. 19592439e4bfSJean-Christophe PLAGNIOL-VILLARD * This is needed because one of the SW controlled pins is used for 19602439e4bfSJean-Christophe PLAGNIOL-VILLARD * signal detection. So this should be done before e1000_setup_pcs_link() 19612439e4bfSJean-Christophe PLAGNIOL-VILLARD * or e1000_phy_setup() is called. 19622439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 19632439e4bfSJean-Christophe PLAGNIOL-VILLARD if (hw->mac_type == e1000_82543) { 19642439e4bfSJean-Christophe PLAGNIOL-VILLARD ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) << 19652439e4bfSJean-Christophe PLAGNIOL-VILLARD SWDPIO__EXT_SHIFT); 19662439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 19672439e4bfSJean-Christophe PLAGNIOL-VILLARD } 19688712adfdSRojhalat Ibrahim #endif 19692439e4bfSJean-Christophe PLAGNIOL-VILLARD 19702439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Call the necessary subroutine to configure the link. */ 19712439e4bfSJean-Christophe PLAGNIOL-VILLARD ret_val = (hw->media_type == e1000_media_type_fiber) ? 19725c5e707aSSimon Glass e1000_setup_fiber_link(hw) : e1000_setup_copper_link(hw); 19732439e4bfSJean-Christophe PLAGNIOL-VILLARD if (ret_val < 0) { 19742439e4bfSJean-Christophe PLAGNIOL-VILLARD return ret_val; 19752439e4bfSJean-Christophe PLAGNIOL-VILLARD } 19762439e4bfSJean-Christophe PLAGNIOL-VILLARD 19772439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Initialize the flow control address, type, and PAUSE timer 19782439e4bfSJean-Christophe PLAGNIOL-VILLARD * registers to their default values. This is done even if flow 19792439e4bfSJean-Christophe PLAGNIOL-VILLARD * control is disabled, because it does not hurt anything to 19802439e4bfSJean-Christophe PLAGNIOL-VILLARD * initialize these registers. 19812439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 1982aa070789SRoy Zang DEBUGOUT("Initializing the Flow Control address, type" 1983aa070789SRoy Zang "and timer regs\n"); 19842439e4bfSJean-Christophe PLAGNIOL-VILLARD 1985aa070789SRoy Zang /* FCAL/H and FCT are hardcoded to standard values in e1000_ich8lan. */ 1986aa070789SRoy Zang if (hw->mac_type != e1000_ich8lan) { 19872439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE); 1988aa070789SRoy Zang E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH); 1989aa070789SRoy Zang E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW); 1990aa070789SRoy Zang } 1991aa070789SRoy Zang 19922439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time); 19932439e4bfSJean-Christophe PLAGNIOL-VILLARD 19942439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Set the flow control receive threshold registers. Normally, 19952439e4bfSJean-Christophe PLAGNIOL-VILLARD * these registers will be set to a default threshold that may be 19962439e4bfSJean-Christophe PLAGNIOL-VILLARD * adjusted later by the driver's runtime code. However, if the 19972439e4bfSJean-Christophe PLAGNIOL-VILLARD * ability to transmit pause frames in not enabled, then these 19982439e4bfSJean-Christophe PLAGNIOL-VILLARD * registers will be set to 0. 19992439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 20002439e4bfSJean-Christophe PLAGNIOL-VILLARD if (!(hw->fc & e1000_fc_tx_pause)) { 20012439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, FCRTL, 0); 20022439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, FCRTH, 0); 20032439e4bfSJean-Christophe PLAGNIOL-VILLARD } else { 20042439e4bfSJean-Christophe PLAGNIOL-VILLARD /* We need to set up the Receive Threshold high and low water marks 20052439e4bfSJean-Christophe PLAGNIOL-VILLARD * as well as (optionally) enabling the transmission of XON frames. 20062439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 20072439e4bfSJean-Christophe PLAGNIOL-VILLARD if (hw->fc_send_xon) { 20082439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, FCRTL, 20092439e4bfSJean-Christophe PLAGNIOL-VILLARD (hw->fc_low_water | E1000_FCRTL_XONE)); 20102439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water); 20112439e4bfSJean-Christophe PLAGNIOL-VILLARD } else { 20122439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water); 20132439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water); 20142439e4bfSJean-Christophe PLAGNIOL-VILLARD } 20152439e4bfSJean-Christophe PLAGNIOL-VILLARD } 20162439e4bfSJean-Christophe PLAGNIOL-VILLARD return ret_val; 20172439e4bfSJean-Christophe PLAGNIOL-VILLARD } 20182439e4bfSJean-Christophe PLAGNIOL-VILLARD 20192439e4bfSJean-Christophe PLAGNIOL-VILLARD /****************************************************************************** 20202439e4bfSJean-Christophe PLAGNIOL-VILLARD * Sets up link for a fiber based adapter 20212439e4bfSJean-Christophe PLAGNIOL-VILLARD * 20222439e4bfSJean-Christophe PLAGNIOL-VILLARD * hw - Struct containing variables accessed by shared code 20232439e4bfSJean-Christophe PLAGNIOL-VILLARD * 20242439e4bfSJean-Christophe PLAGNIOL-VILLARD * Manipulates Physical Coding Sublayer functions in order to configure 20252439e4bfSJean-Christophe PLAGNIOL-VILLARD * link. Assumes the hardware has been previously reset and the transmitter 20262439e4bfSJean-Christophe PLAGNIOL-VILLARD * and receiver are not enabled. 20272439e4bfSJean-Christophe PLAGNIOL-VILLARD *****************************************************************************/ 20282439e4bfSJean-Christophe PLAGNIOL-VILLARD static int 20295c5e707aSSimon Glass e1000_setup_fiber_link(struct e1000_hw *hw) 20302439e4bfSJean-Christophe PLAGNIOL-VILLARD { 20312439e4bfSJean-Christophe PLAGNIOL-VILLARD uint32_t ctrl; 20322439e4bfSJean-Christophe PLAGNIOL-VILLARD uint32_t status; 20332439e4bfSJean-Christophe PLAGNIOL-VILLARD uint32_t txcw = 0; 20342439e4bfSJean-Christophe PLAGNIOL-VILLARD uint32_t i; 20352439e4bfSJean-Christophe PLAGNIOL-VILLARD uint32_t signal; 20362439e4bfSJean-Christophe PLAGNIOL-VILLARD int32_t ret_val; 20372439e4bfSJean-Christophe PLAGNIOL-VILLARD 20382439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGFUNC(); 20392439e4bfSJean-Christophe PLAGNIOL-VILLARD /* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be 20402439e4bfSJean-Christophe PLAGNIOL-VILLARD * set when the optics detect a signal. On older adapters, it will be 20412439e4bfSJean-Christophe PLAGNIOL-VILLARD * cleared when there is a signal 20422439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 20432439e4bfSJean-Christophe PLAGNIOL-VILLARD ctrl = E1000_READ_REG(hw, CTRL); 20442439e4bfSJean-Christophe PLAGNIOL-VILLARD if ((hw->mac_type > e1000_82544) && !(ctrl & E1000_CTRL_ILOS)) 20452439e4bfSJean-Christophe PLAGNIOL-VILLARD signal = E1000_CTRL_SWDPIN1; 20462439e4bfSJean-Christophe PLAGNIOL-VILLARD else 20472439e4bfSJean-Christophe PLAGNIOL-VILLARD signal = 0; 20482439e4bfSJean-Christophe PLAGNIOL-VILLARD 20495c5e707aSSimon Glass printf("signal for %s is %x (ctrl %08x)!!!!\n", hw->name, signal, 20502439e4bfSJean-Christophe PLAGNIOL-VILLARD ctrl); 20512439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Take the link out of reset */ 20522439e4bfSJean-Christophe PLAGNIOL-VILLARD ctrl &= ~(E1000_CTRL_LRST); 20532439e4bfSJean-Christophe PLAGNIOL-VILLARD 20542439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_config_collision_dist(hw); 20552439e4bfSJean-Christophe PLAGNIOL-VILLARD 20562439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Check for a software override of the flow control settings, and setup 20572439e4bfSJean-Christophe PLAGNIOL-VILLARD * the device accordingly. If auto-negotiation is enabled, then software 20582439e4bfSJean-Christophe PLAGNIOL-VILLARD * will have to set the "PAUSE" bits to the correct value in the Tranmsit 20592439e4bfSJean-Christophe PLAGNIOL-VILLARD * Config Word Register (TXCW) and re-start auto-negotiation. However, if 20602439e4bfSJean-Christophe PLAGNIOL-VILLARD * auto-negotiation is disabled, then software will have to manually 20612439e4bfSJean-Christophe PLAGNIOL-VILLARD * configure the two flow control enable bits in the CTRL register. 20622439e4bfSJean-Christophe PLAGNIOL-VILLARD * 20632439e4bfSJean-Christophe PLAGNIOL-VILLARD * The possible values of the "fc" parameter are: 20642439e4bfSJean-Christophe PLAGNIOL-VILLARD * 0: Flow control is completely disabled 20652439e4bfSJean-Christophe PLAGNIOL-VILLARD * 1: Rx flow control is enabled (we can receive pause frames, but 20662439e4bfSJean-Christophe PLAGNIOL-VILLARD * not send pause frames). 20672439e4bfSJean-Christophe PLAGNIOL-VILLARD * 2: Tx flow control is enabled (we can send pause frames but we do 20682439e4bfSJean-Christophe PLAGNIOL-VILLARD * not support receiving pause frames). 20692439e4bfSJean-Christophe PLAGNIOL-VILLARD * 3: Both Rx and TX flow control (symmetric) are enabled. 20702439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 20712439e4bfSJean-Christophe PLAGNIOL-VILLARD switch (hw->fc) { 20722439e4bfSJean-Christophe PLAGNIOL-VILLARD case e1000_fc_none: 20732439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Flow control is completely disabled by a software over-ride. */ 20742439e4bfSJean-Christophe PLAGNIOL-VILLARD txcw = (E1000_TXCW_ANE | E1000_TXCW_FD); 20752439e4bfSJean-Christophe PLAGNIOL-VILLARD break; 20762439e4bfSJean-Christophe PLAGNIOL-VILLARD case e1000_fc_rx_pause: 20772439e4bfSJean-Christophe PLAGNIOL-VILLARD /* RX Flow control is enabled and TX Flow control is disabled by a 20782439e4bfSJean-Christophe PLAGNIOL-VILLARD * software over-ride. Since there really isn't a way to advertise 20792439e4bfSJean-Christophe PLAGNIOL-VILLARD * that we are capable of RX Pause ONLY, we will advertise that we 20802439e4bfSJean-Christophe PLAGNIOL-VILLARD * support both symmetric and asymmetric RX PAUSE. Later, we will 20812439e4bfSJean-Christophe PLAGNIOL-VILLARD * disable the adapter's ability to send PAUSE frames. 20822439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 20832439e4bfSJean-Christophe PLAGNIOL-VILLARD txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); 20842439e4bfSJean-Christophe PLAGNIOL-VILLARD break; 20852439e4bfSJean-Christophe PLAGNIOL-VILLARD case e1000_fc_tx_pause: 20862439e4bfSJean-Christophe PLAGNIOL-VILLARD /* TX Flow control is enabled, and RX Flow control is disabled, by a 20872439e4bfSJean-Christophe PLAGNIOL-VILLARD * software over-ride. 20882439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 20892439e4bfSJean-Christophe PLAGNIOL-VILLARD txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR); 20902439e4bfSJean-Christophe PLAGNIOL-VILLARD break; 20912439e4bfSJean-Christophe PLAGNIOL-VILLARD case e1000_fc_full: 20922439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Flow control (both RX and TX) is enabled by a software over-ride. */ 20932439e4bfSJean-Christophe PLAGNIOL-VILLARD txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); 20942439e4bfSJean-Christophe PLAGNIOL-VILLARD break; 20952439e4bfSJean-Christophe PLAGNIOL-VILLARD default: 20962439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("Flow control param set incorrectly\n"); 20972439e4bfSJean-Christophe PLAGNIOL-VILLARD return -E1000_ERR_CONFIG; 20982439e4bfSJean-Christophe PLAGNIOL-VILLARD break; 20992439e4bfSJean-Christophe PLAGNIOL-VILLARD } 21002439e4bfSJean-Christophe PLAGNIOL-VILLARD 21012439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Since auto-negotiation is enabled, take the link out of reset (the link 21022439e4bfSJean-Christophe PLAGNIOL-VILLARD * will be in reset, because we previously reset the chip). This will 21032439e4bfSJean-Christophe PLAGNIOL-VILLARD * restart auto-negotiation. If auto-neogtiation is successful then the 21042439e4bfSJean-Christophe PLAGNIOL-VILLARD * link-up status bit will be set and the flow control enable bits (RFCE 21052439e4bfSJean-Christophe PLAGNIOL-VILLARD * and TFCE) will be set according to their negotiated value. 21062439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 21072439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("Auto-negotiation enabled (%#x)\n", txcw); 21082439e4bfSJean-Christophe PLAGNIOL-VILLARD 21092439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, TXCW, txcw); 21102439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, CTRL, ctrl); 21112439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_FLUSH(hw); 21122439e4bfSJean-Christophe PLAGNIOL-VILLARD 21132439e4bfSJean-Christophe PLAGNIOL-VILLARD hw->txcw = txcw; 21142439e4bfSJean-Christophe PLAGNIOL-VILLARD mdelay(1); 21152439e4bfSJean-Christophe PLAGNIOL-VILLARD 21162439e4bfSJean-Christophe PLAGNIOL-VILLARD /* If we have a signal (the cable is plugged in) then poll for a "Link-Up" 21172439e4bfSJean-Christophe PLAGNIOL-VILLARD * indication in the Device Status Register. Time-out if a link isn't 21182439e4bfSJean-Christophe PLAGNIOL-VILLARD * seen in 500 milliseconds seconds (Auto-negotiation should complete in 21192439e4bfSJean-Christophe PLAGNIOL-VILLARD * less than 500 milliseconds even if the other end is doing it in SW). 21202439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 21212439e4bfSJean-Christophe PLAGNIOL-VILLARD if ((E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) { 21222439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("Looking for Link\n"); 21232439e4bfSJean-Christophe PLAGNIOL-VILLARD for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) { 21242439e4bfSJean-Christophe PLAGNIOL-VILLARD mdelay(10); 21252439e4bfSJean-Christophe PLAGNIOL-VILLARD status = E1000_READ_REG(hw, STATUS); 21262439e4bfSJean-Christophe PLAGNIOL-VILLARD if (status & E1000_STATUS_LU) 21272439e4bfSJean-Christophe PLAGNIOL-VILLARD break; 21282439e4bfSJean-Christophe PLAGNIOL-VILLARD } 21292439e4bfSJean-Christophe PLAGNIOL-VILLARD if (i == (LINK_UP_TIMEOUT / 10)) { 21302439e4bfSJean-Christophe PLAGNIOL-VILLARD /* AutoNeg failed to achieve a link, so we'll call 21312439e4bfSJean-Christophe PLAGNIOL-VILLARD * e1000_check_for_link. This routine will force the link up if we 21322439e4bfSJean-Christophe PLAGNIOL-VILLARD * detect a signal. This will allow us to communicate with 21332439e4bfSJean-Christophe PLAGNIOL-VILLARD * non-autonegotiating link partners. 21342439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 21352439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("Never got a valid link from auto-neg!!!\n"); 21362439e4bfSJean-Christophe PLAGNIOL-VILLARD hw->autoneg_failed = 1; 21375c5e707aSSimon Glass ret_val = e1000_check_for_link(hw); 21382439e4bfSJean-Christophe PLAGNIOL-VILLARD if (ret_val < 0) { 21392439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("Error while checking for link\n"); 21402439e4bfSJean-Christophe PLAGNIOL-VILLARD return ret_val; 21412439e4bfSJean-Christophe PLAGNIOL-VILLARD } 21422439e4bfSJean-Christophe PLAGNIOL-VILLARD hw->autoneg_failed = 0; 21432439e4bfSJean-Christophe PLAGNIOL-VILLARD } else { 21442439e4bfSJean-Christophe PLAGNIOL-VILLARD hw->autoneg_failed = 0; 21452439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("Valid Link Found\n"); 21462439e4bfSJean-Christophe PLAGNIOL-VILLARD } 21472439e4bfSJean-Christophe PLAGNIOL-VILLARD } else { 21482439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("No Signal Detected\n"); 21492439e4bfSJean-Christophe PLAGNIOL-VILLARD return -E1000_ERR_NOLINK; 21502439e4bfSJean-Christophe PLAGNIOL-VILLARD } 21512439e4bfSJean-Christophe PLAGNIOL-VILLARD return 0; 21522439e4bfSJean-Christophe PLAGNIOL-VILLARD } 21532439e4bfSJean-Christophe PLAGNIOL-VILLARD 21542439e4bfSJean-Christophe PLAGNIOL-VILLARD /****************************************************************************** 2155aa070789SRoy Zang * Make sure we have a valid PHY and change PHY mode before link setup. 21562439e4bfSJean-Christophe PLAGNIOL-VILLARD * 21572439e4bfSJean-Christophe PLAGNIOL-VILLARD * hw - Struct containing variables accessed by shared code 21582439e4bfSJean-Christophe PLAGNIOL-VILLARD ******************************************************************************/ 2159aa070789SRoy Zang static int32_t 2160aa070789SRoy Zang e1000_copper_link_preconfig(struct e1000_hw *hw) 21612439e4bfSJean-Christophe PLAGNIOL-VILLARD { 21622439e4bfSJean-Christophe PLAGNIOL-VILLARD uint32_t ctrl; 21632439e4bfSJean-Christophe PLAGNIOL-VILLARD int32_t ret_val; 21642439e4bfSJean-Christophe PLAGNIOL-VILLARD uint16_t phy_data; 21652439e4bfSJean-Christophe PLAGNIOL-VILLARD 21662439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGFUNC(); 21672439e4bfSJean-Christophe PLAGNIOL-VILLARD 21682439e4bfSJean-Christophe PLAGNIOL-VILLARD ctrl = E1000_READ_REG(hw, CTRL); 21692439e4bfSJean-Christophe PLAGNIOL-VILLARD /* With 82543, we need to force speed and duplex on the MAC equal to what 21702439e4bfSJean-Christophe PLAGNIOL-VILLARD * the PHY speed and duplex configuration is. In addition, we need to 21712439e4bfSJean-Christophe PLAGNIOL-VILLARD * perform a hardware reset on the PHY to take it out of reset. 21722439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 21732439e4bfSJean-Christophe PLAGNIOL-VILLARD if (hw->mac_type > e1000_82543) { 21742439e4bfSJean-Christophe PLAGNIOL-VILLARD ctrl |= E1000_CTRL_SLU; 21752439e4bfSJean-Christophe PLAGNIOL-VILLARD ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 21762439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, CTRL, ctrl); 21772439e4bfSJean-Christophe PLAGNIOL-VILLARD } else { 2178aa070789SRoy Zang ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX 2179aa070789SRoy Zang | E1000_CTRL_SLU); 21802439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, CTRL, ctrl); 2181aa070789SRoy Zang ret_val = e1000_phy_hw_reset(hw); 2182aa070789SRoy Zang if (ret_val) 2183aa070789SRoy Zang return ret_val; 21842439e4bfSJean-Christophe PLAGNIOL-VILLARD } 21852439e4bfSJean-Christophe PLAGNIOL-VILLARD 21862439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Make sure we have a valid PHY */ 21872439e4bfSJean-Christophe PLAGNIOL-VILLARD ret_val = e1000_detect_gig_phy(hw); 2188aa070789SRoy Zang if (ret_val) { 21892439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("Error, did not detect valid phy.\n"); 21902439e4bfSJean-Christophe PLAGNIOL-VILLARD return ret_val; 21912439e4bfSJean-Christophe PLAGNIOL-VILLARD } 21922439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("Phy ID = %x\n", hw->phy_id); 21932439e4bfSJean-Christophe PLAGNIOL-VILLARD 2194aa070789SRoy Zang /* Set PHY to class A mode (if necessary) */ 2195aa070789SRoy Zang ret_val = e1000_set_phy_mode(hw); 2196aa070789SRoy Zang if (ret_val) 2197aa070789SRoy Zang return ret_val; 2198aa070789SRoy Zang if ((hw->mac_type == e1000_82545_rev_3) || 2199aa070789SRoy Zang (hw->mac_type == e1000_82546_rev_3)) { 2200aa070789SRoy Zang ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 2201aa070789SRoy Zang &phy_data); 2202aa070789SRoy Zang phy_data |= 0x00000008; 2203aa070789SRoy Zang ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 2204aa070789SRoy Zang phy_data); 22052439e4bfSJean-Christophe PLAGNIOL-VILLARD } 2206aa070789SRoy Zang 2207aa070789SRoy Zang if (hw->mac_type <= e1000_82543 || 2208aa070789SRoy Zang hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 || 2209aa070789SRoy Zang hw->mac_type == e1000_82541_rev_2 2210aa070789SRoy Zang || hw->mac_type == e1000_82547_rev_2) 2211472d5460SYork Sun hw->phy_reset_disable = false; 2212aa070789SRoy Zang 2213aa070789SRoy Zang return E1000_SUCCESS; 2214aa070789SRoy Zang } 2215aa070789SRoy Zang 2216aa070789SRoy Zang /***************************************************************************** 2217aa070789SRoy Zang * 2218aa070789SRoy Zang * This function sets the lplu state according to the active flag. When 2219aa070789SRoy Zang * activating lplu this function also disables smart speed and vise versa. 2220aa070789SRoy Zang * lplu will not be activated unless the device autonegotiation advertisment 2221aa070789SRoy Zang * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes. 2222aa070789SRoy Zang * hw: Struct containing variables accessed by shared code 2223aa070789SRoy Zang * active - true to enable lplu false to disable lplu. 2224aa070789SRoy Zang * 2225aa070789SRoy Zang * returns: - E1000_ERR_PHY if fail to read/write the PHY 2226aa070789SRoy Zang * E1000_SUCCESS at any other case. 2227aa070789SRoy Zang * 2228aa070789SRoy Zang ****************************************************************************/ 2229aa070789SRoy Zang 2230aa070789SRoy Zang static int32_t 2231472d5460SYork Sun e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active) 2232aa070789SRoy Zang { 2233aa070789SRoy Zang uint32_t phy_ctrl = 0; 2234aa070789SRoy Zang int32_t ret_val; 2235aa070789SRoy Zang uint16_t phy_data; 2236aa070789SRoy Zang DEBUGFUNC(); 2237aa070789SRoy Zang 2238aa070789SRoy Zang if (hw->phy_type != e1000_phy_igp && hw->phy_type != e1000_phy_igp_2 2239aa070789SRoy Zang && hw->phy_type != e1000_phy_igp_3) 2240aa070789SRoy Zang return E1000_SUCCESS; 2241aa070789SRoy Zang 2242aa070789SRoy Zang /* During driver activity LPLU should not be used or it will attain link 2243aa070789SRoy Zang * from the lowest speeds starting from 10Mbps. The capability is used 2244aa070789SRoy Zang * for Dx transitions and states */ 2245aa070789SRoy Zang if (hw->mac_type == e1000_82541_rev_2 2246aa070789SRoy Zang || hw->mac_type == e1000_82547_rev_2) { 2247aa070789SRoy Zang ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, 2248aa070789SRoy Zang &phy_data); 2249aa070789SRoy Zang if (ret_val) 2250aa070789SRoy Zang return ret_val; 2251aa070789SRoy Zang } else if (hw->mac_type == e1000_ich8lan) { 2252aa070789SRoy Zang /* MAC writes into PHY register based on the state transition 2253aa070789SRoy Zang * and start auto-negotiation. SW driver can overwrite the 2254aa070789SRoy Zang * settings in CSR PHY power control E1000_PHY_CTRL register. */ 2255aa070789SRoy Zang phy_ctrl = E1000_READ_REG(hw, PHY_CTRL); 2256aa070789SRoy Zang } else { 2257aa070789SRoy Zang ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, 2258aa070789SRoy Zang &phy_data); 2259aa070789SRoy Zang if (ret_val) 2260aa070789SRoy Zang return ret_val; 2261aa070789SRoy Zang } 2262aa070789SRoy Zang 2263aa070789SRoy Zang if (!active) { 2264aa070789SRoy Zang if (hw->mac_type == e1000_82541_rev_2 || 2265aa070789SRoy Zang hw->mac_type == e1000_82547_rev_2) { 2266aa070789SRoy Zang phy_data &= ~IGP01E1000_GMII_FLEX_SPD; 2267aa070789SRoy Zang ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, 2268aa070789SRoy Zang phy_data); 2269aa070789SRoy Zang if (ret_val) 2270aa070789SRoy Zang return ret_val; 2271aa070789SRoy Zang } else { 2272aa070789SRoy Zang if (hw->mac_type == e1000_ich8lan) { 2273aa070789SRoy Zang phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU; 2274aa070789SRoy Zang E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); 2275aa070789SRoy Zang } else { 2276aa070789SRoy Zang phy_data &= ~IGP02E1000_PM_D3_LPLU; 2277aa070789SRoy Zang ret_val = e1000_write_phy_reg(hw, 2278aa070789SRoy Zang IGP02E1000_PHY_POWER_MGMT, phy_data); 2279aa070789SRoy Zang if (ret_val) 2280aa070789SRoy Zang return ret_val; 2281aa070789SRoy Zang } 2282aa070789SRoy Zang } 2283aa070789SRoy Zang 2284aa070789SRoy Zang /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during 2285aa070789SRoy Zang * Dx states where the power conservation is most important. During 2286aa070789SRoy Zang * driver activity we should enable SmartSpeed, so performance is 2287aa070789SRoy Zang * maintained. */ 2288aa070789SRoy Zang if (hw->smart_speed == e1000_smart_speed_on) { 2289aa070789SRoy Zang ret_val = e1000_read_phy_reg(hw, 2290aa070789SRoy Zang IGP01E1000_PHY_PORT_CONFIG, &phy_data); 2291aa070789SRoy Zang if (ret_val) 2292aa070789SRoy Zang return ret_val; 2293aa070789SRoy Zang 2294aa070789SRoy Zang phy_data |= IGP01E1000_PSCFR_SMART_SPEED; 2295aa070789SRoy Zang ret_val = e1000_write_phy_reg(hw, 2296aa070789SRoy Zang IGP01E1000_PHY_PORT_CONFIG, phy_data); 2297aa070789SRoy Zang if (ret_val) 2298aa070789SRoy Zang return ret_val; 2299aa070789SRoy Zang } else if (hw->smart_speed == e1000_smart_speed_off) { 2300aa070789SRoy Zang ret_val = e1000_read_phy_reg(hw, 2301aa070789SRoy Zang IGP01E1000_PHY_PORT_CONFIG, &phy_data); 2302aa070789SRoy Zang if (ret_val) 2303aa070789SRoy Zang return ret_val; 2304aa070789SRoy Zang 2305aa070789SRoy Zang phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 2306aa070789SRoy Zang ret_val = e1000_write_phy_reg(hw, 2307aa070789SRoy Zang IGP01E1000_PHY_PORT_CONFIG, phy_data); 2308aa070789SRoy Zang if (ret_val) 2309aa070789SRoy Zang return ret_val; 2310aa070789SRoy Zang } 2311aa070789SRoy Zang 2312aa070789SRoy Zang } else if ((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT) 2313aa070789SRoy Zang || (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL) || 2314aa070789SRoy Zang (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) { 2315aa070789SRoy Zang 2316aa070789SRoy Zang if (hw->mac_type == e1000_82541_rev_2 || 2317aa070789SRoy Zang hw->mac_type == e1000_82547_rev_2) { 2318aa070789SRoy Zang phy_data |= IGP01E1000_GMII_FLEX_SPD; 2319aa070789SRoy Zang ret_val = e1000_write_phy_reg(hw, 2320aa070789SRoy Zang IGP01E1000_GMII_FIFO, phy_data); 2321aa070789SRoy Zang if (ret_val) 2322aa070789SRoy Zang return ret_val; 2323aa070789SRoy Zang } else { 2324aa070789SRoy Zang if (hw->mac_type == e1000_ich8lan) { 2325aa070789SRoy Zang phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU; 2326aa070789SRoy Zang E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); 2327aa070789SRoy Zang } else { 2328aa070789SRoy Zang phy_data |= IGP02E1000_PM_D3_LPLU; 2329aa070789SRoy Zang ret_val = e1000_write_phy_reg(hw, 2330aa070789SRoy Zang IGP02E1000_PHY_POWER_MGMT, phy_data); 2331aa070789SRoy Zang if (ret_val) 2332aa070789SRoy Zang return ret_val; 2333aa070789SRoy Zang } 2334aa070789SRoy Zang } 2335aa070789SRoy Zang 2336aa070789SRoy Zang /* When LPLU is enabled we should disable SmartSpeed */ 2337aa070789SRoy Zang ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 2338aa070789SRoy Zang &phy_data); 2339aa070789SRoy Zang if (ret_val) 2340aa070789SRoy Zang return ret_val; 2341aa070789SRoy Zang 2342aa070789SRoy Zang phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 2343aa070789SRoy Zang ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 2344aa070789SRoy Zang phy_data); 2345aa070789SRoy Zang if (ret_val) 2346aa070789SRoy Zang return ret_val; 2347aa070789SRoy Zang } 2348aa070789SRoy Zang return E1000_SUCCESS; 2349aa070789SRoy Zang } 2350aa070789SRoy Zang 2351aa070789SRoy Zang /***************************************************************************** 2352aa070789SRoy Zang * 2353aa070789SRoy Zang * This function sets the lplu d0 state according to the active flag. When 2354aa070789SRoy Zang * activating lplu this function also disables smart speed and vise versa. 2355aa070789SRoy Zang * lplu will not be activated unless the device autonegotiation advertisment 2356aa070789SRoy Zang * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes. 2357aa070789SRoy Zang * hw: Struct containing variables accessed by shared code 2358aa070789SRoy Zang * active - true to enable lplu false to disable lplu. 2359aa070789SRoy Zang * 2360aa070789SRoy Zang * returns: - E1000_ERR_PHY if fail to read/write the PHY 2361aa070789SRoy Zang * E1000_SUCCESS at any other case. 2362aa070789SRoy Zang * 2363aa070789SRoy Zang ****************************************************************************/ 2364aa070789SRoy Zang 2365aa070789SRoy Zang static int32_t 2366472d5460SYork Sun e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active) 2367aa070789SRoy Zang { 2368aa070789SRoy Zang uint32_t phy_ctrl = 0; 2369aa070789SRoy Zang int32_t ret_val; 2370aa070789SRoy Zang uint16_t phy_data; 2371aa070789SRoy Zang DEBUGFUNC(); 2372aa070789SRoy Zang 2373aa070789SRoy Zang if (hw->mac_type <= e1000_82547_rev_2) 2374aa070789SRoy Zang return E1000_SUCCESS; 2375aa070789SRoy Zang 2376aa070789SRoy Zang if (hw->mac_type == e1000_ich8lan) { 2377aa070789SRoy Zang phy_ctrl = E1000_READ_REG(hw, PHY_CTRL); 237895186063SMarek Vasut } else if (hw->mac_type == e1000_igb) { 237995186063SMarek Vasut phy_ctrl = E1000_READ_REG(hw, I210_PHY_CTRL); 2380aa070789SRoy Zang } else { 2381aa070789SRoy Zang ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, 2382aa070789SRoy Zang &phy_data); 2383aa070789SRoy Zang if (ret_val) 2384aa070789SRoy Zang return ret_val; 2385aa070789SRoy Zang } 2386aa070789SRoy Zang 2387aa070789SRoy Zang if (!active) { 2388aa070789SRoy Zang if (hw->mac_type == e1000_ich8lan) { 2389aa070789SRoy Zang phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU; 2390aa070789SRoy Zang E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); 239195186063SMarek Vasut } else if (hw->mac_type == e1000_igb) { 239295186063SMarek Vasut phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU; 239395186063SMarek Vasut E1000_WRITE_REG(hw, I210_PHY_CTRL, phy_ctrl); 2394aa070789SRoy Zang } else { 2395aa070789SRoy Zang phy_data &= ~IGP02E1000_PM_D0_LPLU; 2396aa070789SRoy Zang ret_val = e1000_write_phy_reg(hw, 2397aa070789SRoy Zang IGP02E1000_PHY_POWER_MGMT, phy_data); 2398aa070789SRoy Zang if (ret_val) 2399aa070789SRoy Zang return ret_val; 2400aa070789SRoy Zang } 2401aa070789SRoy Zang 240295186063SMarek Vasut if (hw->mac_type == e1000_igb) 240395186063SMarek Vasut return E1000_SUCCESS; 240495186063SMarek Vasut 2405aa070789SRoy Zang /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during 2406aa070789SRoy Zang * Dx states where the power conservation is most important. During 2407aa070789SRoy Zang * driver activity we should enable SmartSpeed, so performance is 2408aa070789SRoy Zang * maintained. */ 2409aa070789SRoy Zang if (hw->smart_speed == e1000_smart_speed_on) { 2410aa070789SRoy Zang ret_val = e1000_read_phy_reg(hw, 2411aa070789SRoy Zang IGP01E1000_PHY_PORT_CONFIG, &phy_data); 2412aa070789SRoy Zang if (ret_val) 2413aa070789SRoy Zang return ret_val; 2414aa070789SRoy Zang 2415aa070789SRoy Zang phy_data |= IGP01E1000_PSCFR_SMART_SPEED; 2416aa070789SRoy Zang ret_val = e1000_write_phy_reg(hw, 2417aa070789SRoy Zang IGP01E1000_PHY_PORT_CONFIG, phy_data); 2418aa070789SRoy Zang if (ret_val) 2419aa070789SRoy Zang return ret_val; 2420aa070789SRoy Zang } else if (hw->smart_speed == e1000_smart_speed_off) { 2421aa070789SRoy Zang ret_val = e1000_read_phy_reg(hw, 2422aa070789SRoy Zang IGP01E1000_PHY_PORT_CONFIG, &phy_data); 2423aa070789SRoy Zang if (ret_val) 2424aa070789SRoy Zang return ret_val; 2425aa070789SRoy Zang 2426aa070789SRoy Zang phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 2427aa070789SRoy Zang ret_val = e1000_write_phy_reg(hw, 2428aa070789SRoy Zang IGP01E1000_PHY_PORT_CONFIG, phy_data); 2429aa070789SRoy Zang if (ret_val) 2430aa070789SRoy Zang return ret_val; 2431aa070789SRoy Zang } 2432aa070789SRoy Zang 2433aa070789SRoy Zang 2434aa070789SRoy Zang } else { 2435aa070789SRoy Zang 2436aa070789SRoy Zang if (hw->mac_type == e1000_ich8lan) { 2437aa070789SRoy Zang phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU; 2438aa070789SRoy Zang E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); 243995186063SMarek Vasut } else if (hw->mac_type == e1000_igb) { 244095186063SMarek Vasut phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU; 244195186063SMarek Vasut E1000_WRITE_REG(hw, I210_PHY_CTRL, phy_ctrl); 2442aa070789SRoy Zang } else { 2443aa070789SRoy Zang phy_data |= IGP02E1000_PM_D0_LPLU; 2444aa070789SRoy Zang ret_val = e1000_write_phy_reg(hw, 2445aa070789SRoy Zang IGP02E1000_PHY_POWER_MGMT, phy_data); 2446aa070789SRoy Zang if (ret_val) 2447aa070789SRoy Zang return ret_val; 2448aa070789SRoy Zang } 2449aa070789SRoy Zang 245095186063SMarek Vasut if (hw->mac_type == e1000_igb) 245195186063SMarek Vasut return E1000_SUCCESS; 245295186063SMarek Vasut 2453aa070789SRoy Zang /* When LPLU is enabled we should disable SmartSpeed */ 2454aa070789SRoy Zang ret_val = e1000_read_phy_reg(hw, 2455aa070789SRoy Zang IGP01E1000_PHY_PORT_CONFIG, &phy_data); 2456aa070789SRoy Zang if (ret_val) 2457aa070789SRoy Zang return ret_val; 2458aa070789SRoy Zang 2459aa070789SRoy Zang phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 2460aa070789SRoy Zang ret_val = e1000_write_phy_reg(hw, 2461aa070789SRoy Zang IGP01E1000_PHY_PORT_CONFIG, phy_data); 2462aa070789SRoy Zang if (ret_val) 2463aa070789SRoy Zang return ret_val; 2464aa070789SRoy Zang 2465aa070789SRoy Zang } 2466aa070789SRoy Zang return E1000_SUCCESS; 2467aa070789SRoy Zang } 2468aa070789SRoy Zang 2469aa070789SRoy Zang /******************************************************************** 2470aa070789SRoy Zang * Copper link setup for e1000_phy_igp series. 2471aa070789SRoy Zang * 2472aa070789SRoy Zang * hw - Struct containing variables accessed by shared code 2473aa070789SRoy Zang *********************************************************************/ 2474aa070789SRoy Zang static int32_t 2475aa070789SRoy Zang e1000_copper_link_igp_setup(struct e1000_hw *hw) 2476aa070789SRoy Zang { 2477aa070789SRoy Zang uint32_t led_ctrl; 2478aa070789SRoy Zang int32_t ret_val; 2479aa070789SRoy Zang uint16_t phy_data; 2480aa070789SRoy Zang 2481f81ecb5dSTimur Tabi DEBUGFUNC(); 2482aa070789SRoy Zang 2483aa070789SRoy Zang if (hw->phy_reset_disable) 2484aa070789SRoy Zang return E1000_SUCCESS; 2485aa070789SRoy Zang 2486aa070789SRoy Zang ret_val = e1000_phy_reset(hw); 2487aa070789SRoy Zang if (ret_val) { 2488aa070789SRoy Zang DEBUGOUT("Error Resetting the PHY\n"); 2489aa070789SRoy Zang return ret_val; 2490aa070789SRoy Zang } 2491aa070789SRoy Zang 2492aa070789SRoy Zang /* Wait 15ms for MAC to configure PHY from eeprom settings */ 2493aa070789SRoy Zang mdelay(15); 2494aa070789SRoy Zang if (hw->mac_type != e1000_ich8lan) { 2495aa070789SRoy Zang /* Configure activity LED after PHY reset */ 2496aa070789SRoy Zang led_ctrl = E1000_READ_REG(hw, LEDCTL); 2497aa070789SRoy Zang led_ctrl &= IGP_ACTIVITY_LED_MASK; 2498aa070789SRoy Zang led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); 2499aa070789SRoy Zang E1000_WRITE_REG(hw, LEDCTL, led_ctrl); 2500aa070789SRoy Zang } 2501aa070789SRoy Zang 2502aa070789SRoy Zang /* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */ 2503aa070789SRoy Zang if (hw->phy_type == e1000_phy_igp) { 2504aa070789SRoy Zang /* disable lplu d3 during driver init */ 2505472d5460SYork Sun ret_val = e1000_set_d3_lplu_state(hw, false); 2506aa070789SRoy Zang if (ret_val) { 2507aa070789SRoy Zang DEBUGOUT("Error Disabling LPLU D3\n"); 2508aa070789SRoy Zang return ret_val; 2509aa070789SRoy Zang } 2510aa070789SRoy Zang } 2511aa070789SRoy Zang 2512aa070789SRoy Zang /* disable lplu d0 during driver init */ 2513472d5460SYork Sun ret_val = e1000_set_d0_lplu_state(hw, false); 2514aa070789SRoy Zang if (ret_val) { 2515aa070789SRoy Zang DEBUGOUT("Error Disabling LPLU D0\n"); 2516aa070789SRoy Zang return ret_val; 2517aa070789SRoy Zang } 2518aa070789SRoy Zang /* Configure mdi-mdix settings */ 2519aa070789SRoy Zang ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); 2520aa070789SRoy Zang if (ret_val) 2521aa070789SRoy Zang return ret_val; 2522aa070789SRoy Zang 2523aa070789SRoy Zang if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { 2524aa070789SRoy Zang hw->dsp_config_state = e1000_dsp_config_disabled; 2525aa070789SRoy Zang /* Force MDI for earlier revs of the IGP PHY */ 2526aa070789SRoy Zang phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX 2527aa070789SRoy Zang | IGP01E1000_PSCR_FORCE_MDI_MDIX); 2528aa070789SRoy Zang hw->mdix = 1; 2529aa070789SRoy Zang 2530aa070789SRoy Zang } else { 2531aa070789SRoy Zang hw->dsp_config_state = e1000_dsp_config_enabled; 2532aa070789SRoy Zang phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; 2533aa070789SRoy Zang 2534aa070789SRoy Zang switch (hw->mdix) { 2535aa070789SRoy Zang case 1: 2536aa070789SRoy Zang phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; 2537aa070789SRoy Zang break; 2538aa070789SRoy Zang case 2: 2539aa070789SRoy Zang phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX; 2540aa070789SRoy Zang break; 2541aa070789SRoy Zang case 0: 2542aa070789SRoy Zang default: 2543aa070789SRoy Zang phy_data |= IGP01E1000_PSCR_AUTO_MDIX; 2544aa070789SRoy Zang break; 2545aa070789SRoy Zang } 2546aa070789SRoy Zang } 2547aa070789SRoy Zang ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); 2548aa070789SRoy Zang if (ret_val) 2549aa070789SRoy Zang return ret_val; 2550aa070789SRoy Zang 2551aa070789SRoy Zang /* set auto-master slave resolution settings */ 2552aa070789SRoy Zang if (hw->autoneg) { 2553aa070789SRoy Zang e1000_ms_type phy_ms_setting = hw->master_slave; 2554aa070789SRoy Zang 2555aa070789SRoy Zang if (hw->ffe_config_state == e1000_ffe_config_active) 2556aa070789SRoy Zang hw->ffe_config_state = e1000_ffe_config_enabled; 2557aa070789SRoy Zang 2558aa070789SRoy Zang if (hw->dsp_config_state == e1000_dsp_config_activated) 2559aa070789SRoy Zang hw->dsp_config_state = e1000_dsp_config_enabled; 2560aa070789SRoy Zang 2561aa070789SRoy Zang /* when autonegotiation advertisment is only 1000Mbps then we 2562aa070789SRoy Zang * should disable SmartSpeed and enable Auto MasterSlave 2563aa070789SRoy Zang * resolution as hardware default. */ 2564aa070789SRoy Zang if (hw->autoneg_advertised == ADVERTISE_1000_FULL) { 2565aa070789SRoy Zang /* Disable SmartSpeed */ 2566aa070789SRoy Zang ret_val = e1000_read_phy_reg(hw, 2567aa070789SRoy Zang IGP01E1000_PHY_PORT_CONFIG, &phy_data); 2568aa070789SRoy Zang if (ret_val) 2569aa070789SRoy Zang return ret_val; 2570aa070789SRoy Zang phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 2571aa070789SRoy Zang ret_val = e1000_write_phy_reg(hw, 2572aa070789SRoy Zang IGP01E1000_PHY_PORT_CONFIG, phy_data); 2573aa070789SRoy Zang if (ret_val) 2574aa070789SRoy Zang return ret_val; 2575aa070789SRoy Zang /* Set auto Master/Slave resolution process */ 2576aa070789SRoy Zang ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, 2577aa070789SRoy Zang &phy_data); 2578aa070789SRoy Zang if (ret_val) 2579aa070789SRoy Zang return ret_val; 2580aa070789SRoy Zang phy_data &= ~CR_1000T_MS_ENABLE; 2581aa070789SRoy Zang ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, 2582aa070789SRoy Zang phy_data); 2583aa070789SRoy Zang if (ret_val) 2584aa070789SRoy Zang return ret_val; 2585aa070789SRoy Zang } 2586aa070789SRoy Zang 2587aa070789SRoy Zang ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data); 2588aa070789SRoy Zang if (ret_val) 2589aa070789SRoy Zang return ret_val; 2590aa070789SRoy Zang 2591aa070789SRoy Zang /* load defaults for future use */ 2592aa070789SRoy Zang hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ? 2593aa070789SRoy Zang ((phy_data & CR_1000T_MS_VALUE) ? 2594aa070789SRoy Zang e1000_ms_force_master : 2595aa070789SRoy Zang e1000_ms_force_slave) : 2596aa070789SRoy Zang e1000_ms_auto; 2597aa070789SRoy Zang 2598aa070789SRoy Zang switch (phy_ms_setting) { 2599aa070789SRoy Zang case e1000_ms_force_master: 2600aa070789SRoy Zang phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE); 2601aa070789SRoy Zang break; 2602aa070789SRoy Zang case e1000_ms_force_slave: 2603aa070789SRoy Zang phy_data |= CR_1000T_MS_ENABLE; 2604aa070789SRoy Zang phy_data &= ~(CR_1000T_MS_VALUE); 2605aa070789SRoy Zang break; 2606aa070789SRoy Zang case e1000_ms_auto: 2607aa070789SRoy Zang phy_data &= ~CR_1000T_MS_ENABLE; 2608aa070789SRoy Zang default: 2609aa070789SRoy Zang break; 2610aa070789SRoy Zang } 2611aa070789SRoy Zang ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data); 2612aa070789SRoy Zang if (ret_val) 2613aa070789SRoy Zang return ret_val; 2614aa070789SRoy Zang } 2615aa070789SRoy Zang 2616aa070789SRoy Zang return E1000_SUCCESS; 2617aa070789SRoy Zang } 2618aa070789SRoy Zang 2619aa070789SRoy Zang /***************************************************************************** 2620aa070789SRoy Zang * This function checks the mode of the firmware. 2621aa070789SRoy Zang * 2622472d5460SYork Sun * returns - true when the mode is IAMT or false. 2623aa070789SRoy Zang ****************************************************************************/ 2624472d5460SYork Sun bool 2625aa070789SRoy Zang e1000_check_mng_mode(struct e1000_hw *hw) 2626aa070789SRoy Zang { 2627aa070789SRoy Zang uint32_t fwsm; 2628aa070789SRoy Zang DEBUGFUNC(); 2629aa070789SRoy Zang 2630aa070789SRoy Zang fwsm = E1000_READ_REG(hw, FWSM); 2631aa070789SRoy Zang 2632aa070789SRoy Zang if (hw->mac_type == e1000_ich8lan) { 2633aa070789SRoy Zang if ((fwsm & E1000_FWSM_MODE_MASK) == 2634aa070789SRoy Zang (E1000_MNG_ICH_IAMT_MODE << E1000_FWSM_MODE_SHIFT)) 2635472d5460SYork Sun return true; 2636aa070789SRoy Zang } else if ((fwsm & E1000_FWSM_MODE_MASK) == 2637aa070789SRoy Zang (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT)) 2638472d5460SYork Sun return true; 2639aa070789SRoy Zang 2640472d5460SYork Sun return false; 2641aa070789SRoy Zang } 2642aa070789SRoy Zang 2643aa070789SRoy Zang static int32_t 2644aa070789SRoy Zang e1000_write_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t data) 2645aa070789SRoy Zang { 2646987b43a1SKyle Moffett uint16_t swfw = E1000_SWFW_PHY0_SM; 2647aa070789SRoy Zang uint32_t reg_val; 2648aa070789SRoy Zang DEBUGFUNC(); 2649aa070789SRoy Zang 2650987b43a1SKyle Moffett if (e1000_is_second_port(hw)) 2651aa070789SRoy Zang swfw = E1000_SWFW_PHY1_SM; 2652987b43a1SKyle Moffett 2653aa070789SRoy Zang if (e1000_swfw_sync_acquire(hw, swfw)) 2654aa070789SRoy Zang return -E1000_ERR_SWFW_SYNC; 2655aa070789SRoy Zang 2656aa070789SRoy Zang reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) 2657aa070789SRoy Zang & E1000_KUMCTRLSTA_OFFSET) | data; 2658aa070789SRoy Zang E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val); 2659aa070789SRoy Zang udelay(2); 2660aa070789SRoy Zang 2661aa070789SRoy Zang return E1000_SUCCESS; 2662aa070789SRoy Zang } 2663aa070789SRoy Zang 2664aa070789SRoy Zang static int32_t 2665aa070789SRoy Zang e1000_read_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *data) 2666aa070789SRoy Zang { 2667987b43a1SKyle Moffett uint16_t swfw = E1000_SWFW_PHY0_SM; 2668aa070789SRoy Zang uint32_t reg_val; 2669aa070789SRoy Zang DEBUGFUNC(); 2670aa070789SRoy Zang 2671987b43a1SKyle Moffett if (e1000_is_second_port(hw)) 2672aa070789SRoy Zang swfw = E1000_SWFW_PHY1_SM; 2673987b43a1SKyle Moffett 267495186063SMarek Vasut if (e1000_swfw_sync_acquire(hw, swfw)) { 267595186063SMarek Vasut debug("%s[%i]\n", __func__, __LINE__); 2676aa070789SRoy Zang return -E1000_ERR_SWFW_SYNC; 267795186063SMarek Vasut } 2678aa070789SRoy Zang 2679aa070789SRoy Zang /* Write register address */ 2680aa070789SRoy Zang reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) & 2681aa070789SRoy Zang E1000_KUMCTRLSTA_OFFSET) | E1000_KUMCTRLSTA_REN; 2682aa070789SRoy Zang E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val); 2683aa070789SRoy Zang udelay(2); 2684aa070789SRoy Zang 2685aa070789SRoy Zang /* Read the data returned */ 2686aa070789SRoy Zang reg_val = E1000_READ_REG(hw, KUMCTRLSTA); 2687aa070789SRoy Zang *data = (uint16_t)reg_val; 2688aa070789SRoy Zang 2689aa070789SRoy Zang return E1000_SUCCESS; 2690aa070789SRoy Zang } 2691aa070789SRoy Zang 2692aa070789SRoy Zang /******************************************************************** 2693aa070789SRoy Zang * Copper link setup for e1000_phy_gg82563 series. 2694aa070789SRoy Zang * 2695aa070789SRoy Zang * hw - Struct containing variables accessed by shared code 2696aa070789SRoy Zang *********************************************************************/ 2697aa070789SRoy Zang static int32_t 2698aa070789SRoy Zang e1000_copper_link_ggp_setup(struct e1000_hw *hw) 2699aa070789SRoy Zang { 2700aa070789SRoy Zang int32_t ret_val; 2701aa070789SRoy Zang uint16_t phy_data; 2702aa070789SRoy Zang uint32_t reg_data; 2703aa070789SRoy Zang 2704aa070789SRoy Zang DEBUGFUNC(); 2705aa070789SRoy Zang 2706aa070789SRoy Zang if (!hw->phy_reset_disable) { 2707aa070789SRoy Zang /* Enable CRS on TX for half-duplex operation. */ 2708aa070789SRoy Zang ret_val = e1000_read_phy_reg(hw, 2709aa070789SRoy Zang GG82563_PHY_MAC_SPEC_CTRL, &phy_data); 2710aa070789SRoy Zang if (ret_val) 2711aa070789SRoy Zang return ret_val; 2712aa070789SRoy Zang 2713aa070789SRoy Zang phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX; 2714aa070789SRoy Zang /* Use 25MHz for both link down and 1000BASE-T for Tx clock */ 2715aa070789SRoy Zang phy_data |= GG82563_MSCR_TX_CLK_1000MBPS_25MHZ; 2716aa070789SRoy Zang 2717aa070789SRoy Zang ret_val = e1000_write_phy_reg(hw, 2718aa070789SRoy Zang GG82563_PHY_MAC_SPEC_CTRL, phy_data); 2719aa070789SRoy Zang if (ret_val) 2720aa070789SRoy Zang return ret_val; 2721aa070789SRoy Zang 2722aa070789SRoy Zang /* Options: 2723aa070789SRoy Zang * MDI/MDI-X = 0 (default) 2724aa070789SRoy Zang * 0 - Auto for all speeds 2725aa070789SRoy Zang * 1 - MDI mode 2726aa070789SRoy Zang * 2 - MDI-X mode 2727aa070789SRoy Zang * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) 2728aa070789SRoy Zang */ 2729aa070789SRoy Zang ret_val = e1000_read_phy_reg(hw, 2730aa070789SRoy Zang GG82563_PHY_SPEC_CTRL, &phy_data); 2731aa070789SRoy Zang if (ret_val) 2732aa070789SRoy Zang return ret_val; 2733aa070789SRoy Zang 2734aa070789SRoy Zang phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK; 2735aa070789SRoy Zang 2736aa070789SRoy Zang switch (hw->mdix) { 2737aa070789SRoy Zang case 1: 2738aa070789SRoy Zang phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDI; 2739aa070789SRoy Zang break; 2740aa070789SRoy Zang case 2: 2741aa070789SRoy Zang phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDIX; 2742aa070789SRoy Zang break; 2743aa070789SRoy Zang case 0: 2744aa070789SRoy Zang default: 2745aa070789SRoy Zang phy_data |= GG82563_PSCR_CROSSOVER_MODE_AUTO; 2746aa070789SRoy Zang break; 2747aa070789SRoy Zang } 2748aa070789SRoy Zang 2749aa070789SRoy Zang /* Options: 2750aa070789SRoy Zang * disable_polarity_correction = 0 (default) 2751aa070789SRoy Zang * Automatic Correction for Reversed Cable Polarity 2752aa070789SRoy Zang * 0 - Disabled 2753aa070789SRoy Zang * 1 - Enabled 2754aa070789SRoy Zang */ 2755aa070789SRoy Zang phy_data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE; 2756aa070789SRoy Zang ret_val = e1000_write_phy_reg(hw, 2757aa070789SRoy Zang GG82563_PHY_SPEC_CTRL, phy_data); 2758aa070789SRoy Zang 2759aa070789SRoy Zang if (ret_val) 2760aa070789SRoy Zang return ret_val; 2761aa070789SRoy Zang 2762aa070789SRoy Zang /* SW Reset the PHY so all changes take effect */ 2763aa070789SRoy Zang ret_val = e1000_phy_reset(hw); 2764aa070789SRoy Zang if (ret_val) { 2765aa070789SRoy Zang DEBUGOUT("Error Resetting the PHY\n"); 2766aa070789SRoy Zang return ret_val; 2767aa070789SRoy Zang } 2768aa070789SRoy Zang } /* phy_reset_disable */ 2769aa070789SRoy Zang 2770aa070789SRoy Zang if (hw->mac_type == e1000_80003es2lan) { 2771aa070789SRoy Zang /* Bypass RX and TX FIFO's */ 2772aa070789SRoy Zang ret_val = e1000_write_kmrn_reg(hw, 2773aa070789SRoy Zang E1000_KUMCTRLSTA_OFFSET_FIFO_CTRL, 2774aa070789SRoy Zang E1000_KUMCTRLSTA_FIFO_CTRL_RX_BYPASS 2775aa070789SRoy Zang | E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS); 2776aa070789SRoy Zang if (ret_val) 2777aa070789SRoy Zang return ret_val; 2778aa070789SRoy Zang 2779aa070789SRoy Zang ret_val = e1000_read_phy_reg(hw, 2780aa070789SRoy Zang GG82563_PHY_SPEC_CTRL_2, &phy_data); 2781aa070789SRoy Zang if (ret_val) 2782aa070789SRoy Zang return ret_val; 2783aa070789SRoy Zang 2784aa070789SRoy Zang phy_data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG; 2785aa070789SRoy Zang ret_val = e1000_write_phy_reg(hw, 2786aa070789SRoy Zang GG82563_PHY_SPEC_CTRL_2, phy_data); 2787aa070789SRoy Zang 2788aa070789SRoy Zang if (ret_val) 2789aa070789SRoy Zang return ret_val; 2790aa070789SRoy Zang 2791aa070789SRoy Zang reg_data = E1000_READ_REG(hw, CTRL_EXT); 2792aa070789SRoy Zang reg_data &= ~(E1000_CTRL_EXT_LINK_MODE_MASK); 2793aa070789SRoy Zang E1000_WRITE_REG(hw, CTRL_EXT, reg_data); 2794aa070789SRoy Zang 2795aa070789SRoy Zang ret_val = e1000_read_phy_reg(hw, 2796aa070789SRoy Zang GG82563_PHY_PWR_MGMT_CTRL, &phy_data); 2797aa070789SRoy Zang if (ret_val) 2798aa070789SRoy Zang return ret_val; 2799aa070789SRoy Zang 2800aa070789SRoy Zang /* Do not init these registers when the HW is in IAMT mode, since the 2801aa070789SRoy Zang * firmware will have already initialized them. We only initialize 2802aa070789SRoy Zang * them if the HW is not in IAMT mode. 2803aa070789SRoy Zang */ 2804472d5460SYork Sun if (e1000_check_mng_mode(hw) == false) { 2805aa070789SRoy Zang /* Enable Electrical Idle on the PHY */ 2806aa070789SRoy Zang phy_data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE; 2807aa070789SRoy Zang ret_val = e1000_write_phy_reg(hw, 2808aa070789SRoy Zang GG82563_PHY_PWR_MGMT_CTRL, phy_data); 2809aa070789SRoy Zang if (ret_val) 2810aa070789SRoy Zang return ret_val; 2811aa070789SRoy Zang 2812aa070789SRoy Zang ret_val = e1000_read_phy_reg(hw, 2813aa070789SRoy Zang GG82563_PHY_KMRN_MODE_CTRL, &phy_data); 2814aa070789SRoy Zang if (ret_val) 2815aa070789SRoy Zang return ret_val; 2816aa070789SRoy Zang 2817aa070789SRoy Zang phy_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; 2818aa070789SRoy Zang ret_val = e1000_write_phy_reg(hw, 2819aa070789SRoy Zang GG82563_PHY_KMRN_MODE_CTRL, phy_data); 2820aa070789SRoy Zang 2821aa070789SRoy Zang if (ret_val) 2822aa070789SRoy Zang return ret_val; 2823aa070789SRoy Zang } 2824aa070789SRoy Zang 2825aa070789SRoy Zang /* Workaround: Disable padding in Kumeran interface in the MAC 2826aa070789SRoy Zang * and in the PHY to avoid CRC errors. 2827aa070789SRoy Zang */ 2828aa070789SRoy Zang ret_val = e1000_read_phy_reg(hw, 2829aa070789SRoy Zang GG82563_PHY_INBAND_CTRL, &phy_data); 2830aa070789SRoy Zang if (ret_val) 2831aa070789SRoy Zang return ret_val; 2832aa070789SRoy Zang phy_data |= GG82563_ICR_DIS_PADDING; 2833aa070789SRoy Zang ret_val = e1000_write_phy_reg(hw, 2834aa070789SRoy Zang GG82563_PHY_INBAND_CTRL, phy_data); 2835aa070789SRoy Zang if (ret_val) 2836aa070789SRoy Zang return ret_val; 2837aa070789SRoy Zang } 2838aa070789SRoy Zang return E1000_SUCCESS; 2839aa070789SRoy Zang } 2840aa070789SRoy Zang 2841aa070789SRoy Zang /******************************************************************** 2842aa070789SRoy Zang * Copper link setup for e1000_phy_m88 series. 2843aa070789SRoy Zang * 2844aa070789SRoy Zang * hw - Struct containing variables accessed by shared code 2845aa070789SRoy Zang *********************************************************************/ 2846aa070789SRoy Zang static int32_t 2847aa070789SRoy Zang e1000_copper_link_mgp_setup(struct e1000_hw *hw) 2848aa070789SRoy Zang { 2849aa070789SRoy Zang int32_t ret_val; 2850aa070789SRoy Zang uint16_t phy_data; 2851aa070789SRoy Zang 2852aa070789SRoy Zang DEBUGFUNC(); 2853aa070789SRoy Zang 2854aa070789SRoy Zang if (hw->phy_reset_disable) 2855aa070789SRoy Zang return E1000_SUCCESS; 2856aa070789SRoy Zang 2857aa070789SRoy Zang /* Enable CRS on TX. This must be set for half-duplex operation. */ 2858aa070789SRoy Zang ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 2859aa070789SRoy Zang if (ret_val) 2860aa070789SRoy Zang return ret_val; 2861aa070789SRoy Zang 28622439e4bfSJean-Christophe PLAGNIOL-VILLARD phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; 28632439e4bfSJean-Christophe PLAGNIOL-VILLARD 28642439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Options: 28652439e4bfSJean-Christophe PLAGNIOL-VILLARD * MDI/MDI-X = 0 (default) 28662439e4bfSJean-Christophe PLAGNIOL-VILLARD * 0 - Auto for all speeds 28672439e4bfSJean-Christophe PLAGNIOL-VILLARD * 1 - MDI mode 28682439e4bfSJean-Christophe PLAGNIOL-VILLARD * 2 - MDI-X mode 28692439e4bfSJean-Christophe PLAGNIOL-VILLARD * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) 28702439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 28712439e4bfSJean-Christophe PLAGNIOL-VILLARD phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 2872aa070789SRoy Zang 28732439e4bfSJean-Christophe PLAGNIOL-VILLARD switch (hw->mdix) { 28742439e4bfSJean-Christophe PLAGNIOL-VILLARD case 1: 28752439e4bfSJean-Christophe PLAGNIOL-VILLARD phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; 28762439e4bfSJean-Christophe PLAGNIOL-VILLARD break; 28772439e4bfSJean-Christophe PLAGNIOL-VILLARD case 2: 28782439e4bfSJean-Christophe PLAGNIOL-VILLARD phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; 28792439e4bfSJean-Christophe PLAGNIOL-VILLARD break; 28802439e4bfSJean-Christophe PLAGNIOL-VILLARD case 3: 28812439e4bfSJean-Christophe PLAGNIOL-VILLARD phy_data |= M88E1000_PSCR_AUTO_X_1000T; 28822439e4bfSJean-Christophe PLAGNIOL-VILLARD break; 28832439e4bfSJean-Christophe PLAGNIOL-VILLARD case 0: 28842439e4bfSJean-Christophe PLAGNIOL-VILLARD default: 28852439e4bfSJean-Christophe PLAGNIOL-VILLARD phy_data |= M88E1000_PSCR_AUTO_X_MODE; 28862439e4bfSJean-Christophe PLAGNIOL-VILLARD break; 28872439e4bfSJean-Christophe PLAGNIOL-VILLARD } 28882439e4bfSJean-Christophe PLAGNIOL-VILLARD 28892439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Options: 28902439e4bfSJean-Christophe PLAGNIOL-VILLARD * disable_polarity_correction = 0 (default) 28912439e4bfSJean-Christophe PLAGNIOL-VILLARD * Automatic Correction for Reversed Cable Polarity 28922439e4bfSJean-Christophe PLAGNIOL-VILLARD * 0 - Disabled 28932439e4bfSJean-Christophe PLAGNIOL-VILLARD * 1 - Enabled 28942439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 28952439e4bfSJean-Christophe PLAGNIOL-VILLARD phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; 2896aa070789SRoy Zang ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 2897aa070789SRoy Zang if (ret_val) 2898aa070789SRoy Zang return ret_val; 28992439e4bfSJean-Christophe PLAGNIOL-VILLARD 2900aa070789SRoy Zang if (hw->phy_revision < M88E1011_I_REV_4) { 29012439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Force TX_CLK in the Extended PHY Specific Control Register 29022439e4bfSJean-Christophe PLAGNIOL-VILLARD * to 25MHz clock. 29032439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 2904aa070789SRoy Zang ret_val = e1000_read_phy_reg(hw, 2905aa070789SRoy Zang M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); 2906aa070789SRoy Zang if (ret_val) 2907aa070789SRoy Zang return ret_val; 2908aa070789SRoy Zang 29092439e4bfSJean-Christophe PLAGNIOL-VILLARD phy_data |= M88E1000_EPSCR_TX_CLK_25; 2910aa070789SRoy Zang 2911aa070789SRoy Zang if ((hw->phy_revision == E1000_REVISION_2) && 2912aa070789SRoy Zang (hw->phy_id == M88E1111_I_PHY_ID)) { 2913aa070789SRoy Zang /* Vidalia Phy, set the downshift counter to 5x */ 2914aa070789SRoy Zang phy_data &= ~(M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK); 2915aa070789SRoy Zang phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X; 2916aa070789SRoy Zang ret_val = e1000_write_phy_reg(hw, 2917aa070789SRoy Zang M88E1000_EXT_PHY_SPEC_CTRL, phy_data); 2918aa070789SRoy Zang if (ret_val) 2919aa070789SRoy Zang return ret_val; 2920aa070789SRoy Zang } else { 29212439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Configure Master and Slave downshift values */ 2922aa070789SRoy Zang phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 2923aa070789SRoy Zang | M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK); 2924aa070789SRoy Zang phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X 2925aa070789SRoy Zang | M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X); 2926aa070789SRoy Zang ret_val = e1000_write_phy_reg(hw, 2927aa070789SRoy Zang M88E1000_EXT_PHY_SPEC_CTRL, phy_data); 2928aa070789SRoy Zang if (ret_val) 2929aa070789SRoy Zang return ret_val; 2930aa070789SRoy Zang } 29312439e4bfSJean-Christophe PLAGNIOL-VILLARD } 29322439e4bfSJean-Christophe PLAGNIOL-VILLARD 29332439e4bfSJean-Christophe PLAGNIOL-VILLARD /* SW Reset the PHY so all changes take effect */ 29342439e4bfSJean-Christophe PLAGNIOL-VILLARD ret_val = e1000_phy_reset(hw); 2935aa070789SRoy Zang if (ret_val) { 29362439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("Error Resetting the PHY\n"); 29372439e4bfSJean-Christophe PLAGNIOL-VILLARD return ret_val; 29382439e4bfSJean-Christophe PLAGNIOL-VILLARD } 29392439e4bfSJean-Christophe PLAGNIOL-VILLARD 2940aa070789SRoy Zang return E1000_SUCCESS; 2941aa070789SRoy Zang } 29422439e4bfSJean-Christophe PLAGNIOL-VILLARD 2943aa070789SRoy Zang /******************************************************************** 2944aa070789SRoy Zang * Setup auto-negotiation and flow control advertisements, 2945aa070789SRoy Zang * and then perform auto-negotiation. 2946aa070789SRoy Zang * 2947aa070789SRoy Zang * hw - Struct containing variables accessed by shared code 2948aa070789SRoy Zang *********************************************************************/ 2949aa070789SRoy Zang static int32_t 2950aa070789SRoy Zang e1000_copper_link_autoneg(struct e1000_hw *hw) 2951aa070789SRoy Zang { 2952aa070789SRoy Zang int32_t ret_val; 2953aa070789SRoy Zang uint16_t phy_data; 2954aa070789SRoy Zang 2955aa070789SRoy Zang DEBUGFUNC(); 2956aa070789SRoy Zang 29572439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Perform some bounds checking on the hw->autoneg_advertised 29582439e4bfSJean-Christophe PLAGNIOL-VILLARD * parameter. If this variable is zero, then set it to the default. 29592439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 29602439e4bfSJean-Christophe PLAGNIOL-VILLARD hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT; 29612439e4bfSJean-Christophe PLAGNIOL-VILLARD 29622439e4bfSJean-Christophe PLAGNIOL-VILLARD /* If autoneg_advertised is zero, we assume it was not defaulted 29632439e4bfSJean-Christophe PLAGNIOL-VILLARD * by the calling code so we set to advertise full capability. 29642439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 29652439e4bfSJean-Christophe PLAGNIOL-VILLARD if (hw->autoneg_advertised == 0) 29662439e4bfSJean-Christophe PLAGNIOL-VILLARD hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT; 29672439e4bfSJean-Christophe PLAGNIOL-VILLARD 2968aa070789SRoy Zang /* IFE phy only supports 10/100 */ 2969aa070789SRoy Zang if (hw->phy_type == e1000_phy_ife) 2970aa070789SRoy Zang hw->autoneg_advertised &= AUTONEG_ADVERTISE_10_100_ALL; 2971aa070789SRoy Zang 29722439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("Reconfiguring auto-neg advertisement params\n"); 29732439e4bfSJean-Christophe PLAGNIOL-VILLARD ret_val = e1000_phy_setup_autoneg(hw); 2974aa070789SRoy Zang if (ret_val) { 29752439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("Error Setting up Auto-Negotiation\n"); 29762439e4bfSJean-Christophe PLAGNIOL-VILLARD return ret_val; 29772439e4bfSJean-Christophe PLAGNIOL-VILLARD } 29782439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("Restarting Auto-Neg\n"); 29792439e4bfSJean-Christophe PLAGNIOL-VILLARD 29802439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Restart auto-negotiation by setting the Auto Neg Enable bit and 29812439e4bfSJean-Christophe PLAGNIOL-VILLARD * the Auto Neg Restart bit in the PHY control register. 29822439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 2983aa070789SRoy Zang ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data); 2984aa070789SRoy Zang if (ret_val) 2985aa070789SRoy Zang return ret_val; 2986aa070789SRoy Zang 29872439e4bfSJean-Christophe PLAGNIOL-VILLARD phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); 2988aa070789SRoy Zang ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data); 2989aa070789SRoy Zang if (ret_val) 2990aa070789SRoy Zang return ret_val; 2991aa070789SRoy Zang 29922439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Does the user want to wait for Auto-Neg to complete here, or 29932439e4bfSJean-Christophe PLAGNIOL-VILLARD * check at a later time (for example, callback routine). 29942439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 29952439e4bfSJean-Christophe PLAGNIOL-VILLARD /* If we do not wait for autonegtation to complete I 29962439e4bfSJean-Christophe PLAGNIOL-VILLARD * do not see a valid link status. 2997aa070789SRoy Zang * wait_autoneg_complete = 1 . 29982439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 2999aa070789SRoy Zang if (hw->wait_autoneg_complete) { 30002439e4bfSJean-Christophe PLAGNIOL-VILLARD ret_val = e1000_wait_autoneg(hw); 3001aa070789SRoy Zang if (ret_val) { 3002aa070789SRoy Zang DEBUGOUT("Error while waiting for autoneg" 3003aa070789SRoy Zang "to complete\n"); 30042439e4bfSJean-Christophe PLAGNIOL-VILLARD return ret_val; 30052439e4bfSJean-Christophe PLAGNIOL-VILLARD } 3006aa070789SRoy Zang } 30072439e4bfSJean-Christophe PLAGNIOL-VILLARD 3008472d5460SYork Sun hw->get_link_status = true; 3009aa070789SRoy Zang 3010aa070789SRoy Zang return E1000_SUCCESS; 30112439e4bfSJean-Christophe PLAGNIOL-VILLARD } 3012aa070789SRoy Zang 3013aa070789SRoy Zang /****************************************************************************** 3014aa070789SRoy Zang * Config the MAC and the PHY after link is up. 30152439e4bfSJean-Christophe PLAGNIOL-VILLARD * 1) Set up the MAC to the current PHY speed/duplex 30162439e4bfSJean-Christophe PLAGNIOL-VILLARD * if we are on 82543. If we 30172439e4bfSJean-Christophe PLAGNIOL-VILLARD * are on newer silicon, we only need to configure 30182439e4bfSJean-Christophe PLAGNIOL-VILLARD * collision distance in the Transmit Control Register. 30192439e4bfSJean-Christophe PLAGNIOL-VILLARD * 2) Set up flow control on the MAC to that established with 30202439e4bfSJean-Christophe PLAGNIOL-VILLARD * the link partner. 3021aa070789SRoy Zang * 3) Config DSP to improve Gigabit link quality for some PHY revisions. 3022aa070789SRoy Zang * 3023aa070789SRoy Zang * hw - Struct containing variables accessed by shared code 3024aa070789SRoy Zang ******************************************************************************/ 3025aa070789SRoy Zang static int32_t 3026aa070789SRoy Zang e1000_copper_link_postconfig(struct e1000_hw *hw) 3027aa070789SRoy Zang { 3028aa070789SRoy Zang int32_t ret_val; 3029aa070789SRoy Zang DEBUGFUNC(); 3030aa070789SRoy Zang 30312439e4bfSJean-Christophe PLAGNIOL-VILLARD if (hw->mac_type >= e1000_82544) { 30322439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_config_collision_dist(hw); 30332439e4bfSJean-Christophe PLAGNIOL-VILLARD } else { 30342439e4bfSJean-Christophe PLAGNIOL-VILLARD ret_val = e1000_config_mac_to_phy(hw); 3035aa070789SRoy Zang if (ret_val) { 3036aa070789SRoy Zang DEBUGOUT("Error configuring MAC to PHY settings\n"); 30372439e4bfSJean-Christophe PLAGNIOL-VILLARD return ret_val; 30382439e4bfSJean-Christophe PLAGNIOL-VILLARD } 30392439e4bfSJean-Christophe PLAGNIOL-VILLARD } 30402439e4bfSJean-Christophe PLAGNIOL-VILLARD ret_val = e1000_config_fc_after_link_up(hw); 3041aa070789SRoy Zang if (ret_val) { 30422439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("Error Configuring Flow Control\n"); 30432439e4bfSJean-Christophe PLAGNIOL-VILLARD return ret_val; 30442439e4bfSJean-Christophe PLAGNIOL-VILLARD } 3045aa070789SRoy Zang return E1000_SUCCESS; 3046aa070789SRoy Zang } 3047aa070789SRoy Zang 3048aa070789SRoy Zang /****************************************************************************** 3049aa070789SRoy Zang * Detects which PHY is present and setup the speed and duplex 3050aa070789SRoy Zang * 3051aa070789SRoy Zang * hw - Struct containing variables accessed by shared code 3052aa070789SRoy Zang ******************************************************************************/ 3053aa070789SRoy Zang static int 30545c5e707aSSimon Glass e1000_setup_copper_link(struct e1000_hw *hw) 3055aa070789SRoy Zang { 3056aa070789SRoy Zang int32_t ret_val; 3057aa070789SRoy Zang uint16_t i; 3058aa070789SRoy Zang uint16_t phy_data; 3059aa070789SRoy Zang uint16_t reg_data; 3060aa070789SRoy Zang 3061aa070789SRoy Zang DEBUGFUNC(); 3062aa070789SRoy Zang 3063aa070789SRoy Zang switch (hw->mac_type) { 3064aa070789SRoy Zang case e1000_80003es2lan: 3065aa070789SRoy Zang case e1000_ich8lan: 3066aa070789SRoy Zang /* Set the mac to wait the maximum time between each 3067aa070789SRoy Zang * iteration and increase the max iterations when 3068aa070789SRoy Zang * polling the phy; this fixes erroneous timeouts at 10Mbps. */ 3069aa070789SRoy Zang ret_val = e1000_write_kmrn_reg(hw, 3070aa070789SRoy Zang GG82563_REG(0x34, 4), 0xFFFF); 3071aa070789SRoy Zang if (ret_val) 3072aa070789SRoy Zang return ret_val; 3073aa070789SRoy Zang ret_val = e1000_read_kmrn_reg(hw, 3074aa070789SRoy Zang GG82563_REG(0x34, 9), ®_data); 3075aa070789SRoy Zang if (ret_val) 3076aa070789SRoy Zang return ret_val; 3077aa070789SRoy Zang reg_data |= 0x3F; 3078aa070789SRoy Zang ret_val = e1000_write_kmrn_reg(hw, 3079aa070789SRoy Zang GG82563_REG(0x34, 9), reg_data); 3080aa070789SRoy Zang if (ret_val) 3081aa070789SRoy Zang return ret_val; 3082aa070789SRoy Zang default: 3083aa070789SRoy Zang break; 3084aa070789SRoy Zang } 3085aa070789SRoy Zang 3086aa070789SRoy Zang /* Check if it is a valid PHY and set PHY mode if necessary. */ 3087aa070789SRoy Zang ret_val = e1000_copper_link_preconfig(hw); 3088aa070789SRoy Zang if (ret_val) 3089aa070789SRoy Zang return ret_val; 3090aa070789SRoy Zang switch (hw->mac_type) { 3091aa070789SRoy Zang case e1000_80003es2lan: 3092aa070789SRoy Zang /* Kumeran registers are written-only */ 3093aa070789SRoy Zang reg_data = 3094aa070789SRoy Zang E1000_KUMCTRLSTA_INB_CTRL_LINK_STATUS_TX_TIMEOUT_DEFAULT; 3095aa070789SRoy Zang reg_data |= E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING; 3096aa070789SRoy Zang ret_val = e1000_write_kmrn_reg(hw, 3097aa070789SRoy Zang E1000_KUMCTRLSTA_OFFSET_INB_CTRL, reg_data); 3098aa070789SRoy Zang if (ret_val) 3099aa070789SRoy Zang return ret_val; 3100aa070789SRoy Zang break; 3101aa070789SRoy Zang default: 3102aa070789SRoy Zang break; 3103aa070789SRoy Zang } 3104aa070789SRoy Zang 3105aa070789SRoy Zang if (hw->phy_type == e1000_phy_igp || 3106aa070789SRoy Zang hw->phy_type == e1000_phy_igp_3 || 3107aa070789SRoy Zang hw->phy_type == e1000_phy_igp_2) { 3108aa070789SRoy Zang ret_val = e1000_copper_link_igp_setup(hw); 3109aa070789SRoy Zang if (ret_val) 3110aa070789SRoy Zang return ret_val; 311195186063SMarek Vasut } else if (hw->phy_type == e1000_phy_m88 || 311295186063SMarek Vasut hw->phy_type == e1000_phy_igb) { 3113aa070789SRoy Zang ret_val = e1000_copper_link_mgp_setup(hw); 3114aa070789SRoy Zang if (ret_val) 3115aa070789SRoy Zang return ret_val; 3116aa070789SRoy Zang } else if (hw->phy_type == e1000_phy_gg82563) { 3117aa070789SRoy Zang ret_val = e1000_copper_link_ggp_setup(hw); 3118aa070789SRoy Zang if (ret_val) 3119aa070789SRoy Zang return ret_val; 3120aa070789SRoy Zang } 3121aa070789SRoy Zang 3122aa070789SRoy Zang /* always auto */ 3123aa070789SRoy Zang /* Setup autoneg and flow control advertisement 3124aa070789SRoy Zang * and perform autonegotiation */ 3125aa070789SRoy Zang ret_val = e1000_copper_link_autoneg(hw); 3126aa070789SRoy Zang if (ret_val) 3127aa070789SRoy Zang return ret_val; 3128aa070789SRoy Zang 3129aa070789SRoy Zang /* Check link status. Wait up to 100 microseconds for link to become 3130aa070789SRoy Zang * valid. 3131aa070789SRoy Zang */ 3132aa070789SRoy Zang for (i = 0; i < 10; i++) { 3133aa070789SRoy Zang ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); 3134aa070789SRoy Zang if (ret_val) 3135aa070789SRoy Zang return ret_val; 3136aa070789SRoy Zang ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); 3137aa070789SRoy Zang if (ret_val) 3138aa070789SRoy Zang return ret_val; 3139aa070789SRoy Zang 3140aa070789SRoy Zang if (phy_data & MII_SR_LINK_STATUS) { 3141aa070789SRoy Zang /* Config the MAC and PHY after link is up */ 3142aa070789SRoy Zang ret_val = e1000_copper_link_postconfig(hw); 3143aa070789SRoy Zang if (ret_val) 3144aa070789SRoy Zang return ret_val; 3145aa070789SRoy Zang 31462439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("Valid link established!!!\n"); 3147aa070789SRoy Zang return E1000_SUCCESS; 31482439e4bfSJean-Christophe PLAGNIOL-VILLARD } 31492439e4bfSJean-Christophe PLAGNIOL-VILLARD udelay(10); 31502439e4bfSJean-Christophe PLAGNIOL-VILLARD } 31512439e4bfSJean-Christophe PLAGNIOL-VILLARD 31522439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("Unable to establish link!!!\n"); 3153aa070789SRoy Zang return E1000_SUCCESS; 31542439e4bfSJean-Christophe PLAGNIOL-VILLARD } 31552439e4bfSJean-Christophe PLAGNIOL-VILLARD 31562439e4bfSJean-Christophe PLAGNIOL-VILLARD /****************************************************************************** 31572439e4bfSJean-Christophe PLAGNIOL-VILLARD * Configures PHY autoneg and flow control advertisement settings 31582439e4bfSJean-Christophe PLAGNIOL-VILLARD * 31592439e4bfSJean-Christophe PLAGNIOL-VILLARD * hw - Struct containing variables accessed by shared code 31602439e4bfSJean-Christophe PLAGNIOL-VILLARD ******************************************************************************/ 3161aa070789SRoy Zang int32_t 31622439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_phy_setup_autoneg(struct e1000_hw *hw) 31632439e4bfSJean-Christophe PLAGNIOL-VILLARD { 3164aa070789SRoy Zang int32_t ret_val; 31652439e4bfSJean-Christophe PLAGNIOL-VILLARD uint16_t mii_autoneg_adv_reg; 31662439e4bfSJean-Christophe PLAGNIOL-VILLARD uint16_t mii_1000t_ctrl_reg; 31672439e4bfSJean-Christophe PLAGNIOL-VILLARD 31682439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGFUNC(); 31692439e4bfSJean-Christophe PLAGNIOL-VILLARD 31702439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Read the MII Auto-Neg Advertisement Register (Address 4). */ 3171aa070789SRoy Zang ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg); 3172aa070789SRoy Zang if (ret_val) 3173aa070789SRoy Zang return ret_val; 31742439e4bfSJean-Christophe PLAGNIOL-VILLARD 3175aa070789SRoy Zang if (hw->phy_type != e1000_phy_ife) { 31762439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Read the MII 1000Base-T Control Register (Address 9). */ 3177aa070789SRoy Zang ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, 3178aa070789SRoy Zang &mii_1000t_ctrl_reg); 3179aa070789SRoy Zang if (ret_val) 3180aa070789SRoy Zang return ret_val; 3181aa070789SRoy Zang } else 3182aa070789SRoy Zang mii_1000t_ctrl_reg = 0; 31832439e4bfSJean-Christophe PLAGNIOL-VILLARD 31842439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Need to parse both autoneg_advertised and fc and set up 31852439e4bfSJean-Christophe PLAGNIOL-VILLARD * the appropriate PHY registers. First we will parse for 31862439e4bfSJean-Christophe PLAGNIOL-VILLARD * autoneg_advertised software override. Since we can advertise 31872439e4bfSJean-Christophe PLAGNIOL-VILLARD * a plethora of combinations, we need to check each bit 31882439e4bfSJean-Christophe PLAGNIOL-VILLARD * individually. 31892439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 31902439e4bfSJean-Christophe PLAGNIOL-VILLARD 31912439e4bfSJean-Christophe PLAGNIOL-VILLARD /* First we clear all the 10/100 mb speed bits in the Auto-Neg 31922439e4bfSJean-Christophe PLAGNIOL-VILLARD * Advertisement Register (Address 4) and the 1000 mb speed bits in 31932439e4bfSJean-Christophe PLAGNIOL-VILLARD * the 1000Base-T Control Register (Address 9). 31942439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 31952439e4bfSJean-Christophe PLAGNIOL-VILLARD mii_autoneg_adv_reg &= ~REG4_SPEED_MASK; 31962439e4bfSJean-Christophe PLAGNIOL-VILLARD mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK; 31972439e4bfSJean-Christophe PLAGNIOL-VILLARD 31982439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("autoneg_advertised %x\n", hw->autoneg_advertised); 31992439e4bfSJean-Christophe PLAGNIOL-VILLARD 32002439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Do we want to advertise 10 Mb Half Duplex? */ 32012439e4bfSJean-Christophe PLAGNIOL-VILLARD if (hw->autoneg_advertised & ADVERTISE_10_HALF) { 32022439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("Advertise 10mb Half duplex\n"); 32032439e4bfSJean-Christophe PLAGNIOL-VILLARD mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS; 32042439e4bfSJean-Christophe PLAGNIOL-VILLARD } 32052439e4bfSJean-Christophe PLAGNIOL-VILLARD 32062439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Do we want to advertise 10 Mb Full Duplex? */ 32072439e4bfSJean-Christophe PLAGNIOL-VILLARD if (hw->autoneg_advertised & ADVERTISE_10_FULL) { 32082439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("Advertise 10mb Full duplex\n"); 32092439e4bfSJean-Christophe PLAGNIOL-VILLARD mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS; 32102439e4bfSJean-Christophe PLAGNIOL-VILLARD } 32112439e4bfSJean-Christophe PLAGNIOL-VILLARD 32122439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Do we want to advertise 100 Mb Half Duplex? */ 32132439e4bfSJean-Christophe PLAGNIOL-VILLARD if (hw->autoneg_advertised & ADVERTISE_100_HALF) { 32142439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("Advertise 100mb Half duplex\n"); 32152439e4bfSJean-Christophe PLAGNIOL-VILLARD mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS; 32162439e4bfSJean-Christophe PLAGNIOL-VILLARD } 32172439e4bfSJean-Christophe PLAGNIOL-VILLARD 32182439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Do we want to advertise 100 Mb Full Duplex? */ 32192439e4bfSJean-Christophe PLAGNIOL-VILLARD if (hw->autoneg_advertised & ADVERTISE_100_FULL) { 32202439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("Advertise 100mb Full duplex\n"); 32212439e4bfSJean-Christophe PLAGNIOL-VILLARD mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS; 32222439e4bfSJean-Christophe PLAGNIOL-VILLARD } 32232439e4bfSJean-Christophe PLAGNIOL-VILLARD 32242439e4bfSJean-Christophe PLAGNIOL-VILLARD /* We do not allow the Phy to advertise 1000 Mb Half Duplex */ 32252439e4bfSJean-Christophe PLAGNIOL-VILLARD if (hw->autoneg_advertised & ADVERTISE_1000_HALF) { 32262439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT 32272439e4bfSJean-Christophe PLAGNIOL-VILLARD ("Advertise 1000mb Half duplex requested, request denied!\n"); 32282439e4bfSJean-Christophe PLAGNIOL-VILLARD } 32292439e4bfSJean-Christophe PLAGNIOL-VILLARD 32302439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Do we want to advertise 1000 Mb Full Duplex? */ 32312439e4bfSJean-Christophe PLAGNIOL-VILLARD if (hw->autoneg_advertised & ADVERTISE_1000_FULL) { 32322439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("Advertise 1000mb Full duplex\n"); 32332439e4bfSJean-Christophe PLAGNIOL-VILLARD mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS; 32342439e4bfSJean-Christophe PLAGNIOL-VILLARD } 32352439e4bfSJean-Christophe PLAGNIOL-VILLARD 32362439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Check for a software override of the flow control settings, and 32372439e4bfSJean-Christophe PLAGNIOL-VILLARD * setup the PHY advertisement registers accordingly. If 32382439e4bfSJean-Christophe PLAGNIOL-VILLARD * auto-negotiation is enabled, then software will have to set the 32392439e4bfSJean-Christophe PLAGNIOL-VILLARD * "PAUSE" bits to the correct value in the Auto-Negotiation 32402439e4bfSJean-Christophe PLAGNIOL-VILLARD * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation. 32412439e4bfSJean-Christophe PLAGNIOL-VILLARD * 32422439e4bfSJean-Christophe PLAGNIOL-VILLARD * The possible values of the "fc" parameter are: 32432439e4bfSJean-Christophe PLAGNIOL-VILLARD * 0: Flow control is completely disabled 32442439e4bfSJean-Christophe PLAGNIOL-VILLARD * 1: Rx flow control is enabled (we can receive pause frames 32452439e4bfSJean-Christophe PLAGNIOL-VILLARD * but not send pause frames). 32462439e4bfSJean-Christophe PLAGNIOL-VILLARD * 2: Tx flow control is enabled (we can send pause frames 32472439e4bfSJean-Christophe PLAGNIOL-VILLARD * but we do not support receiving pause frames). 32482439e4bfSJean-Christophe PLAGNIOL-VILLARD * 3: Both Rx and TX flow control (symmetric) are enabled. 32492439e4bfSJean-Christophe PLAGNIOL-VILLARD * other: No software override. The flow control configuration 32502439e4bfSJean-Christophe PLAGNIOL-VILLARD * in the EEPROM is used. 32512439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 32522439e4bfSJean-Christophe PLAGNIOL-VILLARD switch (hw->fc) { 32532439e4bfSJean-Christophe PLAGNIOL-VILLARD case e1000_fc_none: /* 0 */ 32542439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Flow control (RX & TX) is completely disabled by a 32552439e4bfSJean-Christophe PLAGNIOL-VILLARD * software over-ride. 32562439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 32572439e4bfSJean-Christophe PLAGNIOL-VILLARD mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 32582439e4bfSJean-Christophe PLAGNIOL-VILLARD break; 32592439e4bfSJean-Christophe PLAGNIOL-VILLARD case e1000_fc_rx_pause: /* 1 */ 32602439e4bfSJean-Christophe PLAGNIOL-VILLARD /* RX Flow control is enabled, and TX Flow control is 32612439e4bfSJean-Christophe PLAGNIOL-VILLARD * disabled, by a software over-ride. 32622439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 32632439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Since there really isn't a way to advertise that we are 32642439e4bfSJean-Christophe PLAGNIOL-VILLARD * capable of RX Pause ONLY, we will advertise that we 32652439e4bfSJean-Christophe PLAGNIOL-VILLARD * support both symmetric and asymmetric RX PAUSE. Later 32662439e4bfSJean-Christophe PLAGNIOL-VILLARD * (in e1000_config_fc_after_link_up) we will disable the 32672439e4bfSJean-Christophe PLAGNIOL-VILLARD *hw's ability to send PAUSE frames. 32682439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 32692439e4bfSJean-Christophe PLAGNIOL-VILLARD mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 32702439e4bfSJean-Christophe PLAGNIOL-VILLARD break; 32712439e4bfSJean-Christophe PLAGNIOL-VILLARD case e1000_fc_tx_pause: /* 2 */ 32722439e4bfSJean-Christophe PLAGNIOL-VILLARD /* TX Flow control is enabled, and RX Flow control is 32732439e4bfSJean-Christophe PLAGNIOL-VILLARD * disabled, by a software over-ride. 32742439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 32752439e4bfSJean-Christophe PLAGNIOL-VILLARD mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR; 32762439e4bfSJean-Christophe PLAGNIOL-VILLARD mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE; 32772439e4bfSJean-Christophe PLAGNIOL-VILLARD break; 32782439e4bfSJean-Christophe PLAGNIOL-VILLARD case e1000_fc_full: /* 3 */ 32792439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Flow control (both RX and TX) is enabled by a software 32802439e4bfSJean-Christophe PLAGNIOL-VILLARD * over-ride. 32812439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 32822439e4bfSJean-Christophe PLAGNIOL-VILLARD mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 32832439e4bfSJean-Christophe PLAGNIOL-VILLARD break; 32842439e4bfSJean-Christophe PLAGNIOL-VILLARD default: 32852439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("Flow control param set incorrectly\n"); 32862439e4bfSJean-Christophe PLAGNIOL-VILLARD return -E1000_ERR_CONFIG; 32872439e4bfSJean-Christophe PLAGNIOL-VILLARD } 32882439e4bfSJean-Christophe PLAGNIOL-VILLARD 3289aa070789SRoy Zang ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg); 3290aa070789SRoy Zang if (ret_val) 3291aa070789SRoy Zang return ret_val; 32922439e4bfSJean-Christophe PLAGNIOL-VILLARD 32932439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); 32942439e4bfSJean-Christophe PLAGNIOL-VILLARD 3295aa070789SRoy Zang if (hw->phy_type != e1000_phy_ife) { 3296aa070789SRoy Zang ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, 3297aa070789SRoy Zang mii_1000t_ctrl_reg); 3298aa070789SRoy Zang if (ret_val) 3299aa070789SRoy Zang return ret_val; 33002439e4bfSJean-Christophe PLAGNIOL-VILLARD } 3301aa070789SRoy Zang 3302aa070789SRoy Zang return E1000_SUCCESS; 33032439e4bfSJean-Christophe PLAGNIOL-VILLARD } 33042439e4bfSJean-Christophe PLAGNIOL-VILLARD 33052439e4bfSJean-Christophe PLAGNIOL-VILLARD /****************************************************************************** 33062439e4bfSJean-Christophe PLAGNIOL-VILLARD * Sets the collision distance in the Transmit Control register 33072439e4bfSJean-Christophe PLAGNIOL-VILLARD * 33082439e4bfSJean-Christophe PLAGNIOL-VILLARD * hw - Struct containing variables accessed by shared code 33092439e4bfSJean-Christophe PLAGNIOL-VILLARD * 33102439e4bfSJean-Christophe PLAGNIOL-VILLARD * Link should have been established previously. Reads the speed and duplex 33112439e4bfSJean-Christophe PLAGNIOL-VILLARD * information from the Device Status register. 33122439e4bfSJean-Christophe PLAGNIOL-VILLARD ******************************************************************************/ 33132439e4bfSJean-Christophe PLAGNIOL-VILLARD static void 33142439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_config_collision_dist(struct e1000_hw *hw) 33152439e4bfSJean-Christophe PLAGNIOL-VILLARD { 3316aa070789SRoy Zang uint32_t tctl, coll_dist; 3317aa070789SRoy Zang 3318aa070789SRoy Zang DEBUGFUNC(); 3319aa070789SRoy Zang 3320aa070789SRoy Zang if (hw->mac_type < e1000_82543) 3321aa070789SRoy Zang coll_dist = E1000_COLLISION_DISTANCE_82542; 3322aa070789SRoy Zang else 3323aa070789SRoy Zang coll_dist = E1000_COLLISION_DISTANCE; 33242439e4bfSJean-Christophe PLAGNIOL-VILLARD 33252439e4bfSJean-Christophe PLAGNIOL-VILLARD tctl = E1000_READ_REG(hw, TCTL); 33262439e4bfSJean-Christophe PLAGNIOL-VILLARD 33272439e4bfSJean-Christophe PLAGNIOL-VILLARD tctl &= ~E1000_TCTL_COLD; 3328aa070789SRoy Zang tctl |= coll_dist << E1000_COLD_SHIFT; 33292439e4bfSJean-Christophe PLAGNIOL-VILLARD 33302439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, TCTL, tctl); 33312439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_FLUSH(hw); 33322439e4bfSJean-Christophe PLAGNIOL-VILLARD } 33332439e4bfSJean-Christophe PLAGNIOL-VILLARD 33342439e4bfSJean-Christophe PLAGNIOL-VILLARD /****************************************************************************** 33352439e4bfSJean-Christophe PLAGNIOL-VILLARD * Sets MAC speed and duplex settings to reflect the those in the PHY 33362439e4bfSJean-Christophe PLAGNIOL-VILLARD * 33372439e4bfSJean-Christophe PLAGNIOL-VILLARD * hw - Struct containing variables accessed by shared code 33382439e4bfSJean-Christophe PLAGNIOL-VILLARD * mii_reg - data to write to the MII control register 33392439e4bfSJean-Christophe PLAGNIOL-VILLARD * 33402439e4bfSJean-Christophe PLAGNIOL-VILLARD * The contents of the PHY register containing the needed information need to 33412439e4bfSJean-Christophe PLAGNIOL-VILLARD * be passed in. 33422439e4bfSJean-Christophe PLAGNIOL-VILLARD ******************************************************************************/ 33432439e4bfSJean-Christophe PLAGNIOL-VILLARD static int 33442439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_config_mac_to_phy(struct e1000_hw *hw) 33452439e4bfSJean-Christophe PLAGNIOL-VILLARD { 33462439e4bfSJean-Christophe PLAGNIOL-VILLARD uint32_t ctrl; 33472439e4bfSJean-Christophe PLAGNIOL-VILLARD uint16_t phy_data; 33482439e4bfSJean-Christophe PLAGNIOL-VILLARD 33492439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGFUNC(); 33502439e4bfSJean-Christophe PLAGNIOL-VILLARD 33512439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Read the Device Control Register and set the bits to Force Speed 33522439e4bfSJean-Christophe PLAGNIOL-VILLARD * and Duplex. 33532439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 33542439e4bfSJean-Christophe PLAGNIOL-VILLARD ctrl = E1000_READ_REG(hw, CTRL); 33552439e4bfSJean-Christophe PLAGNIOL-VILLARD ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 335695186063SMarek Vasut ctrl &= ~(E1000_CTRL_ILOS); 335795186063SMarek Vasut ctrl |= (E1000_CTRL_SPD_SEL); 33582439e4bfSJean-Christophe PLAGNIOL-VILLARD 33592439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Set up duplex in the Device Control and Transmit Control 33602439e4bfSJean-Christophe PLAGNIOL-VILLARD * registers depending on negotiated values. 33612439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 33622439e4bfSJean-Christophe PLAGNIOL-VILLARD if (e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data) < 0) { 33632439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("PHY Read Error\n"); 33642439e4bfSJean-Christophe PLAGNIOL-VILLARD return -E1000_ERR_PHY; 33652439e4bfSJean-Christophe PLAGNIOL-VILLARD } 33662439e4bfSJean-Christophe PLAGNIOL-VILLARD if (phy_data & M88E1000_PSSR_DPLX) 33672439e4bfSJean-Christophe PLAGNIOL-VILLARD ctrl |= E1000_CTRL_FD; 33682439e4bfSJean-Christophe PLAGNIOL-VILLARD else 33692439e4bfSJean-Christophe PLAGNIOL-VILLARD ctrl &= ~E1000_CTRL_FD; 33702439e4bfSJean-Christophe PLAGNIOL-VILLARD 33712439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_config_collision_dist(hw); 33722439e4bfSJean-Christophe PLAGNIOL-VILLARD 33732439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Set up speed in the Device Control register depending on 33742439e4bfSJean-Christophe PLAGNIOL-VILLARD * negotiated values. 33752439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 33762439e4bfSJean-Christophe PLAGNIOL-VILLARD if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) 33772439e4bfSJean-Christophe PLAGNIOL-VILLARD ctrl |= E1000_CTRL_SPD_1000; 33782439e4bfSJean-Christophe PLAGNIOL-VILLARD else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS) 33792439e4bfSJean-Christophe PLAGNIOL-VILLARD ctrl |= E1000_CTRL_SPD_100; 33802439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Write the configured values back to the Device Control Reg. */ 33812439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, CTRL, ctrl); 33822439e4bfSJean-Christophe PLAGNIOL-VILLARD return 0; 33832439e4bfSJean-Christophe PLAGNIOL-VILLARD } 33842439e4bfSJean-Christophe PLAGNIOL-VILLARD 33852439e4bfSJean-Christophe PLAGNIOL-VILLARD /****************************************************************************** 33862439e4bfSJean-Christophe PLAGNIOL-VILLARD * Forces the MAC's flow control settings. 33872439e4bfSJean-Christophe PLAGNIOL-VILLARD * 33882439e4bfSJean-Christophe PLAGNIOL-VILLARD * hw - Struct containing variables accessed by shared code 33892439e4bfSJean-Christophe PLAGNIOL-VILLARD * 33902439e4bfSJean-Christophe PLAGNIOL-VILLARD * Sets the TFCE and RFCE bits in the device control register to reflect 33912439e4bfSJean-Christophe PLAGNIOL-VILLARD * the adapter settings. TFCE and RFCE need to be explicitly set by 33922439e4bfSJean-Christophe PLAGNIOL-VILLARD * software when a Copper PHY is used because autonegotiation is managed 33932439e4bfSJean-Christophe PLAGNIOL-VILLARD * by the PHY rather than the MAC. Software must also configure these 33942439e4bfSJean-Christophe PLAGNIOL-VILLARD * bits when link is forced on a fiber connection. 33952439e4bfSJean-Christophe PLAGNIOL-VILLARD *****************************************************************************/ 33962439e4bfSJean-Christophe PLAGNIOL-VILLARD static int 33972439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_force_mac_fc(struct e1000_hw *hw) 33982439e4bfSJean-Christophe PLAGNIOL-VILLARD { 33992439e4bfSJean-Christophe PLAGNIOL-VILLARD uint32_t ctrl; 34002439e4bfSJean-Christophe PLAGNIOL-VILLARD 34012439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGFUNC(); 34022439e4bfSJean-Christophe PLAGNIOL-VILLARD 34032439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Get the current configuration of the Device Control Register */ 34042439e4bfSJean-Christophe PLAGNIOL-VILLARD ctrl = E1000_READ_REG(hw, CTRL); 34052439e4bfSJean-Christophe PLAGNIOL-VILLARD 34062439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Because we didn't get link via the internal auto-negotiation 34072439e4bfSJean-Christophe PLAGNIOL-VILLARD * mechanism (we either forced link or we got link via PHY 34082439e4bfSJean-Christophe PLAGNIOL-VILLARD * auto-neg), we have to manually enable/disable transmit an 34092439e4bfSJean-Christophe PLAGNIOL-VILLARD * receive flow control. 34102439e4bfSJean-Christophe PLAGNIOL-VILLARD * 34112439e4bfSJean-Christophe PLAGNIOL-VILLARD * The "Case" statement below enables/disable flow control 34122439e4bfSJean-Christophe PLAGNIOL-VILLARD * according to the "hw->fc" parameter. 34132439e4bfSJean-Christophe PLAGNIOL-VILLARD * 34142439e4bfSJean-Christophe PLAGNIOL-VILLARD * The possible values of the "fc" parameter are: 34152439e4bfSJean-Christophe PLAGNIOL-VILLARD * 0: Flow control is completely disabled 34162439e4bfSJean-Christophe PLAGNIOL-VILLARD * 1: Rx flow control is enabled (we can receive pause 34172439e4bfSJean-Christophe PLAGNIOL-VILLARD * frames but not send pause frames). 34182439e4bfSJean-Christophe PLAGNIOL-VILLARD * 2: Tx flow control is enabled (we can send pause frames 34192439e4bfSJean-Christophe PLAGNIOL-VILLARD * frames but we do not receive pause frames). 34202439e4bfSJean-Christophe PLAGNIOL-VILLARD * 3: Both Rx and TX flow control (symmetric) is enabled. 34212439e4bfSJean-Christophe PLAGNIOL-VILLARD * other: No other values should be possible at this point. 34222439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 34232439e4bfSJean-Christophe PLAGNIOL-VILLARD 34242439e4bfSJean-Christophe PLAGNIOL-VILLARD switch (hw->fc) { 34252439e4bfSJean-Christophe PLAGNIOL-VILLARD case e1000_fc_none: 34262439e4bfSJean-Christophe PLAGNIOL-VILLARD ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE)); 34272439e4bfSJean-Christophe PLAGNIOL-VILLARD break; 34282439e4bfSJean-Christophe PLAGNIOL-VILLARD case e1000_fc_rx_pause: 34292439e4bfSJean-Christophe PLAGNIOL-VILLARD ctrl &= (~E1000_CTRL_TFCE); 34302439e4bfSJean-Christophe PLAGNIOL-VILLARD ctrl |= E1000_CTRL_RFCE; 34312439e4bfSJean-Christophe PLAGNIOL-VILLARD break; 34322439e4bfSJean-Christophe PLAGNIOL-VILLARD case e1000_fc_tx_pause: 34332439e4bfSJean-Christophe PLAGNIOL-VILLARD ctrl &= (~E1000_CTRL_RFCE); 34342439e4bfSJean-Christophe PLAGNIOL-VILLARD ctrl |= E1000_CTRL_TFCE; 34352439e4bfSJean-Christophe PLAGNIOL-VILLARD break; 34362439e4bfSJean-Christophe PLAGNIOL-VILLARD case e1000_fc_full: 34372439e4bfSJean-Christophe PLAGNIOL-VILLARD ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE); 34382439e4bfSJean-Christophe PLAGNIOL-VILLARD break; 34392439e4bfSJean-Christophe PLAGNIOL-VILLARD default: 34402439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("Flow control param set incorrectly\n"); 34412439e4bfSJean-Christophe PLAGNIOL-VILLARD return -E1000_ERR_CONFIG; 34422439e4bfSJean-Christophe PLAGNIOL-VILLARD } 34432439e4bfSJean-Christophe PLAGNIOL-VILLARD 34442439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Disable TX Flow Control for 82542 (rev 2.0) */ 34452439e4bfSJean-Christophe PLAGNIOL-VILLARD if (hw->mac_type == e1000_82542_rev2_0) 34462439e4bfSJean-Christophe PLAGNIOL-VILLARD ctrl &= (~E1000_CTRL_TFCE); 34472439e4bfSJean-Christophe PLAGNIOL-VILLARD 34482439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, CTRL, ctrl); 34492439e4bfSJean-Christophe PLAGNIOL-VILLARD return 0; 34502439e4bfSJean-Christophe PLAGNIOL-VILLARD } 34512439e4bfSJean-Christophe PLAGNIOL-VILLARD 34522439e4bfSJean-Christophe PLAGNIOL-VILLARD /****************************************************************************** 34532439e4bfSJean-Christophe PLAGNIOL-VILLARD * Configures flow control settings after link is established 34542439e4bfSJean-Christophe PLAGNIOL-VILLARD * 34552439e4bfSJean-Christophe PLAGNIOL-VILLARD * hw - Struct containing variables accessed by shared code 34562439e4bfSJean-Christophe PLAGNIOL-VILLARD * 34572439e4bfSJean-Christophe PLAGNIOL-VILLARD * Should be called immediately after a valid link has been established. 34582439e4bfSJean-Christophe PLAGNIOL-VILLARD * Forces MAC flow control settings if link was forced. When in MII/GMII mode 34592439e4bfSJean-Christophe PLAGNIOL-VILLARD * and autonegotiation is enabled, the MAC flow control settings will be set 34602439e4bfSJean-Christophe PLAGNIOL-VILLARD * based on the flow control negotiated by the PHY. In TBI mode, the TFCE 34612439e4bfSJean-Christophe PLAGNIOL-VILLARD * and RFCE bits will be automaticaly set to the negotiated flow control mode. 34622439e4bfSJean-Christophe PLAGNIOL-VILLARD *****************************************************************************/ 3463aa070789SRoy Zang static int32_t 34642439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_config_fc_after_link_up(struct e1000_hw *hw) 34652439e4bfSJean-Christophe PLAGNIOL-VILLARD { 34662439e4bfSJean-Christophe PLAGNIOL-VILLARD int32_t ret_val; 34672439e4bfSJean-Christophe PLAGNIOL-VILLARD uint16_t mii_status_reg; 34682439e4bfSJean-Christophe PLAGNIOL-VILLARD uint16_t mii_nway_adv_reg; 34692439e4bfSJean-Christophe PLAGNIOL-VILLARD uint16_t mii_nway_lp_ability_reg; 34702439e4bfSJean-Christophe PLAGNIOL-VILLARD uint16_t speed; 34712439e4bfSJean-Christophe PLAGNIOL-VILLARD uint16_t duplex; 34722439e4bfSJean-Christophe PLAGNIOL-VILLARD 34732439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGFUNC(); 34742439e4bfSJean-Christophe PLAGNIOL-VILLARD 34752439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Check for the case where we have fiber media and auto-neg failed 34762439e4bfSJean-Christophe PLAGNIOL-VILLARD * so we had to force link. In this case, we need to force the 34772439e4bfSJean-Christophe PLAGNIOL-VILLARD * configuration of the MAC to match the "fc" parameter. 34782439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 3479aa070789SRoy Zang if (((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed)) 3480aa070789SRoy Zang || ((hw->media_type == e1000_media_type_internal_serdes) 3481aa070789SRoy Zang && (hw->autoneg_failed)) 3482aa070789SRoy Zang || ((hw->media_type == e1000_media_type_copper) 3483aa070789SRoy Zang && (!hw->autoneg))) { 34842439e4bfSJean-Christophe PLAGNIOL-VILLARD ret_val = e1000_force_mac_fc(hw); 34852439e4bfSJean-Christophe PLAGNIOL-VILLARD if (ret_val < 0) { 34862439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("Error forcing flow control settings\n"); 34872439e4bfSJean-Christophe PLAGNIOL-VILLARD return ret_val; 34882439e4bfSJean-Christophe PLAGNIOL-VILLARD } 34892439e4bfSJean-Christophe PLAGNIOL-VILLARD } 34902439e4bfSJean-Christophe PLAGNIOL-VILLARD 34912439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Check for the case where we have copper media and auto-neg is 34922439e4bfSJean-Christophe PLAGNIOL-VILLARD * enabled. In this case, we need to check and see if Auto-Neg 34932439e4bfSJean-Christophe PLAGNIOL-VILLARD * has completed, and if so, how the PHY and link partner has 34942439e4bfSJean-Christophe PLAGNIOL-VILLARD * flow control configured. 34952439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 34962439e4bfSJean-Christophe PLAGNIOL-VILLARD if (hw->media_type == e1000_media_type_copper) { 34972439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Read the MII Status Register and check to see if AutoNeg 34982439e4bfSJean-Christophe PLAGNIOL-VILLARD * has completed. We read this twice because this reg has 34992439e4bfSJean-Christophe PLAGNIOL-VILLARD * some "sticky" (latched) bits. 35002439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 35012439e4bfSJean-Christophe PLAGNIOL-VILLARD if (e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) { 35022439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("PHY Read Error\n"); 35032439e4bfSJean-Christophe PLAGNIOL-VILLARD return -E1000_ERR_PHY; 35042439e4bfSJean-Christophe PLAGNIOL-VILLARD } 35052439e4bfSJean-Christophe PLAGNIOL-VILLARD if (e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) { 35062439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("PHY Read Error\n"); 35072439e4bfSJean-Christophe PLAGNIOL-VILLARD return -E1000_ERR_PHY; 35082439e4bfSJean-Christophe PLAGNIOL-VILLARD } 35092439e4bfSJean-Christophe PLAGNIOL-VILLARD 35102439e4bfSJean-Christophe PLAGNIOL-VILLARD if (mii_status_reg & MII_SR_AUTONEG_COMPLETE) { 35112439e4bfSJean-Christophe PLAGNIOL-VILLARD /* The AutoNeg process has completed, so we now need to 35122439e4bfSJean-Christophe PLAGNIOL-VILLARD * read both the Auto Negotiation Advertisement Register 35132439e4bfSJean-Christophe PLAGNIOL-VILLARD * (Address 4) and the Auto_Negotiation Base Page Ability 35142439e4bfSJean-Christophe PLAGNIOL-VILLARD * Register (Address 5) to determine how flow control was 35152439e4bfSJean-Christophe PLAGNIOL-VILLARD * negotiated. 35162439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 35172439e4bfSJean-Christophe PLAGNIOL-VILLARD if (e1000_read_phy_reg 35182439e4bfSJean-Christophe PLAGNIOL-VILLARD (hw, PHY_AUTONEG_ADV, &mii_nway_adv_reg) < 0) { 35192439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("PHY Read Error\n"); 35202439e4bfSJean-Christophe PLAGNIOL-VILLARD return -E1000_ERR_PHY; 35212439e4bfSJean-Christophe PLAGNIOL-VILLARD } 35222439e4bfSJean-Christophe PLAGNIOL-VILLARD if (e1000_read_phy_reg 35232439e4bfSJean-Christophe PLAGNIOL-VILLARD (hw, PHY_LP_ABILITY, 35242439e4bfSJean-Christophe PLAGNIOL-VILLARD &mii_nway_lp_ability_reg) < 0) { 35252439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("PHY Read Error\n"); 35262439e4bfSJean-Christophe PLAGNIOL-VILLARD return -E1000_ERR_PHY; 35272439e4bfSJean-Christophe PLAGNIOL-VILLARD } 35282439e4bfSJean-Christophe PLAGNIOL-VILLARD 35292439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Two bits in the Auto Negotiation Advertisement Register 35302439e4bfSJean-Christophe PLAGNIOL-VILLARD * (Address 4) and two bits in the Auto Negotiation Base 35312439e4bfSJean-Christophe PLAGNIOL-VILLARD * Page Ability Register (Address 5) determine flow control 35322439e4bfSJean-Christophe PLAGNIOL-VILLARD * for both the PHY and the link partner. The following 35332439e4bfSJean-Christophe PLAGNIOL-VILLARD * table, taken out of the IEEE 802.3ab/D6.0 dated March 25, 35342439e4bfSJean-Christophe PLAGNIOL-VILLARD * 1999, describes these PAUSE resolution bits and how flow 35352439e4bfSJean-Christophe PLAGNIOL-VILLARD * control is determined based upon these settings. 35362439e4bfSJean-Christophe PLAGNIOL-VILLARD * NOTE: DC = Don't Care 35372439e4bfSJean-Christophe PLAGNIOL-VILLARD * 35382439e4bfSJean-Christophe PLAGNIOL-VILLARD * LOCAL DEVICE | LINK PARTNER 35392439e4bfSJean-Christophe PLAGNIOL-VILLARD * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution 35402439e4bfSJean-Christophe PLAGNIOL-VILLARD *-------|---------|-------|---------|-------------------- 35412439e4bfSJean-Christophe PLAGNIOL-VILLARD * 0 | 0 | DC | DC | e1000_fc_none 35422439e4bfSJean-Christophe PLAGNIOL-VILLARD * 0 | 1 | 0 | DC | e1000_fc_none 35432439e4bfSJean-Christophe PLAGNIOL-VILLARD * 0 | 1 | 1 | 0 | e1000_fc_none 35442439e4bfSJean-Christophe PLAGNIOL-VILLARD * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 35452439e4bfSJean-Christophe PLAGNIOL-VILLARD * 1 | 0 | 0 | DC | e1000_fc_none 35462439e4bfSJean-Christophe PLAGNIOL-VILLARD * 1 | DC | 1 | DC | e1000_fc_full 35472439e4bfSJean-Christophe PLAGNIOL-VILLARD * 1 | 1 | 0 | 0 | e1000_fc_none 35482439e4bfSJean-Christophe PLAGNIOL-VILLARD * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 35492439e4bfSJean-Christophe PLAGNIOL-VILLARD * 35502439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 35512439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Are both PAUSE bits set to 1? If so, this implies 35522439e4bfSJean-Christophe PLAGNIOL-VILLARD * Symmetric Flow Control is enabled at both ends. The 35532439e4bfSJean-Christophe PLAGNIOL-VILLARD * ASM_DIR bits are irrelevant per the spec. 35542439e4bfSJean-Christophe PLAGNIOL-VILLARD * 35552439e4bfSJean-Christophe PLAGNIOL-VILLARD * For Symmetric Flow Control: 35562439e4bfSJean-Christophe PLAGNIOL-VILLARD * 35572439e4bfSJean-Christophe PLAGNIOL-VILLARD * LOCAL DEVICE | LINK PARTNER 35582439e4bfSJean-Christophe PLAGNIOL-VILLARD * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 35592439e4bfSJean-Christophe PLAGNIOL-VILLARD *-------|---------|-------|---------|-------------------- 35602439e4bfSJean-Christophe PLAGNIOL-VILLARD * 1 | DC | 1 | DC | e1000_fc_full 35612439e4bfSJean-Christophe PLAGNIOL-VILLARD * 35622439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 35632439e4bfSJean-Christophe PLAGNIOL-VILLARD if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 35642439e4bfSJean-Christophe PLAGNIOL-VILLARD (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) { 35652439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Now we need to check if the user selected RX ONLY 35662439e4bfSJean-Christophe PLAGNIOL-VILLARD * of pause frames. In this case, we had to advertise 35672439e4bfSJean-Christophe PLAGNIOL-VILLARD * FULL flow control because we could not advertise RX 35682439e4bfSJean-Christophe PLAGNIOL-VILLARD * ONLY. Hence, we must now check to see if we need to 35692439e4bfSJean-Christophe PLAGNIOL-VILLARD * turn OFF the TRANSMISSION of PAUSE frames. 35702439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 35712439e4bfSJean-Christophe PLAGNIOL-VILLARD if (hw->original_fc == e1000_fc_full) { 35722439e4bfSJean-Christophe PLAGNIOL-VILLARD hw->fc = e1000_fc_full; 35732439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("Flow Control = FULL.\r\n"); 35742439e4bfSJean-Christophe PLAGNIOL-VILLARD } else { 35752439e4bfSJean-Christophe PLAGNIOL-VILLARD hw->fc = e1000_fc_rx_pause; 35762439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT 35772439e4bfSJean-Christophe PLAGNIOL-VILLARD ("Flow Control = RX PAUSE frames only.\r\n"); 35782439e4bfSJean-Christophe PLAGNIOL-VILLARD } 35792439e4bfSJean-Christophe PLAGNIOL-VILLARD } 35802439e4bfSJean-Christophe PLAGNIOL-VILLARD /* For receiving PAUSE frames ONLY. 35812439e4bfSJean-Christophe PLAGNIOL-VILLARD * 35822439e4bfSJean-Christophe PLAGNIOL-VILLARD * LOCAL DEVICE | LINK PARTNER 35832439e4bfSJean-Christophe PLAGNIOL-VILLARD * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 35842439e4bfSJean-Christophe PLAGNIOL-VILLARD *-------|---------|-------|---------|-------------------- 35852439e4bfSJean-Christophe PLAGNIOL-VILLARD * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 35862439e4bfSJean-Christophe PLAGNIOL-VILLARD * 35872439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 35882439e4bfSJean-Christophe PLAGNIOL-VILLARD else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) && 35892439e4bfSJean-Christophe PLAGNIOL-VILLARD (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 35902439e4bfSJean-Christophe PLAGNIOL-VILLARD (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 35912439e4bfSJean-Christophe PLAGNIOL-VILLARD (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) 35922439e4bfSJean-Christophe PLAGNIOL-VILLARD { 35932439e4bfSJean-Christophe PLAGNIOL-VILLARD hw->fc = e1000_fc_tx_pause; 35942439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT 35952439e4bfSJean-Christophe PLAGNIOL-VILLARD ("Flow Control = TX PAUSE frames only.\r\n"); 35962439e4bfSJean-Christophe PLAGNIOL-VILLARD } 35972439e4bfSJean-Christophe PLAGNIOL-VILLARD /* For transmitting PAUSE frames ONLY. 35982439e4bfSJean-Christophe PLAGNIOL-VILLARD * 35992439e4bfSJean-Christophe PLAGNIOL-VILLARD * LOCAL DEVICE | LINK PARTNER 36002439e4bfSJean-Christophe PLAGNIOL-VILLARD * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 36012439e4bfSJean-Christophe PLAGNIOL-VILLARD *-------|---------|-------|---------|-------------------- 36022439e4bfSJean-Christophe PLAGNIOL-VILLARD * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 36032439e4bfSJean-Christophe PLAGNIOL-VILLARD * 36042439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 36052439e4bfSJean-Christophe PLAGNIOL-VILLARD else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 36062439e4bfSJean-Christophe PLAGNIOL-VILLARD (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 36072439e4bfSJean-Christophe PLAGNIOL-VILLARD !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 36082439e4bfSJean-Christophe PLAGNIOL-VILLARD (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) 36092439e4bfSJean-Christophe PLAGNIOL-VILLARD { 36102439e4bfSJean-Christophe PLAGNIOL-VILLARD hw->fc = e1000_fc_rx_pause; 36112439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT 36122439e4bfSJean-Christophe PLAGNIOL-VILLARD ("Flow Control = RX PAUSE frames only.\r\n"); 36132439e4bfSJean-Christophe PLAGNIOL-VILLARD } 36142439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Per the IEEE spec, at this point flow control should be 36152439e4bfSJean-Christophe PLAGNIOL-VILLARD * disabled. However, we want to consider that we could 36162439e4bfSJean-Christophe PLAGNIOL-VILLARD * be connected to a legacy switch that doesn't advertise 36172439e4bfSJean-Christophe PLAGNIOL-VILLARD * desired flow control, but can be forced on the link 36182439e4bfSJean-Christophe PLAGNIOL-VILLARD * partner. So if we advertised no flow control, that is 36192439e4bfSJean-Christophe PLAGNIOL-VILLARD * what we will resolve to. If we advertised some kind of 36202439e4bfSJean-Christophe PLAGNIOL-VILLARD * receive capability (Rx Pause Only or Full Flow Control) 36212439e4bfSJean-Christophe PLAGNIOL-VILLARD * and the link partner advertised none, we will configure 36222439e4bfSJean-Christophe PLAGNIOL-VILLARD * ourselves to enable Rx Flow Control only. We can do 36232439e4bfSJean-Christophe PLAGNIOL-VILLARD * this safely for two reasons: If the link partner really 36242439e4bfSJean-Christophe PLAGNIOL-VILLARD * didn't want flow control enabled, and we enable Rx, no 36252439e4bfSJean-Christophe PLAGNIOL-VILLARD * harm done since we won't be receiving any PAUSE frames 36262439e4bfSJean-Christophe PLAGNIOL-VILLARD * anyway. If the intent on the link partner was to have 36272439e4bfSJean-Christophe PLAGNIOL-VILLARD * flow control enabled, then by us enabling RX only, we 36282439e4bfSJean-Christophe PLAGNIOL-VILLARD * can at least receive pause frames and process them. 36292439e4bfSJean-Christophe PLAGNIOL-VILLARD * This is a good idea because in most cases, since we are 36302439e4bfSJean-Christophe PLAGNIOL-VILLARD * predominantly a server NIC, more times than not we will 36312439e4bfSJean-Christophe PLAGNIOL-VILLARD * be asked to delay transmission of packets than asking 36322439e4bfSJean-Christophe PLAGNIOL-VILLARD * our link partner to pause transmission of frames. 36332439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 36342439e4bfSJean-Christophe PLAGNIOL-VILLARD else if (hw->original_fc == e1000_fc_none || 36352439e4bfSJean-Christophe PLAGNIOL-VILLARD hw->original_fc == e1000_fc_tx_pause) { 36362439e4bfSJean-Christophe PLAGNIOL-VILLARD hw->fc = e1000_fc_none; 36372439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("Flow Control = NONE.\r\n"); 36382439e4bfSJean-Christophe PLAGNIOL-VILLARD } else { 36392439e4bfSJean-Christophe PLAGNIOL-VILLARD hw->fc = e1000_fc_rx_pause; 36402439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT 36412439e4bfSJean-Christophe PLAGNIOL-VILLARD ("Flow Control = RX PAUSE frames only.\r\n"); 36422439e4bfSJean-Christophe PLAGNIOL-VILLARD } 36432439e4bfSJean-Christophe PLAGNIOL-VILLARD 36442439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Now we need to do one last check... If we auto- 36452439e4bfSJean-Christophe PLAGNIOL-VILLARD * negotiated to HALF DUPLEX, flow control should not be 36462439e4bfSJean-Christophe PLAGNIOL-VILLARD * enabled per IEEE 802.3 spec. 36472439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 36482439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_get_speed_and_duplex(hw, &speed, &duplex); 36492439e4bfSJean-Christophe PLAGNIOL-VILLARD 36502439e4bfSJean-Christophe PLAGNIOL-VILLARD if (duplex == HALF_DUPLEX) 36512439e4bfSJean-Christophe PLAGNIOL-VILLARD hw->fc = e1000_fc_none; 36522439e4bfSJean-Christophe PLAGNIOL-VILLARD 36532439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Now we call a subroutine to actually force the MAC 36542439e4bfSJean-Christophe PLAGNIOL-VILLARD * controller to use the correct flow control settings. 36552439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 36562439e4bfSJean-Christophe PLAGNIOL-VILLARD ret_val = e1000_force_mac_fc(hw); 36572439e4bfSJean-Christophe PLAGNIOL-VILLARD if (ret_val < 0) { 36582439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT 36592439e4bfSJean-Christophe PLAGNIOL-VILLARD ("Error forcing flow control settings\n"); 36602439e4bfSJean-Christophe PLAGNIOL-VILLARD return ret_val; 36612439e4bfSJean-Christophe PLAGNIOL-VILLARD } 36622439e4bfSJean-Christophe PLAGNIOL-VILLARD } else { 36632439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT 36642439e4bfSJean-Christophe PLAGNIOL-VILLARD ("Copper PHY and Auto Neg has not completed.\r\n"); 36652439e4bfSJean-Christophe PLAGNIOL-VILLARD } 36662439e4bfSJean-Christophe PLAGNIOL-VILLARD } 3667aa070789SRoy Zang return E1000_SUCCESS; 36682439e4bfSJean-Christophe PLAGNIOL-VILLARD } 36692439e4bfSJean-Christophe PLAGNIOL-VILLARD 36702439e4bfSJean-Christophe PLAGNIOL-VILLARD /****************************************************************************** 36712439e4bfSJean-Christophe PLAGNIOL-VILLARD * Checks to see if the link status of the hardware has changed. 36722439e4bfSJean-Christophe PLAGNIOL-VILLARD * 36732439e4bfSJean-Christophe PLAGNIOL-VILLARD * hw - Struct containing variables accessed by shared code 36742439e4bfSJean-Christophe PLAGNIOL-VILLARD * 36752439e4bfSJean-Christophe PLAGNIOL-VILLARD * Called by any function that needs to check the link status of the adapter. 36762439e4bfSJean-Christophe PLAGNIOL-VILLARD *****************************************************************************/ 36772439e4bfSJean-Christophe PLAGNIOL-VILLARD static int 36785c5e707aSSimon Glass e1000_check_for_link(struct e1000_hw *hw) 36792439e4bfSJean-Christophe PLAGNIOL-VILLARD { 36802439e4bfSJean-Christophe PLAGNIOL-VILLARD uint32_t rxcw; 36812439e4bfSJean-Christophe PLAGNIOL-VILLARD uint32_t ctrl; 36822439e4bfSJean-Christophe PLAGNIOL-VILLARD uint32_t status; 36832439e4bfSJean-Christophe PLAGNIOL-VILLARD uint32_t rctl; 36842439e4bfSJean-Christophe PLAGNIOL-VILLARD uint32_t signal; 36852439e4bfSJean-Christophe PLAGNIOL-VILLARD int32_t ret_val; 36862439e4bfSJean-Christophe PLAGNIOL-VILLARD uint16_t phy_data; 36872439e4bfSJean-Christophe PLAGNIOL-VILLARD uint16_t lp_capability; 36882439e4bfSJean-Christophe PLAGNIOL-VILLARD 36892439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGFUNC(); 36902439e4bfSJean-Christophe PLAGNIOL-VILLARD 36912439e4bfSJean-Christophe PLAGNIOL-VILLARD /* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be 36922439e4bfSJean-Christophe PLAGNIOL-VILLARD * set when the optics detect a signal. On older adapters, it will be 36932439e4bfSJean-Christophe PLAGNIOL-VILLARD * cleared when there is a signal 36942439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 36952439e4bfSJean-Christophe PLAGNIOL-VILLARD ctrl = E1000_READ_REG(hw, CTRL); 36962439e4bfSJean-Christophe PLAGNIOL-VILLARD if ((hw->mac_type > e1000_82544) && !(ctrl & E1000_CTRL_ILOS)) 36972439e4bfSJean-Christophe PLAGNIOL-VILLARD signal = E1000_CTRL_SWDPIN1; 36982439e4bfSJean-Christophe PLAGNIOL-VILLARD else 36992439e4bfSJean-Christophe PLAGNIOL-VILLARD signal = 0; 37002439e4bfSJean-Christophe PLAGNIOL-VILLARD 37012439e4bfSJean-Christophe PLAGNIOL-VILLARD status = E1000_READ_REG(hw, STATUS); 37022439e4bfSJean-Christophe PLAGNIOL-VILLARD rxcw = E1000_READ_REG(hw, RXCW); 37032439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("ctrl: %#08x status %#08x rxcw %#08x\n", ctrl, status, rxcw); 37042439e4bfSJean-Christophe PLAGNIOL-VILLARD 37052439e4bfSJean-Christophe PLAGNIOL-VILLARD /* If we have a copper PHY then we only want to go out to the PHY 37062439e4bfSJean-Christophe PLAGNIOL-VILLARD * registers to see if Auto-Neg has completed and/or if our link 37072439e4bfSJean-Christophe PLAGNIOL-VILLARD * status has changed. The get_link_status flag will be set if we 37082439e4bfSJean-Christophe PLAGNIOL-VILLARD * receive a Link Status Change interrupt or we have Rx Sequence 37092439e4bfSJean-Christophe PLAGNIOL-VILLARD * Errors. 37102439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 37112439e4bfSJean-Christophe PLAGNIOL-VILLARD if ((hw->media_type == e1000_media_type_copper) && hw->get_link_status) { 37122439e4bfSJean-Christophe PLAGNIOL-VILLARD /* First we want to see if the MII Status Register reports 37132439e4bfSJean-Christophe PLAGNIOL-VILLARD * link. If so, then we want to get the current speed/duplex 37142439e4bfSJean-Christophe PLAGNIOL-VILLARD * of the PHY. 37152439e4bfSJean-Christophe PLAGNIOL-VILLARD * Read the register twice since the link bit is sticky. 37162439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 37172439e4bfSJean-Christophe PLAGNIOL-VILLARD if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) { 37182439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("PHY Read Error\n"); 37192439e4bfSJean-Christophe PLAGNIOL-VILLARD return -E1000_ERR_PHY; 37202439e4bfSJean-Christophe PLAGNIOL-VILLARD } 37212439e4bfSJean-Christophe PLAGNIOL-VILLARD if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) { 37222439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("PHY Read Error\n"); 37232439e4bfSJean-Christophe PLAGNIOL-VILLARD return -E1000_ERR_PHY; 37242439e4bfSJean-Christophe PLAGNIOL-VILLARD } 37252439e4bfSJean-Christophe PLAGNIOL-VILLARD 37262439e4bfSJean-Christophe PLAGNIOL-VILLARD if (phy_data & MII_SR_LINK_STATUS) { 3727472d5460SYork Sun hw->get_link_status = false; 37282439e4bfSJean-Christophe PLAGNIOL-VILLARD } else { 37292439e4bfSJean-Christophe PLAGNIOL-VILLARD /* No link detected */ 37302439e4bfSJean-Christophe PLAGNIOL-VILLARD return -E1000_ERR_NOLINK; 37312439e4bfSJean-Christophe PLAGNIOL-VILLARD } 37322439e4bfSJean-Christophe PLAGNIOL-VILLARD 37332439e4bfSJean-Christophe PLAGNIOL-VILLARD /* We have a M88E1000 PHY and Auto-Neg is enabled. If we 37342439e4bfSJean-Christophe PLAGNIOL-VILLARD * have Si on board that is 82544 or newer, Auto 37352439e4bfSJean-Christophe PLAGNIOL-VILLARD * Speed Detection takes care of MAC speed/duplex 37362439e4bfSJean-Christophe PLAGNIOL-VILLARD * configuration. So we only need to configure Collision 37372439e4bfSJean-Christophe PLAGNIOL-VILLARD * Distance in the MAC. Otherwise, we need to force 37382439e4bfSJean-Christophe PLAGNIOL-VILLARD * speed/duplex on the MAC to the current PHY speed/duplex 37392439e4bfSJean-Christophe PLAGNIOL-VILLARD * settings. 37402439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 37412439e4bfSJean-Christophe PLAGNIOL-VILLARD if (hw->mac_type >= e1000_82544) 37422439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_config_collision_dist(hw); 37432439e4bfSJean-Christophe PLAGNIOL-VILLARD else { 37442439e4bfSJean-Christophe PLAGNIOL-VILLARD ret_val = e1000_config_mac_to_phy(hw); 37452439e4bfSJean-Christophe PLAGNIOL-VILLARD if (ret_val < 0) { 37462439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT 37472439e4bfSJean-Christophe PLAGNIOL-VILLARD ("Error configuring MAC to PHY settings\n"); 37482439e4bfSJean-Christophe PLAGNIOL-VILLARD return ret_val; 37492439e4bfSJean-Christophe PLAGNIOL-VILLARD } 37502439e4bfSJean-Christophe PLAGNIOL-VILLARD } 37512439e4bfSJean-Christophe PLAGNIOL-VILLARD 37522439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Configure Flow Control now that Auto-Neg has completed. First, we 37532439e4bfSJean-Christophe PLAGNIOL-VILLARD * need to restore the desired flow control settings because we may 37542439e4bfSJean-Christophe PLAGNIOL-VILLARD * have had to re-autoneg with a different link partner. 37552439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 37562439e4bfSJean-Christophe PLAGNIOL-VILLARD ret_val = e1000_config_fc_after_link_up(hw); 37572439e4bfSJean-Christophe PLAGNIOL-VILLARD if (ret_val < 0) { 37582439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("Error configuring flow control\n"); 37592439e4bfSJean-Christophe PLAGNIOL-VILLARD return ret_val; 37602439e4bfSJean-Christophe PLAGNIOL-VILLARD } 37612439e4bfSJean-Christophe PLAGNIOL-VILLARD 37622439e4bfSJean-Christophe PLAGNIOL-VILLARD /* At this point we know that we are on copper and we have 37632439e4bfSJean-Christophe PLAGNIOL-VILLARD * auto-negotiated link. These are conditions for checking the link 37642439e4bfSJean-Christophe PLAGNIOL-VILLARD * parter capability register. We use the link partner capability to 37652439e4bfSJean-Christophe PLAGNIOL-VILLARD * determine if TBI Compatibility needs to be turned on or off. If 37662439e4bfSJean-Christophe PLAGNIOL-VILLARD * the link partner advertises any speed in addition to Gigabit, then 37672439e4bfSJean-Christophe PLAGNIOL-VILLARD * we assume that they are GMII-based, and TBI compatibility is not 37682439e4bfSJean-Christophe PLAGNIOL-VILLARD * needed. If no other speeds are advertised, we assume the link 37692439e4bfSJean-Christophe PLAGNIOL-VILLARD * partner is TBI-based, and we turn on TBI Compatibility. 37702439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 37712439e4bfSJean-Christophe PLAGNIOL-VILLARD if (hw->tbi_compatibility_en) { 37722439e4bfSJean-Christophe PLAGNIOL-VILLARD if (e1000_read_phy_reg 37732439e4bfSJean-Christophe PLAGNIOL-VILLARD (hw, PHY_LP_ABILITY, &lp_capability) < 0) { 37742439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("PHY Read Error\n"); 37752439e4bfSJean-Christophe PLAGNIOL-VILLARD return -E1000_ERR_PHY; 37762439e4bfSJean-Christophe PLAGNIOL-VILLARD } 37772439e4bfSJean-Christophe PLAGNIOL-VILLARD if (lp_capability & (NWAY_LPAR_10T_HD_CAPS | 37782439e4bfSJean-Christophe PLAGNIOL-VILLARD NWAY_LPAR_10T_FD_CAPS | 37792439e4bfSJean-Christophe PLAGNIOL-VILLARD NWAY_LPAR_100TX_HD_CAPS | 37802439e4bfSJean-Christophe PLAGNIOL-VILLARD NWAY_LPAR_100TX_FD_CAPS | 37812439e4bfSJean-Christophe PLAGNIOL-VILLARD NWAY_LPAR_100T4_CAPS)) { 37822439e4bfSJean-Christophe PLAGNIOL-VILLARD /* If our link partner advertises anything in addition to 37832439e4bfSJean-Christophe PLAGNIOL-VILLARD * gigabit, we do not need to enable TBI compatibility. 37842439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 37852439e4bfSJean-Christophe PLAGNIOL-VILLARD if (hw->tbi_compatibility_on) { 37862439e4bfSJean-Christophe PLAGNIOL-VILLARD /* If we previously were in the mode, turn it off. */ 37872439e4bfSJean-Christophe PLAGNIOL-VILLARD rctl = E1000_READ_REG(hw, RCTL); 37882439e4bfSJean-Christophe PLAGNIOL-VILLARD rctl &= ~E1000_RCTL_SBP; 37892439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, RCTL, rctl); 3790472d5460SYork Sun hw->tbi_compatibility_on = false; 37912439e4bfSJean-Christophe PLAGNIOL-VILLARD } 37922439e4bfSJean-Christophe PLAGNIOL-VILLARD } else { 37932439e4bfSJean-Christophe PLAGNIOL-VILLARD /* If TBI compatibility is was previously off, turn it on. For 37942439e4bfSJean-Christophe PLAGNIOL-VILLARD * compatibility with a TBI link partner, we will store bad 37952439e4bfSJean-Christophe PLAGNIOL-VILLARD * packets. Some frames have an additional byte on the end and 37962439e4bfSJean-Christophe PLAGNIOL-VILLARD * will look like CRC errors to to the hardware. 37972439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 37982439e4bfSJean-Christophe PLAGNIOL-VILLARD if (!hw->tbi_compatibility_on) { 3799472d5460SYork Sun hw->tbi_compatibility_on = true; 38002439e4bfSJean-Christophe PLAGNIOL-VILLARD rctl = E1000_READ_REG(hw, RCTL); 38012439e4bfSJean-Christophe PLAGNIOL-VILLARD rctl |= E1000_RCTL_SBP; 38022439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, RCTL, rctl); 38032439e4bfSJean-Christophe PLAGNIOL-VILLARD } 38042439e4bfSJean-Christophe PLAGNIOL-VILLARD } 38052439e4bfSJean-Christophe PLAGNIOL-VILLARD } 38062439e4bfSJean-Christophe PLAGNIOL-VILLARD } 38072439e4bfSJean-Christophe PLAGNIOL-VILLARD /* If we don't have link (auto-negotiation failed or link partner cannot 38082439e4bfSJean-Christophe PLAGNIOL-VILLARD * auto-negotiate), the cable is plugged in (we have signal), and our 38092439e4bfSJean-Christophe PLAGNIOL-VILLARD * link partner is not trying to auto-negotiate with us (we are receiving 38102439e4bfSJean-Christophe PLAGNIOL-VILLARD * idles or data), we need to force link up. We also need to give 38112439e4bfSJean-Christophe PLAGNIOL-VILLARD * auto-negotiation time to complete, in case the cable was just plugged 38122439e4bfSJean-Christophe PLAGNIOL-VILLARD * in. The autoneg_failed flag does this. 38132439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 38142439e4bfSJean-Christophe PLAGNIOL-VILLARD else if ((hw->media_type == e1000_media_type_fiber) && 38152439e4bfSJean-Christophe PLAGNIOL-VILLARD (!(status & E1000_STATUS_LU)) && 38162439e4bfSJean-Christophe PLAGNIOL-VILLARD ((ctrl & E1000_CTRL_SWDPIN1) == signal) && 38172439e4bfSJean-Christophe PLAGNIOL-VILLARD (!(rxcw & E1000_RXCW_C))) { 38182439e4bfSJean-Christophe PLAGNIOL-VILLARD if (hw->autoneg_failed == 0) { 38192439e4bfSJean-Christophe PLAGNIOL-VILLARD hw->autoneg_failed = 1; 38202439e4bfSJean-Christophe PLAGNIOL-VILLARD return 0; 38212439e4bfSJean-Christophe PLAGNIOL-VILLARD } 38222439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\r\n"); 38232439e4bfSJean-Christophe PLAGNIOL-VILLARD 38242439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Disable auto-negotiation in the TXCW register */ 38252439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE)); 38262439e4bfSJean-Christophe PLAGNIOL-VILLARD 38272439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Force link-up and also force full-duplex. */ 38282439e4bfSJean-Christophe PLAGNIOL-VILLARD ctrl = E1000_READ_REG(hw, CTRL); 38292439e4bfSJean-Christophe PLAGNIOL-VILLARD ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 38302439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, CTRL, ctrl); 38312439e4bfSJean-Christophe PLAGNIOL-VILLARD 38322439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Configure Flow Control after forcing link up. */ 38332439e4bfSJean-Christophe PLAGNIOL-VILLARD ret_val = e1000_config_fc_after_link_up(hw); 38342439e4bfSJean-Christophe PLAGNIOL-VILLARD if (ret_val < 0) { 38352439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("Error configuring flow control\n"); 38362439e4bfSJean-Christophe PLAGNIOL-VILLARD return ret_val; 38372439e4bfSJean-Christophe PLAGNIOL-VILLARD } 38382439e4bfSJean-Christophe PLAGNIOL-VILLARD } 38392439e4bfSJean-Christophe PLAGNIOL-VILLARD /* If we are forcing link and we are receiving /C/ ordered sets, re-enable 38402439e4bfSJean-Christophe PLAGNIOL-VILLARD * auto-negotiation in the TXCW register and disable forced link in the 38412439e4bfSJean-Christophe PLAGNIOL-VILLARD * Device Control register in an attempt to auto-negotiate with our link 38422439e4bfSJean-Christophe PLAGNIOL-VILLARD * partner. 38432439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 38442439e4bfSJean-Christophe PLAGNIOL-VILLARD else if ((hw->media_type == e1000_media_type_fiber) && 38452439e4bfSJean-Christophe PLAGNIOL-VILLARD (ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { 38462439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT 38472439e4bfSJean-Christophe PLAGNIOL-VILLARD ("RXing /C/, enable AutoNeg and stop forcing link.\r\n"); 38482439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, TXCW, hw->txcw); 38492439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU)); 38502439e4bfSJean-Christophe PLAGNIOL-VILLARD } 38512439e4bfSJean-Christophe PLAGNIOL-VILLARD return 0; 38522439e4bfSJean-Christophe PLAGNIOL-VILLARD } 38532439e4bfSJean-Christophe PLAGNIOL-VILLARD 38542439e4bfSJean-Christophe PLAGNIOL-VILLARD /****************************************************************************** 3855aa070789SRoy Zang * Configure the MAC-to-PHY interface for 10/100Mbps 3856aa070789SRoy Zang * 3857aa070789SRoy Zang * hw - Struct containing variables accessed by shared code 3858aa070789SRoy Zang ******************************************************************************/ 3859aa070789SRoy Zang static int32_t 3860aa070789SRoy Zang e1000_configure_kmrn_for_10_100(struct e1000_hw *hw, uint16_t duplex) 3861aa070789SRoy Zang { 3862aa070789SRoy Zang int32_t ret_val = E1000_SUCCESS; 3863aa070789SRoy Zang uint32_t tipg; 3864aa070789SRoy Zang uint16_t reg_data; 3865aa070789SRoy Zang 3866aa070789SRoy Zang DEBUGFUNC(); 3867aa070789SRoy Zang 3868aa070789SRoy Zang reg_data = E1000_KUMCTRLSTA_HD_CTRL_10_100_DEFAULT; 3869aa070789SRoy Zang ret_val = e1000_write_kmrn_reg(hw, 3870aa070789SRoy Zang E1000_KUMCTRLSTA_OFFSET_HD_CTRL, reg_data); 3871aa070789SRoy Zang if (ret_val) 3872aa070789SRoy Zang return ret_val; 3873aa070789SRoy Zang 3874aa070789SRoy Zang /* Configure Transmit Inter-Packet Gap */ 3875aa070789SRoy Zang tipg = E1000_READ_REG(hw, TIPG); 3876aa070789SRoy Zang tipg &= ~E1000_TIPG_IPGT_MASK; 3877aa070789SRoy Zang tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_10_100; 3878aa070789SRoy Zang E1000_WRITE_REG(hw, TIPG, tipg); 3879aa070789SRoy Zang 3880aa070789SRoy Zang ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data); 3881aa070789SRoy Zang 3882aa070789SRoy Zang if (ret_val) 3883aa070789SRoy Zang return ret_val; 3884aa070789SRoy Zang 3885aa070789SRoy Zang if (duplex == HALF_DUPLEX) 3886aa070789SRoy Zang reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER; 3887aa070789SRoy Zang else 3888aa070789SRoy Zang reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; 3889aa070789SRoy Zang 3890aa070789SRoy Zang ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data); 3891aa070789SRoy Zang 3892aa070789SRoy Zang return ret_val; 3893aa070789SRoy Zang } 3894aa070789SRoy Zang 3895aa070789SRoy Zang static int32_t 3896aa070789SRoy Zang e1000_configure_kmrn_for_1000(struct e1000_hw *hw) 3897aa070789SRoy Zang { 3898aa070789SRoy Zang int32_t ret_val = E1000_SUCCESS; 3899aa070789SRoy Zang uint16_t reg_data; 3900aa070789SRoy Zang uint32_t tipg; 3901aa070789SRoy Zang 3902aa070789SRoy Zang DEBUGFUNC(); 3903aa070789SRoy Zang 3904aa070789SRoy Zang reg_data = E1000_KUMCTRLSTA_HD_CTRL_1000_DEFAULT; 3905aa070789SRoy Zang ret_val = e1000_write_kmrn_reg(hw, 3906aa070789SRoy Zang E1000_KUMCTRLSTA_OFFSET_HD_CTRL, reg_data); 3907aa070789SRoy Zang if (ret_val) 3908aa070789SRoy Zang return ret_val; 3909aa070789SRoy Zang 3910aa070789SRoy Zang /* Configure Transmit Inter-Packet Gap */ 3911aa070789SRoy Zang tipg = E1000_READ_REG(hw, TIPG); 3912aa070789SRoy Zang tipg &= ~E1000_TIPG_IPGT_MASK; 3913aa070789SRoy Zang tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000; 3914aa070789SRoy Zang E1000_WRITE_REG(hw, TIPG, tipg); 3915aa070789SRoy Zang 3916aa070789SRoy Zang ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data); 3917aa070789SRoy Zang 3918aa070789SRoy Zang if (ret_val) 3919aa070789SRoy Zang return ret_val; 3920aa070789SRoy Zang 3921aa070789SRoy Zang reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; 3922aa070789SRoy Zang ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data); 3923aa070789SRoy Zang 3924aa070789SRoy Zang return ret_val; 3925aa070789SRoy Zang } 3926aa070789SRoy Zang 3927aa070789SRoy Zang /****************************************************************************** 39282439e4bfSJean-Christophe PLAGNIOL-VILLARD * Detects the current speed and duplex settings of the hardware. 39292439e4bfSJean-Christophe PLAGNIOL-VILLARD * 39302439e4bfSJean-Christophe PLAGNIOL-VILLARD * hw - Struct containing variables accessed by shared code 39312439e4bfSJean-Christophe PLAGNIOL-VILLARD * speed - Speed of the connection 39322439e4bfSJean-Christophe PLAGNIOL-VILLARD * duplex - Duplex setting of the connection 39332439e4bfSJean-Christophe PLAGNIOL-VILLARD *****************************************************************************/ 3934aa070789SRoy Zang static int 3935aa070789SRoy Zang e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t *speed, 3936aa070789SRoy Zang uint16_t *duplex) 39372439e4bfSJean-Christophe PLAGNIOL-VILLARD { 39382439e4bfSJean-Christophe PLAGNIOL-VILLARD uint32_t status; 3939aa070789SRoy Zang int32_t ret_val; 3940aa070789SRoy Zang uint16_t phy_data; 39412439e4bfSJean-Christophe PLAGNIOL-VILLARD 39422439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGFUNC(); 39432439e4bfSJean-Christophe PLAGNIOL-VILLARD 39442439e4bfSJean-Christophe PLAGNIOL-VILLARD if (hw->mac_type >= e1000_82543) { 39452439e4bfSJean-Christophe PLAGNIOL-VILLARD status = E1000_READ_REG(hw, STATUS); 39462439e4bfSJean-Christophe PLAGNIOL-VILLARD if (status & E1000_STATUS_SPEED_1000) { 39472439e4bfSJean-Christophe PLAGNIOL-VILLARD *speed = SPEED_1000; 39482439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("1000 Mbs, "); 39492439e4bfSJean-Christophe PLAGNIOL-VILLARD } else if (status & E1000_STATUS_SPEED_100) { 39502439e4bfSJean-Christophe PLAGNIOL-VILLARD *speed = SPEED_100; 39512439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("100 Mbs, "); 39522439e4bfSJean-Christophe PLAGNIOL-VILLARD } else { 39532439e4bfSJean-Christophe PLAGNIOL-VILLARD *speed = SPEED_10; 39542439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("10 Mbs, "); 39552439e4bfSJean-Christophe PLAGNIOL-VILLARD } 39562439e4bfSJean-Christophe PLAGNIOL-VILLARD 39572439e4bfSJean-Christophe PLAGNIOL-VILLARD if (status & E1000_STATUS_FD) { 39582439e4bfSJean-Christophe PLAGNIOL-VILLARD *duplex = FULL_DUPLEX; 39592439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("Full Duplex\r\n"); 39602439e4bfSJean-Christophe PLAGNIOL-VILLARD } else { 39612439e4bfSJean-Christophe PLAGNIOL-VILLARD *duplex = HALF_DUPLEX; 39622439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT(" Half Duplex\r\n"); 39632439e4bfSJean-Christophe PLAGNIOL-VILLARD } 39642439e4bfSJean-Christophe PLAGNIOL-VILLARD } else { 39652439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("1000 Mbs, Full Duplex\r\n"); 39662439e4bfSJean-Christophe PLAGNIOL-VILLARD *speed = SPEED_1000; 39672439e4bfSJean-Christophe PLAGNIOL-VILLARD *duplex = FULL_DUPLEX; 39682439e4bfSJean-Christophe PLAGNIOL-VILLARD } 3969aa070789SRoy Zang 3970aa070789SRoy Zang /* IGP01 PHY may advertise full duplex operation after speed downgrade 3971aa070789SRoy Zang * even if it is operating at half duplex. Here we set the duplex 3972aa070789SRoy Zang * settings to match the duplex in the link partner's capabilities. 3973aa070789SRoy Zang */ 3974aa070789SRoy Zang if (hw->phy_type == e1000_phy_igp && hw->speed_downgraded) { 3975aa070789SRoy Zang ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data); 3976aa070789SRoy Zang if (ret_val) 3977aa070789SRoy Zang return ret_val; 3978aa070789SRoy Zang 3979aa070789SRoy Zang if (!(phy_data & NWAY_ER_LP_NWAY_CAPS)) 3980aa070789SRoy Zang *duplex = HALF_DUPLEX; 3981aa070789SRoy Zang else { 3982aa070789SRoy Zang ret_val = e1000_read_phy_reg(hw, 3983aa070789SRoy Zang PHY_LP_ABILITY, &phy_data); 3984aa070789SRoy Zang if (ret_val) 3985aa070789SRoy Zang return ret_val; 3986aa070789SRoy Zang if ((*speed == SPEED_100 && 3987aa070789SRoy Zang !(phy_data & NWAY_LPAR_100TX_FD_CAPS)) 3988aa070789SRoy Zang || (*speed == SPEED_10 3989aa070789SRoy Zang && !(phy_data & NWAY_LPAR_10T_FD_CAPS))) 3990aa070789SRoy Zang *duplex = HALF_DUPLEX; 3991aa070789SRoy Zang } 3992aa070789SRoy Zang } 3993aa070789SRoy Zang 3994aa070789SRoy Zang if ((hw->mac_type == e1000_80003es2lan) && 3995aa070789SRoy Zang (hw->media_type == e1000_media_type_copper)) { 3996aa070789SRoy Zang if (*speed == SPEED_1000) 3997aa070789SRoy Zang ret_val = e1000_configure_kmrn_for_1000(hw); 3998aa070789SRoy Zang else 3999aa070789SRoy Zang ret_val = e1000_configure_kmrn_for_10_100(hw, *duplex); 4000aa070789SRoy Zang if (ret_val) 4001aa070789SRoy Zang return ret_val; 4002aa070789SRoy Zang } 4003aa070789SRoy Zang return E1000_SUCCESS; 40042439e4bfSJean-Christophe PLAGNIOL-VILLARD } 40052439e4bfSJean-Christophe PLAGNIOL-VILLARD 40062439e4bfSJean-Christophe PLAGNIOL-VILLARD /****************************************************************************** 40072439e4bfSJean-Christophe PLAGNIOL-VILLARD * Blocks until autoneg completes or times out (~4.5 seconds) 40082439e4bfSJean-Christophe PLAGNIOL-VILLARD * 40092439e4bfSJean-Christophe PLAGNIOL-VILLARD * hw - Struct containing variables accessed by shared code 40102439e4bfSJean-Christophe PLAGNIOL-VILLARD ******************************************************************************/ 40112439e4bfSJean-Christophe PLAGNIOL-VILLARD static int 40122439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_wait_autoneg(struct e1000_hw *hw) 40132439e4bfSJean-Christophe PLAGNIOL-VILLARD { 40142439e4bfSJean-Christophe PLAGNIOL-VILLARD uint16_t i; 40152439e4bfSJean-Christophe PLAGNIOL-VILLARD uint16_t phy_data; 40162439e4bfSJean-Christophe PLAGNIOL-VILLARD 40172439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGFUNC(); 40182439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("Waiting for Auto-Neg to complete.\n"); 40192439e4bfSJean-Christophe PLAGNIOL-VILLARD 4020faa765d4SStefan Roese /* We will wait for autoneg to complete or timeout to expire. */ 40212439e4bfSJean-Christophe PLAGNIOL-VILLARD for (i = PHY_AUTO_NEG_TIME; i > 0; i--) { 40222439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Read the MII Status Register and wait for Auto-Neg 40232439e4bfSJean-Christophe PLAGNIOL-VILLARD * Complete bit to be set. 40242439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 40252439e4bfSJean-Christophe PLAGNIOL-VILLARD if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) { 40262439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("PHY Read Error\n"); 40272439e4bfSJean-Christophe PLAGNIOL-VILLARD return -E1000_ERR_PHY; 40282439e4bfSJean-Christophe PLAGNIOL-VILLARD } 40292439e4bfSJean-Christophe PLAGNIOL-VILLARD if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) { 40302439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("PHY Read Error\n"); 40312439e4bfSJean-Christophe PLAGNIOL-VILLARD return -E1000_ERR_PHY; 40322439e4bfSJean-Christophe PLAGNIOL-VILLARD } 40332439e4bfSJean-Christophe PLAGNIOL-VILLARD if (phy_data & MII_SR_AUTONEG_COMPLETE) { 40342439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("Auto-Neg complete.\n"); 40352439e4bfSJean-Christophe PLAGNIOL-VILLARD return 0; 40362439e4bfSJean-Christophe PLAGNIOL-VILLARD } 40372439e4bfSJean-Christophe PLAGNIOL-VILLARD mdelay(100); 40382439e4bfSJean-Christophe PLAGNIOL-VILLARD } 40392439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("Auto-Neg timedout.\n"); 40402439e4bfSJean-Christophe PLAGNIOL-VILLARD return -E1000_ERR_TIMEOUT; 40412439e4bfSJean-Christophe PLAGNIOL-VILLARD } 40422439e4bfSJean-Christophe PLAGNIOL-VILLARD 40432439e4bfSJean-Christophe PLAGNIOL-VILLARD /****************************************************************************** 40442439e4bfSJean-Christophe PLAGNIOL-VILLARD * Raises the Management Data Clock 40452439e4bfSJean-Christophe PLAGNIOL-VILLARD * 40462439e4bfSJean-Christophe PLAGNIOL-VILLARD * hw - Struct containing variables accessed by shared code 40472439e4bfSJean-Christophe PLAGNIOL-VILLARD * ctrl - Device control register's current value 40482439e4bfSJean-Christophe PLAGNIOL-VILLARD ******************************************************************************/ 40492439e4bfSJean-Christophe PLAGNIOL-VILLARD static void 40502439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_raise_mdi_clk(struct e1000_hw *hw, uint32_t * ctrl) 40512439e4bfSJean-Christophe PLAGNIOL-VILLARD { 40522439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Raise the clock input to the Management Data Clock (by setting the MDC 40532439e4bfSJean-Christophe PLAGNIOL-VILLARD * bit), and then delay 2 microseconds. 40542439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 40552439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC)); 40562439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_FLUSH(hw); 40572439e4bfSJean-Christophe PLAGNIOL-VILLARD udelay(2); 40582439e4bfSJean-Christophe PLAGNIOL-VILLARD } 40592439e4bfSJean-Christophe PLAGNIOL-VILLARD 40602439e4bfSJean-Christophe PLAGNIOL-VILLARD /****************************************************************************** 40612439e4bfSJean-Christophe PLAGNIOL-VILLARD * Lowers the Management Data Clock 40622439e4bfSJean-Christophe PLAGNIOL-VILLARD * 40632439e4bfSJean-Christophe PLAGNIOL-VILLARD * hw - Struct containing variables accessed by shared code 40642439e4bfSJean-Christophe PLAGNIOL-VILLARD * ctrl - Device control register's current value 40652439e4bfSJean-Christophe PLAGNIOL-VILLARD ******************************************************************************/ 40662439e4bfSJean-Christophe PLAGNIOL-VILLARD static void 40672439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_lower_mdi_clk(struct e1000_hw *hw, uint32_t * ctrl) 40682439e4bfSJean-Christophe PLAGNIOL-VILLARD { 40692439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Lower the clock input to the Management Data Clock (by clearing the MDC 40702439e4bfSJean-Christophe PLAGNIOL-VILLARD * bit), and then delay 2 microseconds. 40712439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 40722439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC)); 40732439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_FLUSH(hw); 40742439e4bfSJean-Christophe PLAGNIOL-VILLARD udelay(2); 40752439e4bfSJean-Christophe PLAGNIOL-VILLARD } 40762439e4bfSJean-Christophe PLAGNIOL-VILLARD 40772439e4bfSJean-Christophe PLAGNIOL-VILLARD /****************************************************************************** 40782439e4bfSJean-Christophe PLAGNIOL-VILLARD * Shifts data bits out to the PHY 40792439e4bfSJean-Christophe PLAGNIOL-VILLARD * 40802439e4bfSJean-Christophe PLAGNIOL-VILLARD * hw - Struct containing variables accessed by shared code 40812439e4bfSJean-Christophe PLAGNIOL-VILLARD * data - Data to send out to the PHY 40822439e4bfSJean-Christophe PLAGNIOL-VILLARD * count - Number of bits to shift out 40832439e4bfSJean-Christophe PLAGNIOL-VILLARD * 40842439e4bfSJean-Christophe PLAGNIOL-VILLARD * Bits are shifted out in MSB to LSB order. 40852439e4bfSJean-Christophe PLAGNIOL-VILLARD ******************************************************************************/ 40862439e4bfSJean-Christophe PLAGNIOL-VILLARD static void 40872439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_shift_out_mdi_bits(struct e1000_hw *hw, uint32_t data, uint16_t count) 40882439e4bfSJean-Christophe PLAGNIOL-VILLARD { 40892439e4bfSJean-Christophe PLAGNIOL-VILLARD uint32_t ctrl; 40902439e4bfSJean-Christophe PLAGNIOL-VILLARD uint32_t mask; 40912439e4bfSJean-Christophe PLAGNIOL-VILLARD 40922439e4bfSJean-Christophe PLAGNIOL-VILLARD /* We need to shift "count" number of bits out to the PHY. So, the value 40932439e4bfSJean-Christophe PLAGNIOL-VILLARD * in the "data" parameter will be shifted out to the PHY one bit at a 40942439e4bfSJean-Christophe PLAGNIOL-VILLARD * time. In order to do this, "data" must be broken down into bits. 40952439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 40962439e4bfSJean-Christophe PLAGNIOL-VILLARD mask = 0x01; 40972439e4bfSJean-Christophe PLAGNIOL-VILLARD mask <<= (count - 1); 40982439e4bfSJean-Christophe PLAGNIOL-VILLARD 40992439e4bfSJean-Christophe PLAGNIOL-VILLARD ctrl = E1000_READ_REG(hw, CTRL); 41002439e4bfSJean-Christophe PLAGNIOL-VILLARD 41012439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */ 41022439e4bfSJean-Christophe PLAGNIOL-VILLARD ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR); 41032439e4bfSJean-Christophe PLAGNIOL-VILLARD 41042439e4bfSJean-Christophe PLAGNIOL-VILLARD while (mask) { 41052439e4bfSJean-Christophe PLAGNIOL-VILLARD /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and 41062439e4bfSJean-Christophe PLAGNIOL-VILLARD * then raising and lowering the Management Data Clock. A "0" is 41072439e4bfSJean-Christophe PLAGNIOL-VILLARD * shifted out to the PHY by setting the MDIO bit to "0" and then 41082439e4bfSJean-Christophe PLAGNIOL-VILLARD * raising and lowering the clock. 41092439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 41102439e4bfSJean-Christophe PLAGNIOL-VILLARD if (data & mask) 41112439e4bfSJean-Christophe PLAGNIOL-VILLARD ctrl |= E1000_CTRL_MDIO; 41122439e4bfSJean-Christophe PLAGNIOL-VILLARD else 41132439e4bfSJean-Christophe PLAGNIOL-VILLARD ctrl &= ~E1000_CTRL_MDIO; 41142439e4bfSJean-Christophe PLAGNIOL-VILLARD 41152439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, CTRL, ctrl); 41162439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_FLUSH(hw); 41172439e4bfSJean-Christophe PLAGNIOL-VILLARD 41182439e4bfSJean-Christophe PLAGNIOL-VILLARD udelay(2); 41192439e4bfSJean-Christophe PLAGNIOL-VILLARD 41202439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_raise_mdi_clk(hw, &ctrl); 41212439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_lower_mdi_clk(hw, &ctrl); 41222439e4bfSJean-Christophe PLAGNIOL-VILLARD 41232439e4bfSJean-Christophe PLAGNIOL-VILLARD mask = mask >> 1; 41242439e4bfSJean-Christophe PLAGNIOL-VILLARD } 41252439e4bfSJean-Christophe PLAGNIOL-VILLARD } 41262439e4bfSJean-Christophe PLAGNIOL-VILLARD 41272439e4bfSJean-Christophe PLAGNIOL-VILLARD /****************************************************************************** 41282439e4bfSJean-Christophe PLAGNIOL-VILLARD * Shifts data bits in from the PHY 41292439e4bfSJean-Christophe PLAGNIOL-VILLARD * 41302439e4bfSJean-Christophe PLAGNIOL-VILLARD * hw - Struct containing variables accessed by shared code 41312439e4bfSJean-Christophe PLAGNIOL-VILLARD * 41322439e4bfSJean-Christophe PLAGNIOL-VILLARD * Bits are shifted in in MSB to LSB order. 41332439e4bfSJean-Christophe PLAGNIOL-VILLARD ******************************************************************************/ 41342439e4bfSJean-Christophe PLAGNIOL-VILLARD static uint16_t 41352439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_shift_in_mdi_bits(struct e1000_hw *hw) 41362439e4bfSJean-Christophe PLAGNIOL-VILLARD { 41372439e4bfSJean-Christophe PLAGNIOL-VILLARD uint32_t ctrl; 41382439e4bfSJean-Christophe PLAGNIOL-VILLARD uint16_t data = 0; 41392439e4bfSJean-Christophe PLAGNIOL-VILLARD uint8_t i; 41402439e4bfSJean-Christophe PLAGNIOL-VILLARD 41412439e4bfSJean-Christophe PLAGNIOL-VILLARD /* In order to read a register from the PHY, we need to shift in a total 41422439e4bfSJean-Christophe PLAGNIOL-VILLARD * of 18 bits from the PHY. The first two bit (turnaround) times are used 41432439e4bfSJean-Christophe PLAGNIOL-VILLARD * to avoid contention on the MDIO pin when a read operation is performed. 41442439e4bfSJean-Christophe PLAGNIOL-VILLARD * These two bits are ignored by us and thrown away. Bits are "shifted in" 41452439e4bfSJean-Christophe PLAGNIOL-VILLARD * by raising the input to the Management Data Clock (setting the MDC bit), 41462439e4bfSJean-Christophe PLAGNIOL-VILLARD * and then reading the value of the MDIO bit. 41472439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 41482439e4bfSJean-Christophe PLAGNIOL-VILLARD ctrl = E1000_READ_REG(hw, CTRL); 41492439e4bfSJean-Christophe PLAGNIOL-VILLARD 41502439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */ 41512439e4bfSJean-Christophe PLAGNIOL-VILLARD ctrl &= ~E1000_CTRL_MDIO_DIR; 41522439e4bfSJean-Christophe PLAGNIOL-VILLARD ctrl &= ~E1000_CTRL_MDIO; 41532439e4bfSJean-Christophe PLAGNIOL-VILLARD 41542439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, CTRL, ctrl); 41552439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_FLUSH(hw); 41562439e4bfSJean-Christophe PLAGNIOL-VILLARD 41572439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Raise and Lower the clock before reading in the data. This accounts for 41582439e4bfSJean-Christophe PLAGNIOL-VILLARD * the turnaround bits. The first clock occurred when we clocked out the 41592439e4bfSJean-Christophe PLAGNIOL-VILLARD * last bit of the Register Address. 41602439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 41612439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_raise_mdi_clk(hw, &ctrl); 41622439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_lower_mdi_clk(hw, &ctrl); 41632439e4bfSJean-Christophe PLAGNIOL-VILLARD 41642439e4bfSJean-Christophe PLAGNIOL-VILLARD for (data = 0, i = 0; i < 16; i++) { 41652439e4bfSJean-Christophe PLAGNIOL-VILLARD data = data << 1; 41662439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_raise_mdi_clk(hw, &ctrl); 41672439e4bfSJean-Christophe PLAGNIOL-VILLARD ctrl = E1000_READ_REG(hw, CTRL); 41682439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Check to see if we shifted in a "1". */ 41692439e4bfSJean-Christophe PLAGNIOL-VILLARD if (ctrl & E1000_CTRL_MDIO) 41702439e4bfSJean-Christophe PLAGNIOL-VILLARD data |= 1; 41712439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_lower_mdi_clk(hw, &ctrl); 41722439e4bfSJean-Christophe PLAGNIOL-VILLARD } 41732439e4bfSJean-Christophe PLAGNIOL-VILLARD 41742439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_raise_mdi_clk(hw, &ctrl); 41752439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_lower_mdi_clk(hw, &ctrl); 41762439e4bfSJean-Christophe PLAGNIOL-VILLARD 41772439e4bfSJean-Christophe PLAGNIOL-VILLARD return data; 41782439e4bfSJean-Christophe PLAGNIOL-VILLARD } 41792439e4bfSJean-Christophe PLAGNIOL-VILLARD 41802439e4bfSJean-Christophe PLAGNIOL-VILLARD /***************************************************************************** 41812439e4bfSJean-Christophe PLAGNIOL-VILLARD * Reads the value from a PHY register 41822439e4bfSJean-Christophe PLAGNIOL-VILLARD * 41832439e4bfSJean-Christophe PLAGNIOL-VILLARD * hw - Struct containing variables accessed by shared code 41842439e4bfSJean-Christophe PLAGNIOL-VILLARD * reg_addr - address of the PHY register to read 41852439e4bfSJean-Christophe PLAGNIOL-VILLARD ******************************************************************************/ 41862439e4bfSJean-Christophe PLAGNIOL-VILLARD static int 41872439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t * phy_data) 41882439e4bfSJean-Christophe PLAGNIOL-VILLARD { 41892439e4bfSJean-Christophe PLAGNIOL-VILLARD uint32_t i; 41902439e4bfSJean-Christophe PLAGNIOL-VILLARD uint32_t mdic = 0; 41912439e4bfSJean-Christophe PLAGNIOL-VILLARD const uint32_t phy_addr = 1; 41922439e4bfSJean-Christophe PLAGNIOL-VILLARD 41932439e4bfSJean-Christophe PLAGNIOL-VILLARD if (reg_addr > MAX_PHY_REG_ADDRESS) { 41942439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("PHY Address %d is out of range\n", reg_addr); 41952439e4bfSJean-Christophe PLAGNIOL-VILLARD return -E1000_ERR_PARAM; 41962439e4bfSJean-Christophe PLAGNIOL-VILLARD } 41972439e4bfSJean-Christophe PLAGNIOL-VILLARD 41982439e4bfSJean-Christophe PLAGNIOL-VILLARD if (hw->mac_type > e1000_82543) { 41992439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Set up Op-code, Phy Address, and register address in the MDI 42002439e4bfSJean-Christophe PLAGNIOL-VILLARD * Control register. The MAC will take care of interfacing with the 42012439e4bfSJean-Christophe PLAGNIOL-VILLARD * PHY to retrieve the desired data. 42022439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 42032439e4bfSJean-Christophe PLAGNIOL-VILLARD mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) | 42042439e4bfSJean-Christophe PLAGNIOL-VILLARD (phy_addr << E1000_MDIC_PHY_SHIFT) | 42052439e4bfSJean-Christophe PLAGNIOL-VILLARD (E1000_MDIC_OP_READ)); 42062439e4bfSJean-Christophe PLAGNIOL-VILLARD 42072439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, MDIC, mdic); 42082439e4bfSJean-Christophe PLAGNIOL-VILLARD 42092439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Poll the ready bit to see if the MDI read completed */ 42102439e4bfSJean-Christophe PLAGNIOL-VILLARD for (i = 0; i < 64; i++) { 42112439e4bfSJean-Christophe PLAGNIOL-VILLARD udelay(10); 42122439e4bfSJean-Christophe PLAGNIOL-VILLARD mdic = E1000_READ_REG(hw, MDIC); 42132439e4bfSJean-Christophe PLAGNIOL-VILLARD if (mdic & E1000_MDIC_READY) 42142439e4bfSJean-Christophe PLAGNIOL-VILLARD break; 42152439e4bfSJean-Christophe PLAGNIOL-VILLARD } 42162439e4bfSJean-Christophe PLAGNIOL-VILLARD if (!(mdic & E1000_MDIC_READY)) { 42172439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("MDI Read did not complete\n"); 42182439e4bfSJean-Christophe PLAGNIOL-VILLARD return -E1000_ERR_PHY; 42192439e4bfSJean-Christophe PLAGNIOL-VILLARD } 42202439e4bfSJean-Christophe PLAGNIOL-VILLARD if (mdic & E1000_MDIC_ERROR) { 42212439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("MDI Error\n"); 42222439e4bfSJean-Christophe PLAGNIOL-VILLARD return -E1000_ERR_PHY; 42232439e4bfSJean-Christophe PLAGNIOL-VILLARD } 42242439e4bfSJean-Christophe PLAGNIOL-VILLARD *phy_data = (uint16_t) mdic; 42252439e4bfSJean-Christophe PLAGNIOL-VILLARD } else { 42262439e4bfSJean-Christophe PLAGNIOL-VILLARD /* We must first send a preamble through the MDIO pin to signal the 42272439e4bfSJean-Christophe PLAGNIOL-VILLARD * beginning of an MII instruction. This is done by sending 32 42282439e4bfSJean-Christophe PLAGNIOL-VILLARD * consecutive "1" bits. 42292439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 42302439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); 42312439e4bfSJean-Christophe PLAGNIOL-VILLARD 42322439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Now combine the next few fields that are required for a read 42332439e4bfSJean-Christophe PLAGNIOL-VILLARD * operation. We use this method instead of calling the 42342439e4bfSJean-Christophe PLAGNIOL-VILLARD * e1000_shift_out_mdi_bits routine five different times. The format of 42352439e4bfSJean-Christophe PLAGNIOL-VILLARD * a MII read instruction consists of a shift out of 14 bits and is 42362439e4bfSJean-Christophe PLAGNIOL-VILLARD * defined as follows: 42372439e4bfSJean-Christophe PLAGNIOL-VILLARD * <Preamble><SOF><Op Code><Phy Addr><Reg Addr> 42382439e4bfSJean-Christophe PLAGNIOL-VILLARD * followed by a shift in of 18 bits. This first two bits shifted in 42392439e4bfSJean-Christophe PLAGNIOL-VILLARD * are TurnAround bits used to avoid contention on the MDIO pin when a 42402439e4bfSJean-Christophe PLAGNIOL-VILLARD * READ operation is performed. These two bits are thrown away 42412439e4bfSJean-Christophe PLAGNIOL-VILLARD * followed by a shift in of 16 bits which contains the desired data. 42422439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 42432439e4bfSJean-Christophe PLAGNIOL-VILLARD mdic = ((reg_addr) | (phy_addr << 5) | 42442439e4bfSJean-Christophe PLAGNIOL-VILLARD (PHY_OP_READ << 10) | (PHY_SOF << 12)); 42452439e4bfSJean-Christophe PLAGNIOL-VILLARD 42462439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_shift_out_mdi_bits(hw, mdic, 14); 42472439e4bfSJean-Christophe PLAGNIOL-VILLARD 42482439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Now that we've shifted out the read command to the MII, we need to 42492439e4bfSJean-Christophe PLAGNIOL-VILLARD * "shift in" the 16-bit value (18 total bits) of the requested PHY 42502439e4bfSJean-Christophe PLAGNIOL-VILLARD * register address. 42512439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 42522439e4bfSJean-Christophe PLAGNIOL-VILLARD *phy_data = e1000_shift_in_mdi_bits(hw); 42532439e4bfSJean-Christophe PLAGNIOL-VILLARD } 42542439e4bfSJean-Christophe PLAGNIOL-VILLARD return 0; 42552439e4bfSJean-Christophe PLAGNIOL-VILLARD } 42562439e4bfSJean-Christophe PLAGNIOL-VILLARD 42572439e4bfSJean-Christophe PLAGNIOL-VILLARD /****************************************************************************** 42582439e4bfSJean-Christophe PLAGNIOL-VILLARD * Writes a value to a PHY register 42592439e4bfSJean-Christophe PLAGNIOL-VILLARD * 42602439e4bfSJean-Christophe PLAGNIOL-VILLARD * hw - Struct containing variables accessed by shared code 42612439e4bfSJean-Christophe PLAGNIOL-VILLARD * reg_addr - address of the PHY register to write 42622439e4bfSJean-Christophe PLAGNIOL-VILLARD * data - data to write to the PHY 42632439e4bfSJean-Christophe PLAGNIOL-VILLARD ******************************************************************************/ 42642439e4bfSJean-Christophe PLAGNIOL-VILLARD static int 42652439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t phy_data) 42662439e4bfSJean-Christophe PLAGNIOL-VILLARD { 42672439e4bfSJean-Christophe PLAGNIOL-VILLARD uint32_t i; 42682439e4bfSJean-Christophe PLAGNIOL-VILLARD uint32_t mdic = 0; 42692439e4bfSJean-Christophe PLAGNIOL-VILLARD const uint32_t phy_addr = 1; 42702439e4bfSJean-Christophe PLAGNIOL-VILLARD 42712439e4bfSJean-Christophe PLAGNIOL-VILLARD if (reg_addr > MAX_PHY_REG_ADDRESS) { 42722439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("PHY Address %d is out of range\n", reg_addr); 42732439e4bfSJean-Christophe PLAGNIOL-VILLARD return -E1000_ERR_PARAM; 42742439e4bfSJean-Christophe PLAGNIOL-VILLARD } 42752439e4bfSJean-Christophe PLAGNIOL-VILLARD 42762439e4bfSJean-Christophe PLAGNIOL-VILLARD if (hw->mac_type > e1000_82543) { 42772439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Set up Op-code, Phy Address, register address, and data intended 42782439e4bfSJean-Christophe PLAGNIOL-VILLARD * for the PHY register in the MDI Control register. The MAC will take 42792439e4bfSJean-Christophe PLAGNIOL-VILLARD * care of interfacing with the PHY to send the desired data. 42802439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 42812439e4bfSJean-Christophe PLAGNIOL-VILLARD mdic = (((uint32_t) phy_data) | 42822439e4bfSJean-Christophe PLAGNIOL-VILLARD (reg_addr << E1000_MDIC_REG_SHIFT) | 42832439e4bfSJean-Christophe PLAGNIOL-VILLARD (phy_addr << E1000_MDIC_PHY_SHIFT) | 42842439e4bfSJean-Christophe PLAGNIOL-VILLARD (E1000_MDIC_OP_WRITE)); 42852439e4bfSJean-Christophe PLAGNIOL-VILLARD 42862439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, MDIC, mdic); 42872439e4bfSJean-Christophe PLAGNIOL-VILLARD 42882439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Poll the ready bit to see if the MDI read completed */ 42892439e4bfSJean-Christophe PLAGNIOL-VILLARD for (i = 0; i < 64; i++) { 42902439e4bfSJean-Christophe PLAGNIOL-VILLARD udelay(10); 42912439e4bfSJean-Christophe PLAGNIOL-VILLARD mdic = E1000_READ_REG(hw, MDIC); 42922439e4bfSJean-Christophe PLAGNIOL-VILLARD if (mdic & E1000_MDIC_READY) 42932439e4bfSJean-Christophe PLAGNIOL-VILLARD break; 42942439e4bfSJean-Christophe PLAGNIOL-VILLARD } 42952439e4bfSJean-Christophe PLAGNIOL-VILLARD if (!(mdic & E1000_MDIC_READY)) { 42962439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("MDI Write did not complete\n"); 42972439e4bfSJean-Christophe PLAGNIOL-VILLARD return -E1000_ERR_PHY; 42982439e4bfSJean-Christophe PLAGNIOL-VILLARD } 42992439e4bfSJean-Christophe PLAGNIOL-VILLARD } else { 43002439e4bfSJean-Christophe PLAGNIOL-VILLARD /* We'll need to use the SW defined pins to shift the write command 43012439e4bfSJean-Christophe PLAGNIOL-VILLARD * out to the PHY. We first send a preamble to the PHY to signal the 43022439e4bfSJean-Christophe PLAGNIOL-VILLARD * beginning of the MII instruction. This is done by sending 32 43032439e4bfSJean-Christophe PLAGNIOL-VILLARD * consecutive "1" bits. 43042439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 43052439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); 43062439e4bfSJean-Christophe PLAGNIOL-VILLARD 43072439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Now combine the remaining required fields that will indicate a 43082439e4bfSJean-Christophe PLAGNIOL-VILLARD * write operation. We use this method instead of calling the 43092439e4bfSJean-Christophe PLAGNIOL-VILLARD * e1000_shift_out_mdi_bits routine for each field in the command. The 43102439e4bfSJean-Christophe PLAGNIOL-VILLARD * format of a MII write instruction is as follows: 43112439e4bfSJean-Christophe PLAGNIOL-VILLARD * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>. 43122439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 43132439e4bfSJean-Christophe PLAGNIOL-VILLARD mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) | 43142439e4bfSJean-Christophe PLAGNIOL-VILLARD (PHY_OP_WRITE << 12) | (PHY_SOF << 14)); 43152439e4bfSJean-Christophe PLAGNIOL-VILLARD mdic <<= 16; 43162439e4bfSJean-Christophe PLAGNIOL-VILLARD mdic |= (uint32_t) phy_data; 43172439e4bfSJean-Christophe PLAGNIOL-VILLARD 43182439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_shift_out_mdi_bits(hw, mdic, 32); 43192439e4bfSJean-Christophe PLAGNIOL-VILLARD } 43202439e4bfSJean-Christophe PLAGNIOL-VILLARD return 0; 43212439e4bfSJean-Christophe PLAGNIOL-VILLARD } 43222439e4bfSJean-Christophe PLAGNIOL-VILLARD 43232439e4bfSJean-Christophe PLAGNIOL-VILLARD /****************************************************************************** 4324aa070789SRoy Zang * Checks if PHY reset is blocked due to SOL/IDER session, for example. 4325aa070789SRoy Zang * Returning E1000_BLK_PHY_RESET isn't necessarily an error. But it's up to 4326aa070789SRoy Zang * the caller to figure out how to deal with it. 4327aa070789SRoy Zang * 4328aa070789SRoy Zang * hw - Struct containing variables accessed by shared code 4329aa070789SRoy Zang * 4330aa070789SRoy Zang * returns: - E1000_BLK_PHY_RESET 4331aa070789SRoy Zang * E1000_SUCCESS 4332aa070789SRoy Zang * 4333aa070789SRoy Zang *****************************************************************************/ 4334aa070789SRoy Zang int32_t 4335aa070789SRoy Zang e1000_check_phy_reset_block(struct e1000_hw *hw) 4336aa070789SRoy Zang { 4337aa070789SRoy Zang uint32_t manc = 0; 4338aa070789SRoy Zang uint32_t fwsm = 0; 4339aa070789SRoy Zang 4340aa070789SRoy Zang if (hw->mac_type == e1000_ich8lan) { 4341aa070789SRoy Zang fwsm = E1000_READ_REG(hw, FWSM); 4342aa070789SRoy Zang return (fwsm & E1000_FWSM_RSPCIPHY) ? E1000_SUCCESS 4343aa070789SRoy Zang : E1000_BLK_PHY_RESET; 4344aa070789SRoy Zang } 4345aa070789SRoy Zang 4346aa070789SRoy Zang if (hw->mac_type > e1000_82547_rev_2) 4347aa070789SRoy Zang manc = E1000_READ_REG(hw, MANC); 4348aa070789SRoy Zang return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ? 4349aa070789SRoy Zang E1000_BLK_PHY_RESET : E1000_SUCCESS; 4350aa070789SRoy Zang } 4351aa070789SRoy Zang 4352aa070789SRoy Zang /*************************************************************************** 4353aa070789SRoy Zang * Checks if the PHY configuration is done 4354aa070789SRoy Zang * 4355aa070789SRoy Zang * hw: Struct containing variables accessed by shared code 4356aa070789SRoy Zang * 4357aa070789SRoy Zang * returns: - E1000_ERR_RESET if fail to reset MAC 4358aa070789SRoy Zang * E1000_SUCCESS at any other case. 4359aa070789SRoy Zang * 4360aa070789SRoy Zang ***************************************************************************/ 4361aa070789SRoy Zang static int32_t 4362aa070789SRoy Zang e1000_get_phy_cfg_done(struct e1000_hw *hw) 4363aa070789SRoy Zang { 4364aa070789SRoy Zang int32_t timeout = PHY_CFG_TIMEOUT; 4365aa070789SRoy Zang uint32_t cfg_mask = E1000_EEPROM_CFG_DONE; 4366aa070789SRoy Zang 4367aa070789SRoy Zang DEBUGFUNC(); 4368aa070789SRoy Zang 4369aa070789SRoy Zang switch (hw->mac_type) { 4370aa070789SRoy Zang default: 4371aa070789SRoy Zang mdelay(10); 4372aa070789SRoy Zang break; 4373987b43a1SKyle Moffett 4374aa070789SRoy Zang case e1000_80003es2lan: 4375aa070789SRoy Zang /* Separate *_CFG_DONE_* bit for each port */ 4376987b43a1SKyle Moffett if (e1000_is_second_port(hw)) 4377aa070789SRoy Zang cfg_mask = E1000_EEPROM_CFG_DONE_PORT_1; 4378aa070789SRoy Zang /* Fall Through */ 4379987b43a1SKyle Moffett 4380aa070789SRoy Zang case e1000_82571: 4381aa070789SRoy Zang case e1000_82572: 438295186063SMarek Vasut case e1000_igb: 4383aa070789SRoy Zang while (timeout) { 438495186063SMarek Vasut if (hw->mac_type == e1000_igb) { 438595186063SMarek Vasut if (E1000_READ_REG(hw, I210_EEMNGCTL) & cfg_mask) 438695186063SMarek Vasut break; 438795186063SMarek Vasut } else { 4388aa070789SRoy Zang if (E1000_READ_REG(hw, EEMNGCTL) & cfg_mask) 4389aa070789SRoy Zang break; 439095186063SMarek Vasut } 4391aa070789SRoy Zang mdelay(1); 4392aa070789SRoy Zang timeout--; 4393aa070789SRoy Zang } 4394aa070789SRoy Zang if (!timeout) { 4395aa070789SRoy Zang DEBUGOUT("MNG configuration cycle has not " 4396aa070789SRoy Zang "completed.\n"); 4397aa070789SRoy Zang return -E1000_ERR_RESET; 4398aa070789SRoy Zang } 4399aa070789SRoy Zang break; 4400aa070789SRoy Zang } 4401aa070789SRoy Zang 4402aa070789SRoy Zang return E1000_SUCCESS; 4403aa070789SRoy Zang } 4404aa070789SRoy Zang 4405aa070789SRoy Zang /****************************************************************************** 44062439e4bfSJean-Christophe PLAGNIOL-VILLARD * Returns the PHY to the power-on reset state 44072439e4bfSJean-Christophe PLAGNIOL-VILLARD * 44082439e4bfSJean-Christophe PLAGNIOL-VILLARD * hw - Struct containing variables accessed by shared code 44092439e4bfSJean-Christophe PLAGNIOL-VILLARD ******************************************************************************/ 4410aa070789SRoy Zang int32_t 44112439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_phy_hw_reset(struct e1000_hw *hw) 44122439e4bfSJean-Christophe PLAGNIOL-VILLARD { 4413987b43a1SKyle Moffett uint16_t swfw = E1000_SWFW_PHY0_SM; 4414aa070789SRoy Zang uint32_t ctrl, ctrl_ext; 4415aa070789SRoy Zang uint32_t led_ctrl; 4416aa070789SRoy Zang int32_t ret_val; 44172439e4bfSJean-Christophe PLAGNIOL-VILLARD 44182439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGFUNC(); 44192439e4bfSJean-Christophe PLAGNIOL-VILLARD 4420aa070789SRoy Zang /* In the case of the phy reset being blocked, it's not an error, we 4421aa070789SRoy Zang * simply return success without performing the reset. */ 4422aa070789SRoy Zang ret_val = e1000_check_phy_reset_block(hw); 4423aa070789SRoy Zang if (ret_val) 4424aa070789SRoy Zang return E1000_SUCCESS; 4425aa070789SRoy Zang 44262439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("Resetting Phy...\n"); 44272439e4bfSJean-Christophe PLAGNIOL-VILLARD 44282439e4bfSJean-Christophe PLAGNIOL-VILLARD if (hw->mac_type > e1000_82543) { 4429987b43a1SKyle Moffett if (e1000_is_second_port(hw)) 4430aa070789SRoy Zang swfw = E1000_SWFW_PHY1_SM; 4431987b43a1SKyle Moffett 4432aa070789SRoy Zang if (e1000_swfw_sync_acquire(hw, swfw)) { 4433aa070789SRoy Zang DEBUGOUT("Unable to acquire swfw sync\n"); 4434aa070789SRoy Zang return -E1000_ERR_SWFW_SYNC; 4435aa070789SRoy Zang } 4436987b43a1SKyle Moffett 44372439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Read the device control register and assert the E1000_CTRL_PHY_RST 44382439e4bfSJean-Christophe PLAGNIOL-VILLARD * bit. Then, take it out of reset. 44392439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 44402439e4bfSJean-Christophe PLAGNIOL-VILLARD ctrl = E1000_READ_REG(hw, CTRL); 44412439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST); 44422439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_FLUSH(hw); 4443aa070789SRoy Zang 4444aa070789SRoy Zang if (hw->mac_type < e1000_82571) 4445aa070789SRoy Zang udelay(10); 4446aa070789SRoy Zang else 4447aa070789SRoy Zang udelay(100); 4448aa070789SRoy Zang 44492439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, CTRL, ctrl); 44502439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_FLUSH(hw); 4451aa070789SRoy Zang 4452aa070789SRoy Zang if (hw->mac_type >= e1000_82571) 4453aa070789SRoy Zang mdelay(10); 44543c63dd53STim Harvey 44552439e4bfSJean-Christophe PLAGNIOL-VILLARD } else { 44562439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Read the Extended Device Control Register, assert the PHY_RESET_DIR 44572439e4bfSJean-Christophe PLAGNIOL-VILLARD * bit to put the PHY into reset. Then, take it out of reset. 44582439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 44592439e4bfSJean-Christophe PLAGNIOL-VILLARD ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 44602439e4bfSJean-Christophe PLAGNIOL-VILLARD ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR; 44612439e4bfSJean-Christophe PLAGNIOL-VILLARD ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA; 44622439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 44632439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_FLUSH(hw); 44642439e4bfSJean-Christophe PLAGNIOL-VILLARD mdelay(10); 44652439e4bfSJean-Christophe PLAGNIOL-VILLARD ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA; 44662439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 44672439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_FLUSH(hw); 44682439e4bfSJean-Christophe PLAGNIOL-VILLARD } 44692439e4bfSJean-Christophe PLAGNIOL-VILLARD udelay(150); 4470aa070789SRoy Zang 4471aa070789SRoy Zang if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { 4472aa070789SRoy Zang /* Configure activity LED after PHY reset */ 4473aa070789SRoy Zang led_ctrl = E1000_READ_REG(hw, LEDCTL); 4474aa070789SRoy Zang led_ctrl &= IGP_ACTIVITY_LED_MASK; 4475aa070789SRoy Zang led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); 4476aa070789SRoy Zang E1000_WRITE_REG(hw, LEDCTL, led_ctrl); 4477aa070789SRoy Zang } 4478aa070789SRoy Zang 44797e2d991dSTim Harvey e1000_swfw_sync_release(hw, swfw); 44807e2d991dSTim Harvey 4481aa070789SRoy Zang /* Wait for FW to finish PHY configuration. */ 4482aa070789SRoy Zang ret_val = e1000_get_phy_cfg_done(hw); 4483aa070789SRoy Zang if (ret_val != E1000_SUCCESS) 4484aa070789SRoy Zang return ret_val; 4485aa070789SRoy Zang 4486aa070789SRoy Zang return ret_val; 4487aa070789SRoy Zang } 4488aa070789SRoy Zang 4489aa070789SRoy Zang /****************************************************************************** 4490aa070789SRoy Zang * IGP phy init script - initializes the GbE PHY 4491aa070789SRoy Zang * 4492aa070789SRoy Zang * hw - Struct containing variables accessed by shared code 4493aa070789SRoy Zang *****************************************************************************/ 4494aa070789SRoy Zang static void 4495aa070789SRoy Zang e1000_phy_init_script(struct e1000_hw *hw) 4496aa070789SRoy Zang { 4497aa070789SRoy Zang uint32_t ret_val; 4498aa070789SRoy Zang uint16_t phy_saved_data; 4499aa070789SRoy Zang DEBUGFUNC(); 4500aa070789SRoy Zang 4501aa070789SRoy Zang if (hw->phy_init_script) { 4502aa070789SRoy Zang mdelay(20); 4503aa070789SRoy Zang 4504aa070789SRoy Zang /* Save off the current value of register 0x2F5B to be 4505aa070789SRoy Zang * restored at the end of this routine. */ 4506aa070789SRoy Zang ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data); 4507aa070789SRoy Zang 4508aa070789SRoy Zang /* Disabled the PHY transmitter */ 4509aa070789SRoy Zang e1000_write_phy_reg(hw, 0x2F5B, 0x0003); 4510aa070789SRoy Zang 4511aa070789SRoy Zang mdelay(20); 4512aa070789SRoy Zang 4513aa070789SRoy Zang e1000_write_phy_reg(hw, 0x0000, 0x0140); 4514aa070789SRoy Zang 4515aa070789SRoy Zang mdelay(5); 4516aa070789SRoy Zang 4517aa070789SRoy Zang switch (hw->mac_type) { 4518aa070789SRoy Zang case e1000_82541: 4519aa070789SRoy Zang case e1000_82547: 4520aa070789SRoy Zang e1000_write_phy_reg(hw, 0x1F95, 0x0001); 4521aa070789SRoy Zang 4522aa070789SRoy Zang e1000_write_phy_reg(hw, 0x1F71, 0xBD21); 4523aa070789SRoy Zang 4524aa070789SRoy Zang e1000_write_phy_reg(hw, 0x1F79, 0x0018); 4525aa070789SRoy Zang 4526aa070789SRoy Zang e1000_write_phy_reg(hw, 0x1F30, 0x1600); 4527aa070789SRoy Zang 4528aa070789SRoy Zang e1000_write_phy_reg(hw, 0x1F31, 0x0014); 4529aa070789SRoy Zang 4530aa070789SRoy Zang e1000_write_phy_reg(hw, 0x1F32, 0x161C); 4531aa070789SRoy Zang 4532aa070789SRoy Zang e1000_write_phy_reg(hw, 0x1F94, 0x0003); 4533aa070789SRoy Zang 4534aa070789SRoy Zang e1000_write_phy_reg(hw, 0x1F96, 0x003F); 4535aa070789SRoy Zang 4536aa070789SRoy Zang e1000_write_phy_reg(hw, 0x2010, 0x0008); 4537aa070789SRoy Zang break; 4538aa070789SRoy Zang 4539aa070789SRoy Zang case e1000_82541_rev_2: 4540aa070789SRoy Zang case e1000_82547_rev_2: 4541aa070789SRoy Zang e1000_write_phy_reg(hw, 0x1F73, 0x0099); 4542aa070789SRoy Zang break; 4543aa070789SRoy Zang default: 4544aa070789SRoy Zang break; 4545aa070789SRoy Zang } 4546aa070789SRoy Zang 4547aa070789SRoy Zang e1000_write_phy_reg(hw, 0x0000, 0x3300); 4548aa070789SRoy Zang 4549aa070789SRoy Zang mdelay(20); 4550aa070789SRoy Zang 4551aa070789SRoy Zang /* Now enable the transmitter */ 455256b13b1eSZang Roy-R61911 if (!ret_val) 4553aa070789SRoy Zang e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data); 4554aa070789SRoy Zang 4555aa070789SRoy Zang if (hw->mac_type == e1000_82547) { 4556aa070789SRoy Zang uint16_t fused, fine, coarse; 4557aa070789SRoy Zang 4558aa070789SRoy Zang /* Move to analog registers page */ 4559aa070789SRoy Zang e1000_read_phy_reg(hw, 4560aa070789SRoy Zang IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused); 4561aa070789SRoy Zang 4562aa070789SRoy Zang if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) { 4563aa070789SRoy Zang e1000_read_phy_reg(hw, 4564aa070789SRoy Zang IGP01E1000_ANALOG_FUSE_STATUS, &fused); 4565aa070789SRoy Zang 4566aa070789SRoy Zang fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK; 4567aa070789SRoy Zang coarse = fused 4568aa070789SRoy Zang & IGP01E1000_ANALOG_FUSE_COARSE_MASK; 4569aa070789SRoy Zang 4570aa070789SRoy Zang if (coarse > 4571aa070789SRoy Zang IGP01E1000_ANALOG_FUSE_COARSE_THRESH) { 4572aa070789SRoy Zang coarse -= 4573aa070789SRoy Zang IGP01E1000_ANALOG_FUSE_COARSE_10; 4574aa070789SRoy Zang fine -= IGP01E1000_ANALOG_FUSE_FINE_1; 4575aa070789SRoy Zang } else if (coarse 4576aa070789SRoy Zang == IGP01E1000_ANALOG_FUSE_COARSE_THRESH) 4577aa070789SRoy Zang fine -= IGP01E1000_ANALOG_FUSE_FINE_10; 4578aa070789SRoy Zang 4579aa070789SRoy Zang fused = (fused 4580aa070789SRoy Zang & IGP01E1000_ANALOG_FUSE_POLY_MASK) | 4581aa070789SRoy Zang (fine 4582aa070789SRoy Zang & IGP01E1000_ANALOG_FUSE_FINE_MASK) | 4583aa070789SRoy Zang (coarse 4584aa070789SRoy Zang & IGP01E1000_ANALOG_FUSE_COARSE_MASK); 4585aa070789SRoy Zang 4586aa070789SRoy Zang e1000_write_phy_reg(hw, 4587aa070789SRoy Zang IGP01E1000_ANALOG_FUSE_CONTROL, fused); 4588aa070789SRoy Zang e1000_write_phy_reg(hw, 4589aa070789SRoy Zang IGP01E1000_ANALOG_FUSE_BYPASS, 4590aa070789SRoy Zang IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL); 4591aa070789SRoy Zang } 4592aa070789SRoy Zang } 4593aa070789SRoy Zang } 45942439e4bfSJean-Christophe PLAGNIOL-VILLARD } 45952439e4bfSJean-Christophe PLAGNIOL-VILLARD 45962439e4bfSJean-Christophe PLAGNIOL-VILLARD /****************************************************************************** 45972439e4bfSJean-Christophe PLAGNIOL-VILLARD * Resets the PHY 45982439e4bfSJean-Christophe PLAGNIOL-VILLARD * 45992439e4bfSJean-Christophe PLAGNIOL-VILLARD * hw - Struct containing variables accessed by shared code 46002439e4bfSJean-Christophe PLAGNIOL-VILLARD * 4601aa070789SRoy Zang * Sets bit 15 of the MII Control register 46022439e4bfSJean-Christophe PLAGNIOL-VILLARD ******************************************************************************/ 4603aa070789SRoy Zang int32_t 46042439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_phy_reset(struct e1000_hw *hw) 46052439e4bfSJean-Christophe PLAGNIOL-VILLARD { 4606aa070789SRoy Zang int32_t ret_val; 46072439e4bfSJean-Christophe PLAGNIOL-VILLARD uint16_t phy_data; 46082439e4bfSJean-Christophe PLAGNIOL-VILLARD 46092439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGFUNC(); 46102439e4bfSJean-Christophe PLAGNIOL-VILLARD 4611aa070789SRoy Zang /* In the case of the phy reset being blocked, it's not an error, we 4612aa070789SRoy Zang * simply return success without performing the reset. */ 4613aa070789SRoy Zang ret_val = e1000_check_phy_reset_block(hw); 4614aa070789SRoy Zang if (ret_val) 4615aa070789SRoy Zang return E1000_SUCCESS; 4616aa070789SRoy Zang 4617aa070789SRoy Zang switch (hw->phy_type) { 4618aa070789SRoy Zang case e1000_phy_igp: 4619aa070789SRoy Zang case e1000_phy_igp_2: 4620aa070789SRoy Zang case e1000_phy_igp_3: 4621aa070789SRoy Zang case e1000_phy_ife: 462295186063SMarek Vasut case e1000_phy_igb: 4623aa070789SRoy Zang ret_val = e1000_phy_hw_reset(hw); 4624aa070789SRoy Zang if (ret_val) 4625aa070789SRoy Zang return ret_val; 4626aa070789SRoy Zang break; 4627aa070789SRoy Zang default: 4628aa070789SRoy Zang ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data); 4629aa070789SRoy Zang if (ret_val) 4630aa070789SRoy Zang return ret_val; 4631aa070789SRoy Zang 46322439e4bfSJean-Christophe PLAGNIOL-VILLARD phy_data |= MII_CR_RESET; 4633aa070789SRoy Zang ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data); 4634aa070789SRoy Zang if (ret_val) 4635aa070789SRoy Zang return ret_val; 4636aa070789SRoy Zang 46372439e4bfSJean-Christophe PLAGNIOL-VILLARD udelay(1); 4638aa070789SRoy Zang break; 4639aa070789SRoy Zang } 4640aa070789SRoy Zang 4641aa070789SRoy Zang if (hw->phy_type == e1000_phy_igp || hw->phy_type == e1000_phy_igp_2) 4642aa070789SRoy Zang e1000_phy_init_script(hw); 4643aa070789SRoy Zang 4644aa070789SRoy Zang return E1000_SUCCESS; 46452439e4bfSJean-Christophe PLAGNIOL-VILLARD } 46462439e4bfSJean-Christophe PLAGNIOL-VILLARD 46471aeed8d7SWolfgang Denk static int e1000_set_phy_type (struct e1000_hw *hw) 4648ac3315c2SAndre Schwarz { 4649ac3315c2SAndre Schwarz DEBUGFUNC (); 4650ac3315c2SAndre Schwarz 4651ac3315c2SAndre Schwarz if (hw->mac_type == e1000_undefined) 4652ac3315c2SAndre Schwarz return -E1000_ERR_PHY_TYPE; 4653ac3315c2SAndre Schwarz 4654ac3315c2SAndre Schwarz switch (hw->phy_id) { 4655ac3315c2SAndre Schwarz case M88E1000_E_PHY_ID: 4656ac3315c2SAndre Schwarz case M88E1000_I_PHY_ID: 4657ac3315c2SAndre Schwarz case M88E1011_I_PHY_ID: 4658aa070789SRoy Zang case M88E1111_I_PHY_ID: 4659ac3315c2SAndre Schwarz hw->phy_type = e1000_phy_m88; 4660ac3315c2SAndre Schwarz break; 4661ac3315c2SAndre Schwarz case IGP01E1000_I_PHY_ID: 4662ac3315c2SAndre Schwarz if (hw->mac_type == e1000_82541 || 4663aa070789SRoy Zang hw->mac_type == e1000_82541_rev_2 || 4664aa070789SRoy Zang hw->mac_type == e1000_82547 || 4665aa070789SRoy Zang hw->mac_type == e1000_82547_rev_2) { 4666ac3315c2SAndre Schwarz hw->phy_type = e1000_phy_igp; 4667aa070789SRoy Zang break; 4668aa070789SRoy Zang } 4669aa070789SRoy Zang case IGP03E1000_E_PHY_ID: 4670aa070789SRoy Zang hw->phy_type = e1000_phy_igp_3; 4671aa070789SRoy Zang break; 4672aa070789SRoy Zang case IFE_E_PHY_ID: 4673aa070789SRoy Zang case IFE_PLUS_E_PHY_ID: 4674aa070789SRoy Zang case IFE_C_E_PHY_ID: 4675aa070789SRoy Zang hw->phy_type = e1000_phy_ife; 4676aa070789SRoy Zang break; 4677aa070789SRoy Zang case GG82563_E_PHY_ID: 4678aa070789SRoy Zang if (hw->mac_type == e1000_80003es2lan) { 4679aa070789SRoy Zang hw->phy_type = e1000_phy_gg82563; 4680ac3315c2SAndre Schwarz break; 4681ac3315c2SAndre Schwarz } 46822c2668f9SRoy Zang case BME1000_E_PHY_ID: 46832c2668f9SRoy Zang hw->phy_type = e1000_phy_bm; 46842c2668f9SRoy Zang break; 468595186063SMarek Vasut case I210_I_PHY_ID: 468695186063SMarek Vasut hw->phy_type = e1000_phy_igb; 468795186063SMarek Vasut break; 4688ac3315c2SAndre Schwarz /* Fall Through */ 4689ac3315c2SAndre Schwarz default: 4690ac3315c2SAndre Schwarz /* Should never have loaded on this device */ 4691ac3315c2SAndre Schwarz hw->phy_type = e1000_phy_undefined; 4692ac3315c2SAndre Schwarz return -E1000_ERR_PHY_TYPE; 4693ac3315c2SAndre Schwarz } 4694ac3315c2SAndre Schwarz 4695ac3315c2SAndre Schwarz return E1000_SUCCESS; 4696ac3315c2SAndre Schwarz } 4697ac3315c2SAndre Schwarz 46982439e4bfSJean-Christophe PLAGNIOL-VILLARD /****************************************************************************** 46992439e4bfSJean-Christophe PLAGNIOL-VILLARD * Probes the expected PHY address for known PHY IDs 47002439e4bfSJean-Christophe PLAGNIOL-VILLARD * 47012439e4bfSJean-Christophe PLAGNIOL-VILLARD * hw - Struct containing variables accessed by shared code 47022439e4bfSJean-Christophe PLAGNIOL-VILLARD ******************************************************************************/ 4703aa070789SRoy Zang static int32_t 47042439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_detect_gig_phy(struct e1000_hw *hw) 47052439e4bfSJean-Christophe PLAGNIOL-VILLARD { 4706aa070789SRoy Zang int32_t phy_init_status, ret_val; 47072439e4bfSJean-Christophe PLAGNIOL-VILLARD uint16_t phy_id_high, phy_id_low; 4708472d5460SYork Sun bool match = false; 47092439e4bfSJean-Christophe PLAGNIOL-VILLARD 47102439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGFUNC(); 47112439e4bfSJean-Christophe PLAGNIOL-VILLARD 4712aa070789SRoy Zang /* The 82571 firmware may still be configuring the PHY. In this 4713aa070789SRoy Zang * case, we cannot access the PHY until the configuration is done. So 4714aa070789SRoy Zang * we explicitly set the PHY values. */ 4715aa070789SRoy Zang if (hw->mac_type == e1000_82571 || 4716aa070789SRoy Zang hw->mac_type == e1000_82572) { 4717aa070789SRoy Zang hw->phy_id = IGP01E1000_I_PHY_ID; 4718aa070789SRoy Zang hw->phy_type = e1000_phy_igp_2; 4719aa070789SRoy Zang return E1000_SUCCESS; 4720aa070789SRoy Zang } 4721aa070789SRoy Zang 4722aa070789SRoy Zang /* ESB-2 PHY reads require e1000_phy_gg82563 to be set because of a 4723aa070789SRoy Zang * work- around that forces PHY page 0 to be set or the reads fail. 4724aa070789SRoy Zang * The rest of the code in this routine uses e1000_read_phy_reg to 4725aa070789SRoy Zang * read the PHY ID. So for ESB-2 we need to have this set so our 4726aa070789SRoy Zang * reads won't fail. If the attached PHY is not a e1000_phy_gg82563, 4727aa070789SRoy Zang * the routines below will figure this out as well. */ 4728aa070789SRoy Zang if (hw->mac_type == e1000_80003es2lan) 4729aa070789SRoy Zang hw->phy_type = e1000_phy_gg82563; 4730aa070789SRoy Zang 47312439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Read the PHY ID Registers to identify which PHY is onboard. */ 4732aa070789SRoy Zang ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high); 4733aa070789SRoy Zang if (ret_val) 4734aa070789SRoy Zang return ret_val; 4735aa070789SRoy Zang 47362439e4bfSJean-Christophe PLAGNIOL-VILLARD hw->phy_id = (uint32_t) (phy_id_high << 16); 4737aa070789SRoy Zang udelay(20); 4738aa070789SRoy Zang ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low); 4739aa070789SRoy Zang if (ret_val) 4740aa070789SRoy Zang return ret_val; 4741aa070789SRoy Zang 47422439e4bfSJean-Christophe PLAGNIOL-VILLARD hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK); 4743aa070789SRoy Zang hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK; 47442439e4bfSJean-Christophe PLAGNIOL-VILLARD 47452439e4bfSJean-Christophe PLAGNIOL-VILLARD switch (hw->mac_type) { 47462439e4bfSJean-Christophe PLAGNIOL-VILLARD case e1000_82543: 47472439e4bfSJean-Christophe PLAGNIOL-VILLARD if (hw->phy_id == M88E1000_E_PHY_ID) 4748472d5460SYork Sun match = true; 47492439e4bfSJean-Christophe PLAGNIOL-VILLARD break; 47502439e4bfSJean-Christophe PLAGNIOL-VILLARD case e1000_82544: 47512439e4bfSJean-Christophe PLAGNIOL-VILLARD if (hw->phy_id == M88E1000_I_PHY_ID) 4752472d5460SYork Sun match = true; 47532439e4bfSJean-Christophe PLAGNIOL-VILLARD break; 47542439e4bfSJean-Christophe PLAGNIOL-VILLARD case e1000_82540: 47552439e4bfSJean-Christophe PLAGNIOL-VILLARD case e1000_82545: 4756aa070789SRoy Zang case e1000_82545_rev_3: 47572439e4bfSJean-Christophe PLAGNIOL-VILLARD case e1000_82546: 4758aa070789SRoy Zang case e1000_82546_rev_3: 47592439e4bfSJean-Christophe PLAGNIOL-VILLARD if (hw->phy_id == M88E1011_I_PHY_ID) 4760472d5460SYork Sun match = true; 47612439e4bfSJean-Christophe PLAGNIOL-VILLARD break; 4762aa070789SRoy Zang case e1000_82541: 4763ac3315c2SAndre Schwarz case e1000_82541_rev_2: 4764aa070789SRoy Zang case e1000_82547: 4765aa070789SRoy Zang case e1000_82547_rev_2: 4766ac3315c2SAndre Schwarz if(hw->phy_id == IGP01E1000_I_PHY_ID) 4767472d5460SYork Sun match = true; 4768ac3315c2SAndre Schwarz 4769ac3315c2SAndre Schwarz break; 4770aa070789SRoy Zang case e1000_82573: 4771aa070789SRoy Zang if (hw->phy_id == M88E1111_I_PHY_ID) 4772472d5460SYork Sun match = true; 4773aa070789SRoy Zang break; 47742c2668f9SRoy Zang case e1000_82574: 47752c2668f9SRoy Zang if (hw->phy_id == BME1000_E_PHY_ID) 4776472d5460SYork Sun match = true; 47772c2668f9SRoy Zang break; 4778aa070789SRoy Zang case e1000_80003es2lan: 4779aa070789SRoy Zang if (hw->phy_id == GG82563_E_PHY_ID) 4780472d5460SYork Sun match = true; 4781aa070789SRoy Zang break; 4782aa070789SRoy Zang case e1000_ich8lan: 4783aa070789SRoy Zang if (hw->phy_id == IGP03E1000_E_PHY_ID) 4784472d5460SYork Sun match = true; 4785aa070789SRoy Zang if (hw->phy_id == IFE_E_PHY_ID) 4786472d5460SYork Sun match = true; 4787aa070789SRoy Zang if (hw->phy_id == IFE_PLUS_E_PHY_ID) 4788472d5460SYork Sun match = true; 4789aa070789SRoy Zang if (hw->phy_id == IFE_C_E_PHY_ID) 4790472d5460SYork Sun match = true; 4791aa070789SRoy Zang break; 479295186063SMarek Vasut case e1000_igb: 479395186063SMarek Vasut if (hw->phy_id == I210_I_PHY_ID) 479495186063SMarek Vasut match = true; 479595186063SMarek Vasut break; 47962439e4bfSJean-Christophe PLAGNIOL-VILLARD default: 47972439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("Invalid MAC type %d\n", hw->mac_type); 47982439e4bfSJean-Christophe PLAGNIOL-VILLARD return -E1000_ERR_CONFIG; 47992439e4bfSJean-Christophe PLAGNIOL-VILLARD } 4800ac3315c2SAndre Schwarz 4801ac3315c2SAndre Schwarz phy_init_status = e1000_set_phy_type(hw); 4802ac3315c2SAndre Schwarz 4803ac3315c2SAndre Schwarz if ((match) && (phy_init_status == E1000_SUCCESS)) { 48042439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("PHY ID 0x%X detected\n", hw->phy_id); 48052439e4bfSJean-Christophe PLAGNIOL-VILLARD return 0; 48062439e4bfSJean-Christophe PLAGNIOL-VILLARD } 48072439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("Invalid PHY ID 0x%X\n", hw->phy_id); 48082439e4bfSJean-Christophe PLAGNIOL-VILLARD return -E1000_ERR_PHY; 48092439e4bfSJean-Christophe PLAGNIOL-VILLARD } 48102439e4bfSJean-Christophe PLAGNIOL-VILLARD 4811aa070789SRoy Zang /***************************************************************************** 4812aa070789SRoy Zang * Set media type and TBI compatibility. 4813aa070789SRoy Zang * 4814aa070789SRoy Zang * hw - Struct containing variables accessed by shared code 4815aa070789SRoy Zang * **************************************************************************/ 4816aa070789SRoy Zang void 4817aa070789SRoy Zang e1000_set_media_type(struct e1000_hw *hw) 4818aa070789SRoy Zang { 4819aa070789SRoy Zang uint32_t status; 4820aa070789SRoy Zang 4821aa070789SRoy Zang DEBUGFUNC(); 4822aa070789SRoy Zang 4823aa070789SRoy Zang if (hw->mac_type != e1000_82543) { 4824aa070789SRoy Zang /* tbi_compatibility is only valid on 82543 */ 4825472d5460SYork Sun hw->tbi_compatibility_en = false; 4826aa070789SRoy Zang } 4827aa070789SRoy Zang 4828aa070789SRoy Zang switch (hw->device_id) { 4829aa070789SRoy Zang case E1000_DEV_ID_82545GM_SERDES: 4830aa070789SRoy Zang case E1000_DEV_ID_82546GB_SERDES: 4831aa070789SRoy Zang case E1000_DEV_ID_82571EB_SERDES: 4832aa070789SRoy Zang case E1000_DEV_ID_82571EB_SERDES_DUAL: 4833aa070789SRoy Zang case E1000_DEV_ID_82571EB_SERDES_QUAD: 4834aa070789SRoy Zang case E1000_DEV_ID_82572EI_SERDES: 4835aa070789SRoy Zang case E1000_DEV_ID_80003ES2LAN_SERDES_DPT: 4836aa070789SRoy Zang hw->media_type = e1000_media_type_internal_serdes; 4837aa070789SRoy Zang break; 4838aa070789SRoy Zang default: 4839aa070789SRoy Zang switch (hw->mac_type) { 4840aa070789SRoy Zang case e1000_82542_rev2_0: 4841aa070789SRoy Zang case e1000_82542_rev2_1: 4842aa070789SRoy Zang hw->media_type = e1000_media_type_fiber; 4843aa070789SRoy Zang break; 4844aa070789SRoy Zang case e1000_ich8lan: 4845aa070789SRoy Zang case e1000_82573: 48462c2668f9SRoy Zang case e1000_82574: 484795186063SMarek Vasut case e1000_igb: 4848aa070789SRoy Zang /* The STATUS_TBIMODE bit is reserved or reused 4849aa070789SRoy Zang * for the this device. 4850aa070789SRoy Zang */ 4851aa070789SRoy Zang hw->media_type = e1000_media_type_copper; 4852aa070789SRoy Zang break; 4853aa070789SRoy Zang default: 4854aa070789SRoy Zang status = E1000_READ_REG(hw, STATUS); 4855aa070789SRoy Zang if (status & E1000_STATUS_TBIMODE) { 4856aa070789SRoy Zang hw->media_type = e1000_media_type_fiber; 4857aa070789SRoy Zang /* tbi_compatibility not valid on fiber */ 4858472d5460SYork Sun hw->tbi_compatibility_en = false; 4859aa070789SRoy Zang } else { 4860aa070789SRoy Zang hw->media_type = e1000_media_type_copper; 4861aa070789SRoy Zang } 4862aa070789SRoy Zang break; 4863aa070789SRoy Zang } 4864aa070789SRoy Zang } 4865aa070789SRoy Zang } 4866aa070789SRoy Zang 48672439e4bfSJean-Christophe PLAGNIOL-VILLARD /** 48682439e4bfSJean-Christophe PLAGNIOL-VILLARD * e1000_sw_init - Initialize general software structures (struct e1000_adapter) 48692439e4bfSJean-Christophe PLAGNIOL-VILLARD * 48702439e4bfSJean-Christophe PLAGNIOL-VILLARD * e1000_sw_init initializes the Adapter private data structure. 48712439e4bfSJean-Christophe PLAGNIOL-VILLARD * Fields are initialized based on PCI device information and 48722439e4bfSJean-Christophe PLAGNIOL-VILLARD * OS network device settings (MTU size). 48732439e4bfSJean-Christophe PLAGNIOL-VILLARD **/ 48742439e4bfSJean-Christophe PLAGNIOL-VILLARD 48752439e4bfSJean-Christophe PLAGNIOL-VILLARD static int 48765c5e707aSSimon Glass e1000_sw_init(struct e1000_hw *hw) 48772439e4bfSJean-Christophe PLAGNIOL-VILLARD { 48782439e4bfSJean-Christophe PLAGNIOL-VILLARD int result; 48792439e4bfSJean-Christophe PLAGNIOL-VILLARD 48802439e4bfSJean-Christophe PLAGNIOL-VILLARD /* PCI config space info */ 48812439e4bfSJean-Christophe PLAGNIOL-VILLARD pci_read_config_word(hw->pdev, PCI_VENDOR_ID, &hw->vendor_id); 48822439e4bfSJean-Christophe PLAGNIOL-VILLARD pci_read_config_word(hw->pdev, PCI_DEVICE_ID, &hw->device_id); 48832439e4bfSJean-Christophe PLAGNIOL-VILLARD pci_read_config_word(hw->pdev, PCI_SUBSYSTEM_VENDOR_ID, 48842439e4bfSJean-Christophe PLAGNIOL-VILLARD &hw->subsystem_vendor_id); 48852439e4bfSJean-Christophe PLAGNIOL-VILLARD pci_read_config_word(hw->pdev, PCI_SUBSYSTEM_ID, &hw->subsystem_id); 48862439e4bfSJean-Christophe PLAGNIOL-VILLARD 48872439e4bfSJean-Christophe PLAGNIOL-VILLARD pci_read_config_byte(hw->pdev, PCI_REVISION_ID, &hw->revision_id); 48882439e4bfSJean-Christophe PLAGNIOL-VILLARD pci_read_config_word(hw->pdev, PCI_COMMAND, &hw->pci_cmd_word); 48892439e4bfSJean-Christophe PLAGNIOL-VILLARD 48902439e4bfSJean-Christophe PLAGNIOL-VILLARD /* identify the MAC */ 48912439e4bfSJean-Christophe PLAGNIOL-VILLARD result = e1000_set_mac_type(hw); 48922439e4bfSJean-Christophe PLAGNIOL-VILLARD if (result) { 48935c5e707aSSimon Glass E1000_ERR(hw, "Unknown MAC Type\n"); 48942439e4bfSJean-Christophe PLAGNIOL-VILLARD return result; 48952439e4bfSJean-Christophe PLAGNIOL-VILLARD } 48962439e4bfSJean-Christophe PLAGNIOL-VILLARD 4897aa070789SRoy Zang switch (hw->mac_type) { 4898aa070789SRoy Zang default: 4899aa070789SRoy Zang break; 4900aa070789SRoy Zang case e1000_82541: 4901aa070789SRoy Zang case e1000_82547: 4902aa070789SRoy Zang case e1000_82541_rev_2: 4903aa070789SRoy Zang case e1000_82547_rev_2: 4904aa070789SRoy Zang hw->phy_init_script = 1; 4905aa070789SRoy Zang break; 4906aa070789SRoy Zang } 4907aa070789SRoy Zang 49082439e4bfSJean-Christophe PLAGNIOL-VILLARD /* flow control settings */ 49092439e4bfSJean-Christophe PLAGNIOL-VILLARD hw->fc_high_water = E1000_FC_HIGH_THRESH; 49102439e4bfSJean-Christophe PLAGNIOL-VILLARD hw->fc_low_water = E1000_FC_LOW_THRESH; 49112439e4bfSJean-Christophe PLAGNIOL-VILLARD hw->fc_pause_time = E1000_FC_PAUSE_TIME; 49122439e4bfSJean-Christophe PLAGNIOL-VILLARD hw->fc_send_xon = 1; 49132439e4bfSJean-Christophe PLAGNIOL-VILLARD 49142439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Media type - copper or fiber */ 491595186063SMarek Vasut hw->tbi_compatibility_en = true; 4916aa070789SRoy Zang e1000_set_media_type(hw); 49172439e4bfSJean-Christophe PLAGNIOL-VILLARD 49182439e4bfSJean-Christophe PLAGNIOL-VILLARD if (hw->mac_type >= e1000_82543) { 49192439e4bfSJean-Christophe PLAGNIOL-VILLARD uint32_t status = E1000_READ_REG(hw, STATUS); 49202439e4bfSJean-Christophe PLAGNIOL-VILLARD 49212439e4bfSJean-Christophe PLAGNIOL-VILLARD if (status & E1000_STATUS_TBIMODE) { 49222439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("fiber interface\n"); 49232439e4bfSJean-Christophe PLAGNIOL-VILLARD hw->media_type = e1000_media_type_fiber; 49242439e4bfSJean-Christophe PLAGNIOL-VILLARD } else { 49252439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("copper interface\n"); 49262439e4bfSJean-Christophe PLAGNIOL-VILLARD hw->media_type = e1000_media_type_copper; 49272439e4bfSJean-Christophe PLAGNIOL-VILLARD } 49282439e4bfSJean-Christophe PLAGNIOL-VILLARD } else { 49292439e4bfSJean-Christophe PLAGNIOL-VILLARD hw->media_type = e1000_media_type_fiber; 49302439e4bfSJean-Christophe PLAGNIOL-VILLARD } 49312439e4bfSJean-Christophe PLAGNIOL-VILLARD 4932472d5460SYork Sun hw->wait_autoneg_complete = true; 49332439e4bfSJean-Christophe PLAGNIOL-VILLARD if (hw->mac_type < e1000_82543) 49342439e4bfSJean-Christophe PLAGNIOL-VILLARD hw->report_tx_early = 0; 49352439e4bfSJean-Christophe PLAGNIOL-VILLARD else 49362439e4bfSJean-Christophe PLAGNIOL-VILLARD hw->report_tx_early = 1; 49372439e4bfSJean-Christophe PLAGNIOL-VILLARD 49382439e4bfSJean-Christophe PLAGNIOL-VILLARD return E1000_SUCCESS; 49392439e4bfSJean-Christophe PLAGNIOL-VILLARD } 49402439e4bfSJean-Christophe PLAGNIOL-VILLARD 49412439e4bfSJean-Christophe PLAGNIOL-VILLARD void 49422439e4bfSJean-Christophe PLAGNIOL-VILLARD fill_rx(struct e1000_hw *hw) 49432439e4bfSJean-Christophe PLAGNIOL-VILLARD { 49442439e4bfSJean-Christophe PLAGNIOL-VILLARD struct e1000_rx_desc *rd; 494506e07f65SMinghuan Lian unsigned long flush_start, flush_end; 49462439e4bfSJean-Christophe PLAGNIOL-VILLARD 49472439e4bfSJean-Christophe PLAGNIOL-VILLARD rx_last = rx_tail; 49482439e4bfSJean-Christophe PLAGNIOL-VILLARD rd = rx_base + rx_tail; 49492439e4bfSJean-Christophe PLAGNIOL-VILLARD rx_tail = (rx_tail + 1) % 8; 49502439e4bfSJean-Christophe PLAGNIOL-VILLARD memset(rd, 0, 16); 495106e07f65SMinghuan Lian rd->buffer_addr = cpu_to_le64((unsigned long)packet); 4952873e8e01SMarek Vasut 4953873e8e01SMarek Vasut /* 4954873e8e01SMarek Vasut * Make sure there are no stale data in WB over this area, which 4955873e8e01SMarek Vasut * might get written into the memory while the e1000 also writes 4956873e8e01SMarek Vasut * into the same memory area. 4957873e8e01SMarek Vasut */ 495806e07f65SMinghuan Lian invalidate_dcache_range((unsigned long)packet, 495906e07f65SMinghuan Lian (unsigned long)packet + 4096); 4960873e8e01SMarek Vasut /* Dump the DMA descriptor into RAM. */ 496106e07f65SMinghuan Lian flush_start = ((unsigned long)rd) & ~(ARCH_DMA_MINALIGN - 1); 4962873e8e01SMarek Vasut flush_end = flush_start + roundup(sizeof(*rd), ARCH_DMA_MINALIGN); 4963873e8e01SMarek Vasut flush_dcache_range(flush_start, flush_end); 4964873e8e01SMarek Vasut 49652439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, RDT, rx_tail); 49662439e4bfSJean-Christophe PLAGNIOL-VILLARD } 49672439e4bfSJean-Christophe PLAGNIOL-VILLARD 49682439e4bfSJean-Christophe PLAGNIOL-VILLARD /** 49692439e4bfSJean-Christophe PLAGNIOL-VILLARD * e1000_configure_tx - Configure 8254x Transmit Unit after Reset 49702439e4bfSJean-Christophe PLAGNIOL-VILLARD * @adapter: board private structure 49712439e4bfSJean-Christophe PLAGNIOL-VILLARD * 49722439e4bfSJean-Christophe PLAGNIOL-VILLARD * Configure the Tx unit of the MAC after a reset. 49732439e4bfSJean-Christophe PLAGNIOL-VILLARD **/ 49742439e4bfSJean-Christophe PLAGNIOL-VILLARD 49752439e4bfSJean-Christophe PLAGNIOL-VILLARD static void 49762439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_configure_tx(struct e1000_hw *hw) 49772439e4bfSJean-Christophe PLAGNIOL-VILLARD { 49782439e4bfSJean-Christophe PLAGNIOL-VILLARD unsigned long tctl; 4979aa070789SRoy Zang unsigned long tipg, tarc; 4980aa070789SRoy Zang uint32_t ipgr1, ipgr2; 49812439e4bfSJean-Christophe PLAGNIOL-VILLARD 49821d8a078bSBin Meng E1000_WRITE_REG(hw, TDBAL, lower_32_bits((unsigned long)tx_base)); 49831d8a078bSBin Meng E1000_WRITE_REG(hw, TDBAH, upper_32_bits((unsigned long)tx_base)); 49842439e4bfSJean-Christophe PLAGNIOL-VILLARD 49852439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, TDLEN, 128); 49862439e4bfSJean-Christophe PLAGNIOL-VILLARD 49872439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Setup the HW Tx Head and Tail descriptor pointers */ 49882439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, TDH, 0); 49892439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, TDT, 0); 49902439e4bfSJean-Christophe PLAGNIOL-VILLARD tx_tail = 0; 49912439e4bfSJean-Christophe PLAGNIOL-VILLARD 49922439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Set the default values for the Tx Inter Packet Gap timer */ 4993aa070789SRoy Zang if (hw->mac_type <= e1000_82547_rev_2 && 4994aa070789SRoy Zang (hw->media_type == e1000_media_type_fiber || 4995aa070789SRoy Zang hw->media_type == e1000_media_type_internal_serdes)) 4996aa070789SRoy Zang tipg = DEFAULT_82543_TIPG_IPGT_FIBER; 4997aa070789SRoy Zang else 4998aa070789SRoy Zang tipg = DEFAULT_82543_TIPG_IPGT_COPPER; 4999aa070789SRoy Zang 5000aa070789SRoy Zang /* Set the default values for the Tx Inter Packet Gap timer */ 50012439e4bfSJean-Christophe PLAGNIOL-VILLARD switch (hw->mac_type) { 50022439e4bfSJean-Christophe PLAGNIOL-VILLARD case e1000_82542_rev2_0: 50032439e4bfSJean-Christophe PLAGNIOL-VILLARD case e1000_82542_rev2_1: 50042439e4bfSJean-Christophe PLAGNIOL-VILLARD tipg = DEFAULT_82542_TIPG_IPGT; 5005aa070789SRoy Zang ipgr1 = DEFAULT_82542_TIPG_IPGR1; 5006aa070789SRoy Zang ipgr2 = DEFAULT_82542_TIPG_IPGR2; 5007aa070789SRoy Zang break; 5008aa070789SRoy Zang case e1000_80003es2lan: 5009aa070789SRoy Zang ipgr1 = DEFAULT_82543_TIPG_IPGR1; 5010aa070789SRoy Zang ipgr2 = DEFAULT_80003ES2LAN_TIPG_IPGR2; 50112439e4bfSJean-Christophe PLAGNIOL-VILLARD break; 50122439e4bfSJean-Christophe PLAGNIOL-VILLARD default: 5013aa070789SRoy Zang ipgr1 = DEFAULT_82543_TIPG_IPGR1; 5014aa070789SRoy Zang ipgr2 = DEFAULT_82543_TIPG_IPGR2; 5015aa070789SRoy Zang break; 50162439e4bfSJean-Christophe PLAGNIOL-VILLARD } 5017aa070789SRoy Zang tipg |= ipgr1 << E1000_TIPG_IPGR1_SHIFT; 5018aa070789SRoy Zang tipg |= ipgr2 << E1000_TIPG_IPGR2_SHIFT; 50192439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, TIPG, tipg); 50202439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Program the Transmit Control Register */ 50212439e4bfSJean-Christophe PLAGNIOL-VILLARD tctl = E1000_READ_REG(hw, TCTL); 50222439e4bfSJean-Christophe PLAGNIOL-VILLARD tctl &= ~E1000_TCTL_CT; 50232439e4bfSJean-Christophe PLAGNIOL-VILLARD tctl |= E1000_TCTL_EN | E1000_TCTL_PSP | 50242439e4bfSJean-Christophe PLAGNIOL-VILLARD (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); 5025aa070789SRoy Zang 5026aa070789SRoy Zang if (hw->mac_type == e1000_82571 || hw->mac_type == e1000_82572) { 5027aa070789SRoy Zang tarc = E1000_READ_REG(hw, TARC0); 5028aa070789SRoy Zang /* set the speed mode bit, we'll clear it if we're not at 5029aa070789SRoy Zang * gigabit link later */ 5030aa070789SRoy Zang /* git bit can be set to 1*/ 5031aa070789SRoy Zang } else if (hw->mac_type == e1000_80003es2lan) { 5032aa070789SRoy Zang tarc = E1000_READ_REG(hw, TARC0); 5033aa070789SRoy Zang tarc |= 1; 5034aa070789SRoy Zang E1000_WRITE_REG(hw, TARC0, tarc); 5035aa070789SRoy Zang tarc = E1000_READ_REG(hw, TARC1); 5036aa070789SRoy Zang tarc |= 1; 5037aa070789SRoy Zang E1000_WRITE_REG(hw, TARC1, tarc); 5038aa070789SRoy Zang } 5039aa070789SRoy Zang 50402439e4bfSJean-Christophe PLAGNIOL-VILLARD 50412439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_config_collision_dist(hw); 5042aa070789SRoy Zang /* Setup Transmit Descriptor Settings for eop descriptor */ 5043aa070789SRoy Zang hw->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS; 50442439e4bfSJean-Christophe PLAGNIOL-VILLARD 5045aa070789SRoy Zang /* Need to set up RS bit */ 5046aa070789SRoy Zang if (hw->mac_type < e1000_82543) 5047aa070789SRoy Zang hw->txd_cmd |= E1000_TXD_CMD_RPS; 50482439e4bfSJean-Christophe PLAGNIOL-VILLARD else 5049aa070789SRoy Zang hw->txd_cmd |= E1000_TXD_CMD_RS; 505095186063SMarek Vasut 505195186063SMarek Vasut 505295186063SMarek Vasut if (hw->mac_type == e1000_igb) { 505395186063SMarek Vasut E1000_WRITE_REG(hw, TCTL_EXT, 0x42 << 10); 505495186063SMarek Vasut 505595186063SMarek Vasut uint32_t reg_txdctl = E1000_READ_REG(hw, TXDCTL); 505695186063SMarek Vasut reg_txdctl |= 1 << 25; 505795186063SMarek Vasut E1000_WRITE_REG(hw, TXDCTL, reg_txdctl); 505895186063SMarek Vasut mdelay(20); 505995186063SMarek Vasut } 506095186063SMarek Vasut 506195186063SMarek Vasut 506295186063SMarek Vasut 5063aa070789SRoy Zang E1000_WRITE_REG(hw, TCTL, tctl); 506495186063SMarek Vasut 506595186063SMarek Vasut 50662439e4bfSJean-Christophe PLAGNIOL-VILLARD } 50672439e4bfSJean-Christophe PLAGNIOL-VILLARD 50682439e4bfSJean-Christophe PLAGNIOL-VILLARD /** 50692439e4bfSJean-Christophe PLAGNIOL-VILLARD * e1000_setup_rctl - configure the receive control register 50702439e4bfSJean-Christophe PLAGNIOL-VILLARD * @adapter: Board private structure 50712439e4bfSJean-Christophe PLAGNIOL-VILLARD **/ 50722439e4bfSJean-Christophe PLAGNIOL-VILLARD static void 50732439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_setup_rctl(struct e1000_hw *hw) 50742439e4bfSJean-Christophe PLAGNIOL-VILLARD { 50752439e4bfSJean-Christophe PLAGNIOL-VILLARD uint32_t rctl; 50762439e4bfSJean-Christophe PLAGNIOL-VILLARD 50772439e4bfSJean-Christophe PLAGNIOL-VILLARD rctl = E1000_READ_REG(hw, RCTL); 50782439e4bfSJean-Christophe PLAGNIOL-VILLARD 50792439e4bfSJean-Christophe PLAGNIOL-VILLARD rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 50802439e4bfSJean-Christophe PLAGNIOL-VILLARD 5081aa070789SRoy Zang rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO 5082aa070789SRoy Zang | E1000_RCTL_RDMTS_HALF; /* | 50832439e4bfSJean-Christophe PLAGNIOL-VILLARD (hw.mc_filter_type << E1000_RCTL_MO_SHIFT); */ 50842439e4bfSJean-Christophe PLAGNIOL-VILLARD 50852439e4bfSJean-Christophe PLAGNIOL-VILLARD if (hw->tbi_compatibility_on == 1) 50862439e4bfSJean-Christophe PLAGNIOL-VILLARD rctl |= E1000_RCTL_SBP; 50872439e4bfSJean-Christophe PLAGNIOL-VILLARD else 50882439e4bfSJean-Christophe PLAGNIOL-VILLARD rctl &= ~E1000_RCTL_SBP; 50892439e4bfSJean-Christophe PLAGNIOL-VILLARD 50902439e4bfSJean-Christophe PLAGNIOL-VILLARD rctl &= ~(E1000_RCTL_SZ_4096); 50912439e4bfSJean-Christophe PLAGNIOL-VILLARD rctl |= E1000_RCTL_SZ_2048; 50922439e4bfSJean-Christophe PLAGNIOL-VILLARD rctl &= ~(E1000_RCTL_BSEX | E1000_RCTL_LPE); 50932439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, RCTL, rctl); 50942439e4bfSJean-Christophe PLAGNIOL-VILLARD } 50952439e4bfSJean-Christophe PLAGNIOL-VILLARD 50962439e4bfSJean-Christophe PLAGNIOL-VILLARD /** 50972439e4bfSJean-Christophe PLAGNIOL-VILLARD * e1000_configure_rx - Configure 8254x Receive Unit after Reset 50982439e4bfSJean-Christophe PLAGNIOL-VILLARD * @adapter: board private structure 50992439e4bfSJean-Christophe PLAGNIOL-VILLARD * 51002439e4bfSJean-Christophe PLAGNIOL-VILLARD * Configure the Rx unit of the MAC after a reset. 51012439e4bfSJean-Christophe PLAGNIOL-VILLARD **/ 51022439e4bfSJean-Christophe PLAGNIOL-VILLARD static void 51032439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_configure_rx(struct e1000_hw *hw) 51042439e4bfSJean-Christophe PLAGNIOL-VILLARD { 5105aa070789SRoy Zang unsigned long rctl, ctrl_ext; 51062439e4bfSJean-Christophe PLAGNIOL-VILLARD rx_tail = 0; 51071d8a078bSBin Meng 51082439e4bfSJean-Christophe PLAGNIOL-VILLARD /* make sure receives are disabled while setting up the descriptors */ 51092439e4bfSJean-Christophe PLAGNIOL-VILLARD rctl = E1000_READ_REG(hw, RCTL); 51102439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, RCTL, rctl & ~E1000_RCTL_EN); 51112439e4bfSJean-Christophe PLAGNIOL-VILLARD if (hw->mac_type >= e1000_82540) { 51122439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Set the interrupt throttling rate. Value is calculated 51132439e4bfSJean-Christophe PLAGNIOL-VILLARD * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns) */ 51142439e4bfSJean-Christophe PLAGNIOL-VILLARD #define MAX_INTS_PER_SEC 8000 51152439e4bfSJean-Christophe PLAGNIOL-VILLARD #define DEFAULT_ITR 1000000000/(MAX_INTS_PER_SEC * 256) 51162439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, ITR, DEFAULT_ITR); 51172439e4bfSJean-Christophe PLAGNIOL-VILLARD } 51182439e4bfSJean-Christophe PLAGNIOL-VILLARD 5119aa070789SRoy Zang if (hw->mac_type >= e1000_82571) { 5120aa070789SRoy Zang ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 5121aa070789SRoy Zang /* Reset delay timers after every interrupt */ 5122aa070789SRoy Zang ctrl_ext |= E1000_CTRL_EXT_INT_TIMER_CLR; 5123aa070789SRoy Zang E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 5124aa070789SRoy Zang E1000_WRITE_FLUSH(hw); 5125aa070789SRoy Zang } 51262439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Setup the Base and Length of the Rx Descriptor Ring */ 51271d8a078bSBin Meng E1000_WRITE_REG(hw, RDBAL, lower_32_bits((unsigned long)rx_base)); 51281d8a078bSBin Meng E1000_WRITE_REG(hw, RDBAH, upper_32_bits((unsigned long)rx_base)); 51292439e4bfSJean-Christophe PLAGNIOL-VILLARD 51302439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, RDLEN, 128); 51312439e4bfSJean-Christophe PLAGNIOL-VILLARD 51322439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Setup the HW Rx Head and Tail Descriptor Pointers */ 51332439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, RDH, 0); 51342439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, RDT, 0); 51352439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Enable Receives */ 51362439e4bfSJean-Christophe PLAGNIOL-VILLARD 513795186063SMarek Vasut if (hw->mac_type == e1000_igb) { 513895186063SMarek Vasut 513995186063SMarek Vasut uint32_t reg_rxdctl = E1000_READ_REG(hw, RXDCTL); 514095186063SMarek Vasut reg_rxdctl |= 1 << 25; 514195186063SMarek Vasut E1000_WRITE_REG(hw, RXDCTL, reg_rxdctl); 514295186063SMarek Vasut mdelay(20); 514395186063SMarek Vasut } 514495186063SMarek Vasut 51452439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, RCTL, rctl); 514695186063SMarek Vasut 51472439e4bfSJean-Christophe PLAGNIOL-VILLARD fill_rx(hw); 51482439e4bfSJean-Christophe PLAGNIOL-VILLARD } 51492439e4bfSJean-Christophe PLAGNIOL-VILLARD 51502439e4bfSJean-Christophe PLAGNIOL-VILLARD /************************************************************************** 51512439e4bfSJean-Christophe PLAGNIOL-VILLARD POLL - Wait for a frame 51522439e4bfSJean-Christophe PLAGNIOL-VILLARD ***************************************************************************/ 51532439e4bfSJean-Christophe PLAGNIOL-VILLARD static int 51545c5e707aSSimon Glass _e1000_poll(struct e1000_hw *hw) 51552439e4bfSJean-Christophe PLAGNIOL-VILLARD { 51562439e4bfSJean-Christophe PLAGNIOL-VILLARD struct e1000_rx_desc *rd; 515706e07f65SMinghuan Lian unsigned long inval_start, inval_end; 5158873e8e01SMarek Vasut uint32_t len; 5159873e8e01SMarek Vasut 51602439e4bfSJean-Christophe PLAGNIOL-VILLARD /* return true if there's an ethernet packet ready to read */ 51612439e4bfSJean-Christophe PLAGNIOL-VILLARD rd = rx_base + rx_last; 5162873e8e01SMarek Vasut 5163873e8e01SMarek Vasut /* Re-load the descriptor from RAM. */ 516406e07f65SMinghuan Lian inval_start = ((unsigned long)rd) & ~(ARCH_DMA_MINALIGN - 1); 5165873e8e01SMarek Vasut inval_end = inval_start + roundup(sizeof(*rd), ARCH_DMA_MINALIGN); 5166873e8e01SMarek Vasut invalidate_dcache_range(inval_start, inval_end); 5167873e8e01SMarek Vasut 5168*a40b2dffSMiao Yan if (!(rd->status & E1000_RXD_STAT_DD)) 51692439e4bfSJean-Christophe PLAGNIOL-VILLARD return 0; 51702439e4bfSJean-Christophe PLAGNIOL-VILLARD /* DEBUGOUT("recv: packet len=%d\n", rd->length); */ 5171873e8e01SMarek Vasut /* Packet received, make sure the data are re-loaded from RAM. */ 5172*a40b2dffSMiao Yan len = le16_to_cpu(rd->length); 517306e07f65SMinghuan Lian invalidate_dcache_range((unsigned long)packet, 517406e07f65SMinghuan Lian (unsigned long)packet + 517506e07f65SMinghuan Lian roundup(len, ARCH_DMA_MINALIGN)); 51765c5e707aSSimon Glass return len; 51772439e4bfSJean-Christophe PLAGNIOL-VILLARD } 51782439e4bfSJean-Christophe PLAGNIOL-VILLARD 51795c5e707aSSimon Glass static int _e1000_transmit(struct e1000_hw *hw, void *txpacket, int length) 51802439e4bfSJean-Christophe PLAGNIOL-VILLARD { 5181873e8e01SMarek Vasut void *nv_packet = (void *)txpacket; 51822439e4bfSJean-Christophe PLAGNIOL-VILLARD struct e1000_tx_desc *txp; 51832439e4bfSJean-Christophe PLAGNIOL-VILLARD int i = 0; 518406e07f65SMinghuan Lian unsigned long flush_start, flush_end; 51852439e4bfSJean-Christophe PLAGNIOL-VILLARD 51862439e4bfSJean-Christophe PLAGNIOL-VILLARD txp = tx_base + tx_tail; 51872439e4bfSJean-Christophe PLAGNIOL-VILLARD tx_tail = (tx_tail + 1) % 8; 51882439e4bfSJean-Christophe PLAGNIOL-VILLARD 51898aa858cbSWolfgang Denk txp->buffer_addr = cpu_to_le64(virt_to_bus(hw->pdev, nv_packet)); 5190aa070789SRoy Zang txp->lower.data = cpu_to_le32(hw->txd_cmd | length); 51912439e4bfSJean-Christophe PLAGNIOL-VILLARD txp->upper.data = 0; 5192873e8e01SMarek Vasut 5193873e8e01SMarek Vasut /* Dump the packet into RAM so e1000 can pick them. */ 519406e07f65SMinghuan Lian flush_dcache_range((unsigned long)nv_packet, 519506e07f65SMinghuan Lian (unsigned long)nv_packet + 519606e07f65SMinghuan Lian roundup(length, ARCH_DMA_MINALIGN)); 5197873e8e01SMarek Vasut /* Dump the descriptor into RAM as well. */ 519806e07f65SMinghuan Lian flush_start = ((unsigned long)txp) & ~(ARCH_DMA_MINALIGN - 1); 5199873e8e01SMarek Vasut flush_end = flush_start + roundup(sizeof(*txp), ARCH_DMA_MINALIGN); 5200873e8e01SMarek Vasut flush_dcache_range(flush_start, flush_end); 5201873e8e01SMarek Vasut 52022439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, TDT, tx_tail); 52032439e4bfSJean-Christophe PLAGNIOL-VILLARD 5204aa070789SRoy Zang E1000_WRITE_FLUSH(hw); 5205873e8e01SMarek Vasut while (1) { 5206873e8e01SMarek Vasut invalidate_dcache_range(flush_start, flush_end); 5207873e8e01SMarek Vasut if (le32_to_cpu(txp->upper.data) & E1000_TXD_STAT_DD) 5208873e8e01SMarek Vasut break; 52092439e4bfSJean-Christophe PLAGNIOL-VILLARD if (i++ > TOUT_LOOP) { 52102439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("e1000: tx timeout\n"); 52112439e4bfSJean-Christophe PLAGNIOL-VILLARD return 0; 52122439e4bfSJean-Christophe PLAGNIOL-VILLARD } 52132439e4bfSJean-Christophe PLAGNIOL-VILLARD udelay(10); /* give the nic a chance to write to the register */ 52142439e4bfSJean-Christophe PLAGNIOL-VILLARD } 52152439e4bfSJean-Christophe PLAGNIOL-VILLARD return 1; 52162439e4bfSJean-Christophe PLAGNIOL-VILLARD } 52172439e4bfSJean-Christophe PLAGNIOL-VILLARD 52182439e4bfSJean-Christophe PLAGNIOL-VILLARD static void 52195c5e707aSSimon Glass _e1000_disable(struct e1000_hw *hw) 52202439e4bfSJean-Christophe PLAGNIOL-VILLARD { 52212439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Turn off the ethernet interface */ 52222439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, RCTL, 0); 52232439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, TCTL, 0); 52242439e4bfSJean-Christophe PLAGNIOL-VILLARD 52252439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Clear the transmit ring */ 52262439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, TDH, 0); 52272439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, TDT, 0); 52282439e4bfSJean-Christophe PLAGNIOL-VILLARD 52292439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Clear the receive ring */ 52302439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, RDH, 0); 52312439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, RDT, 0); 52322439e4bfSJean-Christophe PLAGNIOL-VILLARD 52332439e4bfSJean-Christophe PLAGNIOL-VILLARD /* put the card in its initial state */ 52342439e4bfSJean-Christophe PLAGNIOL-VILLARD #if 0 52352439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, CTRL, E1000_CTRL_RST); 52362439e4bfSJean-Christophe PLAGNIOL-VILLARD #endif 52372439e4bfSJean-Christophe PLAGNIOL-VILLARD mdelay(10); 52382439e4bfSJean-Christophe PLAGNIOL-VILLARD } 52392439e4bfSJean-Christophe PLAGNIOL-VILLARD 52405c5e707aSSimon Glass /*reset function*/ 52415c5e707aSSimon Glass static inline int 52425c5e707aSSimon Glass e1000_reset(struct e1000_hw *hw, unsigned char enetaddr[6]) 52432439e4bfSJean-Christophe PLAGNIOL-VILLARD { 52445c5e707aSSimon Glass e1000_reset_hw(hw); 52455c5e707aSSimon Glass if (hw->mac_type >= e1000_82544) 52465c5e707aSSimon Glass E1000_WRITE_REG(hw, WUC, 0); 52475c5e707aSSimon Glass 52485c5e707aSSimon Glass return e1000_init_hw(hw, enetaddr); 52495c5e707aSSimon Glass } 52505c5e707aSSimon Glass 52515c5e707aSSimon Glass static int 52525c5e707aSSimon Glass _e1000_init(struct e1000_hw *hw, unsigned char enetaddr[6]) 52535c5e707aSSimon Glass { 52542439e4bfSJean-Christophe PLAGNIOL-VILLARD int ret_val = 0; 52552439e4bfSJean-Christophe PLAGNIOL-VILLARD 52565c5e707aSSimon Glass ret_val = e1000_reset(hw, enetaddr); 52572439e4bfSJean-Christophe PLAGNIOL-VILLARD if (ret_val < 0) { 52582439e4bfSJean-Christophe PLAGNIOL-VILLARD if ((ret_val == -E1000_ERR_NOLINK) || 52592439e4bfSJean-Christophe PLAGNIOL-VILLARD (ret_val == -E1000_ERR_TIMEOUT)) { 52605c5e707aSSimon Glass E1000_ERR(hw, "Valid Link not detected: %d\n", ret_val); 52612439e4bfSJean-Christophe PLAGNIOL-VILLARD } else { 52625c5e707aSSimon Glass E1000_ERR(hw, "Hardware Initialization Failed\n"); 52632439e4bfSJean-Christophe PLAGNIOL-VILLARD } 52645c5e707aSSimon Glass return ret_val; 52652439e4bfSJean-Christophe PLAGNIOL-VILLARD } 52662439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_configure_tx(hw); 52672439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_setup_rctl(hw); 52682439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_configure_rx(hw); 52695c5e707aSSimon Glass return 0; 52702439e4bfSJean-Christophe PLAGNIOL-VILLARD } 52712439e4bfSJean-Christophe PLAGNIOL-VILLARD 5272aa070789SRoy Zang /****************************************************************************** 5273aa070789SRoy Zang * Gets the current PCI bus type of hardware 5274aa070789SRoy Zang * 5275aa070789SRoy Zang * hw - Struct containing variables accessed by shared code 5276aa070789SRoy Zang *****************************************************************************/ 5277aa070789SRoy Zang void e1000_get_bus_type(struct e1000_hw *hw) 5278aa070789SRoy Zang { 5279aa070789SRoy Zang uint32_t status; 5280aa070789SRoy Zang 5281aa070789SRoy Zang switch (hw->mac_type) { 5282aa070789SRoy Zang case e1000_82542_rev2_0: 5283aa070789SRoy Zang case e1000_82542_rev2_1: 5284aa070789SRoy Zang hw->bus_type = e1000_bus_type_pci; 5285aa070789SRoy Zang break; 5286aa070789SRoy Zang case e1000_82571: 5287aa070789SRoy Zang case e1000_82572: 5288aa070789SRoy Zang case e1000_82573: 52892c2668f9SRoy Zang case e1000_82574: 5290aa070789SRoy Zang case e1000_80003es2lan: 5291aa070789SRoy Zang case e1000_ich8lan: 529295186063SMarek Vasut case e1000_igb: 5293aa070789SRoy Zang hw->bus_type = e1000_bus_type_pci_express; 5294aa070789SRoy Zang break; 5295aa070789SRoy Zang default: 5296aa070789SRoy Zang status = E1000_READ_REG(hw, STATUS); 5297aa070789SRoy Zang hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ? 5298aa070789SRoy Zang e1000_bus_type_pcix : e1000_bus_type_pci; 5299aa070789SRoy Zang break; 5300aa070789SRoy Zang } 5301aa070789SRoy Zang } 5302aa070789SRoy Zang 5303c6d80a15SSimon Glass #ifndef CONFIG_DM_ETH 5304ce5207e1SKyle Moffett /* A list of all registered e1000 devices */ 5305ce5207e1SKyle Moffett static LIST_HEAD(e1000_hw_list); 5306c6d80a15SSimon Glass #endif 5307ce5207e1SKyle Moffett 53085c5e707aSSimon Glass static int e1000_init_one(struct e1000_hw *hw, int cardnum, pci_dev_t devno, 53095c5e707aSSimon Glass unsigned char enetaddr[6]) 53102439e4bfSJean-Christophe PLAGNIOL-VILLARD { 5311d60626f8SKyle Moffett u32 val; 53122439e4bfSJean-Christophe PLAGNIOL-VILLARD 5313d60626f8SKyle Moffett /* Assign the passed-in values */ 53142439e4bfSJean-Christophe PLAGNIOL-VILLARD hw->pdev = devno; 53155c5e707aSSimon Glass hw->cardnum = cardnum; 5316d60626f8SKyle Moffett 5317d60626f8SKyle Moffett /* Print a debug message with the IO base address */ 5318d60626f8SKyle Moffett pci_read_config_dword(devno, PCI_BASE_ADDRESS_0, &val); 53195c5e707aSSimon Glass E1000_DBG(hw, "iobase 0x%08x\n", val & 0xfffffff0); 5320d60626f8SKyle Moffett 5321d60626f8SKyle Moffett /* Try to enable I/O accesses and bus-mastering */ 5322d60626f8SKyle Moffett val = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; 5323d60626f8SKyle Moffett pci_write_config_dword(devno, PCI_COMMAND, val); 5324d60626f8SKyle Moffett 5325d60626f8SKyle Moffett /* Make sure it worked */ 5326d60626f8SKyle Moffett pci_read_config_dword(devno, PCI_COMMAND, &val); 5327d60626f8SKyle Moffett if (!(val & PCI_COMMAND_MEMORY)) { 53285c5e707aSSimon Glass E1000_ERR(hw, "Can't enable I/O memory\n"); 53295c5e707aSSimon Glass return -ENOSPC; 5330d60626f8SKyle Moffett } 5331d60626f8SKyle Moffett if (!(val & PCI_COMMAND_MASTER)) { 53325c5e707aSSimon Glass E1000_ERR(hw, "Can't enable bus-mastering\n"); 53335c5e707aSSimon Glass return -EPERM; 5334d60626f8SKyle Moffett } 53352439e4bfSJean-Christophe PLAGNIOL-VILLARD 53362439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Are these variables needed? */ 53372439e4bfSJean-Christophe PLAGNIOL-VILLARD hw->fc = e1000_fc_default; 53382439e4bfSJean-Christophe PLAGNIOL-VILLARD hw->original_fc = e1000_fc_default; 53392439e4bfSJean-Christophe PLAGNIOL-VILLARD hw->autoneg_failed = 0; 5340aa070789SRoy Zang hw->autoneg = 1; 5341472d5460SYork Sun hw->get_link_status = true; 5342a4277200SMarcel Ziswiler #ifndef CONFIG_E1000_NO_NVM 534395186063SMarek Vasut hw->eeprom_semaphore_present = true; 5344a4277200SMarcel Ziswiler #endif 5345d60626f8SKyle Moffett hw->hw_addr = pci_map_bar(devno, PCI_BASE_ADDRESS_0, 5346d60626f8SKyle Moffett PCI_REGION_MEM); 53472439e4bfSJean-Christophe PLAGNIOL-VILLARD hw->mac_type = e1000_undefined; 53482439e4bfSJean-Christophe PLAGNIOL-VILLARD 53492439e4bfSJean-Christophe PLAGNIOL-VILLARD /* MAC and Phy settings */ 53505c5e707aSSimon Glass if (e1000_sw_init(hw) < 0) { 53515c5e707aSSimon Glass E1000_ERR(hw, "Software init failed\n"); 53525c5e707aSSimon Glass return -EIO; 53532439e4bfSJean-Christophe PLAGNIOL-VILLARD } 5354aa070789SRoy Zang if (e1000_check_phy_reset_block(hw)) 53555c5e707aSSimon Glass E1000_ERR(hw, "PHY Reset is blocked!\n"); 5356d60626f8SKyle Moffett 5357ce5207e1SKyle Moffett /* Basic init was OK, reset the hardware and allow SPI access */ 5358aa070789SRoy Zang e1000_reset_hw(hw); 5359d60626f8SKyle Moffett 53608712adfdSRojhalat Ibrahim #ifndef CONFIG_E1000_NO_NVM 5361d60626f8SKyle Moffett /* Validate the EEPROM and get chipset information */ 5362a821d08dSStefan Roese #if !defined(CONFIG_MVBC_1G) 5363aa070789SRoy Zang if (e1000_init_eeprom_params(hw)) { 53645c5e707aSSimon Glass E1000_ERR(hw, "EEPROM is invalid!\n"); 53655c5e707aSSimon Glass return -EINVAL; 5366aa070789SRoy Zang } 536795186063SMarek Vasut if ((E1000_READ_REG(hw, I210_EECD) & E1000_EECD_FLUPD) && 536895186063SMarek Vasut e1000_validate_eeprom_checksum(hw)) 53695c5e707aSSimon Glass return -ENXIO; 53702439e4bfSJean-Christophe PLAGNIOL-VILLARD #endif 53715c5e707aSSimon Glass e1000_read_mac_addr(hw, enetaddr); 53728712adfdSRojhalat Ibrahim #endif 5373aa070789SRoy Zang e1000_get_bus_type(hw); 53742439e4bfSJean-Christophe PLAGNIOL-VILLARD 53758712adfdSRojhalat Ibrahim #ifndef CONFIG_E1000_NO_NVM 53762439e4bfSJean-Christophe PLAGNIOL-VILLARD printf("e1000: %02x:%02x:%02x:%02x:%02x:%02x\n ", 53775c5e707aSSimon Glass enetaddr[0], enetaddr[1], enetaddr[2], 53785c5e707aSSimon Glass enetaddr[3], enetaddr[4], enetaddr[5]); 53798712adfdSRojhalat Ibrahim #else 53805c5e707aSSimon Glass memset(enetaddr, 0, 6); 53818712adfdSRojhalat Ibrahim printf("e1000: no NVM\n"); 53828712adfdSRojhalat Ibrahim #endif 53832439e4bfSJean-Christophe PLAGNIOL-VILLARD 53845c5e707aSSimon Glass return 0; 53855c5e707aSSimon Glass } 53865c5e707aSSimon Glass 53875c5e707aSSimon Glass /* Put the name of a device in a string */ 53885c5e707aSSimon Glass static void e1000_name(char *str, int cardnum) 53895c5e707aSSimon Glass { 53905c5e707aSSimon Glass sprintf(str, "e1000#%u", cardnum); 53915c5e707aSSimon Glass } 53925c5e707aSSimon Glass 5393c6d80a15SSimon Glass #ifndef CONFIG_DM_ETH 53945c5e707aSSimon Glass /************************************************************************** 53955c5e707aSSimon Glass TRANSMIT - Transmit a frame 53965c5e707aSSimon Glass ***************************************************************************/ 53975c5e707aSSimon Glass static int e1000_transmit(struct eth_device *nic, void *txpacket, int length) 53985c5e707aSSimon Glass { 53995c5e707aSSimon Glass struct e1000_hw *hw = nic->priv; 54005c5e707aSSimon Glass 54015c5e707aSSimon Glass return _e1000_transmit(hw, txpacket, length); 54025c5e707aSSimon Glass } 54035c5e707aSSimon Glass 54045c5e707aSSimon Glass /************************************************************************** 54055c5e707aSSimon Glass DISABLE - Turn off ethernet interface 54065c5e707aSSimon Glass ***************************************************************************/ 54075c5e707aSSimon Glass static void 54085c5e707aSSimon Glass e1000_disable(struct eth_device *nic) 54095c5e707aSSimon Glass { 54105c5e707aSSimon Glass struct e1000_hw *hw = nic->priv; 54115c5e707aSSimon Glass 54125c5e707aSSimon Glass _e1000_disable(hw); 54135c5e707aSSimon Glass } 54145c5e707aSSimon Glass 54155c5e707aSSimon Glass /************************************************************************** 54165c5e707aSSimon Glass INIT - set up ethernet interface(s) 54175c5e707aSSimon Glass ***************************************************************************/ 54185c5e707aSSimon Glass static int 54195c5e707aSSimon Glass e1000_init(struct eth_device *nic, bd_t *bis) 54205c5e707aSSimon Glass { 54215c5e707aSSimon Glass struct e1000_hw *hw = nic->priv; 54225c5e707aSSimon Glass 54235c5e707aSSimon Glass return _e1000_init(hw, nic->enetaddr); 54245c5e707aSSimon Glass } 54255c5e707aSSimon Glass 54265c5e707aSSimon Glass static int 54275c5e707aSSimon Glass e1000_poll(struct eth_device *nic) 54285c5e707aSSimon Glass { 54295c5e707aSSimon Glass struct e1000_hw *hw = nic->priv; 54305c5e707aSSimon Glass int len; 54315c5e707aSSimon Glass 54325c5e707aSSimon Glass len = _e1000_poll(hw); 54335c5e707aSSimon Glass if (len) { 54345c5e707aSSimon Glass net_process_received_packet((uchar *)packet, len); 54355c5e707aSSimon Glass fill_rx(hw); 54365c5e707aSSimon Glass } 54375c5e707aSSimon Glass 54385c5e707aSSimon Glass return len ? 1 : 0; 54395c5e707aSSimon Glass } 54405c5e707aSSimon Glass 54415c5e707aSSimon Glass /************************************************************************** 54425c5e707aSSimon Glass PROBE - Look for an adapter, this routine's visible to the outside 54435c5e707aSSimon Glass You should omit the last argument struct pci_device * for a non-PCI NIC 54445c5e707aSSimon Glass ***************************************************************************/ 54455c5e707aSSimon Glass int 54465c5e707aSSimon Glass e1000_initialize(bd_t * bis) 54475c5e707aSSimon Glass { 54485c5e707aSSimon Glass unsigned int i; 54495c5e707aSSimon Glass pci_dev_t devno; 54505c5e707aSSimon Glass int ret; 54515c5e707aSSimon Glass 54525c5e707aSSimon Glass DEBUGFUNC(); 54535c5e707aSSimon Glass 54545c5e707aSSimon Glass /* Find and probe all the matching PCI devices */ 54555c5e707aSSimon Glass for (i = 0; (devno = pci_find_devices(e1000_supported, i)) >= 0; i++) { 54565c5e707aSSimon Glass /* 54575c5e707aSSimon Glass * These will never get freed due to errors, this allows us to 54585c5e707aSSimon Glass * perform SPI EEPROM programming from U-boot, for example. 54595c5e707aSSimon Glass */ 54605c5e707aSSimon Glass struct eth_device *nic = malloc(sizeof(*nic)); 54615c5e707aSSimon Glass struct e1000_hw *hw = malloc(sizeof(*hw)); 54625c5e707aSSimon Glass if (!nic || !hw) { 54635c5e707aSSimon Glass printf("e1000#%u: Out of Memory!\n", i); 54645c5e707aSSimon Glass free(nic); 54655c5e707aSSimon Glass free(hw); 54665c5e707aSSimon Glass continue; 54675c5e707aSSimon Glass } 54685c5e707aSSimon Glass 54695c5e707aSSimon Glass /* Make sure all of the fields are initially zeroed */ 54705c5e707aSSimon Glass memset(nic, 0, sizeof(*nic)); 54715c5e707aSSimon Glass memset(hw, 0, sizeof(*hw)); 54725c5e707aSSimon Glass nic->priv = hw; 54735c5e707aSSimon Glass 54745c5e707aSSimon Glass /* Generate a card name */ 54755c5e707aSSimon Glass e1000_name(nic->name, i); 54765c5e707aSSimon Glass hw->name = nic->name; 54775c5e707aSSimon Glass 54785c5e707aSSimon Glass ret = e1000_init_one(hw, i, devno, nic->enetaddr); 54795c5e707aSSimon Glass if (ret) 54805c5e707aSSimon Glass continue; 54815c5e707aSSimon Glass list_add_tail(&hw->list_node, &e1000_hw_list); 54825c5e707aSSimon Glass 54835c5e707aSSimon Glass hw->nic = nic; 54845c5e707aSSimon Glass 5485d60626f8SKyle Moffett /* Set up the function pointers and register the device */ 54862439e4bfSJean-Christophe PLAGNIOL-VILLARD nic->init = e1000_init; 54872439e4bfSJean-Christophe PLAGNIOL-VILLARD nic->recv = e1000_poll; 54882439e4bfSJean-Christophe PLAGNIOL-VILLARD nic->send = e1000_transmit; 54892439e4bfSJean-Christophe PLAGNIOL-VILLARD nic->halt = e1000_disable; 54902439e4bfSJean-Christophe PLAGNIOL-VILLARD eth_register(nic); 54912439e4bfSJean-Christophe PLAGNIOL-VILLARD } 5492d60626f8SKyle Moffett 5493d60626f8SKyle Moffett return i; 54942439e4bfSJean-Christophe PLAGNIOL-VILLARD } 5495ce5207e1SKyle Moffett 5496ce5207e1SKyle Moffett struct e1000_hw *e1000_find_card(unsigned int cardnum) 5497ce5207e1SKyle Moffett { 5498ce5207e1SKyle Moffett struct e1000_hw *hw; 5499ce5207e1SKyle Moffett 5500ce5207e1SKyle Moffett list_for_each_entry(hw, &e1000_hw_list, list_node) 5501ce5207e1SKyle Moffett if (hw->cardnum == cardnum) 5502ce5207e1SKyle Moffett return hw; 5503ce5207e1SKyle Moffett 5504ce5207e1SKyle Moffett return NULL; 5505ce5207e1SKyle Moffett } 5506c6d80a15SSimon Glass #endif /* !CONFIG_DM_ETH */ 5507ce5207e1SKyle Moffett 5508ce5207e1SKyle Moffett #ifdef CONFIG_CMD_E1000 5509ce5207e1SKyle Moffett static int do_e1000(cmd_tbl_t *cmdtp, int flag, 5510ce5207e1SKyle Moffett int argc, char * const argv[]) 5511ce5207e1SKyle Moffett { 55125c5e707aSSimon Glass unsigned char *mac = NULL; 5513c6d80a15SSimon Glass #ifdef CONFIG_DM_ETH 5514c6d80a15SSimon Glass struct eth_pdata *plat; 5515c6d80a15SSimon Glass struct udevice *dev; 5516c6d80a15SSimon Glass char name[30]; 5517c6d80a15SSimon Glass int ret; 5518c6d80a15SSimon Glass #else 5519ce5207e1SKyle Moffett struct e1000_hw *hw; 5520c6d80a15SSimon Glass #endif 5521c6d80a15SSimon Glass int cardnum; 5522ce5207e1SKyle Moffett 5523ce5207e1SKyle Moffett if (argc < 3) { 5524ce5207e1SKyle Moffett cmd_usage(cmdtp); 5525ce5207e1SKyle Moffett return 1; 5526ce5207e1SKyle Moffett } 5527ce5207e1SKyle Moffett 5528ce5207e1SKyle Moffett /* Make sure we can find the requested e1000 card */ 55295c5e707aSSimon Glass cardnum = simple_strtoul(argv[1], NULL, 10); 5530c6d80a15SSimon Glass #ifdef CONFIG_DM_ETH 5531c6d80a15SSimon Glass e1000_name(name, cardnum); 5532c6d80a15SSimon Glass ret = uclass_get_device_by_name(UCLASS_ETH, name, &dev); 5533c6d80a15SSimon Glass if (!ret) { 5534c6d80a15SSimon Glass plat = dev_get_platdata(dev); 5535c6d80a15SSimon Glass mac = plat->enetaddr; 5536c6d80a15SSimon Glass } 5537c6d80a15SSimon Glass #else 55385c5e707aSSimon Glass hw = e1000_find_card(cardnum); 55395c5e707aSSimon Glass if (hw) 55405c5e707aSSimon Glass mac = hw->nic->enetaddr; 5541c6d80a15SSimon Glass #endif 55425c5e707aSSimon Glass if (!mac) { 5543ce5207e1SKyle Moffett printf("e1000: ERROR: No such device: e1000#%s\n", argv[1]); 5544ce5207e1SKyle Moffett return 1; 5545ce5207e1SKyle Moffett } 5546ce5207e1SKyle Moffett 5547ce5207e1SKyle Moffett if (!strcmp(argv[2], "print-mac-address")) { 5548ce5207e1SKyle Moffett printf("%02x:%02x:%02x:%02x:%02x:%02x\n", 5549ce5207e1SKyle Moffett mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]); 5550ce5207e1SKyle Moffett return 0; 5551ce5207e1SKyle Moffett } 5552ce5207e1SKyle Moffett 5553ce5207e1SKyle Moffett #ifdef CONFIG_E1000_SPI 5554ce5207e1SKyle Moffett /* Handle the "SPI" subcommand */ 5555ce5207e1SKyle Moffett if (!strcmp(argv[2], "spi")) 5556ce5207e1SKyle Moffett return do_e1000_spi(cmdtp, hw, argc - 3, argv + 3); 5557ce5207e1SKyle Moffett #endif 5558ce5207e1SKyle Moffett 5559ce5207e1SKyle Moffett cmd_usage(cmdtp); 5560ce5207e1SKyle Moffett return 1; 5561ce5207e1SKyle Moffett } 5562ce5207e1SKyle Moffett 5563ce5207e1SKyle Moffett U_BOOT_CMD( 5564ce5207e1SKyle Moffett e1000, 7, 0, do_e1000, 5565ce5207e1SKyle Moffett "Intel e1000 controller management", 5566ce5207e1SKyle Moffett /* */"<card#> print-mac-address\n" 5567ce5207e1SKyle Moffett #ifdef CONFIG_E1000_SPI 5568ce5207e1SKyle Moffett "e1000 <card#> spi show [<offset> [<length>]]\n" 5569ce5207e1SKyle Moffett "e1000 <card#> spi dump <addr> <offset> <length>\n" 5570ce5207e1SKyle Moffett "e1000 <card#> spi program <addr> <offset> <length>\n" 5571ce5207e1SKyle Moffett "e1000 <card#> spi checksum [update]\n" 5572ce5207e1SKyle Moffett #endif 5573ce5207e1SKyle Moffett " - Manage the Intel E1000 PCI device" 5574ce5207e1SKyle Moffett ); 5575ce5207e1SKyle Moffett #endif /* not CONFIG_CMD_E1000 */ 5576c6d80a15SSimon Glass 5577c6d80a15SSimon Glass #ifdef CONFIG_DM_ETH 5578c6d80a15SSimon Glass static int e1000_eth_start(struct udevice *dev) 5579c6d80a15SSimon Glass { 5580c6d80a15SSimon Glass struct eth_pdata *plat = dev_get_platdata(dev); 5581c6d80a15SSimon Glass struct e1000_hw *hw = dev_get_priv(dev); 5582c6d80a15SSimon Glass 5583c6d80a15SSimon Glass return _e1000_init(hw, plat->enetaddr); 5584c6d80a15SSimon Glass } 5585c6d80a15SSimon Glass 5586c6d80a15SSimon Glass static void e1000_eth_stop(struct udevice *dev) 5587c6d80a15SSimon Glass { 5588c6d80a15SSimon Glass struct e1000_hw *hw = dev_get_priv(dev); 5589c6d80a15SSimon Glass 5590c6d80a15SSimon Glass _e1000_disable(hw); 5591c6d80a15SSimon Glass } 5592c6d80a15SSimon Glass 5593c6d80a15SSimon Glass static int e1000_eth_send(struct udevice *dev, void *packet, int length) 5594c6d80a15SSimon Glass { 5595c6d80a15SSimon Glass struct e1000_hw *hw = dev_get_priv(dev); 5596c6d80a15SSimon Glass int ret; 5597c6d80a15SSimon Glass 5598c6d80a15SSimon Glass ret = _e1000_transmit(hw, packet, length); 5599c6d80a15SSimon Glass 5600c6d80a15SSimon Glass return ret ? 0 : -ETIMEDOUT; 5601c6d80a15SSimon Glass } 5602c6d80a15SSimon Glass 5603c6d80a15SSimon Glass static int e1000_eth_recv(struct udevice *dev, int flags, uchar **packetp) 5604c6d80a15SSimon Glass { 5605c6d80a15SSimon Glass struct e1000_hw *hw = dev_get_priv(dev); 5606c6d80a15SSimon Glass int len; 5607c6d80a15SSimon Glass 5608c6d80a15SSimon Glass len = _e1000_poll(hw); 5609c6d80a15SSimon Glass if (len) 5610c6d80a15SSimon Glass *packetp = packet; 5611c6d80a15SSimon Glass 5612c6d80a15SSimon Glass return len ? len : -EAGAIN; 5613c6d80a15SSimon Glass } 5614c6d80a15SSimon Glass 5615c6d80a15SSimon Glass static int e1000_free_pkt(struct udevice *dev, uchar *packet, int length) 5616c6d80a15SSimon Glass { 5617c6d80a15SSimon Glass struct e1000_hw *hw = dev_get_priv(dev); 5618c6d80a15SSimon Glass 5619c6d80a15SSimon Glass fill_rx(hw); 5620c6d80a15SSimon Glass 5621c6d80a15SSimon Glass return 0; 5622c6d80a15SSimon Glass } 5623c6d80a15SSimon Glass 5624c6d80a15SSimon Glass static int e1000_eth_probe(struct udevice *dev) 5625c6d80a15SSimon Glass { 5626c6d80a15SSimon Glass struct eth_pdata *plat = dev_get_platdata(dev); 5627c6d80a15SSimon Glass struct e1000_hw *hw = dev_get_priv(dev); 5628c6d80a15SSimon Glass int ret; 5629c6d80a15SSimon Glass 5630c6d80a15SSimon Glass hw->name = dev->name; 5631c6d80a15SSimon Glass ret = e1000_init_one(hw, trailing_strtol(dev->name), pci_get_bdf(dev), 5632c6d80a15SSimon Glass plat->enetaddr); 5633c6d80a15SSimon Glass if (ret < 0) { 5634c6d80a15SSimon Glass printf(pr_fmt("failed to initialize card: %d\n"), ret); 5635c6d80a15SSimon Glass return ret; 5636c6d80a15SSimon Glass } 5637c6d80a15SSimon Glass 5638c6d80a15SSimon Glass return 0; 5639c6d80a15SSimon Glass } 5640c6d80a15SSimon Glass 5641c6d80a15SSimon Glass static int e1000_eth_bind(struct udevice *dev) 5642c6d80a15SSimon Glass { 5643c6d80a15SSimon Glass char name[20]; 5644c6d80a15SSimon Glass 5645c6d80a15SSimon Glass /* 5646c6d80a15SSimon Glass * A simple way to number the devices. When device tree is used this 5647c6d80a15SSimon Glass * is unnecessary, but when the device is just discovered on the PCI 5648c6d80a15SSimon Glass * bus we need a name. We could instead have the uclass figure out 5649c6d80a15SSimon Glass * which devices are different and number them. 5650c6d80a15SSimon Glass */ 5651c6d80a15SSimon Glass e1000_name(name, num_cards++); 5652c6d80a15SSimon Glass 5653c6d80a15SSimon Glass return device_set_name(dev, name); 5654c6d80a15SSimon Glass } 5655c6d80a15SSimon Glass 5656c6d80a15SSimon Glass static const struct eth_ops e1000_eth_ops = { 5657c6d80a15SSimon Glass .start = e1000_eth_start, 5658c6d80a15SSimon Glass .send = e1000_eth_send, 5659c6d80a15SSimon Glass .recv = e1000_eth_recv, 5660c6d80a15SSimon Glass .stop = e1000_eth_stop, 5661c6d80a15SSimon Glass .free_pkt = e1000_free_pkt, 5662c6d80a15SSimon Glass }; 5663c6d80a15SSimon Glass 5664c6d80a15SSimon Glass static const struct udevice_id e1000_eth_ids[] = { 5665c6d80a15SSimon Glass { .compatible = "intel,e1000" }, 5666c6d80a15SSimon Glass { } 5667c6d80a15SSimon Glass }; 5668c6d80a15SSimon Glass 5669c6d80a15SSimon Glass U_BOOT_DRIVER(eth_e1000) = { 5670c6d80a15SSimon Glass .name = "eth_e1000", 5671c6d80a15SSimon Glass .id = UCLASS_ETH, 5672c6d80a15SSimon Glass .of_match = e1000_eth_ids, 5673c6d80a15SSimon Glass .bind = e1000_eth_bind, 5674c6d80a15SSimon Glass .probe = e1000_eth_probe, 5675c6d80a15SSimon Glass .ops = &e1000_eth_ops, 5676c6d80a15SSimon Glass .priv_auto_alloc_size = sizeof(struct e1000_hw), 5677c6d80a15SSimon Glass .platdata_auto_alloc_size = sizeof(struct eth_pdata), 5678c6d80a15SSimon Glass }; 5679c6d80a15SSimon Glass 5680c6d80a15SSimon Glass U_BOOT_PCI_DEVICE(eth_e1000, e1000_supported); 5681c6d80a15SSimon Glass #endif 5682