12439e4bfSJean-Christophe PLAGNIOL-VILLARD /************************************************************************** 2ac3315c2SAndre Schwarz Intel Pro 1000 for ppcboot/das-u-boot 32439e4bfSJean-Christophe PLAGNIOL-VILLARD Drivers are port from Intel's Linux driver e1000-4.3.15 42439e4bfSJean-Christophe PLAGNIOL-VILLARD and from Etherboot pro 1000 driver by mrakes at vivato dot net 52439e4bfSJean-Christophe PLAGNIOL-VILLARD tested on both gig copper and gig fiber boards 62439e4bfSJean-Christophe PLAGNIOL-VILLARD ***************************************************************************/ 72439e4bfSJean-Christophe PLAGNIOL-VILLARD /******************************************************************************* 82439e4bfSJean-Christophe PLAGNIOL-VILLARD 92439e4bfSJean-Christophe PLAGNIOL-VILLARD 102439e4bfSJean-Christophe PLAGNIOL-VILLARD Copyright(c) 1999 - 2002 Intel Corporation. All rights reserved. 112439e4bfSJean-Christophe PLAGNIOL-VILLARD 121a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 132439e4bfSJean-Christophe PLAGNIOL-VILLARD 142439e4bfSJean-Christophe PLAGNIOL-VILLARD Contact Information: 152439e4bfSJean-Christophe PLAGNIOL-VILLARD Linux NICS <linux.nics@intel.com> 162439e4bfSJean-Christophe PLAGNIOL-VILLARD Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 172439e4bfSJean-Christophe PLAGNIOL-VILLARD 182439e4bfSJean-Christophe PLAGNIOL-VILLARD *******************************************************************************/ 192439e4bfSJean-Christophe PLAGNIOL-VILLARD /* 202439e4bfSJean-Christophe PLAGNIOL-VILLARD * Copyright (C) Archway Digital Solutions. 212439e4bfSJean-Christophe PLAGNIOL-VILLARD * 222439e4bfSJean-Christophe PLAGNIOL-VILLARD * written by Chrsitopher Li <cli at arcyway dot com> or <chrisl at gnuchina dot org> 232439e4bfSJean-Christophe PLAGNIOL-VILLARD * 2/9/2002 242439e4bfSJean-Christophe PLAGNIOL-VILLARD * 252439e4bfSJean-Christophe PLAGNIOL-VILLARD * Copyright (C) Linux Networx. 262439e4bfSJean-Christophe PLAGNIOL-VILLARD * Massive upgrade to work with the new intel gigabit NICs. 272439e4bfSJean-Christophe PLAGNIOL-VILLARD * <ebiederman at lnxi dot com> 282c2668f9SRoy Zang * 292c2668f9SRoy Zang * Copyright 2011 Freescale Semiconductor, Inc. 302439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 312439e4bfSJean-Christophe PLAGNIOL-VILLARD 322439e4bfSJean-Christophe PLAGNIOL-VILLARD #include "e1000.h" 332439e4bfSJean-Christophe PLAGNIOL-VILLARD 342439e4bfSJean-Christophe PLAGNIOL-VILLARD #define TOUT_LOOP 100000 352439e4bfSJean-Christophe PLAGNIOL-VILLARD 36f81ecb5dSTimur Tabi #define virt_to_bus(devno, v) pci_virt_to_mem(devno, (void *) (v)) 372439e4bfSJean-Christophe PLAGNIOL-VILLARD #define bus_to_phys(devno, a) pci_mem_to_phys(devno, a) 382439e4bfSJean-Christophe PLAGNIOL-VILLARD 399ea005fbSRoy Zang #define E1000_DEFAULT_PCI_PBA 0x00000030 409ea005fbSRoy Zang #define E1000_DEFAULT_PCIE_PBA 0x000a0026 412439e4bfSJean-Christophe PLAGNIOL-VILLARD 422439e4bfSJean-Christophe PLAGNIOL-VILLARD /* NIC specific static variables go here */ 432439e4bfSJean-Christophe PLAGNIOL-VILLARD 44873e8e01SMarek Vasut /* Intel i210 needs the DMA descriptor rings aligned to 128b */ 45873e8e01SMarek Vasut #define E1000_BUFFER_ALIGN 128 462439e4bfSJean-Christophe PLAGNIOL-VILLARD 47873e8e01SMarek Vasut DEFINE_ALIGN_BUFFER(struct e1000_tx_desc, tx_base, 16, E1000_BUFFER_ALIGN); 48873e8e01SMarek Vasut DEFINE_ALIGN_BUFFER(struct e1000_rx_desc, rx_base, 16, E1000_BUFFER_ALIGN); 49873e8e01SMarek Vasut DEFINE_ALIGN_BUFFER(unsigned char, packet, 4096, E1000_BUFFER_ALIGN); 502439e4bfSJean-Christophe PLAGNIOL-VILLARD 512439e4bfSJean-Christophe PLAGNIOL-VILLARD static int tx_tail; 522439e4bfSJean-Christophe PLAGNIOL-VILLARD static int rx_tail, rx_last; 532439e4bfSJean-Christophe PLAGNIOL-VILLARD 54d60626f8SKyle Moffett static struct pci_device_id e1000_supported[] = { 552439e4bfSJean-Christophe PLAGNIOL-VILLARD {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82542}, 562439e4bfSJean-Christophe PLAGNIOL-VILLARD {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82543GC_FIBER}, 572439e4bfSJean-Christophe PLAGNIOL-VILLARD {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82543GC_COPPER}, 582439e4bfSJean-Christophe PLAGNIOL-VILLARD {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544EI_COPPER}, 592439e4bfSJean-Christophe PLAGNIOL-VILLARD {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544EI_FIBER}, 602439e4bfSJean-Christophe PLAGNIOL-VILLARD {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544GC_COPPER}, 612439e4bfSJean-Christophe PLAGNIOL-VILLARD {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544GC_LOM}, 622439e4bfSJean-Christophe PLAGNIOL-VILLARD {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82540EM}, 632439e4bfSJean-Christophe PLAGNIOL-VILLARD {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545EM_COPPER}, 648915f118SPaul Gortmaker {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545GM_COPPER}, 652439e4bfSJean-Christophe PLAGNIOL-VILLARD {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_COPPER}, 662439e4bfSJean-Christophe PLAGNIOL-VILLARD {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545EM_FIBER}, 672439e4bfSJean-Christophe PLAGNIOL-VILLARD {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_FIBER}, 682ab4a4d0SReinhard Arlt {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546GB_COPPER}, 692439e4bfSJean-Christophe PLAGNIOL-VILLARD {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82540EM_LOM}, 70ac3315c2SAndre Schwarz {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82541ER}, 71aa3b8bf9SWolfgang Grandegger {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82541GI_LF}, 72aa070789SRoy Zang /* E1000 PCIe card */ 73aa070789SRoy Zang {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_COPPER}, 74aa070789SRoy Zang {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_FIBER }, 75aa070789SRoy Zang {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES }, 76aa070789SRoy Zang {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_COPPER}, 77aa070789SRoy Zang {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571PT_QUAD_COPPER}, 78aa070789SRoy Zang {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_FIBER}, 79aa070789SRoy Zang {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_COPPER_LOWPROFILE}, 80aa070789SRoy Zang {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES_DUAL}, 81aa070789SRoy Zang {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES_QUAD}, 82aa070789SRoy Zang {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_COPPER}, 83aa070789SRoy Zang {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_FIBER}, 84aa070789SRoy Zang {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_SERDES}, 85aa070789SRoy Zang {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI}, 86aa070789SRoy Zang {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573E}, 87aa070789SRoy Zang {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573E_IAMT}, 88aa070789SRoy Zang {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573L}, 892c2668f9SRoy Zang {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82574L}, 90aa070789SRoy Zang {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546GB_QUAD_COPPER_KSP3}, 91aa070789SRoy Zang {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_COPPER_DPT}, 92aa070789SRoy Zang {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_SERDES_DPT}, 93aa070789SRoy Zang {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_COPPER_SPT}, 94aa070789SRoy Zang {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_SERDES_SPT}, 956c499abeSMarcel Ziswiler {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_UNPROGRAMMED}, 966c499abeSMarcel Ziswiler {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I211_UNPROGRAMMED}, 9795186063SMarek Vasut {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_COPPER}, 986c499abeSMarcel Ziswiler {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I211_COPPER}, 9995186063SMarek Vasut {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_COPPER_FLASHLESS}, 10095186063SMarek Vasut {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_SERDES}, 10195186063SMarek Vasut {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_SERDES_FLASHLESS}, 10295186063SMarek Vasut {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_1000BASEKX}, 10395186063SMarek Vasut 1041bc43437SStefan Althoefer {} 1052439e4bfSJean-Christophe PLAGNIOL-VILLARD }; 1062439e4bfSJean-Christophe PLAGNIOL-VILLARD 1072439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Function forward declarations */ 1082439e4bfSJean-Christophe PLAGNIOL-VILLARD static int e1000_setup_link(struct eth_device *nic); 1092439e4bfSJean-Christophe PLAGNIOL-VILLARD static int e1000_setup_fiber_link(struct eth_device *nic); 1102439e4bfSJean-Christophe PLAGNIOL-VILLARD static int e1000_setup_copper_link(struct eth_device *nic); 1112439e4bfSJean-Christophe PLAGNIOL-VILLARD static int e1000_phy_setup_autoneg(struct e1000_hw *hw); 1122439e4bfSJean-Christophe PLAGNIOL-VILLARD static void e1000_config_collision_dist(struct e1000_hw *hw); 1132439e4bfSJean-Christophe PLAGNIOL-VILLARD static int e1000_config_mac_to_phy(struct e1000_hw *hw); 1142439e4bfSJean-Christophe PLAGNIOL-VILLARD static int e1000_config_fc_after_link_up(struct e1000_hw *hw); 1152439e4bfSJean-Christophe PLAGNIOL-VILLARD static int e1000_check_for_link(struct eth_device *nic); 1162439e4bfSJean-Christophe PLAGNIOL-VILLARD static int e1000_wait_autoneg(struct e1000_hw *hw); 117aa070789SRoy Zang static int e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t * speed, 1182439e4bfSJean-Christophe PLAGNIOL-VILLARD uint16_t * duplex); 1192439e4bfSJean-Christophe PLAGNIOL-VILLARD static int e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, 1202439e4bfSJean-Christophe PLAGNIOL-VILLARD uint16_t * phy_data); 1212439e4bfSJean-Christophe PLAGNIOL-VILLARD static int e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, 1222439e4bfSJean-Christophe PLAGNIOL-VILLARD uint16_t phy_data); 123aa070789SRoy Zang static int32_t e1000_phy_hw_reset(struct e1000_hw *hw); 1242439e4bfSJean-Christophe PLAGNIOL-VILLARD static int e1000_phy_reset(struct e1000_hw *hw); 1252439e4bfSJean-Christophe PLAGNIOL-VILLARD static int e1000_detect_gig_phy(struct e1000_hw *hw); 126aa070789SRoy Zang static void e1000_set_media_type(struct e1000_hw *hw); 1272439e4bfSJean-Christophe PLAGNIOL-VILLARD 128aa070789SRoy Zang static int32_t e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask); 129aa070789SRoy Zang static int32_t e1000_check_phy_reset_block(struct e1000_hw *hw); 1302439e4bfSJean-Christophe PLAGNIOL-VILLARD 1318712adfdSRojhalat Ibrahim #ifndef CONFIG_E1000_NO_NVM 1328712adfdSRojhalat Ibrahim static void e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw); 133ecbd2078SRoy Zang static int32_t e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset, 134ecbd2078SRoy Zang uint16_t words, 135ecbd2078SRoy Zang uint16_t *data); 1362439e4bfSJean-Christophe PLAGNIOL-VILLARD /****************************************************************************** 1372439e4bfSJean-Christophe PLAGNIOL-VILLARD * Raises the EEPROM's clock input. 1382439e4bfSJean-Christophe PLAGNIOL-VILLARD * 1392439e4bfSJean-Christophe PLAGNIOL-VILLARD * hw - Struct containing variables accessed by shared code 1402439e4bfSJean-Christophe PLAGNIOL-VILLARD * eecd - EECD's current value 1412439e4bfSJean-Christophe PLAGNIOL-VILLARD *****************************************************************************/ 1422326a94dSKyle Moffett void e1000_raise_ee_clk(struct e1000_hw *hw, uint32_t * eecd) 1432439e4bfSJean-Christophe PLAGNIOL-VILLARD { 1442439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Raise the clock input to the EEPROM (by setting the SK bit), and then 1452439e4bfSJean-Christophe PLAGNIOL-VILLARD * wait 50 microseconds. 1462439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 1472439e4bfSJean-Christophe PLAGNIOL-VILLARD *eecd = *eecd | E1000_EECD_SK; 1482439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, EECD, *eecd); 1492439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_FLUSH(hw); 1502439e4bfSJean-Christophe PLAGNIOL-VILLARD udelay(50); 1512439e4bfSJean-Christophe PLAGNIOL-VILLARD } 1522439e4bfSJean-Christophe PLAGNIOL-VILLARD 1532439e4bfSJean-Christophe PLAGNIOL-VILLARD /****************************************************************************** 1542439e4bfSJean-Christophe PLAGNIOL-VILLARD * Lowers the EEPROM's clock input. 1552439e4bfSJean-Christophe PLAGNIOL-VILLARD * 1562439e4bfSJean-Christophe PLAGNIOL-VILLARD * hw - Struct containing variables accessed by shared code 1572439e4bfSJean-Christophe PLAGNIOL-VILLARD * eecd - EECD's current value 1582439e4bfSJean-Christophe PLAGNIOL-VILLARD *****************************************************************************/ 1592326a94dSKyle Moffett void e1000_lower_ee_clk(struct e1000_hw *hw, uint32_t * eecd) 1602439e4bfSJean-Christophe PLAGNIOL-VILLARD { 1612439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Lower the clock input to the EEPROM (by clearing the SK bit), and then 1622439e4bfSJean-Christophe PLAGNIOL-VILLARD * wait 50 microseconds. 1632439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 1642439e4bfSJean-Christophe PLAGNIOL-VILLARD *eecd = *eecd & ~E1000_EECD_SK; 1652439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, EECD, *eecd); 1662439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_FLUSH(hw); 1672439e4bfSJean-Christophe PLAGNIOL-VILLARD udelay(50); 1682439e4bfSJean-Christophe PLAGNIOL-VILLARD } 1692439e4bfSJean-Christophe PLAGNIOL-VILLARD 1702439e4bfSJean-Christophe PLAGNIOL-VILLARD /****************************************************************************** 1712439e4bfSJean-Christophe PLAGNIOL-VILLARD * Shift data bits out to the EEPROM. 1722439e4bfSJean-Christophe PLAGNIOL-VILLARD * 1732439e4bfSJean-Christophe PLAGNIOL-VILLARD * hw - Struct containing variables accessed by shared code 1742439e4bfSJean-Christophe PLAGNIOL-VILLARD * data - data to send to the EEPROM 1752439e4bfSJean-Christophe PLAGNIOL-VILLARD * count - number of bits to shift out 1762439e4bfSJean-Christophe PLAGNIOL-VILLARD *****************************************************************************/ 1772439e4bfSJean-Christophe PLAGNIOL-VILLARD static void 1782439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_shift_out_ee_bits(struct e1000_hw *hw, uint16_t data, uint16_t count) 1792439e4bfSJean-Christophe PLAGNIOL-VILLARD { 1802439e4bfSJean-Christophe PLAGNIOL-VILLARD uint32_t eecd; 1812439e4bfSJean-Christophe PLAGNIOL-VILLARD uint32_t mask; 1822439e4bfSJean-Christophe PLAGNIOL-VILLARD 1832439e4bfSJean-Christophe PLAGNIOL-VILLARD /* We need to shift "count" bits out to the EEPROM. So, value in the 1842439e4bfSJean-Christophe PLAGNIOL-VILLARD * "data" parameter will be shifted out to the EEPROM one bit at a time. 1852439e4bfSJean-Christophe PLAGNIOL-VILLARD * In order to do this, "data" must be broken down into bits. 1862439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 1872439e4bfSJean-Christophe PLAGNIOL-VILLARD mask = 0x01 << (count - 1); 1882439e4bfSJean-Christophe PLAGNIOL-VILLARD eecd = E1000_READ_REG(hw, EECD); 1892439e4bfSJean-Christophe PLAGNIOL-VILLARD eecd &= ~(E1000_EECD_DO | E1000_EECD_DI); 1902439e4bfSJean-Christophe PLAGNIOL-VILLARD do { 1912439e4bfSJean-Christophe PLAGNIOL-VILLARD /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1", 1922439e4bfSJean-Christophe PLAGNIOL-VILLARD * and then raising and then lowering the clock (the SK bit controls 1932439e4bfSJean-Christophe PLAGNIOL-VILLARD * the clock input to the EEPROM). A "0" is shifted out to the EEPROM 1942439e4bfSJean-Christophe PLAGNIOL-VILLARD * by setting "DI" to "0" and then raising and then lowering the clock. 1952439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 1962439e4bfSJean-Christophe PLAGNIOL-VILLARD eecd &= ~E1000_EECD_DI; 1972439e4bfSJean-Christophe PLAGNIOL-VILLARD 1982439e4bfSJean-Christophe PLAGNIOL-VILLARD if (data & mask) 1992439e4bfSJean-Christophe PLAGNIOL-VILLARD eecd |= E1000_EECD_DI; 2002439e4bfSJean-Christophe PLAGNIOL-VILLARD 2012439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, EECD, eecd); 2022439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_FLUSH(hw); 2032439e4bfSJean-Christophe PLAGNIOL-VILLARD 2042439e4bfSJean-Christophe PLAGNIOL-VILLARD udelay(50); 2052439e4bfSJean-Christophe PLAGNIOL-VILLARD 2062439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_raise_ee_clk(hw, &eecd); 2072439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_lower_ee_clk(hw, &eecd); 2082439e4bfSJean-Christophe PLAGNIOL-VILLARD 2092439e4bfSJean-Christophe PLAGNIOL-VILLARD mask = mask >> 1; 2102439e4bfSJean-Christophe PLAGNIOL-VILLARD 2112439e4bfSJean-Christophe PLAGNIOL-VILLARD } while (mask); 2122439e4bfSJean-Christophe PLAGNIOL-VILLARD 2132439e4bfSJean-Christophe PLAGNIOL-VILLARD /* We leave the "DI" bit set to "0" when we leave this routine. */ 2142439e4bfSJean-Christophe PLAGNIOL-VILLARD eecd &= ~E1000_EECD_DI; 2152439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, EECD, eecd); 2162439e4bfSJean-Christophe PLAGNIOL-VILLARD } 2172439e4bfSJean-Christophe PLAGNIOL-VILLARD 2182439e4bfSJean-Christophe PLAGNIOL-VILLARD /****************************************************************************** 2192439e4bfSJean-Christophe PLAGNIOL-VILLARD * Shift data bits in from the EEPROM 2202439e4bfSJean-Christophe PLAGNIOL-VILLARD * 2212439e4bfSJean-Christophe PLAGNIOL-VILLARD * hw - Struct containing variables accessed by shared code 2222439e4bfSJean-Christophe PLAGNIOL-VILLARD *****************************************************************************/ 2232439e4bfSJean-Christophe PLAGNIOL-VILLARD static uint16_t 224aa070789SRoy Zang e1000_shift_in_ee_bits(struct e1000_hw *hw, uint16_t count) 2252439e4bfSJean-Christophe PLAGNIOL-VILLARD { 2262439e4bfSJean-Christophe PLAGNIOL-VILLARD uint32_t eecd; 2272439e4bfSJean-Christophe PLAGNIOL-VILLARD uint32_t i; 2282439e4bfSJean-Christophe PLAGNIOL-VILLARD uint16_t data; 2292439e4bfSJean-Christophe PLAGNIOL-VILLARD 230aa070789SRoy Zang /* In order to read a register from the EEPROM, we need to shift 'count' 231aa070789SRoy Zang * bits in from the EEPROM. Bits are "shifted in" by raising the clock 232aa070789SRoy Zang * input to the EEPROM (setting the SK bit), and then reading the 233aa070789SRoy Zang * value of the "DO" bit. During this "shifting in" process the 234aa070789SRoy Zang * "DI" bit should always be clear. 2352439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 2362439e4bfSJean-Christophe PLAGNIOL-VILLARD 2372439e4bfSJean-Christophe PLAGNIOL-VILLARD eecd = E1000_READ_REG(hw, EECD); 2382439e4bfSJean-Christophe PLAGNIOL-VILLARD 2392439e4bfSJean-Christophe PLAGNIOL-VILLARD eecd &= ~(E1000_EECD_DO | E1000_EECD_DI); 2402439e4bfSJean-Christophe PLAGNIOL-VILLARD data = 0; 2412439e4bfSJean-Christophe PLAGNIOL-VILLARD 242aa070789SRoy Zang for (i = 0; i < count; i++) { 2432439e4bfSJean-Christophe PLAGNIOL-VILLARD data = data << 1; 2442439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_raise_ee_clk(hw, &eecd); 2452439e4bfSJean-Christophe PLAGNIOL-VILLARD 2462439e4bfSJean-Christophe PLAGNIOL-VILLARD eecd = E1000_READ_REG(hw, EECD); 2472439e4bfSJean-Christophe PLAGNIOL-VILLARD 2482439e4bfSJean-Christophe PLAGNIOL-VILLARD eecd &= ~(E1000_EECD_DI); 2492439e4bfSJean-Christophe PLAGNIOL-VILLARD if (eecd & E1000_EECD_DO) 2502439e4bfSJean-Christophe PLAGNIOL-VILLARD data |= 1; 2512439e4bfSJean-Christophe PLAGNIOL-VILLARD 2522439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_lower_ee_clk(hw, &eecd); 2532439e4bfSJean-Christophe PLAGNIOL-VILLARD } 2542439e4bfSJean-Christophe PLAGNIOL-VILLARD 2552439e4bfSJean-Christophe PLAGNIOL-VILLARD return data; 2562439e4bfSJean-Christophe PLAGNIOL-VILLARD } 2572439e4bfSJean-Christophe PLAGNIOL-VILLARD 2582439e4bfSJean-Christophe PLAGNIOL-VILLARD /****************************************************************************** 2592439e4bfSJean-Christophe PLAGNIOL-VILLARD * Returns EEPROM to a "standby" state 2602439e4bfSJean-Christophe PLAGNIOL-VILLARD * 2612439e4bfSJean-Christophe PLAGNIOL-VILLARD * hw - Struct containing variables accessed by shared code 2622439e4bfSJean-Christophe PLAGNIOL-VILLARD *****************************************************************************/ 2632326a94dSKyle Moffett void e1000_standby_eeprom(struct e1000_hw *hw) 2642439e4bfSJean-Christophe PLAGNIOL-VILLARD { 265aa070789SRoy Zang struct e1000_eeprom_info *eeprom = &hw->eeprom; 2662439e4bfSJean-Christophe PLAGNIOL-VILLARD uint32_t eecd; 2672439e4bfSJean-Christophe PLAGNIOL-VILLARD 2682439e4bfSJean-Christophe PLAGNIOL-VILLARD eecd = E1000_READ_REG(hw, EECD); 2692439e4bfSJean-Christophe PLAGNIOL-VILLARD 270aa070789SRoy Zang if (eeprom->type == e1000_eeprom_microwire) { 2712439e4bfSJean-Christophe PLAGNIOL-VILLARD eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); 2722439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, EECD, eecd); 2732439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_FLUSH(hw); 274aa070789SRoy Zang udelay(eeprom->delay_usec); 2752439e4bfSJean-Christophe PLAGNIOL-VILLARD 2762439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Clock high */ 2772439e4bfSJean-Christophe PLAGNIOL-VILLARD eecd |= E1000_EECD_SK; 2782439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, EECD, eecd); 2792439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_FLUSH(hw); 280aa070789SRoy Zang udelay(eeprom->delay_usec); 2812439e4bfSJean-Christophe PLAGNIOL-VILLARD 2822439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Select EEPROM */ 2832439e4bfSJean-Christophe PLAGNIOL-VILLARD eecd |= E1000_EECD_CS; 2842439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, EECD, eecd); 2852439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_FLUSH(hw); 286aa070789SRoy Zang udelay(eeprom->delay_usec); 2872439e4bfSJean-Christophe PLAGNIOL-VILLARD 2882439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Clock low */ 2892439e4bfSJean-Christophe PLAGNIOL-VILLARD eecd &= ~E1000_EECD_SK; 2902439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, EECD, eecd); 2912439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_FLUSH(hw); 292aa070789SRoy Zang udelay(eeprom->delay_usec); 293aa070789SRoy Zang } else if (eeprom->type == e1000_eeprom_spi) { 294aa070789SRoy Zang /* Toggle CS to flush commands */ 295aa070789SRoy Zang eecd |= E1000_EECD_CS; 296aa070789SRoy Zang E1000_WRITE_REG(hw, EECD, eecd); 297aa070789SRoy Zang E1000_WRITE_FLUSH(hw); 298aa070789SRoy Zang udelay(eeprom->delay_usec); 299aa070789SRoy Zang eecd &= ~E1000_EECD_CS; 300aa070789SRoy Zang E1000_WRITE_REG(hw, EECD, eecd); 301aa070789SRoy Zang E1000_WRITE_FLUSH(hw); 302aa070789SRoy Zang udelay(eeprom->delay_usec); 303aa070789SRoy Zang } 304aa070789SRoy Zang } 305aa070789SRoy Zang 306aa070789SRoy Zang /*************************************************************************** 307aa070789SRoy Zang * Description: Determines if the onboard NVM is FLASH or EEPROM. 308aa070789SRoy Zang * 309aa070789SRoy Zang * hw - Struct containing variables accessed by shared code 310aa070789SRoy Zang ****************************************************************************/ 311472d5460SYork Sun static bool e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw) 312aa070789SRoy Zang { 313aa070789SRoy Zang uint32_t eecd = 0; 314aa070789SRoy Zang 315aa070789SRoy Zang DEBUGFUNC(); 316aa070789SRoy Zang 317aa070789SRoy Zang if (hw->mac_type == e1000_ich8lan) 318472d5460SYork Sun return false; 319aa070789SRoy Zang 3202c2668f9SRoy Zang if (hw->mac_type == e1000_82573 || hw->mac_type == e1000_82574) { 321aa070789SRoy Zang eecd = E1000_READ_REG(hw, EECD); 322aa070789SRoy Zang 323aa070789SRoy Zang /* Isolate bits 15 & 16 */ 324aa070789SRoy Zang eecd = ((eecd >> 15) & 0x03); 325aa070789SRoy Zang 326aa070789SRoy Zang /* If both bits are set, device is Flash type */ 327aa070789SRoy Zang if (eecd == 0x03) 328472d5460SYork Sun return false; 329aa070789SRoy Zang } 330472d5460SYork Sun return true; 3312439e4bfSJean-Christophe PLAGNIOL-VILLARD } 3322439e4bfSJean-Christophe PLAGNIOL-VILLARD 3332439e4bfSJean-Christophe PLAGNIOL-VILLARD /****************************************************************************** 334aa070789SRoy Zang * Prepares EEPROM for access 3352439e4bfSJean-Christophe PLAGNIOL-VILLARD * 3362439e4bfSJean-Christophe PLAGNIOL-VILLARD * hw - Struct containing variables accessed by shared code 337aa070789SRoy Zang * 338aa070789SRoy Zang * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This 339aa070789SRoy Zang * function should be called before issuing a command to the EEPROM. 3402439e4bfSJean-Christophe PLAGNIOL-VILLARD *****************************************************************************/ 3412326a94dSKyle Moffett int32_t e1000_acquire_eeprom(struct e1000_hw *hw) 3422439e4bfSJean-Christophe PLAGNIOL-VILLARD { 343aa070789SRoy Zang struct e1000_eeprom_info *eeprom = &hw->eeprom; 344aa070789SRoy Zang uint32_t eecd, i = 0; 3452439e4bfSJean-Christophe PLAGNIOL-VILLARD 346f81ecb5dSTimur Tabi DEBUGFUNC(); 347aa070789SRoy Zang 348aa070789SRoy Zang if (e1000_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM)) 349aa070789SRoy Zang return -E1000_ERR_SWFW_SYNC; 350aa070789SRoy Zang eecd = E1000_READ_REG(hw, EECD); 351aa070789SRoy Zang 35295186063SMarek Vasut if (hw->mac_type != e1000_82573 && hw->mac_type != e1000_82574) { 3532439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Request EEPROM Access */ 3542439e4bfSJean-Christophe PLAGNIOL-VILLARD if (hw->mac_type > e1000_82544) { 3552439e4bfSJean-Christophe PLAGNIOL-VILLARD eecd |= E1000_EECD_REQ; 3562439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, EECD, eecd); 3572439e4bfSJean-Christophe PLAGNIOL-VILLARD eecd = E1000_READ_REG(hw, EECD); 358aa070789SRoy Zang while ((!(eecd & E1000_EECD_GNT)) && 359aa070789SRoy Zang (i < E1000_EEPROM_GRANT_ATTEMPTS)) { 3602439e4bfSJean-Christophe PLAGNIOL-VILLARD i++; 361aa070789SRoy Zang udelay(5); 3622439e4bfSJean-Christophe PLAGNIOL-VILLARD eecd = E1000_READ_REG(hw, EECD); 3632439e4bfSJean-Christophe PLAGNIOL-VILLARD } 3642439e4bfSJean-Christophe PLAGNIOL-VILLARD if (!(eecd & E1000_EECD_GNT)) { 3652439e4bfSJean-Christophe PLAGNIOL-VILLARD eecd &= ~E1000_EECD_REQ; 3662439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, EECD, eecd); 3672439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("Could not acquire EEPROM grant\n"); 3682439e4bfSJean-Christophe PLAGNIOL-VILLARD return -E1000_ERR_EEPROM; 3692439e4bfSJean-Christophe PLAGNIOL-VILLARD } 3702439e4bfSJean-Christophe PLAGNIOL-VILLARD } 371aa070789SRoy Zang } 3722439e4bfSJean-Christophe PLAGNIOL-VILLARD 373aa070789SRoy Zang /* Setup EEPROM for Read/Write */ 3742439e4bfSJean-Christophe PLAGNIOL-VILLARD 375aa070789SRoy Zang if (eeprom->type == e1000_eeprom_microwire) { 376aa070789SRoy Zang /* Clear SK and DI */ 377aa070789SRoy Zang eecd &= ~(E1000_EECD_DI | E1000_EECD_SK); 378aa070789SRoy Zang E1000_WRITE_REG(hw, EECD, eecd); 3792439e4bfSJean-Christophe PLAGNIOL-VILLARD 380aa070789SRoy Zang /* Set CS */ 381aa070789SRoy Zang eecd |= E1000_EECD_CS; 382aa070789SRoy Zang E1000_WRITE_REG(hw, EECD, eecd); 383aa070789SRoy Zang } else if (eeprom->type == e1000_eeprom_spi) { 384aa070789SRoy Zang /* Clear SK and CS */ 385aa070789SRoy Zang eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); 386aa070789SRoy Zang E1000_WRITE_REG(hw, EECD, eecd); 387aa070789SRoy Zang udelay(1); 388aa070789SRoy Zang } 3892439e4bfSJean-Christophe PLAGNIOL-VILLARD 390aa070789SRoy Zang return E1000_SUCCESS; 391aa070789SRoy Zang } 3922439e4bfSJean-Christophe PLAGNIOL-VILLARD 393aa070789SRoy Zang /****************************************************************************** 394aa070789SRoy Zang * Sets up eeprom variables in the hw struct. Must be called after mac_type 395aa070789SRoy Zang * is configured. Additionally, if this is ICH8, the flash controller GbE 396aa070789SRoy Zang * registers must be mapped, or this will crash. 397aa070789SRoy Zang * 398aa070789SRoy Zang * hw - Struct containing variables accessed by shared code 399aa070789SRoy Zang *****************************************************************************/ 400aa070789SRoy Zang static int32_t e1000_init_eeprom_params(struct e1000_hw *hw) 401aa070789SRoy Zang { 402aa070789SRoy Zang struct e1000_eeprom_info *eeprom = &hw->eeprom; 40395186063SMarek Vasut uint32_t eecd; 404aa070789SRoy Zang int32_t ret_val = E1000_SUCCESS; 405aa070789SRoy Zang uint16_t eeprom_size; 406aa070789SRoy Zang 40795186063SMarek Vasut if (hw->mac_type == e1000_igb) 40895186063SMarek Vasut eecd = E1000_READ_REG(hw, I210_EECD); 40995186063SMarek Vasut else 41095186063SMarek Vasut eecd = E1000_READ_REG(hw, EECD); 41195186063SMarek Vasut 412f81ecb5dSTimur Tabi DEBUGFUNC(); 413aa070789SRoy Zang 414aa070789SRoy Zang switch (hw->mac_type) { 415aa070789SRoy Zang case e1000_82542_rev2_0: 416aa070789SRoy Zang case e1000_82542_rev2_1: 417aa070789SRoy Zang case e1000_82543: 418aa070789SRoy Zang case e1000_82544: 419aa070789SRoy Zang eeprom->type = e1000_eeprom_microwire; 420aa070789SRoy Zang eeprom->word_size = 64; 421aa070789SRoy Zang eeprom->opcode_bits = 3; 422aa070789SRoy Zang eeprom->address_bits = 6; 423aa070789SRoy Zang eeprom->delay_usec = 50; 424472d5460SYork Sun eeprom->use_eerd = false; 425472d5460SYork Sun eeprom->use_eewr = false; 426aa070789SRoy Zang break; 427aa070789SRoy Zang case e1000_82540: 428aa070789SRoy Zang case e1000_82545: 429aa070789SRoy Zang case e1000_82545_rev_3: 430aa070789SRoy Zang case e1000_82546: 431aa070789SRoy Zang case e1000_82546_rev_3: 432aa070789SRoy Zang eeprom->type = e1000_eeprom_microwire; 433aa070789SRoy Zang eeprom->opcode_bits = 3; 434aa070789SRoy Zang eeprom->delay_usec = 50; 435aa070789SRoy Zang if (eecd & E1000_EECD_SIZE) { 436aa070789SRoy Zang eeprom->word_size = 256; 437aa070789SRoy Zang eeprom->address_bits = 8; 438aa070789SRoy Zang } else { 439aa070789SRoy Zang eeprom->word_size = 64; 440aa070789SRoy Zang eeprom->address_bits = 6; 441aa070789SRoy Zang } 442472d5460SYork Sun eeprom->use_eerd = false; 443472d5460SYork Sun eeprom->use_eewr = false; 444aa070789SRoy Zang break; 445aa070789SRoy Zang case e1000_82541: 446aa070789SRoy Zang case e1000_82541_rev_2: 447aa070789SRoy Zang case e1000_82547: 448aa070789SRoy Zang case e1000_82547_rev_2: 449aa070789SRoy Zang if (eecd & E1000_EECD_TYPE) { 450aa070789SRoy Zang eeprom->type = e1000_eeprom_spi; 451aa070789SRoy Zang eeprom->opcode_bits = 8; 452aa070789SRoy Zang eeprom->delay_usec = 1; 453aa070789SRoy Zang if (eecd & E1000_EECD_ADDR_BITS) { 454aa070789SRoy Zang eeprom->page_size = 32; 455aa070789SRoy Zang eeprom->address_bits = 16; 456aa070789SRoy Zang } else { 457aa070789SRoy Zang eeprom->page_size = 8; 458aa070789SRoy Zang eeprom->address_bits = 8; 459aa070789SRoy Zang } 460aa070789SRoy Zang } else { 461aa070789SRoy Zang eeprom->type = e1000_eeprom_microwire; 462aa070789SRoy Zang eeprom->opcode_bits = 3; 463aa070789SRoy Zang eeprom->delay_usec = 50; 464aa070789SRoy Zang if (eecd & E1000_EECD_ADDR_BITS) { 465aa070789SRoy Zang eeprom->word_size = 256; 466aa070789SRoy Zang eeprom->address_bits = 8; 467aa070789SRoy Zang } else { 468aa070789SRoy Zang eeprom->word_size = 64; 469aa070789SRoy Zang eeprom->address_bits = 6; 470aa070789SRoy Zang } 471aa070789SRoy Zang } 472472d5460SYork Sun eeprom->use_eerd = false; 473472d5460SYork Sun eeprom->use_eewr = false; 474aa070789SRoy Zang break; 475aa070789SRoy Zang case e1000_82571: 476aa070789SRoy Zang case e1000_82572: 477aa070789SRoy Zang eeprom->type = e1000_eeprom_spi; 478aa070789SRoy Zang eeprom->opcode_bits = 8; 479aa070789SRoy Zang eeprom->delay_usec = 1; 480aa070789SRoy Zang if (eecd & E1000_EECD_ADDR_BITS) { 481aa070789SRoy Zang eeprom->page_size = 32; 482aa070789SRoy Zang eeprom->address_bits = 16; 483aa070789SRoy Zang } else { 484aa070789SRoy Zang eeprom->page_size = 8; 485aa070789SRoy Zang eeprom->address_bits = 8; 486aa070789SRoy Zang } 487472d5460SYork Sun eeprom->use_eerd = false; 488472d5460SYork Sun eeprom->use_eewr = false; 489aa070789SRoy Zang break; 490aa070789SRoy Zang case e1000_82573: 4912c2668f9SRoy Zang case e1000_82574: 492aa070789SRoy Zang eeprom->type = e1000_eeprom_spi; 493aa070789SRoy Zang eeprom->opcode_bits = 8; 494aa070789SRoy Zang eeprom->delay_usec = 1; 495aa070789SRoy Zang if (eecd & E1000_EECD_ADDR_BITS) { 496aa070789SRoy Zang eeprom->page_size = 32; 497aa070789SRoy Zang eeprom->address_bits = 16; 498aa070789SRoy Zang } else { 499aa070789SRoy Zang eeprom->page_size = 8; 500aa070789SRoy Zang eeprom->address_bits = 8; 501aa070789SRoy Zang } 50295186063SMarek Vasut if (e1000_is_onboard_nvm_eeprom(hw) == false) { 503472d5460SYork Sun eeprom->use_eerd = true; 504472d5460SYork Sun eeprom->use_eewr = true; 50595186063SMarek Vasut 506aa070789SRoy Zang eeprom->type = e1000_eeprom_flash; 507aa070789SRoy Zang eeprom->word_size = 2048; 508aa070789SRoy Zang 509aa070789SRoy Zang /* Ensure that the Autonomous FLASH update bit is cleared due to 510aa070789SRoy Zang * Flash update issue on parts which use a FLASH for NVM. */ 511aa070789SRoy Zang eecd &= ~E1000_EECD_AUPDEN; 5122439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, EECD, eecd); 5132439e4bfSJean-Christophe PLAGNIOL-VILLARD } 514aa070789SRoy Zang break; 515aa070789SRoy Zang case e1000_80003es2lan: 516aa070789SRoy Zang eeprom->type = e1000_eeprom_spi; 517aa070789SRoy Zang eeprom->opcode_bits = 8; 518aa070789SRoy Zang eeprom->delay_usec = 1; 519aa070789SRoy Zang if (eecd & E1000_EECD_ADDR_BITS) { 520aa070789SRoy Zang eeprom->page_size = 32; 521aa070789SRoy Zang eeprom->address_bits = 16; 522aa070789SRoy Zang } else { 523aa070789SRoy Zang eeprom->page_size = 8; 524aa070789SRoy Zang eeprom->address_bits = 8; 5252439e4bfSJean-Christophe PLAGNIOL-VILLARD } 526472d5460SYork Sun eeprom->use_eerd = true; 527472d5460SYork Sun eeprom->use_eewr = false; 528aa070789SRoy Zang break; 52995186063SMarek Vasut case e1000_igb: 53095186063SMarek Vasut /* i210 has 4k of iNVM mapped as EEPROM */ 53195186063SMarek Vasut eeprom->type = e1000_eeprom_invm; 53295186063SMarek Vasut eeprom->opcode_bits = 8; 53395186063SMarek Vasut eeprom->delay_usec = 1; 53495186063SMarek Vasut eeprom->page_size = 32; 53595186063SMarek Vasut eeprom->address_bits = 16; 53695186063SMarek Vasut eeprom->use_eerd = true; 53795186063SMarek Vasut eeprom->use_eewr = false; 53895186063SMarek Vasut break; 5392439e4bfSJean-Christophe PLAGNIOL-VILLARD 540aa070789SRoy Zang /* ich8lan does not support currently. if needed, please 541aa070789SRoy Zang * add corresponding code and functions. 542aa070789SRoy Zang */ 5432439e4bfSJean-Christophe PLAGNIOL-VILLARD #if 0 544aa070789SRoy Zang case e1000_ich8lan: 5452439e4bfSJean-Christophe PLAGNIOL-VILLARD { 546aa070789SRoy Zang int32_t i = 0; 5472439e4bfSJean-Christophe PLAGNIOL-VILLARD 548aa070789SRoy Zang eeprom->type = e1000_eeprom_ich8; 549472d5460SYork Sun eeprom->use_eerd = false; 550472d5460SYork Sun eeprom->use_eewr = false; 551aa070789SRoy Zang eeprom->word_size = E1000_SHADOW_RAM_WORDS; 552aa070789SRoy Zang uint32_t flash_size = E1000_READ_ICH_FLASH_REG(hw, 553aa070789SRoy Zang ICH_FLASH_GFPREG); 554aa070789SRoy Zang /* Zero the shadow RAM structure. But don't load it from NVM 555aa070789SRoy Zang * so as to save time for driver init */ 556aa070789SRoy Zang if (hw->eeprom_shadow_ram != NULL) { 557aa070789SRoy Zang for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) { 558472d5460SYork Sun hw->eeprom_shadow_ram[i].modified = false; 559aa070789SRoy Zang hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF; 560aa070789SRoy Zang } 5612439e4bfSJean-Christophe PLAGNIOL-VILLARD } 5622439e4bfSJean-Christophe PLAGNIOL-VILLARD 563aa070789SRoy Zang hw->flash_base_addr = (flash_size & ICH_GFPREG_BASE_MASK) * 564aa070789SRoy Zang ICH_FLASH_SECTOR_SIZE; 5652439e4bfSJean-Christophe PLAGNIOL-VILLARD 566aa070789SRoy Zang hw->flash_bank_size = ((flash_size >> 16) 567aa070789SRoy Zang & ICH_GFPREG_BASE_MASK) + 1; 568aa070789SRoy Zang hw->flash_bank_size -= (flash_size & ICH_GFPREG_BASE_MASK); 5692439e4bfSJean-Christophe PLAGNIOL-VILLARD 570aa070789SRoy Zang hw->flash_bank_size *= ICH_FLASH_SECTOR_SIZE; 5712439e4bfSJean-Christophe PLAGNIOL-VILLARD 572aa070789SRoy Zang hw->flash_bank_size /= 2 * sizeof(uint16_t); 573aa070789SRoy Zang break; 5742439e4bfSJean-Christophe PLAGNIOL-VILLARD } 5752439e4bfSJean-Christophe PLAGNIOL-VILLARD #endif 576aa070789SRoy Zang default: 577aa070789SRoy Zang break; 578aa070789SRoy Zang } 579aa070789SRoy Zang 58095186063SMarek Vasut if (eeprom->type == e1000_eeprom_spi || 58195186063SMarek Vasut eeprom->type == e1000_eeprom_invm) { 582aa070789SRoy Zang /* eeprom_size will be an enum [0..8] that maps 583aa070789SRoy Zang * to eeprom sizes 128B to 584aa070789SRoy Zang * 32KB (incremented by powers of 2). 585aa070789SRoy Zang */ 586aa070789SRoy Zang if (hw->mac_type <= e1000_82547_rev_2) { 587aa070789SRoy Zang /* Set to default value for initial eeprom read. */ 588aa070789SRoy Zang eeprom->word_size = 64; 589aa070789SRoy Zang ret_val = e1000_read_eeprom(hw, EEPROM_CFG, 1, 590aa070789SRoy Zang &eeprom_size); 591aa070789SRoy Zang if (ret_val) 592aa070789SRoy Zang return ret_val; 593aa070789SRoy Zang eeprom_size = (eeprom_size & EEPROM_SIZE_MASK) 594aa070789SRoy Zang >> EEPROM_SIZE_SHIFT; 595aa070789SRoy Zang /* 256B eeprom size was not supported in earlier 596aa070789SRoy Zang * hardware, so we bump eeprom_size up one to 597aa070789SRoy Zang * ensure that "1" (which maps to 256B) is never 598aa070789SRoy Zang * the result used in the shifting logic below. */ 599aa070789SRoy Zang if (eeprom_size) 600aa070789SRoy Zang eeprom_size++; 601aa070789SRoy Zang } else { 602aa070789SRoy Zang eeprom_size = (uint16_t)((eecd & 603aa070789SRoy Zang E1000_EECD_SIZE_EX_MASK) >> 604aa070789SRoy Zang E1000_EECD_SIZE_EX_SHIFT); 605aa070789SRoy Zang } 606aa070789SRoy Zang 607aa070789SRoy Zang eeprom->word_size = 1 << (eeprom_size + EEPROM_WORD_SIZE_SHIFT); 608aa070789SRoy Zang } 609aa070789SRoy Zang return ret_val; 610aa070789SRoy Zang } 611aa070789SRoy Zang 612aa070789SRoy Zang /****************************************************************************** 613aa070789SRoy Zang * Polls the status bit (bit 1) of the EERD to determine when the read is done. 614aa070789SRoy Zang * 615aa070789SRoy Zang * hw - Struct containing variables accessed by shared code 616aa070789SRoy Zang *****************************************************************************/ 617aa070789SRoy Zang static int32_t 618aa070789SRoy Zang e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd) 619aa070789SRoy Zang { 620aa070789SRoy Zang uint32_t attempts = 100000; 621aa070789SRoy Zang uint32_t i, reg = 0; 622aa070789SRoy Zang int32_t done = E1000_ERR_EEPROM; 623aa070789SRoy Zang 624aa070789SRoy Zang for (i = 0; i < attempts; i++) { 62595186063SMarek Vasut if (eerd == E1000_EEPROM_POLL_READ) { 62695186063SMarek Vasut if (hw->mac_type == e1000_igb) 62795186063SMarek Vasut reg = E1000_READ_REG(hw, I210_EERD); 62895186063SMarek Vasut else 629aa070789SRoy Zang reg = E1000_READ_REG(hw, EERD); 63095186063SMarek Vasut } else { 63195186063SMarek Vasut if (hw->mac_type == e1000_igb) 63295186063SMarek Vasut reg = E1000_READ_REG(hw, I210_EEWR); 633aa070789SRoy Zang else 634aa070789SRoy Zang reg = E1000_READ_REG(hw, EEWR); 63595186063SMarek Vasut } 636aa070789SRoy Zang 637aa070789SRoy Zang if (reg & E1000_EEPROM_RW_REG_DONE) { 638aa070789SRoy Zang done = E1000_SUCCESS; 639aa070789SRoy Zang break; 640aa070789SRoy Zang } 641aa070789SRoy Zang udelay(5); 642aa070789SRoy Zang } 643aa070789SRoy Zang 644aa070789SRoy Zang return done; 645aa070789SRoy Zang } 646aa070789SRoy Zang 647aa070789SRoy Zang /****************************************************************************** 648aa070789SRoy Zang * Reads a 16 bit word from the EEPROM using the EERD register. 649aa070789SRoy Zang * 650aa070789SRoy Zang * hw - Struct containing variables accessed by shared code 651aa070789SRoy Zang * offset - offset of word in the EEPROM to read 652aa070789SRoy Zang * data - word read from the EEPROM 653aa070789SRoy Zang * words - number of words to read 654aa070789SRoy Zang *****************************************************************************/ 655aa070789SRoy Zang static int32_t 656aa070789SRoy Zang e1000_read_eeprom_eerd(struct e1000_hw *hw, 657aa070789SRoy Zang uint16_t offset, 658aa070789SRoy Zang uint16_t words, 659aa070789SRoy Zang uint16_t *data) 660aa070789SRoy Zang { 661aa070789SRoy Zang uint32_t i, eerd = 0; 662aa070789SRoy Zang int32_t error = 0; 663aa070789SRoy Zang 664aa070789SRoy Zang for (i = 0; i < words; i++) { 665aa070789SRoy Zang eerd = ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) + 666aa070789SRoy Zang E1000_EEPROM_RW_REG_START; 667aa070789SRoy Zang 66895186063SMarek Vasut if (hw->mac_type == e1000_igb) 66995186063SMarek Vasut E1000_WRITE_REG(hw, I210_EERD, eerd); 67095186063SMarek Vasut else 671aa070789SRoy Zang E1000_WRITE_REG(hw, EERD, eerd); 67295186063SMarek Vasut 673aa070789SRoy Zang error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_READ); 674aa070789SRoy Zang 675aa070789SRoy Zang if (error) 676aa070789SRoy Zang break; 67795186063SMarek Vasut 67895186063SMarek Vasut if (hw->mac_type == e1000_igb) { 67995186063SMarek Vasut data[i] = (E1000_READ_REG(hw, I210_EERD) >> 68095186063SMarek Vasut E1000_EEPROM_RW_REG_DATA); 68195186063SMarek Vasut } else { 682aa070789SRoy Zang data[i] = (E1000_READ_REG(hw, EERD) >> 683aa070789SRoy Zang E1000_EEPROM_RW_REG_DATA); 68495186063SMarek Vasut } 685aa070789SRoy Zang 686aa070789SRoy Zang } 687aa070789SRoy Zang 688aa070789SRoy Zang return error; 689aa070789SRoy Zang } 690aa070789SRoy Zang 6912326a94dSKyle Moffett void e1000_release_eeprom(struct e1000_hw *hw) 692aa070789SRoy Zang { 693aa070789SRoy Zang uint32_t eecd; 694aa070789SRoy Zang 695aa070789SRoy Zang DEBUGFUNC(); 696aa070789SRoy Zang 697aa070789SRoy Zang eecd = E1000_READ_REG(hw, EECD); 698aa070789SRoy Zang 699aa070789SRoy Zang if (hw->eeprom.type == e1000_eeprom_spi) { 700aa070789SRoy Zang eecd |= E1000_EECD_CS; /* Pull CS high */ 701aa070789SRoy Zang eecd &= ~E1000_EECD_SK; /* Lower SCK */ 702aa070789SRoy Zang 703aa070789SRoy Zang E1000_WRITE_REG(hw, EECD, eecd); 704aa070789SRoy Zang 705aa070789SRoy Zang udelay(hw->eeprom.delay_usec); 706aa070789SRoy Zang } else if (hw->eeprom.type == e1000_eeprom_microwire) { 707aa070789SRoy Zang /* cleanup eeprom */ 708aa070789SRoy Zang 709aa070789SRoy Zang /* CS on Microwire is active-high */ 710aa070789SRoy Zang eecd &= ~(E1000_EECD_CS | E1000_EECD_DI); 711aa070789SRoy Zang 712aa070789SRoy Zang E1000_WRITE_REG(hw, EECD, eecd); 713aa070789SRoy Zang 714aa070789SRoy Zang /* Rising edge of clock */ 715aa070789SRoy Zang eecd |= E1000_EECD_SK; 716aa070789SRoy Zang E1000_WRITE_REG(hw, EECD, eecd); 717aa070789SRoy Zang E1000_WRITE_FLUSH(hw); 718aa070789SRoy Zang udelay(hw->eeprom.delay_usec); 719aa070789SRoy Zang 720aa070789SRoy Zang /* Falling edge of clock */ 721aa070789SRoy Zang eecd &= ~E1000_EECD_SK; 722aa070789SRoy Zang E1000_WRITE_REG(hw, EECD, eecd); 723aa070789SRoy Zang E1000_WRITE_FLUSH(hw); 724aa070789SRoy Zang udelay(hw->eeprom.delay_usec); 725aa070789SRoy Zang } 726aa070789SRoy Zang 727aa070789SRoy Zang /* Stop requesting EEPROM access */ 728aa070789SRoy Zang if (hw->mac_type > e1000_82544) { 729aa070789SRoy Zang eecd &= ~E1000_EECD_REQ; 730aa070789SRoy Zang E1000_WRITE_REG(hw, EECD, eecd); 731aa070789SRoy Zang } 732aa070789SRoy Zang } 733aa070789SRoy Zang /****************************************************************************** 734aa070789SRoy Zang * Reads a 16 bit word from the EEPROM. 735aa070789SRoy Zang * 736aa070789SRoy Zang * hw - Struct containing variables accessed by shared code 737aa070789SRoy Zang *****************************************************************************/ 738aa070789SRoy Zang static int32_t 739aa070789SRoy Zang e1000_spi_eeprom_ready(struct e1000_hw *hw) 740aa070789SRoy Zang { 741aa070789SRoy Zang uint16_t retry_count = 0; 742aa070789SRoy Zang uint8_t spi_stat_reg; 743aa070789SRoy Zang 744aa070789SRoy Zang DEBUGFUNC(); 745aa070789SRoy Zang 746aa070789SRoy Zang /* Read "Status Register" repeatedly until the LSB is cleared. The 747aa070789SRoy Zang * EEPROM will signal that the command has been completed by clearing 748aa070789SRoy Zang * bit 0 of the internal status register. If it's not cleared within 749aa070789SRoy Zang * 5 milliseconds, then error out. 750aa070789SRoy Zang */ 751aa070789SRoy Zang retry_count = 0; 752aa070789SRoy Zang do { 753aa070789SRoy Zang e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI, 754aa070789SRoy Zang hw->eeprom.opcode_bits); 755aa070789SRoy Zang spi_stat_reg = (uint8_t)e1000_shift_in_ee_bits(hw, 8); 756aa070789SRoy Zang if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI)) 757aa070789SRoy Zang break; 758aa070789SRoy Zang 759aa070789SRoy Zang udelay(5); 760aa070789SRoy Zang retry_count += 5; 761aa070789SRoy Zang 762aa070789SRoy Zang e1000_standby_eeprom(hw); 763aa070789SRoy Zang } while (retry_count < EEPROM_MAX_RETRY_SPI); 764aa070789SRoy Zang 765aa070789SRoy Zang /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and 766aa070789SRoy Zang * only 0-5mSec on 5V devices) 767aa070789SRoy Zang */ 768aa070789SRoy Zang if (retry_count >= EEPROM_MAX_RETRY_SPI) { 769aa070789SRoy Zang DEBUGOUT("SPI EEPROM Status error\n"); 770aa070789SRoy Zang return -E1000_ERR_EEPROM; 771aa070789SRoy Zang } 772aa070789SRoy Zang 773aa070789SRoy Zang return E1000_SUCCESS; 774aa070789SRoy Zang } 775aa070789SRoy Zang 776aa070789SRoy Zang /****************************************************************************** 777aa070789SRoy Zang * Reads a 16 bit word from the EEPROM. 778aa070789SRoy Zang * 779aa070789SRoy Zang * hw - Struct containing variables accessed by shared code 780aa070789SRoy Zang * offset - offset of word in the EEPROM to read 781aa070789SRoy Zang * data - word read from the EEPROM 782aa070789SRoy Zang *****************************************************************************/ 783aa070789SRoy Zang static int32_t 784aa070789SRoy Zang e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset, 785aa070789SRoy Zang uint16_t words, uint16_t *data) 786aa070789SRoy Zang { 787aa070789SRoy Zang struct e1000_eeprom_info *eeprom = &hw->eeprom; 788aa070789SRoy Zang uint32_t i = 0; 789aa070789SRoy Zang 790aa070789SRoy Zang DEBUGFUNC(); 791aa070789SRoy Zang 792aa070789SRoy Zang /* If eeprom is not yet detected, do so now */ 793aa070789SRoy Zang if (eeprom->word_size == 0) 794aa070789SRoy Zang e1000_init_eeprom_params(hw); 795aa070789SRoy Zang 796aa070789SRoy Zang /* A check for invalid values: offset too large, too many words, 797aa070789SRoy Zang * and not enough words. 798aa070789SRoy Zang */ 799aa070789SRoy Zang if ((offset >= eeprom->word_size) || 800aa070789SRoy Zang (words > eeprom->word_size - offset) || 801aa070789SRoy Zang (words == 0)) { 802aa070789SRoy Zang DEBUGOUT("\"words\" parameter out of bounds." 803aa070789SRoy Zang "Words = %d, size = %d\n", offset, eeprom->word_size); 804aa070789SRoy Zang return -E1000_ERR_EEPROM; 805aa070789SRoy Zang } 806aa070789SRoy Zang 807aa070789SRoy Zang /* EEPROM's that don't use EERD to read require us to bit-bang the SPI 808aa070789SRoy Zang * directly. In this case, we need to acquire the EEPROM so that 809aa070789SRoy Zang * FW or other port software does not interrupt. 810aa070789SRoy Zang */ 811472d5460SYork Sun if (e1000_is_onboard_nvm_eeprom(hw) == true && 812472d5460SYork Sun hw->eeprom.use_eerd == false) { 813aa070789SRoy Zang 814aa070789SRoy Zang /* Prepare the EEPROM for bit-bang reading */ 815aa070789SRoy Zang if (e1000_acquire_eeprom(hw) != E1000_SUCCESS) 816aa070789SRoy Zang return -E1000_ERR_EEPROM; 817aa070789SRoy Zang } 818aa070789SRoy Zang 819aa070789SRoy Zang /* Eerd register EEPROM access requires no eeprom aquire/release */ 820472d5460SYork Sun if (eeprom->use_eerd == true) 821aa070789SRoy Zang return e1000_read_eeprom_eerd(hw, offset, words, data); 822aa070789SRoy Zang 823aa070789SRoy Zang /* ich8lan does not support currently. if needed, please 824aa070789SRoy Zang * add corresponding code and functions. 825aa070789SRoy Zang */ 826aa070789SRoy Zang #if 0 827aa070789SRoy Zang /* ICH EEPROM access is done via the ICH flash controller */ 828aa070789SRoy Zang if (eeprom->type == e1000_eeprom_ich8) 829aa070789SRoy Zang return e1000_read_eeprom_ich8(hw, offset, words, data); 830aa070789SRoy Zang #endif 831aa070789SRoy Zang /* Set up the SPI or Microwire EEPROM for bit-bang reading. We have 832aa070789SRoy Zang * acquired the EEPROM at this point, so any returns should relase it */ 833aa070789SRoy Zang if (eeprom->type == e1000_eeprom_spi) { 834aa070789SRoy Zang uint16_t word_in; 835aa070789SRoy Zang uint8_t read_opcode = EEPROM_READ_OPCODE_SPI; 836aa070789SRoy Zang 837aa070789SRoy Zang if (e1000_spi_eeprom_ready(hw)) { 838aa070789SRoy Zang e1000_release_eeprom(hw); 839aa070789SRoy Zang return -E1000_ERR_EEPROM; 840aa070789SRoy Zang } 841aa070789SRoy Zang 842aa070789SRoy Zang e1000_standby_eeprom(hw); 843aa070789SRoy Zang 844aa070789SRoy Zang /* Some SPI eeproms use the 8th address bit embedded in 845aa070789SRoy Zang * the opcode */ 846aa070789SRoy Zang if ((eeprom->address_bits == 8) && (offset >= 128)) 847aa070789SRoy Zang read_opcode |= EEPROM_A8_OPCODE_SPI; 848aa070789SRoy Zang 849aa070789SRoy Zang /* Send the READ command (opcode + addr) */ 850aa070789SRoy Zang e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits); 851aa070789SRoy Zang e1000_shift_out_ee_bits(hw, (uint16_t)(offset*2), 852aa070789SRoy Zang eeprom->address_bits); 853aa070789SRoy Zang 854aa070789SRoy Zang /* Read the data. The address of the eeprom internally 855aa070789SRoy Zang * increments with each byte (spi) being read, saving on the 856aa070789SRoy Zang * overhead of eeprom setup and tear-down. The address 857aa070789SRoy Zang * counter will roll over if reading beyond the size of 858aa070789SRoy Zang * the eeprom, thus allowing the entire memory to be read 859aa070789SRoy Zang * starting from any offset. */ 860aa070789SRoy Zang for (i = 0; i < words; i++) { 861aa070789SRoy Zang word_in = e1000_shift_in_ee_bits(hw, 16); 862aa070789SRoy Zang data[i] = (word_in >> 8) | (word_in << 8); 863aa070789SRoy Zang } 864aa070789SRoy Zang } else if (eeprom->type == e1000_eeprom_microwire) { 865aa070789SRoy Zang for (i = 0; i < words; i++) { 866aa070789SRoy Zang /* Send the READ command (opcode + addr) */ 867aa070789SRoy Zang e1000_shift_out_ee_bits(hw, 868aa070789SRoy Zang EEPROM_READ_OPCODE_MICROWIRE, 869aa070789SRoy Zang eeprom->opcode_bits); 870aa070789SRoy Zang e1000_shift_out_ee_bits(hw, (uint16_t)(offset + i), 871aa070789SRoy Zang eeprom->address_bits); 872aa070789SRoy Zang 873aa070789SRoy Zang /* Read the data. For microwire, each word requires 874aa070789SRoy Zang * the overhead of eeprom setup and tear-down. */ 875aa070789SRoy Zang data[i] = e1000_shift_in_ee_bits(hw, 16); 876aa070789SRoy Zang e1000_standby_eeprom(hw); 877aa070789SRoy Zang } 878aa070789SRoy Zang } 879aa070789SRoy Zang 880aa070789SRoy Zang /* End this read operation */ 881aa070789SRoy Zang e1000_release_eeprom(hw); 882aa070789SRoy Zang 883aa070789SRoy Zang return E1000_SUCCESS; 884aa070789SRoy Zang } 8852439e4bfSJean-Christophe PLAGNIOL-VILLARD 8862439e4bfSJean-Christophe PLAGNIOL-VILLARD /****************************************************************************** 8872439e4bfSJean-Christophe PLAGNIOL-VILLARD * Verifies that the EEPROM has a valid checksum 8882439e4bfSJean-Christophe PLAGNIOL-VILLARD * 8892439e4bfSJean-Christophe PLAGNIOL-VILLARD * hw - Struct containing variables accessed by shared code 8902439e4bfSJean-Christophe PLAGNIOL-VILLARD * 8912439e4bfSJean-Christophe PLAGNIOL-VILLARD * Reads the first 64 16 bit words of the EEPROM and sums the values read. 8922439e4bfSJean-Christophe PLAGNIOL-VILLARD * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is 8932439e4bfSJean-Christophe PLAGNIOL-VILLARD * valid. 8942439e4bfSJean-Christophe PLAGNIOL-VILLARD *****************************************************************************/ 895114d7fc0SKyle Moffett static int e1000_validate_eeprom_checksum(struct e1000_hw *hw) 8962439e4bfSJean-Christophe PLAGNIOL-VILLARD { 897114d7fc0SKyle Moffett uint16_t i, checksum, checksum_reg, *buf; 8982439e4bfSJean-Christophe PLAGNIOL-VILLARD 8992439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGFUNC(); 9002439e4bfSJean-Christophe PLAGNIOL-VILLARD 901114d7fc0SKyle Moffett /* Allocate a temporary buffer */ 902114d7fc0SKyle Moffett buf = malloc(sizeof(buf[0]) * (EEPROM_CHECKSUM_REG + 1)); 903114d7fc0SKyle Moffett if (!buf) { 904114d7fc0SKyle Moffett E1000_ERR(hw->nic, "Unable to allocate EEPROM buffer!\n"); 9052439e4bfSJean-Christophe PLAGNIOL-VILLARD return -E1000_ERR_EEPROM; 9062439e4bfSJean-Christophe PLAGNIOL-VILLARD } 9072439e4bfSJean-Christophe PLAGNIOL-VILLARD 908114d7fc0SKyle Moffett /* Read the EEPROM */ 909114d7fc0SKyle Moffett if (e1000_read_eeprom(hw, 0, EEPROM_CHECKSUM_REG + 1, buf) < 0) { 910114d7fc0SKyle Moffett E1000_ERR(hw->nic, "Unable to read EEPROM!\n"); 9112439e4bfSJean-Christophe PLAGNIOL-VILLARD return -E1000_ERR_EEPROM; 9122439e4bfSJean-Christophe PLAGNIOL-VILLARD } 913114d7fc0SKyle Moffett 914114d7fc0SKyle Moffett /* Compute the checksum */ 9157a341066SWolfgang Denk checksum = 0; 916114d7fc0SKyle Moffett for (i = 0; i < EEPROM_CHECKSUM_REG; i++) 917114d7fc0SKyle Moffett checksum += buf[i]; 918114d7fc0SKyle Moffett checksum = ((uint16_t)EEPROM_SUM) - checksum; 919114d7fc0SKyle Moffett checksum_reg = buf[i]; 920114d7fc0SKyle Moffett 921114d7fc0SKyle Moffett /* Verify it! */ 922114d7fc0SKyle Moffett if (checksum == checksum_reg) 923114d7fc0SKyle Moffett return 0; 924114d7fc0SKyle Moffett 925114d7fc0SKyle Moffett /* Hrm, verification failed, print an error */ 926114d7fc0SKyle Moffett E1000_ERR(hw->nic, "EEPROM checksum is incorrect!\n"); 927114d7fc0SKyle Moffett E1000_ERR(hw->nic, " ...register was 0x%04hx, calculated 0x%04hx\n", 928114d7fc0SKyle Moffett checksum_reg, checksum); 929114d7fc0SKyle Moffett 930114d7fc0SKyle Moffett return -E1000_ERR_EEPROM; 9312439e4bfSJean-Christophe PLAGNIOL-VILLARD } 9328712adfdSRojhalat Ibrahim #endif /* CONFIG_E1000_NO_NVM */ 933ecbd2078SRoy Zang 934ecbd2078SRoy Zang /***************************************************************************** 935ecbd2078SRoy Zang * Set PHY to class A mode 936ecbd2078SRoy Zang * Assumes the following operations will follow to enable the new class mode. 937ecbd2078SRoy Zang * 1. Do a PHY soft reset 938ecbd2078SRoy Zang * 2. Restart auto-negotiation or force link. 939ecbd2078SRoy Zang * 940ecbd2078SRoy Zang * hw - Struct containing variables accessed by shared code 941ecbd2078SRoy Zang ****************************************************************************/ 942ecbd2078SRoy Zang static int32_t 943ecbd2078SRoy Zang e1000_set_phy_mode(struct e1000_hw *hw) 944ecbd2078SRoy Zang { 9458712adfdSRojhalat Ibrahim #ifndef CONFIG_E1000_NO_NVM 946ecbd2078SRoy Zang int32_t ret_val; 947ecbd2078SRoy Zang uint16_t eeprom_data; 948ecbd2078SRoy Zang 949ecbd2078SRoy Zang DEBUGFUNC(); 950ecbd2078SRoy Zang 951ecbd2078SRoy Zang if ((hw->mac_type == e1000_82545_rev_3) && 952ecbd2078SRoy Zang (hw->media_type == e1000_media_type_copper)) { 953ecbd2078SRoy Zang ret_val = e1000_read_eeprom(hw, EEPROM_PHY_CLASS_WORD, 954ecbd2078SRoy Zang 1, &eeprom_data); 955ecbd2078SRoy Zang if (ret_val) 956ecbd2078SRoy Zang return ret_val; 957ecbd2078SRoy Zang 958ecbd2078SRoy Zang if ((eeprom_data != EEPROM_RESERVED_WORD) && 959ecbd2078SRoy Zang (eeprom_data & EEPROM_PHY_CLASS_A)) { 960ecbd2078SRoy Zang ret_val = e1000_write_phy_reg(hw, 961ecbd2078SRoy Zang M88E1000_PHY_PAGE_SELECT, 0x000B); 962ecbd2078SRoy Zang if (ret_val) 963ecbd2078SRoy Zang return ret_val; 964ecbd2078SRoy Zang ret_val = e1000_write_phy_reg(hw, 965ecbd2078SRoy Zang M88E1000_PHY_GEN_CONTROL, 0x8104); 966ecbd2078SRoy Zang if (ret_val) 967ecbd2078SRoy Zang return ret_val; 968ecbd2078SRoy Zang 969472d5460SYork Sun hw->phy_reset_disable = false; 970ecbd2078SRoy Zang } 971ecbd2078SRoy Zang } 9728712adfdSRojhalat Ibrahim #endif 973ecbd2078SRoy Zang return E1000_SUCCESS; 974ecbd2078SRoy Zang } 9752439e4bfSJean-Christophe PLAGNIOL-VILLARD 9768712adfdSRojhalat Ibrahim #ifndef CONFIG_E1000_NO_NVM 977aa070789SRoy Zang /*************************************************************************** 978aa070789SRoy Zang * 979aa070789SRoy Zang * Obtaining software semaphore bit (SMBI) before resetting PHY. 980aa070789SRoy Zang * 981aa070789SRoy Zang * hw: Struct containing variables accessed by shared code 982aa070789SRoy Zang * 983aa070789SRoy Zang * returns: - E1000_ERR_RESET if fail to obtain semaphore. 984aa070789SRoy Zang * E1000_SUCCESS at any other case. 985aa070789SRoy Zang * 986aa070789SRoy Zang ***************************************************************************/ 987aa070789SRoy Zang static int32_t 988aa070789SRoy Zang e1000_get_software_semaphore(struct e1000_hw *hw) 989aa070789SRoy Zang { 990aa070789SRoy Zang int32_t timeout = hw->eeprom.word_size + 1; 991aa070789SRoy Zang uint32_t swsm; 992aa070789SRoy Zang 993aa070789SRoy Zang DEBUGFUNC(); 994aa070789SRoy Zang 99595186063SMarek Vasut swsm = E1000_READ_REG(hw, SWSM); 99695186063SMarek Vasut swsm &= ~E1000_SWSM_SMBI; 99795186063SMarek Vasut E1000_WRITE_REG(hw, SWSM, swsm); 99895186063SMarek Vasut 999aa070789SRoy Zang if (hw->mac_type != e1000_80003es2lan) 1000aa070789SRoy Zang return E1000_SUCCESS; 1001aa070789SRoy Zang 1002aa070789SRoy Zang while (timeout) { 1003aa070789SRoy Zang swsm = E1000_READ_REG(hw, SWSM); 1004aa070789SRoy Zang /* If SMBI bit cleared, it is now set and we hold 1005aa070789SRoy Zang * the semaphore */ 1006aa070789SRoy Zang if (!(swsm & E1000_SWSM_SMBI)) 1007aa070789SRoy Zang break; 1008aa070789SRoy Zang mdelay(1); 1009aa070789SRoy Zang timeout--; 1010aa070789SRoy Zang } 1011aa070789SRoy Zang 1012aa070789SRoy Zang if (!timeout) { 1013aa070789SRoy Zang DEBUGOUT("Driver can't access device - SMBI bit is set.\n"); 1014aa070789SRoy Zang return -E1000_ERR_RESET; 1015aa070789SRoy Zang } 1016aa070789SRoy Zang 1017aa070789SRoy Zang return E1000_SUCCESS; 1018aa070789SRoy Zang } 10198712adfdSRojhalat Ibrahim #endif 1020aa070789SRoy Zang 1021aa070789SRoy Zang /*************************************************************************** 1022aa070789SRoy Zang * This function clears HW semaphore bits. 1023aa070789SRoy Zang * 1024aa070789SRoy Zang * hw: Struct containing variables accessed by shared code 1025aa070789SRoy Zang * 1026aa070789SRoy Zang * returns: - None. 1027aa070789SRoy Zang * 1028aa070789SRoy Zang ***************************************************************************/ 1029aa070789SRoy Zang static void 1030aa070789SRoy Zang e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw) 1031aa070789SRoy Zang { 10328712adfdSRojhalat Ibrahim #ifndef CONFIG_E1000_NO_NVM 1033aa070789SRoy Zang uint32_t swsm; 1034aa070789SRoy Zang 1035aa070789SRoy Zang DEBUGFUNC(); 1036aa070789SRoy Zang 1037aa070789SRoy Zang if (!hw->eeprom_semaphore_present) 1038aa070789SRoy Zang return; 1039aa070789SRoy Zang 1040aa070789SRoy Zang swsm = E1000_READ_REG(hw, SWSM); 1041aa070789SRoy Zang if (hw->mac_type == e1000_80003es2lan) { 1042aa070789SRoy Zang /* Release both semaphores. */ 1043aa070789SRoy Zang swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI); 1044aa070789SRoy Zang } else 1045aa070789SRoy Zang swsm &= ~(E1000_SWSM_SWESMBI); 1046aa070789SRoy Zang E1000_WRITE_REG(hw, SWSM, swsm); 10478712adfdSRojhalat Ibrahim #endif 1048aa070789SRoy Zang } 1049aa070789SRoy Zang 1050aa070789SRoy Zang /*************************************************************************** 1051aa070789SRoy Zang * 1052aa070789SRoy Zang * Using the combination of SMBI and SWESMBI semaphore bits when resetting 1053aa070789SRoy Zang * adapter or Eeprom access. 1054aa070789SRoy Zang * 1055aa070789SRoy Zang * hw: Struct containing variables accessed by shared code 1056aa070789SRoy Zang * 1057aa070789SRoy Zang * returns: - E1000_ERR_EEPROM if fail to access EEPROM. 1058aa070789SRoy Zang * E1000_SUCCESS at any other case. 1059aa070789SRoy Zang * 1060aa070789SRoy Zang ***************************************************************************/ 1061aa070789SRoy Zang static int32_t 1062aa070789SRoy Zang e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw) 1063aa070789SRoy Zang { 10648712adfdSRojhalat Ibrahim #ifndef CONFIG_E1000_NO_NVM 1065aa070789SRoy Zang int32_t timeout; 1066aa070789SRoy Zang uint32_t swsm; 1067aa070789SRoy Zang 1068aa070789SRoy Zang DEBUGFUNC(); 1069aa070789SRoy Zang 1070aa070789SRoy Zang if (!hw->eeprom_semaphore_present) 1071aa070789SRoy Zang return E1000_SUCCESS; 1072aa070789SRoy Zang 1073aa070789SRoy Zang if (hw->mac_type == e1000_80003es2lan) { 1074aa070789SRoy Zang /* Get the SW semaphore. */ 1075aa070789SRoy Zang if (e1000_get_software_semaphore(hw) != E1000_SUCCESS) 1076aa070789SRoy Zang return -E1000_ERR_EEPROM; 1077aa070789SRoy Zang } 1078aa070789SRoy Zang 1079aa070789SRoy Zang /* Get the FW semaphore. */ 1080aa070789SRoy Zang timeout = hw->eeprom.word_size + 1; 1081aa070789SRoy Zang while (timeout) { 1082aa070789SRoy Zang swsm = E1000_READ_REG(hw, SWSM); 1083aa070789SRoy Zang swsm |= E1000_SWSM_SWESMBI; 1084aa070789SRoy Zang E1000_WRITE_REG(hw, SWSM, swsm); 1085aa070789SRoy Zang /* if we managed to set the bit we got the semaphore. */ 1086aa070789SRoy Zang swsm = E1000_READ_REG(hw, SWSM); 1087aa070789SRoy Zang if (swsm & E1000_SWSM_SWESMBI) 1088aa070789SRoy Zang break; 1089aa070789SRoy Zang 1090aa070789SRoy Zang udelay(50); 1091aa070789SRoy Zang timeout--; 1092aa070789SRoy Zang } 1093aa070789SRoy Zang 1094aa070789SRoy Zang if (!timeout) { 1095aa070789SRoy Zang /* Release semaphores */ 1096aa070789SRoy Zang e1000_put_hw_eeprom_semaphore(hw); 1097aa070789SRoy Zang DEBUGOUT("Driver can't access the Eeprom - " 1098aa070789SRoy Zang "SWESMBI bit is set.\n"); 1099aa070789SRoy Zang return -E1000_ERR_EEPROM; 1100aa070789SRoy Zang } 11018712adfdSRojhalat Ibrahim #endif 1102aa070789SRoy Zang return E1000_SUCCESS; 1103aa070789SRoy Zang } 1104aa070789SRoy Zang 1105aa070789SRoy Zang static int32_t 1106aa070789SRoy Zang e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask) 1107aa070789SRoy Zang { 1108aa070789SRoy Zang uint32_t swfw_sync = 0; 1109aa070789SRoy Zang uint32_t swmask = mask; 1110aa070789SRoy Zang uint32_t fwmask = mask << 16; 1111aa070789SRoy Zang int32_t timeout = 200; 1112aa070789SRoy Zang 1113aa070789SRoy Zang DEBUGFUNC(); 1114aa070789SRoy Zang while (timeout) { 1115aa070789SRoy Zang if (e1000_get_hw_eeprom_semaphore(hw)) 1116aa070789SRoy Zang return -E1000_ERR_SWFW_SYNC; 1117aa070789SRoy Zang 111817da7120SMarcel Ziswiler if (hw->mac_type == e1000_igb) 111917da7120SMarcel Ziswiler swfw_sync = E1000_READ_REG(hw, I210_SW_FW_SYNC); 112017da7120SMarcel Ziswiler else 1121aa070789SRoy Zang swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC); 112276f8cdb2SYork Sun if (!(swfw_sync & (fwmask | swmask))) 1123aa070789SRoy Zang break; 1124aa070789SRoy Zang 1125aa070789SRoy Zang /* firmware currently using resource (fwmask) */ 1126aa070789SRoy Zang /* or other software thread currently using resource (swmask) */ 1127aa070789SRoy Zang e1000_put_hw_eeprom_semaphore(hw); 1128aa070789SRoy Zang mdelay(5); 1129aa070789SRoy Zang timeout--; 1130aa070789SRoy Zang } 1131aa070789SRoy Zang 1132aa070789SRoy Zang if (!timeout) { 1133aa070789SRoy Zang DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n"); 1134aa070789SRoy Zang return -E1000_ERR_SWFW_SYNC; 1135aa070789SRoy Zang } 1136aa070789SRoy Zang 1137aa070789SRoy Zang swfw_sync |= swmask; 1138aa070789SRoy Zang E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync); 1139aa070789SRoy Zang 1140aa070789SRoy Zang e1000_put_hw_eeprom_semaphore(hw); 1141aa070789SRoy Zang return E1000_SUCCESS; 1142aa070789SRoy Zang } 1143aa070789SRoy Zang 1144472d5460SYork Sun static bool e1000_is_second_port(struct e1000_hw *hw) 1145987b43a1SKyle Moffett { 1146987b43a1SKyle Moffett switch (hw->mac_type) { 1147987b43a1SKyle Moffett case e1000_80003es2lan: 1148987b43a1SKyle Moffett case e1000_82546: 1149987b43a1SKyle Moffett case e1000_82571: 1150987b43a1SKyle Moffett if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1) 1151472d5460SYork Sun return true; 1152987b43a1SKyle Moffett /* Fallthrough */ 1153987b43a1SKyle Moffett default: 1154472d5460SYork Sun return false; 1155987b43a1SKyle Moffett } 1156987b43a1SKyle Moffett } 1157987b43a1SKyle Moffett 11588712adfdSRojhalat Ibrahim #ifndef CONFIG_E1000_NO_NVM 11592439e4bfSJean-Christophe PLAGNIOL-VILLARD /****************************************************************************** 11602439e4bfSJean-Christophe PLAGNIOL-VILLARD * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the 11612439e4bfSJean-Christophe PLAGNIOL-VILLARD * second function of dual function devices 11622439e4bfSJean-Christophe PLAGNIOL-VILLARD * 11632439e4bfSJean-Christophe PLAGNIOL-VILLARD * nic - Struct containing variables accessed by shared code 11642439e4bfSJean-Christophe PLAGNIOL-VILLARD *****************************************************************************/ 11652439e4bfSJean-Christophe PLAGNIOL-VILLARD static int 11662439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_read_mac_addr(struct eth_device *nic) 11672439e4bfSJean-Christophe PLAGNIOL-VILLARD { 11682439e4bfSJean-Christophe PLAGNIOL-VILLARD struct e1000_hw *hw = nic->priv; 11692439e4bfSJean-Christophe PLAGNIOL-VILLARD uint16_t offset; 11702439e4bfSJean-Christophe PLAGNIOL-VILLARD uint16_t eeprom_data; 117195186063SMarek Vasut uint32_t reg_data = 0; 11722439e4bfSJean-Christophe PLAGNIOL-VILLARD int i; 11732439e4bfSJean-Christophe PLAGNIOL-VILLARD 11742439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGFUNC(); 11752439e4bfSJean-Christophe PLAGNIOL-VILLARD 11762439e4bfSJean-Christophe PLAGNIOL-VILLARD for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) { 11772439e4bfSJean-Christophe PLAGNIOL-VILLARD offset = i >> 1; 117895186063SMarek Vasut if (hw->mac_type == e1000_igb) { 117995186063SMarek Vasut /* i210 preloads MAC address into RAL/RAH registers */ 118095186063SMarek Vasut if (offset == 0) 118195186063SMarek Vasut reg_data = E1000_READ_REG_ARRAY(hw, RA, 0); 118295186063SMarek Vasut else if (offset == 1) 118395186063SMarek Vasut reg_data >>= 16; 118495186063SMarek Vasut else if (offset == 2) 118595186063SMarek Vasut reg_data = E1000_READ_REG_ARRAY(hw, RA, 1); 118695186063SMarek Vasut eeprom_data = reg_data & 0xffff; 118795186063SMarek Vasut } else if (e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) { 11882439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("EEPROM Read Error\n"); 11892439e4bfSJean-Christophe PLAGNIOL-VILLARD return -E1000_ERR_EEPROM; 11902439e4bfSJean-Christophe PLAGNIOL-VILLARD } 11912439e4bfSJean-Christophe PLAGNIOL-VILLARD nic->enetaddr[i] = eeprom_data & 0xff; 11922439e4bfSJean-Christophe PLAGNIOL-VILLARD nic->enetaddr[i + 1] = (eeprom_data >> 8) & 0xff; 11932439e4bfSJean-Christophe PLAGNIOL-VILLARD } 1194987b43a1SKyle Moffett 11952439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Invert the last bit if this is the second device */ 1196987b43a1SKyle Moffett if (e1000_is_second_port(hw)) 1197987b43a1SKyle Moffett nic->enetaddr[5] ^= 1; 1198987b43a1SKyle Moffett 1199ac3315c2SAndre Schwarz #ifdef CONFIG_E1000_FALLBACK_MAC 120040867a2fSAnatolij Gustschin if (!is_valid_ether_addr(nic->enetaddr)) { 1201f2302d44SStefan Roese unsigned char fb_mac[NODE_ADDRESS_SIZE] = CONFIG_E1000_FALLBACK_MAC; 1202f2302d44SStefan Roese 1203f2302d44SStefan Roese memcpy (nic->enetaddr, fb_mac, NODE_ADDRESS_SIZE); 1204f2302d44SStefan Roese } 1205ac3315c2SAndre Schwarz #endif 12062439e4bfSJean-Christophe PLAGNIOL-VILLARD return 0; 12072439e4bfSJean-Christophe PLAGNIOL-VILLARD } 12088712adfdSRojhalat Ibrahim #endif 12092439e4bfSJean-Christophe PLAGNIOL-VILLARD 12102439e4bfSJean-Christophe PLAGNIOL-VILLARD /****************************************************************************** 12112439e4bfSJean-Christophe PLAGNIOL-VILLARD * Initializes receive address filters. 12122439e4bfSJean-Christophe PLAGNIOL-VILLARD * 12132439e4bfSJean-Christophe PLAGNIOL-VILLARD * hw - Struct containing variables accessed by shared code 12142439e4bfSJean-Christophe PLAGNIOL-VILLARD * 12152439e4bfSJean-Christophe PLAGNIOL-VILLARD * Places the MAC address in receive address register 0 and clears the rest 12162439e4bfSJean-Christophe PLAGNIOL-VILLARD * of the receive addresss registers. Clears the multicast table. Assumes 12172439e4bfSJean-Christophe PLAGNIOL-VILLARD * the receiver is in reset when the routine is called. 12182439e4bfSJean-Christophe PLAGNIOL-VILLARD *****************************************************************************/ 12192439e4bfSJean-Christophe PLAGNIOL-VILLARD static void 12202439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_init_rx_addrs(struct eth_device *nic) 12212439e4bfSJean-Christophe PLAGNIOL-VILLARD { 12222439e4bfSJean-Christophe PLAGNIOL-VILLARD struct e1000_hw *hw = nic->priv; 12232439e4bfSJean-Christophe PLAGNIOL-VILLARD uint32_t i; 12242439e4bfSJean-Christophe PLAGNIOL-VILLARD uint32_t addr_low; 12252439e4bfSJean-Christophe PLAGNIOL-VILLARD uint32_t addr_high; 12262439e4bfSJean-Christophe PLAGNIOL-VILLARD 12272439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGFUNC(); 12282439e4bfSJean-Christophe PLAGNIOL-VILLARD 12292439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Setup the receive address. */ 12302439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("Programming MAC Address into RAR[0]\n"); 12312439e4bfSJean-Christophe PLAGNIOL-VILLARD addr_low = (nic->enetaddr[0] | 12322439e4bfSJean-Christophe PLAGNIOL-VILLARD (nic->enetaddr[1] << 8) | 12332439e4bfSJean-Christophe PLAGNIOL-VILLARD (nic->enetaddr[2] << 16) | (nic->enetaddr[3] << 24)); 12342439e4bfSJean-Christophe PLAGNIOL-VILLARD 12352439e4bfSJean-Christophe PLAGNIOL-VILLARD addr_high = (nic->enetaddr[4] | (nic->enetaddr[5] << 8) | E1000_RAH_AV); 12362439e4bfSJean-Christophe PLAGNIOL-VILLARD 12372439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG_ARRAY(hw, RA, 0, addr_low); 12382439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG_ARRAY(hw, RA, 1, addr_high); 12392439e4bfSJean-Christophe PLAGNIOL-VILLARD 12402439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Zero out the other 15 receive addresses. */ 12412439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("Clearing RAR[1-15]\n"); 12422439e4bfSJean-Christophe PLAGNIOL-VILLARD for (i = 1; i < E1000_RAR_ENTRIES; i++) { 12432439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0); 12442439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0); 12452439e4bfSJean-Christophe PLAGNIOL-VILLARD } 12462439e4bfSJean-Christophe PLAGNIOL-VILLARD } 12472439e4bfSJean-Christophe PLAGNIOL-VILLARD 12482439e4bfSJean-Christophe PLAGNIOL-VILLARD /****************************************************************************** 12492439e4bfSJean-Christophe PLAGNIOL-VILLARD * Clears the VLAN filer table 12502439e4bfSJean-Christophe PLAGNIOL-VILLARD * 12512439e4bfSJean-Christophe PLAGNIOL-VILLARD * hw - Struct containing variables accessed by shared code 12522439e4bfSJean-Christophe PLAGNIOL-VILLARD *****************************************************************************/ 12532439e4bfSJean-Christophe PLAGNIOL-VILLARD static void 12542439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_clear_vfta(struct e1000_hw *hw) 12552439e4bfSJean-Christophe PLAGNIOL-VILLARD { 12562439e4bfSJean-Christophe PLAGNIOL-VILLARD uint32_t offset; 12572439e4bfSJean-Christophe PLAGNIOL-VILLARD 12582439e4bfSJean-Christophe PLAGNIOL-VILLARD for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) 12592439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG_ARRAY(hw, VFTA, offset, 0); 12602439e4bfSJean-Christophe PLAGNIOL-VILLARD } 12612439e4bfSJean-Christophe PLAGNIOL-VILLARD 12622439e4bfSJean-Christophe PLAGNIOL-VILLARD /****************************************************************************** 12632439e4bfSJean-Christophe PLAGNIOL-VILLARD * Set the mac type member in the hw struct. 12642439e4bfSJean-Christophe PLAGNIOL-VILLARD * 12652439e4bfSJean-Christophe PLAGNIOL-VILLARD * hw - Struct containing variables accessed by shared code 12662439e4bfSJean-Christophe PLAGNIOL-VILLARD *****************************************************************************/ 1267aa070789SRoy Zang int32_t 12682439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_set_mac_type(struct e1000_hw *hw) 12692439e4bfSJean-Christophe PLAGNIOL-VILLARD { 12702439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGFUNC(); 12712439e4bfSJean-Christophe PLAGNIOL-VILLARD 12722439e4bfSJean-Christophe PLAGNIOL-VILLARD switch (hw->device_id) { 12732439e4bfSJean-Christophe PLAGNIOL-VILLARD case E1000_DEV_ID_82542: 12742439e4bfSJean-Christophe PLAGNIOL-VILLARD switch (hw->revision_id) { 12752439e4bfSJean-Christophe PLAGNIOL-VILLARD case E1000_82542_2_0_REV_ID: 12762439e4bfSJean-Christophe PLAGNIOL-VILLARD hw->mac_type = e1000_82542_rev2_0; 12772439e4bfSJean-Christophe PLAGNIOL-VILLARD break; 12782439e4bfSJean-Christophe PLAGNIOL-VILLARD case E1000_82542_2_1_REV_ID: 12792439e4bfSJean-Christophe PLAGNIOL-VILLARD hw->mac_type = e1000_82542_rev2_1; 12802439e4bfSJean-Christophe PLAGNIOL-VILLARD break; 12812439e4bfSJean-Christophe PLAGNIOL-VILLARD default: 12822439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Invalid 82542 revision ID */ 12832439e4bfSJean-Christophe PLAGNIOL-VILLARD return -E1000_ERR_MAC_TYPE; 12842439e4bfSJean-Christophe PLAGNIOL-VILLARD } 12852439e4bfSJean-Christophe PLAGNIOL-VILLARD break; 12862439e4bfSJean-Christophe PLAGNIOL-VILLARD case E1000_DEV_ID_82543GC_FIBER: 12872439e4bfSJean-Christophe PLAGNIOL-VILLARD case E1000_DEV_ID_82543GC_COPPER: 12882439e4bfSJean-Christophe PLAGNIOL-VILLARD hw->mac_type = e1000_82543; 12892439e4bfSJean-Christophe PLAGNIOL-VILLARD break; 12902439e4bfSJean-Christophe PLAGNIOL-VILLARD case E1000_DEV_ID_82544EI_COPPER: 12912439e4bfSJean-Christophe PLAGNIOL-VILLARD case E1000_DEV_ID_82544EI_FIBER: 12922439e4bfSJean-Christophe PLAGNIOL-VILLARD case E1000_DEV_ID_82544GC_COPPER: 12932439e4bfSJean-Christophe PLAGNIOL-VILLARD case E1000_DEV_ID_82544GC_LOM: 12942439e4bfSJean-Christophe PLAGNIOL-VILLARD hw->mac_type = e1000_82544; 12952439e4bfSJean-Christophe PLAGNIOL-VILLARD break; 12962439e4bfSJean-Christophe PLAGNIOL-VILLARD case E1000_DEV_ID_82540EM: 12972439e4bfSJean-Christophe PLAGNIOL-VILLARD case E1000_DEV_ID_82540EM_LOM: 1298aa070789SRoy Zang case E1000_DEV_ID_82540EP: 1299aa070789SRoy Zang case E1000_DEV_ID_82540EP_LOM: 1300aa070789SRoy Zang case E1000_DEV_ID_82540EP_LP: 13012439e4bfSJean-Christophe PLAGNIOL-VILLARD hw->mac_type = e1000_82540; 13022439e4bfSJean-Christophe PLAGNIOL-VILLARD break; 13032439e4bfSJean-Christophe PLAGNIOL-VILLARD case E1000_DEV_ID_82545EM_COPPER: 13042439e4bfSJean-Christophe PLAGNIOL-VILLARD case E1000_DEV_ID_82545EM_FIBER: 13052439e4bfSJean-Christophe PLAGNIOL-VILLARD hw->mac_type = e1000_82545; 13062439e4bfSJean-Christophe PLAGNIOL-VILLARD break; 1307aa070789SRoy Zang case E1000_DEV_ID_82545GM_COPPER: 1308aa070789SRoy Zang case E1000_DEV_ID_82545GM_FIBER: 1309aa070789SRoy Zang case E1000_DEV_ID_82545GM_SERDES: 1310aa070789SRoy Zang hw->mac_type = e1000_82545_rev_3; 1311aa070789SRoy Zang break; 13122439e4bfSJean-Christophe PLAGNIOL-VILLARD case E1000_DEV_ID_82546EB_COPPER: 13132439e4bfSJean-Christophe PLAGNIOL-VILLARD case E1000_DEV_ID_82546EB_FIBER: 1314aa070789SRoy Zang case E1000_DEV_ID_82546EB_QUAD_COPPER: 13152439e4bfSJean-Christophe PLAGNIOL-VILLARD hw->mac_type = e1000_82546; 13162439e4bfSJean-Christophe PLAGNIOL-VILLARD break; 1317aa070789SRoy Zang case E1000_DEV_ID_82546GB_COPPER: 1318aa070789SRoy Zang case E1000_DEV_ID_82546GB_FIBER: 1319aa070789SRoy Zang case E1000_DEV_ID_82546GB_SERDES: 1320aa070789SRoy Zang case E1000_DEV_ID_82546GB_PCIE: 1321aa070789SRoy Zang case E1000_DEV_ID_82546GB_QUAD_COPPER: 1322aa070789SRoy Zang case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3: 1323aa070789SRoy Zang hw->mac_type = e1000_82546_rev_3; 1324aa070789SRoy Zang break; 1325aa070789SRoy Zang case E1000_DEV_ID_82541EI: 1326aa070789SRoy Zang case E1000_DEV_ID_82541EI_MOBILE: 1327aa070789SRoy Zang case E1000_DEV_ID_82541ER_LOM: 1328aa070789SRoy Zang hw->mac_type = e1000_82541; 1329aa070789SRoy Zang break; 1330ac3315c2SAndre Schwarz case E1000_DEV_ID_82541ER: 1331aa070789SRoy Zang case E1000_DEV_ID_82541GI: 1332aa3b8bf9SWolfgang Grandegger case E1000_DEV_ID_82541GI_LF: 1333aa070789SRoy Zang case E1000_DEV_ID_82541GI_MOBILE: 1334ac3315c2SAndre Schwarz hw->mac_type = e1000_82541_rev_2; 1335ac3315c2SAndre Schwarz break; 1336aa070789SRoy Zang case E1000_DEV_ID_82547EI: 1337aa070789SRoy Zang case E1000_DEV_ID_82547EI_MOBILE: 1338aa070789SRoy Zang hw->mac_type = e1000_82547; 1339aa070789SRoy Zang break; 1340aa070789SRoy Zang case E1000_DEV_ID_82547GI: 1341aa070789SRoy Zang hw->mac_type = e1000_82547_rev_2; 1342aa070789SRoy Zang break; 1343aa070789SRoy Zang case E1000_DEV_ID_82571EB_COPPER: 1344aa070789SRoy Zang case E1000_DEV_ID_82571EB_FIBER: 1345aa070789SRoy Zang case E1000_DEV_ID_82571EB_SERDES: 1346aa070789SRoy Zang case E1000_DEV_ID_82571EB_SERDES_DUAL: 1347aa070789SRoy Zang case E1000_DEV_ID_82571EB_SERDES_QUAD: 1348aa070789SRoy Zang case E1000_DEV_ID_82571EB_QUAD_COPPER: 1349aa070789SRoy Zang case E1000_DEV_ID_82571PT_QUAD_COPPER: 1350aa070789SRoy Zang case E1000_DEV_ID_82571EB_QUAD_FIBER: 1351aa070789SRoy Zang case E1000_DEV_ID_82571EB_QUAD_COPPER_LOWPROFILE: 1352aa070789SRoy Zang hw->mac_type = e1000_82571; 1353aa070789SRoy Zang break; 1354aa070789SRoy Zang case E1000_DEV_ID_82572EI_COPPER: 1355aa070789SRoy Zang case E1000_DEV_ID_82572EI_FIBER: 1356aa070789SRoy Zang case E1000_DEV_ID_82572EI_SERDES: 1357aa070789SRoy Zang case E1000_DEV_ID_82572EI: 1358aa070789SRoy Zang hw->mac_type = e1000_82572; 1359aa070789SRoy Zang break; 1360aa070789SRoy Zang case E1000_DEV_ID_82573E: 1361aa070789SRoy Zang case E1000_DEV_ID_82573E_IAMT: 1362aa070789SRoy Zang case E1000_DEV_ID_82573L: 1363aa070789SRoy Zang hw->mac_type = e1000_82573; 1364aa070789SRoy Zang break; 13652c2668f9SRoy Zang case E1000_DEV_ID_82574L: 13662c2668f9SRoy Zang hw->mac_type = e1000_82574; 13672c2668f9SRoy Zang break; 1368aa070789SRoy Zang case E1000_DEV_ID_80003ES2LAN_COPPER_SPT: 1369aa070789SRoy Zang case E1000_DEV_ID_80003ES2LAN_SERDES_SPT: 1370aa070789SRoy Zang case E1000_DEV_ID_80003ES2LAN_COPPER_DPT: 1371aa070789SRoy Zang case E1000_DEV_ID_80003ES2LAN_SERDES_DPT: 1372aa070789SRoy Zang hw->mac_type = e1000_80003es2lan; 1373aa070789SRoy Zang break; 1374aa070789SRoy Zang case E1000_DEV_ID_ICH8_IGP_M_AMT: 1375aa070789SRoy Zang case E1000_DEV_ID_ICH8_IGP_AMT: 1376aa070789SRoy Zang case E1000_DEV_ID_ICH8_IGP_C: 1377aa070789SRoy Zang case E1000_DEV_ID_ICH8_IFE: 1378aa070789SRoy Zang case E1000_DEV_ID_ICH8_IFE_GT: 1379aa070789SRoy Zang case E1000_DEV_ID_ICH8_IFE_G: 1380aa070789SRoy Zang case E1000_DEV_ID_ICH8_IGP_M: 1381aa070789SRoy Zang hw->mac_type = e1000_ich8lan; 1382aa070789SRoy Zang break; 13836c499abeSMarcel Ziswiler case PCI_DEVICE_ID_INTEL_I210_UNPROGRAMMED: 13846c499abeSMarcel Ziswiler case PCI_DEVICE_ID_INTEL_I211_UNPROGRAMMED: 138595186063SMarek Vasut case PCI_DEVICE_ID_INTEL_I210_COPPER: 13866c499abeSMarcel Ziswiler case PCI_DEVICE_ID_INTEL_I211_COPPER: 138795186063SMarek Vasut case PCI_DEVICE_ID_INTEL_I210_COPPER_FLASHLESS: 138895186063SMarek Vasut case PCI_DEVICE_ID_INTEL_I210_SERDES: 138995186063SMarek Vasut case PCI_DEVICE_ID_INTEL_I210_SERDES_FLASHLESS: 139095186063SMarek Vasut case PCI_DEVICE_ID_INTEL_I210_1000BASEKX: 139195186063SMarek Vasut hw->mac_type = e1000_igb; 139295186063SMarek Vasut break; 13932439e4bfSJean-Christophe PLAGNIOL-VILLARD default: 13942439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Should never have loaded on this device */ 13952439e4bfSJean-Christophe PLAGNIOL-VILLARD return -E1000_ERR_MAC_TYPE; 13962439e4bfSJean-Christophe PLAGNIOL-VILLARD } 13972439e4bfSJean-Christophe PLAGNIOL-VILLARD return E1000_SUCCESS; 13982439e4bfSJean-Christophe PLAGNIOL-VILLARD } 13992439e4bfSJean-Christophe PLAGNIOL-VILLARD 14002439e4bfSJean-Christophe PLAGNIOL-VILLARD /****************************************************************************** 14012439e4bfSJean-Christophe PLAGNIOL-VILLARD * Reset the transmit and receive units; mask and clear all interrupts. 14022439e4bfSJean-Christophe PLAGNIOL-VILLARD * 14032439e4bfSJean-Christophe PLAGNIOL-VILLARD * hw - Struct containing variables accessed by shared code 14042439e4bfSJean-Christophe PLAGNIOL-VILLARD *****************************************************************************/ 14052439e4bfSJean-Christophe PLAGNIOL-VILLARD void 14062439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_reset_hw(struct e1000_hw *hw) 14072439e4bfSJean-Christophe PLAGNIOL-VILLARD { 14082439e4bfSJean-Christophe PLAGNIOL-VILLARD uint32_t ctrl; 14092439e4bfSJean-Christophe PLAGNIOL-VILLARD uint32_t ctrl_ext; 14102439e4bfSJean-Christophe PLAGNIOL-VILLARD uint32_t manc; 14119ea005fbSRoy Zang uint32_t pba = 0; 141295186063SMarek Vasut uint32_t reg; 14132439e4bfSJean-Christophe PLAGNIOL-VILLARD 14142439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGFUNC(); 14152439e4bfSJean-Christophe PLAGNIOL-VILLARD 14169ea005fbSRoy Zang /* get the correct pba value for both PCI and PCIe*/ 14179ea005fbSRoy Zang if (hw->mac_type < e1000_82571) 14189ea005fbSRoy Zang pba = E1000_DEFAULT_PCI_PBA; 14199ea005fbSRoy Zang else 14209ea005fbSRoy Zang pba = E1000_DEFAULT_PCIE_PBA; 14219ea005fbSRoy Zang 14222439e4bfSJean-Christophe PLAGNIOL-VILLARD /* For 82542 (rev 2.0), disable MWI before issuing a device reset */ 14232439e4bfSJean-Christophe PLAGNIOL-VILLARD if (hw->mac_type == e1000_82542_rev2_0) { 14242439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("Disabling MWI on 82542 rev 2.0\n"); 14252439e4bfSJean-Christophe PLAGNIOL-VILLARD pci_write_config_word(hw->pdev, PCI_COMMAND, 1426aa070789SRoy Zang hw->pci_cmd_word & ~PCI_COMMAND_INVALIDATE); 14272439e4bfSJean-Christophe PLAGNIOL-VILLARD } 14282439e4bfSJean-Christophe PLAGNIOL-VILLARD 14292439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Clear interrupt mask to stop board from generating interrupts */ 14302439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("Masking off all interrupts\n"); 143195186063SMarek Vasut if (hw->mac_type == e1000_igb) 143295186063SMarek Vasut E1000_WRITE_REG(hw, I210_IAM, 0); 14332439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, IMC, 0xffffffff); 14342439e4bfSJean-Christophe PLAGNIOL-VILLARD 14352439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Disable the Transmit and Receive units. Then delay to allow 14362439e4bfSJean-Christophe PLAGNIOL-VILLARD * any pending transactions to complete before we hit the MAC with 14372439e4bfSJean-Christophe PLAGNIOL-VILLARD * the global reset. 14382439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 14392439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, RCTL, 0); 14402439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP); 14412439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_FLUSH(hw); 14422439e4bfSJean-Christophe PLAGNIOL-VILLARD 14432439e4bfSJean-Christophe PLAGNIOL-VILLARD /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */ 1444472d5460SYork Sun hw->tbi_compatibility_on = false; 14452439e4bfSJean-Christophe PLAGNIOL-VILLARD 14462439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Delay to allow any outstanding PCI transactions to complete before 14472439e4bfSJean-Christophe PLAGNIOL-VILLARD * resetting the device 14482439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 14492439e4bfSJean-Christophe PLAGNIOL-VILLARD mdelay(10); 14502439e4bfSJean-Christophe PLAGNIOL-VILLARD 14512439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Issue a global reset to the MAC. This will reset the chip's 14522439e4bfSJean-Christophe PLAGNIOL-VILLARD * transmit, receive, DMA, and link units. It will not effect 14532439e4bfSJean-Christophe PLAGNIOL-VILLARD * the current PCI configuration. The global reset bit is self- 14542439e4bfSJean-Christophe PLAGNIOL-VILLARD * clearing, and should clear within a microsecond. 14552439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 14562439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("Issuing a global reset to MAC\n"); 14572439e4bfSJean-Christophe PLAGNIOL-VILLARD ctrl = E1000_READ_REG(hw, CTRL); 14582439e4bfSJean-Christophe PLAGNIOL-VILLARD 14592439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST)); 14602439e4bfSJean-Christophe PLAGNIOL-VILLARD 14612439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Force a reload from the EEPROM if necessary */ 146295186063SMarek Vasut if (hw->mac_type == e1000_igb) { 146395186063SMarek Vasut mdelay(20); 146495186063SMarek Vasut reg = E1000_READ_REG(hw, STATUS); 146595186063SMarek Vasut if (reg & E1000_STATUS_PF_RST_DONE) 146695186063SMarek Vasut DEBUGOUT("PF OK\n"); 146795186063SMarek Vasut reg = E1000_READ_REG(hw, I210_EECD); 146895186063SMarek Vasut if (reg & E1000_EECD_AUTO_RD) 146995186063SMarek Vasut DEBUGOUT("EEC OK\n"); 147095186063SMarek Vasut } else if (hw->mac_type < e1000_82540) { 14712439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Wait for reset to complete */ 14722439e4bfSJean-Christophe PLAGNIOL-VILLARD udelay(10); 14732439e4bfSJean-Christophe PLAGNIOL-VILLARD ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 14742439e4bfSJean-Christophe PLAGNIOL-VILLARD ctrl_ext |= E1000_CTRL_EXT_EE_RST; 14752439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 14762439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_FLUSH(hw); 14772439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Wait for EEPROM reload */ 14782439e4bfSJean-Christophe PLAGNIOL-VILLARD mdelay(2); 14792439e4bfSJean-Christophe PLAGNIOL-VILLARD } else { 14802439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Wait for EEPROM reload (it happens automatically) */ 14812439e4bfSJean-Christophe PLAGNIOL-VILLARD mdelay(4); 14822439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Dissable HW ARPs on ASF enabled adapters */ 14832439e4bfSJean-Christophe PLAGNIOL-VILLARD manc = E1000_READ_REG(hw, MANC); 14842439e4bfSJean-Christophe PLAGNIOL-VILLARD manc &= ~(E1000_MANC_ARP_EN); 14852439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, MANC, manc); 14862439e4bfSJean-Christophe PLAGNIOL-VILLARD } 14872439e4bfSJean-Christophe PLAGNIOL-VILLARD 14882439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Clear interrupt mask to stop board from generating interrupts */ 14892439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("Masking off all interrupts\n"); 149095186063SMarek Vasut if (hw->mac_type == e1000_igb) 149195186063SMarek Vasut E1000_WRITE_REG(hw, I210_IAM, 0); 14922439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, IMC, 0xffffffff); 14932439e4bfSJean-Christophe PLAGNIOL-VILLARD 14942439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Clear any pending interrupt events. */ 149556b13b1eSZang Roy-R61911 E1000_READ_REG(hw, ICR); 14962439e4bfSJean-Christophe PLAGNIOL-VILLARD 14972439e4bfSJean-Christophe PLAGNIOL-VILLARD /* If MWI was previously enabled, reenable it. */ 14982439e4bfSJean-Christophe PLAGNIOL-VILLARD if (hw->mac_type == e1000_82542_rev2_0) { 14992439e4bfSJean-Christophe PLAGNIOL-VILLARD pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word); 15002439e4bfSJean-Christophe PLAGNIOL-VILLARD } 150195186063SMarek Vasut if (hw->mac_type != e1000_igb) 15029ea005fbSRoy Zang E1000_WRITE_REG(hw, PBA, pba); 1503aa070789SRoy Zang } 1504aa070789SRoy Zang 1505aa070789SRoy Zang /****************************************************************************** 1506aa070789SRoy Zang * 1507aa070789SRoy Zang * Initialize a number of hardware-dependent bits 1508aa070789SRoy Zang * 1509aa070789SRoy Zang * hw: Struct containing variables accessed by shared code 1510aa070789SRoy Zang * 1511aa070789SRoy Zang * This function contains hardware limitation workarounds for PCI-E adapters 1512aa070789SRoy Zang * 1513aa070789SRoy Zang *****************************************************************************/ 1514aa070789SRoy Zang static void 1515aa070789SRoy Zang e1000_initialize_hardware_bits(struct e1000_hw *hw) 1516aa070789SRoy Zang { 1517aa070789SRoy Zang if ((hw->mac_type >= e1000_82571) && 1518aa070789SRoy Zang (!hw->initialize_hw_bits_disable)) { 1519aa070789SRoy Zang /* Settings common to all PCI-express silicon */ 1520aa070789SRoy Zang uint32_t reg_ctrl, reg_ctrl_ext; 1521aa070789SRoy Zang uint32_t reg_tarc0, reg_tarc1; 1522aa070789SRoy Zang uint32_t reg_tctl; 1523aa070789SRoy Zang uint32_t reg_txdctl, reg_txdctl1; 1524aa070789SRoy Zang 1525aa070789SRoy Zang /* link autonegotiation/sync workarounds */ 1526aa070789SRoy Zang reg_tarc0 = E1000_READ_REG(hw, TARC0); 1527aa070789SRoy Zang reg_tarc0 &= ~((1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)); 1528aa070789SRoy Zang 1529aa070789SRoy Zang /* Enable not-done TX descriptor counting */ 1530aa070789SRoy Zang reg_txdctl = E1000_READ_REG(hw, TXDCTL); 1531aa070789SRoy Zang reg_txdctl |= E1000_TXDCTL_COUNT_DESC; 1532aa070789SRoy Zang E1000_WRITE_REG(hw, TXDCTL, reg_txdctl); 1533aa070789SRoy Zang 1534aa070789SRoy Zang reg_txdctl1 = E1000_READ_REG(hw, TXDCTL1); 1535aa070789SRoy Zang reg_txdctl1 |= E1000_TXDCTL_COUNT_DESC; 1536aa070789SRoy Zang E1000_WRITE_REG(hw, TXDCTL1, reg_txdctl1); 1537aa070789SRoy Zang 153895186063SMarek Vasut /* IGB is cool */ 153995186063SMarek Vasut if (hw->mac_type == e1000_igb) 154095186063SMarek Vasut return; 154195186063SMarek Vasut 1542aa070789SRoy Zang switch (hw->mac_type) { 1543aa070789SRoy Zang case e1000_82571: 1544aa070789SRoy Zang case e1000_82572: 1545aa070789SRoy Zang /* Clear PHY TX compatible mode bits */ 1546aa070789SRoy Zang reg_tarc1 = E1000_READ_REG(hw, TARC1); 1547aa070789SRoy Zang reg_tarc1 &= ~((1 << 30)|(1 << 29)); 1548aa070789SRoy Zang 1549aa070789SRoy Zang /* link autonegotiation/sync workarounds */ 1550aa070789SRoy Zang reg_tarc0 |= ((1 << 26)|(1 << 25)|(1 << 24)|(1 << 23)); 1551aa070789SRoy Zang 1552aa070789SRoy Zang /* TX ring control fixes */ 1553aa070789SRoy Zang reg_tarc1 |= ((1 << 26)|(1 << 25)|(1 << 24)); 1554aa070789SRoy Zang 1555aa070789SRoy Zang /* Multiple read bit is reversed polarity */ 1556aa070789SRoy Zang reg_tctl = E1000_READ_REG(hw, TCTL); 1557aa070789SRoy Zang if (reg_tctl & E1000_TCTL_MULR) 1558aa070789SRoy Zang reg_tarc1 &= ~(1 << 28); 1559aa070789SRoy Zang else 1560aa070789SRoy Zang reg_tarc1 |= (1 << 28); 1561aa070789SRoy Zang 1562aa070789SRoy Zang E1000_WRITE_REG(hw, TARC1, reg_tarc1); 1563aa070789SRoy Zang break; 1564aa070789SRoy Zang case e1000_82573: 15652c2668f9SRoy Zang case e1000_82574: 1566aa070789SRoy Zang reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 1567aa070789SRoy Zang reg_ctrl_ext &= ~(1 << 23); 1568aa070789SRoy Zang reg_ctrl_ext |= (1 << 22); 1569aa070789SRoy Zang 1570aa070789SRoy Zang /* TX byte count fix */ 1571aa070789SRoy Zang reg_ctrl = E1000_READ_REG(hw, CTRL); 1572aa070789SRoy Zang reg_ctrl &= ~(1 << 29); 1573aa070789SRoy Zang 1574aa070789SRoy Zang E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext); 1575aa070789SRoy Zang E1000_WRITE_REG(hw, CTRL, reg_ctrl); 1576aa070789SRoy Zang break; 1577aa070789SRoy Zang case e1000_80003es2lan: 1578aa070789SRoy Zang /* improve small packet performace for fiber/serdes */ 1579aa070789SRoy Zang if ((hw->media_type == e1000_media_type_fiber) 1580aa070789SRoy Zang || (hw->media_type == 1581aa070789SRoy Zang e1000_media_type_internal_serdes)) { 1582aa070789SRoy Zang reg_tarc0 &= ~(1 << 20); 1583aa070789SRoy Zang } 1584aa070789SRoy Zang 1585aa070789SRoy Zang /* Multiple read bit is reversed polarity */ 1586aa070789SRoy Zang reg_tctl = E1000_READ_REG(hw, TCTL); 1587aa070789SRoy Zang reg_tarc1 = E1000_READ_REG(hw, TARC1); 1588aa070789SRoy Zang if (reg_tctl & E1000_TCTL_MULR) 1589aa070789SRoy Zang reg_tarc1 &= ~(1 << 28); 1590aa070789SRoy Zang else 1591aa070789SRoy Zang reg_tarc1 |= (1 << 28); 1592aa070789SRoy Zang 1593aa070789SRoy Zang E1000_WRITE_REG(hw, TARC1, reg_tarc1); 1594aa070789SRoy Zang break; 1595aa070789SRoy Zang case e1000_ich8lan: 1596aa070789SRoy Zang /* Reduce concurrent DMA requests to 3 from 4 */ 1597aa070789SRoy Zang if ((hw->revision_id < 3) || 1598aa070789SRoy Zang ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) && 1599aa070789SRoy Zang (hw->device_id != E1000_DEV_ID_ICH8_IGP_M))) 1600aa070789SRoy Zang reg_tarc0 |= ((1 << 29)|(1 << 28)); 1601aa070789SRoy Zang 1602aa070789SRoy Zang reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 1603aa070789SRoy Zang reg_ctrl_ext |= (1 << 22); 1604aa070789SRoy Zang E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext); 1605aa070789SRoy Zang 1606aa070789SRoy Zang /* workaround TX hang with TSO=on */ 1607aa070789SRoy Zang reg_tarc0 |= ((1 << 27)|(1 << 26)|(1 << 24)|(1 << 23)); 1608aa070789SRoy Zang 1609aa070789SRoy Zang /* Multiple read bit is reversed polarity */ 1610aa070789SRoy Zang reg_tctl = E1000_READ_REG(hw, TCTL); 1611aa070789SRoy Zang reg_tarc1 = E1000_READ_REG(hw, TARC1); 1612aa070789SRoy Zang if (reg_tctl & E1000_TCTL_MULR) 1613aa070789SRoy Zang reg_tarc1 &= ~(1 << 28); 1614aa070789SRoy Zang else 1615aa070789SRoy Zang reg_tarc1 |= (1 << 28); 1616aa070789SRoy Zang 1617aa070789SRoy Zang /* workaround TX hang with TSO=on */ 1618aa070789SRoy Zang reg_tarc1 |= ((1 << 30)|(1 << 26)|(1 << 24)); 1619aa070789SRoy Zang 1620aa070789SRoy Zang E1000_WRITE_REG(hw, TARC1, reg_tarc1); 1621aa070789SRoy Zang break; 1622aa070789SRoy Zang default: 1623aa070789SRoy Zang break; 1624aa070789SRoy Zang } 1625aa070789SRoy Zang 1626aa070789SRoy Zang E1000_WRITE_REG(hw, TARC0, reg_tarc0); 1627aa070789SRoy Zang } 16282439e4bfSJean-Christophe PLAGNIOL-VILLARD } 16292439e4bfSJean-Christophe PLAGNIOL-VILLARD 16302439e4bfSJean-Christophe PLAGNIOL-VILLARD /****************************************************************************** 16312439e4bfSJean-Christophe PLAGNIOL-VILLARD * Performs basic configuration of the adapter. 16322439e4bfSJean-Christophe PLAGNIOL-VILLARD * 16332439e4bfSJean-Christophe PLAGNIOL-VILLARD * hw - Struct containing variables accessed by shared code 16342439e4bfSJean-Christophe PLAGNIOL-VILLARD * 16352439e4bfSJean-Christophe PLAGNIOL-VILLARD * Assumes that the controller has previously been reset and is in a 16362439e4bfSJean-Christophe PLAGNIOL-VILLARD * post-reset uninitialized state. Initializes the receive address registers, 16372439e4bfSJean-Christophe PLAGNIOL-VILLARD * multicast table, and VLAN filter table. Calls routines to setup link 16382439e4bfSJean-Christophe PLAGNIOL-VILLARD * configuration and flow control settings. Clears all on-chip counters. Leaves 16392439e4bfSJean-Christophe PLAGNIOL-VILLARD * the transmit and receive units disabled and uninitialized. 16402439e4bfSJean-Christophe PLAGNIOL-VILLARD *****************************************************************************/ 16412439e4bfSJean-Christophe PLAGNIOL-VILLARD static int 16422439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_init_hw(struct eth_device *nic) 16432439e4bfSJean-Christophe PLAGNIOL-VILLARD { 16442439e4bfSJean-Christophe PLAGNIOL-VILLARD struct e1000_hw *hw = nic->priv; 1645aa070789SRoy Zang uint32_t ctrl; 16462439e4bfSJean-Christophe PLAGNIOL-VILLARD uint32_t i; 16472439e4bfSJean-Christophe PLAGNIOL-VILLARD int32_t ret_val; 16482439e4bfSJean-Christophe PLAGNIOL-VILLARD uint16_t pcix_cmd_word; 16492439e4bfSJean-Christophe PLAGNIOL-VILLARD uint16_t pcix_stat_hi_word; 16502439e4bfSJean-Christophe PLAGNIOL-VILLARD uint16_t cmd_mmrbc; 16512439e4bfSJean-Christophe PLAGNIOL-VILLARD uint16_t stat_mmrbc; 1652aa070789SRoy Zang uint32_t mta_size; 1653aa070789SRoy Zang uint32_t reg_data; 1654aa070789SRoy Zang uint32_t ctrl_ext; 16552439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGFUNC(); 1656aa070789SRoy Zang /* force full DMA clock frequency for 10/100 on ICH8 A0-B0 */ 1657aa070789SRoy Zang if ((hw->mac_type == e1000_ich8lan) && 1658aa070789SRoy Zang ((hw->revision_id < 3) || 1659aa070789SRoy Zang ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) && 1660aa070789SRoy Zang (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))) { 1661aa070789SRoy Zang reg_data = E1000_READ_REG(hw, STATUS); 1662aa070789SRoy Zang reg_data &= ~0x80000000; 1663aa070789SRoy Zang E1000_WRITE_REG(hw, STATUS, reg_data); 16642439e4bfSJean-Christophe PLAGNIOL-VILLARD } 1665aa070789SRoy Zang /* Do not need initialize Identification LED */ 16662439e4bfSJean-Christophe PLAGNIOL-VILLARD 1667aa070789SRoy Zang /* Set the media type and TBI compatibility */ 1668aa070789SRoy Zang e1000_set_media_type(hw); 1669aa070789SRoy Zang 1670aa070789SRoy Zang /* Must be called after e1000_set_media_type 1671aa070789SRoy Zang * because media_type is used */ 1672aa070789SRoy Zang e1000_initialize_hardware_bits(hw); 16732439e4bfSJean-Christophe PLAGNIOL-VILLARD 16742439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Disabling VLAN filtering. */ 16752439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("Initializing the IEEE VLAN\n"); 1676aa070789SRoy Zang /* VET hardcoded to standard value and VFTA removed in ICH8 LAN */ 1677aa070789SRoy Zang if (hw->mac_type != e1000_ich8lan) { 1678aa070789SRoy Zang if (hw->mac_type < e1000_82545_rev_3) 16792439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, VET, 0); 16802439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_clear_vfta(hw); 1681aa070789SRoy Zang } 16822439e4bfSJean-Christophe PLAGNIOL-VILLARD 16832439e4bfSJean-Christophe PLAGNIOL-VILLARD /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */ 16842439e4bfSJean-Christophe PLAGNIOL-VILLARD if (hw->mac_type == e1000_82542_rev2_0) { 16852439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("Disabling MWI on 82542 rev 2.0\n"); 16862439e4bfSJean-Christophe PLAGNIOL-VILLARD pci_write_config_word(hw->pdev, PCI_COMMAND, 16872439e4bfSJean-Christophe PLAGNIOL-VILLARD hw-> 16882439e4bfSJean-Christophe PLAGNIOL-VILLARD pci_cmd_word & ~PCI_COMMAND_INVALIDATE); 16892439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST); 16902439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_FLUSH(hw); 16912439e4bfSJean-Christophe PLAGNIOL-VILLARD mdelay(5); 16922439e4bfSJean-Christophe PLAGNIOL-VILLARD } 16932439e4bfSJean-Christophe PLAGNIOL-VILLARD 16942439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Setup the receive address. This involves initializing all of the Receive 16952439e4bfSJean-Christophe PLAGNIOL-VILLARD * Address Registers (RARs 0 - 15). 16962439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 16972439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_init_rx_addrs(nic); 16982439e4bfSJean-Christophe PLAGNIOL-VILLARD 16992439e4bfSJean-Christophe PLAGNIOL-VILLARD /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */ 17002439e4bfSJean-Christophe PLAGNIOL-VILLARD if (hw->mac_type == e1000_82542_rev2_0) { 17012439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, RCTL, 0); 17022439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_FLUSH(hw); 17032439e4bfSJean-Christophe PLAGNIOL-VILLARD mdelay(1); 17042439e4bfSJean-Christophe PLAGNIOL-VILLARD pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word); 17052439e4bfSJean-Christophe PLAGNIOL-VILLARD } 17062439e4bfSJean-Christophe PLAGNIOL-VILLARD 17072439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Zero out the Multicast HASH table */ 17082439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("Zeroing the MTA\n"); 1709aa070789SRoy Zang mta_size = E1000_MC_TBL_SIZE; 1710aa070789SRoy Zang if (hw->mac_type == e1000_ich8lan) 1711aa070789SRoy Zang mta_size = E1000_MC_TBL_SIZE_ICH8LAN; 1712aa070789SRoy Zang for (i = 0; i < mta_size; i++) { 17132439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG_ARRAY(hw, MTA, i, 0); 1714aa070789SRoy Zang /* use write flush to prevent Memory Write Block (MWB) from 1715aa070789SRoy Zang * occuring when accessing our register space */ 1716aa070789SRoy Zang E1000_WRITE_FLUSH(hw); 1717aa070789SRoy Zang } 17182439e4bfSJean-Christophe PLAGNIOL-VILLARD #if 0 17192439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Set the PCI priority bit correctly in the CTRL register. This 17202439e4bfSJean-Christophe PLAGNIOL-VILLARD * determines if the adapter gives priority to receives, or if it 1721aa070789SRoy Zang * gives equal priority to transmits and receives. Valid only on 1722aa070789SRoy Zang * 82542 and 82543 silicon. 17232439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 1724aa070789SRoy Zang if (hw->dma_fairness && hw->mac_type <= e1000_82543) { 17252439e4bfSJean-Christophe PLAGNIOL-VILLARD ctrl = E1000_READ_REG(hw, CTRL); 17262439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR); 17272439e4bfSJean-Christophe PLAGNIOL-VILLARD } 17282439e4bfSJean-Christophe PLAGNIOL-VILLARD #endif 1729aa070789SRoy Zang switch (hw->mac_type) { 1730aa070789SRoy Zang case e1000_82545_rev_3: 1731aa070789SRoy Zang case e1000_82546_rev_3: 173295186063SMarek Vasut case e1000_igb: 1733aa070789SRoy Zang break; 1734aa070789SRoy Zang default: 17352439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */ 1736aa070789SRoy Zang if (hw->bus_type == e1000_bus_type_pcix) { 17372439e4bfSJean-Christophe PLAGNIOL-VILLARD pci_read_config_word(hw->pdev, PCIX_COMMAND_REGISTER, 17382439e4bfSJean-Christophe PLAGNIOL-VILLARD &pcix_cmd_word); 17392439e4bfSJean-Christophe PLAGNIOL-VILLARD pci_read_config_word(hw->pdev, PCIX_STATUS_REGISTER_HI, 17402439e4bfSJean-Christophe PLAGNIOL-VILLARD &pcix_stat_hi_word); 17412439e4bfSJean-Christophe PLAGNIOL-VILLARD cmd_mmrbc = 17422439e4bfSJean-Christophe PLAGNIOL-VILLARD (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) >> 17432439e4bfSJean-Christophe PLAGNIOL-VILLARD PCIX_COMMAND_MMRBC_SHIFT; 17442439e4bfSJean-Christophe PLAGNIOL-VILLARD stat_mmrbc = 17452439e4bfSJean-Christophe PLAGNIOL-VILLARD (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >> 17462439e4bfSJean-Christophe PLAGNIOL-VILLARD PCIX_STATUS_HI_MMRBC_SHIFT; 17472439e4bfSJean-Christophe PLAGNIOL-VILLARD if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K) 17482439e4bfSJean-Christophe PLAGNIOL-VILLARD stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K; 17492439e4bfSJean-Christophe PLAGNIOL-VILLARD if (cmd_mmrbc > stat_mmrbc) { 17502439e4bfSJean-Christophe PLAGNIOL-VILLARD pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK; 17512439e4bfSJean-Christophe PLAGNIOL-VILLARD pcix_cmd_word |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT; 17522439e4bfSJean-Christophe PLAGNIOL-VILLARD pci_write_config_word(hw->pdev, PCIX_COMMAND_REGISTER, 17532439e4bfSJean-Christophe PLAGNIOL-VILLARD pcix_cmd_word); 17542439e4bfSJean-Christophe PLAGNIOL-VILLARD } 17552439e4bfSJean-Christophe PLAGNIOL-VILLARD } 1756aa070789SRoy Zang break; 1757aa070789SRoy Zang } 1758aa070789SRoy Zang 1759aa070789SRoy Zang /* More time needed for PHY to initialize */ 1760aa070789SRoy Zang if (hw->mac_type == e1000_ich8lan) 1761aa070789SRoy Zang mdelay(15); 176295186063SMarek Vasut if (hw->mac_type == e1000_igb) 176395186063SMarek Vasut mdelay(15); 17642439e4bfSJean-Christophe PLAGNIOL-VILLARD 17652439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Call a subroutine to configure the link and setup flow control. */ 17662439e4bfSJean-Christophe PLAGNIOL-VILLARD ret_val = e1000_setup_link(nic); 17672439e4bfSJean-Christophe PLAGNIOL-VILLARD 17682439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Set the transmit descriptor write-back policy */ 17692439e4bfSJean-Christophe PLAGNIOL-VILLARD if (hw->mac_type > e1000_82544) { 17702439e4bfSJean-Christophe PLAGNIOL-VILLARD ctrl = E1000_READ_REG(hw, TXDCTL); 17712439e4bfSJean-Christophe PLAGNIOL-VILLARD ctrl = 17722439e4bfSJean-Christophe PLAGNIOL-VILLARD (ctrl & ~E1000_TXDCTL_WTHRESH) | 17732439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_TXDCTL_FULL_TX_DESC_WB; 17742439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, TXDCTL, ctrl); 17752439e4bfSJean-Christophe PLAGNIOL-VILLARD } 1776aa070789SRoy Zang 1777776e66e8SRuchika Gupta /* Set the receive descriptor write back policy */ 1778776e66e8SRuchika Gupta if (hw->mac_type >= e1000_82571) { 1779776e66e8SRuchika Gupta ctrl = E1000_READ_REG(hw, RXDCTL); 1780776e66e8SRuchika Gupta ctrl = 1781776e66e8SRuchika Gupta (ctrl & ~E1000_RXDCTL_WTHRESH) | 1782776e66e8SRuchika Gupta E1000_RXDCTL_FULL_RX_DESC_WB; 1783776e66e8SRuchika Gupta E1000_WRITE_REG(hw, RXDCTL, ctrl); 1784776e66e8SRuchika Gupta } 1785776e66e8SRuchika Gupta 1786aa070789SRoy Zang switch (hw->mac_type) { 1787aa070789SRoy Zang default: 1788aa070789SRoy Zang break; 1789aa070789SRoy Zang case e1000_80003es2lan: 1790aa070789SRoy Zang /* Enable retransmit on late collisions */ 1791aa070789SRoy Zang reg_data = E1000_READ_REG(hw, TCTL); 1792aa070789SRoy Zang reg_data |= E1000_TCTL_RTLC; 1793aa070789SRoy Zang E1000_WRITE_REG(hw, TCTL, reg_data); 1794aa070789SRoy Zang 1795aa070789SRoy Zang /* Configure Gigabit Carry Extend Padding */ 1796aa070789SRoy Zang reg_data = E1000_READ_REG(hw, TCTL_EXT); 1797aa070789SRoy Zang reg_data &= ~E1000_TCTL_EXT_GCEX_MASK; 1798aa070789SRoy Zang reg_data |= DEFAULT_80003ES2LAN_TCTL_EXT_GCEX; 1799aa070789SRoy Zang E1000_WRITE_REG(hw, TCTL_EXT, reg_data); 1800aa070789SRoy Zang 1801aa070789SRoy Zang /* Configure Transmit Inter-Packet Gap */ 1802aa070789SRoy Zang reg_data = E1000_READ_REG(hw, TIPG); 1803aa070789SRoy Zang reg_data &= ~E1000_TIPG_IPGT_MASK; 1804aa070789SRoy Zang reg_data |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000; 1805aa070789SRoy Zang E1000_WRITE_REG(hw, TIPG, reg_data); 1806aa070789SRoy Zang 1807aa070789SRoy Zang reg_data = E1000_READ_REG_ARRAY(hw, FFLT, 0x0001); 1808aa070789SRoy Zang reg_data &= ~0x00100000; 1809aa070789SRoy Zang E1000_WRITE_REG_ARRAY(hw, FFLT, 0x0001, reg_data); 1810aa070789SRoy Zang /* Fall through */ 1811aa070789SRoy Zang case e1000_82571: 1812aa070789SRoy Zang case e1000_82572: 1813aa070789SRoy Zang case e1000_ich8lan: 1814aa070789SRoy Zang ctrl = E1000_READ_REG(hw, TXDCTL1); 1815aa070789SRoy Zang ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) 1816aa070789SRoy Zang | E1000_TXDCTL_FULL_TX_DESC_WB; 1817aa070789SRoy Zang E1000_WRITE_REG(hw, TXDCTL1, ctrl); 1818aa070789SRoy Zang break; 18192c2668f9SRoy Zang case e1000_82573: 18202c2668f9SRoy Zang case e1000_82574: 18212c2668f9SRoy Zang reg_data = E1000_READ_REG(hw, GCR); 18222c2668f9SRoy Zang reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX; 18232c2668f9SRoy Zang E1000_WRITE_REG(hw, GCR, reg_data); 182495186063SMarek Vasut case e1000_igb: 182595186063SMarek Vasut break; 1826aa070789SRoy Zang } 1827aa070789SRoy Zang 18282439e4bfSJean-Christophe PLAGNIOL-VILLARD #if 0 18292439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Clear all of the statistics registers (clear on read). It is 18302439e4bfSJean-Christophe PLAGNIOL-VILLARD * important that we do this after we have tried to establish link 18312439e4bfSJean-Christophe PLAGNIOL-VILLARD * because the symbol error count will increment wildly if there 18322439e4bfSJean-Christophe PLAGNIOL-VILLARD * is no link. 18332439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 18342439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_clear_hw_cntrs(hw); 1835aa070789SRoy Zang 1836aa070789SRoy Zang /* ICH8 No-snoop bits are opposite polarity. 1837aa070789SRoy Zang * Set to snoop by default after reset. */ 1838aa070789SRoy Zang if (hw->mac_type == e1000_ich8lan) 1839aa070789SRoy Zang e1000_set_pci_ex_no_snoop(hw, PCI_EX_82566_SNOOP_ALL); 18402439e4bfSJean-Christophe PLAGNIOL-VILLARD #endif 18412439e4bfSJean-Christophe PLAGNIOL-VILLARD 1842aa070789SRoy Zang if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER || 1843aa070789SRoy Zang hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) { 1844aa070789SRoy Zang ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 1845aa070789SRoy Zang /* Relaxed ordering must be disabled to avoid a parity 1846aa070789SRoy Zang * error crash in a PCI slot. */ 1847aa070789SRoy Zang ctrl_ext |= E1000_CTRL_EXT_RO_DIS; 1848aa070789SRoy Zang E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 1849aa070789SRoy Zang } 1850aa070789SRoy Zang 18512439e4bfSJean-Christophe PLAGNIOL-VILLARD return ret_val; 18522439e4bfSJean-Christophe PLAGNIOL-VILLARD } 18532439e4bfSJean-Christophe PLAGNIOL-VILLARD 18542439e4bfSJean-Christophe PLAGNIOL-VILLARD /****************************************************************************** 18552439e4bfSJean-Christophe PLAGNIOL-VILLARD * Configures flow control and link settings. 18562439e4bfSJean-Christophe PLAGNIOL-VILLARD * 18572439e4bfSJean-Christophe PLAGNIOL-VILLARD * hw - Struct containing variables accessed by shared code 18582439e4bfSJean-Christophe PLAGNIOL-VILLARD * 18592439e4bfSJean-Christophe PLAGNIOL-VILLARD * Determines which flow control settings to use. Calls the apropriate media- 18602439e4bfSJean-Christophe PLAGNIOL-VILLARD * specific link configuration function. Configures the flow control settings. 18612439e4bfSJean-Christophe PLAGNIOL-VILLARD * Assuming the adapter has a valid link partner, a valid link should be 18622439e4bfSJean-Christophe PLAGNIOL-VILLARD * established. Assumes the hardware has previously been reset and the 18632439e4bfSJean-Christophe PLAGNIOL-VILLARD * transmitter and receiver are not enabled. 18642439e4bfSJean-Christophe PLAGNIOL-VILLARD *****************************************************************************/ 18652439e4bfSJean-Christophe PLAGNIOL-VILLARD static int 18662439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_setup_link(struct eth_device *nic) 18672439e4bfSJean-Christophe PLAGNIOL-VILLARD { 18682439e4bfSJean-Christophe PLAGNIOL-VILLARD struct e1000_hw *hw = nic->priv; 18692439e4bfSJean-Christophe PLAGNIOL-VILLARD int32_t ret_val; 18708712adfdSRojhalat Ibrahim #ifndef CONFIG_E1000_NO_NVM 18718712adfdSRojhalat Ibrahim uint32_t ctrl_ext; 18722439e4bfSJean-Christophe PLAGNIOL-VILLARD uint16_t eeprom_data; 18738712adfdSRojhalat Ibrahim #endif 18742439e4bfSJean-Christophe PLAGNIOL-VILLARD 18752439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGFUNC(); 18762439e4bfSJean-Christophe PLAGNIOL-VILLARD 1877aa070789SRoy Zang /* In the case of the phy reset being blocked, we already have a link. 1878aa070789SRoy Zang * We do not have to set it up again. */ 1879aa070789SRoy Zang if (e1000_check_phy_reset_block(hw)) 1880aa070789SRoy Zang return E1000_SUCCESS; 1881aa070789SRoy Zang 18828712adfdSRojhalat Ibrahim #ifndef CONFIG_E1000_NO_NVM 18832439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Read and store word 0x0F of the EEPROM. This word contains bits 18842439e4bfSJean-Christophe PLAGNIOL-VILLARD * that determine the hardware's default PAUSE (flow control) mode, 18852439e4bfSJean-Christophe PLAGNIOL-VILLARD * a bit that determines whether the HW defaults to enabling or 18862439e4bfSJean-Christophe PLAGNIOL-VILLARD * disabling auto-negotiation, and the direction of the 18872439e4bfSJean-Christophe PLAGNIOL-VILLARD * SW defined pins. If there is no SW over-ride of the flow 18882439e4bfSJean-Christophe PLAGNIOL-VILLARD * control setting, then the variable hw->fc will 18892439e4bfSJean-Christophe PLAGNIOL-VILLARD * be initialized based on a value in the EEPROM. 18902439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 1891aa070789SRoy Zang if (e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, 1, 1892aa070789SRoy Zang &eeprom_data) < 0) { 18932439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("EEPROM Read Error\n"); 18942439e4bfSJean-Christophe PLAGNIOL-VILLARD return -E1000_ERR_EEPROM; 18952439e4bfSJean-Christophe PLAGNIOL-VILLARD } 18968712adfdSRojhalat Ibrahim #endif 18972439e4bfSJean-Christophe PLAGNIOL-VILLARD if (hw->fc == e1000_fc_default) { 1898aa070789SRoy Zang switch (hw->mac_type) { 1899aa070789SRoy Zang case e1000_ich8lan: 1900aa070789SRoy Zang case e1000_82573: 19012c2668f9SRoy Zang case e1000_82574: 190295186063SMarek Vasut case e1000_igb: 1903aa070789SRoy Zang hw->fc = e1000_fc_full; 1904aa070789SRoy Zang break; 1905aa070789SRoy Zang default: 19068712adfdSRojhalat Ibrahim #ifndef CONFIG_E1000_NO_NVM 1907aa070789SRoy Zang ret_val = e1000_read_eeprom(hw, 1908aa070789SRoy Zang EEPROM_INIT_CONTROL2_REG, 1, &eeprom_data); 1909aa070789SRoy Zang if (ret_val) { 1910aa070789SRoy Zang DEBUGOUT("EEPROM Read Error\n"); 1911aa070789SRoy Zang return -E1000_ERR_EEPROM; 1912aa070789SRoy Zang } 19132439e4bfSJean-Christophe PLAGNIOL-VILLARD if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0) 19142439e4bfSJean-Christophe PLAGNIOL-VILLARD hw->fc = e1000_fc_none; 19152439e4bfSJean-Christophe PLAGNIOL-VILLARD else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 19162439e4bfSJean-Christophe PLAGNIOL-VILLARD EEPROM_WORD0F_ASM_DIR) 19172439e4bfSJean-Christophe PLAGNIOL-VILLARD hw->fc = e1000_fc_tx_pause; 19182439e4bfSJean-Christophe PLAGNIOL-VILLARD else 19198712adfdSRojhalat Ibrahim #endif 19202439e4bfSJean-Christophe PLAGNIOL-VILLARD hw->fc = e1000_fc_full; 1921aa070789SRoy Zang break; 1922aa070789SRoy Zang } 19232439e4bfSJean-Christophe PLAGNIOL-VILLARD } 19242439e4bfSJean-Christophe PLAGNIOL-VILLARD 19252439e4bfSJean-Christophe PLAGNIOL-VILLARD /* We want to save off the original Flow Control configuration just 19262439e4bfSJean-Christophe PLAGNIOL-VILLARD * in case we get disconnected and then reconnected into a different 19272439e4bfSJean-Christophe PLAGNIOL-VILLARD * hub or switch with different Flow Control capabilities. 19282439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 19292439e4bfSJean-Christophe PLAGNIOL-VILLARD if (hw->mac_type == e1000_82542_rev2_0) 19302439e4bfSJean-Christophe PLAGNIOL-VILLARD hw->fc &= (~e1000_fc_tx_pause); 19312439e4bfSJean-Christophe PLAGNIOL-VILLARD 19322439e4bfSJean-Christophe PLAGNIOL-VILLARD if ((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1)) 19332439e4bfSJean-Christophe PLAGNIOL-VILLARD hw->fc &= (~e1000_fc_rx_pause); 19342439e4bfSJean-Christophe PLAGNIOL-VILLARD 19352439e4bfSJean-Christophe PLAGNIOL-VILLARD hw->original_fc = hw->fc; 19362439e4bfSJean-Christophe PLAGNIOL-VILLARD 19372439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("After fix-ups FlowControl is now = %x\n", hw->fc); 19382439e4bfSJean-Christophe PLAGNIOL-VILLARD 19398712adfdSRojhalat Ibrahim #ifndef CONFIG_E1000_NO_NVM 19402439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Take the 4 bits from EEPROM word 0x0F that determine the initial 19412439e4bfSJean-Christophe PLAGNIOL-VILLARD * polarity value for the SW controlled pins, and setup the 19422439e4bfSJean-Christophe PLAGNIOL-VILLARD * Extended Device Control reg with that info. 19432439e4bfSJean-Christophe PLAGNIOL-VILLARD * This is needed because one of the SW controlled pins is used for 19442439e4bfSJean-Christophe PLAGNIOL-VILLARD * signal detection. So this should be done before e1000_setup_pcs_link() 19452439e4bfSJean-Christophe PLAGNIOL-VILLARD * or e1000_phy_setup() is called. 19462439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 19472439e4bfSJean-Christophe PLAGNIOL-VILLARD if (hw->mac_type == e1000_82543) { 19482439e4bfSJean-Christophe PLAGNIOL-VILLARD ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) << 19492439e4bfSJean-Christophe PLAGNIOL-VILLARD SWDPIO__EXT_SHIFT); 19502439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 19512439e4bfSJean-Christophe PLAGNIOL-VILLARD } 19528712adfdSRojhalat Ibrahim #endif 19532439e4bfSJean-Christophe PLAGNIOL-VILLARD 19542439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Call the necessary subroutine to configure the link. */ 19552439e4bfSJean-Christophe PLAGNIOL-VILLARD ret_val = (hw->media_type == e1000_media_type_fiber) ? 19562439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_setup_fiber_link(nic) : e1000_setup_copper_link(nic); 19572439e4bfSJean-Christophe PLAGNIOL-VILLARD if (ret_val < 0) { 19582439e4bfSJean-Christophe PLAGNIOL-VILLARD return ret_val; 19592439e4bfSJean-Christophe PLAGNIOL-VILLARD } 19602439e4bfSJean-Christophe PLAGNIOL-VILLARD 19612439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Initialize the flow control address, type, and PAUSE timer 19622439e4bfSJean-Christophe PLAGNIOL-VILLARD * registers to their default values. This is done even if flow 19632439e4bfSJean-Christophe PLAGNIOL-VILLARD * control is disabled, because it does not hurt anything to 19642439e4bfSJean-Christophe PLAGNIOL-VILLARD * initialize these registers. 19652439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 1966aa070789SRoy Zang DEBUGOUT("Initializing the Flow Control address, type" 1967aa070789SRoy Zang "and timer regs\n"); 19682439e4bfSJean-Christophe PLAGNIOL-VILLARD 1969aa070789SRoy Zang /* FCAL/H and FCT are hardcoded to standard values in e1000_ich8lan. */ 1970aa070789SRoy Zang if (hw->mac_type != e1000_ich8lan) { 19712439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE); 1972aa070789SRoy Zang E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH); 1973aa070789SRoy Zang E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW); 1974aa070789SRoy Zang } 1975aa070789SRoy Zang 19762439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time); 19772439e4bfSJean-Christophe PLAGNIOL-VILLARD 19782439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Set the flow control receive threshold registers. Normally, 19792439e4bfSJean-Christophe PLAGNIOL-VILLARD * these registers will be set to a default threshold that may be 19802439e4bfSJean-Christophe PLAGNIOL-VILLARD * adjusted later by the driver's runtime code. However, if the 19812439e4bfSJean-Christophe PLAGNIOL-VILLARD * ability to transmit pause frames in not enabled, then these 19822439e4bfSJean-Christophe PLAGNIOL-VILLARD * registers will be set to 0. 19832439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 19842439e4bfSJean-Christophe PLAGNIOL-VILLARD if (!(hw->fc & e1000_fc_tx_pause)) { 19852439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, FCRTL, 0); 19862439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, FCRTH, 0); 19872439e4bfSJean-Christophe PLAGNIOL-VILLARD } else { 19882439e4bfSJean-Christophe PLAGNIOL-VILLARD /* We need to set up the Receive Threshold high and low water marks 19892439e4bfSJean-Christophe PLAGNIOL-VILLARD * as well as (optionally) enabling the transmission of XON frames. 19902439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 19912439e4bfSJean-Christophe PLAGNIOL-VILLARD if (hw->fc_send_xon) { 19922439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, FCRTL, 19932439e4bfSJean-Christophe PLAGNIOL-VILLARD (hw->fc_low_water | E1000_FCRTL_XONE)); 19942439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water); 19952439e4bfSJean-Christophe PLAGNIOL-VILLARD } else { 19962439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water); 19972439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water); 19982439e4bfSJean-Christophe PLAGNIOL-VILLARD } 19992439e4bfSJean-Christophe PLAGNIOL-VILLARD } 20002439e4bfSJean-Christophe PLAGNIOL-VILLARD return ret_val; 20012439e4bfSJean-Christophe PLAGNIOL-VILLARD } 20022439e4bfSJean-Christophe PLAGNIOL-VILLARD 20032439e4bfSJean-Christophe PLAGNIOL-VILLARD /****************************************************************************** 20042439e4bfSJean-Christophe PLAGNIOL-VILLARD * Sets up link for a fiber based adapter 20052439e4bfSJean-Christophe PLAGNIOL-VILLARD * 20062439e4bfSJean-Christophe PLAGNIOL-VILLARD * hw - Struct containing variables accessed by shared code 20072439e4bfSJean-Christophe PLAGNIOL-VILLARD * 20082439e4bfSJean-Christophe PLAGNIOL-VILLARD * Manipulates Physical Coding Sublayer functions in order to configure 20092439e4bfSJean-Christophe PLAGNIOL-VILLARD * link. Assumes the hardware has been previously reset and the transmitter 20102439e4bfSJean-Christophe PLAGNIOL-VILLARD * and receiver are not enabled. 20112439e4bfSJean-Christophe PLAGNIOL-VILLARD *****************************************************************************/ 20122439e4bfSJean-Christophe PLAGNIOL-VILLARD static int 20132439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_setup_fiber_link(struct eth_device *nic) 20142439e4bfSJean-Christophe PLAGNIOL-VILLARD { 20152439e4bfSJean-Christophe PLAGNIOL-VILLARD struct e1000_hw *hw = nic->priv; 20162439e4bfSJean-Christophe PLAGNIOL-VILLARD uint32_t ctrl; 20172439e4bfSJean-Christophe PLAGNIOL-VILLARD uint32_t status; 20182439e4bfSJean-Christophe PLAGNIOL-VILLARD uint32_t txcw = 0; 20192439e4bfSJean-Christophe PLAGNIOL-VILLARD uint32_t i; 20202439e4bfSJean-Christophe PLAGNIOL-VILLARD uint32_t signal; 20212439e4bfSJean-Christophe PLAGNIOL-VILLARD int32_t ret_val; 20222439e4bfSJean-Christophe PLAGNIOL-VILLARD 20232439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGFUNC(); 20242439e4bfSJean-Christophe PLAGNIOL-VILLARD /* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be 20252439e4bfSJean-Christophe PLAGNIOL-VILLARD * set when the optics detect a signal. On older adapters, it will be 20262439e4bfSJean-Christophe PLAGNIOL-VILLARD * cleared when there is a signal 20272439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 20282439e4bfSJean-Christophe PLAGNIOL-VILLARD ctrl = E1000_READ_REG(hw, CTRL); 20292439e4bfSJean-Christophe PLAGNIOL-VILLARD if ((hw->mac_type > e1000_82544) && !(ctrl & E1000_CTRL_ILOS)) 20302439e4bfSJean-Christophe PLAGNIOL-VILLARD signal = E1000_CTRL_SWDPIN1; 20312439e4bfSJean-Christophe PLAGNIOL-VILLARD else 20322439e4bfSJean-Christophe PLAGNIOL-VILLARD signal = 0; 20332439e4bfSJean-Christophe PLAGNIOL-VILLARD 20342439e4bfSJean-Christophe PLAGNIOL-VILLARD printf("signal for %s is %x (ctrl %08x)!!!!\n", nic->name, signal, 20352439e4bfSJean-Christophe PLAGNIOL-VILLARD ctrl); 20362439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Take the link out of reset */ 20372439e4bfSJean-Christophe PLAGNIOL-VILLARD ctrl &= ~(E1000_CTRL_LRST); 20382439e4bfSJean-Christophe PLAGNIOL-VILLARD 20392439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_config_collision_dist(hw); 20402439e4bfSJean-Christophe PLAGNIOL-VILLARD 20412439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Check for a software override of the flow control settings, and setup 20422439e4bfSJean-Christophe PLAGNIOL-VILLARD * the device accordingly. If auto-negotiation is enabled, then software 20432439e4bfSJean-Christophe PLAGNIOL-VILLARD * will have to set the "PAUSE" bits to the correct value in the Tranmsit 20442439e4bfSJean-Christophe PLAGNIOL-VILLARD * Config Word Register (TXCW) and re-start auto-negotiation. However, if 20452439e4bfSJean-Christophe PLAGNIOL-VILLARD * auto-negotiation is disabled, then software will have to manually 20462439e4bfSJean-Christophe PLAGNIOL-VILLARD * configure the two flow control enable bits in the CTRL register. 20472439e4bfSJean-Christophe PLAGNIOL-VILLARD * 20482439e4bfSJean-Christophe PLAGNIOL-VILLARD * The possible values of the "fc" parameter are: 20492439e4bfSJean-Christophe PLAGNIOL-VILLARD * 0: Flow control is completely disabled 20502439e4bfSJean-Christophe PLAGNIOL-VILLARD * 1: Rx flow control is enabled (we can receive pause frames, but 20512439e4bfSJean-Christophe PLAGNIOL-VILLARD * not send pause frames). 20522439e4bfSJean-Christophe PLAGNIOL-VILLARD * 2: Tx flow control is enabled (we can send pause frames but we do 20532439e4bfSJean-Christophe PLAGNIOL-VILLARD * not support receiving pause frames). 20542439e4bfSJean-Christophe PLAGNIOL-VILLARD * 3: Both Rx and TX flow control (symmetric) are enabled. 20552439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 20562439e4bfSJean-Christophe PLAGNIOL-VILLARD switch (hw->fc) { 20572439e4bfSJean-Christophe PLAGNIOL-VILLARD case e1000_fc_none: 20582439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Flow control is completely disabled by a software over-ride. */ 20592439e4bfSJean-Christophe PLAGNIOL-VILLARD txcw = (E1000_TXCW_ANE | E1000_TXCW_FD); 20602439e4bfSJean-Christophe PLAGNIOL-VILLARD break; 20612439e4bfSJean-Christophe PLAGNIOL-VILLARD case e1000_fc_rx_pause: 20622439e4bfSJean-Christophe PLAGNIOL-VILLARD /* RX Flow control is enabled and TX Flow control is disabled by a 20632439e4bfSJean-Christophe PLAGNIOL-VILLARD * software over-ride. Since there really isn't a way to advertise 20642439e4bfSJean-Christophe PLAGNIOL-VILLARD * that we are capable of RX Pause ONLY, we will advertise that we 20652439e4bfSJean-Christophe PLAGNIOL-VILLARD * support both symmetric and asymmetric RX PAUSE. Later, we will 20662439e4bfSJean-Christophe PLAGNIOL-VILLARD * disable the adapter's ability to send PAUSE frames. 20672439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 20682439e4bfSJean-Christophe PLAGNIOL-VILLARD txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); 20692439e4bfSJean-Christophe PLAGNIOL-VILLARD break; 20702439e4bfSJean-Christophe PLAGNIOL-VILLARD case e1000_fc_tx_pause: 20712439e4bfSJean-Christophe PLAGNIOL-VILLARD /* TX Flow control is enabled, and RX Flow control is disabled, by a 20722439e4bfSJean-Christophe PLAGNIOL-VILLARD * software over-ride. 20732439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 20742439e4bfSJean-Christophe PLAGNIOL-VILLARD txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR); 20752439e4bfSJean-Christophe PLAGNIOL-VILLARD break; 20762439e4bfSJean-Christophe PLAGNIOL-VILLARD case e1000_fc_full: 20772439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Flow control (both RX and TX) is enabled by a software over-ride. */ 20782439e4bfSJean-Christophe PLAGNIOL-VILLARD txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); 20792439e4bfSJean-Christophe PLAGNIOL-VILLARD break; 20802439e4bfSJean-Christophe PLAGNIOL-VILLARD default: 20812439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("Flow control param set incorrectly\n"); 20822439e4bfSJean-Christophe PLAGNIOL-VILLARD return -E1000_ERR_CONFIG; 20832439e4bfSJean-Christophe PLAGNIOL-VILLARD break; 20842439e4bfSJean-Christophe PLAGNIOL-VILLARD } 20852439e4bfSJean-Christophe PLAGNIOL-VILLARD 20862439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Since auto-negotiation is enabled, take the link out of reset (the link 20872439e4bfSJean-Christophe PLAGNIOL-VILLARD * will be in reset, because we previously reset the chip). This will 20882439e4bfSJean-Christophe PLAGNIOL-VILLARD * restart auto-negotiation. If auto-neogtiation is successful then the 20892439e4bfSJean-Christophe PLAGNIOL-VILLARD * link-up status bit will be set and the flow control enable bits (RFCE 20902439e4bfSJean-Christophe PLAGNIOL-VILLARD * and TFCE) will be set according to their negotiated value. 20912439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 20922439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("Auto-negotiation enabled (%#x)\n", txcw); 20932439e4bfSJean-Christophe PLAGNIOL-VILLARD 20942439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, TXCW, txcw); 20952439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, CTRL, ctrl); 20962439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_FLUSH(hw); 20972439e4bfSJean-Christophe PLAGNIOL-VILLARD 20982439e4bfSJean-Christophe PLAGNIOL-VILLARD hw->txcw = txcw; 20992439e4bfSJean-Christophe PLAGNIOL-VILLARD mdelay(1); 21002439e4bfSJean-Christophe PLAGNIOL-VILLARD 21012439e4bfSJean-Christophe PLAGNIOL-VILLARD /* If we have a signal (the cable is plugged in) then poll for a "Link-Up" 21022439e4bfSJean-Christophe PLAGNIOL-VILLARD * indication in the Device Status Register. Time-out if a link isn't 21032439e4bfSJean-Christophe PLAGNIOL-VILLARD * seen in 500 milliseconds seconds (Auto-negotiation should complete in 21042439e4bfSJean-Christophe PLAGNIOL-VILLARD * less than 500 milliseconds even if the other end is doing it in SW). 21052439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 21062439e4bfSJean-Christophe PLAGNIOL-VILLARD if ((E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) { 21072439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("Looking for Link\n"); 21082439e4bfSJean-Christophe PLAGNIOL-VILLARD for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) { 21092439e4bfSJean-Christophe PLAGNIOL-VILLARD mdelay(10); 21102439e4bfSJean-Christophe PLAGNIOL-VILLARD status = E1000_READ_REG(hw, STATUS); 21112439e4bfSJean-Christophe PLAGNIOL-VILLARD if (status & E1000_STATUS_LU) 21122439e4bfSJean-Christophe PLAGNIOL-VILLARD break; 21132439e4bfSJean-Christophe PLAGNIOL-VILLARD } 21142439e4bfSJean-Christophe PLAGNIOL-VILLARD if (i == (LINK_UP_TIMEOUT / 10)) { 21152439e4bfSJean-Christophe PLAGNIOL-VILLARD /* AutoNeg failed to achieve a link, so we'll call 21162439e4bfSJean-Christophe PLAGNIOL-VILLARD * e1000_check_for_link. This routine will force the link up if we 21172439e4bfSJean-Christophe PLAGNIOL-VILLARD * detect a signal. This will allow us to communicate with 21182439e4bfSJean-Christophe PLAGNIOL-VILLARD * non-autonegotiating link partners. 21192439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 21202439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("Never got a valid link from auto-neg!!!\n"); 21212439e4bfSJean-Christophe PLAGNIOL-VILLARD hw->autoneg_failed = 1; 21222439e4bfSJean-Christophe PLAGNIOL-VILLARD ret_val = e1000_check_for_link(nic); 21232439e4bfSJean-Christophe PLAGNIOL-VILLARD if (ret_val < 0) { 21242439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("Error while checking for link\n"); 21252439e4bfSJean-Christophe PLAGNIOL-VILLARD return ret_val; 21262439e4bfSJean-Christophe PLAGNIOL-VILLARD } 21272439e4bfSJean-Christophe PLAGNIOL-VILLARD hw->autoneg_failed = 0; 21282439e4bfSJean-Christophe PLAGNIOL-VILLARD } else { 21292439e4bfSJean-Christophe PLAGNIOL-VILLARD hw->autoneg_failed = 0; 21302439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("Valid Link Found\n"); 21312439e4bfSJean-Christophe PLAGNIOL-VILLARD } 21322439e4bfSJean-Christophe PLAGNIOL-VILLARD } else { 21332439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("No Signal Detected\n"); 21342439e4bfSJean-Christophe PLAGNIOL-VILLARD return -E1000_ERR_NOLINK; 21352439e4bfSJean-Christophe PLAGNIOL-VILLARD } 21362439e4bfSJean-Christophe PLAGNIOL-VILLARD return 0; 21372439e4bfSJean-Christophe PLAGNIOL-VILLARD } 21382439e4bfSJean-Christophe PLAGNIOL-VILLARD 21392439e4bfSJean-Christophe PLAGNIOL-VILLARD /****************************************************************************** 2140aa070789SRoy Zang * Make sure we have a valid PHY and change PHY mode before link setup. 21412439e4bfSJean-Christophe PLAGNIOL-VILLARD * 21422439e4bfSJean-Christophe PLAGNIOL-VILLARD * hw - Struct containing variables accessed by shared code 21432439e4bfSJean-Christophe PLAGNIOL-VILLARD ******************************************************************************/ 2144aa070789SRoy Zang static int32_t 2145aa070789SRoy Zang e1000_copper_link_preconfig(struct e1000_hw *hw) 21462439e4bfSJean-Christophe PLAGNIOL-VILLARD { 21472439e4bfSJean-Christophe PLAGNIOL-VILLARD uint32_t ctrl; 21482439e4bfSJean-Christophe PLAGNIOL-VILLARD int32_t ret_val; 21492439e4bfSJean-Christophe PLAGNIOL-VILLARD uint16_t phy_data; 21502439e4bfSJean-Christophe PLAGNIOL-VILLARD 21512439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGFUNC(); 21522439e4bfSJean-Christophe PLAGNIOL-VILLARD 21532439e4bfSJean-Christophe PLAGNIOL-VILLARD ctrl = E1000_READ_REG(hw, CTRL); 21542439e4bfSJean-Christophe PLAGNIOL-VILLARD /* With 82543, we need to force speed and duplex on the MAC equal to what 21552439e4bfSJean-Christophe PLAGNIOL-VILLARD * the PHY speed and duplex configuration is. In addition, we need to 21562439e4bfSJean-Christophe PLAGNIOL-VILLARD * perform a hardware reset on the PHY to take it out of reset. 21572439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 21582439e4bfSJean-Christophe PLAGNIOL-VILLARD if (hw->mac_type > e1000_82543) { 21592439e4bfSJean-Christophe PLAGNIOL-VILLARD ctrl |= E1000_CTRL_SLU; 21602439e4bfSJean-Christophe PLAGNIOL-VILLARD ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 21612439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, CTRL, ctrl); 21622439e4bfSJean-Christophe PLAGNIOL-VILLARD } else { 2163aa070789SRoy Zang ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX 2164aa070789SRoy Zang | E1000_CTRL_SLU); 21652439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, CTRL, ctrl); 2166aa070789SRoy Zang ret_val = e1000_phy_hw_reset(hw); 2167aa070789SRoy Zang if (ret_val) 2168aa070789SRoy Zang return ret_val; 21692439e4bfSJean-Christophe PLAGNIOL-VILLARD } 21702439e4bfSJean-Christophe PLAGNIOL-VILLARD 21712439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Make sure we have a valid PHY */ 21722439e4bfSJean-Christophe PLAGNIOL-VILLARD ret_val = e1000_detect_gig_phy(hw); 2173aa070789SRoy Zang if (ret_val) { 21742439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("Error, did not detect valid phy.\n"); 21752439e4bfSJean-Christophe PLAGNIOL-VILLARD return ret_val; 21762439e4bfSJean-Christophe PLAGNIOL-VILLARD } 21772439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("Phy ID = %x \n", hw->phy_id); 21782439e4bfSJean-Christophe PLAGNIOL-VILLARD 2179aa070789SRoy Zang /* Set PHY to class A mode (if necessary) */ 2180aa070789SRoy Zang ret_val = e1000_set_phy_mode(hw); 2181aa070789SRoy Zang if (ret_val) 2182aa070789SRoy Zang return ret_val; 2183aa070789SRoy Zang if ((hw->mac_type == e1000_82545_rev_3) || 2184aa070789SRoy Zang (hw->mac_type == e1000_82546_rev_3)) { 2185aa070789SRoy Zang ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 2186aa070789SRoy Zang &phy_data); 2187aa070789SRoy Zang phy_data |= 0x00000008; 2188aa070789SRoy Zang ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 2189aa070789SRoy Zang phy_data); 21902439e4bfSJean-Christophe PLAGNIOL-VILLARD } 2191aa070789SRoy Zang 2192aa070789SRoy Zang if (hw->mac_type <= e1000_82543 || 2193aa070789SRoy Zang hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 || 2194aa070789SRoy Zang hw->mac_type == e1000_82541_rev_2 2195aa070789SRoy Zang || hw->mac_type == e1000_82547_rev_2) 2196472d5460SYork Sun hw->phy_reset_disable = false; 2197aa070789SRoy Zang 2198aa070789SRoy Zang return E1000_SUCCESS; 2199aa070789SRoy Zang } 2200aa070789SRoy Zang 2201aa070789SRoy Zang /***************************************************************************** 2202aa070789SRoy Zang * 2203aa070789SRoy Zang * This function sets the lplu state according to the active flag. When 2204aa070789SRoy Zang * activating lplu this function also disables smart speed and vise versa. 2205aa070789SRoy Zang * lplu will not be activated unless the device autonegotiation advertisment 2206aa070789SRoy Zang * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes. 2207aa070789SRoy Zang * hw: Struct containing variables accessed by shared code 2208aa070789SRoy Zang * active - true to enable lplu false to disable lplu. 2209aa070789SRoy Zang * 2210aa070789SRoy Zang * returns: - E1000_ERR_PHY if fail to read/write the PHY 2211aa070789SRoy Zang * E1000_SUCCESS at any other case. 2212aa070789SRoy Zang * 2213aa070789SRoy Zang ****************************************************************************/ 2214aa070789SRoy Zang 2215aa070789SRoy Zang static int32_t 2216472d5460SYork Sun e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active) 2217aa070789SRoy Zang { 2218aa070789SRoy Zang uint32_t phy_ctrl = 0; 2219aa070789SRoy Zang int32_t ret_val; 2220aa070789SRoy Zang uint16_t phy_data; 2221aa070789SRoy Zang DEBUGFUNC(); 2222aa070789SRoy Zang 2223aa070789SRoy Zang if (hw->phy_type != e1000_phy_igp && hw->phy_type != e1000_phy_igp_2 2224aa070789SRoy Zang && hw->phy_type != e1000_phy_igp_3) 2225aa070789SRoy Zang return E1000_SUCCESS; 2226aa070789SRoy Zang 2227aa070789SRoy Zang /* During driver activity LPLU should not be used or it will attain link 2228aa070789SRoy Zang * from the lowest speeds starting from 10Mbps. The capability is used 2229aa070789SRoy Zang * for Dx transitions and states */ 2230aa070789SRoy Zang if (hw->mac_type == e1000_82541_rev_2 2231aa070789SRoy Zang || hw->mac_type == e1000_82547_rev_2) { 2232aa070789SRoy Zang ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, 2233aa070789SRoy Zang &phy_data); 2234aa070789SRoy Zang if (ret_val) 2235aa070789SRoy Zang return ret_val; 2236aa070789SRoy Zang } else if (hw->mac_type == e1000_ich8lan) { 2237aa070789SRoy Zang /* MAC writes into PHY register based on the state transition 2238aa070789SRoy Zang * and start auto-negotiation. SW driver can overwrite the 2239aa070789SRoy Zang * settings in CSR PHY power control E1000_PHY_CTRL register. */ 2240aa070789SRoy Zang phy_ctrl = E1000_READ_REG(hw, PHY_CTRL); 2241aa070789SRoy Zang } else { 2242aa070789SRoy Zang ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, 2243aa070789SRoy Zang &phy_data); 2244aa070789SRoy Zang if (ret_val) 2245aa070789SRoy Zang return ret_val; 2246aa070789SRoy Zang } 2247aa070789SRoy Zang 2248aa070789SRoy Zang if (!active) { 2249aa070789SRoy Zang if (hw->mac_type == e1000_82541_rev_2 || 2250aa070789SRoy Zang hw->mac_type == e1000_82547_rev_2) { 2251aa070789SRoy Zang phy_data &= ~IGP01E1000_GMII_FLEX_SPD; 2252aa070789SRoy Zang ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, 2253aa070789SRoy Zang phy_data); 2254aa070789SRoy Zang if (ret_val) 2255aa070789SRoy Zang return ret_val; 2256aa070789SRoy Zang } else { 2257aa070789SRoy Zang if (hw->mac_type == e1000_ich8lan) { 2258aa070789SRoy Zang phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU; 2259aa070789SRoy Zang E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); 2260aa070789SRoy Zang } else { 2261aa070789SRoy Zang phy_data &= ~IGP02E1000_PM_D3_LPLU; 2262aa070789SRoy Zang ret_val = e1000_write_phy_reg(hw, 2263aa070789SRoy Zang IGP02E1000_PHY_POWER_MGMT, phy_data); 2264aa070789SRoy Zang if (ret_val) 2265aa070789SRoy Zang return ret_val; 2266aa070789SRoy Zang } 2267aa070789SRoy Zang } 2268aa070789SRoy Zang 2269aa070789SRoy Zang /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during 2270aa070789SRoy Zang * Dx states where the power conservation is most important. During 2271aa070789SRoy Zang * driver activity we should enable SmartSpeed, so performance is 2272aa070789SRoy Zang * maintained. */ 2273aa070789SRoy Zang if (hw->smart_speed == e1000_smart_speed_on) { 2274aa070789SRoy Zang ret_val = e1000_read_phy_reg(hw, 2275aa070789SRoy Zang IGP01E1000_PHY_PORT_CONFIG, &phy_data); 2276aa070789SRoy Zang if (ret_val) 2277aa070789SRoy Zang return ret_val; 2278aa070789SRoy Zang 2279aa070789SRoy Zang phy_data |= IGP01E1000_PSCFR_SMART_SPEED; 2280aa070789SRoy Zang ret_val = e1000_write_phy_reg(hw, 2281aa070789SRoy Zang IGP01E1000_PHY_PORT_CONFIG, phy_data); 2282aa070789SRoy Zang if (ret_val) 2283aa070789SRoy Zang return ret_val; 2284aa070789SRoy Zang } else if (hw->smart_speed == e1000_smart_speed_off) { 2285aa070789SRoy Zang ret_val = e1000_read_phy_reg(hw, 2286aa070789SRoy Zang IGP01E1000_PHY_PORT_CONFIG, &phy_data); 2287aa070789SRoy Zang if (ret_val) 2288aa070789SRoy Zang return ret_val; 2289aa070789SRoy Zang 2290aa070789SRoy Zang phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 2291aa070789SRoy Zang ret_val = e1000_write_phy_reg(hw, 2292aa070789SRoy Zang IGP01E1000_PHY_PORT_CONFIG, phy_data); 2293aa070789SRoy Zang if (ret_val) 2294aa070789SRoy Zang return ret_val; 2295aa070789SRoy Zang } 2296aa070789SRoy Zang 2297aa070789SRoy Zang } else if ((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT) 2298aa070789SRoy Zang || (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL) || 2299aa070789SRoy Zang (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) { 2300aa070789SRoy Zang 2301aa070789SRoy Zang if (hw->mac_type == e1000_82541_rev_2 || 2302aa070789SRoy Zang hw->mac_type == e1000_82547_rev_2) { 2303aa070789SRoy Zang phy_data |= IGP01E1000_GMII_FLEX_SPD; 2304aa070789SRoy Zang ret_val = e1000_write_phy_reg(hw, 2305aa070789SRoy Zang IGP01E1000_GMII_FIFO, phy_data); 2306aa070789SRoy Zang if (ret_val) 2307aa070789SRoy Zang return ret_val; 2308aa070789SRoy Zang } else { 2309aa070789SRoy Zang if (hw->mac_type == e1000_ich8lan) { 2310aa070789SRoy Zang phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU; 2311aa070789SRoy Zang E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); 2312aa070789SRoy Zang } else { 2313aa070789SRoy Zang phy_data |= IGP02E1000_PM_D3_LPLU; 2314aa070789SRoy Zang ret_val = e1000_write_phy_reg(hw, 2315aa070789SRoy Zang IGP02E1000_PHY_POWER_MGMT, phy_data); 2316aa070789SRoy Zang if (ret_val) 2317aa070789SRoy Zang return ret_val; 2318aa070789SRoy Zang } 2319aa070789SRoy Zang } 2320aa070789SRoy Zang 2321aa070789SRoy Zang /* When LPLU is enabled we should disable SmartSpeed */ 2322aa070789SRoy Zang ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 2323aa070789SRoy Zang &phy_data); 2324aa070789SRoy Zang if (ret_val) 2325aa070789SRoy Zang return ret_val; 2326aa070789SRoy Zang 2327aa070789SRoy Zang phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 2328aa070789SRoy Zang ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 2329aa070789SRoy Zang phy_data); 2330aa070789SRoy Zang if (ret_val) 2331aa070789SRoy Zang return ret_val; 2332aa070789SRoy Zang } 2333aa070789SRoy Zang return E1000_SUCCESS; 2334aa070789SRoy Zang } 2335aa070789SRoy Zang 2336aa070789SRoy Zang /***************************************************************************** 2337aa070789SRoy Zang * 2338aa070789SRoy Zang * This function sets the lplu d0 state according to the active flag. When 2339aa070789SRoy Zang * activating lplu this function also disables smart speed and vise versa. 2340aa070789SRoy Zang * lplu will not be activated unless the device autonegotiation advertisment 2341aa070789SRoy Zang * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes. 2342aa070789SRoy Zang * hw: Struct containing variables accessed by shared code 2343aa070789SRoy Zang * active - true to enable lplu false to disable lplu. 2344aa070789SRoy Zang * 2345aa070789SRoy Zang * returns: - E1000_ERR_PHY if fail to read/write the PHY 2346aa070789SRoy Zang * E1000_SUCCESS at any other case. 2347aa070789SRoy Zang * 2348aa070789SRoy Zang ****************************************************************************/ 2349aa070789SRoy Zang 2350aa070789SRoy Zang static int32_t 2351472d5460SYork Sun e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active) 2352aa070789SRoy Zang { 2353aa070789SRoy Zang uint32_t phy_ctrl = 0; 2354aa070789SRoy Zang int32_t ret_val; 2355aa070789SRoy Zang uint16_t phy_data; 2356aa070789SRoy Zang DEBUGFUNC(); 2357aa070789SRoy Zang 2358aa070789SRoy Zang if (hw->mac_type <= e1000_82547_rev_2) 2359aa070789SRoy Zang return E1000_SUCCESS; 2360aa070789SRoy Zang 2361aa070789SRoy Zang if (hw->mac_type == e1000_ich8lan) { 2362aa070789SRoy Zang phy_ctrl = E1000_READ_REG(hw, PHY_CTRL); 236395186063SMarek Vasut } else if (hw->mac_type == e1000_igb) { 236495186063SMarek Vasut phy_ctrl = E1000_READ_REG(hw, I210_PHY_CTRL); 2365aa070789SRoy Zang } else { 2366aa070789SRoy Zang ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, 2367aa070789SRoy Zang &phy_data); 2368aa070789SRoy Zang if (ret_val) 2369aa070789SRoy Zang return ret_val; 2370aa070789SRoy Zang } 2371aa070789SRoy Zang 2372aa070789SRoy Zang if (!active) { 2373aa070789SRoy Zang if (hw->mac_type == e1000_ich8lan) { 2374aa070789SRoy Zang phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU; 2375aa070789SRoy Zang E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); 237695186063SMarek Vasut } else if (hw->mac_type == e1000_igb) { 237795186063SMarek Vasut phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU; 237895186063SMarek Vasut E1000_WRITE_REG(hw, I210_PHY_CTRL, phy_ctrl); 2379aa070789SRoy Zang } else { 2380aa070789SRoy Zang phy_data &= ~IGP02E1000_PM_D0_LPLU; 2381aa070789SRoy Zang ret_val = e1000_write_phy_reg(hw, 2382aa070789SRoy Zang IGP02E1000_PHY_POWER_MGMT, phy_data); 2383aa070789SRoy Zang if (ret_val) 2384aa070789SRoy Zang return ret_val; 2385aa070789SRoy Zang } 2386aa070789SRoy Zang 238795186063SMarek Vasut if (hw->mac_type == e1000_igb) 238895186063SMarek Vasut return E1000_SUCCESS; 238995186063SMarek Vasut 2390aa070789SRoy Zang /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during 2391aa070789SRoy Zang * Dx states where the power conservation is most important. During 2392aa070789SRoy Zang * driver activity we should enable SmartSpeed, so performance is 2393aa070789SRoy Zang * maintained. */ 2394aa070789SRoy Zang if (hw->smart_speed == e1000_smart_speed_on) { 2395aa070789SRoy Zang ret_val = e1000_read_phy_reg(hw, 2396aa070789SRoy Zang IGP01E1000_PHY_PORT_CONFIG, &phy_data); 2397aa070789SRoy Zang if (ret_val) 2398aa070789SRoy Zang return ret_val; 2399aa070789SRoy Zang 2400aa070789SRoy Zang phy_data |= IGP01E1000_PSCFR_SMART_SPEED; 2401aa070789SRoy Zang ret_val = e1000_write_phy_reg(hw, 2402aa070789SRoy Zang IGP01E1000_PHY_PORT_CONFIG, phy_data); 2403aa070789SRoy Zang if (ret_val) 2404aa070789SRoy Zang return ret_val; 2405aa070789SRoy Zang } else if (hw->smart_speed == e1000_smart_speed_off) { 2406aa070789SRoy Zang ret_val = e1000_read_phy_reg(hw, 2407aa070789SRoy Zang IGP01E1000_PHY_PORT_CONFIG, &phy_data); 2408aa070789SRoy Zang if (ret_val) 2409aa070789SRoy Zang return ret_val; 2410aa070789SRoy Zang 2411aa070789SRoy Zang phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 2412aa070789SRoy Zang ret_val = e1000_write_phy_reg(hw, 2413aa070789SRoy Zang IGP01E1000_PHY_PORT_CONFIG, phy_data); 2414aa070789SRoy Zang if (ret_val) 2415aa070789SRoy Zang return ret_val; 2416aa070789SRoy Zang } 2417aa070789SRoy Zang 2418aa070789SRoy Zang 2419aa070789SRoy Zang } else { 2420aa070789SRoy Zang 2421aa070789SRoy Zang if (hw->mac_type == e1000_ich8lan) { 2422aa070789SRoy Zang phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU; 2423aa070789SRoy Zang E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); 242495186063SMarek Vasut } else if (hw->mac_type == e1000_igb) { 242595186063SMarek Vasut phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU; 242695186063SMarek Vasut E1000_WRITE_REG(hw, I210_PHY_CTRL, phy_ctrl); 2427aa070789SRoy Zang } else { 2428aa070789SRoy Zang phy_data |= IGP02E1000_PM_D0_LPLU; 2429aa070789SRoy Zang ret_val = e1000_write_phy_reg(hw, 2430aa070789SRoy Zang IGP02E1000_PHY_POWER_MGMT, phy_data); 2431aa070789SRoy Zang if (ret_val) 2432aa070789SRoy Zang return ret_val; 2433aa070789SRoy Zang } 2434aa070789SRoy Zang 243595186063SMarek Vasut if (hw->mac_type == e1000_igb) 243695186063SMarek Vasut return E1000_SUCCESS; 243795186063SMarek Vasut 2438aa070789SRoy Zang /* When LPLU is enabled we should disable SmartSpeed */ 2439aa070789SRoy Zang ret_val = e1000_read_phy_reg(hw, 2440aa070789SRoy Zang IGP01E1000_PHY_PORT_CONFIG, &phy_data); 2441aa070789SRoy Zang if (ret_val) 2442aa070789SRoy Zang return ret_val; 2443aa070789SRoy Zang 2444aa070789SRoy Zang phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 2445aa070789SRoy Zang ret_val = e1000_write_phy_reg(hw, 2446aa070789SRoy Zang IGP01E1000_PHY_PORT_CONFIG, phy_data); 2447aa070789SRoy Zang if (ret_val) 2448aa070789SRoy Zang return ret_val; 2449aa070789SRoy Zang 2450aa070789SRoy Zang } 2451aa070789SRoy Zang return E1000_SUCCESS; 2452aa070789SRoy Zang } 2453aa070789SRoy Zang 2454aa070789SRoy Zang /******************************************************************** 2455aa070789SRoy Zang * Copper link setup for e1000_phy_igp series. 2456aa070789SRoy Zang * 2457aa070789SRoy Zang * hw - Struct containing variables accessed by shared code 2458aa070789SRoy Zang *********************************************************************/ 2459aa070789SRoy Zang static int32_t 2460aa070789SRoy Zang e1000_copper_link_igp_setup(struct e1000_hw *hw) 2461aa070789SRoy Zang { 2462aa070789SRoy Zang uint32_t led_ctrl; 2463aa070789SRoy Zang int32_t ret_val; 2464aa070789SRoy Zang uint16_t phy_data; 2465aa070789SRoy Zang 2466f81ecb5dSTimur Tabi DEBUGFUNC(); 2467aa070789SRoy Zang 2468aa070789SRoy Zang if (hw->phy_reset_disable) 2469aa070789SRoy Zang return E1000_SUCCESS; 2470aa070789SRoy Zang 2471aa070789SRoy Zang ret_val = e1000_phy_reset(hw); 2472aa070789SRoy Zang if (ret_val) { 2473aa070789SRoy Zang DEBUGOUT("Error Resetting the PHY\n"); 2474aa070789SRoy Zang return ret_val; 2475aa070789SRoy Zang } 2476aa070789SRoy Zang 2477aa070789SRoy Zang /* Wait 15ms for MAC to configure PHY from eeprom settings */ 2478aa070789SRoy Zang mdelay(15); 2479aa070789SRoy Zang if (hw->mac_type != e1000_ich8lan) { 2480aa070789SRoy Zang /* Configure activity LED after PHY reset */ 2481aa070789SRoy Zang led_ctrl = E1000_READ_REG(hw, LEDCTL); 2482aa070789SRoy Zang led_ctrl &= IGP_ACTIVITY_LED_MASK; 2483aa070789SRoy Zang led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); 2484aa070789SRoy Zang E1000_WRITE_REG(hw, LEDCTL, led_ctrl); 2485aa070789SRoy Zang } 2486aa070789SRoy Zang 2487aa070789SRoy Zang /* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */ 2488aa070789SRoy Zang if (hw->phy_type == e1000_phy_igp) { 2489aa070789SRoy Zang /* disable lplu d3 during driver init */ 2490472d5460SYork Sun ret_val = e1000_set_d3_lplu_state(hw, false); 2491aa070789SRoy Zang if (ret_val) { 2492aa070789SRoy Zang DEBUGOUT("Error Disabling LPLU D3\n"); 2493aa070789SRoy Zang return ret_val; 2494aa070789SRoy Zang } 2495aa070789SRoy Zang } 2496aa070789SRoy Zang 2497aa070789SRoy Zang /* disable lplu d0 during driver init */ 2498472d5460SYork Sun ret_val = e1000_set_d0_lplu_state(hw, false); 2499aa070789SRoy Zang if (ret_val) { 2500aa070789SRoy Zang DEBUGOUT("Error Disabling LPLU D0\n"); 2501aa070789SRoy Zang return ret_val; 2502aa070789SRoy Zang } 2503aa070789SRoy Zang /* Configure mdi-mdix settings */ 2504aa070789SRoy Zang ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); 2505aa070789SRoy Zang if (ret_val) 2506aa070789SRoy Zang return ret_val; 2507aa070789SRoy Zang 2508aa070789SRoy Zang if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { 2509aa070789SRoy Zang hw->dsp_config_state = e1000_dsp_config_disabled; 2510aa070789SRoy Zang /* Force MDI for earlier revs of the IGP PHY */ 2511aa070789SRoy Zang phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX 2512aa070789SRoy Zang | IGP01E1000_PSCR_FORCE_MDI_MDIX); 2513aa070789SRoy Zang hw->mdix = 1; 2514aa070789SRoy Zang 2515aa070789SRoy Zang } else { 2516aa070789SRoy Zang hw->dsp_config_state = e1000_dsp_config_enabled; 2517aa070789SRoy Zang phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; 2518aa070789SRoy Zang 2519aa070789SRoy Zang switch (hw->mdix) { 2520aa070789SRoy Zang case 1: 2521aa070789SRoy Zang phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; 2522aa070789SRoy Zang break; 2523aa070789SRoy Zang case 2: 2524aa070789SRoy Zang phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX; 2525aa070789SRoy Zang break; 2526aa070789SRoy Zang case 0: 2527aa070789SRoy Zang default: 2528aa070789SRoy Zang phy_data |= IGP01E1000_PSCR_AUTO_MDIX; 2529aa070789SRoy Zang break; 2530aa070789SRoy Zang } 2531aa070789SRoy Zang } 2532aa070789SRoy Zang ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); 2533aa070789SRoy Zang if (ret_val) 2534aa070789SRoy Zang return ret_val; 2535aa070789SRoy Zang 2536aa070789SRoy Zang /* set auto-master slave resolution settings */ 2537aa070789SRoy Zang if (hw->autoneg) { 2538aa070789SRoy Zang e1000_ms_type phy_ms_setting = hw->master_slave; 2539aa070789SRoy Zang 2540aa070789SRoy Zang if (hw->ffe_config_state == e1000_ffe_config_active) 2541aa070789SRoy Zang hw->ffe_config_state = e1000_ffe_config_enabled; 2542aa070789SRoy Zang 2543aa070789SRoy Zang if (hw->dsp_config_state == e1000_dsp_config_activated) 2544aa070789SRoy Zang hw->dsp_config_state = e1000_dsp_config_enabled; 2545aa070789SRoy Zang 2546aa070789SRoy Zang /* when autonegotiation advertisment is only 1000Mbps then we 2547aa070789SRoy Zang * should disable SmartSpeed and enable Auto MasterSlave 2548aa070789SRoy Zang * resolution as hardware default. */ 2549aa070789SRoy Zang if (hw->autoneg_advertised == ADVERTISE_1000_FULL) { 2550aa070789SRoy Zang /* Disable SmartSpeed */ 2551aa070789SRoy Zang ret_val = e1000_read_phy_reg(hw, 2552aa070789SRoy Zang IGP01E1000_PHY_PORT_CONFIG, &phy_data); 2553aa070789SRoy Zang if (ret_val) 2554aa070789SRoy Zang return ret_val; 2555aa070789SRoy Zang phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 2556aa070789SRoy Zang ret_val = e1000_write_phy_reg(hw, 2557aa070789SRoy Zang IGP01E1000_PHY_PORT_CONFIG, phy_data); 2558aa070789SRoy Zang if (ret_val) 2559aa070789SRoy Zang return ret_val; 2560aa070789SRoy Zang /* Set auto Master/Slave resolution process */ 2561aa070789SRoy Zang ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, 2562aa070789SRoy Zang &phy_data); 2563aa070789SRoy Zang if (ret_val) 2564aa070789SRoy Zang return ret_val; 2565aa070789SRoy Zang phy_data &= ~CR_1000T_MS_ENABLE; 2566aa070789SRoy Zang ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, 2567aa070789SRoy Zang phy_data); 2568aa070789SRoy Zang if (ret_val) 2569aa070789SRoy Zang return ret_val; 2570aa070789SRoy Zang } 2571aa070789SRoy Zang 2572aa070789SRoy Zang ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data); 2573aa070789SRoy Zang if (ret_val) 2574aa070789SRoy Zang return ret_val; 2575aa070789SRoy Zang 2576aa070789SRoy Zang /* load defaults for future use */ 2577aa070789SRoy Zang hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ? 2578aa070789SRoy Zang ((phy_data & CR_1000T_MS_VALUE) ? 2579aa070789SRoy Zang e1000_ms_force_master : 2580aa070789SRoy Zang e1000_ms_force_slave) : 2581aa070789SRoy Zang e1000_ms_auto; 2582aa070789SRoy Zang 2583aa070789SRoy Zang switch (phy_ms_setting) { 2584aa070789SRoy Zang case e1000_ms_force_master: 2585aa070789SRoy Zang phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE); 2586aa070789SRoy Zang break; 2587aa070789SRoy Zang case e1000_ms_force_slave: 2588aa070789SRoy Zang phy_data |= CR_1000T_MS_ENABLE; 2589aa070789SRoy Zang phy_data &= ~(CR_1000T_MS_VALUE); 2590aa070789SRoy Zang break; 2591aa070789SRoy Zang case e1000_ms_auto: 2592aa070789SRoy Zang phy_data &= ~CR_1000T_MS_ENABLE; 2593aa070789SRoy Zang default: 2594aa070789SRoy Zang break; 2595aa070789SRoy Zang } 2596aa070789SRoy Zang ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data); 2597aa070789SRoy Zang if (ret_val) 2598aa070789SRoy Zang return ret_val; 2599aa070789SRoy Zang } 2600aa070789SRoy Zang 2601aa070789SRoy Zang return E1000_SUCCESS; 2602aa070789SRoy Zang } 2603aa070789SRoy Zang 2604aa070789SRoy Zang /***************************************************************************** 2605aa070789SRoy Zang * This function checks the mode of the firmware. 2606aa070789SRoy Zang * 2607472d5460SYork Sun * returns - true when the mode is IAMT or false. 2608aa070789SRoy Zang ****************************************************************************/ 2609472d5460SYork Sun bool 2610aa070789SRoy Zang e1000_check_mng_mode(struct e1000_hw *hw) 2611aa070789SRoy Zang { 2612aa070789SRoy Zang uint32_t fwsm; 2613aa070789SRoy Zang DEBUGFUNC(); 2614aa070789SRoy Zang 2615aa070789SRoy Zang fwsm = E1000_READ_REG(hw, FWSM); 2616aa070789SRoy Zang 2617aa070789SRoy Zang if (hw->mac_type == e1000_ich8lan) { 2618aa070789SRoy Zang if ((fwsm & E1000_FWSM_MODE_MASK) == 2619aa070789SRoy Zang (E1000_MNG_ICH_IAMT_MODE << E1000_FWSM_MODE_SHIFT)) 2620472d5460SYork Sun return true; 2621aa070789SRoy Zang } else if ((fwsm & E1000_FWSM_MODE_MASK) == 2622aa070789SRoy Zang (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT)) 2623472d5460SYork Sun return true; 2624aa070789SRoy Zang 2625472d5460SYork Sun return false; 2626aa070789SRoy Zang } 2627aa070789SRoy Zang 2628aa070789SRoy Zang static int32_t 2629aa070789SRoy Zang e1000_write_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t data) 2630aa070789SRoy Zang { 2631987b43a1SKyle Moffett uint16_t swfw = E1000_SWFW_PHY0_SM; 2632aa070789SRoy Zang uint32_t reg_val; 2633aa070789SRoy Zang DEBUGFUNC(); 2634aa070789SRoy Zang 2635987b43a1SKyle Moffett if (e1000_is_second_port(hw)) 2636aa070789SRoy Zang swfw = E1000_SWFW_PHY1_SM; 2637987b43a1SKyle Moffett 2638aa070789SRoy Zang if (e1000_swfw_sync_acquire(hw, swfw)) 2639aa070789SRoy Zang return -E1000_ERR_SWFW_SYNC; 2640aa070789SRoy Zang 2641aa070789SRoy Zang reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) 2642aa070789SRoy Zang & E1000_KUMCTRLSTA_OFFSET) | data; 2643aa070789SRoy Zang E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val); 2644aa070789SRoy Zang udelay(2); 2645aa070789SRoy Zang 2646aa070789SRoy Zang return E1000_SUCCESS; 2647aa070789SRoy Zang } 2648aa070789SRoy Zang 2649aa070789SRoy Zang static int32_t 2650aa070789SRoy Zang e1000_read_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *data) 2651aa070789SRoy Zang { 2652987b43a1SKyle Moffett uint16_t swfw = E1000_SWFW_PHY0_SM; 2653aa070789SRoy Zang uint32_t reg_val; 2654aa070789SRoy Zang DEBUGFUNC(); 2655aa070789SRoy Zang 2656987b43a1SKyle Moffett if (e1000_is_second_port(hw)) 2657aa070789SRoy Zang swfw = E1000_SWFW_PHY1_SM; 2658987b43a1SKyle Moffett 265995186063SMarek Vasut if (e1000_swfw_sync_acquire(hw, swfw)) { 266095186063SMarek Vasut debug("%s[%i]\n", __func__, __LINE__); 2661aa070789SRoy Zang return -E1000_ERR_SWFW_SYNC; 266295186063SMarek Vasut } 2663aa070789SRoy Zang 2664aa070789SRoy Zang /* Write register address */ 2665aa070789SRoy Zang reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) & 2666aa070789SRoy Zang E1000_KUMCTRLSTA_OFFSET) | E1000_KUMCTRLSTA_REN; 2667aa070789SRoy Zang E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val); 2668aa070789SRoy Zang udelay(2); 2669aa070789SRoy Zang 2670aa070789SRoy Zang /* Read the data returned */ 2671aa070789SRoy Zang reg_val = E1000_READ_REG(hw, KUMCTRLSTA); 2672aa070789SRoy Zang *data = (uint16_t)reg_val; 2673aa070789SRoy Zang 2674aa070789SRoy Zang return E1000_SUCCESS; 2675aa070789SRoy Zang } 2676aa070789SRoy Zang 2677aa070789SRoy Zang /******************************************************************** 2678aa070789SRoy Zang * Copper link setup for e1000_phy_gg82563 series. 2679aa070789SRoy Zang * 2680aa070789SRoy Zang * hw - Struct containing variables accessed by shared code 2681aa070789SRoy Zang *********************************************************************/ 2682aa070789SRoy Zang static int32_t 2683aa070789SRoy Zang e1000_copper_link_ggp_setup(struct e1000_hw *hw) 2684aa070789SRoy Zang { 2685aa070789SRoy Zang int32_t ret_val; 2686aa070789SRoy Zang uint16_t phy_data; 2687aa070789SRoy Zang uint32_t reg_data; 2688aa070789SRoy Zang 2689aa070789SRoy Zang DEBUGFUNC(); 2690aa070789SRoy Zang 2691aa070789SRoy Zang if (!hw->phy_reset_disable) { 2692aa070789SRoy Zang /* Enable CRS on TX for half-duplex operation. */ 2693aa070789SRoy Zang ret_val = e1000_read_phy_reg(hw, 2694aa070789SRoy Zang GG82563_PHY_MAC_SPEC_CTRL, &phy_data); 2695aa070789SRoy Zang if (ret_val) 2696aa070789SRoy Zang return ret_val; 2697aa070789SRoy Zang 2698aa070789SRoy Zang phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX; 2699aa070789SRoy Zang /* Use 25MHz for both link down and 1000BASE-T for Tx clock */ 2700aa070789SRoy Zang phy_data |= GG82563_MSCR_TX_CLK_1000MBPS_25MHZ; 2701aa070789SRoy Zang 2702aa070789SRoy Zang ret_val = e1000_write_phy_reg(hw, 2703aa070789SRoy Zang GG82563_PHY_MAC_SPEC_CTRL, phy_data); 2704aa070789SRoy Zang if (ret_val) 2705aa070789SRoy Zang return ret_val; 2706aa070789SRoy Zang 2707aa070789SRoy Zang /* Options: 2708aa070789SRoy Zang * MDI/MDI-X = 0 (default) 2709aa070789SRoy Zang * 0 - Auto for all speeds 2710aa070789SRoy Zang * 1 - MDI mode 2711aa070789SRoy Zang * 2 - MDI-X mode 2712aa070789SRoy Zang * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) 2713aa070789SRoy Zang */ 2714aa070789SRoy Zang ret_val = e1000_read_phy_reg(hw, 2715aa070789SRoy Zang GG82563_PHY_SPEC_CTRL, &phy_data); 2716aa070789SRoy Zang if (ret_val) 2717aa070789SRoy Zang return ret_val; 2718aa070789SRoy Zang 2719aa070789SRoy Zang phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK; 2720aa070789SRoy Zang 2721aa070789SRoy Zang switch (hw->mdix) { 2722aa070789SRoy Zang case 1: 2723aa070789SRoy Zang phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDI; 2724aa070789SRoy Zang break; 2725aa070789SRoy Zang case 2: 2726aa070789SRoy Zang phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDIX; 2727aa070789SRoy Zang break; 2728aa070789SRoy Zang case 0: 2729aa070789SRoy Zang default: 2730aa070789SRoy Zang phy_data |= GG82563_PSCR_CROSSOVER_MODE_AUTO; 2731aa070789SRoy Zang break; 2732aa070789SRoy Zang } 2733aa070789SRoy Zang 2734aa070789SRoy Zang /* Options: 2735aa070789SRoy Zang * disable_polarity_correction = 0 (default) 2736aa070789SRoy Zang * Automatic Correction for Reversed Cable Polarity 2737aa070789SRoy Zang * 0 - Disabled 2738aa070789SRoy Zang * 1 - Enabled 2739aa070789SRoy Zang */ 2740aa070789SRoy Zang phy_data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE; 2741aa070789SRoy Zang ret_val = e1000_write_phy_reg(hw, 2742aa070789SRoy Zang GG82563_PHY_SPEC_CTRL, phy_data); 2743aa070789SRoy Zang 2744aa070789SRoy Zang if (ret_val) 2745aa070789SRoy Zang return ret_val; 2746aa070789SRoy Zang 2747aa070789SRoy Zang /* SW Reset the PHY so all changes take effect */ 2748aa070789SRoy Zang ret_val = e1000_phy_reset(hw); 2749aa070789SRoy Zang if (ret_val) { 2750aa070789SRoy Zang DEBUGOUT("Error Resetting the PHY\n"); 2751aa070789SRoy Zang return ret_val; 2752aa070789SRoy Zang } 2753aa070789SRoy Zang } /* phy_reset_disable */ 2754aa070789SRoy Zang 2755aa070789SRoy Zang if (hw->mac_type == e1000_80003es2lan) { 2756aa070789SRoy Zang /* Bypass RX and TX FIFO's */ 2757aa070789SRoy Zang ret_val = e1000_write_kmrn_reg(hw, 2758aa070789SRoy Zang E1000_KUMCTRLSTA_OFFSET_FIFO_CTRL, 2759aa070789SRoy Zang E1000_KUMCTRLSTA_FIFO_CTRL_RX_BYPASS 2760aa070789SRoy Zang | E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS); 2761aa070789SRoy Zang if (ret_val) 2762aa070789SRoy Zang return ret_val; 2763aa070789SRoy Zang 2764aa070789SRoy Zang ret_val = e1000_read_phy_reg(hw, 2765aa070789SRoy Zang GG82563_PHY_SPEC_CTRL_2, &phy_data); 2766aa070789SRoy Zang if (ret_val) 2767aa070789SRoy Zang return ret_val; 2768aa070789SRoy Zang 2769aa070789SRoy Zang phy_data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG; 2770aa070789SRoy Zang ret_val = e1000_write_phy_reg(hw, 2771aa070789SRoy Zang GG82563_PHY_SPEC_CTRL_2, phy_data); 2772aa070789SRoy Zang 2773aa070789SRoy Zang if (ret_val) 2774aa070789SRoy Zang return ret_val; 2775aa070789SRoy Zang 2776aa070789SRoy Zang reg_data = E1000_READ_REG(hw, CTRL_EXT); 2777aa070789SRoy Zang reg_data &= ~(E1000_CTRL_EXT_LINK_MODE_MASK); 2778aa070789SRoy Zang E1000_WRITE_REG(hw, CTRL_EXT, reg_data); 2779aa070789SRoy Zang 2780aa070789SRoy Zang ret_val = e1000_read_phy_reg(hw, 2781aa070789SRoy Zang GG82563_PHY_PWR_MGMT_CTRL, &phy_data); 2782aa070789SRoy Zang if (ret_val) 2783aa070789SRoy Zang return ret_val; 2784aa070789SRoy Zang 2785aa070789SRoy Zang /* Do not init these registers when the HW is in IAMT mode, since the 2786aa070789SRoy Zang * firmware will have already initialized them. We only initialize 2787aa070789SRoy Zang * them if the HW is not in IAMT mode. 2788aa070789SRoy Zang */ 2789472d5460SYork Sun if (e1000_check_mng_mode(hw) == false) { 2790aa070789SRoy Zang /* Enable Electrical Idle on the PHY */ 2791aa070789SRoy Zang phy_data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE; 2792aa070789SRoy Zang ret_val = e1000_write_phy_reg(hw, 2793aa070789SRoy Zang GG82563_PHY_PWR_MGMT_CTRL, phy_data); 2794aa070789SRoy Zang if (ret_val) 2795aa070789SRoy Zang return ret_val; 2796aa070789SRoy Zang 2797aa070789SRoy Zang ret_val = e1000_read_phy_reg(hw, 2798aa070789SRoy Zang GG82563_PHY_KMRN_MODE_CTRL, &phy_data); 2799aa070789SRoy Zang if (ret_val) 2800aa070789SRoy Zang return ret_val; 2801aa070789SRoy Zang 2802aa070789SRoy Zang phy_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; 2803aa070789SRoy Zang ret_val = e1000_write_phy_reg(hw, 2804aa070789SRoy Zang GG82563_PHY_KMRN_MODE_CTRL, phy_data); 2805aa070789SRoy Zang 2806aa070789SRoy Zang if (ret_val) 2807aa070789SRoy Zang return ret_val; 2808aa070789SRoy Zang } 2809aa070789SRoy Zang 2810aa070789SRoy Zang /* Workaround: Disable padding in Kumeran interface in the MAC 2811aa070789SRoy Zang * and in the PHY to avoid CRC errors. 2812aa070789SRoy Zang */ 2813aa070789SRoy Zang ret_val = e1000_read_phy_reg(hw, 2814aa070789SRoy Zang GG82563_PHY_INBAND_CTRL, &phy_data); 2815aa070789SRoy Zang if (ret_val) 2816aa070789SRoy Zang return ret_val; 2817aa070789SRoy Zang phy_data |= GG82563_ICR_DIS_PADDING; 2818aa070789SRoy Zang ret_val = e1000_write_phy_reg(hw, 2819aa070789SRoy Zang GG82563_PHY_INBAND_CTRL, phy_data); 2820aa070789SRoy Zang if (ret_val) 2821aa070789SRoy Zang return ret_val; 2822aa070789SRoy Zang } 2823aa070789SRoy Zang return E1000_SUCCESS; 2824aa070789SRoy Zang } 2825aa070789SRoy Zang 2826aa070789SRoy Zang /******************************************************************** 2827aa070789SRoy Zang * Copper link setup for e1000_phy_m88 series. 2828aa070789SRoy Zang * 2829aa070789SRoy Zang * hw - Struct containing variables accessed by shared code 2830aa070789SRoy Zang *********************************************************************/ 2831aa070789SRoy Zang static int32_t 2832aa070789SRoy Zang e1000_copper_link_mgp_setup(struct e1000_hw *hw) 2833aa070789SRoy Zang { 2834aa070789SRoy Zang int32_t ret_val; 2835aa070789SRoy Zang uint16_t phy_data; 2836aa070789SRoy Zang 2837aa070789SRoy Zang DEBUGFUNC(); 2838aa070789SRoy Zang 2839aa070789SRoy Zang if (hw->phy_reset_disable) 2840aa070789SRoy Zang return E1000_SUCCESS; 2841aa070789SRoy Zang 2842aa070789SRoy Zang /* Enable CRS on TX. This must be set for half-duplex operation. */ 2843aa070789SRoy Zang ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 2844aa070789SRoy Zang if (ret_val) 2845aa070789SRoy Zang return ret_val; 2846aa070789SRoy Zang 28472439e4bfSJean-Christophe PLAGNIOL-VILLARD phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; 28482439e4bfSJean-Christophe PLAGNIOL-VILLARD 28492439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Options: 28502439e4bfSJean-Christophe PLAGNIOL-VILLARD * MDI/MDI-X = 0 (default) 28512439e4bfSJean-Christophe PLAGNIOL-VILLARD * 0 - Auto for all speeds 28522439e4bfSJean-Christophe PLAGNIOL-VILLARD * 1 - MDI mode 28532439e4bfSJean-Christophe PLAGNIOL-VILLARD * 2 - MDI-X mode 28542439e4bfSJean-Christophe PLAGNIOL-VILLARD * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) 28552439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 28562439e4bfSJean-Christophe PLAGNIOL-VILLARD phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 2857aa070789SRoy Zang 28582439e4bfSJean-Christophe PLAGNIOL-VILLARD switch (hw->mdix) { 28592439e4bfSJean-Christophe PLAGNIOL-VILLARD case 1: 28602439e4bfSJean-Christophe PLAGNIOL-VILLARD phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; 28612439e4bfSJean-Christophe PLAGNIOL-VILLARD break; 28622439e4bfSJean-Christophe PLAGNIOL-VILLARD case 2: 28632439e4bfSJean-Christophe PLAGNIOL-VILLARD phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; 28642439e4bfSJean-Christophe PLAGNIOL-VILLARD break; 28652439e4bfSJean-Christophe PLAGNIOL-VILLARD case 3: 28662439e4bfSJean-Christophe PLAGNIOL-VILLARD phy_data |= M88E1000_PSCR_AUTO_X_1000T; 28672439e4bfSJean-Christophe PLAGNIOL-VILLARD break; 28682439e4bfSJean-Christophe PLAGNIOL-VILLARD case 0: 28692439e4bfSJean-Christophe PLAGNIOL-VILLARD default: 28702439e4bfSJean-Christophe PLAGNIOL-VILLARD phy_data |= M88E1000_PSCR_AUTO_X_MODE; 28712439e4bfSJean-Christophe PLAGNIOL-VILLARD break; 28722439e4bfSJean-Christophe PLAGNIOL-VILLARD } 28732439e4bfSJean-Christophe PLAGNIOL-VILLARD 28742439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Options: 28752439e4bfSJean-Christophe PLAGNIOL-VILLARD * disable_polarity_correction = 0 (default) 28762439e4bfSJean-Christophe PLAGNIOL-VILLARD * Automatic Correction for Reversed Cable Polarity 28772439e4bfSJean-Christophe PLAGNIOL-VILLARD * 0 - Disabled 28782439e4bfSJean-Christophe PLAGNIOL-VILLARD * 1 - Enabled 28792439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 28802439e4bfSJean-Christophe PLAGNIOL-VILLARD phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; 2881aa070789SRoy Zang ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 2882aa070789SRoy Zang if (ret_val) 2883aa070789SRoy Zang return ret_val; 28842439e4bfSJean-Christophe PLAGNIOL-VILLARD 2885aa070789SRoy Zang if (hw->phy_revision < M88E1011_I_REV_4) { 28862439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Force TX_CLK in the Extended PHY Specific Control Register 28872439e4bfSJean-Christophe PLAGNIOL-VILLARD * to 25MHz clock. 28882439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 2889aa070789SRoy Zang ret_val = e1000_read_phy_reg(hw, 2890aa070789SRoy Zang M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); 2891aa070789SRoy Zang if (ret_val) 2892aa070789SRoy Zang return ret_val; 2893aa070789SRoy Zang 28942439e4bfSJean-Christophe PLAGNIOL-VILLARD phy_data |= M88E1000_EPSCR_TX_CLK_25; 2895aa070789SRoy Zang 2896aa070789SRoy Zang if ((hw->phy_revision == E1000_REVISION_2) && 2897aa070789SRoy Zang (hw->phy_id == M88E1111_I_PHY_ID)) { 2898aa070789SRoy Zang /* Vidalia Phy, set the downshift counter to 5x */ 2899aa070789SRoy Zang phy_data &= ~(M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK); 2900aa070789SRoy Zang phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X; 2901aa070789SRoy Zang ret_val = e1000_write_phy_reg(hw, 2902aa070789SRoy Zang M88E1000_EXT_PHY_SPEC_CTRL, phy_data); 2903aa070789SRoy Zang if (ret_val) 2904aa070789SRoy Zang return ret_val; 2905aa070789SRoy Zang } else { 29062439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Configure Master and Slave downshift values */ 2907aa070789SRoy Zang phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 2908aa070789SRoy Zang | M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK); 2909aa070789SRoy Zang phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X 2910aa070789SRoy Zang | M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X); 2911aa070789SRoy Zang ret_val = e1000_write_phy_reg(hw, 2912aa070789SRoy Zang M88E1000_EXT_PHY_SPEC_CTRL, phy_data); 2913aa070789SRoy Zang if (ret_val) 2914aa070789SRoy Zang return ret_val; 2915aa070789SRoy Zang } 29162439e4bfSJean-Christophe PLAGNIOL-VILLARD } 29172439e4bfSJean-Christophe PLAGNIOL-VILLARD 29182439e4bfSJean-Christophe PLAGNIOL-VILLARD /* SW Reset the PHY so all changes take effect */ 29192439e4bfSJean-Christophe PLAGNIOL-VILLARD ret_val = e1000_phy_reset(hw); 2920aa070789SRoy Zang if (ret_val) { 29212439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("Error Resetting the PHY\n"); 29222439e4bfSJean-Christophe PLAGNIOL-VILLARD return ret_val; 29232439e4bfSJean-Christophe PLAGNIOL-VILLARD } 29242439e4bfSJean-Christophe PLAGNIOL-VILLARD 2925aa070789SRoy Zang return E1000_SUCCESS; 2926aa070789SRoy Zang } 29272439e4bfSJean-Christophe PLAGNIOL-VILLARD 2928aa070789SRoy Zang /******************************************************************** 2929aa070789SRoy Zang * Setup auto-negotiation and flow control advertisements, 2930aa070789SRoy Zang * and then perform auto-negotiation. 2931aa070789SRoy Zang * 2932aa070789SRoy Zang * hw - Struct containing variables accessed by shared code 2933aa070789SRoy Zang *********************************************************************/ 2934aa070789SRoy Zang static int32_t 2935aa070789SRoy Zang e1000_copper_link_autoneg(struct e1000_hw *hw) 2936aa070789SRoy Zang { 2937aa070789SRoy Zang int32_t ret_val; 2938aa070789SRoy Zang uint16_t phy_data; 2939aa070789SRoy Zang 2940aa070789SRoy Zang DEBUGFUNC(); 2941aa070789SRoy Zang 29422439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Perform some bounds checking on the hw->autoneg_advertised 29432439e4bfSJean-Christophe PLAGNIOL-VILLARD * parameter. If this variable is zero, then set it to the default. 29442439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 29452439e4bfSJean-Christophe PLAGNIOL-VILLARD hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT; 29462439e4bfSJean-Christophe PLAGNIOL-VILLARD 29472439e4bfSJean-Christophe PLAGNIOL-VILLARD /* If autoneg_advertised is zero, we assume it was not defaulted 29482439e4bfSJean-Christophe PLAGNIOL-VILLARD * by the calling code so we set to advertise full capability. 29492439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 29502439e4bfSJean-Christophe PLAGNIOL-VILLARD if (hw->autoneg_advertised == 0) 29512439e4bfSJean-Christophe PLAGNIOL-VILLARD hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT; 29522439e4bfSJean-Christophe PLAGNIOL-VILLARD 2953aa070789SRoy Zang /* IFE phy only supports 10/100 */ 2954aa070789SRoy Zang if (hw->phy_type == e1000_phy_ife) 2955aa070789SRoy Zang hw->autoneg_advertised &= AUTONEG_ADVERTISE_10_100_ALL; 2956aa070789SRoy Zang 29572439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("Reconfiguring auto-neg advertisement params\n"); 29582439e4bfSJean-Christophe PLAGNIOL-VILLARD ret_val = e1000_phy_setup_autoneg(hw); 2959aa070789SRoy Zang if (ret_val) { 29602439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("Error Setting up Auto-Negotiation\n"); 29612439e4bfSJean-Christophe PLAGNIOL-VILLARD return ret_val; 29622439e4bfSJean-Christophe PLAGNIOL-VILLARD } 29632439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("Restarting Auto-Neg\n"); 29642439e4bfSJean-Christophe PLAGNIOL-VILLARD 29652439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Restart auto-negotiation by setting the Auto Neg Enable bit and 29662439e4bfSJean-Christophe PLAGNIOL-VILLARD * the Auto Neg Restart bit in the PHY control register. 29672439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 2968aa070789SRoy Zang ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data); 2969aa070789SRoy Zang if (ret_val) 2970aa070789SRoy Zang return ret_val; 2971aa070789SRoy Zang 29722439e4bfSJean-Christophe PLAGNIOL-VILLARD phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); 2973aa070789SRoy Zang ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data); 2974aa070789SRoy Zang if (ret_val) 2975aa070789SRoy Zang return ret_val; 2976aa070789SRoy Zang 29772439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Does the user want to wait for Auto-Neg to complete here, or 29782439e4bfSJean-Christophe PLAGNIOL-VILLARD * check at a later time (for example, callback routine). 29792439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 29802439e4bfSJean-Christophe PLAGNIOL-VILLARD /* If we do not wait for autonegtation to complete I 29812439e4bfSJean-Christophe PLAGNIOL-VILLARD * do not see a valid link status. 2982aa070789SRoy Zang * wait_autoneg_complete = 1 . 29832439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 2984aa070789SRoy Zang if (hw->wait_autoneg_complete) { 29852439e4bfSJean-Christophe PLAGNIOL-VILLARD ret_val = e1000_wait_autoneg(hw); 2986aa070789SRoy Zang if (ret_val) { 2987aa070789SRoy Zang DEBUGOUT("Error while waiting for autoneg" 2988aa070789SRoy Zang "to complete\n"); 29892439e4bfSJean-Christophe PLAGNIOL-VILLARD return ret_val; 29902439e4bfSJean-Christophe PLAGNIOL-VILLARD } 2991aa070789SRoy Zang } 29922439e4bfSJean-Christophe PLAGNIOL-VILLARD 2993472d5460SYork Sun hw->get_link_status = true; 2994aa070789SRoy Zang 2995aa070789SRoy Zang return E1000_SUCCESS; 29962439e4bfSJean-Christophe PLAGNIOL-VILLARD } 2997aa070789SRoy Zang 2998aa070789SRoy Zang /****************************************************************************** 2999aa070789SRoy Zang * Config the MAC and the PHY after link is up. 30002439e4bfSJean-Christophe PLAGNIOL-VILLARD * 1) Set up the MAC to the current PHY speed/duplex 30012439e4bfSJean-Christophe PLAGNIOL-VILLARD * if we are on 82543. If we 30022439e4bfSJean-Christophe PLAGNIOL-VILLARD * are on newer silicon, we only need to configure 30032439e4bfSJean-Christophe PLAGNIOL-VILLARD * collision distance in the Transmit Control Register. 30042439e4bfSJean-Christophe PLAGNIOL-VILLARD * 2) Set up flow control on the MAC to that established with 30052439e4bfSJean-Christophe PLAGNIOL-VILLARD * the link partner. 3006aa070789SRoy Zang * 3) Config DSP to improve Gigabit link quality for some PHY revisions. 3007aa070789SRoy Zang * 3008aa070789SRoy Zang * hw - Struct containing variables accessed by shared code 3009aa070789SRoy Zang ******************************************************************************/ 3010aa070789SRoy Zang static int32_t 3011aa070789SRoy Zang e1000_copper_link_postconfig(struct e1000_hw *hw) 3012aa070789SRoy Zang { 3013aa070789SRoy Zang int32_t ret_val; 3014aa070789SRoy Zang DEBUGFUNC(); 3015aa070789SRoy Zang 30162439e4bfSJean-Christophe PLAGNIOL-VILLARD if (hw->mac_type >= e1000_82544) { 30172439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_config_collision_dist(hw); 30182439e4bfSJean-Christophe PLAGNIOL-VILLARD } else { 30192439e4bfSJean-Christophe PLAGNIOL-VILLARD ret_val = e1000_config_mac_to_phy(hw); 3020aa070789SRoy Zang if (ret_val) { 3021aa070789SRoy Zang DEBUGOUT("Error configuring MAC to PHY settings\n"); 30222439e4bfSJean-Christophe PLAGNIOL-VILLARD return ret_val; 30232439e4bfSJean-Christophe PLAGNIOL-VILLARD } 30242439e4bfSJean-Christophe PLAGNIOL-VILLARD } 30252439e4bfSJean-Christophe PLAGNIOL-VILLARD ret_val = e1000_config_fc_after_link_up(hw); 3026aa070789SRoy Zang if (ret_val) { 30272439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("Error Configuring Flow Control\n"); 30282439e4bfSJean-Christophe PLAGNIOL-VILLARD return ret_val; 30292439e4bfSJean-Christophe PLAGNIOL-VILLARD } 3030aa070789SRoy Zang return E1000_SUCCESS; 3031aa070789SRoy Zang } 3032aa070789SRoy Zang 3033aa070789SRoy Zang /****************************************************************************** 3034aa070789SRoy Zang * Detects which PHY is present and setup the speed and duplex 3035aa070789SRoy Zang * 3036aa070789SRoy Zang * hw - Struct containing variables accessed by shared code 3037aa070789SRoy Zang ******************************************************************************/ 3038aa070789SRoy Zang static int 3039aa070789SRoy Zang e1000_setup_copper_link(struct eth_device *nic) 3040aa070789SRoy Zang { 3041aa070789SRoy Zang struct e1000_hw *hw = nic->priv; 3042aa070789SRoy Zang int32_t ret_val; 3043aa070789SRoy Zang uint16_t i; 3044aa070789SRoy Zang uint16_t phy_data; 3045aa070789SRoy Zang uint16_t reg_data; 3046aa070789SRoy Zang 3047aa070789SRoy Zang DEBUGFUNC(); 3048aa070789SRoy Zang 3049aa070789SRoy Zang switch (hw->mac_type) { 3050aa070789SRoy Zang case e1000_80003es2lan: 3051aa070789SRoy Zang case e1000_ich8lan: 3052aa070789SRoy Zang /* Set the mac to wait the maximum time between each 3053aa070789SRoy Zang * iteration and increase the max iterations when 3054aa070789SRoy Zang * polling the phy; this fixes erroneous timeouts at 10Mbps. */ 3055aa070789SRoy Zang ret_val = e1000_write_kmrn_reg(hw, 3056aa070789SRoy Zang GG82563_REG(0x34, 4), 0xFFFF); 3057aa070789SRoy Zang if (ret_val) 3058aa070789SRoy Zang return ret_val; 3059aa070789SRoy Zang ret_val = e1000_read_kmrn_reg(hw, 3060aa070789SRoy Zang GG82563_REG(0x34, 9), ®_data); 3061aa070789SRoy Zang if (ret_val) 3062aa070789SRoy Zang return ret_val; 3063aa070789SRoy Zang reg_data |= 0x3F; 3064aa070789SRoy Zang ret_val = e1000_write_kmrn_reg(hw, 3065aa070789SRoy Zang GG82563_REG(0x34, 9), reg_data); 3066aa070789SRoy Zang if (ret_val) 3067aa070789SRoy Zang return ret_val; 3068aa070789SRoy Zang default: 3069aa070789SRoy Zang break; 3070aa070789SRoy Zang } 3071aa070789SRoy Zang 3072aa070789SRoy Zang /* Check if it is a valid PHY and set PHY mode if necessary. */ 3073aa070789SRoy Zang ret_val = e1000_copper_link_preconfig(hw); 3074aa070789SRoy Zang if (ret_val) 3075aa070789SRoy Zang return ret_val; 3076aa070789SRoy Zang switch (hw->mac_type) { 3077aa070789SRoy Zang case e1000_80003es2lan: 3078aa070789SRoy Zang /* Kumeran registers are written-only */ 3079aa070789SRoy Zang reg_data = 3080aa070789SRoy Zang E1000_KUMCTRLSTA_INB_CTRL_LINK_STATUS_TX_TIMEOUT_DEFAULT; 3081aa070789SRoy Zang reg_data |= E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING; 3082aa070789SRoy Zang ret_val = e1000_write_kmrn_reg(hw, 3083aa070789SRoy Zang E1000_KUMCTRLSTA_OFFSET_INB_CTRL, reg_data); 3084aa070789SRoy Zang if (ret_val) 3085aa070789SRoy Zang return ret_val; 3086aa070789SRoy Zang break; 3087aa070789SRoy Zang default: 3088aa070789SRoy Zang break; 3089aa070789SRoy Zang } 3090aa070789SRoy Zang 3091aa070789SRoy Zang if (hw->phy_type == e1000_phy_igp || 3092aa070789SRoy Zang hw->phy_type == e1000_phy_igp_3 || 3093aa070789SRoy Zang hw->phy_type == e1000_phy_igp_2) { 3094aa070789SRoy Zang ret_val = e1000_copper_link_igp_setup(hw); 3095aa070789SRoy Zang if (ret_val) 3096aa070789SRoy Zang return ret_val; 309795186063SMarek Vasut } else if (hw->phy_type == e1000_phy_m88 || 309895186063SMarek Vasut hw->phy_type == e1000_phy_igb) { 3099aa070789SRoy Zang ret_val = e1000_copper_link_mgp_setup(hw); 3100aa070789SRoy Zang if (ret_val) 3101aa070789SRoy Zang return ret_val; 3102aa070789SRoy Zang } else if (hw->phy_type == e1000_phy_gg82563) { 3103aa070789SRoy Zang ret_val = e1000_copper_link_ggp_setup(hw); 3104aa070789SRoy Zang if (ret_val) 3105aa070789SRoy Zang return ret_val; 3106aa070789SRoy Zang } 3107aa070789SRoy Zang 3108aa070789SRoy Zang /* always auto */ 3109aa070789SRoy Zang /* Setup autoneg and flow control advertisement 3110aa070789SRoy Zang * and perform autonegotiation */ 3111aa070789SRoy Zang ret_val = e1000_copper_link_autoneg(hw); 3112aa070789SRoy Zang if (ret_val) 3113aa070789SRoy Zang return ret_val; 3114aa070789SRoy Zang 3115aa070789SRoy Zang /* Check link status. Wait up to 100 microseconds for link to become 3116aa070789SRoy Zang * valid. 3117aa070789SRoy Zang */ 3118aa070789SRoy Zang for (i = 0; i < 10; i++) { 3119aa070789SRoy Zang ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); 3120aa070789SRoy Zang if (ret_val) 3121aa070789SRoy Zang return ret_val; 3122aa070789SRoy Zang ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); 3123aa070789SRoy Zang if (ret_val) 3124aa070789SRoy Zang return ret_val; 3125aa070789SRoy Zang 3126aa070789SRoy Zang if (phy_data & MII_SR_LINK_STATUS) { 3127aa070789SRoy Zang /* Config the MAC and PHY after link is up */ 3128aa070789SRoy Zang ret_val = e1000_copper_link_postconfig(hw); 3129aa070789SRoy Zang if (ret_val) 3130aa070789SRoy Zang return ret_val; 3131aa070789SRoy Zang 31322439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("Valid link established!!!\n"); 3133aa070789SRoy Zang return E1000_SUCCESS; 31342439e4bfSJean-Christophe PLAGNIOL-VILLARD } 31352439e4bfSJean-Christophe PLAGNIOL-VILLARD udelay(10); 31362439e4bfSJean-Christophe PLAGNIOL-VILLARD } 31372439e4bfSJean-Christophe PLAGNIOL-VILLARD 31382439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("Unable to establish link!!!\n"); 3139aa070789SRoy Zang return E1000_SUCCESS; 31402439e4bfSJean-Christophe PLAGNIOL-VILLARD } 31412439e4bfSJean-Christophe PLAGNIOL-VILLARD 31422439e4bfSJean-Christophe PLAGNIOL-VILLARD /****************************************************************************** 31432439e4bfSJean-Christophe PLAGNIOL-VILLARD * Configures PHY autoneg and flow control advertisement settings 31442439e4bfSJean-Christophe PLAGNIOL-VILLARD * 31452439e4bfSJean-Christophe PLAGNIOL-VILLARD * hw - Struct containing variables accessed by shared code 31462439e4bfSJean-Christophe PLAGNIOL-VILLARD ******************************************************************************/ 3147aa070789SRoy Zang int32_t 31482439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_phy_setup_autoneg(struct e1000_hw *hw) 31492439e4bfSJean-Christophe PLAGNIOL-VILLARD { 3150aa070789SRoy Zang int32_t ret_val; 31512439e4bfSJean-Christophe PLAGNIOL-VILLARD uint16_t mii_autoneg_adv_reg; 31522439e4bfSJean-Christophe PLAGNIOL-VILLARD uint16_t mii_1000t_ctrl_reg; 31532439e4bfSJean-Christophe PLAGNIOL-VILLARD 31542439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGFUNC(); 31552439e4bfSJean-Christophe PLAGNIOL-VILLARD 31562439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Read the MII Auto-Neg Advertisement Register (Address 4). */ 3157aa070789SRoy Zang ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg); 3158aa070789SRoy Zang if (ret_val) 3159aa070789SRoy Zang return ret_val; 31602439e4bfSJean-Christophe PLAGNIOL-VILLARD 3161aa070789SRoy Zang if (hw->phy_type != e1000_phy_ife) { 31622439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Read the MII 1000Base-T Control Register (Address 9). */ 3163aa070789SRoy Zang ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, 3164aa070789SRoy Zang &mii_1000t_ctrl_reg); 3165aa070789SRoy Zang if (ret_val) 3166aa070789SRoy Zang return ret_val; 3167aa070789SRoy Zang } else 3168aa070789SRoy Zang mii_1000t_ctrl_reg = 0; 31692439e4bfSJean-Christophe PLAGNIOL-VILLARD 31702439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Need to parse both autoneg_advertised and fc and set up 31712439e4bfSJean-Christophe PLAGNIOL-VILLARD * the appropriate PHY registers. First we will parse for 31722439e4bfSJean-Christophe PLAGNIOL-VILLARD * autoneg_advertised software override. Since we can advertise 31732439e4bfSJean-Christophe PLAGNIOL-VILLARD * a plethora of combinations, we need to check each bit 31742439e4bfSJean-Christophe PLAGNIOL-VILLARD * individually. 31752439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 31762439e4bfSJean-Christophe PLAGNIOL-VILLARD 31772439e4bfSJean-Christophe PLAGNIOL-VILLARD /* First we clear all the 10/100 mb speed bits in the Auto-Neg 31782439e4bfSJean-Christophe PLAGNIOL-VILLARD * Advertisement Register (Address 4) and the 1000 mb speed bits in 31792439e4bfSJean-Christophe PLAGNIOL-VILLARD * the 1000Base-T Control Register (Address 9). 31802439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 31812439e4bfSJean-Christophe PLAGNIOL-VILLARD mii_autoneg_adv_reg &= ~REG4_SPEED_MASK; 31822439e4bfSJean-Christophe PLAGNIOL-VILLARD mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK; 31832439e4bfSJean-Christophe PLAGNIOL-VILLARD 31842439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("autoneg_advertised %x\n", hw->autoneg_advertised); 31852439e4bfSJean-Christophe PLAGNIOL-VILLARD 31862439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Do we want to advertise 10 Mb Half Duplex? */ 31872439e4bfSJean-Christophe PLAGNIOL-VILLARD if (hw->autoneg_advertised & ADVERTISE_10_HALF) { 31882439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("Advertise 10mb Half duplex\n"); 31892439e4bfSJean-Christophe PLAGNIOL-VILLARD mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS; 31902439e4bfSJean-Christophe PLAGNIOL-VILLARD } 31912439e4bfSJean-Christophe PLAGNIOL-VILLARD 31922439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Do we want to advertise 10 Mb Full Duplex? */ 31932439e4bfSJean-Christophe PLAGNIOL-VILLARD if (hw->autoneg_advertised & ADVERTISE_10_FULL) { 31942439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("Advertise 10mb Full duplex\n"); 31952439e4bfSJean-Christophe PLAGNIOL-VILLARD mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS; 31962439e4bfSJean-Christophe PLAGNIOL-VILLARD } 31972439e4bfSJean-Christophe PLAGNIOL-VILLARD 31982439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Do we want to advertise 100 Mb Half Duplex? */ 31992439e4bfSJean-Christophe PLAGNIOL-VILLARD if (hw->autoneg_advertised & ADVERTISE_100_HALF) { 32002439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("Advertise 100mb Half duplex\n"); 32012439e4bfSJean-Christophe PLAGNIOL-VILLARD mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS; 32022439e4bfSJean-Christophe PLAGNIOL-VILLARD } 32032439e4bfSJean-Christophe PLAGNIOL-VILLARD 32042439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Do we want to advertise 100 Mb Full Duplex? */ 32052439e4bfSJean-Christophe PLAGNIOL-VILLARD if (hw->autoneg_advertised & ADVERTISE_100_FULL) { 32062439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("Advertise 100mb Full duplex\n"); 32072439e4bfSJean-Christophe PLAGNIOL-VILLARD mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS; 32082439e4bfSJean-Christophe PLAGNIOL-VILLARD } 32092439e4bfSJean-Christophe PLAGNIOL-VILLARD 32102439e4bfSJean-Christophe PLAGNIOL-VILLARD /* We do not allow the Phy to advertise 1000 Mb Half Duplex */ 32112439e4bfSJean-Christophe PLAGNIOL-VILLARD if (hw->autoneg_advertised & ADVERTISE_1000_HALF) { 32122439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT 32132439e4bfSJean-Christophe PLAGNIOL-VILLARD ("Advertise 1000mb Half duplex requested, request denied!\n"); 32142439e4bfSJean-Christophe PLAGNIOL-VILLARD } 32152439e4bfSJean-Christophe PLAGNIOL-VILLARD 32162439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Do we want to advertise 1000 Mb Full Duplex? */ 32172439e4bfSJean-Christophe PLAGNIOL-VILLARD if (hw->autoneg_advertised & ADVERTISE_1000_FULL) { 32182439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("Advertise 1000mb Full duplex\n"); 32192439e4bfSJean-Christophe PLAGNIOL-VILLARD mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS; 32202439e4bfSJean-Christophe PLAGNIOL-VILLARD } 32212439e4bfSJean-Christophe PLAGNIOL-VILLARD 32222439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Check for a software override of the flow control settings, and 32232439e4bfSJean-Christophe PLAGNIOL-VILLARD * setup the PHY advertisement registers accordingly. If 32242439e4bfSJean-Christophe PLAGNIOL-VILLARD * auto-negotiation is enabled, then software will have to set the 32252439e4bfSJean-Christophe PLAGNIOL-VILLARD * "PAUSE" bits to the correct value in the Auto-Negotiation 32262439e4bfSJean-Christophe PLAGNIOL-VILLARD * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation. 32272439e4bfSJean-Christophe PLAGNIOL-VILLARD * 32282439e4bfSJean-Christophe PLAGNIOL-VILLARD * The possible values of the "fc" parameter are: 32292439e4bfSJean-Christophe PLAGNIOL-VILLARD * 0: Flow control is completely disabled 32302439e4bfSJean-Christophe PLAGNIOL-VILLARD * 1: Rx flow control is enabled (we can receive pause frames 32312439e4bfSJean-Christophe PLAGNIOL-VILLARD * but not send pause frames). 32322439e4bfSJean-Christophe PLAGNIOL-VILLARD * 2: Tx flow control is enabled (we can send pause frames 32332439e4bfSJean-Christophe PLAGNIOL-VILLARD * but we do not support receiving pause frames). 32342439e4bfSJean-Christophe PLAGNIOL-VILLARD * 3: Both Rx and TX flow control (symmetric) are enabled. 32352439e4bfSJean-Christophe PLAGNIOL-VILLARD * other: No software override. The flow control configuration 32362439e4bfSJean-Christophe PLAGNIOL-VILLARD * in the EEPROM is used. 32372439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 32382439e4bfSJean-Christophe PLAGNIOL-VILLARD switch (hw->fc) { 32392439e4bfSJean-Christophe PLAGNIOL-VILLARD case e1000_fc_none: /* 0 */ 32402439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Flow control (RX & TX) is completely disabled by a 32412439e4bfSJean-Christophe PLAGNIOL-VILLARD * software over-ride. 32422439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 32432439e4bfSJean-Christophe PLAGNIOL-VILLARD mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 32442439e4bfSJean-Christophe PLAGNIOL-VILLARD break; 32452439e4bfSJean-Christophe PLAGNIOL-VILLARD case e1000_fc_rx_pause: /* 1 */ 32462439e4bfSJean-Christophe PLAGNIOL-VILLARD /* RX Flow control is enabled, and TX Flow control is 32472439e4bfSJean-Christophe PLAGNIOL-VILLARD * disabled, by a software over-ride. 32482439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 32492439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Since there really isn't a way to advertise that we are 32502439e4bfSJean-Christophe PLAGNIOL-VILLARD * capable of RX Pause ONLY, we will advertise that we 32512439e4bfSJean-Christophe PLAGNIOL-VILLARD * support both symmetric and asymmetric RX PAUSE. Later 32522439e4bfSJean-Christophe PLAGNIOL-VILLARD * (in e1000_config_fc_after_link_up) we will disable the 32532439e4bfSJean-Christophe PLAGNIOL-VILLARD *hw's ability to send PAUSE frames. 32542439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 32552439e4bfSJean-Christophe PLAGNIOL-VILLARD mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 32562439e4bfSJean-Christophe PLAGNIOL-VILLARD break; 32572439e4bfSJean-Christophe PLAGNIOL-VILLARD case e1000_fc_tx_pause: /* 2 */ 32582439e4bfSJean-Christophe PLAGNIOL-VILLARD /* TX Flow control is enabled, and RX Flow control is 32592439e4bfSJean-Christophe PLAGNIOL-VILLARD * disabled, by a software over-ride. 32602439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 32612439e4bfSJean-Christophe PLAGNIOL-VILLARD mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR; 32622439e4bfSJean-Christophe PLAGNIOL-VILLARD mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE; 32632439e4bfSJean-Christophe PLAGNIOL-VILLARD break; 32642439e4bfSJean-Christophe PLAGNIOL-VILLARD case e1000_fc_full: /* 3 */ 32652439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Flow control (both RX and TX) is enabled by a software 32662439e4bfSJean-Christophe PLAGNIOL-VILLARD * over-ride. 32672439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 32682439e4bfSJean-Christophe PLAGNIOL-VILLARD mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 32692439e4bfSJean-Christophe PLAGNIOL-VILLARD break; 32702439e4bfSJean-Christophe PLAGNIOL-VILLARD default: 32712439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("Flow control param set incorrectly\n"); 32722439e4bfSJean-Christophe PLAGNIOL-VILLARD return -E1000_ERR_CONFIG; 32732439e4bfSJean-Christophe PLAGNIOL-VILLARD } 32742439e4bfSJean-Christophe PLAGNIOL-VILLARD 3275aa070789SRoy Zang ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg); 3276aa070789SRoy Zang if (ret_val) 3277aa070789SRoy Zang return ret_val; 32782439e4bfSJean-Christophe PLAGNIOL-VILLARD 32792439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); 32802439e4bfSJean-Christophe PLAGNIOL-VILLARD 3281aa070789SRoy Zang if (hw->phy_type != e1000_phy_ife) { 3282aa070789SRoy Zang ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, 3283aa070789SRoy Zang mii_1000t_ctrl_reg); 3284aa070789SRoy Zang if (ret_val) 3285aa070789SRoy Zang return ret_val; 32862439e4bfSJean-Christophe PLAGNIOL-VILLARD } 3287aa070789SRoy Zang 3288aa070789SRoy Zang return E1000_SUCCESS; 32892439e4bfSJean-Christophe PLAGNIOL-VILLARD } 32902439e4bfSJean-Christophe PLAGNIOL-VILLARD 32912439e4bfSJean-Christophe PLAGNIOL-VILLARD /****************************************************************************** 32922439e4bfSJean-Christophe PLAGNIOL-VILLARD * Sets the collision distance in the Transmit Control register 32932439e4bfSJean-Christophe PLAGNIOL-VILLARD * 32942439e4bfSJean-Christophe PLAGNIOL-VILLARD * hw - Struct containing variables accessed by shared code 32952439e4bfSJean-Christophe PLAGNIOL-VILLARD * 32962439e4bfSJean-Christophe PLAGNIOL-VILLARD * Link should have been established previously. Reads the speed and duplex 32972439e4bfSJean-Christophe PLAGNIOL-VILLARD * information from the Device Status register. 32982439e4bfSJean-Christophe PLAGNIOL-VILLARD ******************************************************************************/ 32992439e4bfSJean-Christophe PLAGNIOL-VILLARD static void 33002439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_config_collision_dist(struct e1000_hw *hw) 33012439e4bfSJean-Christophe PLAGNIOL-VILLARD { 3302aa070789SRoy Zang uint32_t tctl, coll_dist; 3303aa070789SRoy Zang 3304aa070789SRoy Zang DEBUGFUNC(); 3305aa070789SRoy Zang 3306aa070789SRoy Zang if (hw->mac_type < e1000_82543) 3307aa070789SRoy Zang coll_dist = E1000_COLLISION_DISTANCE_82542; 3308aa070789SRoy Zang else 3309aa070789SRoy Zang coll_dist = E1000_COLLISION_DISTANCE; 33102439e4bfSJean-Christophe PLAGNIOL-VILLARD 33112439e4bfSJean-Christophe PLAGNIOL-VILLARD tctl = E1000_READ_REG(hw, TCTL); 33122439e4bfSJean-Christophe PLAGNIOL-VILLARD 33132439e4bfSJean-Christophe PLAGNIOL-VILLARD tctl &= ~E1000_TCTL_COLD; 3314aa070789SRoy Zang tctl |= coll_dist << E1000_COLD_SHIFT; 33152439e4bfSJean-Christophe PLAGNIOL-VILLARD 33162439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, TCTL, tctl); 33172439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_FLUSH(hw); 33182439e4bfSJean-Christophe PLAGNIOL-VILLARD } 33192439e4bfSJean-Christophe PLAGNIOL-VILLARD 33202439e4bfSJean-Christophe PLAGNIOL-VILLARD /****************************************************************************** 33212439e4bfSJean-Christophe PLAGNIOL-VILLARD * Sets MAC speed and duplex settings to reflect the those in the PHY 33222439e4bfSJean-Christophe PLAGNIOL-VILLARD * 33232439e4bfSJean-Christophe PLAGNIOL-VILLARD * hw - Struct containing variables accessed by shared code 33242439e4bfSJean-Christophe PLAGNIOL-VILLARD * mii_reg - data to write to the MII control register 33252439e4bfSJean-Christophe PLAGNIOL-VILLARD * 33262439e4bfSJean-Christophe PLAGNIOL-VILLARD * The contents of the PHY register containing the needed information need to 33272439e4bfSJean-Christophe PLAGNIOL-VILLARD * be passed in. 33282439e4bfSJean-Christophe PLAGNIOL-VILLARD ******************************************************************************/ 33292439e4bfSJean-Christophe PLAGNIOL-VILLARD static int 33302439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_config_mac_to_phy(struct e1000_hw *hw) 33312439e4bfSJean-Christophe PLAGNIOL-VILLARD { 33322439e4bfSJean-Christophe PLAGNIOL-VILLARD uint32_t ctrl; 33332439e4bfSJean-Christophe PLAGNIOL-VILLARD uint16_t phy_data; 33342439e4bfSJean-Christophe PLAGNIOL-VILLARD 33352439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGFUNC(); 33362439e4bfSJean-Christophe PLAGNIOL-VILLARD 33372439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Read the Device Control Register and set the bits to Force Speed 33382439e4bfSJean-Christophe PLAGNIOL-VILLARD * and Duplex. 33392439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 33402439e4bfSJean-Christophe PLAGNIOL-VILLARD ctrl = E1000_READ_REG(hw, CTRL); 33412439e4bfSJean-Christophe PLAGNIOL-VILLARD ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 334295186063SMarek Vasut ctrl &= ~(E1000_CTRL_ILOS); 334395186063SMarek Vasut ctrl |= (E1000_CTRL_SPD_SEL); 33442439e4bfSJean-Christophe PLAGNIOL-VILLARD 33452439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Set up duplex in the Device Control and Transmit Control 33462439e4bfSJean-Christophe PLAGNIOL-VILLARD * registers depending on negotiated values. 33472439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 33482439e4bfSJean-Christophe PLAGNIOL-VILLARD if (e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data) < 0) { 33492439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("PHY Read Error\n"); 33502439e4bfSJean-Christophe PLAGNIOL-VILLARD return -E1000_ERR_PHY; 33512439e4bfSJean-Christophe PLAGNIOL-VILLARD } 33522439e4bfSJean-Christophe PLAGNIOL-VILLARD if (phy_data & M88E1000_PSSR_DPLX) 33532439e4bfSJean-Christophe PLAGNIOL-VILLARD ctrl |= E1000_CTRL_FD; 33542439e4bfSJean-Christophe PLAGNIOL-VILLARD else 33552439e4bfSJean-Christophe PLAGNIOL-VILLARD ctrl &= ~E1000_CTRL_FD; 33562439e4bfSJean-Christophe PLAGNIOL-VILLARD 33572439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_config_collision_dist(hw); 33582439e4bfSJean-Christophe PLAGNIOL-VILLARD 33592439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Set up speed in the Device Control register depending on 33602439e4bfSJean-Christophe PLAGNIOL-VILLARD * negotiated values. 33612439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 33622439e4bfSJean-Christophe PLAGNIOL-VILLARD if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) 33632439e4bfSJean-Christophe PLAGNIOL-VILLARD ctrl |= E1000_CTRL_SPD_1000; 33642439e4bfSJean-Christophe PLAGNIOL-VILLARD else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS) 33652439e4bfSJean-Christophe PLAGNIOL-VILLARD ctrl |= E1000_CTRL_SPD_100; 33662439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Write the configured values back to the Device Control Reg. */ 33672439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, CTRL, ctrl); 33682439e4bfSJean-Christophe PLAGNIOL-VILLARD return 0; 33692439e4bfSJean-Christophe PLAGNIOL-VILLARD } 33702439e4bfSJean-Christophe PLAGNIOL-VILLARD 33712439e4bfSJean-Christophe PLAGNIOL-VILLARD /****************************************************************************** 33722439e4bfSJean-Christophe PLAGNIOL-VILLARD * Forces the MAC's flow control settings. 33732439e4bfSJean-Christophe PLAGNIOL-VILLARD * 33742439e4bfSJean-Christophe PLAGNIOL-VILLARD * hw - Struct containing variables accessed by shared code 33752439e4bfSJean-Christophe PLAGNIOL-VILLARD * 33762439e4bfSJean-Christophe PLAGNIOL-VILLARD * Sets the TFCE and RFCE bits in the device control register to reflect 33772439e4bfSJean-Christophe PLAGNIOL-VILLARD * the adapter settings. TFCE and RFCE need to be explicitly set by 33782439e4bfSJean-Christophe PLAGNIOL-VILLARD * software when a Copper PHY is used because autonegotiation is managed 33792439e4bfSJean-Christophe PLAGNIOL-VILLARD * by the PHY rather than the MAC. Software must also configure these 33802439e4bfSJean-Christophe PLAGNIOL-VILLARD * bits when link is forced on a fiber connection. 33812439e4bfSJean-Christophe PLAGNIOL-VILLARD *****************************************************************************/ 33822439e4bfSJean-Christophe PLAGNIOL-VILLARD static int 33832439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_force_mac_fc(struct e1000_hw *hw) 33842439e4bfSJean-Christophe PLAGNIOL-VILLARD { 33852439e4bfSJean-Christophe PLAGNIOL-VILLARD uint32_t ctrl; 33862439e4bfSJean-Christophe PLAGNIOL-VILLARD 33872439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGFUNC(); 33882439e4bfSJean-Christophe PLAGNIOL-VILLARD 33892439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Get the current configuration of the Device Control Register */ 33902439e4bfSJean-Christophe PLAGNIOL-VILLARD ctrl = E1000_READ_REG(hw, CTRL); 33912439e4bfSJean-Christophe PLAGNIOL-VILLARD 33922439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Because we didn't get link via the internal auto-negotiation 33932439e4bfSJean-Christophe PLAGNIOL-VILLARD * mechanism (we either forced link or we got link via PHY 33942439e4bfSJean-Christophe PLAGNIOL-VILLARD * auto-neg), we have to manually enable/disable transmit an 33952439e4bfSJean-Christophe PLAGNIOL-VILLARD * receive flow control. 33962439e4bfSJean-Christophe PLAGNIOL-VILLARD * 33972439e4bfSJean-Christophe PLAGNIOL-VILLARD * The "Case" statement below enables/disable flow control 33982439e4bfSJean-Christophe PLAGNIOL-VILLARD * according to the "hw->fc" parameter. 33992439e4bfSJean-Christophe PLAGNIOL-VILLARD * 34002439e4bfSJean-Christophe PLAGNIOL-VILLARD * The possible values of the "fc" parameter are: 34012439e4bfSJean-Christophe PLAGNIOL-VILLARD * 0: Flow control is completely disabled 34022439e4bfSJean-Christophe PLAGNIOL-VILLARD * 1: Rx flow control is enabled (we can receive pause 34032439e4bfSJean-Christophe PLAGNIOL-VILLARD * frames but not send pause frames). 34042439e4bfSJean-Christophe PLAGNIOL-VILLARD * 2: Tx flow control is enabled (we can send pause frames 34052439e4bfSJean-Christophe PLAGNIOL-VILLARD * frames but we do not receive pause frames). 34062439e4bfSJean-Christophe PLAGNIOL-VILLARD * 3: Both Rx and TX flow control (symmetric) is enabled. 34072439e4bfSJean-Christophe PLAGNIOL-VILLARD * other: No other values should be possible at this point. 34082439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 34092439e4bfSJean-Christophe PLAGNIOL-VILLARD 34102439e4bfSJean-Christophe PLAGNIOL-VILLARD switch (hw->fc) { 34112439e4bfSJean-Christophe PLAGNIOL-VILLARD case e1000_fc_none: 34122439e4bfSJean-Christophe PLAGNIOL-VILLARD ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE)); 34132439e4bfSJean-Christophe PLAGNIOL-VILLARD break; 34142439e4bfSJean-Christophe PLAGNIOL-VILLARD case e1000_fc_rx_pause: 34152439e4bfSJean-Christophe PLAGNIOL-VILLARD ctrl &= (~E1000_CTRL_TFCE); 34162439e4bfSJean-Christophe PLAGNIOL-VILLARD ctrl |= E1000_CTRL_RFCE; 34172439e4bfSJean-Christophe PLAGNIOL-VILLARD break; 34182439e4bfSJean-Christophe PLAGNIOL-VILLARD case e1000_fc_tx_pause: 34192439e4bfSJean-Christophe PLAGNIOL-VILLARD ctrl &= (~E1000_CTRL_RFCE); 34202439e4bfSJean-Christophe PLAGNIOL-VILLARD ctrl |= E1000_CTRL_TFCE; 34212439e4bfSJean-Christophe PLAGNIOL-VILLARD break; 34222439e4bfSJean-Christophe PLAGNIOL-VILLARD case e1000_fc_full: 34232439e4bfSJean-Christophe PLAGNIOL-VILLARD ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE); 34242439e4bfSJean-Christophe PLAGNIOL-VILLARD break; 34252439e4bfSJean-Christophe PLAGNIOL-VILLARD default: 34262439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("Flow control param set incorrectly\n"); 34272439e4bfSJean-Christophe PLAGNIOL-VILLARD return -E1000_ERR_CONFIG; 34282439e4bfSJean-Christophe PLAGNIOL-VILLARD } 34292439e4bfSJean-Christophe PLAGNIOL-VILLARD 34302439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Disable TX Flow Control for 82542 (rev 2.0) */ 34312439e4bfSJean-Christophe PLAGNIOL-VILLARD if (hw->mac_type == e1000_82542_rev2_0) 34322439e4bfSJean-Christophe PLAGNIOL-VILLARD ctrl &= (~E1000_CTRL_TFCE); 34332439e4bfSJean-Christophe PLAGNIOL-VILLARD 34342439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, CTRL, ctrl); 34352439e4bfSJean-Christophe PLAGNIOL-VILLARD return 0; 34362439e4bfSJean-Christophe PLAGNIOL-VILLARD } 34372439e4bfSJean-Christophe PLAGNIOL-VILLARD 34382439e4bfSJean-Christophe PLAGNIOL-VILLARD /****************************************************************************** 34392439e4bfSJean-Christophe PLAGNIOL-VILLARD * Configures flow control settings after link is established 34402439e4bfSJean-Christophe PLAGNIOL-VILLARD * 34412439e4bfSJean-Christophe PLAGNIOL-VILLARD * hw - Struct containing variables accessed by shared code 34422439e4bfSJean-Christophe PLAGNIOL-VILLARD * 34432439e4bfSJean-Christophe PLAGNIOL-VILLARD * Should be called immediately after a valid link has been established. 34442439e4bfSJean-Christophe PLAGNIOL-VILLARD * Forces MAC flow control settings if link was forced. When in MII/GMII mode 34452439e4bfSJean-Christophe PLAGNIOL-VILLARD * and autonegotiation is enabled, the MAC flow control settings will be set 34462439e4bfSJean-Christophe PLAGNIOL-VILLARD * based on the flow control negotiated by the PHY. In TBI mode, the TFCE 34472439e4bfSJean-Christophe PLAGNIOL-VILLARD * and RFCE bits will be automaticaly set to the negotiated flow control mode. 34482439e4bfSJean-Christophe PLAGNIOL-VILLARD *****************************************************************************/ 3449aa070789SRoy Zang static int32_t 34502439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_config_fc_after_link_up(struct e1000_hw *hw) 34512439e4bfSJean-Christophe PLAGNIOL-VILLARD { 34522439e4bfSJean-Christophe PLAGNIOL-VILLARD int32_t ret_val; 34532439e4bfSJean-Christophe PLAGNIOL-VILLARD uint16_t mii_status_reg; 34542439e4bfSJean-Christophe PLAGNIOL-VILLARD uint16_t mii_nway_adv_reg; 34552439e4bfSJean-Christophe PLAGNIOL-VILLARD uint16_t mii_nway_lp_ability_reg; 34562439e4bfSJean-Christophe PLAGNIOL-VILLARD uint16_t speed; 34572439e4bfSJean-Christophe PLAGNIOL-VILLARD uint16_t duplex; 34582439e4bfSJean-Christophe PLAGNIOL-VILLARD 34592439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGFUNC(); 34602439e4bfSJean-Christophe PLAGNIOL-VILLARD 34612439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Check for the case where we have fiber media and auto-neg failed 34622439e4bfSJean-Christophe PLAGNIOL-VILLARD * so we had to force link. In this case, we need to force the 34632439e4bfSJean-Christophe PLAGNIOL-VILLARD * configuration of the MAC to match the "fc" parameter. 34642439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 3465aa070789SRoy Zang if (((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed)) 3466aa070789SRoy Zang || ((hw->media_type == e1000_media_type_internal_serdes) 3467aa070789SRoy Zang && (hw->autoneg_failed)) 3468aa070789SRoy Zang || ((hw->media_type == e1000_media_type_copper) 3469aa070789SRoy Zang && (!hw->autoneg))) { 34702439e4bfSJean-Christophe PLAGNIOL-VILLARD ret_val = e1000_force_mac_fc(hw); 34712439e4bfSJean-Christophe PLAGNIOL-VILLARD if (ret_val < 0) { 34722439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("Error forcing flow control settings\n"); 34732439e4bfSJean-Christophe PLAGNIOL-VILLARD return ret_val; 34742439e4bfSJean-Christophe PLAGNIOL-VILLARD } 34752439e4bfSJean-Christophe PLAGNIOL-VILLARD } 34762439e4bfSJean-Christophe PLAGNIOL-VILLARD 34772439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Check for the case where we have copper media and auto-neg is 34782439e4bfSJean-Christophe PLAGNIOL-VILLARD * enabled. In this case, we need to check and see if Auto-Neg 34792439e4bfSJean-Christophe PLAGNIOL-VILLARD * has completed, and if so, how the PHY and link partner has 34802439e4bfSJean-Christophe PLAGNIOL-VILLARD * flow control configured. 34812439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 34822439e4bfSJean-Christophe PLAGNIOL-VILLARD if (hw->media_type == e1000_media_type_copper) { 34832439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Read the MII Status Register and check to see if AutoNeg 34842439e4bfSJean-Christophe PLAGNIOL-VILLARD * has completed. We read this twice because this reg has 34852439e4bfSJean-Christophe PLAGNIOL-VILLARD * some "sticky" (latched) bits. 34862439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 34872439e4bfSJean-Christophe PLAGNIOL-VILLARD if (e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) { 34882439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("PHY Read Error \n"); 34892439e4bfSJean-Christophe PLAGNIOL-VILLARD return -E1000_ERR_PHY; 34902439e4bfSJean-Christophe PLAGNIOL-VILLARD } 34912439e4bfSJean-Christophe PLAGNIOL-VILLARD if (e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) { 34922439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("PHY Read Error \n"); 34932439e4bfSJean-Christophe PLAGNIOL-VILLARD return -E1000_ERR_PHY; 34942439e4bfSJean-Christophe PLAGNIOL-VILLARD } 34952439e4bfSJean-Christophe PLAGNIOL-VILLARD 34962439e4bfSJean-Christophe PLAGNIOL-VILLARD if (mii_status_reg & MII_SR_AUTONEG_COMPLETE) { 34972439e4bfSJean-Christophe PLAGNIOL-VILLARD /* The AutoNeg process has completed, so we now need to 34982439e4bfSJean-Christophe PLAGNIOL-VILLARD * read both the Auto Negotiation Advertisement Register 34992439e4bfSJean-Christophe PLAGNIOL-VILLARD * (Address 4) and the Auto_Negotiation Base Page Ability 35002439e4bfSJean-Christophe PLAGNIOL-VILLARD * Register (Address 5) to determine how flow control was 35012439e4bfSJean-Christophe PLAGNIOL-VILLARD * negotiated. 35022439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 35032439e4bfSJean-Christophe PLAGNIOL-VILLARD if (e1000_read_phy_reg 35042439e4bfSJean-Christophe PLAGNIOL-VILLARD (hw, PHY_AUTONEG_ADV, &mii_nway_adv_reg) < 0) { 35052439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("PHY Read Error\n"); 35062439e4bfSJean-Christophe PLAGNIOL-VILLARD return -E1000_ERR_PHY; 35072439e4bfSJean-Christophe PLAGNIOL-VILLARD } 35082439e4bfSJean-Christophe PLAGNIOL-VILLARD if (e1000_read_phy_reg 35092439e4bfSJean-Christophe PLAGNIOL-VILLARD (hw, PHY_LP_ABILITY, 35102439e4bfSJean-Christophe PLAGNIOL-VILLARD &mii_nway_lp_ability_reg) < 0) { 35112439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("PHY Read Error\n"); 35122439e4bfSJean-Christophe PLAGNIOL-VILLARD return -E1000_ERR_PHY; 35132439e4bfSJean-Christophe PLAGNIOL-VILLARD } 35142439e4bfSJean-Christophe PLAGNIOL-VILLARD 35152439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Two bits in the Auto Negotiation Advertisement Register 35162439e4bfSJean-Christophe PLAGNIOL-VILLARD * (Address 4) and two bits in the Auto Negotiation Base 35172439e4bfSJean-Christophe PLAGNIOL-VILLARD * Page Ability Register (Address 5) determine flow control 35182439e4bfSJean-Christophe PLAGNIOL-VILLARD * for both the PHY and the link partner. The following 35192439e4bfSJean-Christophe PLAGNIOL-VILLARD * table, taken out of the IEEE 802.3ab/D6.0 dated March 25, 35202439e4bfSJean-Christophe PLAGNIOL-VILLARD * 1999, describes these PAUSE resolution bits and how flow 35212439e4bfSJean-Christophe PLAGNIOL-VILLARD * control is determined based upon these settings. 35222439e4bfSJean-Christophe PLAGNIOL-VILLARD * NOTE: DC = Don't Care 35232439e4bfSJean-Christophe PLAGNIOL-VILLARD * 35242439e4bfSJean-Christophe PLAGNIOL-VILLARD * LOCAL DEVICE | LINK PARTNER 35252439e4bfSJean-Christophe PLAGNIOL-VILLARD * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution 35262439e4bfSJean-Christophe PLAGNIOL-VILLARD *-------|---------|-------|---------|-------------------- 35272439e4bfSJean-Christophe PLAGNIOL-VILLARD * 0 | 0 | DC | DC | e1000_fc_none 35282439e4bfSJean-Christophe PLAGNIOL-VILLARD * 0 | 1 | 0 | DC | e1000_fc_none 35292439e4bfSJean-Christophe PLAGNIOL-VILLARD * 0 | 1 | 1 | 0 | e1000_fc_none 35302439e4bfSJean-Christophe PLAGNIOL-VILLARD * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 35312439e4bfSJean-Christophe PLAGNIOL-VILLARD * 1 | 0 | 0 | DC | e1000_fc_none 35322439e4bfSJean-Christophe PLAGNIOL-VILLARD * 1 | DC | 1 | DC | e1000_fc_full 35332439e4bfSJean-Christophe PLAGNIOL-VILLARD * 1 | 1 | 0 | 0 | e1000_fc_none 35342439e4bfSJean-Christophe PLAGNIOL-VILLARD * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 35352439e4bfSJean-Christophe PLAGNIOL-VILLARD * 35362439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 35372439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Are both PAUSE bits set to 1? If so, this implies 35382439e4bfSJean-Christophe PLAGNIOL-VILLARD * Symmetric Flow Control is enabled at both ends. The 35392439e4bfSJean-Christophe PLAGNIOL-VILLARD * ASM_DIR bits are irrelevant per the spec. 35402439e4bfSJean-Christophe PLAGNIOL-VILLARD * 35412439e4bfSJean-Christophe PLAGNIOL-VILLARD * For Symmetric Flow Control: 35422439e4bfSJean-Christophe PLAGNIOL-VILLARD * 35432439e4bfSJean-Christophe PLAGNIOL-VILLARD * LOCAL DEVICE | LINK PARTNER 35442439e4bfSJean-Christophe PLAGNIOL-VILLARD * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 35452439e4bfSJean-Christophe PLAGNIOL-VILLARD *-------|---------|-------|---------|-------------------- 35462439e4bfSJean-Christophe PLAGNIOL-VILLARD * 1 | DC | 1 | DC | e1000_fc_full 35472439e4bfSJean-Christophe PLAGNIOL-VILLARD * 35482439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 35492439e4bfSJean-Christophe PLAGNIOL-VILLARD if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 35502439e4bfSJean-Christophe PLAGNIOL-VILLARD (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) { 35512439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Now we need to check if the user selected RX ONLY 35522439e4bfSJean-Christophe PLAGNIOL-VILLARD * of pause frames. In this case, we had to advertise 35532439e4bfSJean-Christophe PLAGNIOL-VILLARD * FULL flow control because we could not advertise RX 35542439e4bfSJean-Christophe PLAGNIOL-VILLARD * ONLY. Hence, we must now check to see if we need to 35552439e4bfSJean-Christophe PLAGNIOL-VILLARD * turn OFF the TRANSMISSION of PAUSE frames. 35562439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 35572439e4bfSJean-Christophe PLAGNIOL-VILLARD if (hw->original_fc == e1000_fc_full) { 35582439e4bfSJean-Christophe PLAGNIOL-VILLARD hw->fc = e1000_fc_full; 35592439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("Flow Control = FULL.\r\n"); 35602439e4bfSJean-Christophe PLAGNIOL-VILLARD } else { 35612439e4bfSJean-Christophe PLAGNIOL-VILLARD hw->fc = e1000_fc_rx_pause; 35622439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT 35632439e4bfSJean-Christophe PLAGNIOL-VILLARD ("Flow Control = RX PAUSE frames only.\r\n"); 35642439e4bfSJean-Christophe PLAGNIOL-VILLARD } 35652439e4bfSJean-Christophe PLAGNIOL-VILLARD } 35662439e4bfSJean-Christophe PLAGNIOL-VILLARD /* For receiving PAUSE frames ONLY. 35672439e4bfSJean-Christophe PLAGNIOL-VILLARD * 35682439e4bfSJean-Christophe PLAGNIOL-VILLARD * LOCAL DEVICE | LINK PARTNER 35692439e4bfSJean-Christophe PLAGNIOL-VILLARD * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 35702439e4bfSJean-Christophe PLAGNIOL-VILLARD *-------|---------|-------|---------|-------------------- 35712439e4bfSJean-Christophe PLAGNIOL-VILLARD * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 35722439e4bfSJean-Christophe PLAGNIOL-VILLARD * 35732439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 35742439e4bfSJean-Christophe PLAGNIOL-VILLARD else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) && 35752439e4bfSJean-Christophe PLAGNIOL-VILLARD (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 35762439e4bfSJean-Christophe PLAGNIOL-VILLARD (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 35772439e4bfSJean-Christophe PLAGNIOL-VILLARD (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) 35782439e4bfSJean-Christophe PLAGNIOL-VILLARD { 35792439e4bfSJean-Christophe PLAGNIOL-VILLARD hw->fc = e1000_fc_tx_pause; 35802439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT 35812439e4bfSJean-Christophe PLAGNIOL-VILLARD ("Flow Control = TX PAUSE frames only.\r\n"); 35822439e4bfSJean-Christophe PLAGNIOL-VILLARD } 35832439e4bfSJean-Christophe PLAGNIOL-VILLARD /* For transmitting PAUSE frames ONLY. 35842439e4bfSJean-Christophe PLAGNIOL-VILLARD * 35852439e4bfSJean-Christophe PLAGNIOL-VILLARD * LOCAL DEVICE | LINK PARTNER 35862439e4bfSJean-Christophe PLAGNIOL-VILLARD * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 35872439e4bfSJean-Christophe PLAGNIOL-VILLARD *-------|---------|-------|---------|-------------------- 35882439e4bfSJean-Christophe PLAGNIOL-VILLARD * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 35892439e4bfSJean-Christophe PLAGNIOL-VILLARD * 35902439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 35912439e4bfSJean-Christophe PLAGNIOL-VILLARD else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 35922439e4bfSJean-Christophe PLAGNIOL-VILLARD (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 35932439e4bfSJean-Christophe PLAGNIOL-VILLARD !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 35942439e4bfSJean-Christophe PLAGNIOL-VILLARD (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) 35952439e4bfSJean-Christophe PLAGNIOL-VILLARD { 35962439e4bfSJean-Christophe PLAGNIOL-VILLARD hw->fc = e1000_fc_rx_pause; 35972439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT 35982439e4bfSJean-Christophe PLAGNIOL-VILLARD ("Flow Control = RX PAUSE frames only.\r\n"); 35992439e4bfSJean-Christophe PLAGNIOL-VILLARD } 36002439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Per the IEEE spec, at this point flow control should be 36012439e4bfSJean-Christophe PLAGNIOL-VILLARD * disabled. However, we want to consider that we could 36022439e4bfSJean-Christophe PLAGNIOL-VILLARD * be connected to a legacy switch that doesn't advertise 36032439e4bfSJean-Christophe PLAGNIOL-VILLARD * desired flow control, but can be forced on the link 36042439e4bfSJean-Christophe PLAGNIOL-VILLARD * partner. So if we advertised no flow control, that is 36052439e4bfSJean-Christophe PLAGNIOL-VILLARD * what we will resolve to. If we advertised some kind of 36062439e4bfSJean-Christophe PLAGNIOL-VILLARD * receive capability (Rx Pause Only or Full Flow Control) 36072439e4bfSJean-Christophe PLAGNIOL-VILLARD * and the link partner advertised none, we will configure 36082439e4bfSJean-Christophe PLAGNIOL-VILLARD * ourselves to enable Rx Flow Control only. We can do 36092439e4bfSJean-Christophe PLAGNIOL-VILLARD * this safely for two reasons: If the link partner really 36102439e4bfSJean-Christophe PLAGNIOL-VILLARD * didn't want flow control enabled, and we enable Rx, no 36112439e4bfSJean-Christophe PLAGNIOL-VILLARD * harm done since we won't be receiving any PAUSE frames 36122439e4bfSJean-Christophe PLAGNIOL-VILLARD * anyway. If the intent on the link partner was to have 36132439e4bfSJean-Christophe PLAGNIOL-VILLARD * flow control enabled, then by us enabling RX only, we 36142439e4bfSJean-Christophe PLAGNIOL-VILLARD * can at least receive pause frames and process them. 36152439e4bfSJean-Christophe PLAGNIOL-VILLARD * This is a good idea because in most cases, since we are 36162439e4bfSJean-Christophe PLAGNIOL-VILLARD * predominantly a server NIC, more times than not we will 36172439e4bfSJean-Christophe PLAGNIOL-VILLARD * be asked to delay transmission of packets than asking 36182439e4bfSJean-Christophe PLAGNIOL-VILLARD * our link partner to pause transmission of frames. 36192439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 36202439e4bfSJean-Christophe PLAGNIOL-VILLARD else if (hw->original_fc == e1000_fc_none || 36212439e4bfSJean-Christophe PLAGNIOL-VILLARD hw->original_fc == e1000_fc_tx_pause) { 36222439e4bfSJean-Christophe PLAGNIOL-VILLARD hw->fc = e1000_fc_none; 36232439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("Flow Control = NONE.\r\n"); 36242439e4bfSJean-Christophe PLAGNIOL-VILLARD } else { 36252439e4bfSJean-Christophe PLAGNIOL-VILLARD hw->fc = e1000_fc_rx_pause; 36262439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT 36272439e4bfSJean-Christophe PLAGNIOL-VILLARD ("Flow Control = RX PAUSE frames only.\r\n"); 36282439e4bfSJean-Christophe PLAGNIOL-VILLARD } 36292439e4bfSJean-Christophe PLAGNIOL-VILLARD 36302439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Now we need to do one last check... If we auto- 36312439e4bfSJean-Christophe PLAGNIOL-VILLARD * negotiated to HALF DUPLEX, flow control should not be 36322439e4bfSJean-Christophe PLAGNIOL-VILLARD * enabled per IEEE 802.3 spec. 36332439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 36342439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_get_speed_and_duplex(hw, &speed, &duplex); 36352439e4bfSJean-Christophe PLAGNIOL-VILLARD 36362439e4bfSJean-Christophe PLAGNIOL-VILLARD if (duplex == HALF_DUPLEX) 36372439e4bfSJean-Christophe PLAGNIOL-VILLARD hw->fc = e1000_fc_none; 36382439e4bfSJean-Christophe PLAGNIOL-VILLARD 36392439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Now we call a subroutine to actually force the MAC 36402439e4bfSJean-Christophe PLAGNIOL-VILLARD * controller to use the correct flow control settings. 36412439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 36422439e4bfSJean-Christophe PLAGNIOL-VILLARD ret_val = e1000_force_mac_fc(hw); 36432439e4bfSJean-Christophe PLAGNIOL-VILLARD if (ret_val < 0) { 36442439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT 36452439e4bfSJean-Christophe PLAGNIOL-VILLARD ("Error forcing flow control settings\n"); 36462439e4bfSJean-Christophe PLAGNIOL-VILLARD return ret_val; 36472439e4bfSJean-Christophe PLAGNIOL-VILLARD } 36482439e4bfSJean-Christophe PLAGNIOL-VILLARD } else { 36492439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT 36502439e4bfSJean-Christophe PLAGNIOL-VILLARD ("Copper PHY and Auto Neg has not completed.\r\n"); 36512439e4bfSJean-Christophe PLAGNIOL-VILLARD } 36522439e4bfSJean-Christophe PLAGNIOL-VILLARD } 3653aa070789SRoy Zang return E1000_SUCCESS; 36542439e4bfSJean-Christophe PLAGNIOL-VILLARD } 36552439e4bfSJean-Christophe PLAGNIOL-VILLARD 36562439e4bfSJean-Christophe PLAGNIOL-VILLARD /****************************************************************************** 36572439e4bfSJean-Christophe PLAGNIOL-VILLARD * Checks to see if the link status of the hardware has changed. 36582439e4bfSJean-Christophe PLAGNIOL-VILLARD * 36592439e4bfSJean-Christophe PLAGNIOL-VILLARD * hw - Struct containing variables accessed by shared code 36602439e4bfSJean-Christophe PLAGNIOL-VILLARD * 36612439e4bfSJean-Christophe PLAGNIOL-VILLARD * Called by any function that needs to check the link status of the adapter. 36622439e4bfSJean-Christophe PLAGNIOL-VILLARD *****************************************************************************/ 36632439e4bfSJean-Christophe PLAGNIOL-VILLARD static int 36642439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_check_for_link(struct eth_device *nic) 36652439e4bfSJean-Christophe PLAGNIOL-VILLARD { 36662439e4bfSJean-Christophe PLAGNIOL-VILLARD struct e1000_hw *hw = nic->priv; 36672439e4bfSJean-Christophe PLAGNIOL-VILLARD uint32_t rxcw; 36682439e4bfSJean-Christophe PLAGNIOL-VILLARD uint32_t ctrl; 36692439e4bfSJean-Christophe PLAGNIOL-VILLARD uint32_t status; 36702439e4bfSJean-Christophe PLAGNIOL-VILLARD uint32_t rctl; 36712439e4bfSJean-Christophe PLAGNIOL-VILLARD uint32_t signal; 36722439e4bfSJean-Christophe PLAGNIOL-VILLARD int32_t ret_val; 36732439e4bfSJean-Christophe PLAGNIOL-VILLARD uint16_t phy_data; 36742439e4bfSJean-Christophe PLAGNIOL-VILLARD uint16_t lp_capability; 36752439e4bfSJean-Christophe PLAGNIOL-VILLARD 36762439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGFUNC(); 36772439e4bfSJean-Christophe PLAGNIOL-VILLARD 36782439e4bfSJean-Christophe PLAGNIOL-VILLARD /* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be 36792439e4bfSJean-Christophe PLAGNIOL-VILLARD * set when the optics detect a signal. On older adapters, it will be 36802439e4bfSJean-Christophe PLAGNIOL-VILLARD * cleared when there is a signal 36812439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 36822439e4bfSJean-Christophe PLAGNIOL-VILLARD ctrl = E1000_READ_REG(hw, CTRL); 36832439e4bfSJean-Christophe PLAGNIOL-VILLARD if ((hw->mac_type > e1000_82544) && !(ctrl & E1000_CTRL_ILOS)) 36842439e4bfSJean-Christophe PLAGNIOL-VILLARD signal = E1000_CTRL_SWDPIN1; 36852439e4bfSJean-Christophe PLAGNIOL-VILLARD else 36862439e4bfSJean-Christophe PLAGNIOL-VILLARD signal = 0; 36872439e4bfSJean-Christophe PLAGNIOL-VILLARD 36882439e4bfSJean-Christophe PLAGNIOL-VILLARD status = E1000_READ_REG(hw, STATUS); 36892439e4bfSJean-Christophe PLAGNIOL-VILLARD rxcw = E1000_READ_REG(hw, RXCW); 36902439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("ctrl: %#08x status %#08x rxcw %#08x\n", ctrl, status, rxcw); 36912439e4bfSJean-Christophe PLAGNIOL-VILLARD 36922439e4bfSJean-Christophe PLAGNIOL-VILLARD /* If we have a copper PHY then we only want to go out to the PHY 36932439e4bfSJean-Christophe PLAGNIOL-VILLARD * registers to see if Auto-Neg has completed and/or if our link 36942439e4bfSJean-Christophe PLAGNIOL-VILLARD * status has changed. The get_link_status flag will be set if we 36952439e4bfSJean-Christophe PLAGNIOL-VILLARD * receive a Link Status Change interrupt or we have Rx Sequence 36962439e4bfSJean-Christophe PLAGNIOL-VILLARD * Errors. 36972439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 36982439e4bfSJean-Christophe PLAGNIOL-VILLARD if ((hw->media_type == e1000_media_type_copper) && hw->get_link_status) { 36992439e4bfSJean-Christophe PLAGNIOL-VILLARD /* First we want to see if the MII Status Register reports 37002439e4bfSJean-Christophe PLAGNIOL-VILLARD * link. If so, then we want to get the current speed/duplex 37012439e4bfSJean-Christophe PLAGNIOL-VILLARD * of the PHY. 37022439e4bfSJean-Christophe PLAGNIOL-VILLARD * Read the register twice since the link bit is sticky. 37032439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 37042439e4bfSJean-Christophe PLAGNIOL-VILLARD if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) { 37052439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("PHY Read Error\n"); 37062439e4bfSJean-Christophe PLAGNIOL-VILLARD return -E1000_ERR_PHY; 37072439e4bfSJean-Christophe PLAGNIOL-VILLARD } 37082439e4bfSJean-Christophe PLAGNIOL-VILLARD if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) { 37092439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("PHY Read Error\n"); 37102439e4bfSJean-Christophe PLAGNIOL-VILLARD return -E1000_ERR_PHY; 37112439e4bfSJean-Christophe PLAGNIOL-VILLARD } 37122439e4bfSJean-Christophe PLAGNIOL-VILLARD 37132439e4bfSJean-Christophe PLAGNIOL-VILLARD if (phy_data & MII_SR_LINK_STATUS) { 3714472d5460SYork Sun hw->get_link_status = false; 37152439e4bfSJean-Christophe PLAGNIOL-VILLARD } else { 37162439e4bfSJean-Christophe PLAGNIOL-VILLARD /* No link detected */ 37172439e4bfSJean-Christophe PLAGNIOL-VILLARD return -E1000_ERR_NOLINK; 37182439e4bfSJean-Christophe PLAGNIOL-VILLARD } 37192439e4bfSJean-Christophe PLAGNIOL-VILLARD 37202439e4bfSJean-Christophe PLAGNIOL-VILLARD /* We have a M88E1000 PHY and Auto-Neg is enabled. If we 37212439e4bfSJean-Christophe PLAGNIOL-VILLARD * have Si on board that is 82544 or newer, Auto 37222439e4bfSJean-Christophe PLAGNIOL-VILLARD * Speed Detection takes care of MAC speed/duplex 37232439e4bfSJean-Christophe PLAGNIOL-VILLARD * configuration. So we only need to configure Collision 37242439e4bfSJean-Christophe PLAGNIOL-VILLARD * Distance in the MAC. Otherwise, we need to force 37252439e4bfSJean-Christophe PLAGNIOL-VILLARD * speed/duplex on the MAC to the current PHY speed/duplex 37262439e4bfSJean-Christophe PLAGNIOL-VILLARD * settings. 37272439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 37282439e4bfSJean-Christophe PLAGNIOL-VILLARD if (hw->mac_type >= e1000_82544) 37292439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_config_collision_dist(hw); 37302439e4bfSJean-Christophe PLAGNIOL-VILLARD else { 37312439e4bfSJean-Christophe PLAGNIOL-VILLARD ret_val = e1000_config_mac_to_phy(hw); 37322439e4bfSJean-Christophe PLAGNIOL-VILLARD if (ret_val < 0) { 37332439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT 37342439e4bfSJean-Christophe PLAGNIOL-VILLARD ("Error configuring MAC to PHY settings\n"); 37352439e4bfSJean-Christophe PLAGNIOL-VILLARD return ret_val; 37362439e4bfSJean-Christophe PLAGNIOL-VILLARD } 37372439e4bfSJean-Christophe PLAGNIOL-VILLARD } 37382439e4bfSJean-Christophe PLAGNIOL-VILLARD 37392439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Configure Flow Control now that Auto-Neg has completed. First, we 37402439e4bfSJean-Christophe PLAGNIOL-VILLARD * need to restore the desired flow control settings because we may 37412439e4bfSJean-Christophe PLAGNIOL-VILLARD * have had to re-autoneg with a different link partner. 37422439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 37432439e4bfSJean-Christophe PLAGNIOL-VILLARD ret_val = e1000_config_fc_after_link_up(hw); 37442439e4bfSJean-Christophe PLAGNIOL-VILLARD if (ret_val < 0) { 37452439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("Error configuring flow control\n"); 37462439e4bfSJean-Christophe PLAGNIOL-VILLARD return ret_val; 37472439e4bfSJean-Christophe PLAGNIOL-VILLARD } 37482439e4bfSJean-Christophe PLAGNIOL-VILLARD 37492439e4bfSJean-Christophe PLAGNIOL-VILLARD /* At this point we know that we are on copper and we have 37502439e4bfSJean-Christophe PLAGNIOL-VILLARD * auto-negotiated link. These are conditions for checking the link 37512439e4bfSJean-Christophe PLAGNIOL-VILLARD * parter capability register. We use the link partner capability to 37522439e4bfSJean-Christophe PLAGNIOL-VILLARD * determine if TBI Compatibility needs to be turned on or off. If 37532439e4bfSJean-Christophe PLAGNIOL-VILLARD * the link partner advertises any speed in addition to Gigabit, then 37542439e4bfSJean-Christophe PLAGNIOL-VILLARD * we assume that they are GMII-based, and TBI compatibility is not 37552439e4bfSJean-Christophe PLAGNIOL-VILLARD * needed. If no other speeds are advertised, we assume the link 37562439e4bfSJean-Christophe PLAGNIOL-VILLARD * partner is TBI-based, and we turn on TBI Compatibility. 37572439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 37582439e4bfSJean-Christophe PLAGNIOL-VILLARD if (hw->tbi_compatibility_en) { 37592439e4bfSJean-Christophe PLAGNIOL-VILLARD if (e1000_read_phy_reg 37602439e4bfSJean-Christophe PLAGNIOL-VILLARD (hw, PHY_LP_ABILITY, &lp_capability) < 0) { 37612439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("PHY Read Error\n"); 37622439e4bfSJean-Christophe PLAGNIOL-VILLARD return -E1000_ERR_PHY; 37632439e4bfSJean-Christophe PLAGNIOL-VILLARD } 37642439e4bfSJean-Christophe PLAGNIOL-VILLARD if (lp_capability & (NWAY_LPAR_10T_HD_CAPS | 37652439e4bfSJean-Christophe PLAGNIOL-VILLARD NWAY_LPAR_10T_FD_CAPS | 37662439e4bfSJean-Christophe PLAGNIOL-VILLARD NWAY_LPAR_100TX_HD_CAPS | 37672439e4bfSJean-Christophe PLAGNIOL-VILLARD NWAY_LPAR_100TX_FD_CAPS | 37682439e4bfSJean-Christophe PLAGNIOL-VILLARD NWAY_LPAR_100T4_CAPS)) { 37692439e4bfSJean-Christophe PLAGNIOL-VILLARD /* If our link partner advertises anything in addition to 37702439e4bfSJean-Christophe PLAGNIOL-VILLARD * gigabit, we do not need to enable TBI compatibility. 37712439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 37722439e4bfSJean-Christophe PLAGNIOL-VILLARD if (hw->tbi_compatibility_on) { 37732439e4bfSJean-Christophe PLAGNIOL-VILLARD /* If we previously were in the mode, turn it off. */ 37742439e4bfSJean-Christophe PLAGNIOL-VILLARD rctl = E1000_READ_REG(hw, RCTL); 37752439e4bfSJean-Christophe PLAGNIOL-VILLARD rctl &= ~E1000_RCTL_SBP; 37762439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, RCTL, rctl); 3777472d5460SYork Sun hw->tbi_compatibility_on = false; 37782439e4bfSJean-Christophe PLAGNIOL-VILLARD } 37792439e4bfSJean-Christophe PLAGNIOL-VILLARD } else { 37802439e4bfSJean-Christophe PLAGNIOL-VILLARD /* If TBI compatibility is was previously off, turn it on. For 37812439e4bfSJean-Christophe PLAGNIOL-VILLARD * compatibility with a TBI link partner, we will store bad 37822439e4bfSJean-Christophe PLAGNIOL-VILLARD * packets. Some frames have an additional byte on the end and 37832439e4bfSJean-Christophe PLAGNIOL-VILLARD * will look like CRC errors to to the hardware. 37842439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 37852439e4bfSJean-Christophe PLAGNIOL-VILLARD if (!hw->tbi_compatibility_on) { 3786472d5460SYork Sun hw->tbi_compatibility_on = true; 37872439e4bfSJean-Christophe PLAGNIOL-VILLARD rctl = E1000_READ_REG(hw, RCTL); 37882439e4bfSJean-Christophe PLAGNIOL-VILLARD rctl |= E1000_RCTL_SBP; 37892439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, RCTL, rctl); 37902439e4bfSJean-Christophe PLAGNIOL-VILLARD } 37912439e4bfSJean-Christophe PLAGNIOL-VILLARD } 37922439e4bfSJean-Christophe PLAGNIOL-VILLARD } 37932439e4bfSJean-Christophe PLAGNIOL-VILLARD } 37942439e4bfSJean-Christophe PLAGNIOL-VILLARD /* If we don't have link (auto-negotiation failed or link partner cannot 37952439e4bfSJean-Christophe PLAGNIOL-VILLARD * auto-negotiate), the cable is plugged in (we have signal), and our 37962439e4bfSJean-Christophe PLAGNIOL-VILLARD * link partner is not trying to auto-negotiate with us (we are receiving 37972439e4bfSJean-Christophe PLAGNIOL-VILLARD * idles or data), we need to force link up. We also need to give 37982439e4bfSJean-Christophe PLAGNIOL-VILLARD * auto-negotiation time to complete, in case the cable was just plugged 37992439e4bfSJean-Christophe PLAGNIOL-VILLARD * in. The autoneg_failed flag does this. 38002439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 38012439e4bfSJean-Christophe PLAGNIOL-VILLARD else if ((hw->media_type == e1000_media_type_fiber) && 38022439e4bfSJean-Christophe PLAGNIOL-VILLARD (!(status & E1000_STATUS_LU)) && 38032439e4bfSJean-Christophe PLAGNIOL-VILLARD ((ctrl & E1000_CTRL_SWDPIN1) == signal) && 38042439e4bfSJean-Christophe PLAGNIOL-VILLARD (!(rxcw & E1000_RXCW_C))) { 38052439e4bfSJean-Christophe PLAGNIOL-VILLARD if (hw->autoneg_failed == 0) { 38062439e4bfSJean-Christophe PLAGNIOL-VILLARD hw->autoneg_failed = 1; 38072439e4bfSJean-Christophe PLAGNIOL-VILLARD return 0; 38082439e4bfSJean-Christophe PLAGNIOL-VILLARD } 38092439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\r\n"); 38102439e4bfSJean-Christophe PLAGNIOL-VILLARD 38112439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Disable auto-negotiation in the TXCW register */ 38122439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE)); 38132439e4bfSJean-Christophe PLAGNIOL-VILLARD 38142439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Force link-up and also force full-duplex. */ 38152439e4bfSJean-Christophe PLAGNIOL-VILLARD ctrl = E1000_READ_REG(hw, CTRL); 38162439e4bfSJean-Christophe PLAGNIOL-VILLARD ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 38172439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, CTRL, ctrl); 38182439e4bfSJean-Christophe PLAGNIOL-VILLARD 38192439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Configure Flow Control after forcing link up. */ 38202439e4bfSJean-Christophe PLAGNIOL-VILLARD ret_val = e1000_config_fc_after_link_up(hw); 38212439e4bfSJean-Christophe PLAGNIOL-VILLARD if (ret_val < 0) { 38222439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("Error configuring flow control\n"); 38232439e4bfSJean-Christophe PLAGNIOL-VILLARD return ret_val; 38242439e4bfSJean-Christophe PLAGNIOL-VILLARD } 38252439e4bfSJean-Christophe PLAGNIOL-VILLARD } 38262439e4bfSJean-Christophe PLAGNIOL-VILLARD /* If we are forcing link and we are receiving /C/ ordered sets, re-enable 38272439e4bfSJean-Christophe PLAGNIOL-VILLARD * auto-negotiation in the TXCW register and disable forced link in the 38282439e4bfSJean-Christophe PLAGNIOL-VILLARD * Device Control register in an attempt to auto-negotiate with our link 38292439e4bfSJean-Christophe PLAGNIOL-VILLARD * partner. 38302439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 38312439e4bfSJean-Christophe PLAGNIOL-VILLARD else if ((hw->media_type == e1000_media_type_fiber) && 38322439e4bfSJean-Christophe PLAGNIOL-VILLARD (ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { 38332439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT 38342439e4bfSJean-Christophe PLAGNIOL-VILLARD ("RXing /C/, enable AutoNeg and stop forcing link.\r\n"); 38352439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, TXCW, hw->txcw); 38362439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU)); 38372439e4bfSJean-Christophe PLAGNIOL-VILLARD } 38382439e4bfSJean-Christophe PLAGNIOL-VILLARD return 0; 38392439e4bfSJean-Christophe PLAGNIOL-VILLARD } 38402439e4bfSJean-Christophe PLAGNIOL-VILLARD 38412439e4bfSJean-Christophe PLAGNIOL-VILLARD /****************************************************************************** 3842aa070789SRoy Zang * Configure the MAC-to-PHY interface for 10/100Mbps 3843aa070789SRoy Zang * 3844aa070789SRoy Zang * hw - Struct containing variables accessed by shared code 3845aa070789SRoy Zang ******************************************************************************/ 3846aa070789SRoy Zang static int32_t 3847aa070789SRoy Zang e1000_configure_kmrn_for_10_100(struct e1000_hw *hw, uint16_t duplex) 3848aa070789SRoy Zang { 3849aa070789SRoy Zang int32_t ret_val = E1000_SUCCESS; 3850aa070789SRoy Zang uint32_t tipg; 3851aa070789SRoy Zang uint16_t reg_data; 3852aa070789SRoy Zang 3853aa070789SRoy Zang DEBUGFUNC(); 3854aa070789SRoy Zang 3855aa070789SRoy Zang reg_data = E1000_KUMCTRLSTA_HD_CTRL_10_100_DEFAULT; 3856aa070789SRoy Zang ret_val = e1000_write_kmrn_reg(hw, 3857aa070789SRoy Zang E1000_KUMCTRLSTA_OFFSET_HD_CTRL, reg_data); 3858aa070789SRoy Zang if (ret_val) 3859aa070789SRoy Zang return ret_val; 3860aa070789SRoy Zang 3861aa070789SRoy Zang /* Configure Transmit Inter-Packet Gap */ 3862aa070789SRoy Zang tipg = E1000_READ_REG(hw, TIPG); 3863aa070789SRoy Zang tipg &= ~E1000_TIPG_IPGT_MASK; 3864aa070789SRoy Zang tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_10_100; 3865aa070789SRoy Zang E1000_WRITE_REG(hw, TIPG, tipg); 3866aa070789SRoy Zang 3867aa070789SRoy Zang ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data); 3868aa070789SRoy Zang 3869aa070789SRoy Zang if (ret_val) 3870aa070789SRoy Zang return ret_val; 3871aa070789SRoy Zang 3872aa070789SRoy Zang if (duplex == HALF_DUPLEX) 3873aa070789SRoy Zang reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER; 3874aa070789SRoy Zang else 3875aa070789SRoy Zang reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; 3876aa070789SRoy Zang 3877aa070789SRoy Zang ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data); 3878aa070789SRoy Zang 3879aa070789SRoy Zang return ret_val; 3880aa070789SRoy Zang } 3881aa070789SRoy Zang 3882aa070789SRoy Zang static int32_t 3883aa070789SRoy Zang e1000_configure_kmrn_for_1000(struct e1000_hw *hw) 3884aa070789SRoy Zang { 3885aa070789SRoy Zang int32_t ret_val = E1000_SUCCESS; 3886aa070789SRoy Zang uint16_t reg_data; 3887aa070789SRoy Zang uint32_t tipg; 3888aa070789SRoy Zang 3889aa070789SRoy Zang DEBUGFUNC(); 3890aa070789SRoy Zang 3891aa070789SRoy Zang reg_data = E1000_KUMCTRLSTA_HD_CTRL_1000_DEFAULT; 3892aa070789SRoy Zang ret_val = e1000_write_kmrn_reg(hw, 3893aa070789SRoy Zang E1000_KUMCTRLSTA_OFFSET_HD_CTRL, reg_data); 3894aa070789SRoy Zang if (ret_val) 3895aa070789SRoy Zang return ret_val; 3896aa070789SRoy Zang 3897aa070789SRoy Zang /* Configure Transmit Inter-Packet Gap */ 3898aa070789SRoy Zang tipg = E1000_READ_REG(hw, TIPG); 3899aa070789SRoy Zang tipg &= ~E1000_TIPG_IPGT_MASK; 3900aa070789SRoy Zang tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000; 3901aa070789SRoy Zang E1000_WRITE_REG(hw, TIPG, tipg); 3902aa070789SRoy Zang 3903aa070789SRoy Zang ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data); 3904aa070789SRoy Zang 3905aa070789SRoy Zang if (ret_val) 3906aa070789SRoy Zang return ret_val; 3907aa070789SRoy Zang 3908aa070789SRoy Zang reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; 3909aa070789SRoy Zang ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data); 3910aa070789SRoy Zang 3911aa070789SRoy Zang return ret_val; 3912aa070789SRoy Zang } 3913aa070789SRoy Zang 3914aa070789SRoy Zang /****************************************************************************** 39152439e4bfSJean-Christophe PLAGNIOL-VILLARD * Detects the current speed and duplex settings of the hardware. 39162439e4bfSJean-Christophe PLAGNIOL-VILLARD * 39172439e4bfSJean-Christophe PLAGNIOL-VILLARD * hw - Struct containing variables accessed by shared code 39182439e4bfSJean-Christophe PLAGNIOL-VILLARD * speed - Speed of the connection 39192439e4bfSJean-Christophe PLAGNIOL-VILLARD * duplex - Duplex setting of the connection 39202439e4bfSJean-Christophe PLAGNIOL-VILLARD *****************************************************************************/ 3921aa070789SRoy Zang static int 3922aa070789SRoy Zang e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t *speed, 3923aa070789SRoy Zang uint16_t *duplex) 39242439e4bfSJean-Christophe PLAGNIOL-VILLARD { 39252439e4bfSJean-Christophe PLAGNIOL-VILLARD uint32_t status; 3926aa070789SRoy Zang int32_t ret_val; 3927aa070789SRoy Zang uint16_t phy_data; 39282439e4bfSJean-Christophe PLAGNIOL-VILLARD 39292439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGFUNC(); 39302439e4bfSJean-Christophe PLAGNIOL-VILLARD 39312439e4bfSJean-Christophe PLAGNIOL-VILLARD if (hw->mac_type >= e1000_82543) { 39322439e4bfSJean-Christophe PLAGNIOL-VILLARD status = E1000_READ_REG(hw, STATUS); 39332439e4bfSJean-Christophe PLAGNIOL-VILLARD if (status & E1000_STATUS_SPEED_1000) { 39342439e4bfSJean-Christophe PLAGNIOL-VILLARD *speed = SPEED_1000; 39352439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("1000 Mbs, "); 39362439e4bfSJean-Christophe PLAGNIOL-VILLARD } else if (status & E1000_STATUS_SPEED_100) { 39372439e4bfSJean-Christophe PLAGNIOL-VILLARD *speed = SPEED_100; 39382439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("100 Mbs, "); 39392439e4bfSJean-Christophe PLAGNIOL-VILLARD } else { 39402439e4bfSJean-Christophe PLAGNIOL-VILLARD *speed = SPEED_10; 39412439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("10 Mbs, "); 39422439e4bfSJean-Christophe PLAGNIOL-VILLARD } 39432439e4bfSJean-Christophe PLAGNIOL-VILLARD 39442439e4bfSJean-Christophe PLAGNIOL-VILLARD if (status & E1000_STATUS_FD) { 39452439e4bfSJean-Christophe PLAGNIOL-VILLARD *duplex = FULL_DUPLEX; 39462439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("Full Duplex\r\n"); 39472439e4bfSJean-Christophe PLAGNIOL-VILLARD } else { 39482439e4bfSJean-Christophe PLAGNIOL-VILLARD *duplex = HALF_DUPLEX; 39492439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT(" Half Duplex\r\n"); 39502439e4bfSJean-Christophe PLAGNIOL-VILLARD } 39512439e4bfSJean-Christophe PLAGNIOL-VILLARD } else { 39522439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("1000 Mbs, Full Duplex\r\n"); 39532439e4bfSJean-Christophe PLAGNIOL-VILLARD *speed = SPEED_1000; 39542439e4bfSJean-Christophe PLAGNIOL-VILLARD *duplex = FULL_DUPLEX; 39552439e4bfSJean-Christophe PLAGNIOL-VILLARD } 3956aa070789SRoy Zang 3957aa070789SRoy Zang /* IGP01 PHY may advertise full duplex operation after speed downgrade 3958aa070789SRoy Zang * even if it is operating at half duplex. Here we set the duplex 3959aa070789SRoy Zang * settings to match the duplex in the link partner's capabilities. 3960aa070789SRoy Zang */ 3961aa070789SRoy Zang if (hw->phy_type == e1000_phy_igp && hw->speed_downgraded) { 3962aa070789SRoy Zang ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data); 3963aa070789SRoy Zang if (ret_val) 3964aa070789SRoy Zang return ret_val; 3965aa070789SRoy Zang 3966aa070789SRoy Zang if (!(phy_data & NWAY_ER_LP_NWAY_CAPS)) 3967aa070789SRoy Zang *duplex = HALF_DUPLEX; 3968aa070789SRoy Zang else { 3969aa070789SRoy Zang ret_val = e1000_read_phy_reg(hw, 3970aa070789SRoy Zang PHY_LP_ABILITY, &phy_data); 3971aa070789SRoy Zang if (ret_val) 3972aa070789SRoy Zang return ret_val; 3973aa070789SRoy Zang if ((*speed == SPEED_100 && 3974aa070789SRoy Zang !(phy_data & NWAY_LPAR_100TX_FD_CAPS)) 3975aa070789SRoy Zang || (*speed == SPEED_10 3976aa070789SRoy Zang && !(phy_data & NWAY_LPAR_10T_FD_CAPS))) 3977aa070789SRoy Zang *duplex = HALF_DUPLEX; 3978aa070789SRoy Zang } 3979aa070789SRoy Zang } 3980aa070789SRoy Zang 3981aa070789SRoy Zang if ((hw->mac_type == e1000_80003es2lan) && 3982aa070789SRoy Zang (hw->media_type == e1000_media_type_copper)) { 3983aa070789SRoy Zang if (*speed == SPEED_1000) 3984aa070789SRoy Zang ret_val = e1000_configure_kmrn_for_1000(hw); 3985aa070789SRoy Zang else 3986aa070789SRoy Zang ret_val = e1000_configure_kmrn_for_10_100(hw, *duplex); 3987aa070789SRoy Zang if (ret_val) 3988aa070789SRoy Zang return ret_val; 3989aa070789SRoy Zang } 3990aa070789SRoy Zang return E1000_SUCCESS; 39912439e4bfSJean-Christophe PLAGNIOL-VILLARD } 39922439e4bfSJean-Christophe PLAGNIOL-VILLARD 39932439e4bfSJean-Christophe PLAGNIOL-VILLARD /****************************************************************************** 39942439e4bfSJean-Christophe PLAGNIOL-VILLARD * Blocks until autoneg completes or times out (~4.5 seconds) 39952439e4bfSJean-Christophe PLAGNIOL-VILLARD * 39962439e4bfSJean-Christophe PLAGNIOL-VILLARD * hw - Struct containing variables accessed by shared code 39972439e4bfSJean-Christophe PLAGNIOL-VILLARD ******************************************************************************/ 39982439e4bfSJean-Christophe PLAGNIOL-VILLARD static int 39992439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_wait_autoneg(struct e1000_hw *hw) 40002439e4bfSJean-Christophe PLAGNIOL-VILLARD { 40012439e4bfSJean-Christophe PLAGNIOL-VILLARD uint16_t i; 40022439e4bfSJean-Christophe PLAGNIOL-VILLARD uint16_t phy_data; 40032439e4bfSJean-Christophe PLAGNIOL-VILLARD 40042439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGFUNC(); 40052439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("Waiting for Auto-Neg to complete.\n"); 40062439e4bfSJean-Christophe PLAGNIOL-VILLARD 40072439e4bfSJean-Christophe PLAGNIOL-VILLARD /* We will wait for autoneg to complete or 4.5 seconds to expire. */ 40082439e4bfSJean-Christophe PLAGNIOL-VILLARD for (i = PHY_AUTO_NEG_TIME; i > 0; i--) { 40092439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Read the MII Status Register and wait for Auto-Neg 40102439e4bfSJean-Christophe PLAGNIOL-VILLARD * Complete bit to be set. 40112439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 40122439e4bfSJean-Christophe PLAGNIOL-VILLARD if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) { 40132439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("PHY Read Error\n"); 40142439e4bfSJean-Christophe PLAGNIOL-VILLARD return -E1000_ERR_PHY; 40152439e4bfSJean-Christophe PLAGNIOL-VILLARD } 40162439e4bfSJean-Christophe PLAGNIOL-VILLARD if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) { 40172439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("PHY Read Error\n"); 40182439e4bfSJean-Christophe PLAGNIOL-VILLARD return -E1000_ERR_PHY; 40192439e4bfSJean-Christophe PLAGNIOL-VILLARD } 40202439e4bfSJean-Christophe PLAGNIOL-VILLARD if (phy_data & MII_SR_AUTONEG_COMPLETE) { 40212439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("Auto-Neg complete.\n"); 40222439e4bfSJean-Christophe PLAGNIOL-VILLARD return 0; 40232439e4bfSJean-Christophe PLAGNIOL-VILLARD } 40242439e4bfSJean-Christophe PLAGNIOL-VILLARD mdelay(100); 40252439e4bfSJean-Christophe PLAGNIOL-VILLARD } 40262439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("Auto-Neg timedout.\n"); 40272439e4bfSJean-Christophe PLAGNIOL-VILLARD return -E1000_ERR_TIMEOUT; 40282439e4bfSJean-Christophe PLAGNIOL-VILLARD } 40292439e4bfSJean-Christophe PLAGNIOL-VILLARD 40302439e4bfSJean-Christophe PLAGNIOL-VILLARD /****************************************************************************** 40312439e4bfSJean-Christophe PLAGNIOL-VILLARD * Raises the Management Data Clock 40322439e4bfSJean-Christophe PLAGNIOL-VILLARD * 40332439e4bfSJean-Christophe PLAGNIOL-VILLARD * hw - Struct containing variables accessed by shared code 40342439e4bfSJean-Christophe PLAGNIOL-VILLARD * ctrl - Device control register's current value 40352439e4bfSJean-Christophe PLAGNIOL-VILLARD ******************************************************************************/ 40362439e4bfSJean-Christophe PLAGNIOL-VILLARD static void 40372439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_raise_mdi_clk(struct e1000_hw *hw, uint32_t * ctrl) 40382439e4bfSJean-Christophe PLAGNIOL-VILLARD { 40392439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Raise the clock input to the Management Data Clock (by setting the MDC 40402439e4bfSJean-Christophe PLAGNIOL-VILLARD * bit), and then delay 2 microseconds. 40412439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 40422439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC)); 40432439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_FLUSH(hw); 40442439e4bfSJean-Christophe PLAGNIOL-VILLARD udelay(2); 40452439e4bfSJean-Christophe PLAGNIOL-VILLARD } 40462439e4bfSJean-Christophe PLAGNIOL-VILLARD 40472439e4bfSJean-Christophe PLAGNIOL-VILLARD /****************************************************************************** 40482439e4bfSJean-Christophe PLAGNIOL-VILLARD * Lowers the Management Data Clock 40492439e4bfSJean-Christophe PLAGNIOL-VILLARD * 40502439e4bfSJean-Christophe PLAGNIOL-VILLARD * hw - Struct containing variables accessed by shared code 40512439e4bfSJean-Christophe PLAGNIOL-VILLARD * ctrl - Device control register's current value 40522439e4bfSJean-Christophe PLAGNIOL-VILLARD ******************************************************************************/ 40532439e4bfSJean-Christophe PLAGNIOL-VILLARD static void 40542439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_lower_mdi_clk(struct e1000_hw *hw, uint32_t * ctrl) 40552439e4bfSJean-Christophe PLAGNIOL-VILLARD { 40562439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Lower the clock input to the Management Data Clock (by clearing the MDC 40572439e4bfSJean-Christophe PLAGNIOL-VILLARD * bit), and then delay 2 microseconds. 40582439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 40592439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC)); 40602439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_FLUSH(hw); 40612439e4bfSJean-Christophe PLAGNIOL-VILLARD udelay(2); 40622439e4bfSJean-Christophe PLAGNIOL-VILLARD } 40632439e4bfSJean-Christophe PLAGNIOL-VILLARD 40642439e4bfSJean-Christophe PLAGNIOL-VILLARD /****************************************************************************** 40652439e4bfSJean-Christophe PLAGNIOL-VILLARD * Shifts data bits out to the PHY 40662439e4bfSJean-Christophe PLAGNIOL-VILLARD * 40672439e4bfSJean-Christophe PLAGNIOL-VILLARD * hw - Struct containing variables accessed by shared code 40682439e4bfSJean-Christophe PLAGNIOL-VILLARD * data - Data to send out to the PHY 40692439e4bfSJean-Christophe PLAGNIOL-VILLARD * count - Number of bits to shift out 40702439e4bfSJean-Christophe PLAGNIOL-VILLARD * 40712439e4bfSJean-Christophe PLAGNIOL-VILLARD * Bits are shifted out in MSB to LSB order. 40722439e4bfSJean-Christophe PLAGNIOL-VILLARD ******************************************************************************/ 40732439e4bfSJean-Christophe PLAGNIOL-VILLARD static void 40742439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_shift_out_mdi_bits(struct e1000_hw *hw, uint32_t data, uint16_t count) 40752439e4bfSJean-Christophe PLAGNIOL-VILLARD { 40762439e4bfSJean-Christophe PLAGNIOL-VILLARD uint32_t ctrl; 40772439e4bfSJean-Christophe PLAGNIOL-VILLARD uint32_t mask; 40782439e4bfSJean-Christophe PLAGNIOL-VILLARD 40792439e4bfSJean-Christophe PLAGNIOL-VILLARD /* We need to shift "count" number of bits out to the PHY. So, the value 40802439e4bfSJean-Christophe PLAGNIOL-VILLARD * in the "data" parameter will be shifted out to the PHY one bit at a 40812439e4bfSJean-Christophe PLAGNIOL-VILLARD * time. In order to do this, "data" must be broken down into bits. 40822439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 40832439e4bfSJean-Christophe PLAGNIOL-VILLARD mask = 0x01; 40842439e4bfSJean-Christophe PLAGNIOL-VILLARD mask <<= (count - 1); 40852439e4bfSJean-Christophe PLAGNIOL-VILLARD 40862439e4bfSJean-Christophe PLAGNIOL-VILLARD ctrl = E1000_READ_REG(hw, CTRL); 40872439e4bfSJean-Christophe PLAGNIOL-VILLARD 40882439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */ 40892439e4bfSJean-Christophe PLAGNIOL-VILLARD ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR); 40902439e4bfSJean-Christophe PLAGNIOL-VILLARD 40912439e4bfSJean-Christophe PLAGNIOL-VILLARD while (mask) { 40922439e4bfSJean-Christophe PLAGNIOL-VILLARD /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and 40932439e4bfSJean-Christophe PLAGNIOL-VILLARD * then raising and lowering the Management Data Clock. A "0" is 40942439e4bfSJean-Christophe PLAGNIOL-VILLARD * shifted out to the PHY by setting the MDIO bit to "0" and then 40952439e4bfSJean-Christophe PLAGNIOL-VILLARD * raising and lowering the clock. 40962439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 40972439e4bfSJean-Christophe PLAGNIOL-VILLARD if (data & mask) 40982439e4bfSJean-Christophe PLAGNIOL-VILLARD ctrl |= E1000_CTRL_MDIO; 40992439e4bfSJean-Christophe PLAGNIOL-VILLARD else 41002439e4bfSJean-Christophe PLAGNIOL-VILLARD ctrl &= ~E1000_CTRL_MDIO; 41012439e4bfSJean-Christophe PLAGNIOL-VILLARD 41022439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, CTRL, ctrl); 41032439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_FLUSH(hw); 41042439e4bfSJean-Christophe PLAGNIOL-VILLARD 41052439e4bfSJean-Christophe PLAGNIOL-VILLARD udelay(2); 41062439e4bfSJean-Christophe PLAGNIOL-VILLARD 41072439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_raise_mdi_clk(hw, &ctrl); 41082439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_lower_mdi_clk(hw, &ctrl); 41092439e4bfSJean-Christophe PLAGNIOL-VILLARD 41102439e4bfSJean-Christophe PLAGNIOL-VILLARD mask = mask >> 1; 41112439e4bfSJean-Christophe PLAGNIOL-VILLARD } 41122439e4bfSJean-Christophe PLAGNIOL-VILLARD } 41132439e4bfSJean-Christophe PLAGNIOL-VILLARD 41142439e4bfSJean-Christophe PLAGNIOL-VILLARD /****************************************************************************** 41152439e4bfSJean-Christophe PLAGNIOL-VILLARD * Shifts data bits in from the PHY 41162439e4bfSJean-Christophe PLAGNIOL-VILLARD * 41172439e4bfSJean-Christophe PLAGNIOL-VILLARD * hw - Struct containing variables accessed by shared code 41182439e4bfSJean-Christophe PLAGNIOL-VILLARD * 41192439e4bfSJean-Christophe PLAGNIOL-VILLARD * Bits are shifted in in MSB to LSB order. 41202439e4bfSJean-Christophe PLAGNIOL-VILLARD ******************************************************************************/ 41212439e4bfSJean-Christophe PLAGNIOL-VILLARD static uint16_t 41222439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_shift_in_mdi_bits(struct e1000_hw *hw) 41232439e4bfSJean-Christophe PLAGNIOL-VILLARD { 41242439e4bfSJean-Christophe PLAGNIOL-VILLARD uint32_t ctrl; 41252439e4bfSJean-Christophe PLAGNIOL-VILLARD uint16_t data = 0; 41262439e4bfSJean-Christophe PLAGNIOL-VILLARD uint8_t i; 41272439e4bfSJean-Christophe PLAGNIOL-VILLARD 41282439e4bfSJean-Christophe PLAGNIOL-VILLARD /* In order to read a register from the PHY, we need to shift in a total 41292439e4bfSJean-Christophe PLAGNIOL-VILLARD * of 18 bits from the PHY. The first two bit (turnaround) times are used 41302439e4bfSJean-Christophe PLAGNIOL-VILLARD * to avoid contention on the MDIO pin when a read operation is performed. 41312439e4bfSJean-Christophe PLAGNIOL-VILLARD * These two bits are ignored by us and thrown away. Bits are "shifted in" 41322439e4bfSJean-Christophe PLAGNIOL-VILLARD * by raising the input to the Management Data Clock (setting the MDC bit), 41332439e4bfSJean-Christophe PLAGNIOL-VILLARD * and then reading the value of the MDIO bit. 41342439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 41352439e4bfSJean-Christophe PLAGNIOL-VILLARD ctrl = E1000_READ_REG(hw, CTRL); 41362439e4bfSJean-Christophe PLAGNIOL-VILLARD 41372439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */ 41382439e4bfSJean-Christophe PLAGNIOL-VILLARD ctrl &= ~E1000_CTRL_MDIO_DIR; 41392439e4bfSJean-Christophe PLAGNIOL-VILLARD ctrl &= ~E1000_CTRL_MDIO; 41402439e4bfSJean-Christophe PLAGNIOL-VILLARD 41412439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, CTRL, ctrl); 41422439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_FLUSH(hw); 41432439e4bfSJean-Christophe PLAGNIOL-VILLARD 41442439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Raise and Lower the clock before reading in the data. This accounts for 41452439e4bfSJean-Christophe PLAGNIOL-VILLARD * the turnaround bits. The first clock occurred when we clocked out the 41462439e4bfSJean-Christophe PLAGNIOL-VILLARD * last bit of the Register Address. 41472439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 41482439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_raise_mdi_clk(hw, &ctrl); 41492439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_lower_mdi_clk(hw, &ctrl); 41502439e4bfSJean-Christophe PLAGNIOL-VILLARD 41512439e4bfSJean-Christophe PLAGNIOL-VILLARD for (data = 0, i = 0; i < 16; i++) { 41522439e4bfSJean-Christophe PLAGNIOL-VILLARD data = data << 1; 41532439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_raise_mdi_clk(hw, &ctrl); 41542439e4bfSJean-Christophe PLAGNIOL-VILLARD ctrl = E1000_READ_REG(hw, CTRL); 41552439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Check to see if we shifted in a "1". */ 41562439e4bfSJean-Christophe PLAGNIOL-VILLARD if (ctrl & E1000_CTRL_MDIO) 41572439e4bfSJean-Christophe PLAGNIOL-VILLARD data |= 1; 41582439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_lower_mdi_clk(hw, &ctrl); 41592439e4bfSJean-Christophe PLAGNIOL-VILLARD } 41602439e4bfSJean-Christophe PLAGNIOL-VILLARD 41612439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_raise_mdi_clk(hw, &ctrl); 41622439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_lower_mdi_clk(hw, &ctrl); 41632439e4bfSJean-Christophe PLAGNIOL-VILLARD 41642439e4bfSJean-Christophe PLAGNIOL-VILLARD return data; 41652439e4bfSJean-Christophe PLAGNIOL-VILLARD } 41662439e4bfSJean-Christophe PLAGNIOL-VILLARD 41672439e4bfSJean-Christophe PLAGNIOL-VILLARD /***************************************************************************** 41682439e4bfSJean-Christophe PLAGNIOL-VILLARD * Reads the value from a PHY register 41692439e4bfSJean-Christophe PLAGNIOL-VILLARD * 41702439e4bfSJean-Christophe PLAGNIOL-VILLARD * hw - Struct containing variables accessed by shared code 41712439e4bfSJean-Christophe PLAGNIOL-VILLARD * reg_addr - address of the PHY register to read 41722439e4bfSJean-Christophe PLAGNIOL-VILLARD ******************************************************************************/ 41732439e4bfSJean-Christophe PLAGNIOL-VILLARD static int 41742439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t * phy_data) 41752439e4bfSJean-Christophe PLAGNIOL-VILLARD { 41762439e4bfSJean-Christophe PLAGNIOL-VILLARD uint32_t i; 41772439e4bfSJean-Christophe PLAGNIOL-VILLARD uint32_t mdic = 0; 41782439e4bfSJean-Christophe PLAGNIOL-VILLARD const uint32_t phy_addr = 1; 41792439e4bfSJean-Christophe PLAGNIOL-VILLARD 41802439e4bfSJean-Christophe PLAGNIOL-VILLARD if (reg_addr > MAX_PHY_REG_ADDRESS) { 41812439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("PHY Address %d is out of range\n", reg_addr); 41822439e4bfSJean-Christophe PLAGNIOL-VILLARD return -E1000_ERR_PARAM; 41832439e4bfSJean-Christophe PLAGNIOL-VILLARD } 41842439e4bfSJean-Christophe PLAGNIOL-VILLARD 41852439e4bfSJean-Christophe PLAGNIOL-VILLARD if (hw->mac_type > e1000_82543) { 41862439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Set up Op-code, Phy Address, and register address in the MDI 41872439e4bfSJean-Christophe PLAGNIOL-VILLARD * Control register. The MAC will take care of interfacing with the 41882439e4bfSJean-Christophe PLAGNIOL-VILLARD * PHY to retrieve the desired data. 41892439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 41902439e4bfSJean-Christophe PLAGNIOL-VILLARD mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) | 41912439e4bfSJean-Christophe PLAGNIOL-VILLARD (phy_addr << E1000_MDIC_PHY_SHIFT) | 41922439e4bfSJean-Christophe PLAGNIOL-VILLARD (E1000_MDIC_OP_READ)); 41932439e4bfSJean-Christophe PLAGNIOL-VILLARD 41942439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, MDIC, mdic); 41952439e4bfSJean-Christophe PLAGNIOL-VILLARD 41962439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Poll the ready bit to see if the MDI read completed */ 41972439e4bfSJean-Christophe PLAGNIOL-VILLARD for (i = 0; i < 64; i++) { 41982439e4bfSJean-Christophe PLAGNIOL-VILLARD udelay(10); 41992439e4bfSJean-Christophe PLAGNIOL-VILLARD mdic = E1000_READ_REG(hw, MDIC); 42002439e4bfSJean-Christophe PLAGNIOL-VILLARD if (mdic & E1000_MDIC_READY) 42012439e4bfSJean-Christophe PLAGNIOL-VILLARD break; 42022439e4bfSJean-Christophe PLAGNIOL-VILLARD } 42032439e4bfSJean-Christophe PLAGNIOL-VILLARD if (!(mdic & E1000_MDIC_READY)) { 42042439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("MDI Read did not complete\n"); 42052439e4bfSJean-Christophe PLAGNIOL-VILLARD return -E1000_ERR_PHY; 42062439e4bfSJean-Christophe PLAGNIOL-VILLARD } 42072439e4bfSJean-Christophe PLAGNIOL-VILLARD if (mdic & E1000_MDIC_ERROR) { 42082439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("MDI Error\n"); 42092439e4bfSJean-Christophe PLAGNIOL-VILLARD return -E1000_ERR_PHY; 42102439e4bfSJean-Christophe PLAGNIOL-VILLARD } 42112439e4bfSJean-Christophe PLAGNIOL-VILLARD *phy_data = (uint16_t) mdic; 42122439e4bfSJean-Christophe PLAGNIOL-VILLARD } else { 42132439e4bfSJean-Christophe PLAGNIOL-VILLARD /* We must first send a preamble through the MDIO pin to signal the 42142439e4bfSJean-Christophe PLAGNIOL-VILLARD * beginning of an MII instruction. This is done by sending 32 42152439e4bfSJean-Christophe PLAGNIOL-VILLARD * consecutive "1" bits. 42162439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 42172439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); 42182439e4bfSJean-Christophe PLAGNIOL-VILLARD 42192439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Now combine the next few fields that are required for a read 42202439e4bfSJean-Christophe PLAGNIOL-VILLARD * operation. We use this method instead of calling the 42212439e4bfSJean-Christophe PLAGNIOL-VILLARD * e1000_shift_out_mdi_bits routine five different times. The format of 42222439e4bfSJean-Christophe PLAGNIOL-VILLARD * a MII read instruction consists of a shift out of 14 bits and is 42232439e4bfSJean-Christophe PLAGNIOL-VILLARD * defined as follows: 42242439e4bfSJean-Christophe PLAGNIOL-VILLARD * <Preamble><SOF><Op Code><Phy Addr><Reg Addr> 42252439e4bfSJean-Christophe PLAGNIOL-VILLARD * followed by a shift in of 18 bits. This first two bits shifted in 42262439e4bfSJean-Christophe PLAGNIOL-VILLARD * are TurnAround bits used to avoid contention on the MDIO pin when a 42272439e4bfSJean-Christophe PLAGNIOL-VILLARD * READ operation is performed. These two bits are thrown away 42282439e4bfSJean-Christophe PLAGNIOL-VILLARD * followed by a shift in of 16 bits which contains the desired data. 42292439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 42302439e4bfSJean-Christophe PLAGNIOL-VILLARD mdic = ((reg_addr) | (phy_addr << 5) | 42312439e4bfSJean-Christophe PLAGNIOL-VILLARD (PHY_OP_READ << 10) | (PHY_SOF << 12)); 42322439e4bfSJean-Christophe PLAGNIOL-VILLARD 42332439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_shift_out_mdi_bits(hw, mdic, 14); 42342439e4bfSJean-Christophe PLAGNIOL-VILLARD 42352439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Now that we've shifted out the read command to the MII, we need to 42362439e4bfSJean-Christophe PLAGNIOL-VILLARD * "shift in" the 16-bit value (18 total bits) of the requested PHY 42372439e4bfSJean-Christophe PLAGNIOL-VILLARD * register address. 42382439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 42392439e4bfSJean-Christophe PLAGNIOL-VILLARD *phy_data = e1000_shift_in_mdi_bits(hw); 42402439e4bfSJean-Christophe PLAGNIOL-VILLARD } 42412439e4bfSJean-Christophe PLAGNIOL-VILLARD return 0; 42422439e4bfSJean-Christophe PLAGNIOL-VILLARD } 42432439e4bfSJean-Christophe PLAGNIOL-VILLARD 42442439e4bfSJean-Christophe PLAGNIOL-VILLARD /****************************************************************************** 42452439e4bfSJean-Christophe PLAGNIOL-VILLARD * Writes a value to a PHY register 42462439e4bfSJean-Christophe PLAGNIOL-VILLARD * 42472439e4bfSJean-Christophe PLAGNIOL-VILLARD * hw - Struct containing variables accessed by shared code 42482439e4bfSJean-Christophe PLAGNIOL-VILLARD * reg_addr - address of the PHY register to write 42492439e4bfSJean-Christophe PLAGNIOL-VILLARD * data - data to write to the PHY 42502439e4bfSJean-Christophe PLAGNIOL-VILLARD ******************************************************************************/ 42512439e4bfSJean-Christophe PLAGNIOL-VILLARD static int 42522439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t phy_data) 42532439e4bfSJean-Christophe PLAGNIOL-VILLARD { 42542439e4bfSJean-Christophe PLAGNIOL-VILLARD uint32_t i; 42552439e4bfSJean-Christophe PLAGNIOL-VILLARD uint32_t mdic = 0; 42562439e4bfSJean-Christophe PLAGNIOL-VILLARD const uint32_t phy_addr = 1; 42572439e4bfSJean-Christophe PLAGNIOL-VILLARD 42582439e4bfSJean-Christophe PLAGNIOL-VILLARD if (reg_addr > MAX_PHY_REG_ADDRESS) { 42592439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("PHY Address %d is out of range\n", reg_addr); 42602439e4bfSJean-Christophe PLAGNIOL-VILLARD return -E1000_ERR_PARAM; 42612439e4bfSJean-Christophe PLAGNIOL-VILLARD } 42622439e4bfSJean-Christophe PLAGNIOL-VILLARD 42632439e4bfSJean-Christophe PLAGNIOL-VILLARD if (hw->mac_type > e1000_82543) { 42642439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Set up Op-code, Phy Address, register address, and data intended 42652439e4bfSJean-Christophe PLAGNIOL-VILLARD * for the PHY register in the MDI Control register. The MAC will take 42662439e4bfSJean-Christophe PLAGNIOL-VILLARD * care of interfacing with the PHY to send the desired data. 42672439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 42682439e4bfSJean-Christophe PLAGNIOL-VILLARD mdic = (((uint32_t) phy_data) | 42692439e4bfSJean-Christophe PLAGNIOL-VILLARD (reg_addr << E1000_MDIC_REG_SHIFT) | 42702439e4bfSJean-Christophe PLAGNIOL-VILLARD (phy_addr << E1000_MDIC_PHY_SHIFT) | 42712439e4bfSJean-Christophe PLAGNIOL-VILLARD (E1000_MDIC_OP_WRITE)); 42722439e4bfSJean-Christophe PLAGNIOL-VILLARD 42732439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, MDIC, mdic); 42742439e4bfSJean-Christophe PLAGNIOL-VILLARD 42752439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Poll the ready bit to see if the MDI read completed */ 42762439e4bfSJean-Christophe PLAGNIOL-VILLARD for (i = 0; i < 64; i++) { 42772439e4bfSJean-Christophe PLAGNIOL-VILLARD udelay(10); 42782439e4bfSJean-Christophe PLAGNIOL-VILLARD mdic = E1000_READ_REG(hw, MDIC); 42792439e4bfSJean-Christophe PLAGNIOL-VILLARD if (mdic & E1000_MDIC_READY) 42802439e4bfSJean-Christophe PLAGNIOL-VILLARD break; 42812439e4bfSJean-Christophe PLAGNIOL-VILLARD } 42822439e4bfSJean-Christophe PLAGNIOL-VILLARD if (!(mdic & E1000_MDIC_READY)) { 42832439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("MDI Write did not complete\n"); 42842439e4bfSJean-Christophe PLAGNIOL-VILLARD return -E1000_ERR_PHY; 42852439e4bfSJean-Christophe PLAGNIOL-VILLARD } 42862439e4bfSJean-Christophe PLAGNIOL-VILLARD } else { 42872439e4bfSJean-Christophe PLAGNIOL-VILLARD /* We'll need to use the SW defined pins to shift the write command 42882439e4bfSJean-Christophe PLAGNIOL-VILLARD * out to the PHY. We first send a preamble to the PHY to signal the 42892439e4bfSJean-Christophe PLAGNIOL-VILLARD * beginning of the MII instruction. This is done by sending 32 42902439e4bfSJean-Christophe PLAGNIOL-VILLARD * consecutive "1" bits. 42912439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 42922439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); 42932439e4bfSJean-Christophe PLAGNIOL-VILLARD 42942439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Now combine the remaining required fields that will indicate a 42952439e4bfSJean-Christophe PLAGNIOL-VILLARD * write operation. We use this method instead of calling the 42962439e4bfSJean-Christophe PLAGNIOL-VILLARD * e1000_shift_out_mdi_bits routine for each field in the command. The 42972439e4bfSJean-Christophe PLAGNIOL-VILLARD * format of a MII write instruction is as follows: 42982439e4bfSJean-Christophe PLAGNIOL-VILLARD * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>. 42992439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 43002439e4bfSJean-Christophe PLAGNIOL-VILLARD mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) | 43012439e4bfSJean-Christophe PLAGNIOL-VILLARD (PHY_OP_WRITE << 12) | (PHY_SOF << 14)); 43022439e4bfSJean-Christophe PLAGNIOL-VILLARD mdic <<= 16; 43032439e4bfSJean-Christophe PLAGNIOL-VILLARD mdic |= (uint32_t) phy_data; 43042439e4bfSJean-Christophe PLAGNIOL-VILLARD 43052439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_shift_out_mdi_bits(hw, mdic, 32); 43062439e4bfSJean-Christophe PLAGNIOL-VILLARD } 43072439e4bfSJean-Christophe PLAGNIOL-VILLARD return 0; 43082439e4bfSJean-Christophe PLAGNIOL-VILLARD } 43092439e4bfSJean-Christophe PLAGNIOL-VILLARD 43102439e4bfSJean-Christophe PLAGNIOL-VILLARD /****************************************************************************** 4311aa070789SRoy Zang * Checks if PHY reset is blocked due to SOL/IDER session, for example. 4312aa070789SRoy Zang * Returning E1000_BLK_PHY_RESET isn't necessarily an error. But it's up to 4313aa070789SRoy Zang * the caller to figure out how to deal with it. 4314aa070789SRoy Zang * 4315aa070789SRoy Zang * hw - Struct containing variables accessed by shared code 4316aa070789SRoy Zang * 4317aa070789SRoy Zang * returns: - E1000_BLK_PHY_RESET 4318aa070789SRoy Zang * E1000_SUCCESS 4319aa070789SRoy Zang * 4320aa070789SRoy Zang *****************************************************************************/ 4321aa070789SRoy Zang int32_t 4322aa070789SRoy Zang e1000_check_phy_reset_block(struct e1000_hw *hw) 4323aa070789SRoy Zang { 4324aa070789SRoy Zang uint32_t manc = 0; 4325aa070789SRoy Zang uint32_t fwsm = 0; 4326aa070789SRoy Zang 4327aa070789SRoy Zang if (hw->mac_type == e1000_ich8lan) { 4328aa070789SRoy Zang fwsm = E1000_READ_REG(hw, FWSM); 4329aa070789SRoy Zang return (fwsm & E1000_FWSM_RSPCIPHY) ? E1000_SUCCESS 4330aa070789SRoy Zang : E1000_BLK_PHY_RESET; 4331aa070789SRoy Zang } 4332aa070789SRoy Zang 4333aa070789SRoy Zang if (hw->mac_type > e1000_82547_rev_2) 4334aa070789SRoy Zang manc = E1000_READ_REG(hw, MANC); 4335aa070789SRoy Zang return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ? 4336aa070789SRoy Zang E1000_BLK_PHY_RESET : E1000_SUCCESS; 4337aa070789SRoy Zang } 4338aa070789SRoy Zang 4339aa070789SRoy Zang /*************************************************************************** 4340aa070789SRoy Zang * Checks if the PHY configuration is done 4341aa070789SRoy Zang * 4342aa070789SRoy Zang * hw: Struct containing variables accessed by shared code 4343aa070789SRoy Zang * 4344aa070789SRoy Zang * returns: - E1000_ERR_RESET if fail to reset MAC 4345aa070789SRoy Zang * E1000_SUCCESS at any other case. 4346aa070789SRoy Zang * 4347aa070789SRoy Zang ***************************************************************************/ 4348aa070789SRoy Zang static int32_t 4349aa070789SRoy Zang e1000_get_phy_cfg_done(struct e1000_hw *hw) 4350aa070789SRoy Zang { 4351aa070789SRoy Zang int32_t timeout = PHY_CFG_TIMEOUT; 4352aa070789SRoy Zang uint32_t cfg_mask = E1000_EEPROM_CFG_DONE; 4353aa070789SRoy Zang 4354aa070789SRoy Zang DEBUGFUNC(); 4355aa070789SRoy Zang 4356aa070789SRoy Zang switch (hw->mac_type) { 4357aa070789SRoy Zang default: 4358aa070789SRoy Zang mdelay(10); 4359aa070789SRoy Zang break; 4360987b43a1SKyle Moffett 4361aa070789SRoy Zang case e1000_80003es2lan: 4362aa070789SRoy Zang /* Separate *_CFG_DONE_* bit for each port */ 4363987b43a1SKyle Moffett if (e1000_is_second_port(hw)) 4364aa070789SRoy Zang cfg_mask = E1000_EEPROM_CFG_DONE_PORT_1; 4365aa070789SRoy Zang /* Fall Through */ 4366987b43a1SKyle Moffett 4367aa070789SRoy Zang case e1000_82571: 4368aa070789SRoy Zang case e1000_82572: 436995186063SMarek Vasut case e1000_igb: 4370aa070789SRoy Zang while (timeout) { 437195186063SMarek Vasut if (hw->mac_type == e1000_igb) { 437295186063SMarek Vasut if (E1000_READ_REG(hw, I210_EEMNGCTL) & cfg_mask) 437395186063SMarek Vasut break; 437495186063SMarek Vasut } else { 4375aa070789SRoy Zang if (E1000_READ_REG(hw, EEMNGCTL) & cfg_mask) 4376aa070789SRoy Zang break; 437795186063SMarek Vasut } 4378aa070789SRoy Zang mdelay(1); 4379aa070789SRoy Zang timeout--; 4380aa070789SRoy Zang } 4381aa070789SRoy Zang if (!timeout) { 4382aa070789SRoy Zang DEBUGOUT("MNG configuration cycle has not " 4383aa070789SRoy Zang "completed.\n"); 4384aa070789SRoy Zang return -E1000_ERR_RESET; 4385aa070789SRoy Zang } 4386aa070789SRoy Zang break; 4387aa070789SRoy Zang } 4388aa070789SRoy Zang 4389aa070789SRoy Zang return E1000_SUCCESS; 4390aa070789SRoy Zang } 4391aa070789SRoy Zang 4392aa070789SRoy Zang /****************************************************************************** 43932439e4bfSJean-Christophe PLAGNIOL-VILLARD * Returns the PHY to the power-on reset state 43942439e4bfSJean-Christophe PLAGNIOL-VILLARD * 43952439e4bfSJean-Christophe PLAGNIOL-VILLARD * hw - Struct containing variables accessed by shared code 43962439e4bfSJean-Christophe PLAGNIOL-VILLARD ******************************************************************************/ 4397aa070789SRoy Zang int32_t 43982439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_phy_hw_reset(struct e1000_hw *hw) 43992439e4bfSJean-Christophe PLAGNIOL-VILLARD { 4400987b43a1SKyle Moffett uint16_t swfw = E1000_SWFW_PHY0_SM; 4401aa070789SRoy Zang uint32_t ctrl, ctrl_ext; 4402aa070789SRoy Zang uint32_t led_ctrl; 4403aa070789SRoy Zang int32_t ret_val; 44042439e4bfSJean-Christophe PLAGNIOL-VILLARD 44052439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGFUNC(); 44062439e4bfSJean-Christophe PLAGNIOL-VILLARD 4407aa070789SRoy Zang /* In the case of the phy reset being blocked, it's not an error, we 4408aa070789SRoy Zang * simply return success without performing the reset. */ 4409aa070789SRoy Zang ret_val = e1000_check_phy_reset_block(hw); 4410aa070789SRoy Zang if (ret_val) 4411aa070789SRoy Zang return E1000_SUCCESS; 4412aa070789SRoy Zang 44132439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("Resetting Phy...\n"); 44142439e4bfSJean-Christophe PLAGNIOL-VILLARD 44152439e4bfSJean-Christophe PLAGNIOL-VILLARD if (hw->mac_type > e1000_82543) { 4416987b43a1SKyle Moffett if (e1000_is_second_port(hw)) 4417aa070789SRoy Zang swfw = E1000_SWFW_PHY1_SM; 4418987b43a1SKyle Moffett 4419aa070789SRoy Zang if (e1000_swfw_sync_acquire(hw, swfw)) { 4420aa070789SRoy Zang DEBUGOUT("Unable to acquire swfw sync\n"); 4421aa070789SRoy Zang return -E1000_ERR_SWFW_SYNC; 4422aa070789SRoy Zang } 4423987b43a1SKyle Moffett 44242439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Read the device control register and assert the E1000_CTRL_PHY_RST 44252439e4bfSJean-Christophe PLAGNIOL-VILLARD * bit. Then, take it out of reset. 44262439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 44272439e4bfSJean-Christophe PLAGNIOL-VILLARD ctrl = E1000_READ_REG(hw, CTRL); 44282439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST); 44292439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_FLUSH(hw); 4430aa070789SRoy Zang 4431aa070789SRoy Zang if (hw->mac_type < e1000_82571) 4432aa070789SRoy Zang udelay(10); 4433aa070789SRoy Zang else 4434aa070789SRoy Zang udelay(100); 4435aa070789SRoy Zang 44362439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, CTRL, ctrl); 44372439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_FLUSH(hw); 4438aa070789SRoy Zang 4439aa070789SRoy Zang if (hw->mac_type >= e1000_82571) 4440aa070789SRoy Zang mdelay(10); 44412439e4bfSJean-Christophe PLAGNIOL-VILLARD } else { 44422439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Read the Extended Device Control Register, assert the PHY_RESET_DIR 44432439e4bfSJean-Christophe PLAGNIOL-VILLARD * bit to put the PHY into reset. Then, take it out of reset. 44442439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 44452439e4bfSJean-Christophe PLAGNIOL-VILLARD ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 44462439e4bfSJean-Christophe PLAGNIOL-VILLARD ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR; 44472439e4bfSJean-Christophe PLAGNIOL-VILLARD ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA; 44482439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 44492439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_FLUSH(hw); 44502439e4bfSJean-Christophe PLAGNIOL-VILLARD mdelay(10); 44512439e4bfSJean-Christophe PLAGNIOL-VILLARD ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA; 44522439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 44532439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_FLUSH(hw); 44542439e4bfSJean-Christophe PLAGNIOL-VILLARD } 44552439e4bfSJean-Christophe PLAGNIOL-VILLARD udelay(150); 4456aa070789SRoy Zang 4457aa070789SRoy Zang if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { 4458aa070789SRoy Zang /* Configure activity LED after PHY reset */ 4459aa070789SRoy Zang led_ctrl = E1000_READ_REG(hw, LEDCTL); 4460aa070789SRoy Zang led_ctrl &= IGP_ACTIVITY_LED_MASK; 4461aa070789SRoy Zang led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); 4462aa070789SRoy Zang E1000_WRITE_REG(hw, LEDCTL, led_ctrl); 4463aa070789SRoy Zang } 4464aa070789SRoy Zang 4465aa070789SRoy Zang /* Wait for FW to finish PHY configuration. */ 4466aa070789SRoy Zang ret_val = e1000_get_phy_cfg_done(hw); 4467aa070789SRoy Zang if (ret_val != E1000_SUCCESS) 4468aa070789SRoy Zang return ret_val; 4469aa070789SRoy Zang 4470aa070789SRoy Zang return ret_val; 4471aa070789SRoy Zang } 4472aa070789SRoy Zang 4473aa070789SRoy Zang /****************************************************************************** 4474aa070789SRoy Zang * IGP phy init script - initializes the GbE PHY 4475aa070789SRoy Zang * 4476aa070789SRoy Zang * hw - Struct containing variables accessed by shared code 4477aa070789SRoy Zang *****************************************************************************/ 4478aa070789SRoy Zang static void 4479aa070789SRoy Zang e1000_phy_init_script(struct e1000_hw *hw) 4480aa070789SRoy Zang { 4481aa070789SRoy Zang uint32_t ret_val; 4482aa070789SRoy Zang uint16_t phy_saved_data; 4483aa070789SRoy Zang DEBUGFUNC(); 4484aa070789SRoy Zang 4485aa070789SRoy Zang if (hw->phy_init_script) { 4486aa070789SRoy Zang mdelay(20); 4487aa070789SRoy Zang 4488aa070789SRoy Zang /* Save off the current value of register 0x2F5B to be 4489aa070789SRoy Zang * restored at the end of this routine. */ 4490aa070789SRoy Zang ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data); 4491aa070789SRoy Zang 4492aa070789SRoy Zang /* Disabled the PHY transmitter */ 4493aa070789SRoy Zang e1000_write_phy_reg(hw, 0x2F5B, 0x0003); 4494aa070789SRoy Zang 4495aa070789SRoy Zang mdelay(20); 4496aa070789SRoy Zang 4497aa070789SRoy Zang e1000_write_phy_reg(hw, 0x0000, 0x0140); 4498aa070789SRoy Zang 4499aa070789SRoy Zang mdelay(5); 4500aa070789SRoy Zang 4501aa070789SRoy Zang switch (hw->mac_type) { 4502aa070789SRoy Zang case e1000_82541: 4503aa070789SRoy Zang case e1000_82547: 4504aa070789SRoy Zang e1000_write_phy_reg(hw, 0x1F95, 0x0001); 4505aa070789SRoy Zang 4506aa070789SRoy Zang e1000_write_phy_reg(hw, 0x1F71, 0xBD21); 4507aa070789SRoy Zang 4508aa070789SRoy Zang e1000_write_phy_reg(hw, 0x1F79, 0x0018); 4509aa070789SRoy Zang 4510aa070789SRoy Zang e1000_write_phy_reg(hw, 0x1F30, 0x1600); 4511aa070789SRoy Zang 4512aa070789SRoy Zang e1000_write_phy_reg(hw, 0x1F31, 0x0014); 4513aa070789SRoy Zang 4514aa070789SRoy Zang e1000_write_phy_reg(hw, 0x1F32, 0x161C); 4515aa070789SRoy Zang 4516aa070789SRoy Zang e1000_write_phy_reg(hw, 0x1F94, 0x0003); 4517aa070789SRoy Zang 4518aa070789SRoy Zang e1000_write_phy_reg(hw, 0x1F96, 0x003F); 4519aa070789SRoy Zang 4520aa070789SRoy Zang e1000_write_phy_reg(hw, 0x2010, 0x0008); 4521aa070789SRoy Zang break; 4522aa070789SRoy Zang 4523aa070789SRoy Zang case e1000_82541_rev_2: 4524aa070789SRoy Zang case e1000_82547_rev_2: 4525aa070789SRoy Zang e1000_write_phy_reg(hw, 0x1F73, 0x0099); 4526aa070789SRoy Zang break; 4527aa070789SRoy Zang default: 4528aa070789SRoy Zang break; 4529aa070789SRoy Zang } 4530aa070789SRoy Zang 4531aa070789SRoy Zang e1000_write_phy_reg(hw, 0x0000, 0x3300); 4532aa070789SRoy Zang 4533aa070789SRoy Zang mdelay(20); 4534aa070789SRoy Zang 4535aa070789SRoy Zang /* Now enable the transmitter */ 453656b13b1eSZang Roy-R61911 if (!ret_val) 4537aa070789SRoy Zang e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data); 4538aa070789SRoy Zang 4539aa070789SRoy Zang if (hw->mac_type == e1000_82547) { 4540aa070789SRoy Zang uint16_t fused, fine, coarse; 4541aa070789SRoy Zang 4542aa070789SRoy Zang /* Move to analog registers page */ 4543aa070789SRoy Zang e1000_read_phy_reg(hw, 4544aa070789SRoy Zang IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused); 4545aa070789SRoy Zang 4546aa070789SRoy Zang if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) { 4547aa070789SRoy Zang e1000_read_phy_reg(hw, 4548aa070789SRoy Zang IGP01E1000_ANALOG_FUSE_STATUS, &fused); 4549aa070789SRoy Zang 4550aa070789SRoy Zang fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK; 4551aa070789SRoy Zang coarse = fused 4552aa070789SRoy Zang & IGP01E1000_ANALOG_FUSE_COARSE_MASK; 4553aa070789SRoy Zang 4554aa070789SRoy Zang if (coarse > 4555aa070789SRoy Zang IGP01E1000_ANALOG_FUSE_COARSE_THRESH) { 4556aa070789SRoy Zang coarse -= 4557aa070789SRoy Zang IGP01E1000_ANALOG_FUSE_COARSE_10; 4558aa070789SRoy Zang fine -= IGP01E1000_ANALOG_FUSE_FINE_1; 4559aa070789SRoy Zang } else if (coarse 4560aa070789SRoy Zang == IGP01E1000_ANALOG_FUSE_COARSE_THRESH) 4561aa070789SRoy Zang fine -= IGP01E1000_ANALOG_FUSE_FINE_10; 4562aa070789SRoy Zang 4563aa070789SRoy Zang fused = (fused 4564aa070789SRoy Zang & IGP01E1000_ANALOG_FUSE_POLY_MASK) | 4565aa070789SRoy Zang (fine 4566aa070789SRoy Zang & IGP01E1000_ANALOG_FUSE_FINE_MASK) | 4567aa070789SRoy Zang (coarse 4568aa070789SRoy Zang & IGP01E1000_ANALOG_FUSE_COARSE_MASK); 4569aa070789SRoy Zang 4570aa070789SRoy Zang e1000_write_phy_reg(hw, 4571aa070789SRoy Zang IGP01E1000_ANALOG_FUSE_CONTROL, fused); 4572aa070789SRoy Zang e1000_write_phy_reg(hw, 4573aa070789SRoy Zang IGP01E1000_ANALOG_FUSE_BYPASS, 4574aa070789SRoy Zang IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL); 4575aa070789SRoy Zang } 4576aa070789SRoy Zang } 4577aa070789SRoy Zang } 45782439e4bfSJean-Christophe PLAGNIOL-VILLARD } 45792439e4bfSJean-Christophe PLAGNIOL-VILLARD 45802439e4bfSJean-Christophe PLAGNIOL-VILLARD /****************************************************************************** 45812439e4bfSJean-Christophe PLAGNIOL-VILLARD * Resets the PHY 45822439e4bfSJean-Christophe PLAGNIOL-VILLARD * 45832439e4bfSJean-Christophe PLAGNIOL-VILLARD * hw - Struct containing variables accessed by shared code 45842439e4bfSJean-Christophe PLAGNIOL-VILLARD * 4585aa070789SRoy Zang * Sets bit 15 of the MII Control register 45862439e4bfSJean-Christophe PLAGNIOL-VILLARD ******************************************************************************/ 4587aa070789SRoy Zang int32_t 45882439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_phy_reset(struct e1000_hw *hw) 45892439e4bfSJean-Christophe PLAGNIOL-VILLARD { 4590aa070789SRoy Zang int32_t ret_val; 45912439e4bfSJean-Christophe PLAGNIOL-VILLARD uint16_t phy_data; 45922439e4bfSJean-Christophe PLAGNIOL-VILLARD 45932439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGFUNC(); 45942439e4bfSJean-Christophe PLAGNIOL-VILLARD 4595aa070789SRoy Zang /* In the case of the phy reset being blocked, it's not an error, we 4596aa070789SRoy Zang * simply return success without performing the reset. */ 4597aa070789SRoy Zang ret_val = e1000_check_phy_reset_block(hw); 4598aa070789SRoy Zang if (ret_val) 4599aa070789SRoy Zang return E1000_SUCCESS; 4600aa070789SRoy Zang 4601aa070789SRoy Zang switch (hw->phy_type) { 4602aa070789SRoy Zang case e1000_phy_igp: 4603aa070789SRoy Zang case e1000_phy_igp_2: 4604aa070789SRoy Zang case e1000_phy_igp_3: 4605aa070789SRoy Zang case e1000_phy_ife: 460695186063SMarek Vasut case e1000_phy_igb: 4607aa070789SRoy Zang ret_val = e1000_phy_hw_reset(hw); 4608aa070789SRoy Zang if (ret_val) 4609aa070789SRoy Zang return ret_val; 4610aa070789SRoy Zang break; 4611aa070789SRoy Zang default: 4612aa070789SRoy Zang ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data); 4613aa070789SRoy Zang if (ret_val) 4614aa070789SRoy Zang return ret_val; 4615aa070789SRoy Zang 46162439e4bfSJean-Christophe PLAGNIOL-VILLARD phy_data |= MII_CR_RESET; 4617aa070789SRoy Zang ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data); 4618aa070789SRoy Zang if (ret_val) 4619aa070789SRoy Zang return ret_val; 4620aa070789SRoy Zang 46212439e4bfSJean-Christophe PLAGNIOL-VILLARD udelay(1); 4622aa070789SRoy Zang break; 4623aa070789SRoy Zang } 4624aa070789SRoy Zang 4625aa070789SRoy Zang if (hw->phy_type == e1000_phy_igp || hw->phy_type == e1000_phy_igp_2) 4626aa070789SRoy Zang e1000_phy_init_script(hw); 4627aa070789SRoy Zang 4628aa070789SRoy Zang return E1000_SUCCESS; 46292439e4bfSJean-Christophe PLAGNIOL-VILLARD } 46302439e4bfSJean-Christophe PLAGNIOL-VILLARD 46311aeed8d7SWolfgang Denk static int e1000_set_phy_type (struct e1000_hw *hw) 4632ac3315c2SAndre Schwarz { 4633ac3315c2SAndre Schwarz DEBUGFUNC (); 4634ac3315c2SAndre Schwarz 4635ac3315c2SAndre Schwarz if (hw->mac_type == e1000_undefined) 4636ac3315c2SAndre Schwarz return -E1000_ERR_PHY_TYPE; 4637ac3315c2SAndre Schwarz 4638ac3315c2SAndre Schwarz switch (hw->phy_id) { 4639ac3315c2SAndre Schwarz case M88E1000_E_PHY_ID: 4640ac3315c2SAndre Schwarz case M88E1000_I_PHY_ID: 4641ac3315c2SAndre Schwarz case M88E1011_I_PHY_ID: 4642aa070789SRoy Zang case M88E1111_I_PHY_ID: 4643ac3315c2SAndre Schwarz hw->phy_type = e1000_phy_m88; 4644ac3315c2SAndre Schwarz break; 4645ac3315c2SAndre Schwarz case IGP01E1000_I_PHY_ID: 4646ac3315c2SAndre Schwarz if (hw->mac_type == e1000_82541 || 4647aa070789SRoy Zang hw->mac_type == e1000_82541_rev_2 || 4648aa070789SRoy Zang hw->mac_type == e1000_82547 || 4649aa070789SRoy Zang hw->mac_type == e1000_82547_rev_2) { 4650ac3315c2SAndre Schwarz hw->phy_type = e1000_phy_igp; 4651aa070789SRoy Zang break; 4652aa070789SRoy Zang } 4653aa070789SRoy Zang case IGP03E1000_E_PHY_ID: 4654aa070789SRoy Zang hw->phy_type = e1000_phy_igp_3; 4655aa070789SRoy Zang break; 4656aa070789SRoy Zang case IFE_E_PHY_ID: 4657aa070789SRoy Zang case IFE_PLUS_E_PHY_ID: 4658aa070789SRoy Zang case IFE_C_E_PHY_ID: 4659aa070789SRoy Zang hw->phy_type = e1000_phy_ife; 4660aa070789SRoy Zang break; 4661aa070789SRoy Zang case GG82563_E_PHY_ID: 4662aa070789SRoy Zang if (hw->mac_type == e1000_80003es2lan) { 4663aa070789SRoy Zang hw->phy_type = e1000_phy_gg82563; 4664ac3315c2SAndre Schwarz break; 4665ac3315c2SAndre Schwarz } 46662c2668f9SRoy Zang case BME1000_E_PHY_ID: 46672c2668f9SRoy Zang hw->phy_type = e1000_phy_bm; 46682c2668f9SRoy Zang break; 466995186063SMarek Vasut case I210_I_PHY_ID: 467095186063SMarek Vasut hw->phy_type = e1000_phy_igb; 467195186063SMarek Vasut break; 4672ac3315c2SAndre Schwarz /* Fall Through */ 4673ac3315c2SAndre Schwarz default: 4674ac3315c2SAndre Schwarz /* Should never have loaded on this device */ 4675ac3315c2SAndre Schwarz hw->phy_type = e1000_phy_undefined; 4676ac3315c2SAndre Schwarz return -E1000_ERR_PHY_TYPE; 4677ac3315c2SAndre Schwarz } 4678ac3315c2SAndre Schwarz 4679ac3315c2SAndre Schwarz return E1000_SUCCESS; 4680ac3315c2SAndre Schwarz } 4681ac3315c2SAndre Schwarz 46822439e4bfSJean-Christophe PLAGNIOL-VILLARD /****************************************************************************** 46832439e4bfSJean-Christophe PLAGNIOL-VILLARD * Probes the expected PHY address for known PHY IDs 46842439e4bfSJean-Christophe PLAGNIOL-VILLARD * 46852439e4bfSJean-Christophe PLAGNIOL-VILLARD * hw - Struct containing variables accessed by shared code 46862439e4bfSJean-Christophe PLAGNIOL-VILLARD ******************************************************************************/ 4687aa070789SRoy Zang static int32_t 46882439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_detect_gig_phy(struct e1000_hw *hw) 46892439e4bfSJean-Christophe PLAGNIOL-VILLARD { 4690aa070789SRoy Zang int32_t phy_init_status, ret_val; 46912439e4bfSJean-Christophe PLAGNIOL-VILLARD uint16_t phy_id_high, phy_id_low; 4692472d5460SYork Sun bool match = false; 46932439e4bfSJean-Christophe PLAGNIOL-VILLARD 46942439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGFUNC(); 46952439e4bfSJean-Christophe PLAGNIOL-VILLARD 4696aa070789SRoy Zang /* The 82571 firmware may still be configuring the PHY. In this 4697aa070789SRoy Zang * case, we cannot access the PHY until the configuration is done. So 4698aa070789SRoy Zang * we explicitly set the PHY values. */ 4699aa070789SRoy Zang if (hw->mac_type == e1000_82571 || 4700aa070789SRoy Zang hw->mac_type == e1000_82572) { 4701aa070789SRoy Zang hw->phy_id = IGP01E1000_I_PHY_ID; 4702aa070789SRoy Zang hw->phy_type = e1000_phy_igp_2; 4703aa070789SRoy Zang return E1000_SUCCESS; 4704aa070789SRoy Zang } 4705aa070789SRoy Zang 4706aa070789SRoy Zang /* ESB-2 PHY reads require e1000_phy_gg82563 to be set because of a 4707aa070789SRoy Zang * work- around that forces PHY page 0 to be set or the reads fail. 4708aa070789SRoy Zang * The rest of the code in this routine uses e1000_read_phy_reg to 4709aa070789SRoy Zang * read the PHY ID. So for ESB-2 we need to have this set so our 4710aa070789SRoy Zang * reads won't fail. If the attached PHY is not a e1000_phy_gg82563, 4711aa070789SRoy Zang * the routines below will figure this out as well. */ 4712aa070789SRoy Zang if (hw->mac_type == e1000_80003es2lan) 4713aa070789SRoy Zang hw->phy_type = e1000_phy_gg82563; 4714aa070789SRoy Zang 47152439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Read the PHY ID Registers to identify which PHY is onboard. */ 4716aa070789SRoy Zang ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high); 4717aa070789SRoy Zang if (ret_val) 4718aa070789SRoy Zang return ret_val; 4719aa070789SRoy Zang 47202439e4bfSJean-Christophe PLAGNIOL-VILLARD hw->phy_id = (uint32_t) (phy_id_high << 16); 4721aa070789SRoy Zang udelay(20); 4722aa070789SRoy Zang ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low); 4723aa070789SRoy Zang if (ret_val) 4724aa070789SRoy Zang return ret_val; 4725aa070789SRoy Zang 47262439e4bfSJean-Christophe PLAGNIOL-VILLARD hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK); 4727aa070789SRoy Zang hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK; 47282439e4bfSJean-Christophe PLAGNIOL-VILLARD 47292439e4bfSJean-Christophe PLAGNIOL-VILLARD switch (hw->mac_type) { 47302439e4bfSJean-Christophe PLAGNIOL-VILLARD case e1000_82543: 47312439e4bfSJean-Christophe PLAGNIOL-VILLARD if (hw->phy_id == M88E1000_E_PHY_ID) 4732472d5460SYork Sun match = true; 47332439e4bfSJean-Christophe PLAGNIOL-VILLARD break; 47342439e4bfSJean-Christophe PLAGNIOL-VILLARD case e1000_82544: 47352439e4bfSJean-Christophe PLAGNIOL-VILLARD if (hw->phy_id == M88E1000_I_PHY_ID) 4736472d5460SYork Sun match = true; 47372439e4bfSJean-Christophe PLAGNIOL-VILLARD break; 47382439e4bfSJean-Christophe PLAGNIOL-VILLARD case e1000_82540: 47392439e4bfSJean-Christophe PLAGNIOL-VILLARD case e1000_82545: 4740aa070789SRoy Zang case e1000_82545_rev_3: 47412439e4bfSJean-Christophe PLAGNIOL-VILLARD case e1000_82546: 4742aa070789SRoy Zang case e1000_82546_rev_3: 47432439e4bfSJean-Christophe PLAGNIOL-VILLARD if (hw->phy_id == M88E1011_I_PHY_ID) 4744472d5460SYork Sun match = true; 47452439e4bfSJean-Christophe PLAGNIOL-VILLARD break; 4746aa070789SRoy Zang case e1000_82541: 4747ac3315c2SAndre Schwarz case e1000_82541_rev_2: 4748aa070789SRoy Zang case e1000_82547: 4749aa070789SRoy Zang case e1000_82547_rev_2: 4750ac3315c2SAndre Schwarz if(hw->phy_id == IGP01E1000_I_PHY_ID) 4751472d5460SYork Sun match = true; 4752ac3315c2SAndre Schwarz 4753ac3315c2SAndre Schwarz break; 4754aa070789SRoy Zang case e1000_82573: 4755aa070789SRoy Zang if (hw->phy_id == M88E1111_I_PHY_ID) 4756472d5460SYork Sun match = true; 4757aa070789SRoy Zang break; 47582c2668f9SRoy Zang case e1000_82574: 47592c2668f9SRoy Zang if (hw->phy_id == BME1000_E_PHY_ID) 4760472d5460SYork Sun match = true; 47612c2668f9SRoy Zang break; 4762aa070789SRoy Zang case e1000_80003es2lan: 4763aa070789SRoy Zang if (hw->phy_id == GG82563_E_PHY_ID) 4764472d5460SYork Sun match = true; 4765aa070789SRoy Zang break; 4766aa070789SRoy Zang case e1000_ich8lan: 4767aa070789SRoy Zang if (hw->phy_id == IGP03E1000_E_PHY_ID) 4768472d5460SYork Sun match = true; 4769aa070789SRoy Zang if (hw->phy_id == IFE_E_PHY_ID) 4770472d5460SYork Sun match = true; 4771aa070789SRoy Zang if (hw->phy_id == IFE_PLUS_E_PHY_ID) 4772472d5460SYork Sun match = true; 4773aa070789SRoy Zang if (hw->phy_id == IFE_C_E_PHY_ID) 4774472d5460SYork Sun match = true; 4775aa070789SRoy Zang break; 477695186063SMarek Vasut case e1000_igb: 477795186063SMarek Vasut if (hw->phy_id == I210_I_PHY_ID) 477895186063SMarek Vasut match = true; 477995186063SMarek Vasut break; 47802439e4bfSJean-Christophe PLAGNIOL-VILLARD default: 47812439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("Invalid MAC type %d\n", hw->mac_type); 47822439e4bfSJean-Christophe PLAGNIOL-VILLARD return -E1000_ERR_CONFIG; 47832439e4bfSJean-Christophe PLAGNIOL-VILLARD } 4784ac3315c2SAndre Schwarz 4785ac3315c2SAndre Schwarz phy_init_status = e1000_set_phy_type(hw); 4786ac3315c2SAndre Schwarz 4787ac3315c2SAndre Schwarz if ((match) && (phy_init_status == E1000_SUCCESS)) { 47882439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("PHY ID 0x%X detected\n", hw->phy_id); 47892439e4bfSJean-Christophe PLAGNIOL-VILLARD return 0; 47902439e4bfSJean-Christophe PLAGNIOL-VILLARD } 47912439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("Invalid PHY ID 0x%X\n", hw->phy_id); 47922439e4bfSJean-Christophe PLAGNIOL-VILLARD return -E1000_ERR_PHY; 47932439e4bfSJean-Christophe PLAGNIOL-VILLARD } 47942439e4bfSJean-Christophe PLAGNIOL-VILLARD 4795aa070789SRoy Zang /***************************************************************************** 4796aa070789SRoy Zang * Set media type and TBI compatibility. 4797aa070789SRoy Zang * 4798aa070789SRoy Zang * hw - Struct containing variables accessed by shared code 4799aa070789SRoy Zang * **************************************************************************/ 4800aa070789SRoy Zang void 4801aa070789SRoy Zang e1000_set_media_type(struct e1000_hw *hw) 4802aa070789SRoy Zang { 4803aa070789SRoy Zang uint32_t status; 4804aa070789SRoy Zang 4805aa070789SRoy Zang DEBUGFUNC(); 4806aa070789SRoy Zang 4807aa070789SRoy Zang if (hw->mac_type != e1000_82543) { 4808aa070789SRoy Zang /* tbi_compatibility is only valid on 82543 */ 4809472d5460SYork Sun hw->tbi_compatibility_en = false; 4810aa070789SRoy Zang } 4811aa070789SRoy Zang 4812aa070789SRoy Zang switch (hw->device_id) { 4813aa070789SRoy Zang case E1000_DEV_ID_82545GM_SERDES: 4814aa070789SRoy Zang case E1000_DEV_ID_82546GB_SERDES: 4815aa070789SRoy Zang case E1000_DEV_ID_82571EB_SERDES: 4816aa070789SRoy Zang case E1000_DEV_ID_82571EB_SERDES_DUAL: 4817aa070789SRoy Zang case E1000_DEV_ID_82571EB_SERDES_QUAD: 4818aa070789SRoy Zang case E1000_DEV_ID_82572EI_SERDES: 4819aa070789SRoy Zang case E1000_DEV_ID_80003ES2LAN_SERDES_DPT: 4820aa070789SRoy Zang hw->media_type = e1000_media_type_internal_serdes; 4821aa070789SRoy Zang break; 4822aa070789SRoy Zang default: 4823aa070789SRoy Zang switch (hw->mac_type) { 4824aa070789SRoy Zang case e1000_82542_rev2_0: 4825aa070789SRoy Zang case e1000_82542_rev2_1: 4826aa070789SRoy Zang hw->media_type = e1000_media_type_fiber; 4827aa070789SRoy Zang break; 4828aa070789SRoy Zang case e1000_ich8lan: 4829aa070789SRoy Zang case e1000_82573: 48302c2668f9SRoy Zang case e1000_82574: 483195186063SMarek Vasut case e1000_igb: 4832aa070789SRoy Zang /* The STATUS_TBIMODE bit is reserved or reused 4833aa070789SRoy Zang * for the this device. 4834aa070789SRoy Zang */ 4835aa070789SRoy Zang hw->media_type = e1000_media_type_copper; 4836aa070789SRoy Zang break; 4837aa070789SRoy Zang default: 4838aa070789SRoy Zang status = E1000_READ_REG(hw, STATUS); 4839aa070789SRoy Zang if (status & E1000_STATUS_TBIMODE) { 4840aa070789SRoy Zang hw->media_type = e1000_media_type_fiber; 4841aa070789SRoy Zang /* tbi_compatibility not valid on fiber */ 4842472d5460SYork Sun hw->tbi_compatibility_en = false; 4843aa070789SRoy Zang } else { 4844aa070789SRoy Zang hw->media_type = e1000_media_type_copper; 4845aa070789SRoy Zang } 4846aa070789SRoy Zang break; 4847aa070789SRoy Zang } 4848aa070789SRoy Zang } 4849aa070789SRoy Zang } 4850aa070789SRoy Zang 48512439e4bfSJean-Christophe PLAGNIOL-VILLARD /** 48522439e4bfSJean-Christophe PLAGNIOL-VILLARD * e1000_sw_init - Initialize general software structures (struct e1000_adapter) 48532439e4bfSJean-Christophe PLAGNIOL-VILLARD * 48542439e4bfSJean-Christophe PLAGNIOL-VILLARD * e1000_sw_init initializes the Adapter private data structure. 48552439e4bfSJean-Christophe PLAGNIOL-VILLARD * Fields are initialized based on PCI device information and 48562439e4bfSJean-Christophe PLAGNIOL-VILLARD * OS network device settings (MTU size). 48572439e4bfSJean-Christophe PLAGNIOL-VILLARD **/ 48582439e4bfSJean-Christophe PLAGNIOL-VILLARD 48592439e4bfSJean-Christophe PLAGNIOL-VILLARD static int 4860d60626f8SKyle Moffett e1000_sw_init(struct eth_device *nic) 48612439e4bfSJean-Christophe PLAGNIOL-VILLARD { 48622439e4bfSJean-Christophe PLAGNIOL-VILLARD struct e1000_hw *hw = (typeof(hw)) nic->priv; 48632439e4bfSJean-Christophe PLAGNIOL-VILLARD int result; 48642439e4bfSJean-Christophe PLAGNIOL-VILLARD 48652439e4bfSJean-Christophe PLAGNIOL-VILLARD /* PCI config space info */ 48662439e4bfSJean-Christophe PLAGNIOL-VILLARD pci_read_config_word(hw->pdev, PCI_VENDOR_ID, &hw->vendor_id); 48672439e4bfSJean-Christophe PLAGNIOL-VILLARD pci_read_config_word(hw->pdev, PCI_DEVICE_ID, &hw->device_id); 48682439e4bfSJean-Christophe PLAGNIOL-VILLARD pci_read_config_word(hw->pdev, PCI_SUBSYSTEM_VENDOR_ID, 48692439e4bfSJean-Christophe PLAGNIOL-VILLARD &hw->subsystem_vendor_id); 48702439e4bfSJean-Christophe PLAGNIOL-VILLARD pci_read_config_word(hw->pdev, PCI_SUBSYSTEM_ID, &hw->subsystem_id); 48712439e4bfSJean-Christophe PLAGNIOL-VILLARD 48722439e4bfSJean-Christophe PLAGNIOL-VILLARD pci_read_config_byte(hw->pdev, PCI_REVISION_ID, &hw->revision_id); 48732439e4bfSJean-Christophe PLAGNIOL-VILLARD pci_read_config_word(hw->pdev, PCI_COMMAND, &hw->pci_cmd_word); 48742439e4bfSJean-Christophe PLAGNIOL-VILLARD 48752439e4bfSJean-Christophe PLAGNIOL-VILLARD /* identify the MAC */ 48762439e4bfSJean-Christophe PLAGNIOL-VILLARD result = e1000_set_mac_type(hw); 48772439e4bfSJean-Christophe PLAGNIOL-VILLARD if (result) { 4878d60626f8SKyle Moffett E1000_ERR(hw->nic, "Unknown MAC Type\n"); 48792439e4bfSJean-Christophe PLAGNIOL-VILLARD return result; 48802439e4bfSJean-Christophe PLAGNIOL-VILLARD } 48812439e4bfSJean-Christophe PLAGNIOL-VILLARD 4882aa070789SRoy Zang switch (hw->mac_type) { 4883aa070789SRoy Zang default: 4884aa070789SRoy Zang break; 4885aa070789SRoy Zang case e1000_82541: 4886aa070789SRoy Zang case e1000_82547: 4887aa070789SRoy Zang case e1000_82541_rev_2: 4888aa070789SRoy Zang case e1000_82547_rev_2: 4889aa070789SRoy Zang hw->phy_init_script = 1; 4890aa070789SRoy Zang break; 4891aa070789SRoy Zang } 4892aa070789SRoy Zang 48932439e4bfSJean-Christophe PLAGNIOL-VILLARD /* flow control settings */ 48942439e4bfSJean-Christophe PLAGNIOL-VILLARD hw->fc_high_water = E1000_FC_HIGH_THRESH; 48952439e4bfSJean-Christophe PLAGNIOL-VILLARD hw->fc_low_water = E1000_FC_LOW_THRESH; 48962439e4bfSJean-Christophe PLAGNIOL-VILLARD hw->fc_pause_time = E1000_FC_PAUSE_TIME; 48972439e4bfSJean-Christophe PLAGNIOL-VILLARD hw->fc_send_xon = 1; 48982439e4bfSJean-Christophe PLAGNIOL-VILLARD 48992439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Media type - copper or fiber */ 490095186063SMarek Vasut hw->tbi_compatibility_en = true; 4901aa070789SRoy Zang e1000_set_media_type(hw); 49022439e4bfSJean-Christophe PLAGNIOL-VILLARD 49032439e4bfSJean-Christophe PLAGNIOL-VILLARD if (hw->mac_type >= e1000_82543) { 49042439e4bfSJean-Christophe PLAGNIOL-VILLARD uint32_t status = E1000_READ_REG(hw, STATUS); 49052439e4bfSJean-Christophe PLAGNIOL-VILLARD 49062439e4bfSJean-Christophe PLAGNIOL-VILLARD if (status & E1000_STATUS_TBIMODE) { 49072439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("fiber interface\n"); 49082439e4bfSJean-Christophe PLAGNIOL-VILLARD hw->media_type = e1000_media_type_fiber; 49092439e4bfSJean-Christophe PLAGNIOL-VILLARD } else { 49102439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("copper interface\n"); 49112439e4bfSJean-Christophe PLAGNIOL-VILLARD hw->media_type = e1000_media_type_copper; 49122439e4bfSJean-Christophe PLAGNIOL-VILLARD } 49132439e4bfSJean-Christophe PLAGNIOL-VILLARD } else { 49142439e4bfSJean-Christophe PLAGNIOL-VILLARD hw->media_type = e1000_media_type_fiber; 49152439e4bfSJean-Christophe PLAGNIOL-VILLARD } 49162439e4bfSJean-Christophe PLAGNIOL-VILLARD 4917472d5460SYork Sun hw->wait_autoneg_complete = true; 49182439e4bfSJean-Christophe PLAGNIOL-VILLARD if (hw->mac_type < e1000_82543) 49192439e4bfSJean-Christophe PLAGNIOL-VILLARD hw->report_tx_early = 0; 49202439e4bfSJean-Christophe PLAGNIOL-VILLARD else 49212439e4bfSJean-Christophe PLAGNIOL-VILLARD hw->report_tx_early = 1; 49222439e4bfSJean-Christophe PLAGNIOL-VILLARD 49232439e4bfSJean-Christophe PLAGNIOL-VILLARD return E1000_SUCCESS; 49242439e4bfSJean-Christophe PLAGNIOL-VILLARD } 49252439e4bfSJean-Christophe PLAGNIOL-VILLARD 49262439e4bfSJean-Christophe PLAGNIOL-VILLARD void 49272439e4bfSJean-Christophe PLAGNIOL-VILLARD fill_rx(struct e1000_hw *hw) 49282439e4bfSJean-Christophe PLAGNIOL-VILLARD { 49292439e4bfSJean-Christophe PLAGNIOL-VILLARD struct e1000_rx_desc *rd; 4930*06e07f65SMinghuan Lian unsigned long flush_start, flush_end; 49312439e4bfSJean-Christophe PLAGNIOL-VILLARD 49322439e4bfSJean-Christophe PLAGNIOL-VILLARD rx_last = rx_tail; 49332439e4bfSJean-Christophe PLAGNIOL-VILLARD rd = rx_base + rx_tail; 49342439e4bfSJean-Christophe PLAGNIOL-VILLARD rx_tail = (rx_tail + 1) % 8; 49352439e4bfSJean-Christophe PLAGNIOL-VILLARD memset(rd, 0, 16); 4936*06e07f65SMinghuan Lian rd->buffer_addr = cpu_to_le64((unsigned long)packet); 4937873e8e01SMarek Vasut 4938873e8e01SMarek Vasut /* 4939873e8e01SMarek Vasut * Make sure there are no stale data in WB over this area, which 4940873e8e01SMarek Vasut * might get written into the memory while the e1000 also writes 4941873e8e01SMarek Vasut * into the same memory area. 4942873e8e01SMarek Vasut */ 4943*06e07f65SMinghuan Lian invalidate_dcache_range((unsigned long)packet, 4944*06e07f65SMinghuan Lian (unsigned long)packet + 4096); 4945873e8e01SMarek Vasut /* Dump the DMA descriptor into RAM. */ 4946*06e07f65SMinghuan Lian flush_start = ((unsigned long)rd) & ~(ARCH_DMA_MINALIGN - 1); 4947873e8e01SMarek Vasut flush_end = flush_start + roundup(sizeof(*rd), ARCH_DMA_MINALIGN); 4948873e8e01SMarek Vasut flush_dcache_range(flush_start, flush_end); 4949873e8e01SMarek Vasut 49502439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, RDT, rx_tail); 49512439e4bfSJean-Christophe PLAGNIOL-VILLARD } 49522439e4bfSJean-Christophe PLAGNIOL-VILLARD 49532439e4bfSJean-Christophe PLAGNIOL-VILLARD /** 49542439e4bfSJean-Christophe PLAGNIOL-VILLARD * e1000_configure_tx - Configure 8254x Transmit Unit after Reset 49552439e4bfSJean-Christophe PLAGNIOL-VILLARD * @adapter: board private structure 49562439e4bfSJean-Christophe PLAGNIOL-VILLARD * 49572439e4bfSJean-Christophe PLAGNIOL-VILLARD * Configure the Tx unit of the MAC after a reset. 49582439e4bfSJean-Christophe PLAGNIOL-VILLARD **/ 49592439e4bfSJean-Christophe PLAGNIOL-VILLARD 49602439e4bfSJean-Christophe PLAGNIOL-VILLARD static void 49612439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_configure_tx(struct e1000_hw *hw) 49622439e4bfSJean-Christophe PLAGNIOL-VILLARD { 49632439e4bfSJean-Christophe PLAGNIOL-VILLARD unsigned long tctl; 4964aa070789SRoy Zang unsigned long tipg, tarc; 4965aa070789SRoy Zang uint32_t ipgr1, ipgr2; 49662439e4bfSJean-Christophe PLAGNIOL-VILLARD 4967*06e07f65SMinghuan Lian E1000_WRITE_REG(hw, TDBAL, (unsigned long)tx_base); 49682439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, TDBAH, 0); 49692439e4bfSJean-Christophe PLAGNIOL-VILLARD 49702439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, TDLEN, 128); 49712439e4bfSJean-Christophe PLAGNIOL-VILLARD 49722439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Setup the HW Tx Head and Tail descriptor pointers */ 49732439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, TDH, 0); 49742439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, TDT, 0); 49752439e4bfSJean-Christophe PLAGNIOL-VILLARD tx_tail = 0; 49762439e4bfSJean-Christophe PLAGNIOL-VILLARD 49772439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Set the default values for the Tx Inter Packet Gap timer */ 4978aa070789SRoy Zang if (hw->mac_type <= e1000_82547_rev_2 && 4979aa070789SRoy Zang (hw->media_type == e1000_media_type_fiber || 4980aa070789SRoy Zang hw->media_type == e1000_media_type_internal_serdes)) 4981aa070789SRoy Zang tipg = DEFAULT_82543_TIPG_IPGT_FIBER; 4982aa070789SRoy Zang else 4983aa070789SRoy Zang tipg = DEFAULT_82543_TIPG_IPGT_COPPER; 4984aa070789SRoy Zang 4985aa070789SRoy Zang /* Set the default values for the Tx Inter Packet Gap timer */ 49862439e4bfSJean-Christophe PLAGNIOL-VILLARD switch (hw->mac_type) { 49872439e4bfSJean-Christophe PLAGNIOL-VILLARD case e1000_82542_rev2_0: 49882439e4bfSJean-Christophe PLAGNIOL-VILLARD case e1000_82542_rev2_1: 49892439e4bfSJean-Christophe PLAGNIOL-VILLARD tipg = DEFAULT_82542_TIPG_IPGT; 4990aa070789SRoy Zang ipgr1 = DEFAULT_82542_TIPG_IPGR1; 4991aa070789SRoy Zang ipgr2 = DEFAULT_82542_TIPG_IPGR2; 4992aa070789SRoy Zang break; 4993aa070789SRoy Zang case e1000_80003es2lan: 4994aa070789SRoy Zang ipgr1 = DEFAULT_82543_TIPG_IPGR1; 4995aa070789SRoy Zang ipgr2 = DEFAULT_80003ES2LAN_TIPG_IPGR2; 49962439e4bfSJean-Christophe PLAGNIOL-VILLARD break; 49972439e4bfSJean-Christophe PLAGNIOL-VILLARD default: 4998aa070789SRoy Zang ipgr1 = DEFAULT_82543_TIPG_IPGR1; 4999aa070789SRoy Zang ipgr2 = DEFAULT_82543_TIPG_IPGR2; 5000aa070789SRoy Zang break; 50012439e4bfSJean-Christophe PLAGNIOL-VILLARD } 5002aa070789SRoy Zang tipg |= ipgr1 << E1000_TIPG_IPGR1_SHIFT; 5003aa070789SRoy Zang tipg |= ipgr2 << E1000_TIPG_IPGR2_SHIFT; 50042439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, TIPG, tipg); 50052439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Program the Transmit Control Register */ 50062439e4bfSJean-Christophe PLAGNIOL-VILLARD tctl = E1000_READ_REG(hw, TCTL); 50072439e4bfSJean-Christophe PLAGNIOL-VILLARD tctl &= ~E1000_TCTL_CT; 50082439e4bfSJean-Christophe PLAGNIOL-VILLARD tctl |= E1000_TCTL_EN | E1000_TCTL_PSP | 50092439e4bfSJean-Christophe PLAGNIOL-VILLARD (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); 5010aa070789SRoy Zang 5011aa070789SRoy Zang if (hw->mac_type == e1000_82571 || hw->mac_type == e1000_82572) { 5012aa070789SRoy Zang tarc = E1000_READ_REG(hw, TARC0); 5013aa070789SRoy Zang /* set the speed mode bit, we'll clear it if we're not at 5014aa070789SRoy Zang * gigabit link later */ 5015aa070789SRoy Zang /* git bit can be set to 1*/ 5016aa070789SRoy Zang } else if (hw->mac_type == e1000_80003es2lan) { 5017aa070789SRoy Zang tarc = E1000_READ_REG(hw, TARC0); 5018aa070789SRoy Zang tarc |= 1; 5019aa070789SRoy Zang E1000_WRITE_REG(hw, TARC0, tarc); 5020aa070789SRoy Zang tarc = E1000_READ_REG(hw, TARC1); 5021aa070789SRoy Zang tarc |= 1; 5022aa070789SRoy Zang E1000_WRITE_REG(hw, TARC1, tarc); 5023aa070789SRoy Zang } 5024aa070789SRoy Zang 50252439e4bfSJean-Christophe PLAGNIOL-VILLARD 50262439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_config_collision_dist(hw); 5027aa070789SRoy Zang /* Setup Transmit Descriptor Settings for eop descriptor */ 5028aa070789SRoy Zang hw->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS; 50292439e4bfSJean-Christophe PLAGNIOL-VILLARD 5030aa070789SRoy Zang /* Need to set up RS bit */ 5031aa070789SRoy Zang if (hw->mac_type < e1000_82543) 5032aa070789SRoy Zang hw->txd_cmd |= E1000_TXD_CMD_RPS; 50332439e4bfSJean-Christophe PLAGNIOL-VILLARD else 5034aa070789SRoy Zang hw->txd_cmd |= E1000_TXD_CMD_RS; 503595186063SMarek Vasut 503695186063SMarek Vasut 503795186063SMarek Vasut if (hw->mac_type == e1000_igb) { 503895186063SMarek Vasut E1000_WRITE_REG(hw, TCTL_EXT, 0x42 << 10); 503995186063SMarek Vasut 504095186063SMarek Vasut uint32_t reg_txdctl = E1000_READ_REG(hw, TXDCTL); 504195186063SMarek Vasut reg_txdctl |= 1 << 25; 504295186063SMarek Vasut E1000_WRITE_REG(hw, TXDCTL, reg_txdctl); 504395186063SMarek Vasut mdelay(20); 504495186063SMarek Vasut } 504595186063SMarek Vasut 504695186063SMarek Vasut 504795186063SMarek Vasut 5048aa070789SRoy Zang E1000_WRITE_REG(hw, TCTL, tctl); 504995186063SMarek Vasut 505095186063SMarek Vasut 50512439e4bfSJean-Christophe PLAGNIOL-VILLARD } 50522439e4bfSJean-Christophe PLAGNIOL-VILLARD 50532439e4bfSJean-Christophe PLAGNIOL-VILLARD /** 50542439e4bfSJean-Christophe PLAGNIOL-VILLARD * e1000_setup_rctl - configure the receive control register 50552439e4bfSJean-Christophe PLAGNIOL-VILLARD * @adapter: Board private structure 50562439e4bfSJean-Christophe PLAGNIOL-VILLARD **/ 50572439e4bfSJean-Christophe PLAGNIOL-VILLARD static void 50582439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_setup_rctl(struct e1000_hw *hw) 50592439e4bfSJean-Christophe PLAGNIOL-VILLARD { 50602439e4bfSJean-Christophe PLAGNIOL-VILLARD uint32_t rctl; 50612439e4bfSJean-Christophe PLAGNIOL-VILLARD 50622439e4bfSJean-Christophe PLAGNIOL-VILLARD rctl = E1000_READ_REG(hw, RCTL); 50632439e4bfSJean-Christophe PLAGNIOL-VILLARD 50642439e4bfSJean-Christophe PLAGNIOL-VILLARD rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 50652439e4bfSJean-Christophe PLAGNIOL-VILLARD 5066aa070789SRoy Zang rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO 5067aa070789SRoy Zang | E1000_RCTL_RDMTS_HALF; /* | 50682439e4bfSJean-Christophe PLAGNIOL-VILLARD (hw.mc_filter_type << E1000_RCTL_MO_SHIFT); */ 50692439e4bfSJean-Christophe PLAGNIOL-VILLARD 50702439e4bfSJean-Christophe PLAGNIOL-VILLARD if (hw->tbi_compatibility_on == 1) 50712439e4bfSJean-Christophe PLAGNIOL-VILLARD rctl |= E1000_RCTL_SBP; 50722439e4bfSJean-Christophe PLAGNIOL-VILLARD else 50732439e4bfSJean-Christophe PLAGNIOL-VILLARD rctl &= ~E1000_RCTL_SBP; 50742439e4bfSJean-Christophe PLAGNIOL-VILLARD 50752439e4bfSJean-Christophe PLAGNIOL-VILLARD rctl &= ~(E1000_RCTL_SZ_4096); 50762439e4bfSJean-Christophe PLAGNIOL-VILLARD rctl |= E1000_RCTL_SZ_2048; 50772439e4bfSJean-Christophe PLAGNIOL-VILLARD rctl &= ~(E1000_RCTL_BSEX | E1000_RCTL_LPE); 50782439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, RCTL, rctl); 50792439e4bfSJean-Christophe PLAGNIOL-VILLARD } 50802439e4bfSJean-Christophe PLAGNIOL-VILLARD 50812439e4bfSJean-Christophe PLAGNIOL-VILLARD /** 50822439e4bfSJean-Christophe PLAGNIOL-VILLARD * e1000_configure_rx - Configure 8254x Receive Unit after Reset 50832439e4bfSJean-Christophe PLAGNIOL-VILLARD * @adapter: board private structure 50842439e4bfSJean-Christophe PLAGNIOL-VILLARD * 50852439e4bfSJean-Christophe PLAGNIOL-VILLARD * Configure the Rx unit of the MAC after a reset. 50862439e4bfSJean-Christophe PLAGNIOL-VILLARD **/ 50872439e4bfSJean-Christophe PLAGNIOL-VILLARD static void 50882439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_configure_rx(struct e1000_hw *hw) 50892439e4bfSJean-Christophe PLAGNIOL-VILLARD { 5090aa070789SRoy Zang unsigned long rctl, ctrl_ext; 50912439e4bfSJean-Christophe PLAGNIOL-VILLARD rx_tail = 0; 50922439e4bfSJean-Christophe PLAGNIOL-VILLARD /* make sure receives are disabled while setting up the descriptors */ 50932439e4bfSJean-Christophe PLAGNIOL-VILLARD rctl = E1000_READ_REG(hw, RCTL); 50942439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, RCTL, rctl & ~E1000_RCTL_EN); 50952439e4bfSJean-Christophe PLAGNIOL-VILLARD if (hw->mac_type >= e1000_82540) { 50962439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Set the interrupt throttling rate. Value is calculated 50972439e4bfSJean-Christophe PLAGNIOL-VILLARD * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns) */ 50982439e4bfSJean-Christophe PLAGNIOL-VILLARD #define MAX_INTS_PER_SEC 8000 50992439e4bfSJean-Christophe PLAGNIOL-VILLARD #define DEFAULT_ITR 1000000000/(MAX_INTS_PER_SEC * 256) 51002439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, ITR, DEFAULT_ITR); 51012439e4bfSJean-Christophe PLAGNIOL-VILLARD } 51022439e4bfSJean-Christophe PLAGNIOL-VILLARD 5103aa070789SRoy Zang if (hw->mac_type >= e1000_82571) { 5104aa070789SRoy Zang ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 5105aa070789SRoy Zang /* Reset delay timers after every interrupt */ 5106aa070789SRoy Zang ctrl_ext |= E1000_CTRL_EXT_INT_TIMER_CLR; 5107aa070789SRoy Zang E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 5108aa070789SRoy Zang E1000_WRITE_FLUSH(hw); 5109aa070789SRoy Zang } 51102439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Setup the Base and Length of the Rx Descriptor Ring */ 5111*06e07f65SMinghuan Lian E1000_WRITE_REG(hw, RDBAL, (unsigned long)rx_base); 51122439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, RDBAH, 0); 51132439e4bfSJean-Christophe PLAGNIOL-VILLARD 51142439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, RDLEN, 128); 51152439e4bfSJean-Christophe PLAGNIOL-VILLARD 51162439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Setup the HW Rx Head and Tail Descriptor Pointers */ 51172439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, RDH, 0); 51182439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, RDT, 0); 51192439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Enable Receives */ 51202439e4bfSJean-Christophe PLAGNIOL-VILLARD 512195186063SMarek Vasut if (hw->mac_type == e1000_igb) { 512295186063SMarek Vasut 512395186063SMarek Vasut uint32_t reg_rxdctl = E1000_READ_REG(hw, RXDCTL); 512495186063SMarek Vasut reg_rxdctl |= 1 << 25; 512595186063SMarek Vasut E1000_WRITE_REG(hw, RXDCTL, reg_rxdctl); 512695186063SMarek Vasut mdelay(20); 512795186063SMarek Vasut } 512895186063SMarek Vasut 51292439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, RCTL, rctl); 513095186063SMarek Vasut 51312439e4bfSJean-Christophe PLAGNIOL-VILLARD fill_rx(hw); 51322439e4bfSJean-Christophe PLAGNIOL-VILLARD } 51332439e4bfSJean-Christophe PLAGNIOL-VILLARD 51342439e4bfSJean-Christophe PLAGNIOL-VILLARD /************************************************************************** 51352439e4bfSJean-Christophe PLAGNIOL-VILLARD POLL - Wait for a frame 51362439e4bfSJean-Christophe PLAGNIOL-VILLARD ***************************************************************************/ 51372439e4bfSJean-Christophe PLAGNIOL-VILLARD static int 51382439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_poll(struct eth_device *nic) 51392439e4bfSJean-Christophe PLAGNIOL-VILLARD { 51402439e4bfSJean-Christophe PLAGNIOL-VILLARD struct e1000_hw *hw = nic->priv; 51412439e4bfSJean-Christophe PLAGNIOL-VILLARD struct e1000_rx_desc *rd; 5142*06e07f65SMinghuan Lian unsigned long inval_start, inval_end; 5143873e8e01SMarek Vasut uint32_t len; 5144873e8e01SMarek Vasut 51452439e4bfSJean-Christophe PLAGNIOL-VILLARD /* return true if there's an ethernet packet ready to read */ 51462439e4bfSJean-Christophe PLAGNIOL-VILLARD rd = rx_base + rx_last; 5147873e8e01SMarek Vasut 5148873e8e01SMarek Vasut /* Re-load the descriptor from RAM. */ 5149*06e07f65SMinghuan Lian inval_start = ((unsigned long)rd) & ~(ARCH_DMA_MINALIGN - 1); 5150873e8e01SMarek Vasut inval_end = inval_start + roundup(sizeof(*rd), ARCH_DMA_MINALIGN); 5151873e8e01SMarek Vasut invalidate_dcache_range(inval_start, inval_end); 5152873e8e01SMarek Vasut 51532439e4bfSJean-Christophe PLAGNIOL-VILLARD if (!(le32_to_cpu(rd->status)) & E1000_RXD_STAT_DD) 51542439e4bfSJean-Christophe PLAGNIOL-VILLARD return 0; 51552439e4bfSJean-Christophe PLAGNIOL-VILLARD /*DEBUGOUT("recv: packet len=%d \n", rd->length); */ 5156873e8e01SMarek Vasut /* Packet received, make sure the data are re-loaded from RAM. */ 5157873e8e01SMarek Vasut len = le32_to_cpu(rd->length); 5158*06e07f65SMinghuan Lian invalidate_dcache_range((unsigned long)packet, 5159*06e07f65SMinghuan Lian (unsigned long)packet + 5160*06e07f65SMinghuan Lian roundup(len, ARCH_DMA_MINALIGN)); 5161873e8e01SMarek Vasut NetReceive((uchar *)packet, len); 51622439e4bfSJean-Christophe PLAGNIOL-VILLARD fill_rx(hw); 51632439e4bfSJean-Christophe PLAGNIOL-VILLARD return 1; 51642439e4bfSJean-Christophe PLAGNIOL-VILLARD } 51652439e4bfSJean-Christophe PLAGNIOL-VILLARD 51662439e4bfSJean-Christophe PLAGNIOL-VILLARD /************************************************************************** 51672439e4bfSJean-Christophe PLAGNIOL-VILLARD TRANSMIT - Transmit a frame 51682439e4bfSJean-Christophe PLAGNIOL-VILLARD ***************************************************************************/ 5169873e8e01SMarek Vasut static int e1000_transmit(struct eth_device *nic, void *txpacket, int length) 51702439e4bfSJean-Christophe PLAGNIOL-VILLARD { 5171873e8e01SMarek Vasut void *nv_packet = (void *)txpacket; 51722439e4bfSJean-Christophe PLAGNIOL-VILLARD struct e1000_hw *hw = nic->priv; 51732439e4bfSJean-Christophe PLAGNIOL-VILLARD struct e1000_tx_desc *txp; 51742439e4bfSJean-Christophe PLAGNIOL-VILLARD int i = 0; 5175*06e07f65SMinghuan Lian unsigned long flush_start, flush_end; 51762439e4bfSJean-Christophe PLAGNIOL-VILLARD 51772439e4bfSJean-Christophe PLAGNIOL-VILLARD txp = tx_base + tx_tail; 51782439e4bfSJean-Christophe PLAGNIOL-VILLARD tx_tail = (tx_tail + 1) % 8; 51792439e4bfSJean-Christophe PLAGNIOL-VILLARD 51808aa858cbSWolfgang Denk txp->buffer_addr = cpu_to_le64(virt_to_bus(hw->pdev, nv_packet)); 5181aa070789SRoy Zang txp->lower.data = cpu_to_le32(hw->txd_cmd | length); 51822439e4bfSJean-Christophe PLAGNIOL-VILLARD txp->upper.data = 0; 5183873e8e01SMarek Vasut 5184873e8e01SMarek Vasut /* Dump the packet into RAM so e1000 can pick them. */ 5185*06e07f65SMinghuan Lian flush_dcache_range((unsigned long)nv_packet, 5186*06e07f65SMinghuan Lian (unsigned long)nv_packet + 5187*06e07f65SMinghuan Lian roundup(length, ARCH_DMA_MINALIGN)); 5188873e8e01SMarek Vasut /* Dump the descriptor into RAM as well. */ 5189*06e07f65SMinghuan Lian flush_start = ((unsigned long)txp) & ~(ARCH_DMA_MINALIGN - 1); 5190873e8e01SMarek Vasut flush_end = flush_start + roundup(sizeof(*txp), ARCH_DMA_MINALIGN); 5191873e8e01SMarek Vasut flush_dcache_range(flush_start, flush_end); 5192873e8e01SMarek Vasut 51932439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, TDT, tx_tail); 51942439e4bfSJean-Christophe PLAGNIOL-VILLARD 5195aa070789SRoy Zang E1000_WRITE_FLUSH(hw); 5196873e8e01SMarek Vasut while (1) { 5197873e8e01SMarek Vasut invalidate_dcache_range(flush_start, flush_end); 5198873e8e01SMarek Vasut if (le32_to_cpu(txp->upper.data) & E1000_TXD_STAT_DD) 5199873e8e01SMarek Vasut break; 52002439e4bfSJean-Christophe PLAGNIOL-VILLARD if (i++ > TOUT_LOOP) { 52012439e4bfSJean-Christophe PLAGNIOL-VILLARD DEBUGOUT("e1000: tx timeout\n"); 52022439e4bfSJean-Christophe PLAGNIOL-VILLARD return 0; 52032439e4bfSJean-Christophe PLAGNIOL-VILLARD } 52042439e4bfSJean-Christophe PLAGNIOL-VILLARD udelay(10); /* give the nic a chance to write to the register */ 52052439e4bfSJean-Christophe PLAGNIOL-VILLARD } 52062439e4bfSJean-Christophe PLAGNIOL-VILLARD return 1; 52072439e4bfSJean-Christophe PLAGNIOL-VILLARD } 52082439e4bfSJean-Christophe PLAGNIOL-VILLARD 52092439e4bfSJean-Christophe PLAGNIOL-VILLARD /*reset function*/ 52102439e4bfSJean-Christophe PLAGNIOL-VILLARD static inline int 52112439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_reset(struct eth_device *nic) 52122439e4bfSJean-Christophe PLAGNIOL-VILLARD { 52132439e4bfSJean-Christophe PLAGNIOL-VILLARD struct e1000_hw *hw = nic->priv; 52142439e4bfSJean-Christophe PLAGNIOL-VILLARD 52152439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_reset_hw(hw); 52162439e4bfSJean-Christophe PLAGNIOL-VILLARD if (hw->mac_type >= e1000_82544) { 52172439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, WUC, 0); 52182439e4bfSJean-Christophe PLAGNIOL-VILLARD } 52192439e4bfSJean-Christophe PLAGNIOL-VILLARD return e1000_init_hw(nic); 52202439e4bfSJean-Christophe PLAGNIOL-VILLARD } 52212439e4bfSJean-Christophe PLAGNIOL-VILLARD 52222439e4bfSJean-Christophe PLAGNIOL-VILLARD /************************************************************************** 52232439e4bfSJean-Christophe PLAGNIOL-VILLARD DISABLE - Turn off ethernet interface 52242439e4bfSJean-Christophe PLAGNIOL-VILLARD ***************************************************************************/ 52252439e4bfSJean-Christophe PLAGNIOL-VILLARD static void 52262439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_disable(struct eth_device *nic) 52272439e4bfSJean-Christophe PLAGNIOL-VILLARD { 52282439e4bfSJean-Christophe PLAGNIOL-VILLARD struct e1000_hw *hw = nic->priv; 52292439e4bfSJean-Christophe PLAGNIOL-VILLARD 52302439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Turn off the ethernet interface */ 52312439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, RCTL, 0); 52322439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, TCTL, 0); 52332439e4bfSJean-Christophe PLAGNIOL-VILLARD 52342439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Clear the transmit ring */ 52352439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, TDH, 0); 52362439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, TDT, 0); 52372439e4bfSJean-Christophe PLAGNIOL-VILLARD 52382439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Clear the receive ring */ 52392439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, RDH, 0); 52402439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, RDT, 0); 52412439e4bfSJean-Christophe PLAGNIOL-VILLARD 52422439e4bfSJean-Christophe PLAGNIOL-VILLARD /* put the card in its initial state */ 52432439e4bfSJean-Christophe PLAGNIOL-VILLARD #if 0 52442439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_WRITE_REG(hw, CTRL, E1000_CTRL_RST); 52452439e4bfSJean-Christophe PLAGNIOL-VILLARD #endif 52462439e4bfSJean-Christophe PLAGNIOL-VILLARD mdelay(10); 52472439e4bfSJean-Christophe PLAGNIOL-VILLARD 52482439e4bfSJean-Christophe PLAGNIOL-VILLARD } 52492439e4bfSJean-Christophe PLAGNIOL-VILLARD 52502439e4bfSJean-Christophe PLAGNIOL-VILLARD /************************************************************************** 52512439e4bfSJean-Christophe PLAGNIOL-VILLARD INIT - set up ethernet interface(s) 52522439e4bfSJean-Christophe PLAGNIOL-VILLARD ***************************************************************************/ 52532439e4bfSJean-Christophe PLAGNIOL-VILLARD static int 52542439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_init(struct eth_device *nic, bd_t * bis) 52552439e4bfSJean-Christophe PLAGNIOL-VILLARD { 52562439e4bfSJean-Christophe PLAGNIOL-VILLARD struct e1000_hw *hw = nic->priv; 52572439e4bfSJean-Christophe PLAGNIOL-VILLARD int ret_val = 0; 52582439e4bfSJean-Christophe PLAGNIOL-VILLARD 52592439e4bfSJean-Christophe PLAGNIOL-VILLARD ret_val = e1000_reset(nic); 52602439e4bfSJean-Christophe PLAGNIOL-VILLARD if (ret_val < 0) { 52612439e4bfSJean-Christophe PLAGNIOL-VILLARD if ((ret_val == -E1000_ERR_NOLINK) || 52622439e4bfSJean-Christophe PLAGNIOL-VILLARD (ret_val == -E1000_ERR_TIMEOUT)) { 5263d60626f8SKyle Moffett E1000_ERR(hw->nic, "Valid Link not detected\n"); 52642439e4bfSJean-Christophe PLAGNIOL-VILLARD } else { 5265d60626f8SKyle Moffett E1000_ERR(hw->nic, "Hardware Initialization Failed\n"); 52662439e4bfSJean-Christophe PLAGNIOL-VILLARD } 52672439e4bfSJean-Christophe PLAGNIOL-VILLARD return 0; 52682439e4bfSJean-Christophe PLAGNIOL-VILLARD } 52692439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_configure_tx(hw); 52702439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_setup_rctl(hw); 52712439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_configure_rx(hw); 52722439e4bfSJean-Christophe PLAGNIOL-VILLARD return 1; 52732439e4bfSJean-Christophe PLAGNIOL-VILLARD } 52742439e4bfSJean-Christophe PLAGNIOL-VILLARD 5275aa070789SRoy Zang /****************************************************************************** 5276aa070789SRoy Zang * Gets the current PCI bus type of hardware 5277aa070789SRoy Zang * 5278aa070789SRoy Zang * hw - Struct containing variables accessed by shared code 5279aa070789SRoy Zang *****************************************************************************/ 5280aa070789SRoy Zang void e1000_get_bus_type(struct e1000_hw *hw) 5281aa070789SRoy Zang { 5282aa070789SRoy Zang uint32_t status; 5283aa070789SRoy Zang 5284aa070789SRoy Zang switch (hw->mac_type) { 5285aa070789SRoy Zang case e1000_82542_rev2_0: 5286aa070789SRoy Zang case e1000_82542_rev2_1: 5287aa070789SRoy Zang hw->bus_type = e1000_bus_type_pci; 5288aa070789SRoy Zang break; 5289aa070789SRoy Zang case e1000_82571: 5290aa070789SRoy Zang case e1000_82572: 5291aa070789SRoy Zang case e1000_82573: 52922c2668f9SRoy Zang case e1000_82574: 5293aa070789SRoy Zang case e1000_80003es2lan: 5294aa070789SRoy Zang case e1000_ich8lan: 529595186063SMarek Vasut case e1000_igb: 5296aa070789SRoy Zang hw->bus_type = e1000_bus_type_pci_express; 5297aa070789SRoy Zang break; 5298aa070789SRoy Zang default: 5299aa070789SRoy Zang status = E1000_READ_REG(hw, STATUS); 5300aa070789SRoy Zang hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ? 5301aa070789SRoy Zang e1000_bus_type_pcix : e1000_bus_type_pci; 5302aa070789SRoy Zang break; 5303aa070789SRoy Zang } 5304aa070789SRoy Zang } 5305aa070789SRoy Zang 5306ce5207e1SKyle Moffett /* A list of all registered e1000 devices */ 5307ce5207e1SKyle Moffett static LIST_HEAD(e1000_hw_list); 5308ce5207e1SKyle Moffett 53092439e4bfSJean-Christophe PLAGNIOL-VILLARD /************************************************************************** 53102439e4bfSJean-Christophe PLAGNIOL-VILLARD PROBE - Look for an adapter, this routine's visible to the outside 53112439e4bfSJean-Christophe PLAGNIOL-VILLARD You should omit the last argument struct pci_device * for a non-PCI NIC 53122439e4bfSJean-Christophe PLAGNIOL-VILLARD ***************************************************************************/ 53132439e4bfSJean-Christophe PLAGNIOL-VILLARD int 53142439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_initialize(bd_t * bis) 53152439e4bfSJean-Christophe PLAGNIOL-VILLARD { 5316d60626f8SKyle Moffett unsigned int i; 53172439e4bfSJean-Christophe PLAGNIOL-VILLARD pci_dev_t devno; 53182439e4bfSJean-Christophe PLAGNIOL-VILLARD 5319f81ecb5dSTimur Tabi DEBUGFUNC(); 5320f81ecb5dSTimur Tabi 5321d60626f8SKyle Moffett /* Find and probe all the matching PCI devices */ 5322d60626f8SKyle Moffett for (i = 0; (devno = pci_find_devices(e1000_supported, i)) >= 0; i++) { 5323d60626f8SKyle Moffett u32 val; 53242439e4bfSJean-Christophe PLAGNIOL-VILLARD 5325d60626f8SKyle Moffett /* 5326d60626f8SKyle Moffett * These will never get freed due to errors, this allows us to 5327d60626f8SKyle Moffett * perform SPI EEPROM programming from U-boot, for example. 5328d60626f8SKyle Moffett */ 5329d60626f8SKyle Moffett struct eth_device *nic = malloc(sizeof(*nic)); 5330d60626f8SKyle Moffett struct e1000_hw *hw = malloc(sizeof(*hw)); 5331d60626f8SKyle Moffett if (!nic || !hw) { 5332d60626f8SKyle Moffett printf("e1000#%u: Out of Memory!\n", i); 53334b29bdb0SKumar Gala free(nic); 5334d60626f8SKyle Moffett free(hw); 5335d60626f8SKyle Moffett continue; 53364b29bdb0SKumar Gala } 53374b29bdb0SKumar Gala 5338d60626f8SKyle Moffett /* Make sure all of the fields are initially zeroed */ 5339f7ac99fdSMatthew McClintock memset(nic, 0, sizeof(*nic)); 53404b29bdb0SKumar Gala memset(hw, 0, sizeof(*hw)); 53414b29bdb0SKumar Gala 5342d60626f8SKyle Moffett /* Assign the passed-in values */ 5343d60626f8SKyle Moffett hw->cardnum = i; 53442439e4bfSJean-Christophe PLAGNIOL-VILLARD hw->pdev = devno; 5345d60626f8SKyle Moffett hw->nic = nic; 53462439e4bfSJean-Christophe PLAGNIOL-VILLARD nic->priv = hw; 53472439e4bfSJean-Christophe PLAGNIOL-VILLARD 5348d60626f8SKyle Moffett /* Generate a card name */ 5349d60626f8SKyle Moffett sprintf(nic->name, "e1000#%u", hw->cardnum); 5350d60626f8SKyle Moffett 5351d60626f8SKyle Moffett /* Print a debug message with the IO base address */ 5352d60626f8SKyle Moffett pci_read_config_dword(devno, PCI_BASE_ADDRESS_0, &val); 5353d60626f8SKyle Moffett E1000_DBG(nic, "iobase 0x%08x\n", val & 0xfffffff0); 5354d60626f8SKyle Moffett 5355d60626f8SKyle Moffett /* Try to enable I/O accesses and bus-mastering */ 5356d60626f8SKyle Moffett val = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; 5357d60626f8SKyle Moffett pci_write_config_dword(devno, PCI_COMMAND, val); 5358d60626f8SKyle Moffett 5359d60626f8SKyle Moffett /* Make sure it worked */ 5360d60626f8SKyle Moffett pci_read_config_dword(devno, PCI_COMMAND, &val); 5361d60626f8SKyle Moffett if (!(val & PCI_COMMAND_MEMORY)) { 5362d60626f8SKyle Moffett E1000_ERR(nic, "Can't enable I/O memory\n"); 5363d60626f8SKyle Moffett continue; 5364d60626f8SKyle Moffett } 5365d60626f8SKyle Moffett if (!(val & PCI_COMMAND_MASTER)) { 5366d60626f8SKyle Moffett E1000_ERR(nic, "Can't enable bus-mastering\n"); 5367d60626f8SKyle Moffett continue; 5368d60626f8SKyle Moffett } 53692439e4bfSJean-Christophe PLAGNIOL-VILLARD 53702439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Are these variables needed? */ 53712439e4bfSJean-Christophe PLAGNIOL-VILLARD hw->fc = e1000_fc_default; 53722439e4bfSJean-Christophe PLAGNIOL-VILLARD hw->original_fc = e1000_fc_default; 53732439e4bfSJean-Christophe PLAGNIOL-VILLARD hw->autoneg_failed = 0; 5374aa070789SRoy Zang hw->autoneg = 1; 5375472d5460SYork Sun hw->get_link_status = true; 5376a4277200SMarcel Ziswiler #ifndef CONFIG_E1000_NO_NVM 537795186063SMarek Vasut hw->eeprom_semaphore_present = true; 5378a4277200SMarcel Ziswiler #endif 5379d60626f8SKyle Moffett hw->hw_addr = pci_map_bar(devno, PCI_BASE_ADDRESS_0, 5380d60626f8SKyle Moffett PCI_REGION_MEM); 53812439e4bfSJean-Christophe PLAGNIOL-VILLARD hw->mac_type = e1000_undefined; 53822439e4bfSJean-Christophe PLAGNIOL-VILLARD 53832439e4bfSJean-Christophe PLAGNIOL-VILLARD /* MAC and Phy settings */ 5384d60626f8SKyle Moffett if (e1000_sw_init(nic) < 0) { 5385d60626f8SKyle Moffett E1000_ERR(nic, "Software init failed\n"); 5386d60626f8SKyle Moffett continue; 53872439e4bfSJean-Christophe PLAGNIOL-VILLARD } 5388aa070789SRoy Zang if (e1000_check_phy_reset_block(hw)) 5389d60626f8SKyle Moffett E1000_ERR(nic, "PHY Reset is blocked!\n"); 5390d60626f8SKyle Moffett 5391ce5207e1SKyle Moffett /* Basic init was OK, reset the hardware and allow SPI access */ 5392aa070789SRoy Zang e1000_reset_hw(hw); 5393ce5207e1SKyle Moffett list_add_tail(&hw->list_node, &e1000_hw_list); 5394d60626f8SKyle Moffett 53958712adfdSRojhalat Ibrahim #ifndef CONFIG_E1000_NO_NVM 5396d60626f8SKyle Moffett /* Validate the EEPROM and get chipset information */ 5397a821d08dSStefan Roese #if !defined(CONFIG_MVBC_1G) 5398aa070789SRoy Zang if (e1000_init_eeprom_params(hw)) { 5399d60626f8SKyle Moffett E1000_ERR(nic, "EEPROM is invalid!\n"); 5400d60626f8SKyle Moffett continue; 5401aa070789SRoy Zang } 540295186063SMarek Vasut if ((E1000_READ_REG(hw, I210_EECD) & E1000_EECD_FLUPD) && 540395186063SMarek Vasut e1000_validate_eeprom_checksum(hw)) 5404d60626f8SKyle Moffett continue; 54052439e4bfSJean-Christophe PLAGNIOL-VILLARD #endif 54062439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_read_mac_addr(nic); 54078712adfdSRojhalat Ibrahim #endif 5408aa070789SRoy Zang e1000_get_bus_type(hw); 54092439e4bfSJean-Christophe PLAGNIOL-VILLARD 54108712adfdSRojhalat Ibrahim #ifndef CONFIG_E1000_NO_NVM 54112439e4bfSJean-Christophe PLAGNIOL-VILLARD printf("e1000: %02x:%02x:%02x:%02x:%02x:%02x\n ", 54122439e4bfSJean-Christophe PLAGNIOL-VILLARD nic->enetaddr[0], nic->enetaddr[1], nic->enetaddr[2], 54132439e4bfSJean-Christophe PLAGNIOL-VILLARD nic->enetaddr[3], nic->enetaddr[4], nic->enetaddr[5]); 54148712adfdSRojhalat Ibrahim #else 54158712adfdSRojhalat Ibrahim memset(nic->enetaddr, 0, 6); 54168712adfdSRojhalat Ibrahim printf("e1000: no NVM\n"); 54178712adfdSRojhalat Ibrahim #endif 54182439e4bfSJean-Christophe PLAGNIOL-VILLARD 5419d60626f8SKyle Moffett /* Set up the function pointers and register the device */ 54202439e4bfSJean-Christophe PLAGNIOL-VILLARD nic->init = e1000_init; 54212439e4bfSJean-Christophe PLAGNIOL-VILLARD nic->recv = e1000_poll; 54222439e4bfSJean-Christophe PLAGNIOL-VILLARD nic->send = e1000_transmit; 54232439e4bfSJean-Christophe PLAGNIOL-VILLARD nic->halt = e1000_disable; 54242439e4bfSJean-Christophe PLAGNIOL-VILLARD eth_register(nic); 54252439e4bfSJean-Christophe PLAGNIOL-VILLARD } 5426d60626f8SKyle Moffett 5427d60626f8SKyle Moffett return i; 54282439e4bfSJean-Christophe PLAGNIOL-VILLARD } 5429ce5207e1SKyle Moffett 5430ce5207e1SKyle Moffett struct e1000_hw *e1000_find_card(unsigned int cardnum) 5431ce5207e1SKyle Moffett { 5432ce5207e1SKyle Moffett struct e1000_hw *hw; 5433ce5207e1SKyle Moffett 5434ce5207e1SKyle Moffett list_for_each_entry(hw, &e1000_hw_list, list_node) 5435ce5207e1SKyle Moffett if (hw->cardnum == cardnum) 5436ce5207e1SKyle Moffett return hw; 5437ce5207e1SKyle Moffett 5438ce5207e1SKyle Moffett return NULL; 5439ce5207e1SKyle Moffett } 5440ce5207e1SKyle Moffett 5441ce5207e1SKyle Moffett #ifdef CONFIG_CMD_E1000 5442ce5207e1SKyle Moffett static int do_e1000(cmd_tbl_t *cmdtp, int flag, 5443ce5207e1SKyle Moffett int argc, char * const argv[]) 5444ce5207e1SKyle Moffett { 5445ce5207e1SKyle Moffett struct e1000_hw *hw; 5446ce5207e1SKyle Moffett 5447ce5207e1SKyle Moffett if (argc < 3) { 5448ce5207e1SKyle Moffett cmd_usage(cmdtp); 5449ce5207e1SKyle Moffett return 1; 5450ce5207e1SKyle Moffett } 5451ce5207e1SKyle Moffett 5452ce5207e1SKyle Moffett /* Make sure we can find the requested e1000 card */ 5453ce5207e1SKyle Moffett hw = e1000_find_card(simple_strtoul(argv[1], NULL, 10)); 5454ce5207e1SKyle Moffett if (!hw) { 5455ce5207e1SKyle Moffett printf("e1000: ERROR: No such device: e1000#%s\n", argv[1]); 5456ce5207e1SKyle Moffett return 1; 5457ce5207e1SKyle Moffett } 5458ce5207e1SKyle Moffett 5459ce5207e1SKyle Moffett if (!strcmp(argv[2], "print-mac-address")) { 5460ce5207e1SKyle Moffett unsigned char *mac = hw->nic->enetaddr; 5461ce5207e1SKyle Moffett printf("%02x:%02x:%02x:%02x:%02x:%02x\n", 5462ce5207e1SKyle Moffett mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]); 5463ce5207e1SKyle Moffett return 0; 5464ce5207e1SKyle Moffett } 5465ce5207e1SKyle Moffett 5466ce5207e1SKyle Moffett #ifdef CONFIG_E1000_SPI 5467ce5207e1SKyle Moffett /* Handle the "SPI" subcommand */ 5468ce5207e1SKyle Moffett if (!strcmp(argv[2], "spi")) 5469ce5207e1SKyle Moffett return do_e1000_spi(cmdtp, hw, argc - 3, argv + 3); 5470ce5207e1SKyle Moffett #endif 5471ce5207e1SKyle Moffett 5472ce5207e1SKyle Moffett cmd_usage(cmdtp); 5473ce5207e1SKyle Moffett return 1; 5474ce5207e1SKyle Moffett } 5475ce5207e1SKyle Moffett 5476ce5207e1SKyle Moffett U_BOOT_CMD( 5477ce5207e1SKyle Moffett e1000, 7, 0, do_e1000, 5478ce5207e1SKyle Moffett "Intel e1000 controller management", 5479ce5207e1SKyle Moffett /* */"<card#> print-mac-address\n" 5480ce5207e1SKyle Moffett #ifdef CONFIG_E1000_SPI 5481ce5207e1SKyle Moffett "e1000 <card#> spi show [<offset> [<length>]]\n" 5482ce5207e1SKyle Moffett "e1000 <card#> spi dump <addr> <offset> <length>\n" 5483ce5207e1SKyle Moffett "e1000 <card#> spi program <addr> <offset> <length>\n" 5484ce5207e1SKyle Moffett "e1000 <card#> spi checksum [update]\n" 5485ce5207e1SKyle Moffett #endif 5486ce5207e1SKyle Moffett " - Manage the Intel E1000 PCI device" 5487ce5207e1SKyle Moffett ); 5488ce5207e1SKyle Moffett #endif /* not CONFIG_CMD_E1000 */ 5489