xref: /openbmc/u-boot/drivers/net/dm9000x.c (revision a71d45d7)
1 /*
2   dm9000.c: Version 1.2 12/15/2003
3 
4 	A Davicom DM9000 ISA NIC fast Ethernet driver for Linux.
5 	Copyright (C) 1997  Sten Wang
6 
7 	This program is free software; you can redistribute it and/or
8 	modify it under the terms of the GNU General Public License
9 	as published by the Free Software Foundation; either version 2
10 	of the License, or (at your option) any later version.
11 
12 	This program is distributed in the hope that it will be useful,
13 	but WITHOUT ANY WARRANTY; without even the implied warranty of
14 	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15 	GNU General Public License for more details.
16 
17   (C)Copyright 1997-1998 DAVICOM Semiconductor,Inc. All Rights Reserved.
18 
19 V0.11	06/20/2001	REG_0A bit3=1, default enable BP with DA match
20 	06/22/2001	Support DM9801 progrmming
21 			E3: R25 = ((R24 + NF) & 0x00ff) | 0xf000
22 			E4: R25 = ((R24 + NF) & 0x00ff) | 0xc200
23 		R17 = (R17 & 0xfff0) | NF + 3
24 			E5: R25 = ((R24 + NF - 3) & 0x00ff) | 0xc200
25 		R17 = (R17 & 0xfff0) | NF
26 
27 v1.00			modify by simon 2001.9.5
28 	                change for kernel 2.4.x
29 
30 v1.1   11/09/2001	fix force mode bug
31 
32 v1.2   03/18/2003       Weilun Huang <weilun_huang@davicom.com.tw>:
33 			Fixed phy reset.
34 			Added tx/rx 32 bit mode.
35 			Cleaned up for kernel merge.
36 
37 --------------------------------------
38 
39        12/15/2003       Initial port to u-boot by
40        			Sascha Hauer <saschahauer@web.de>
41 
42        06/03/2008	Remy Bohmer <linux@bohmer.net>
43 			- Fixed the driver to work with DM9000A.
44 			  (check on ISR receive status bit before reading the
45 			  FIFO as described in DM9000 programming guide and
46 			  application notes)
47 			- Added autodetect of databus width.
48 			- Made debug code compile again.
49 			- Adapt eth_send such that it matches the DM9000*
50 			  application notes. Needed to make it work properly
51 			  for DM9000A.
52 			- Adapted reset procedure to match DM9000 application
53 			  notes (i.e. double reset)
54 			- some minor code cleanups
55 			These changes are tested with DM9000{A,EP,E} together
56 			with a 200MHz Atmel AT91SAM9261 core
57 
58 TODO: external MII is not functional, only internal at the moment.
59 */
60 
61 #include <common.h>
62 #include <command.h>
63 #include <net.h>
64 #include <asm/io.h>
65 #include <dm9000.h>
66 
67 #include "dm9000x.h"
68 
69 /* Board/System/Debug information/definition ---------------- */
70 
71 /* #define CONFIG_DM9000_DEBUG */
72 
73 #ifdef CONFIG_DM9000_DEBUG
74 #define DM9000_DBG(fmt,args...) printf(fmt, ##args)
75 #define DM9000_DMP_PACKET(func,packet,length)  \
76 	do { \
77 		int i; 							\
78 		printf("%s: length: %d\n", func, length);		\
79 		for (i = 0; i < length; i++) {				\
80 			if (i % 8 == 0)					\
81 				printf("\n%s: %02x: ", func, i);	\
82 			printf("%02x ", ((unsigned char *) packet)[i]);	\
83 		} printf("\n");						\
84 	} while(0)
85 #else
86 #define DM9000_DBG(fmt,args...)
87 #define DM9000_DMP_PACKET(func,packet,length)
88 #endif
89 
90 /* Structure/enum declaration ------------------------------- */
91 typedef struct board_info {
92 	u32 runt_length_counter;	/* counter: RX length < 64byte */
93 	u32 long_length_counter;	/* counter: RX length > 1514byte */
94 	u32 reset_counter;	/* counter: RESET */
95 	u32 reset_tx_timeout;	/* RESET caused by TX Timeout */
96 	u32 reset_rx_status;	/* RESET caused by RX Statsus wrong */
97 	u16 tx_pkt_cnt;
98 	u16 queue_start_addr;
99 	u16 dbug_cnt;
100 	u8 phy_addr;
101 	u8 device_wait_reset;	/* device state */
102 	unsigned char srom[128];
103 	void (*outblk)(volatile void *data_ptr, int count);
104 	void (*inblk)(void *data_ptr, int count);
105 	void (*rx_status)(u16 *RxStatus, u16 *RxLen);
106 	struct eth_device netdev;
107 } board_info_t;
108 static board_info_t dm9000_info;
109 
110 
111 /* function declaration ------------------------------------- */
112 static int dm9000_probe(void);
113 static u16 dm9000_phy_read(int);
114 static void dm9000_phy_write(int, u16);
115 static u8 DM9000_ior(int);
116 static void DM9000_iow(int reg, u8 value);
117 
118 /* DM9000 network board routine ---------------------------- */
119 #ifndef CONFIG_DM9000_BYTE_SWAPPED
120 #define DM9000_outb(d,r) writeb(d, (volatile u8 *)(r))
121 #define DM9000_outw(d,r) writew(d, (volatile u16 *)(r))
122 #define DM9000_outl(d,r) writel(d, (volatile u32 *)(r))
123 #define DM9000_inb(r) readb((volatile u8 *)(r))
124 #define DM9000_inw(r) readw((volatile u16 *)(r))
125 #define DM9000_inl(r) readl((volatile u32 *)(r))
126 #else
127 #define DM9000_outb(d, r) __raw_writeb(d, r)
128 #define DM9000_outw(d, r) __raw_writew(d, r)
129 #define DM9000_outl(d, r) __raw_writel(d, r)
130 #define DM9000_inb(r) __raw_readb(r)
131 #define DM9000_inw(r) __raw_readw(r)
132 #define DM9000_inl(r) __raw_readl(r)
133 #endif
134 
135 #ifdef CONFIG_DM9000_DEBUG
136 static void
137 dump_regs(void)
138 {
139 	DM9000_DBG("\n");
140 	DM9000_DBG("NCR   (0x00): %02x\n", DM9000_ior(0));
141 	DM9000_DBG("NSR   (0x01): %02x\n", DM9000_ior(1));
142 	DM9000_DBG("TCR   (0x02): %02x\n", DM9000_ior(2));
143 	DM9000_DBG("TSRI  (0x03): %02x\n", DM9000_ior(3));
144 	DM9000_DBG("TSRII (0x04): %02x\n", DM9000_ior(4));
145 	DM9000_DBG("RCR   (0x05): %02x\n", DM9000_ior(5));
146 	DM9000_DBG("RSR   (0x06): %02x\n", DM9000_ior(6));
147 	DM9000_DBG("ISR   (0xFE): %02x\n", DM9000_ior(DM9000_ISR));
148 	DM9000_DBG("\n");
149 }
150 #endif
151 
152 static void dm9000_outblk_8bit(volatile void *data_ptr, int count)
153 {
154 	int i;
155 	for (i = 0; i < count; i++)
156 		DM9000_outb((((u8 *) data_ptr)[i] & 0xff), DM9000_DATA);
157 }
158 
159 static void dm9000_outblk_16bit(volatile void *data_ptr, int count)
160 {
161 	int i;
162 	u32 tmplen = (count + 1) / 2;
163 
164 	for (i = 0; i < tmplen; i++)
165 		DM9000_outw(((u16 *) data_ptr)[i], DM9000_DATA);
166 }
167 static void dm9000_outblk_32bit(volatile void *data_ptr, int count)
168 {
169 	int i;
170 	u32 tmplen = (count + 3) / 4;
171 
172 	for (i = 0; i < tmplen; i++)
173 		DM9000_outl(((u32 *) data_ptr)[i], DM9000_DATA);
174 }
175 
176 static void dm9000_inblk_8bit(void *data_ptr, int count)
177 {
178 	int i;
179 	for (i = 0; i < count; i++)
180 		((u8 *) data_ptr)[i] = DM9000_inb(DM9000_DATA);
181 }
182 
183 static void dm9000_inblk_16bit(void *data_ptr, int count)
184 {
185 	int i;
186 	u32 tmplen = (count + 1) / 2;
187 
188 	for (i = 0; i < tmplen; i++)
189 		((u16 *) data_ptr)[i] = DM9000_inw(DM9000_DATA);
190 }
191 static void dm9000_inblk_32bit(void *data_ptr, int count)
192 {
193 	int i;
194 	u32 tmplen = (count + 3) / 4;
195 
196 	for (i = 0; i < tmplen; i++)
197 		((u32 *) data_ptr)[i] = DM9000_inl(DM9000_DATA);
198 }
199 
200 static void dm9000_rx_status_32bit(u16 *RxStatus, u16 *RxLen)
201 {
202 	u32 tmpdata;
203 
204 	DM9000_outb(DM9000_MRCMD, DM9000_IO);
205 
206 	tmpdata = DM9000_inl(DM9000_DATA);
207 	*RxStatus = __le16_to_cpu(tmpdata);
208 	*RxLen = __le16_to_cpu(tmpdata >> 16);
209 }
210 
211 static void dm9000_rx_status_16bit(u16 *RxStatus, u16 *RxLen)
212 {
213 	DM9000_outb(DM9000_MRCMD, DM9000_IO);
214 
215 	*RxStatus = __le16_to_cpu(DM9000_inw(DM9000_DATA));
216 	*RxLen = __le16_to_cpu(DM9000_inw(DM9000_DATA));
217 }
218 
219 static void dm9000_rx_status_8bit(u16 *RxStatus, u16 *RxLen)
220 {
221 	DM9000_outb(DM9000_MRCMD, DM9000_IO);
222 
223 	*RxStatus =
224 	    __le16_to_cpu(DM9000_inb(DM9000_DATA) +
225 			  (DM9000_inb(DM9000_DATA) << 8));
226 	*RxLen =
227 	    __le16_to_cpu(DM9000_inb(DM9000_DATA) +
228 			  (DM9000_inb(DM9000_DATA) << 8));
229 }
230 
231 /*
232   Search DM9000 board, allocate space and register it
233 */
234 int
235 dm9000_probe(void)
236 {
237 	u32 id_val;
238 	id_val = DM9000_ior(DM9000_VIDL);
239 	id_val |= DM9000_ior(DM9000_VIDH) << 8;
240 	id_val |= DM9000_ior(DM9000_PIDL) << 16;
241 	id_val |= DM9000_ior(DM9000_PIDH) << 24;
242 	if (id_val == DM9000_ID) {
243 		printf("dm9000 i/o: 0x%x, id: 0x%x \n", CONFIG_DM9000_BASE,
244 		       id_val);
245 		return 0;
246 	} else {
247 		printf("dm9000 not found at 0x%08x id: 0x%08x\n",
248 		       CONFIG_DM9000_BASE, id_val);
249 		return -1;
250 	}
251 }
252 
253 /* General Purpose dm9000 reset routine */
254 static void
255 dm9000_reset(void)
256 {
257 	DM9000_DBG("resetting DM9000\n");
258 
259 	/* Reset DM9000,
260 	   see DM9000 Application Notes V1.22 Jun 11, 2004 page 29 */
261 
262 	/* DEBUG: Make all GPIO0 outputs, all others inputs */
263 	DM9000_iow(DM9000_GPCR, GPCR_GPIO0_OUT);
264 	/* Step 1: Power internal PHY by writing 0 to GPIO0 pin */
265 	DM9000_iow(DM9000_GPR, 0);
266 	/* Step 2: Software reset */
267 	DM9000_iow(DM9000_NCR, (NCR_LBK_INT_MAC | NCR_RST));
268 
269 	do {
270 		DM9000_DBG("resetting the DM9000, 1st reset\n");
271 		udelay(25); /* Wait at least 20 us */
272 	} while (DM9000_ior(DM9000_NCR) & 1);
273 
274 	DM9000_iow(DM9000_NCR, 0);
275 	DM9000_iow(DM9000_NCR, (NCR_LBK_INT_MAC | NCR_RST)); /* Issue a second reset */
276 
277 	do {
278 		DM9000_DBG("resetting the DM9000, 2nd reset\n");
279 		udelay(25); /* Wait at least 20 us */
280 	} while (DM9000_ior(DM9000_NCR) & 1);
281 
282 	/* Check whether the ethernet controller is present */
283 	if ((DM9000_ior(DM9000_PIDL) != 0x0) ||
284 	    (DM9000_ior(DM9000_PIDH) != 0x90))
285 		printf("ERROR: resetting DM9000 -> not responding\n");
286 }
287 
288 /* Initialize dm9000 board
289 */
290 static int dm9000_init(struct eth_device *dev, bd_t *bd)
291 {
292 	int i, oft, lnk;
293 	u8 io_mode;
294 	struct board_info *db = &dm9000_info;
295 
296 	DM9000_DBG("%s\n", __func__);
297 
298 	/* RESET device */
299 	dm9000_reset();
300 
301 	if (dm9000_probe() < 0)
302 		return -1;
303 
304 	/* Auto-detect 8/16/32 bit mode, ISR Bit 6+7 indicate bus width */
305 	io_mode = DM9000_ior(DM9000_ISR) >> 6;
306 
307 	switch (io_mode) {
308 	case 0x0:  /* 16-bit mode */
309 		printf("DM9000: running in 16 bit mode\n");
310 		db->outblk    = dm9000_outblk_16bit;
311 		db->inblk     = dm9000_inblk_16bit;
312 		db->rx_status = dm9000_rx_status_16bit;
313 		break;
314 	case 0x01:  /* 32-bit mode */
315 		printf("DM9000: running in 32 bit mode\n");
316 		db->outblk    = dm9000_outblk_32bit;
317 		db->inblk     = dm9000_inblk_32bit;
318 		db->rx_status = dm9000_rx_status_32bit;
319 		break;
320 	case 0x02: /* 8 bit mode */
321 		printf("DM9000: running in 8 bit mode\n");
322 		db->outblk    = dm9000_outblk_8bit;
323 		db->inblk     = dm9000_inblk_8bit;
324 		db->rx_status = dm9000_rx_status_8bit;
325 		break;
326 	default:
327 		/* Assume 8 bit mode, will probably not work anyway */
328 		printf("DM9000: Undefined IO-mode:0x%x\n", io_mode);
329 		db->outblk    = dm9000_outblk_8bit;
330 		db->inblk     = dm9000_inblk_8bit;
331 		db->rx_status = dm9000_rx_status_8bit;
332 		break;
333 	}
334 
335 	/* Program operating register, only internal phy supported */
336 	DM9000_iow(DM9000_NCR, 0x0);
337 	/* TX Polling clear */
338 	DM9000_iow(DM9000_TCR, 0);
339 	/* Less 3Kb, 200us */
340 	DM9000_iow(DM9000_BPTR, BPTR_BPHW(3) | BPTR_JPT_600US);
341 	/* Flow Control : High/Low Water */
342 	DM9000_iow(DM9000_FCTR, FCTR_HWOT(3) | FCTR_LWOT(8));
343 	/* SH FIXME: This looks strange! Flow Control */
344 	DM9000_iow(DM9000_FCR, 0x0);
345 	/* Special Mode */
346 	DM9000_iow(DM9000_SMCR, 0);
347 	/* clear TX status */
348 	DM9000_iow(DM9000_NSR, NSR_WAKEST | NSR_TX2END | NSR_TX1END);
349 	/* Clear interrupt status */
350 	DM9000_iow(DM9000_ISR, ISR_ROOS | ISR_ROS | ISR_PTS | ISR_PRS);
351 
352 	printf("MAC: %pM\n", dev->enetaddr);
353 
354 	/* fill device MAC address registers */
355 	for (i = 0, oft = DM9000_PAR; i < 6; i++, oft++)
356 		DM9000_iow(oft, dev->enetaddr[i]);
357 	for (i = 0, oft = 0x16; i < 8; i++, oft++)
358 		DM9000_iow(oft, 0xff);
359 
360 	/* read back mac, just to be sure */
361 	for (i = 0, oft = 0x10; i < 6; i++, oft++)
362 		DM9000_DBG("%02x:", DM9000_ior(oft));
363 	DM9000_DBG("\n");
364 
365 	/* Activate DM9000 */
366 	/* RX enable */
367 	DM9000_iow(DM9000_RCR, RCR_DIS_LONG | RCR_DIS_CRC | RCR_RXEN);
368 	/* Enable TX/RX interrupt mask */
369 	DM9000_iow(DM9000_IMR, IMR_PAR);
370 
371 	i = 0;
372 	while (!(dm9000_phy_read(1) & 0x20)) {	/* autonegation complete bit */
373 		udelay(1000);
374 		i++;
375 		if (i == 10000) {
376 			printf("could not establish link\n");
377 			return 0;
378 		}
379 	}
380 
381 	/* see what we've got */
382 	lnk = dm9000_phy_read(17) >> 12;
383 	printf("operating at ");
384 	switch (lnk) {
385 	case 1:
386 		printf("10M half duplex ");
387 		break;
388 	case 2:
389 		printf("10M full duplex ");
390 		break;
391 	case 4:
392 		printf("100M half duplex ");
393 		break;
394 	case 8:
395 		printf("100M full duplex ");
396 		break;
397 	default:
398 		printf("unknown: %d ", lnk);
399 		break;
400 	}
401 	printf("mode\n");
402 	return 0;
403 }
404 
405 /*
406   Hardware start transmission.
407   Send a packet to media from the upper layer.
408 */
409 static int dm9000_send(struct eth_device *netdev, void *packet, int length)
410 {
411 	int tmo;
412 	struct board_info *db = &dm9000_info;
413 
414 	DM9000_DMP_PACKET(__func__ , packet, length);
415 
416 	DM9000_iow(DM9000_ISR, IMR_PTM); /* Clear Tx bit in ISR */
417 
418 	/* Move data to DM9000 TX RAM */
419 	DM9000_outb(DM9000_MWCMD, DM9000_IO); /* Prepare for TX-data */
420 
421 	/* push the data to the TX-fifo */
422 	(db->outblk)(packet, length);
423 
424 	/* Set TX length to DM9000 */
425 	DM9000_iow(DM9000_TXPLL, length & 0xff);
426 	DM9000_iow(DM9000_TXPLH, (length >> 8) & 0xff);
427 
428 	/* Issue TX polling command */
429 	DM9000_iow(DM9000_TCR, TCR_TXREQ); /* Cleared after TX complete */
430 
431 	/* wait for end of transmission */
432 	tmo = get_timer(0) + 5 * CONFIG_SYS_HZ;
433 	while ( !(DM9000_ior(DM9000_NSR) & (NSR_TX1END | NSR_TX2END)) ||
434 		!(DM9000_ior(DM9000_ISR) & IMR_PTM) ) {
435 		if (get_timer(0) >= tmo) {
436 			printf("transmission timeout\n");
437 			break;
438 		}
439 	}
440 	DM9000_iow(DM9000_ISR, IMR_PTM); /* Clear Tx bit in ISR */
441 
442 	DM9000_DBG("transmit done\n\n");
443 	return 0;
444 }
445 
446 /*
447   Stop the interface.
448   The interface is stopped when it is brought.
449 */
450 static void dm9000_halt(struct eth_device *netdev)
451 {
452 	DM9000_DBG("%s\n", __func__);
453 
454 	/* RESET devie */
455 	dm9000_phy_write(0, 0x8000);	/* PHY RESET */
456 	DM9000_iow(DM9000_GPR, 0x01);	/* Power-Down PHY */
457 	DM9000_iow(DM9000_IMR, 0x80);	/* Disable all interrupt */
458 	DM9000_iow(DM9000_RCR, 0x00);	/* Disable RX */
459 }
460 
461 /*
462   Received a packet and pass to upper layer
463 */
464 static int dm9000_rx(struct eth_device *netdev)
465 {
466 	u8 rxbyte, *rdptr = (u8 *) NetRxPackets[0];
467 	u16 RxStatus, RxLen = 0;
468 	struct board_info *db = &dm9000_info;
469 
470 	/* Check packet ready or not, we must check
471 	   the ISR status first for DM9000A */
472 	if (!(DM9000_ior(DM9000_ISR) & 0x01)) /* Rx-ISR bit must be set. */
473 		return 0;
474 
475 	DM9000_iow(DM9000_ISR, 0x01); /* clear PR status latched in bit 0 */
476 
477 	/* There is _at least_ 1 package in the fifo, read them all */
478 	for (;;) {
479 		DM9000_ior(DM9000_MRCMDX);	/* Dummy read */
480 
481 		/* Get most updated data,
482 		   only look at bits 0:1, See application notes DM9000 */
483 		rxbyte = DM9000_inb(DM9000_DATA) & 0x03;
484 
485 		/* Status check: this byte must be 0 or 1 */
486 		if (rxbyte > DM9000_PKT_RDY) {
487 			DM9000_iow(DM9000_RCR, 0x00);	/* Stop Device */
488 			DM9000_iow(DM9000_ISR, 0x80);	/* Stop INT request */
489 			printf("DM9000 error: status check fail: 0x%x\n",
490 				rxbyte);
491 			return 0;
492 		}
493 
494 		if (rxbyte != DM9000_PKT_RDY)
495 			return 0; /* No packet received, ignore */
496 
497 		DM9000_DBG("receiving packet\n");
498 
499 		/* A packet ready now  & Get status/length */
500 		(db->rx_status)(&RxStatus, &RxLen);
501 
502 		DM9000_DBG("rx status: 0x%04x rx len: %d\n", RxStatus, RxLen);
503 
504 		/* Move data from DM9000 */
505 		/* Read received packet from RX SRAM */
506 		(db->inblk)(rdptr, RxLen);
507 
508 		if ((RxStatus & 0xbf00) || (RxLen < 0x40)
509 			|| (RxLen > DM9000_PKT_MAX)) {
510 			if (RxStatus & 0x100) {
511 				printf("rx fifo error\n");
512 			}
513 			if (RxStatus & 0x200) {
514 				printf("rx crc error\n");
515 			}
516 			if (RxStatus & 0x8000) {
517 				printf("rx length error\n");
518 			}
519 			if (RxLen > DM9000_PKT_MAX) {
520 				printf("rx length too big\n");
521 				dm9000_reset();
522 			}
523 		} else {
524 			DM9000_DMP_PACKET(__func__ , rdptr, RxLen);
525 
526 			DM9000_DBG("passing packet to upper layer\n");
527 			NetReceive(NetRxPackets[0], RxLen);
528 		}
529 	}
530 	return 0;
531 }
532 
533 /*
534   Read a word data from SROM
535 */
536 #if !defined(CONFIG_DM9000_NO_SROM)
537 void dm9000_read_srom_word(int offset, u8 *to)
538 {
539 	DM9000_iow(DM9000_EPAR, offset);
540 	DM9000_iow(DM9000_EPCR, 0x4);
541 	udelay(8000);
542 	DM9000_iow(DM9000_EPCR, 0x0);
543 	to[0] = DM9000_ior(DM9000_EPDRL);
544 	to[1] = DM9000_ior(DM9000_EPDRH);
545 }
546 
547 void dm9000_write_srom_word(int offset, u16 val)
548 {
549 	DM9000_iow(DM9000_EPAR, offset);
550 	DM9000_iow(DM9000_EPDRH, ((val >> 8) & 0xff));
551 	DM9000_iow(DM9000_EPDRL, (val & 0xff));
552 	DM9000_iow(DM9000_EPCR, 0x12);
553 	udelay(8000);
554 	DM9000_iow(DM9000_EPCR, 0);
555 }
556 #endif
557 
558 static void dm9000_get_enetaddr(struct eth_device *dev)
559 {
560 #if !defined(CONFIG_DM9000_NO_SROM)
561 	int i;
562 	for (i = 0; i < 3; i++)
563 		dm9000_read_srom_word(i, dev->enetaddr + (2 * i));
564 #endif
565 }
566 
567 /*
568    Read a byte from I/O port
569 */
570 static u8
571 DM9000_ior(int reg)
572 {
573 	DM9000_outb(reg, DM9000_IO);
574 	return DM9000_inb(DM9000_DATA);
575 }
576 
577 /*
578    Write a byte to I/O port
579 */
580 static void
581 DM9000_iow(int reg, u8 value)
582 {
583 	DM9000_outb(reg, DM9000_IO);
584 	DM9000_outb(value, DM9000_DATA);
585 }
586 
587 /*
588    Read a word from phyxcer
589 */
590 static u16
591 dm9000_phy_read(int reg)
592 {
593 	u16 val;
594 
595 	/* Fill the phyxcer register into REG_0C */
596 	DM9000_iow(DM9000_EPAR, DM9000_PHY | reg);
597 	DM9000_iow(DM9000_EPCR, 0xc);	/* Issue phyxcer read command */
598 	udelay(100);			/* Wait read complete */
599 	DM9000_iow(DM9000_EPCR, 0x0);	/* Clear phyxcer read command */
600 	val = (DM9000_ior(DM9000_EPDRH) << 8) | DM9000_ior(DM9000_EPDRL);
601 
602 	/* The read data keeps on REG_0D & REG_0E */
603 	DM9000_DBG("dm9000_phy_read(0x%x): 0x%x\n", reg, val);
604 	return val;
605 }
606 
607 /*
608    Write a word to phyxcer
609 */
610 static void
611 dm9000_phy_write(int reg, u16 value)
612 {
613 
614 	/* Fill the phyxcer register into REG_0C */
615 	DM9000_iow(DM9000_EPAR, DM9000_PHY | reg);
616 
617 	/* Fill the written data into REG_0D & REG_0E */
618 	DM9000_iow(DM9000_EPDRL, (value & 0xff));
619 	DM9000_iow(DM9000_EPDRH, ((value >> 8) & 0xff));
620 	DM9000_iow(DM9000_EPCR, 0xa);	/* Issue phyxcer write command */
621 	udelay(500);			/* Wait write complete */
622 	DM9000_iow(DM9000_EPCR, 0x0);	/* Clear phyxcer write command */
623 	DM9000_DBG("dm9000_phy_write(reg:0x%x, value:0x%x)\n", reg, value);
624 }
625 
626 int dm9000_initialize(bd_t *bis)
627 {
628 	struct eth_device *dev = &(dm9000_info.netdev);
629 
630 	/* Load MAC address from EEPROM */
631 	dm9000_get_enetaddr(dev);
632 
633 	dev->init = dm9000_init;
634 	dev->halt = dm9000_halt;
635 	dev->send = dm9000_send;
636 	dev->recv = dm9000_rx;
637 	sprintf(dev->name, "dm9000");
638 
639 	eth_register(dev);
640 
641 	return 0;
642 }
643