1 /* 2 dm9000.c: Version 1.2 12/15/2003 3 4 A Davicom DM9000 ISA NIC fast Ethernet driver for Linux. 5 Copyright (C) 1997 Sten Wang 6 7 This program is free software; you can redistribute it and/or 8 modify it under the terms of the GNU General Public License 9 as published by the Free Software Foundation; either version 2 10 of the License, or (at your option) any later version. 11 12 This program is distributed in the hope that it will be useful, 13 but WITHOUT ANY WARRANTY; without even the implied warranty of 14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 GNU General Public License for more details. 16 17 (C)Copyright 1997-1998 DAVICOM Semiconductor,Inc. All Rights Reserved. 18 19 V0.11 06/20/2001 REG_0A bit3=1, default enable BP with DA match 20 06/22/2001 Support DM9801 progrmming 21 E3: R25 = ((R24 + NF) & 0x00ff) | 0xf000 22 E4: R25 = ((R24 + NF) & 0x00ff) | 0xc200 23 R17 = (R17 & 0xfff0) | NF + 3 24 E5: R25 = ((R24 + NF - 3) & 0x00ff) | 0xc200 25 R17 = (R17 & 0xfff0) | NF 26 27 v1.00 modify by simon 2001.9.5 28 change for kernel 2.4.x 29 30 v1.1 11/09/2001 fix force mode bug 31 32 v1.2 03/18/2003 Weilun Huang <weilun_huang@davicom.com.tw>: 33 Fixed phy reset. 34 Added tx/rx 32 bit mode. 35 Cleaned up for kernel merge. 36 37 -------------------------------------- 38 39 12/15/2003 Initial port to u-boot by Sascha Hauer <saschahauer@web.de> 40 41 TODO: Homerun NIC and longrun NIC are not functional, only internal at the 42 moment. 43 */ 44 45 #include <common.h> 46 #include <command.h> 47 #include <net.h> 48 #include <asm/io.h> 49 50 #ifdef CONFIG_DRIVER_DM9000 51 52 #include "dm9000x.h" 53 54 /* Board/System/Debug information/definition ---------------- */ 55 56 #define DM9801_NOISE_FLOOR 0x08 57 #define DM9802_NOISE_FLOOR 0x05 58 59 /* #define CONFIG_DM9000_DEBUG */ 60 61 #ifdef CONFIG_DM9000_DEBUG 62 #define DM9000_DBG(fmt,args...) printf(fmt ,##args) 63 #else /* */ 64 #define DM9000_DBG(fmt,args...) 65 #endif /* */ 66 enum DM9000_PHY_mode { DM9000_10MHD = 0, DM9000_100MHD = 67 1, DM9000_10MFD = 4, DM9000_100MFD = 5, DM9000_AUTO = 68 8, DM9000_1M_HPNA = 0x10 69 }; 70 enum DM9000_NIC_TYPE { FASTETHER_NIC = 0, HOMERUN_NIC = 1, LONGRUN_NIC = 2 71 }; 72 73 /* Structure/enum declaration ------------------------------- */ 74 typedef struct board_info { 75 u32 runt_length_counter; /* counter: RX length < 64byte */ 76 u32 long_length_counter; /* counter: RX length > 1514byte */ 77 u32 reset_counter; /* counter: RESET */ 78 u32 reset_tx_timeout; /* RESET caused by TX Timeout */ 79 u32 reset_rx_status; /* RESET caused by RX Statsus wrong */ 80 u16 tx_pkt_cnt; 81 u16 queue_start_addr; 82 u16 dbug_cnt; 83 u8 phy_addr; 84 u8 device_wait_reset; /* device state */ 85 u8 nic_type; /* NIC type */ 86 unsigned char srom[128]; 87 } board_info_t; 88 board_info_t dmfe_info; 89 90 /* For module input parameter */ 91 static int media_mode = DM9000_AUTO; 92 static u8 nfloor = 0; 93 94 /* function declaration ------------------------------------- */ 95 int eth_init(bd_t * bd); 96 int eth_send(volatile void *, int); 97 int eth_rx(void); 98 void eth_halt(void); 99 static int dm9000_probe(void); 100 static u16 phy_read(int); 101 static void phy_write(int, u16); 102 u16 read_srom_word(int); 103 static u8 DM9000_ior(int); 104 static void DM9000_iow(int reg, u8 value); 105 106 /* DM9000 network board routine ---------------------------- */ 107 108 #define DM9000_outb(d,r) ( *(volatile u8 *)r = d ) 109 #define DM9000_outw(d,r) ( *(volatile u16 *)r = d ) 110 #define DM9000_outl(d,r) ( *(volatile u32 *)r = d ) 111 #define DM9000_inb(r) (*(volatile u8 *)r) 112 #define DM9000_inw(r) (*(volatile u16 *)r) 113 #define DM9000_inl(r) (*(volatile u32 *)r) 114 115 #ifdef CONFIG_DM9000_DEBUG 116 static void 117 dump_regs(void) 118 { 119 DM9000_DBG("\n"); 120 DM9000_DBG("NCR (0x00): %02x\n", DM9000_ior(0)); 121 DM9000_DBG("NSR (0x01): %02x\n", DM9000_ior(1)); 122 DM9000_DBG("TCR (0x02): %02x\n", DM9000_ior(2)); 123 DM9000_DBG("TSRI (0x03): %02x\n", DM9000_ior(3)); 124 DM9000_DBG("TSRII (0x04): %02x\n", DM9000_ior(4)); 125 DM9000_DBG("RCR (0x05): %02x\n", DM9000_ior(5)); 126 DM9000_DBG("RSR (0x06): %02x\n", DM9000_ior(6)); 127 DM9000_DBG("ISR (0xFE): %02x\n", DM9000_ior(ISR)); 128 DM9000_DBG("\n"); 129 } 130 #endif /* */ 131 132 /* 133 Search DM9000 board, allocate space and register it 134 */ 135 int 136 dm9000_probe(void) 137 { 138 u32 id_val; 139 id_val = DM9000_ior(DM9000_VIDL); 140 id_val |= DM9000_ior(DM9000_VIDH) << 8; 141 id_val |= DM9000_ior(DM9000_PIDL) << 16; 142 id_val |= DM9000_ior(DM9000_PIDH) << 24; 143 if (id_val == DM9000_ID) { 144 printf("dm9000 i/o: 0x%x, id: 0x%x \n", CONFIG_DM9000_BASE, 145 id_val); 146 return 0; 147 } else { 148 printf("dm9000 not found at 0x%08x id: 0x%08x\n", 149 CONFIG_DM9000_BASE, id_val); 150 return -1; 151 } 152 } 153 154 /* Set PHY operationg mode 155 */ 156 static void 157 set_PHY_mode(void) 158 { 159 u16 phy_reg4 = 0x01e1, phy_reg0 = 0x1000; 160 if (!(media_mode & DM9000_AUTO)) { 161 switch (media_mode) { 162 case DM9000_10MHD: 163 phy_reg4 = 0x21; 164 phy_reg0 = 0x0000; 165 break; 166 case DM9000_10MFD: 167 phy_reg4 = 0x41; 168 phy_reg0 = 0x1100; 169 break; 170 case DM9000_100MHD: 171 phy_reg4 = 0x81; 172 phy_reg0 = 0x2000; 173 break; 174 case DM9000_100MFD: 175 phy_reg4 = 0x101; 176 phy_reg0 = 0x3100; 177 break; 178 } 179 phy_write(4, phy_reg4); /* Set PHY media mode */ 180 phy_write(0, phy_reg0); /* Tmp */ 181 } 182 DM9000_iow(DM9000_GPCR, 0x01); /* Let GPIO0 output */ 183 DM9000_iow(DM9000_GPR, 0x00); /* Enable PHY */ 184 } 185 186 /* 187 Init HomeRun DM9801 188 */ 189 static void 190 program_dm9801(u16 HPNA_rev) 191 { 192 __u16 reg16, reg17, reg24, reg25; 193 if (!nfloor) 194 nfloor = DM9801_NOISE_FLOOR; 195 reg16 = phy_read(16); 196 reg17 = phy_read(17); 197 reg24 = phy_read(24); 198 reg25 = phy_read(25); 199 switch (HPNA_rev) { 200 case 0xb900: /* DM9801 E3 */ 201 reg16 |= 0x1000; 202 reg25 = ((reg24 + nfloor) & 0x00ff) | 0xf000; 203 break; 204 case 0xb901: /* DM9801 E4 */ 205 reg25 = ((reg24 + nfloor) & 0x00ff) | 0xc200; 206 reg17 = (reg17 & 0xfff0) + nfloor + 3; 207 break; 208 case 0xb902: /* DM9801 E5 */ 209 case 0xb903: /* DM9801 E6 */ 210 default: 211 reg16 |= 0x1000; 212 reg25 = ((reg24 + nfloor - 3) & 0x00ff) | 0xc200; 213 reg17 = (reg17 & 0xfff0) + nfloor; 214 } 215 phy_write(16, reg16); 216 phy_write(17, reg17); 217 phy_write(25, reg25); 218 } 219 220 /* 221 Init LongRun DM9802 222 */ 223 static void 224 program_dm9802(void) 225 { 226 __u16 reg25; 227 if (!nfloor) 228 nfloor = DM9802_NOISE_FLOOR; 229 reg25 = phy_read(25); 230 reg25 = (reg25 & 0xff00) + nfloor; 231 phy_write(25, reg25); 232 } 233 234 /* Identify NIC type 235 */ 236 static void 237 identify_nic(void) 238 { 239 struct board_info *db = &dmfe_info; /* Point a board information structure */ 240 u16 phy_reg3; 241 DM9000_iow(DM9000_NCR, NCR_EXT_PHY); 242 phy_reg3 = phy_read(3); 243 switch (phy_reg3 & 0xfff0) { 244 case 0xb900: 245 if (phy_read(31) == 0x4404) { 246 db->nic_type = HOMERUN_NIC; 247 program_dm9801(phy_reg3); 248 DM9000_DBG("found homerun NIC\n"); 249 } else { 250 db->nic_type = LONGRUN_NIC; 251 DM9000_DBG("found longrun NIC\n"); 252 program_dm9802(); 253 } 254 break; 255 default: 256 db->nic_type = FASTETHER_NIC; 257 break; 258 } 259 DM9000_iow(DM9000_NCR, 0); 260 } 261 262 /* General Purpose dm9000 reset routine */ 263 static void 264 dm9000_reset(void) 265 { 266 DM9000_DBG("resetting\n"); 267 DM9000_iow(DM9000_NCR, NCR_RST); 268 udelay(1000); /* delay 1ms */ 269 } 270 271 /* Initilize dm9000 board 272 */ 273 int 274 eth_init(bd_t * bd) 275 { 276 int i, oft, lnk; 277 DM9000_DBG("eth_init()\n"); 278 279 /* RESET device */ 280 dm9000_reset(); 281 dm9000_probe(); 282 283 /* NIC Type: FASTETHER, HOMERUN, LONGRUN */ 284 identify_nic(); 285 286 /* GPIO0 on pre-activate PHY */ 287 DM9000_iow(DM9000_GPR, 0x00); /*REG_1F bit0 activate phyxcer */ 288 289 /* Set PHY */ 290 set_PHY_mode(); 291 292 /* Program operating register */ 293 DM9000_iow(DM9000_NCR, 0x0); /* only intern phy supported by now */ 294 DM9000_iow(DM9000_TCR, 0); /* TX Polling clear */ 295 DM9000_iow(DM9000_BPTR, 0x3f); /* Less 3Kb, 200us */ 296 DM9000_iow(DM9000_FCTR, FCTR_HWOT(3) | FCTR_LWOT(8)); /* Flow Control : High/Low Water */ 297 DM9000_iow(DM9000_FCR, 0x0); /* SH FIXME: This looks strange! Flow Control */ 298 DM9000_iow(DM9000_SMCR, 0); /* Special Mode */ 299 DM9000_iow(DM9000_NSR, NSR_WAKEST | NSR_TX2END | NSR_TX1END); /* clear TX status */ 300 DM9000_iow(DM9000_ISR, 0x0f); /* Clear interrupt status */ 301 302 /* Set Node address */ 303 for (i = 0; i < 6; i++) 304 ((u16 *) bd->bi_enetaddr)[i] = read_srom_word(i); 305 306 if (is_zero_ether_addr(bd->bi_enetaddr) || 307 is_multicast_ether_addr(bd->bi_enetaddr)) { 308 /* try reading from environment */ 309 u8 i; 310 char *s, *e; 311 s = getenv ("ethaddr"); 312 for (i = 0; i < 6; ++i) { 313 bd->bi_enetaddr[i] = s ? 314 simple_strtoul (s, &e, 16) : 0; 315 if (s) 316 s = (*e) ? e + 1 : e; 317 } 318 } 319 320 printf("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n", bd->bi_enetaddr[0], 321 bd->bi_enetaddr[1], bd->bi_enetaddr[2], bd->bi_enetaddr[3], 322 bd->bi_enetaddr[4], bd->bi_enetaddr[5]); 323 for (i = 0, oft = 0x10; i < 6; i++, oft++) 324 DM9000_iow(oft, bd->bi_enetaddr[i]); 325 for (i = 0, oft = 0x16; i < 8; i++, oft++) 326 DM9000_iow(oft, 0xff); 327 328 /* read back mac, just to be sure */ 329 for (i = 0, oft = 0x10; i < 6; i++, oft++) 330 DM9000_DBG("%02x:", DM9000_ior(oft)); 331 DM9000_DBG("\n"); 332 333 /* Activate DM9000 */ 334 DM9000_iow(DM9000_RCR, RCR_DIS_LONG | RCR_DIS_CRC | RCR_RXEN); /* RX enable */ 335 DM9000_iow(DM9000_IMR, IMR_PAR); /* Enable TX/RX interrupt mask */ 336 i = 0; 337 while (!(phy_read(1) & 0x20)) { /* autonegation complete bit */ 338 udelay(1000); 339 i++; 340 if (i == 10000) { 341 printf("could not establish link\n"); 342 return 0; 343 } 344 } 345 346 /* see what we've got */ 347 lnk = phy_read(17) >> 12; 348 printf("operating at "); 349 switch (lnk) { 350 case 1: 351 printf("10M half duplex "); 352 break; 353 case 2: 354 printf("10M full duplex "); 355 break; 356 case 4: 357 printf("100M half duplex "); 358 break; 359 case 8: 360 printf("100M full duplex "); 361 break; 362 default: 363 printf("unknown: %d ", lnk); 364 break; 365 } 366 printf("mode\n"); 367 return 0; 368 } 369 370 /* 371 Hardware start transmission. 372 Send a packet to media from the upper layer. 373 */ 374 int 375 eth_send(volatile void *packet, int length) 376 { 377 char *data_ptr; 378 u32 tmplen, i; 379 int tmo; 380 DM9000_DBG("eth_send: length: %d\n", length); 381 for (i = 0; i < length; i++) { 382 if (i % 8 == 0) 383 DM9000_DBG("\nSend: 02x: ", i); 384 DM9000_DBG("%02x ", ((unsigned char *) packet)[i]); 385 } DM9000_DBG("\n"); 386 387 /* Move data to DM9000 TX RAM */ 388 data_ptr = (char *) packet; 389 DM9000_outb(DM9000_MWCMD, DM9000_IO); 390 391 #ifdef CONFIG_DM9000_USE_8BIT 392 /* Byte mode */ 393 for (i = 0; i < length; i++) 394 DM9000_outb((data_ptr[i] & 0xff), DM9000_DATA); 395 396 #endif /* */ 397 #ifdef CONFIG_DM9000_USE_16BIT 398 tmplen = (length + 1) / 2; 399 for (i = 0; i < tmplen; i++) 400 DM9000_outw(((u16 *) data_ptr)[i], DM9000_DATA); 401 402 #endif /* */ 403 #ifdef CONFIG_DM9000_USE_32BIT 404 tmplen = (length + 3) / 4; 405 for (i = 0; i < tmplen; i++) 406 DM9000_outl(((u32 *) data_ptr)[i], DM9000_DATA); 407 408 #endif /* */ 409 410 /* Set TX length to DM9000 */ 411 DM9000_iow(DM9000_TXPLL, length & 0xff); 412 DM9000_iow(DM9000_TXPLH, (length >> 8) & 0xff); 413 414 /* Issue TX polling command */ 415 DM9000_iow(DM9000_TCR, TCR_TXREQ); /* Cleared after TX complete */ 416 417 /* wait for end of transmission */ 418 tmo = get_timer(0) + 5 * CFG_HZ; 419 while (DM9000_ior(DM9000_TCR) & TCR_TXREQ) { 420 if (get_timer(0) >= tmo) { 421 printf("transmission timeout\n"); 422 break; 423 } 424 } 425 DM9000_DBG("transmit done\n\n"); 426 return 0; 427 } 428 429 /* 430 Stop the interface. 431 The interface is stopped when it is brought. 432 */ 433 void 434 eth_halt(void) 435 { 436 DM9000_DBG("eth_halt\n"); 437 438 /* RESET devie */ 439 phy_write(0, 0x8000); /* PHY RESET */ 440 DM9000_iow(DM9000_GPR, 0x01); /* Power-Down PHY */ 441 DM9000_iow(DM9000_IMR, 0x80); /* Disable all interrupt */ 442 DM9000_iow(DM9000_RCR, 0x00); /* Disable RX */ 443 } 444 445 /* 446 Received a packet and pass to upper layer 447 */ 448 int 449 eth_rx(void) 450 { 451 u8 rxbyte, *rdptr = (u8 *) NetRxPackets[0]; 452 u16 RxStatus, RxLen = 0; 453 u32 tmplen, i; 454 #ifdef CONFIG_DM9000_USE_32BIT 455 u32 tmpdata; 456 #endif 457 458 /* Check packet ready or not */ 459 DM9000_ior(DM9000_MRCMDX); /* Dummy read */ 460 rxbyte = DM9000_inb(DM9000_DATA); /* Got most updated data */ 461 if (rxbyte == 0) 462 return 0; 463 464 /* Status check: this byte must be 0 or 1 */ 465 if (rxbyte > 1) { 466 DM9000_iow(DM9000_RCR, 0x00); /* Stop Device */ 467 DM9000_iow(DM9000_ISR, 0x80); /* Stop INT request */ 468 DM9000_DBG("rx status check: %d\n", rxbyte); 469 } 470 DM9000_DBG("receiving packet\n"); 471 472 /* A packet ready now & Get status/length */ 473 DM9000_outb(DM9000_MRCMD, DM9000_IO); 474 475 #ifdef CONFIG_DM9000_USE_8BIT 476 RxStatus = DM9000_inb(DM9000_DATA) + (DM9000_inb(DM9000_DATA) << 8); 477 RxLen = DM9000_inb(DM9000_DATA) + (DM9000_inb(DM9000_DATA) << 8); 478 479 #endif /* */ 480 #ifdef CONFIG_DM9000_USE_16BIT 481 RxStatus = DM9000_inw(DM9000_DATA); 482 RxLen = DM9000_inw(DM9000_DATA); 483 484 #endif /* */ 485 #ifdef CONFIG_DM9000_USE_32BIT 486 tmpdata = DM9000_inl(DM9000_DATA); 487 RxStatus = tmpdata; 488 RxLen = tmpdata >> 16; 489 490 #endif /* */ 491 DM9000_DBG("rx status: 0x%04x rx len: %d\n", RxStatus, RxLen); 492 493 /* Move data from DM9000 */ 494 /* Read received packet from RX SRAM */ 495 #ifdef CONFIG_DM9000_USE_8BIT 496 for (i = 0; i < RxLen; i++) 497 rdptr[i] = DM9000_inb(DM9000_DATA); 498 499 #endif /* */ 500 #ifdef CONFIG_DM9000_USE_16BIT 501 tmplen = (RxLen + 1) / 2; 502 for (i = 0; i < tmplen; i++) 503 ((u16 *) rdptr)[i] = DM9000_inw(DM9000_DATA); 504 505 #endif /* */ 506 #ifdef CONFIG_DM9000_USE_32BIT 507 tmplen = (RxLen + 3) / 4; 508 for (i = 0; i < tmplen; i++) 509 ((u32 *) rdptr)[i] = DM9000_inl(DM9000_DATA); 510 511 #endif /* */ 512 if ((RxStatus & 0xbf00) || (RxLen < 0x40) 513 || (RxLen > DM9000_PKT_MAX)) { 514 if (RxStatus & 0x100) { 515 printf("rx fifo error\n"); 516 } 517 if (RxStatus & 0x200) { 518 printf("rx crc error\n"); 519 } 520 if (RxStatus & 0x8000) { 521 printf("rx length error\n"); 522 } 523 if (RxLen > DM9000_PKT_MAX) { 524 printf("rx length too big\n"); 525 dm9000_reset(); 526 } 527 } else { 528 529 /* Pass to upper layer */ 530 DM9000_DBG("passing packet to upper layer\n"); 531 NetReceive(NetRxPackets[0], RxLen); 532 return RxLen; 533 } 534 return 0; 535 } 536 537 /* 538 Read a word data from SROM 539 */ 540 u16 541 read_srom_word(int offset) 542 { 543 DM9000_iow(DM9000_EPAR, offset); 544 DM9000_iow(DM9000_EPCR, 0x4); 545 udelay(8000); 546 DM9000_iow(DM9000_EPCR, 0x0); 547 return (DM9000_ior(DM9000_EPDRL) + (DM9000_ior(DM9000_EPDRH) << 8)); 548 } 549 550 void 551 write_srom_word(int offset, u16 val) 552 { 553 DM9000_iow(DM9000_EPAR, offset); 554 DM9000_iow(DM9000_EPDRH, ((val >> 8) & 0xff)); 555 DM9000_iow(DM9000_EPDRL, (val & 0xff)); 556 DM9000_iow(DM9000_EPCR, 0x12); 557 udelay(8000); 558 DM9000_iow(DM9000_EPCR, 0); 559 } 560 561 562 /* 563 Read a byte from I/O port 564 */ 565 static u8 566 DM9000_ior(int reg) 567 { 568 DM9000_outb(reg, DM9000_IO); 569 return DM9000_inb(DM9000_DATA); 570 } 571 572 /* 573 Write a byte to I/O port 574 */ 575 static void 576 DM9000_iow(int reg, u8 value) 577 { 578 DM9000_outb(reg, DM9000_IO); 579 DM9000_outb(value, DM9000_DATA); 580 } 581 582 /* 583 Read a word from phyxcer 584 */ 585 static u16 586 phy_read(int reg) 587 { 588 u16 val; 589 590 /* Fill the phyxcer register into REG_0C */ 591 DM9000_iow(DM9000_EPAR, DM9000_PHY | reg); 592 DM9000_iow(DM9000_EPCR, 0xc); /* Issue phyxcer read command */ 593 udelay(100); /* Wait read complete */ 594 DM9000_iow(DM9000_EPCR, 0x0); /* Clear phyxcer read command */ 595 val = (DM9000_ior(DM9000_EPDRH) << 8) | DM9000_ior(DM9000_EPDRL); 596 597 /* The read data keeps on REG_0D & REG_0E */ 598 DM9000_DBG("phy_read(%d): %d\n", reg, val); 599 return val; 600 } 601 602 /* 603 Write a word to phyxcer 604 */ 605 static void 606 phy_write(int reg, u16 value) 607 { 608 609 /* Fill the phyxcer register into REG_0C */ 610 DM9000_iow(DM9000_EPAR, DM9000_PHY | reg); 611 612 /* Fill the written data into REG_0D & REG_0E */ 613 DM9000_iow(DM9000_EPDRL, (value & 0xff)); 614 DM9000_iow(DM9000_EPDRH, ((value >> 8) & 0xff)); 615 DM9000_iow(DM9000_EPCR, 0xa); /* Issue phyxcer write command */ 616 udelay(500); /* Wait write complete */ 617 DM9000_iow(DM9000_EPCR, 0x0); /* Clear phyxcer write command */ 618 DM9000_DBG("phy_write(reg:%d, value:%d)\n", reg, value); 619 } 620 #endif /* CONFIG_DRIVER_DM9000 */ 621