1 /* 2 dm9000.c: Version 1.2 12/15/2003 3 4 A Davicom DM9000 ISA NIC fast Ethernet driver for Linux. 5 Copyright (C) 1997 Sten Wang 6 7 This program is free software; you can redistribute it and/or 8 modify it under the terms of the GNU General Public License 9 as published by the Free Software Foundation; either version 2 10 of the License, or (at your option) any later version. 11 12 This program is distributed in the hope that it will be useful, 13 but WITHOUT ANY WARRANTY; without even the implied warranty of 14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 GNU General Public License for more details. 16 17 (C)Copyright 1997-1998 DAVICOM Semiconductor,Inc. All Rights Reserved. 18 19 V0.11 06/20/2001 REG_0A bit3=1, default enable BP with DA match 20 06/22/2001 Support DM9801 progrmming 21 E3: R25 = ((R24 + NF) & 0x00ff) | 0xf000 22 E4: R25 = ((R24 + NF) & 0x00ff) | 0xc200 23 R17 = (R17 & 0xfff0) | NF + 3 24 E5: R25 = ((R24 + NF - 3) & 0x00ff) | 0xc200 25 R17 = (R17 & 0xfff0) | NF 26 27 v1.00 modify by simon 2001.9.5 28 change for kernel 2.4.x 29 30 v1.1 11/09/2001 fix force mode bug 31 32 v1.2 03/18/2003 Weilun Huang <weilun_huang@davicom.com.tw>: 33 Fixed phy reset. 34 Added tx/rx 32 bit mode. 35 Cleaned up for kernel merge. 36 37 -------------------------------------- 38 39 12/15/2003 Initial port to u-boot by 40 Sascha Hauer <saschahauer@web.de> 41 42 06/03/2008 Remy Bohmer <linux@bohmer.net> 43 - Fixed the driver to work with DM9000A. 44 (check on ISR receive status bit before reading the 45 FIFO as described in DM9000 programming guide and 46 application notes) 47 - Added autodetect of databus width. 48 - Made debug code compile again. 49 - Adapt eth_send such that it matches the DM9000* 50 application notes. Needed to make it work properly 51 for DM9000A. 52 - Adapted reset procedure to match DM9000 application 53 notes (i.e. double reset) 54 - some minor code cleanups 55 These changes are tested with DM9000{A,EP,E} together 56 with a 200MHz Atmel AT91SAM9261 core 57 58 TODO: external MII is not functional, only internal at the moment. 59 */ 60 61 #include <common.h> 62 #include <command.h> 63 #include <net.h> 64 #include <asm/io.h> 65 #include <dm9000.h> 66 67 #include "dm9000x.h" 68 69 /* Board/System/Debug information/definition ---------------- */ 70 71 /* #define CONFIG_DM9000_DEBUG */ 72 73 #ifdef CONFIG_DM9000_DEBUG 74 #define DM9000_DBG(fmt,args...) printf(fmt, ##args) 75 #define DM9000_DMP_PACKET(func,packet,length) \ 76 do { \ 77 int i; \ 78 printf("%s: length: %d\n", func, length); \ 79 for (i = 0; i < length; i++) { \ 80 if (i % 8 == 0) \ 81 printf("\n%s: %02x: ", func, i); \ 82 printf("%02x ", ((unsigned char *) packet)[i]); \ 83 } printf("\n"); \ 84 } while(0) 85 #else 86 #define DM9000_DBG(fmt,args...) 87 #define DM9000_DMP_PACKET(func,packet,length) 88 #endif 89 90 /* Structure/enum declaration ------------------------------- */ 91 typedef struct board_info { 92 u32 runt_length_counter; /* counter: RX length < 64byte */ 93 u32 long_length_counter; /* counter: RX length > 1514byte */ 94 u32 reset_counter; /* counter: RESET */ 95 u32 reset_tx_timeout; /* RESET caused by TX Timeout */ 96 u32 reset_rx_status; /* RESET caused by RX Statsus wrong */ 97 u16 tx_pkt_cnt; 98 u16 queue_start_addr; 99 u16 dbug_cnt; 100 u8 phy_addr; 101 u8 device_wait_reset; /* device state */ 102 unsigned char srom[128]; 103 void (*outblk)(volatile void *data_ptr, int count); 104 void (*inblk)(void *data_ptr, int count); 105 void (*rx_status)(u16 *RxStatus, u16 *RxLen); 106 struct eth_device netdev; 107 } board_info_t; 108 static board_info_t dm9000_info; 109 110 111 /* function declaration ------------------------------------- */ 112 static int dm9000_probe(void); 113 static u16 dm9000_phy_read(int); 114 static void dm9000_phy_write(int, u16); 115 static u8 DM9000_ior(int); 116 static void DM9000_iow(int reg, u8 value); 117 118 /* DM9000 network board routine ---------------------------- */ 119 120 #define DM9000_outb(d,r) writeb(d, (volatile u8 *)(r)) 121 #define DM9000_outw(d,r) writew(d, (volatile u16 *)(r)) 122 #define DM9000_outl(d,r) writel(d, (volatile u32 *)(r)) 123 #define DM9000_inb(r) readb((volatile u8 *)(r)) 124 #define DM9000_inw(r) readw((volatile u16 *)(r)) 125 #define DM9000_inl(r) readl((volatile u32 *)(r)) 126 127 #ifdef CONFIG_DM9000_DEBUG 128 static void 129 dump_regs(void) 130 { 131 DM9000_DBG("\n"); 132 DM9000_DBG("NCR (0x00): %02x\n", DM9000_ior(0)); 133 DM9000_DBG("NSR (0x01): %02x\n", DM9000_ior(1)); 134 DM9000_DBG("TCR (0x02): %02x\n", DM9000_ior(2)); 135 DM9000_DBG("TSRI (0x03): %02x\n", DM9000_ior(3)); 136 DM9000_DBG("TSRII (0x04): %02x\n", DM9000_ior(4)); 137 DM9000_DBG("RCR (0x05): %02x\n", DM9000_ior(5)); 138 DM9000_DBG("RSR (0x06): %02x\n", DM9000_ior(6)); 139 DM9000_DBG("ISR (0xFE): %02x\n", DM9000_ior(DM9000_ISR)); 140 DM9000_DBG("\n"); 141 } 142 #endif 143 144 static void dm9000_outblk_8bit(volatile void *data_ptr, int count) 145 { 146 int i; 147 for (i = 0; i < count; i++) 148 DM9000_outb((((u8 *) data_ptr)[i] & 0xff), DM9000_DATA); 149 } 150 151 static void dm9000_outblk_16bit(volatile void *data_ptr, int count) 152 { 153 int i; 154 u32 tmplen = (count + 1) / 2; 155 156 for (i = 0; i < tmplen; i++) 157 DM9000_outw(((u16 *) data_ptr)[i], DM9000_DATA); 158 } 159 static void dm9000_outblk_32bit(volatile void *data_ptr, int count) 160 { 161 int i; 162 u32 tmplen = (count + 3) / 4; 163 164 for (i = 0; i < tmplen; i++) 165 DM9000_outl(((u32 *) data_ptr)[i], DM9000_DATA); 166 } 167 168 static void dm9000_inblk_8bit(void *data_ptr, int count) 169 { 170 int i; 171 for (i = 0; i < count; i++) 172 ((u8 *) data_ptr)[i] = DM9000_inb(DM9000_DATA); 173 } 174 175 static void dm9000_inblk_16bit(void *data_ptr, int count) 176 { 177 int i; 178 u32 tmplen = (count + 1) / 2; 179 180 for (i = 0; i < tmplen; i++) 181 ((u16 *) data_ptr)[i] = DM9000_inw(DM9000_DATA); 182 } 183 static void dm9000_inblk_32bit(void *data_ptr, int count) 184 { 185 int i; 186 u32 tmplen = (count + 3) / 4; 187 188 for (i = 0; i < tmplen; i++) 189 ((u32 *) data_ptr)[i] = DM9000_inl(DM9000_DATA); 190 } 191 192 static void dm9000_rx_status_32bit(u16 *RxStatus, u16 *RxLen) 193 { 194 u32 tmpdata; 195 196 DM9000_outb(DM9000_MRCMD, DM9000_IO); 197 198 tmpdata = DM9000_inl(DM9000_DATA); 199 *RxStatus = __le16_to_cpu(tmpdata); 200 *RxLen = __le16_to_cpu(tmpdata >> 16); 201 } 202 203 static void dm9000_rx_status_16bit(u16 *RxStatus, u16 *RxLen) 204 { 205 DM9000_outb(DM9000_MRCMD, DM9000_IO); 206 207 *RxStatus = __le16_to_cpu(DM9000_inw(DM9000_DATA)); 208 *RxLen = __le16_to_cpu(DM9000_inw(DM9000_DATA)); 209 } 210 211 static void dm9000_rx_status_8bit(u16 *RxStatus, u16 *RxLen) 212 { 213 DM9000_outb(DM9000_MRCMD, DM9000_IO); 214 215 *RxStatus = 216 __le16_to_cpu(DM9000_inb(DM9000_DATA) + 217 (DM9000_inb(DM9000_DATA) << 8)); 218 *RxLen = 219 __le16_to_cpu(DM9000_inb(DM9000_DATA) + 220 (DM9000_inb(DM9000_DATA) << 8)); 221 } 222 223 /* 224 Search DM9000 board, allocate space and register it 225 */ 226 int 227 dm9000_probe(void) 228 { 229 u32 id_val; 230 id_val = DM9000_ior(DM9000_VIDL); 231 id_val |= DM9000_ior(DM9000_VIDH) << 8; 232 id_val |= DM9000_ior(DM9000_PIDL) << 16; 233 id_val |= DM9000_ior(DM9000_PIDH) << 24; 234 if (id_val == DM9000_ID) { 235 printf("dm9000 i/o: 0x%x, id: 0x%x \n", CONFIG_DM9000_BASE, 236 id_val); 237 return 0; 238 } else { 239 printf("dm9000 not found at 0x%08x id: 0x%08x\n", 240 CONFIG_DM9000_BASE, id_val); 241 return -1; 242 } 243 } 244 245 /* General Purpose dm9000 reset routine */ 246 static void 247 dm9000_reset(void) 248 { 249 DM9000_DBG("resetting DM9000\n"); 250 251 /* Reset DM9000, 252 see DM9000 Application Notes V1.22 Jun 11, 2004 page 29 */ 253 254 /* DEBUG: Make all GPIO0 outputs, all others inputs */ 255 DM9000_iow(DM9000_GPCR, GPCR_GPIO0_OUT); 256 /* Step 1: Power internal PHY by writing 0 to GPIO0 pin */ 257 DM9000_iow(DM9000_GPR, 0); 258 /* Step 2: Software reset */ 259 DM9000_iow(DM9000_NCR, (NCR_LBK_INT_MAC | NCR_RST)); 260 261 do { 262 DM9000_DBG("resetting the DM9000, 1st reset\n"); 263 udelay(25); /* Wait at least 20 us */ 264 } while (DM9000_ior(DM9000_NCR) & 1); 265 266 DM9000_iow(DM9000_NCR, 0); 267 DM9000_iow(DM9000_NCR, (NCR_LBK_INT_MAC | NCR_RST)); /* Issue a second reset */ 268 269 do { 270 DM9000_DBG("resetting the DM9000, 2nd reset\n"); 271 udelay(25); /* Wait at least 20 us */ 272 } while (DM9000_ior(DM9000_NCR) & 1); 273 274 /* Check whether the ethernet controller is present */ 275 if ((DM9000_ior(DM9000_PIDL) != 0x0) || 276 (DM9000_ior(DM9000_PIDH) != 0x90)) 277 printf("ERROR: resetting DM9000 -> not responding\n"); 278 } 279 280 /* Initialize dm9000 board 281 */ 282 static int dm9000_init(struct eth_device *dev, bd_t *bd) 283 { 284 int i, oft, lnk; 285 u8 io_mode; 286 struct board_info *db = &dm9000_info; 287 288 DM9000_DBG("%s\n", __func__); 289 290 /* RESET device */ 291 dm9000_reset(); 292 293 if (dm9000_probe() < 0) 294 return -1; 295 296 /* Auto-detect 8/16/32 bit mode, ISR Bit 6+7 indicate bus width */ 297 io_mode = DM9000_ior(DM9000_ISR) >> 6; 298 299 switch (io_mode) { 300 case 0x0: /* 16-bit mode */ 301 printf("DM9000: running in 16 bit mode\n"); 302 db->outblk = dm9000_outblk_16bit; 303 db->inblk = dm9000_inblk_16bit; 304 db->rx_status = dm9000_rx_status_16bit; 305 break; 306 case 0x01: /* 32-bit mode */ 307 printf("DM9000: running in 32 bit mode\n"); 308 db->outblk = dm9000_outblk_32bit; 309 db->inblk = dm9000_inblk_32bit; 310 db->rx_status = dm9000_rx_status_32bit; 311 break; 312 case 0x02: /* 8 bit mode */ 313 printf("DM9000: running in 8 bit mode\n"); 314 db->outblk = dm9000_outblk_8bit; 315 db->inblk = dm9000_inblk_8bit; 316 db->rx_status = dm9000_rx_status_8bit; 317 break; 318 default: 319 /* Assume 8 bit mode, will probably not work anyway */ 320 printf("DM9000: Undefined IO-mode:0x%x\n", io_mode); 321 db->outblk = dm9000_outblk_8bit; 322 db->inblk = dm9000_inblk_8bit; 323 db->rx_status = dm9000_rx_status_8bit; 324 break; 325 } 326 327 /* Program operating register, only internal phy supported */ 328 DM9000_iow(DM9000_NCR, 0x0); 329 /* TX Polling clear */ 330 DM9000_iow(DM9000_TCR, 0); 331 /* Less 3Kb, 200us */ 332 DM9000_iow(DM9000_BPTR, BPTR_BPHW(3) | BPTR_JPT_600US); 333 /* Flow Control : High/Low Water */ 334 DM9000_iow(DM9000_FCTR, FCTR_HWOT(3) | FCTR_LWOT(8)); 335 /* SH FIXME: This looks strange! Flow Control */ 336 DM9000_iow(DM9000_FCR, 0x0); 337 /* Special Mode */ 338 DM9000_iow(DM9000_SMCR, 0); 339 /* clear TX status */ 340 DM9000_iow(DM9000_NSR, NSR_WAKEST | NSR_TX2END | NSR_TX1END); 341 /* Clear interrupt status */ 342 DM9000_iow(DM9000_ISR, ISR_ROOS | ISR_ROS | ISR_PTS | ISR_PRS); 343 344 printf("MAC: %pM\n", dev->enetaddr); 345 346 /* fill device MAC address registers */ 347 for (i = 0, oft = DM9000_PAR; i < 6; i++, oft++) 348 DM9000_iow(oft, dev->enetaddr[i]); 349 for (i = 0, oft = 0x16; i < 8; i++, oft++) 350 DM9000_iow(oft, 0xff); 351 352 /* read back mac, just to be sure */ 353 for (i = 0, oft = 0x10; i < 6; i++, oft++) 354 DM9000_DBG("%02x:", DM9000_ior(oft)); 355 DM9000_DBG("\n"); 356 357 /* Activate DM9000 */ 358 /* RX enable */ 359 DM9000_iow(DM9000_RCR, RCR_DIS_LONG | RCR_DIS_CRC | RCR_RXEN); 360 /* Enable TX/RX interrupt mask */ 361 DM9000_iow(DM9000_IMR, IMR_PAR); 362 363 i = 0; 364 while (!(dm9000_phy_read(1) & 0x20)) { /* autonegation complete bit */ 365 udelay(1000); 366 i++; 367 if (i == 10000) { 368 printf("could not establish link\n"); 369 return 0; 370 } 371 } 372 373 /* see what we've got */ 374 lnk = dm9000_phy_read(17) >> 12; 375 printf("operating at "); 376 switch (lnk) { 377 case 1: 378 printf("10M half duplex "); 379 break; 380 case 2: 381 printf("10M full duplex "); 382 break; 383 case 4: 384 printf("100M half duplex "); 385 break; 386 case 8: 387 printf("100M full duplex "); 388 break; 389 default: 390 printf("unknown: %d ", lnk); 391 break; 392 } 393 printf("mode\n"); 394 return 0; 395 } 396 397 /* 398 Hardware start transmission. 399 Send a packet to media from the upper layer. 400 */ 401 static int dm9000_send(struct eth_device *netdev, volatile void *packet, 402 int length) 403 { 404 int tmo; 405 struct board_info *db = &dm9000_info; 406 407 DM9000_DMP_PACKET(__func__ , packet, length); 408 409 DM9000_iow(DM9000_ISR, IMR_PTM); /* Clear Tx bit in ISR */ 410 411 /* Move data to DM9000 TX RAM */ 412 DM9000_outb(DM9000_MWCMD, DM9000_IO); /* Prepare for TX-data */ 413 414 /* push the data to the TX-fifo */ 415 (db->outblk)(packet, length); 416 417 /* Set TX length to DM9000 */ 418 DM9000_iow(DM9000_TXPLL, length & 0xff); 419 DM9000_iow(DM9000_TXPLH, (length >> 8) & 0xff); 420 421 /* Issue TX polling command */ 422 DM9000_iow(DM9000_TCR, TCR_TXREQ); /* Cleared after TX complete */ 423 424 /* wait for end of transmission */ 425 tmo = get_timer(0) + 5 * CONFIG_SYS_HZ; 426 while ( !(DM9000_ior(DM9000_NSR) & (NSR_TX1END | NSR_TX2END)) || 427 !(DM9000_ior(DM9000_ISR) & IMR_PTM) ) { 428 if (get_timer(0) >= tmo) { 429 printf("transmission timeout\n"); 430 break; 431 } 432 } 433 DM9000_iow(DM9000_ISR, IMR_PTM); /* Clear Tx bit in ISR */ 434 435 DM9000_DBG("transmit done\n\n"); 436 return 0; 437 } 438 439 /* 440 Stop the interface. 441 The interface is stopped when it is brought. 442 */ 443 static void dm9000_halt(struct eth_device *netdev) 444 { 445 DM9000_DBG("%s\n", __func__); 446 447 /* RESET devie */ 448 dm9000_phy_write(0, 0x8000); /* PHY RESET */ 449 DM9000_iow(DM9000_GPR, 0x01); /* Power-Down PHY */ 450 DM9000_iow(DM9000_IMR, 0x80); /* Disable all interrupt */ 451 DM9000_iow(DM9000_RCR, 0x00); /* Disable RX */ 452 } 453 454 /* 455 Received a packet and pass to upper layer 456 */ 457 static int dm9000_rx(struct eth_device *netdev) 458 { 459 u8 rxbyte, *rdptr = (u8 *) NetRxPackets[0]; 460 u16 RxStatus, RxLen = 0; 461 struct board_info *db = &dm9000_info; 462 463 /* Check packet ready or not, we must check 464 the ISR status first for DM9000A */ 465 if (!(DM9000_ior(DM9000_ISR) & 0x01)) /* Rx-ISR bit must be set. */ 466 return 0; 467 468 DM9000_iow(DM9000_ISR, 0x01); /* clear PR status latched in bit 0 */ 469 470 /* There is _at least_ 1 package in the fifo, read them all */ 471 for (;;) { 472 DM9000_ior(DM9000_MRCMDX); /* Dummy read */ 473 474 /* Get most updated data, 475 only look at bits 0:1, See application notes DM9000 */ 476 rxbyte = DM9000_inb(DM9000_DATA) & 0x03; 477 478 /* Status check: this byte must be 0 or 1 */ 479 if (rxbyte > DM9000_PKT_RDY) { 480 DM9000_iow(DM9000_RCR, 0x00); /* Stop Device */ 481 DM9000_iow(DM9000_ISR, 0x80); /* Stop INT request */ 482 printf("DM9000 error: status check fail: 0x%x\n", 483 rxbyte); 484 return 0; 485 } 486 487 if (rxbyte != DM9000_PKT_RDY) 488 return 0; /* No packet received, ignore */ 489 490 DM9000_DBG("receiving packet\n"); 491 492 /* A packet ready now & Get status/length */ 493 (db->rx_status)(&RxStatus, &RxLen); 494 495 DM9000_DBG("rx status: 0x%04x rx len: %d\n", RxStatus, RxLen); 496 497 /* Move data from DM9000 */ 498 /* Read received packet from RX SRAM */ 499 (db->inblk)(rdptr, RxLen); 500 501 if ((RxStatus & 0xbf00) || (RxLen < 0x40) 502 || (RxLen > DM9000_PKT_MAX)) { 503 if (RxStatus & 0x100) { 504 printf("rx fifo error\n"); 505 } 506 if (RxStatus & 0x200) { 507 printf("rx crc error\n"); 508 } 509 if (RxStatus & 0x8000) { 510 printf("rx length error\n"); 511 } 512 if (RxLen > DM9000_PKT_MAX) { 513 printf("rx length too big\n"); 514 dm9000_reset(); 515 } 516 } else { 517 DM9000_DMP_PACKET(__func__ , rdptr, RxLen); 518 519 DM9000_DBG("passing packet to upper layer\n"); 520 NetReceive(NetRxPackets[0], RxLen); 521 } 522 } 523 return 0; 524 } 525 526 /* 527 Read a word data from SROM 528 */ 529 #if !defined(CONFIG_DM9000_NO_SROM) 530 void dm9000_read_srom_word(int offset, u8 *to) 531 { 532 DM9000_iow(DM9000_EPAR, offset); 533 DM9000_iow(DM9000_EPCR, 0x4); 534 udelay(8000); 535 DM9000_iow(DM9000_EPCR, 0x0); 536 to[0] = DM9000_ior(DM9000_EPDRL); 537 to[1] = DM9000_ior(DM9000_EPDRH); 538 } 539 540 void dm9000_write_srom_word(int offset, u16 val) 541 { 542 DM9000_iow(DM9000_EPAR, offset); 543 DM9000_iow(DM9000_EPDRH, ((val >> 8) & 0xff)); 544 DM9000_iow(DM9000_EPDRL, (val & 0xff)); 545 DM9000_iow(DM9000_EPCR, 0x12); 546 udelay(8000); 547 DM9000_iow(DM9000_EPCR, 0); 548 } 549 #endif 550 551 static void dm9000_get_enetaddr(struct eth_device *dev) 552 { 553 #if !defined(CONFIG_DM9000_NO_SROM) 554 int i; 555 for (i = 0; i < 3; i++) 556 dm9000_read_srom_word(i, dev->enetaddr + (2 * i)); 557 #endif 558 } 559 560 /* 561 Read a byte from I/O port 562 */ 563 static u8 564 DM9000_ior(int reg) 565 { 566 DM9000_outb(reg, DM9000_IO); 567 return DM9000_inb(DM9000_DATA); 568 } 569 570 /* 571 Write a byte to I/O port 572 */ 573 static void 574 DM9000_iow(int reg, u8 value) 575 { 576 DM9000_outb(reg, DM9000_IO); 577 DM9000_outb(value, DM9000_DATA); 578 } 579 580 /* 581 Read a word from phyxcer 582 */ 583 static u16 584 dm9000_phy_read(int reg) 585 { 586 u16 val; 587 588 /* Fill the phyxcer register into REG_0C */ 589 DM9000_iow(DM9000_EPAR, DM9000_PHY | reg); 590 DM9000_iow(DM9000_EPCR, 0xc); /* Issue phyxcer read command */ 591 udelay(100); /* Wait read complete */ 592 DM9000_iow(DM9000_EPCR, 0x0); /* Clear phyxcer read command */ 593 val = (DM9000_ior(DM9000_EPDRH) << 8) | DM9000_ior(DM9000_EPDRL); 594 595 /* The read data keeps on REG_0D & REG_0E */ 596 DM9000_DBG("dm9000_phy_read(0x%x): 0x%x\n", reg, val); 597 return val; 598 } 599 600 /* 601 Write a word to phyxcer 602 */ 603 static void 604 dm9000_phy_write(int reg, u16 value) 605 { 606 607 /* Fill the phyxcer register into REG_0C */ 608 DM9000_iow(DM9000_EPAR, DM9000_PHY | reg); 609 610 /* Fill the written data into REG_0D & REG_0E */ 611 DM9000_iow(DM9000_EPDRL, (value & 0xff)); 612 DM9000_iow(DM9000_EPDRH, ((value >> 8) & 0xff)); 613 DM9000_iow(DM9000_EPCR, 0xa); /* Issue phyxcer write command */ 614 udelay(500); /* Wait write complete */ 615 DM9000_iow(DM9000_EPCR, 0x0); /* Clear phyxcer write command */ 616 DM9000_DBG("dm9000_phy_write(reg:0x%x, value:0x%x)\n", reg, value); 617 } 618 619 int dm9000_initialize(bd_t *bis) 620 { 621 struct eth_device *dev = &(dm9000_info.netdev); 622 623 /* Load MAC address from EEPROM */ 624 dm9000_get_enetaddr(dev); 625 626 dev->init = dm9000_init; 627 dev->halt = dm9000_halt; 628 dev->send = dm9000_send; 629 dev->recv = dm9000_rx; 630 sprintf(dev->name, "dm9000"); 631 632 eth_register(dev); 633 634 return 0; 635 } 636