12439e4bfSJean-Christophe PLAGNIOL-VILLARD /* 22439e4bfSJean-Christophe PLAGNIOL-VILLARD dm9000.c: Version 1.2 12/15/2003 32439e4bfSJean-Christophe PLAGNIOL-VILLARD 42439e4bfSJean-Christophe PLAGNIOL-VILLARD A Davicom DM9000 ISA NIC fast Ethernet driver for Linux. 52439e4bfSJean-Christophe PLAGNIOL-VILLARD Copyright (C) 1997 Sten Wang 62439e4bfSJean-Christophe PLAGNIOL-VILLARD 72439e4bfSJean-Christophe PLAGNIOL-VILLARD This program is free software; you can redistribute it and/or 82439e4bfSJean-Christophe PLAGNIOL-VILLARD modify it under the terms of the GNU General Public License 92439e4bfSJean-Christophe PLAGNIOL-VILLARD as published by the Free Software Foundation; either version 2 102439e4bfSJean-Christophe PLAGNIOL-VILLARD of the License, or (at your option) any later version. 112439e4bfSJean-Christophe PLAGNIOL-VILLARD 122439e4bfSJean-Christophe PLAGNIOL-VILLARD This program is distributed in the hope that it will be useful, 132439e4bfSJean-Christophe PLAGNIOL-VILLARD but WITHOUT ANY WARRANTY; without even the implied warranty of 142439e4bfSJean-Christophe PLAGNIOL-VILLARD MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 152439e4bfSJean-Christophe PLAGNIOL-VILLARD GNU General Public License for more details. 162439e4bfSJean-Christophe PLAGNIOL-VILLARD 172439e4bfSJean-Christophe PLAGNIOL-VILLARD (C)Copyright 1997-1998 DAVICOM Semiconductor,Inc. All Rights Reserved. 182439e4bfSJean-Christophe PLAGNIOL-VILLARD 192439e4bfSJean-Christophe PLAGNIOL-VILLARD V0.11 06/20/2001 REG_0A bit3=1, default enable BP with DA match 202439e4bfSJean-Christophe PLAGNIOL-VILLARD 06/22/2001 Support DM9801 progrmming 212439e4bfSJean-Christophe PLAGNIOL-VILLARD E3: R25 = ((R24 + NF) & 0x00ff) | 0xf000 222439e4bfSJean-Christophe PLAGNIOL-VILLARD E4: R25 = ((R24 + NF) & 0x00ff) | 0xc200 232439e4bfSJean-Christophe PLAGNIOL-VILLARD R17 = (R17 & 0xfff0) | NF + 3 242439e4bfSJean-Christophe PLAGNIOL-VILLARD E5: R25 = ((R24 + NF - 3) & 0x00ff) | 0xc200 252439e4bfSJean-Christophe PLAGNIOL-VILLARD R17 = (R17 & 0xfff0) | NF 262439e4bfSJean-Christophe PLAGNIOL-VILLARD 272439e4bfSJean-Christophe PLAGNIOL-VILLARD v1.00 modify by simon 2001.9.5 282439e4bfSJean-Christophe PLAGNIOL-VILLARD change for kernel 2.4.x 292439e4bfSJean-Christophe PLAGNIOL-VILLARD 302439e4bfSJean-Christophe PLAGNIOL-VILLARD v1.1 11/09/2001 fix force mode bug 312439e4bfSJean-Christophe PLAGNIOL-VILLARD 322439e4bfSJean-Christophe PLAGNIOL-VILLARD v1.2 03/18/2003 Weilun Huang <weilun_huang@davicom.com.tw>: 332439e4bfSJean-Christophe PLAGNIOL-VILLARD Fixed phy reset. 342439e4bfSJean-Christophe PLAGNIOL-VILLARD Added tx/rx 32 bit mode. 352439e4bfSJean-Christophe PLAGNIOL-VILLARD Cleaned up for kernel merge. 362439e4bfSJean-Christophe PLAGNIOL-VILLARD 372439e4bfSJean-Christophe PLAGNIOL-VILLARD -------------------------------------- 382439e4bfSJean-Christophe PLAGNIOL-VILLARD 39a101361bSRemy Bohmer 12/15/2003 Initial port to u-boot by 40a101361bSRemy Bohmer Sascha Hauer <saschahauer@web.de> 41a101361bSRemy Bohmer 42a101361bSRemy Bohmer 06/03/2008 Remy Bohmer <linux@bohmer.net> 43a101361bSRemy Bohmer - Added autodetect of databus width. 44*134e2662SRemy Bohmer - Made debug code compile again. 45a101361bSRemy Bohmer These changes are tested with DM9000{A,EP,E} together 46a101361bSRemy Bohmer with a 200MHz Atmel AT91SAM92161 core 472439e4bfSJean-Christophe PLAGNIOL-VILLARD 482439e4bfSJean-Christophe PLAGNIOL-VILLARD TODO: Homerun NIC and longrun NIC are not functional, only internal at the 492439e4bfSJean-Christophe PLAGNIOL-VILLARD moment. 502439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 512439e4bfSJean-Christophe PLAGNIOL-VILLARD 522439e4bfSJean-Christophe PLAGNIOL-VILLARD #include <common.h> 532439e4bfSJean-Christophe PLAGNIOL-VILLARD #include <command.h> 542439e4bfSJean-Christophe PLAGNIOL-VILLARD #include <net.h> 552439e4bfSJean-Christophe PLAGNIOL-VILLARD #include <asm/io.h> 562439e4bfSJean-Christophe PLAGNIOL-VILLARD 572439e4bfSJean-Christophe PLAGNIOL-VILLARD #ifdef CONFIG_DRIVER_DM9000 582439e4bfSJean-Christophe PLAGNIOL-VILLARD 592439e4bfSJean-Christophe PLAGNIOL-VILLARD #include "dm9000x.h" 602439e4bfSJean-Christophe PLAGNIOL-VILLARD 612439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Board/System/Debug information/definition ---------------- */ 622439e4bfSJean-Christophe PLAGNIOL-VILLARD 632439e4bfSJean-Christophe PLAGNIOL-VILLARD #define DM9801_NOISE_FLOOR 0x08 642439e4bfSJean-Christophe PLAGNIOL-VILLARD #define DM9802_NOISE_FLOOR 0x05 652439e4bfSJean-Christophe PLAGNIOL-VILLARD 662439e4bfSJean-Christophe PLAGNIOL-VILLARD /* #define CONFIG_DM9000_DEBUG */ 672439e4bfSJean-Christophe PLAGNIOL-VILLARD 682439e4bfSJean-Christophe PLAGNIOL-VILLARD #ifdef CONFIG_DM9000_DEBUG 692439e4bfSJean-Christophe PLAGNIOL-VILLARD #define DM9000_DBG(fmt,args...) printf(fmt, ##args) 70*134e2662SRemy Bohmer #define DM9000_DMP_PACKET(func,packet,length) \ 71*134e2662SRemy Bohmer do { \ 72*134e2662SRemy Bohmer int i; \ 73*134e2662SRemy Bohmer printf(func ": length: %d\n", length); \ 74*134e2662SRemy Bohmer for (i = 0; i < length; i++) { \ 75*134e2662SRemy Bohmer if (i % 8 == 0) \ 76*134e2662SRemy Bohmer printf("\n%s: %02x: ", func, i); \ 77*134e2662SRemy Bohmer printf("%02x ", ((unsigned char *) packet)[i]); \ 78*134e2662SRemy Bohmer } printf("\n"); \ 79*134e2662SRemy Bohmer } while(0) 80*134e2662SRemy Bohmer #else 812439e4bfSJean-Christophe PLAGNIOL-VILLARD #define DM9000_DBG(fmt,args...) 82*134e2662SRemy Bohmer #define DM9000_DMP_PACKET(func,packet,length) 83*134e2662SRemy Bohmer #endif 84*134e2662SRemy Bohmer 852439e4bfSJean-Christophe PLAGNIOL-VILLARD enum DM9000_PHY_mode { DM9000_10MHD = 0, DM9000_100MHD = 862439e4bfSJean-Christophe PLAGNIOL-VILLARD 1, DM9000_10MFD = 4, DM9000_100MFD = 5, DM9000_AUTO = 872439e4bfSJean-Christophe PLAGNIOL-VILLARD 8, DM9000_1M_HPNA = 0x10 882439e4bfSJean-Christophe PLAGNIOL-VILLARD }; 892439e4bfSJean-Christophe PLAGNIOL-VILLARD enum DM9000_NIC_TYPE { FASTETHER_NIC = 0, HOMERUN_NIC = 1, LONGRUN_NIC = 2 902439e4bfSJean-Christophe PLAGNIOL-VILLARD }; 912439e4bfSJean-Christophe PLAGNIOL-VILLARD 922439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Structure/enum declaration ------------------------------- */ 932439e4bfSJean-Christophe PLAGNIOL-VILLARD typedef struct board_info { 942439e4bfSJean-Christophe PLAGNIOL-VILLARD u32 runt_length_counter; /* counter: RX length < 64byte */ 952439e4bfSJean-Christophe PLAGNIOL-VILLARD u32 long_length_counter; /* counter: RX length > 1514byte */ 962439e4bfSJean-Christophe PLAGNIOL-VILLARD u32 reset_counter; /* counter: RESET */ 972439e4bfSJean-Christophe PLAGNIOL-VILLARD u32 reset_tx_timeout; /* RESET caused by TX Timeout */ 982439e4bfSJean-Christophe PLAGNIOL-VILLARD u32 reset_rx_status; /* RESET caused by RX Statsus wrong */ 992439e4bfSJean-Christophe PLAGNIOL-VILLARD u16 tx_pkt_cnt; 1002439e4bfSJean-Christophe PLAGNIOL-VILLARD u16 queue_start_addr; 1012439e4bfSJean-Christophe PLAGNIOL-VILLARD u16 dbug_cnt; 1022439e4bfSJean-Christophe PLAGNIOL-VILLARD u8 phy_addr; 1032439e4bfSJean-Christophe PLAGNIOL-VILLARD u8 device_wait_reset; /* device state */ 1042439e4bfSJean-Christophe PLAGNIOL-VILLARD u8 nic_type; /* NIC type */ 1052439e4bfSJean-Christophe PLAGNIOL-VILLARD unsigned char srom[128]; 106a101361bSRemy Bohmer void (*outblk)(void *data_ptr, int count); 107a101361bSRemy Bohmer void (*inblk)(void *data_ptr, int count); 108a101361bSRemy Bohmer void (*rx_status)(u16 *RxStatus, u16 *RxLen); 1092439e4bfSJean-Christophe PLAGNIOL-VILLARD } board_info_t; 110a101361bSRemy Bohmer static board_info_t dm9000_info; 1112439e4bfSJean-Christophe PLAGNIOL-VILLARD 1122439e4bfSJean-Christophe PLAGNIOL-VILLARD /* For module input parameter */ 1132439e4bfSJean-Christophe PLAGNIOL-VILLARD static int media_mode = DM9000_AUTO; 1142439e4bfSJean-Christophe PLAGNIOL-VILLARD static u8 nfloor = 0; 1152439e4bfSJean-Christophe PLAGNIOL-VILLARD 1162439e4bfSJean-Christophe PLAGNIOL-VILLARD /* function declaration ------------------------------------- */ 1172439e4bfSJean-Christophe PLAGNIOL-VILLARD int eth_init(bd_t * bd); 1182439e4bfSJean-Christophe PLAGNIOL-VILLARD int eth_send(volatile void *, int); 1192439e4bfSJean-Christophe PLAGNIOL-VILLARD int eth_rx(void); 1202439e4bfSJean-Christophe PLAGNIOL-VILLARD void eth_halt(void); 1212439e4bfSJean-Christophe PLAGNIOL-VILLARD static int dm9000_probe(void); 1222439e4bfSJean-Christophe PLAGNIOL-VILLARD static u16 phy_read(int); 1232439e4bfSJean-Christophe PLAGNIOL-VILLARD static void phy_write(int, u16); 1242439e4bfSJean-Christophe PLAGNIOL-VILLARD u16 read_srom_word(int); 1252439e4bfSJean-Christophe PLAGNIOL-VILLARD static u8 DM9000_ior(int); 1262439e4bfSJean-Christophe PLAGNIOL-VILLARD static void DM9000_iow(int reg, u8 value); 1272439e4bfSJean-Christophe PLAGNIOL-VILLARD 1282439e4bfSJean-Christophe PLAGNIOL-VILLARD /* DM9000 network board routine ---------------------------- */ 1292439e4bfSJean-Christophe PLAGNIOL-VILLARD 1302439e4bfSJean-Christophe PLAGNIOL-VILLARD #define DM9000_outb(d,r) ( *(volatile u8 *)r = d ) 1312439e4bfSJean-Christophe PLAGNIOL-VILLARD #define DM9000_outw(d,r) ( *(volatile u16 *)r = d ) 1322439e4bfSJean-Christophe PLAGNIOL-VILLARD #define DM9000_outl(d,r) ( *(volatile u32 *)r = d ) 1332439e4bfSJean-Christophe PLAGNIOL-VILLARD #define DM9000_inb(r) (*(volatile u8 *)r) 1342439e4bfSJean-Christophe PLAGNIOL-VILLARD #define DM9000_inw(r) (*(volatile u16 *)r) 1352439e4bfSJean-Christophe PLAGNIOL-VILLARD #define DM9000_inl(r) (*(volatile u32 *)r) 1362439e4bfSJean-Christophe PLAGNIOL-VILLARD 1372439e4bfSJean-Christophe PLAGNIOL-VILLARD #ifdef CONFIG_DM9000_DEBUG 1382439e4bfSJean-Christophe PLAGNIOL-VILLARD static void 1392439e4bfSJean-Christophe PLAGNIOL-VILLARD dump_regs(void) 1402439e4bfSJean-Christophe PLAGNIOL-VILLARD { 1412439e4bfSJean-Christophe PLAGNIOL-VILLARD DM9000_DBG("\n"); 1422439e4bfSJean-Christophe PLAGNIOL-VILLARD DM9000_DBG("NCR (0x00): %02x\n", DM9000_ior(0)); 1432439e4bfSJean-Christophe PLAGNIOL-VILLARD DM9000_DBG("NSR (0x01): %02x\n", DM9000_ior(1)); 1442439e4bfSJean-Christophe PLAGNIOL-VILLARD DM9000_DBG("TCR (0x02): %02x\n", DM9000_ior(2)); 1452439e4bfSJean-Christophe PLAGNIOL-VILLARD DM9000_DBG("TSRI (0x03): %02x\n", DM9000_ior(3)); 1462439e4bfSJean-Christophe PLAGNIOL-VILLARD DM9000_DBG("TSRII (0x04): %02x\n", DM9000_ior(4)); 1472439e4bfSJean-Christophe PLAGNIOL-VILLARD DM9000_DBG("RCR (0x05): %02x\n", DM9000_ior(5)); 1482439e4bfSJean-Christophe PLAGNIOL-VILLARD DM9000_DBG("RSR (0x06): %02x\n", DM9000_ior(6)); 149*134e2662SRemy Bohmer DM9000_DBG("ISR (0xFE): %02x\n", DM9000_ior(DM9000_ISR)); 1502439e4bfSJean-Christophe PLAGNIOL-VILLARD DM9000_DBG("\n"); 1512439e4bfSJean-Christophe PLAGNIOL-VILLARD } 152a101361bSRemy Bohmer #endif 153a101361bSRemy Bohmer 154a101361bSRemy Bohmer static void dm9000_outblk_8bit(void *data_ptr, int count) 155a101361bSRemy Bohmer { 156a101361bSRemy Bohmer int i; 157a101361bSRemy Bohmer for (i = 0; i < count; i++) 158a101361bSRemy Bohmer DM9000_outb((((u8 *) data_ptr)[i] & 0xff), DM9000_DATA); 159a101361bSRemy Bohmer } 160a101361bSRemy Bohmer 161a101361bSRemy Bohmer static void dm9000_outblk_16bit(void *data_ptr, int count) 162a101361bSRemy Bohmer { 163a101361bSRemy Bohmer int i; 164a101361bSRemy Bohmer u32 tmplen = (count + 1) / 2; 165a101361bSRemy Bohmer 166a101361bSRemy Bohmer for (i = 0; i < tmplen; i++) 167a101361bSRemy Bohmer DM9000_outw(((u16 *) data_ptr)[i], DM9000_DATA); 168a101361bSRemy Bohmer } 169a101361bSRemy Bohmer static void dm9000_outblk_32bit(void *data_ptr, int count) 170a101361bSRemy Bohmer { 171a101361bSRemy Bohmer int i; 172a101361bSRemy Bohmer u32 tmplen = (count + 3) / 4; 173a101361bSRemy Bohmer 174a101361bSRemy Bohmer for (i = 0; i < tmplen; i++) 175a101361bSRemy Bohmer DM9000_outl(((u32 *) data_ptr)[i], DM9000_DATA); 176a101361bSRemy Bohmer } 177a101361bSRemy Bohmer 178a101361bSRemy Bohmer static void dm9000_inblk_8bit(void *data_ptr, int count) 179a101361bSRemy Bohmer { 180a101361bSRemy Bohmer int i; 181a101361bSRemy Bohmer for (i = 0; i < count; i++) 182a101361bSRemy Bohmer ((u8 *) data_ptr)[i] = DM9000_inb(DM9000_DATA); 183a101361bSRemy Bohmer } 184a101361bSRemy Bohmer 185a101361bSRemy Bohmer static void dm9000_inblk_16bit(void *data_ptr, int count) 186a101361bSRemy Bohmer { 187a101361bSRemy Bohmer int i; 188a101361bSRemy Bohmer u32 tmplen = (count + 1) / 2; 189a101361bSRemy Bohmer 190a101361bSRemy Bohmer for (i = 0; i < tmplen; i++) 191a101361bSRemy Bohmer ((u16 *) data_ptr)[i] = DM9000_inw(DM9000_DATA); 192a101361bSRemy Bohmer } 193a101361bSRemy Bohmer static void dm9000_inblk_32bit(void *data_ptr, int count) 194a101361bSRemy Bohmer { 195a101361bSRemy Bohmer int i; 196a101361bSRemy Bohmer u32 tmplen = (count + 3) / 4; 197a101361bSRemy Bohmer 198a101361bSRemy Bohmer for (i = 0; i < tmplen; i++) 199a101361bSRemy Bohmer ((u32 *) data_ptr)[i] = DM9000_inl(DM9000_DATA); 200a101361bSRemy Bohmer } 201a101361bSRemy Bohmer 202a101361bSRemy Bohmer static void dm9000_rx_status_32bit(u16 *RxStatus, u16 *RxLen) 203a101361bSRemy Bohmer { 204a101361bSRemy Bohmer u32 tmpdata = DM9000_inl(DM9000_DATA); 205a101361bSRemy Bohmer 206a101361bSRemy Bohmer DM9000_outb(DM9000_MRCMD, DM9000_IO); 207a101361bSRemy Bohmer 208a101361bSRemy Bohmer *RxStatus = tmpdata; 209a101361bSRemy Bohmer *RxLen = tmpdata >> 16; 210a101361bSRemy Bohmer } 211a101361bSRemy Bohmer 212a101361bSRemy Bohmer static void dm9000_rx_status_16bit(u16 *RxStatus, u16 *RxLen) 213a101361bSRemy Bohmer { 214a101361bSRemy Bohmer DM9000_outb(DM9000_MRCMD, DM9000_IO); 215a101361bSRemy Bohmer 216a101361bSRemy Bohmer *RxStatus = DM9000_inw(DM9000_DATA); 217a101361bSRemy Bohmer *RxLen = DM9000_inw(DM9000_DATA); 218a101361bSRemy Bohmer } 219a101361bSRemy Bohmer 220a101361bSRemy Bohmer static void dm9000_rx_status_8bit(u16 *RxStatus, u16 *RxLen) 221a101361bSRemy Bohmer { 222a101361bSRemy Bohmer DM9000_outb(DM9000_MRCMD, DM9000_IO); 223a101361bSRemy Bohmer 224a101361bSRemy Bohmer *RxStatus = DM9000_inb(DM9000_DATA) + (DM9000_inb(DM9000_DATA) << 8); 225a101361bSRemy Bohmer *RxLen = DM9000_inb(DM9000_DATA) + (DM9000_inb(DM9000_DATA) << 8); 226a101361bSRemy Bohmer } 2272439e4bfSJean-Christophe PLAGNIOL-VILLARD 2282439e4bfSJean-Christophe PLAGNIOL-VILLARD /* 2292439e4bfSJean-Christophe PLAGNIOL-VILLARD Search DM9000 board, allocate space and register it 2302439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 2312439e4bfSJean-Christophe PLAGNIOL-VILLARD int 2322439e4bfSJean-Christophe PLAGNIOL-VILLARD dm9000_probe(void) 2332439e4bfSJean-Christophe PLAGNIOL-VILLARD { 2342439e4bfSJean-Christophe PLAGNIOL-VILLARD u32 id_val; 2352439e4bfSJean-Christophe PLAGNIOL-VILLARD id_val = DM9000_ior(DM9000_VIDL); 2362439e4bfSJean-Christophe PLAGNIOL-VILLARD id_val |= DM9000_ior(DM9000_VIDH) << 8; 2372439e4bfSJean-Christophe PLAGNIOL-VILLARD id_val |= DM9000_ior(DM9000_PIDL) << 16; 2382439e4bfSJean-Christophe PLAGNIOL-VILLARD id_val |= DM9000_ior(DM9000_PIDH) << 24; 2392439e4bfSJean-Christophe PLAGNIOL-VILLARD if (id_val == DM9000_ID) { 2402439e4bfSJean-Christophe PLAGNIOL-VILLARD printf("dm9000 i/o: 0x%x, id: 0x%x \n", CONFIG_DM9000_BASE, 2412439e4bfSJean-Christophe PLAGNIOL-VILLARD id_val); 2422439e4bfSJean-Christophe PLAGNIOL-VILLARD return 0; 2432439e4bfSJean-Christophe PLAGNIOL-VILLARD } else { 2442439e4bfSJean-Christophe PLAGNIOL-VILLARD printf("dm9000 not found at 0x%08x id: 0x%08x\n", 2452439e4bfSJean-Christophe PLAGNIOL-VILLARD CONFIG_DM9000_BASE, id_val); 2462439e4bfSJean-Christophe PLAGNIOL-VILLARD return -1; 2472439e4bfSJean-Christophe PLAGNIOL-VILLARD } 2482439e4bfSJean-Christophe PLAGNIOL-VILLARD } 2492439e4bfSJean-Christophe PLAGNIOL-VILLARD 2502439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Set PHY operationg mode 2512439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 2522439e4bfSJean-Christophe PLAGNIOL-VILLARD static void 2532439e4bfSJean-Christophe PLAGNIOL-VILLARD set_PHY_mode(void) 2542439e4bfSJean-Christophe PLAGNIOL-VILLARD { 2552439e4bfSJean-Christophe PLAGNIOL-VILLARD u16 phy_reg4 = 0x01e1, phy_reg0 = 0x1000; 2562439e4bfSJean-Christophe PLAGNIOL-VILLARD if (!(media_mode & DM9000_AUTO)) { 2572439e4bfSJean-Christophe PLAGNIOL-VILLARD switch (media_mode) { 2582439e4bfSJean-Christophe PLAGNIOL-VILLARD case DM9000_10MHD: 2592439e4bfSJean-Christophe PLAGNIOL-VILLARD phy_reg4 = 0x21; 2602439e4bfSJean-Christophe PLAGNIOL-VILLARD phy_reg0 = 0x0000; 2612439e4bfSJean-Christophe PLAGNIOL-VILLARD break; 2622439e4bfSJean-Christophe PLAGNIOL-VILLARD case DM9000_10MFD: 2632439e4bfSJean-Christophe PLAGNIOL-VILLARD phy_reg4 = 0x41; 2642439e4bfSJean-Christophe PLAGNIOL-VILLARD phy_reg0 = 0x1100; 2652439e4bfSJean-Christophe PLAGNIOL-VILLARD break; 2662439e4bfSJean-Christophe PLAGNIOL-VILLARD case DM9000_100MHD: 2672439e4bfSJean-Christophe PLAGNIOL-VILLARD phy_reg4 = 0x81; 2682439e4bfSJean-Christophe PLAGNIOL-VILLARD phy_reg0 = 0x2000; 2692439e4bfSJean-Christophe PLAGNIOL-VILLARD break; 2702439e4bfSJean-Christophe PLAGNIOL-VILLARD case DM9000_100MFD: 2712439e4bfSJean-Christophe PLAGNIOL-VILLARD phy_reg4 = 0x101; 2722439e4bfSJean-Christophe PLAGNIOL-VILLARD phy_reg0 = 0x3100; 2732439e4bfSJean-Christophe PLAGNIOL-VILLARD break; 2742439e4bfSJean-Christophe PLAGNIOL-VILLARD } 2752439e4bfSJean-Christophe PLAGNIOL-VILLARD phy_write(4, phy_reg4); /* Set PHY media mode */ 2762439e4bfSJean-Christophe PLAGNIOL-VILLARD phy_write(0, phy_reg0); /* Tmp */ 2772439e4bfSJean-Christophe PLAGNIOL-VILLARD } 2782439e4bfSJean-Christophe PLAGNIOL-VILLARD DM9000_iow(DM9000_GPCR, 0x01); /* Let GPIO0 output */ 2792439e4bfSJean-Christophe PLAGNIOL-VILLARD DM9000_iow(DM9000_GPR, 0x00); /* Enable PHY */ 2802439e4bfSJean-Christophe PLAGNIOL-VILLARD } 2812439e4bfSJean-Christophe PLAGNIOL-VILLARD 2822439e4bfSJean-Christophe PLAGNIOL-VILLARD /* 2832439e4bfSJean-Christophe PLAGNIOL-VILLARD Init HomeRun DM9801 2842439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 2852439e4bfSJean-Christophe PLAGNIOL-VILLARD static void 2862439e4bfSJean-Christophe PLAGNIOL-VILLARD program_dm9801(u16 HPNA_rev) 2872439e4bfSJean-Christophe PLAGNIOL-VILLARD { 2882439e4bfSJean-Christophe PLAGNIOL-VILLARD __u16 reg16, reg17, reg24, reg25; 2892439e4bfSJean-Christophe PLAGNIOL-VILLARD if (!nfloor) 2902439e4bfSJean-Christophe PLAGNIOL-VILLARD nfloor = DM9801_NOISE_FLOOR; 2912439e4bfSJean-Christophe PLAGNIOL-VILLARD reg16 = phy_read(16); 2922439e4bfSJean-Christophe PLAGNIOL-VILLARD reg17 = phy_read(17); 2932439e4bfSJean-Christophe PLAGNIOL-VILLARD reg24 = phy_read(24); 2942439e4bfSJean-Christophe PLAGNIOL-VILLARD reg25 = phy_read(25); 2952439e4bfSJean-Christophe PLAGNIOL-VILLARD switch (HPNA_rev) { 2962439e4bfSJean-Christophe PLAGNIOL-VILLARD case 0xb900: /* DM9801 E3 */ 2972439e4bfSJean-Christophe PLAGNIOL-VILLARD reg16 |= 0x1000; 2982439e4bfSJean-Christophe PLAGNIOL-VILLARD reg25 = ((reg24 + nfloor) & 0x00ff) | 0xf000; 2992439e4bfSJean-Christophe PLAGNIOL-VILLARD break; 3002439e4bfSJean-Christophe PLAGNIOL-VILLARD case 0xb901: /* DM9801 E4 */ 3012439e4bfSJean-Christophe PLAGNIOL-VILLARD reg25 = ((reg24 + nfloor) & 0x00ff) | 0xc200; 3022439e4bfSJean-Christophe PLAGNIOL-VILLARD reg17 = (reg17 & 0xfff0) + nfloor + 3; 3032439e4bfSJean-Christophe PLAGNIOL-VILLARD break; 3042439e4bfSJean-Christophe PLAGNIOL-VILLARD case 0xb902: /* DM9801 E5 */ 3052439e4bfSJean-Christophe PLAGNIOL-VILLARD case 0xb903: /* DM9801 E6 */ 3062439e4bfSJean-Christophe PLAGNIOL-VILLARD default: 3072439e4bfSJean-Christophe PLAGNIOL-VILLARD reg16 |= 0x1000; 3082439e4bfSJean-Christophe PLAGNIOL-VILLARD reg25 = ((reg24 + nfloor - 3) & 0x00ff) | 0xc200; 3092439e4bfSJean-Christophe PLAGNIOL-VILLARD reg17 = (reg17 & 0xfff0) + nfloor; 3102439e4bfSJean-Christophe PLAGNIOL-VILLARD } 3112439e4bfSJean-Christophe PLAGNIOL-VILLARD phy_write(16, reg16); 3122439e4bfSJean-Christophe PLAGNIOL-VILLARD phy_write(17, reg17); 3132439e4bfSJean-Christophe PLAGNIOL-VILLARD phy_write(25, reg25); 3142439e4bfSJean-Christophe PLAGNIOL-VILLARD } 3152439e4bfSJean-Christophe PLAGNIOL-VILLARD 3162439e4bfSJean-Christophe PLAGNIOL-VILLARD /* 3172439e4bfSJean-Christophe PLAGNIOL-VILLARD Init LongRun DM9802 3182439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 3192439e4bfSJean-Christophe PLAGNIOL-VILLARD static void 3202439e4bfSJean-Christophe PLAGNIOL-VILLARD program_dm9802(void) 3212439e4bfSJean-Christophe PLAGNIOL-VILLARD { 3222439e4bfSJean-Christophe PLAGNIOL-VILLARD __u16 reg25; 3232439e4bfSJean-Christophe PLAGNIOL-VILLARD if (!nfloor) 3242439e4bfSJean-Christophe PLAGNIOL-VILLARD nfloor = DM9802_NOISE_FLOOR; 3252439e4bfSJean-Christophe PLAGNIOL-VILLARD reg25 = phy_read(25); 3262439e4bfSJean-Christophe PLAGNIOL-VILLARD reg25 = (reg25 & 0xff00) + nfloor; 3272439e4bfSJean-Christophe PLAGNIOL-VILLARD phy_write(25, reg25); 3282439e4bfSJean-Christophe PLAGNIOL-VILLARD } 3292439e4bfSJean-Christophe PLAGNIOL-VILLARD 3302439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Identify NIC type 3312439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 3322439e4bfSJean-Christophe PLAGNIOL-VILLARD static void 3332439e4bfSJean-Christophe PLAGNIOL-VILLARD identify_nic(void) 3342439e4bfSJean-Christophe PLAGNIOL-VILLARD { 335a101361bSRemy Bohmer struct board_info *db = &dm9000_info; 3362439e4bfSJean-Christophe PLAGNIOL-VILLARD u16 phy_reg3; 3372439e4bfSJean-Christophe PLAGNIOL-VILLARD DM9000_iow(DM9000_NCR, NCR_EXT_PHY); 3382439e4bfSJean-Christophe PLAGNIOL-VILLARD phy_reg3 = phy_read(3); 3392439e4bfSJean-Christophe PLAGNIOL-VILLARD switch (phy_reg3 & 0xfff0) { 3402439e4bfSJean-Christophe PLAGNIOL-VILLARD case 0xb900: 3412439e4bfSJean-Christophe PLAGNIOL-VILLARD if (phy_read(31) == 0x4404) { 3422439e4bfSJean-Christophe PLAGNIOL-VILLARD db->nic_type = HOMERUN_NIC; 3432439e4bfSJean-Christophe PLAGNIOL-VILLARD program_dm9801(phy_reg3); 3442439e4bfSJean-Christophe PLAGNIOL-VILLARD DM9000_DBG("found homerun NIC\n"); 3452439e4bfSJean-Christophe PLAGNIOL-VILLARD } else { 3462439e4bfSJean-Christophe PLAGNIOL-VILLARD db->nic_type = LONGRUN_NIC; 3472439e4bfSJean-Christophe PLAGNIOL-VILLARD DM9000_DBG("found longrun NIC\n"); 3482439e4bfSJean-Christophe PLAGNIOL-VILLARD program_dm9802(); 3492439e4bfSJean-Christophe PLAGNIOL-VILLARD } 3502439e4bfSJean-Christophe PLAGNIOL-VILLARD break; 3512439e4bfSJean-Christophe PLAGNIOL-VILLARD default: 3522439e4bfSJean-Christophe PLAGNIOL-VILLARD db->nic_type = FASTETHER_NIC; 3532439e4bfSJean-Christophe PLAGNIOL-VILLARD break; 3542439e4bfSJean-Christophe PLAGNIOL-VILLARD } 3552439e4bfSJean-Christophe PLAGNIOL-VILLARD DM9000_iow(DM9000_NCR, 0); 3562439e4bfSJean-Christophe PLAGNIOL-VILLARD } 3572439e4bfSJean-Christophe PLAGNIOL-VILLARD 3582439e4bfSJean-Christophe PLAGNIOL-VILLARD /* General Purpose dm9000 reset routine */ 3592439e4bfSJean-Christophe PLAGNIOL-VILLARD static void 3602439e4bfSJean-Christophe PLAGNIOL-VILLARD dm9000_reset(void) 3612439e4bfSJean-Christophe PLAGNIOL-VILLARD { 3622439e4bfSJean-Christophe PLAGNIOL-VILLARD DM9000_DBG("resetting\n"); 3632439e4bfSJean-Christophe PLAGNIOL-VILLARD DM9000_iow(DM9000_NCR, NCR_RST); 3642439e4bfSJean-Christophe PLAGNIOL-VILLARD udelay(1000); /* delay 1ms */ 3652439e4bfSJean-Christophe PLAGNIOL-VILLARD } 3662439e4bfSJean-Christophe PLAGNIOL-VILLARD 3672439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Initilize dm9000 board 3682439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 3692439e4bfSJean-Christophe PLAGNIOL-VILLARD int 3702439e4bfSJean-Christophe PLAGNIOL-VILLARD eth_init(bd_t * bd) 3712439e4bfSJean-Christophe PLAGNIOL-VILLARD { 3722439e4bfSJean-Christophe PLAGNIOL-VILLARD int i, oft, lnk; 373a101361bSRemy Bohmer u8 io_mode; 374a101361bSRemy Bohmer struct board_info *db = &dm9000_info; 375a101361bSRemy Bohmer 3762439e4bfSJean-Christophe PLAGNIOL-VILLARD DM9000_DBG("eth_init()\n"); 3772439e4bfSJean-Christophe PLAGNIOL-VILLARD 3782439e4bfSJean-Christophe PLAGNIOL-VILLARD /* RESET device */ 3792439e4bfSJean-Christophe PLAGNIOL-VILLARD dm9000_reset(); 3802439e4bfSJean-Christophe PLAGNIOL-VILLARD dm9000_probe(); 3812439e4bfSJean-Christophe PLAGNIOL-VILLARD 382a101361bSRemy Bohmer /* Auto-detect 8/16/32 bit mode, ISR Bit 6+7 indicate bus width */ 383a101361bSRemy Bohmer io_mode = DM9000_ior(DM9000_ISR) >> 6; 384a101361bSRemy Bohmer 385a101361bSRemy Bohmer switch (io_mode) { 386a101361bSRemy Bohmer case 0x0: /* 16-bit mode */ 387a101361bSRemy Bohmer printf("DM9000: running in 16 bit mode\n"); 388a101361bSRemy Bohmer db->outblk = dm9000_outblk_16bit; 389a101361bSRemy Bohmer db->inblk = dm9000_inblk_16bit; 390a101361bSRemy Bohmer db->rx_status = dm9000_rx_status_16bit; 391a101361bSRemy Bohmer break; 392a101361bSRemy Bohmer case 0x01: /* 32-bit mode */ 393a101361bSRemy Bohmer printf("DM9000: running in 32 bit mode\n"); 394a101361bSRemy Bohmer db->outblk = dm9000_outblk_32bit; 395a101361bSRemy Bohmer db->inblk = dm9000_inblk_32bit; 396a101361bSRemy Bohmer db->rx_status = dm9000_rx_status_32bit; 397a101361bSRemy Bohmer break; 398a101361bSRemy Bohmer case 0x02: /* 8 bit mode */ 399a101361bSRemy Bohmer printf("DM9000: running in 8 bit mode\n"); 400a101361bSRemy Bohmer db->outblk = dm9000_outblk_8bit; 401a101361bSRemy Bohmer db->inblk = dm9000_inblk_8bit; 402a101361bSRemy Bohmer db->rx_status = dm9000_rx_status_8bit; 403a101361bSRemy Bohmer break; 404a101361bSRemy Bohmer default: 405a101361bSRemy Bohmer /* Assume 8 bit mode, will probably not work anyway */ 406a101361bSRemy Bohmer printf("DM9000: Undefined IO-mode:0x%x\n", io_mode); 407a101361bSRemy Bohmer db->outblk = dm9000_outblk_8bit; 408a101361bSRemy Bohmer db->inblk = dm9000_inblk_8bit; 409a101361bSRemy Bohmer db->rx_status = dm9000_rx_status_8bit; 410a101361bSRemy Bohmer break; 411a101361bSRemy Bohmer } 412a101361bSRemy Bohmer 4132439e4bfSJean-Christophe PLAGNIOL-VILLARD /* NIC Type: FASTETHER, HOMERUN, LONGRUN */ 4142439e4bfSJean-Christophe PLAGNIOL-VILLARD identify_nic(); 4152439e4bfSJean-Christophe PLAGNIOL-VILLARD 4162439e4bfSJean-Christophe PLAGNIOL-VILLARD /* GPIO0 on pre-activate PHY */ 4172439e4bfSJean-Christophe PLAGNIOL-VILLARD DM9000_iow(DM9000_GPR, 0x00); /*REG_1F bit0 activate phyxcer */ 4182439e4bfSJean-Christophe PLAGNIOL-VILLARD 4192439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Set PHY */ 4202439e4bfSJean-Christophe PLAGNIOL-VILLARD set_PHY_mode(); 4212439e4bfSJean-Christophe PLAGNIOL-VILLARD 4222439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Program operating register */ 4232439e4bfSJean-Christophe PLAGNIOL-VILLARD DM9000_iow(DM9000_NCR, 0x0); /* only intern phy supported by now */ 4242439e4bfSJean-Christophe PLAGNIOL-VILLARD DM9000_iow(DM9000_TCR, 0); /* TX Polling clear */ 4252439e4bfSJean-Christophe PLAGNIOL-VILLARD DM9000_iow(DM9000_BPTR, 0x3f); /* Less 3Kb, 200us */ 4262439e4bfSJean-Christophe PLAGNIOL-VILLARD DM9000_iow(DM9000_FCTR, FCTR_HWOT(3) | FCTR_LWOT(8)); /* Flow Control : High/Low Water */ 4272439e4bfSJean-Christophe PLAGNIOL-VILLARD DM9000_iow(DM9000_FCR, 0x0); /* SH FIXME: This looks strange! Flow Control */ 4282439e4bfSJean-Christophe PLAGNIOL-VILLARD DM9000_iow(DM9000_SMCR, 0); /* Special Mode */ 4292439e4bfSJean-Christophe PLAGNIOL-VILLARD DM9000_iow(DM9000_NSR, NSR_WAKEST | NSR_TX2END | NSR_TX1END); /* clear TX status */ 4302439e4bfSJean-Christophe PLAGNIOL-VILLARD DM9000_iow(DM9000_ISR, 0x0f); /* Clear interrupt status */ 4312439e4bfSJean-Christophe PLAGNIOL-VILLARD 4322439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Set Node address */ 4332439e4bfSJean-Christophe PLAGNIOL-VILLARD for (i = 0; i < 6; i++) 4342439e4bfSJean-Christophe PLAGNIOL-VILLARD ((u16 *) bd->bi_enetaddr)[i] = read_srom_word(i); 4352439e4bfSJean-Christophe PLAGNIOL-VILLARD 4362439e4bfSJean-Christophe PLAGNIOL-VILLARD if (is_zero_ether_addr(bd->bi_enetaddr) || 4372439e4bfSJean-Christophe PLAGNIOL-VILLARD is_multicast_ether_addr(bd->bi_enetaddr)) { 4382439e4bfSJean-Christophe PLAGNIOL-VILLARD /* try reading from environment */ 4392439e4bfSJean-Christophe PLAGNIOL-VILLARD u8 i; 4402439e4bfSJean-Christophe PLAGNIOL-VILLARD char *s, *e; 4412439e4bfSJean-Christophe PLAGNIOL-VILLARD s = getenv ("ethaddr"); 4422439e4bfSJean-Christophe PLAGNIOL-VILLARD for (i = 0; i < 6; ++i) { 4432439e4bfSJean-Christophe PLAGNIOL-VILLARD bd->bi_enetaddr[i] = s ? 4442439e4bfSJean-Christophe PLAGNIOL-VILLARD simple_strtoul (s, &e, 16) : 0; 4452439e4bfSJean-Christophe PLAGNIOL-VILLARD if (s) 4462439e4bfSJean-Christophe PLAGNIOL-VILLARD s = (*e) ? e + 1 : e; 4472439e4bfSJean-Christophe PLAGNIOL-VILLARD } 4482439e4bfSJean-Christophe PLAGNIOL-VILLARD } 4492439e4bfSJean-Christophe PLAGNIOL-VILLARD 4502439e4bfSJean-Christophe PLAGNIOL-VILLARD printf("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n", bd->bi_enetaddr[0], 4512439e4bfSJean-Christophe PLAGNIOL-VILLARD bd->bi_enetaddr[1], bd->bi_enetaddr[2], bd->bi_enetaddr[3], 4522439e4bfSJean-Christophe PLAGNIOL-VILLARD bd->bi_enetaddr[4], bd->bi_enetaddr[5]); 4532439e4bfSJean-Christophe PLAGNIOL-VILLARD for (i = 0, oft = 0x10; i < 6; i++, oft++) 4542439e4bfSJean-Christophe PLAGNIOL-VILLARD DM9000_iow(oft, bd->bi_enetaddr[i]); 4552439e4bfSJean-Christophe PLAGNIOL-VILLARD for (i = 0, oft = 0x16; i < 8; i++, oft++) 4562439e4bfSJean-Christophe PLAGNIOL-VILLARD DM9000_iow(oft, 0xff); 4572439e4bfSJean-Christophe PLAGNIOL-VILLARD 4582439e4bfSJean-Christophe PLAGNIOL-VILLARD /* read back mac, just to be sure */ 4592439e4bfSJean-Christophe PLAGNIOL-VILLARD for (i = 0, oft = 0x10; i < 6; i++, oft++) 4602439e4bfSJean-Christophe PLAGNIOL-VILLARD DM9000_DBG("%02x:", DM9000_ior(oft)); 4612439e4bfSJean-Christophe PLAGNIOL-VILLARD DM9000_DBG("\n"); 4622439e4bfSJean-Christophe PLAGNIOL-VILLARD 4632439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Activate DM9000 */ 4642439e4bfSJean-Christophe PLAGNIOL-VILLARD DM9000_iow(DM9000_RCR, RCR_DIS_LONG | RCR_DIS_CRC | RCR_RXEN); /* RX enable */ 4652439e4bfSJean-Christophe PLAGNIOL-VILLARD DM9000_iow(DM9000_IMR, IMR_PAR); /* Enable TX/RX interrupt mask */ 4662439e4bfSJean-Christophe PLAGNIOL-VILLARD i = 0; 4672439e4bfSJean-Christophe PLAGNIOL-VILLARD while (!(phy_read(1) & 0x20)) { /* autonegation complete bit */ 4682439e4bfSJean-Christophe PLAGNIOL-VILLARD udelay(1000); 4692439e4bfSJean-Christophe PLAGNIOL-VILLARD i++; 4702439e4bfSJean-Christophe PLAGNIOL-VILLARD if (i == 10000) { 4712439e4bfSJean-Christophe PLAGNIOL-VILLARD printf("could not establish link\n"); 4722439e4bfSJean-Christophe PLAGNIOL-VILLARD return 0; 4732439e4bfSJean-Christophe PLAGNIOL-VILLARD } 4742439e4bfSJean-Christophe PLAGNIOL-VILLARD } 4752439e4bfSJean-Christophe PLAGNIOL-VILLARD 4762439e4bfSJean-Christophe PLAGNIOL-VILLARD /* see what we've got */ 4772439e4bfSJean-Christophe PLAGNIOL-VILLARD lnk = phy_read(17) >> 12; 4782439e4bfSJean-Christophe PLAGNIOL-VILLARD printf("operating at "); 4792439e4bfSJean-Christophe PLAGNIOL-VILLARD switch (lnk) { 4802439e4bfSJean-Christophe PLAGNIOL-VILLARD case 1: 4812439e4bfSJean-Christophe PLAGNIOL-VILLARD printf("10M half duplex "); 4822439e4bfSJean-Christophe PLAGNIOL-VILLARD break; 4832439e4bfSJean-Christophe PLAGNIOL-VILLARD case 2: 4842439e4bfSJean-Christophe PLAGNIOL-VILLARD printf("10M full duplex "); 4852439e4bfSJean-Christophe PLAGNIOL-VILLARD break; 4862439e4bfSJean-Christophe PLAGNIOL-VILLARD case 4: 4872439e4bfSJean-Christophe PLAGNIOL-VILLARD printf("100M half duplex "); 4882439e4bfSJean-Christophe PLAGNIOL-VILLARD break; 4892439e4bfSJean-Christophe PLAGNIOL-VILLARD case 8: 4902439e4bfSJean-Christophe PLAGNIOL-VILLARD printf("100M full duplex "); 4912439e4bfSJean-Christophe PLAGNIOL-VILLARD break; 4922439e4bfSJean-Christophe PLAGNIOL-VILLARD default: 4932439e4bfSJean-Christophe PLAGNIOL-VILLARD printf("unknown: %d ", lnk); 4942439e4bfSJean-Christophe PLAGNIOL-VILLARD break; 4952439e4bfSJean-Christophe PLAGNIOL-VILLARD } 4962439e4bfSJean-Christophe PLAGNIOL-VILLARD printf("mode\n"); 4972439e4bfSJean-Christophe PLAGNIOL-VILLARD return 0; 4982439e4bfSJean-Christophe PLAGNIOL-VILLARD } 4992439e4bfSJean-Christophe PLAGNIOL-VILLARD 5002439e4bfSJean-Christophe PLAGNIOL-VILLARD /* 5012439e4bfSJean-Christophe PLAGNIOL-VILLARD Hardware start transmission. 5022439e4bfSJean-Christophe PLAGNIOL-VILLARD Send a packet to media from the upper layer. 5032439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 5042439e4bfSJean-Christophe PLAGNIOL-VILLARD int 5052439e4bfSJean-Christophe PLAGNIOL-VILLARD eth_send(volatile void *packet, int length) 5062439e4bfSJean-Christophe PLAGNIOL-VILLARD { 5072439e4bfSJean-Christophe PLAGNIOL-VILLARD char *data_ptr; 5082439e4bfSJean-Christophe PLAGNIOL-VILLARD u32 tmplen, i; 5092439e4bfSJean-Christophe PLAGNIOL-VILLARD int tmo; 510a101361bSRemy Bohmer struct board_info *db = &dm9000_info; 511a101361bSRemy Bohmer 512*134e2662SRemy Bohmer DM9000_DMP_PACKET("eth_send", packet, length); 5132439e4bfSJean-Christophe PLAGNIOL-VILLARD 5142439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Move data to DM9000 TX RAM */ 5152439e4bfSJean-Christophe PLAGNIOL-VILLARD data_ptr = (char *) packet; 5162439e4bfSJean-Christophe PLAGNIOL-VILLARD DM9000_outb(DM9000_MWCMD, DM9000_IO); 5172439e4bfSJean-Christophe PLAGNIOL-VILLARD 518a101361bSRemy Bohmer /* push the data to the TX-fifo */ 519a101361bSRemy Bohmer (db->outblk)(data_ptr, length); 5202439e4bfSJean-Christophe PLAGNIOL-VILLARD 5212439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Set TX length to DM9000 */ 5222439e4bfSJean-Christophe PLAGNIOL-VILLARD DM9000_iow(DM9000_TXPLL, length & 0xff); 5232439e4bfSJean-Christophe PLAGNIOL-VILLARD DM9000_iow(DM9000_TXPLH, (length >> 8) & 0xff); 5242439e4bfSJean-Christophe PLAGNIOL-VILLARD 5252439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Issue TX polling command */ 5262439e4bfSJean-Christophe PLAGNIOL-VILLARD DM9000_iow(DM9000_TCR, TCR_TXREQ); /* Cleared after TX complete */ 5272439e4bfSJean-Christophe PLAGNIOL-VILLARD 5282439e4bfSJean-Christophe PLAGNIOL-VILLARD /* wait for end of transmission */ 5292439e4bfSJean-Christophe PLAGNIOL-VILLARD tmo = get_timer(0) + 5 * CFG_HZ; 5302439e4bfSJean-Christophe PLAGNIOL-VILLARD while (DM9000_ior(DM9000_TCR) & TCR_TXREQ) { 5312439e4bfSJean-Christophe PLAGNIOL-VILLARD if (get_timer(0) >= tmo) { 5322439e4bfSJean-Christophe PLAGNIOL-VILLARD printf("transmission timeout\n"); 5332439e4bfSJean-Christophe PLAGNIOL-VILLARD break; 5342439e4bfSJean-Christophe PLAGNIOL-VILLARD } 5352439e4bfSJean-Christophe PLAGNIOL-VILLARD } 5362439e4bfSJean-Christophe PLAGNIOL-VILLARD DM9000_DBG("transmit done\n\n"); 5372439e4bfSJean-Christophe PLAGNIOL-VILLARD return 0; 5382439e4bfSJean-Christophe PLAGNIOL-VILLARD } 5392439e4bfSJean-Christophe PLAGNIOL-VILLARD 5402439e4bfSJean-Christophe PLAGNIOL-VILLARD /* 5412439e4bfSJean-Christophe PLAGNIOL-VILLARD Stop the interface. 5422439e4bfSJean-Christophe PLAGNIOL-VILLARD The interface is stopped when it is brought. 5432439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 5442439e4bfSJean-Christophe PLAGNIOL-VILLARD void 5452439e4bfSJean-Christophe PLAGNIOL-VILLARD eth_halt(void) 5462439e4bfSJean-Christophe PLAGNIOL-VILLARD { 5472439e4bfSJean-Christophe PLAGNIOL-VILLARD DM9000_DBG("eth_halt\n"); 5482439e4bfSJean-Christophe PLAGNIOL-VILLARD 5492439e4bfSJean-Christophe PLAGNIOL-VILLARD /* RESET devie */ 5502439e4bfSJean-Christophe PLAGNIOL-VILLARD phy_write(0, 0x8000); /* PHY RESET */ 5512439e4bfSJean-Christophe PLAGNIOL-VILLARD DM9000_iow(DM9000_GPR, 0x01); /* Power-Down PHY */ 5522439e4bfSJean-Christophe PLAGNIOL-VILLARD DM9000_iow(DM9000_IMR, 0x80); /* Disable all interrupt */ 5532439e4bfSJean-Christophe PLAGNIOL-VILLARD DM9000_iow(DM9000_RCR, 0x00); /* Disable RX */ 5542439e4bfSJean-Christophe PLAGNIOL-VILLARD } 5552439e4bfSJean-Christophe PLAGNIOL-VILLARD 5562439e4bfSJean-Christophe PLAGNIOL-VILLARD /* 5572439e4bfSJean-Christophe PLAGNIOL-VILLARD Received a packet and pass to upper layer 5582439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 5592439e4bfSJean-Christophe PLAGNIOL-VILLARD int 5602439e4bfSJean-Christophe PLAGNIOL-VILLARD eth_rx(void) 5612439e4bfSJean-Christophe PLAGNIOL-VILLARD { 5622439e4bfSJean-Christophe PLAGNIOL-VILLARD u8 rxbyte, *rdptr = (u8 *) NetRxPackets[0]; 5632439e4bfSJean-Christophe PLAGNIOL-VILLARD u16 RxStatus, RxLen = 0; 564a101361bSRemy Bohmer struct board_info *db = &dm9000_info; 5652439e4bfSJean-Christophe PLAGNIOL-VILLARD 5662439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Check packet ready or not */ 5672439e4bfSJean-Christophe PLAGNIOL-VILLARD DM9000_ior(DM9000_MRCMDX); /* Dummy read */ 5682439e4bfSJean-Christophe PLAGNIOL-VILLARD rxbyte = DM9000_inb(DM9000_DATA); /* Got most updated data */ 5692439e4bfSJean-Christophe PLAGNIOL-VILLARD if (rxbyte == 0) 5702439e4bfSJean-Christophe PLAGNIOL-VILLARD return 0; 5712439e4bfSJean-Christophe PLAGNIOL-VILLARD 5722439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Status check: this byte must be 0 or 1 */ 5732439e4bfSJean-Christophe PLAGNIOL-VILLARD if (rxbyte > 1) { 5742439e4bfSJean-Christophe PLAGNIOL-VILLARD DM9000_iow(DM9000_RCR, 0x00); /* Stop Device */ 5752439e4bfSJean-Christophe PLAGNIOL-VILLARD DM9000_iow(DM9000_ISR, 0x80); /* Stop INT request */ 5762439e4bfSJean-Christophe PLAGNIOL-VILLARD DM9000_DBG("rx status check: %d\n", rxbyte); 5772439e4bfSJean-Christophe PLAGNIOL-VILLARD } 5782439e4bfSJean-Christophe PLAGNIOL-VILLARD DM9000_DBG("receiving packet\n"); 5792439e4bfSJean-Christophe PLAGNIOL-VILLARD 5802439e4bfSJean-Christophe PLAGNIOL-VILLARD /* A packet ready now & Get status/length */ 5812439e4bfSJean-Christophe PLAGNIOL-VILLARD DM9000_outb(DM9000_MRCMD, DM9000_IO); 5822439e4bfSJean-Christophe PLAGNIOL-VILLARD 583a101361bSRemy Bohmer (db->rx_status)(&RxStatus, &RxLen); 5842439e4bfSJean-Christophe PLAGNIOL-VILLARD 5852439e4bfSJean-Christophe PLAGNIOL-VILLARD DM9000_DBG("rx status: 0x%04x rx len: %d\n", RxStatus, RxLen); 5862439e4bfSJean-Christophe PLAGNIOL-VILLARD 5872439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Move data from DM9000 */ 5882439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Read received packet from RX SRAM */ 589a101361bSRemy Bohmer (db->inblk)(rdptr, RxLen); 5902439e4bfSJean-Christophe PLAGNIOL-VILLARD 5912439e4bfSJean-Christophe PLAGNIOL-VILLARD if ((RxStatus & 0xbf00) || (RxLen < 0x40) 5922439e4bfSJean-Christophe PLAGNIOL-VILLARD || (RxLen > DM9000_PKT_MAX)) { 5932439e4bfSJean-Christophe PLAGNIOL-VILLARD if (RxStatus & 0x100) { 5942439e4bfSJean-Christophe PLAGNIOL-VILLARD printf("rx fifo error\n"); 5952439e4bfSJean-Christophe PLAGNIOL-VILLARD } 5962439e4bfSJean-Christophe PLAGNIOL-VILLARD if (RxStatus & 0x200) { 5972439e4bfSJean-Christophe PLAGNIOL-VILLARD printf("rx crc error\n"); 5982439e4bfSJean-Christophe PLAGNIOL-VILLARD } 5992439e4bfSJean-Christophe PLAGNIOL-VILLARD if (RxStatus & 0x8000) { 6002439e4bfSJean-Christophe PLAGNIOL-VILLARD printf("rx length error\n"); 6012439e4bfSJean-Christophe PLAGNIOL-VILLARD } 6022439e4bfSJean-Christophe PLAGNIOL-VILLARD if (RxLen > DM9000_PKT_MAX) { 6032439e4bfSJean-Christophe PLAGNIOL-VILLARD printf("rx length too big\n"); 6042439e4bfSJean-Christophe PLAGNIOL-VILLARD dm9000_reset(); 6052439e4bfSJean-Christophe PLAGNIOL-VILLARD } 6062439e4bfSJean-Christophe PLAGNIOL-VILLARD } else { 607*134e2662SRemy Bohmer DM9000_DMP_PACKET("eth_rx", rdptr, RxLen); 6082439e4bfSJean-Christophe PLAGNIOL-VILLARD 6092439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Pass to upper layer */ 6102439e4bfSJean-Christophe PLAGNIOL-VILLARD DM9000_DBG("passing packet to upper layer\n"); 6112439e4bfSJean-Christophe PLAGNIOL-VILLARD NetReceive(NetRxPackets[0], RxLen); 6122439e4bfSJean-Christophe PLAGNIOL-VILLARD return RxLen; 6132439e4bfSJean-Christophe PLAGNIOL-VILLARD } 6142439e4bfSJean-Christophe PLAGNIOL-VILLARD return 0; 6152439e4bfSJean-Christophe PLAGNIOL-VILLARD } 6162439e4bfSJean-Christophe PLAGNIOL-VILLARD 6172439e4bfSJean-Christophe PLAGNIOL-VILLARD /* 6182439e4bfSJean-Christophe PLAGNIOL-VILLARD Read a word data from SROM 6192439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 6202439e4bfSJean-Christophe PLAGNIOL-VILLARD u16 6212439e4bfSJean-Christophe PLAGNIOL-VILLARD read_srom_word(int offset) 6222439e4bfSJean-Christophe PLAGNIOL-VILLARD { 6232439e4bfSJean-Christophe PLAGNIOL-VILLARD DM9000_iow(DM9000_EPAR, offset); 6242439e4bfSJean-Christophe PLAGNIOL-VILLARD DM9000_iow(DM9000_EPCR, 0x4); 6252439e4bfSJean-Christophe PLAGNIOL-VILLARD udelay(8000); 6262439e4bfSJean-Christophe PLAGNIOL-VILLARD DM9000_iow(DM9000_EPCR, 0x0); 6272439e4bfSJean-Christophe PLAGNIOL-VILLARD return (DM9000_ior(DM9000_EPDRL) + (DM9000_ior(DM9000_EPDRH) << 8)); 6282439e4bfSJean-Christophe PLAGNIOL-VILLARD } 6292439e4bfSJean-Christophe PLAGNIOL-VILLARD 6302439e4bfSJean-Christophe PLAGNIOL-VILLARD void 6312439e4bfSJean-Christophe PLAGNIOL-VILLARD write_srom_word(int offset, u16 val) 6322439e4bfSJean-Christophe PLAGNIOL-VILLARD { 6332439e4bfSJean-Christophe PLAGNIOL-VILLARD DM9000_iow(DM9000_EPAR, offset); 6342439e4bfSJean-Christophe PLAGNIOL-VILLARD DM9000_iow(DM9000_EPDRH, ((val >> 8) & 0xff)); 6352439e4bfSJean-Christophe PLAGNIOL-VILLARD DM9000_iow(DM9000_EPDRL, (val & 0xff)); 6362439e4bfSJean-Christophe PLAGNIOL-VILLARD DM9000_iow(DM9000_EPCR, 0x12); 6372439e4bfSJean-Christophe PLAGNIOL-VILLARD udelay(8000); 6382439e4bfSJean-Christophe PLAGNIOL-VILLARD DM9000_iow(DM9000_EPCR, 0); 6392439e4bfSJean-Christophe PLAGNIOL-VILLARD } 6402439e4bfSJean-Christophe PLAGNIOL-VILLARD 6412439e4bfSJean-Christophe PLAGNIOL-VILLARD 6422439e4bfSJean-Christophe PLAGNIOL-VILLARD /* 6432439e4bfSJean-Christophe PLAGNIOL-VILLARD Read a byte from I/O port 6442439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 6452439e4bfSJean-Christophe PLAGNIOL-VILLARD static u8 6462439e4bfSJean-Christophe PLAGNIOL-VILLARD DM9000_ior(int reg) 6472439e4bfSJean-Christophe PLAGNIOL-VILLARD { 6482439e4bfSJean-Christophe PLAGNIOL-VILLARD DM9000_outb(reg, DM9000_IO); 6492439e4bfSJean-Christophe PLAGNIOL-VILLARD return DM9000_inb(DM9000_DATA); 6502439e4bfSJean-Christophe PLAGNIOL-VILLARD } 6512439e4bfSJean-Christophe PLAGNIOL-VILLARD 6522439e4bfSJean-Christophe PLAGNIOL-VILLARD /* 6532439e4bfSJean-Christophe PLAGNIOL-VILLARD Write a byte to I/O port 6542439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 6552439e4bfSJean-Christophe PLAGNIOL-VILLARD static void 6562439e4bfSJean-Christophe PLAGNIOL-VILLARD DM9000_iow(int reg, u8 value) 6572439e4bfSJean-Christophe PLAGNIOL-VILLARD { 6582439e4bfSJean-Christophe PLAGNIOL-VILLARD DM9000_outb(reg, DM9000_IO); 6592439e4bfSJean-Christophe PLAGNIOL-VILLARD DM9000_outb(value, DM9000_DATA); 6602439e4bfSJean-Christophe PLAGNIOL-VILLARD } 6612439e4bfSJean-Christophe PLAGNIOL-VILLARD 6622439e4bfSJean-Christophe PLAGNIOL-VILLARD /* 6632439e4bfSJean-Christophe PLAGNIOL-VILLARD Read a word from phyxcer 6642439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 6652439e4bfSJean-Christophe PLAGNIOL-VILLARD static u16 6662439e4bfSJean-Christophe PLAGNIOL-VILLARD phy_read(int reg) 6672439e4bfSJean-Christophe PLAGNIOL-VILLARD { 6682439e4bfSJean-Christophe PLAGNIOL-VILLARD u16 val; 6692439e4bfSJean-Christophe PLAGNIOL-VILLARD 6702439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Fill the phyxcer register into REG_0C */ 6712439e4bfSJean-Christophe PLAGNIOL-VILLARD DM9000_iow(DM9000_EPAR, DM9000_PHY | reg); 6722439e4bfSJean-Christophe PLAGNIOL-VILLARD DM9000_iow(DM9000_EPCR, 0xc); /* Issue phyxcer read command */ 6732439e4bfSJean-Christophe PLAGNIOL-VILLARD udelay(100); /* Wait read complete */ 6742439e4bfSJean-Christophe PLAGNIOL-VILLARD DM9000_iow(DM9000_EPCR, 0x0); /* Clear phyxcer read command */ 6752439e4bfSJean-Christophe PLAGNIOL-VILLARD val = (DM9000_ior(DM9000_EPDRH) << 8) | DM9000_ior(DM9000_EPDRL); 6762439e4bfSJean-Christophe PLAGNIOL-VILLARD 6772439e4bfSJean-Christophe PLAGNIOL-VILLARD /* The read data keeps on REG_0D & REG_0E */ 678*134e2662SRemy Bohmer DM9000_DBG("phy_read(0x%x): 0x%x\n", reg, val); 6792439e4bfSJean-Christophe PLAGNIOL-VILLARD return val; 6802439e4bfSJean-Christophe PLAGNIOL-VILLARD } 6812439e4bfSJean-Christophe PLAGNIOL-VILLARD 6822439e4bfSJean-Christophe PLAGNIOL-VILLARD /* 6832439e4bfSJean-Christophe PLAGNIOL-VILLARD Write a word to phyxcer 6842439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 6852439e4bfSJean-Christophe PLAGNIOL-VILLARD static void 6862439e4bfSJean-Christophe PLAGNIOL-VILLARD phy_write(int reg, u16 value) 6872439e4bfSJean-Christophe PLAGNIOL-VILLARD { 6882439e4bfSJean-Christophe PLAGNIOL-VILLARD 6892439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Fill the phyxcer register into REG_0C */ 6902439e4bfSJean-Christophe PLAGNIOL-VILLARD DM9000_iow(DM9000_EPAR, DM9000_PHY | reg); 6912439e4bfSJean-Christophe PLAGNIOL-VILLARD 6922439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Fill the written data into REG_0D & REG_0E */ 6932439e4bfSJean-Christophe PLAGNIOL-VILLARD DM9000_iow(DM9000_EPDRL, (value & 0xff)); 6942439e4bfSJean-Christophe PLAGNIOL-VILLARD DM9000_iow(DM9000_EPDRH, ((value >> 8) & 0xff)); 6952439e4bfSJean-Christophe PLAGNIOL-VILLARD DM9000_iow(DM9000_EPCR, 0xa); /* Issue phyxcer write command */ 6962439e4bfSJean-Christophe PLAGNIOL-VILLARD udelay(500); /* Wait write complete */ 6972439e4bfSJean-Christophe PLAGNIOL-VILLARD DM9000_iow(DM9000_EPCR, 0x0); /* Clear phyxcer write command */ 698*134e2662SRemy Bohmer DM9000_DBG("phy_write(reg:0x%x, value:0x%x)\n", reg, value); 6992439e4bfSJean-Christophe PLAGNIOL-VILLARD } 7002439e4bfSJean-Christophe PLAGNIOL-VILLARD #endif /* CONFIG_DRIVER_DM9000 */ 701