1 /* 2 * (C) Copyright 2010 3 * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #ifndef _DW_ETH_H 9 #define _DW_ETH_H 10 11 #define CONFIG_TX_DESCR_NUM 16 12 #define CONFIG_RX_DESCR_NUM 16 13 #define CONFIG_ETH_BUFSIZE 2048 14 #define TX_TOTAL_BUFSIZE (CONFIG_ETH_BUFSIZE * CONFIG_TX_DESCR_NUM) 15 #define RX_TOTAL_BUFSIZE (CONFIG_ETH_BUFSIZE * CONFIG_RX_DESCR_NUM) 16 17 #define CONFIG_MACRESET_TIMEOUT (3 * CONFIG_SYS_HZ) 18 #define CONFIG_MDIO_TIMEOUT (3 * CONFIG_SYS_HZ) 19 20 struct eth_mac_regs { 21 u32 conf; /* 0x00 */ 22 u32 framefilt; /* 0x04 */ 23 u32 hashtablehigh; /* 0x08 */ 24 u32 hashtablelow; /* 0x0c */ 25 u32 miiaddr; /* 0x10 */ 26 u32 miidata; /* 0x14 */ 27 u32 flowcontrol; /* 0x18 */ 28 u32 vlantag; /* 0x1c */ 29 u32 version; /* 0x20 */ 30 u8 reserved_1[20]; 31 u32 intreg; /* 0x38 */ 32 u32 intmask; /* 0x3c */ 33 u32 macaddr0hi; /* 0x40 */ 34 u32 macaddr0lo; /* 0x44 */ 35 }; 36 37 /* MAC configuration register definitions */ 38 #define FRAMEBURSTENABLE (1 << 21) 39 #define MII_PORTSELECT (1 << 15) 40 #define FES_100 (1 << 14) 41 #define DISABLERXOWN (1 << 13) 42 #define FULLDPLXMODE (1 << 11) 43 #define RXENABLE (1 << 2) 44 #define TXENABLE (1 << 3) 45 46 /* MII address register definitions */ 47 #define MII_BUSY (1 << 0) 48 #define MII_WRITE (1 << 1) 49 #define MII_CLKRANGE_60_100M (0) 50 #define MII_CLKRANGE_100_150M (0x4) 51 #define MII_CLKRANGE_20_35M (0x8) 52 #define MII_CLKRANGE_35_60M (0xC) 53 #define MII_CLKRANGE_150_250M (0x10) 54 #define MII_CLKRANGE_250_300M (0x14) 55 56 #define MIIADDRSHIFT (11) 57 #define MIIREGSHIFT (6) 58 #define MII_REGMSK (0x1F << 6) 59 #define MII_ADDRMSK (0x1F << 11) 60 61 62 struct eth_dma_regs { 63 u32 busmode; /* 0x00 */ 64 u32 txpolldemand; /* 0x04 */ 65 u32 rxpolldemand; /* 0x08 */ 66 u32 rxdesclistaddr; /* 0x0c */ 67 u32 txdesclistaddr; /* 0x10 */ 68 u32 status; /* 0x14 */ 69 u32 opmode; /* 0x18 */ 70 u32 intenable; /* 0x1c */ 71 u8 reserved[40]; 72 u32 currhosttxdesc; /* 0x48 */ 73 u32 currhostrxdesc; /* 0x4c */ 74 u32 currhosttxbuffaddr; /* 0x50 */ 75 u32 currhostrxbuffaddr; /* 0x54 */ 76 }; 77 78 #define DW_DMA_BASE_OFFSET (0x1000) 79 80 /* Default DMA Burst length */ 81 #ifndef CONFIG_DW_GMAC_DEFAULT_DMA_PBL 82 #define CONFIG_DW_GMAC_DEFAULT_DMA_PBL 8 83 #endif 84 85 /* Bus mode register definitions */ 86 #define FIXEDBURST (1 << 16) 87 #define PRIORXTX_41 (3 << 14) 88 #define PRIORXTX_31 (2 << 14) 89 #define PRIORXTX_21 (1 << 14) 90 #define PRIORXTX_11 (0 << 14) 91 #define DMA_PBL (CONFIG_DW_GMAC_DEFAULT_DMA_PBL<<8) 92 #define RXHIGHPRIO (1 << 1) 93 #define DMAMAC_SRST (1 << 0) 94 95 /* Poll demand definitions */ 96 #define POLL_DATA (0xFFFFFFFF) 97 98 /* Operation mode definitions */ 99 #define STOREFORWARD (1 << 21) 100 #define FLUSHTXFIFO (1 << 20) 101 #define TXSTART (1 << 13) 102 #define TXSECONDFRAME (1 << 2) 103 #define RXSTART (1 << 1) 104 105 /* Descriptior related definitions */ 106 #define MAC_MAX_FRAME_SZ (1600) 107 108 struct dmamacdescr { 109 u32 txrx_status; 110 u32 dmamac_cntl; 111 void *dmamac_addr; 112 struct dmamacdescr *dmamac_next; 113 } __aligned(ARCH_DMA_MINALIGN); 114 115 /* 116 * txrx_status definitions 117 */ 118 119 /* tx status bits definitions */ 120 #if defined(CONFIG_DW_ALTDESCRIPTOR) 121 122 #define DESC_TXSTS_OWNBYDMA (1 << 31) 123 #define DESC_TXSTS_TXINT (1 << 30) 124 #define DESC_TXSTS_TXLAST (1 << 29) 125 #define DESC_TXSTS_TXFIRST (1 << 28) 126 #define DESC_TXSTS_TXCRCDIS (1 << 27) 127 128 #define DESC_TXSTS_TXPADDIS (1 << 26) 129 #define DESC_TXSTS_TXCHECKINSCTRL (3 << 22) 130 #define DESC_TXSTS_TXRINGEND (1 << 21) 131 #define DESC_TXSTS_TXCHAIN (1 << 20) 132 #define DESC_TXSTS_MSK (0x1FFFF << 0) 133 134 #else 135 136 #define DESC_TXSTS_OWNBYDMA (1 << 31) 137 #define DESC_TXSTS_MSK (0x1FFFF << 0) 138 139 #endif 140 141 /* rx status bits definitions */ 142 #define DESC_RXSTS_OWNBYDMA (1 << 31) 143 #define DESC_RXSTS_DAFILTERFAIL (1 << 30) 144 #define DESC_RXSTS_FRMLENMSK (0x3FFF << 16) 145 #define DESC_RXSTS_FRMLENSHFT (16) 146 147 #define DESC_RXSTS_ERROR (1 << 15) 148 #define DESC_RXSTS_RXTRUNCATED (1 << 14) 149 #define DESC_RXSTS_SAFILTERFAIL (1 << 13) 150 #define DESC_RXSTS_RXIPC_GIANTFRAME (1 << 12) 151 #define DESC_RXSTS_RXDAMAGED (1 << 11) 152 #define DESC_RXSTS_RXVLANTAG (1 << 10) 153 #define DESC_RXSTS_RXFIRST (1 << 9) 154 #define DESC_RXSTS_RXLAST (1 << 8) 155 #define DESC_RXSTS_RXIPC_GIANT (1 << 7) 156 #define DESC_RXSTS_RXCOLLISION (1 << 6) 157 #define DESC_RXSTS_RXFRAMEETHER (1 << 5) 158 #define DESC_RXSTS_RXWATCHDOG (1 << 4) 159 #define DESC_RXSTS_RXMIIERROR (1 << 3) 160 #define DESC_RXSTS_RXDRIBBLING (1 << 2) 161 #define DESC_RXSTS_RXCRC (1 << 1) 162 163 /* 164 * dmamac_cntl definitions 165 */ 166 167 /* tx control bits definitions */ 168 #if defined(CONFIG_DW_ALTDESCRIPTOR) 169 170 #define DESC_TXCTRL_SIZE1MASK (0x1FFF << 0) 171 #define DESC_TXCTRL_SIZE1SHFT (0) 172 #define DESC_TXCTRL_SIZE2MASK (0x1FFF << 16) 173 #define DESC_TXCTRL_SIZE2SHFT (16) 174 175 #else 176 177 #define DESC_TXCTRL_TXINT (1 << 31) 178 #define DESC_TXCTRL_TXLAST (1 << 30) 179 #define DESC_TXCTRL_TXFIRST (1 << 29) 180 #define DESC_TXCTRL_TXCHECKINSCTRL (3 << 27) 181 #define DESC_TXCTRL_TXCRCDIS (1 << 26) 182 #define DESC_TXCTRL_TXRINGEND (1 << 25) 183 #define DESC_TXCTRL_TXCHAIN (1 << 24) 184 185 #define DESC_TXCTRL_SIZE1MASK (0x7FF << 0) 186 #define DESC_TXCTRL_SIZE1SHFT (0) 187 #define DESC_TXCTRL_SIZE2MASK (0x7FF << 11) 188 #define DESC_TXCTRL_SIZE2SHFT (11) 189 190 #endif 191 192 /* rx control bits definitions */ 193 #if defined(CONFIG_DW_ALTDESCRIPTOR) 194 195 #define DESC_RXCTRL_RXINTDIS (1 << 31) 196 #define DESC_RXCTRL_RXRINGEND (1 << 15) 197 #define DESC_RXCTRL_RXCHAIN (1 << 14) 198 199 #define DESC_RXCTRL_SIZE1MASK (0x1FFF << 0) 200 #define DESC_RXCTRL_SIZE1SHFT (0) 201 #define DESC_RXCTRL_SIZE2MASK (0x1FFF << 16) 202 #define DESC_RXCTRL_SIZE2SHFT (16) 203 204 #else 205 206 #define DESC_RXCTRL_RXINTDIS (1 << 31) 207 #define DESC_RXCTRL_RXRINGEND (1 << 25) 208 #define DESC_RXCTRL_RXCHAIN (1 << 24) 209 210 #define DESC_RXCTRL_SIZE1MASK (0x7FF << 0) 211 #define DESC_RXCTRL_SIZE1SHFT (0) 212 #define DESC_RXCTRL_SIZE2MASK (0x7FF << 11) 213 #define DESC_RXCTRL_SIZE2SHFT (11) 214 215 #endif 216 217 struct dw_eth_dev { 218 struct dmamacdescr tx_mac_descrtable[CONFIG_TX_DESCR_NUM]; 219 struct dmamacdescr rx_mac_descrtable[CONFIG_RX_DESCR_NUM]; 220 char txbuffs[TX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN); 221 char rxbuffs[RX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN); 222 223 u32 interface; 224 u32 tx_currdescnum; 225 u32 rx_currdescnum; 226 227 struct eth_mac_regs *mac_regs_p; 228 struct eth_dma_regs *dma_regs_p; 229 230 struct eth_device *dev; 231 struct phy_device *phydev; 232 struct mii_dev *bus; 233 }; 234 235 #endif 236