1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 25b1b1883SVipin KUMAR /* 35b1b1883SVipin KUMAR * (C) Copyright 2010 45b1b1883SVipin KUMAR * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. 55b1b1883SVipin KUMAR */ 65b1b1883SVipin KUMAR 75b1b1883SVipin KUMAR #ifndef _DW_ETH_H 85b1b1883SVipin KUMAR #define _DW_ETH_H 95b1b1883SVipin KUMAR 1066d027e2SAlexey Brodkin #ifdef CONFIG_DM_GPIO 1166d027e2SAlexey Brodkin #include <asm-generic/gpio.h> 1266d027e2SAlexey Brodkin #endif 1390b7fc92SSjoerd Simons 145b1b1883SVipin KUMAR #define CONFIG_TX_DESCR_NUM 16 155b1b1883SVipin KUMAR #define CONFIG_RX_DESCR_NUM 16 165b1b1883SVipin KUMAR #define CONFIG_ETH_BUFSIZE 2048 175b1b1883SVipin KUMAR #define TX_TOTAL_BUFSIZE (CONFIG_ETH_BUFSIZE * CONFIG_TX_DESCR_NUM) 185b1b1883SVipin KUMAR #define RX_TOTAL_BUFSIZE (CONFIG_ETH_BUFSIZE * CONFIG_RX_DESCR_NUM) 195b1b1883SVipin KUMAR 205b1b1883SVipin KUMAR #define CONFIG_MACRESET_TIMEOUT (3 * CONFIG_SYS_HZ) 215b1b1883SVipin KUMAR #define CONFIG_MDIO_TIMEOUT (3 * CONFIG_SYS_HZ) 225b1b1883SVipin KUMAR 235b1b1883SVipin KUMAR struct eth_mac_regs { 245b1b1883SVipin KUMAR u32 conf; /* 0x00 */ 255b1b1883SVipin KUMAR u32 framefilt; /* 0x04 */ 265b1b1883SVipin KUMAR u32 hashtablehigh; /* 0x08 */ 275b1b1883SVipin KUMAR u32 hashtablelow; /* 0x0c */ 285b1b1883SVipin KUMAR u32 miiaddr; /* 0x10 */ 295b1b1883SVipin KUMAR u32 miidata; /* 0x14 */ 305b1b1883SVipin KUMAR u32 flowcontrol; /* 0x18 */ 315b1b1883SVipin KUMAR u32 vlantag; /* 0x1c */ 325b1b1883SVipin KUMAR u32 version; /* 0x20 */ 335b1b1883SVipin KUMAR u8 reserved_1[20]; 345b1b1883SVipin KUMAR u32 intreg; /* 0x38 */ 355b1b1883SVipin KUMAR u32 intmask; /* 0x3c */ 365b1b1883SVipin KUMAR u32 macaddr0hi; /* 0x40 */ 375b1b1883SVipin KUMAR u32 macaddr0lo; /* 0x44 */ 385b1b1883SVipin KUMAR }; 395b1b1883SVipin KUMAR 405b1b1883SVipin KUMAR /* MAC configuration register definitions */ 415b1b1883SVipin KUMAR #define FRAMEBURSTENABLE (1 << 21) 425b1b1883SVipin KUMAR #define MII_PORTSELECT (1 << 15) 435b1b1883SVipin KUMAR #define FES_100 (1 << 14) 445b1b1883SVipin KUMAR #define DISABLERXOWN (1 << 13) 455b1b1883SVipin KUMAR #define FULLDPLXMODE (1 << 11) 465b1b1883SVipin KUMAR #define RXENABLE (1 << 2) 475b1b1883SVipin KUMAR #define TXENABLE (1 << 3) 485b1b1883SVipin KUMAR 495b1b1883SVipin KUMAR /* MII address register definitions */ 505b1b1883SVipin KUMAR #define MII_BUSY (1 << 0) 515b1b1883SVipin KUMAR #define MII_WRITE (1 << 1) 525b1b1883SVipin KUMAR #define MII_CLKRANGE_60_100M (0) 535b1b1883SVipin KUMAR #define MII_CLKRANGE_100_150M (0x4) 545b1b1883SVipin KUMAR #define MII_CLKRANGE_20_35M (0x8) 555b1b1883SVipin KUMAR #define MII_CLKRANGE_35_60M (0xC) 565b1b1883SVipin KUMAR #define MII_CLKRANGE_150_250M (0x10) 575b1b1883SVipin KUMAR #define MII_CLKRANGE_250_300M (0x14) 585b1b1883SVipin KUMAR 595b1b1883SVipin KUMAR #define MIIADDRSHIFT (11) 605b1b1883SVipin KUMAR #define MIIREGSHIFT (6) 615b1b1883SVipin KUMAR #define MII_REGMSK (0x1F << 6) 625b1b1883SVipin KUMAR #define MII_ADDRMSK (0x1F << 11) 635b1b1883SVipin KUMAR 645b1b1883SVipin KUMAR 655b1b1883SVipin KUMAR struct eth_dma_regs { 665b1b1883SVipin KUMAR u32 busmode; /* 0x00 */ 675b1b1883SVipin KUMAR u32 txpolldemand; /* 0x04 */ 685b1b1883SVipin KUMAR u32 rxpolldemand; /* 0x08 */ 695b1b1883SVipin KUMAR u32 rxdesclistaddr; /* 0x0c */ 705b1b1883SVipin KUMAR u32 txdesclistaddr; /* 0x10 */ 715b1b1883SVipin KUMAR u32 status; /* 0x14 */ 725b1b1883SVipin KUMAR u32 opmode; /* 0x18 */ 735b1b1883SVipin KUMAR u32 intenable; /* 0x1c */ 742ddaf13bSSonic Zhang u32 reserved1[2]; 752ddaf13bSSonic Zhang u32 axibus; /* 0x28 */ 762ddaf13bSSonic Zhang u32 reserved2[7]; 775b1b1883SVipin KUMAR u32 currhosttxdesc; /* 0x48 */ 785b1b1883SVipin KUMAR u32 currhostrxdesc; /* 0x4c */ 795b1b1883SVipin KUMAR u32 currhosttxbuffaddr; /* 0x50 */ 805b1b1883SVipin KUMAR u32 currhostrxbuffaddr; /* 0x54 */ 815b1b1883SVipin KUMAR }; 825b1b1883SVipin KUMAR 835b1b1883SVipin KUMAR #define DW_DMA_BASE_OFFSET (0x1000) 845b1b1883SVipin KUMAR 8549692c5fSIan Campbell /* Default DMA Burst length */ 8649692c5fSIan Campbell #ifndef CONFIG_DW_GMAC_DEFAULT_DMA_PBL 8749692c5fSIan Campbell #define CONFIG_DW_GMAC_DEFAULT_DMA_PBL 8 8849692c5fSIan Campbell #endif 8949692c5fSIan Campbell 905b1b1883SVipin KUMAR /* Bus mode register definitions */ 915b1b1883SVipin KUMAR #define FIXEDBURST (1 << 16) 925b1b1883SVipin KUMAR #define PRIORXTX_41 (3 << 14) 935b1b1883SVipin KUMAR #define PRIORXTX_31 (2 << 14) 945b1b1883SVipin KUMAR #define PRIORXTX_21 (1 << 14) 955b1b1883SVipin KUMAR #define PRIORXTX_11 (0 << 14) 9649692c5fSIan Campbell #define DMA_PBL (CONFIG_DW_GMAC_DEFAULT_DMA_PBL<<8) 975b1b1883SVipin KUMAR #define RXHIGHPRIO (1 << 1) 985b1b1883SVipin KUMAR #define DMAMAC_SRST (1 << 0) 995b1b1883SVipin KUMAR 1005b1b1883SVipin KUMAR /* Poll demand definitions */ 1015b1b1883SVipin KUMAR #define POLL_DATA (0xFFFFFFFF) 1025b1b1883SVipin KUMAR 1035b1b1883SVipin KUMAR /* Operation mode definitions */ 1045b1b1883SVipin KUMAR #define STOREFORWARD (1 << 21) 1055b1b1883SVipin KUMAR #define FLUSHTXFIFO (1 << 20) 1065b1b1883SVipin KUMAR #define TXSTART (1 << 13) 1075b1b1883SVipin KUMAR #define TXSECONDFRAME (1 << 2) 1085b1b1883SVipin KUMAR #define RXSTART (1 << 1) 1095b1b1883SVipin KUMAR 1105b1b1883SVipin KUMAR /* Descriptior related definitions */ 11197a6caa6SVipin KUMAR #define MAC_MAX_FRAME_SZ (1600) 1125b1b1883SVipin KUMAR 1135b1b1883SVipin KUMAR struct dmamacdescr { 1145b1b1883SVipin KUMAR u32 txrx_status; 1155b1b1883SVipin KUMAR u32 dmamac_cntl; 1160e1a3e30SBeniamino Galvani u32 dmamac_addr; 1170e1a3e30SBeniamino Galvani u32 dmamac_next; 118a7b26dbbSAlexey Brodkin } __aligned(ARCH_DMA_MINALIGN); 1195b1b1883SVipin KUMAR 1205b1b1883SVipin KUMAR /* 1215b1b1883SVipin KUMAR * txrx_status definitions 1225b1b1883SVipin KUMAR */ 1235b1b1883SVipin KUMAR 1245b1b1883SVipin KUMAR /* tx status bits definitions */ 1255b1b1883SVipin KUMAR #if defined(CONFIG_DW_ALTDESCRIPTOR) 1265b1b1883SVipin KUMAR 1275b1b1883SVipin KUMAR #define DESC_TXSTS_OWNBYDMA (1 << 31) 1285b1b1883SVipin KUMAR #define DESC_TXSTS_TXINT (1 << 30) 1295b1b1883SVipin KUMAR #define DESC_TXSTS_TXLAST (1 << 29) 1305b1b1883SVipin KUMAR #define DESC_TXSTS_TXFIRST (1 << 28) 1315b1b1883SVipin KUMAR #define DESC_TXSTS_TXCRCDIS (1 << 27) 1325b1b1883SVipin KUMAR 1335b1b1883SVipin KUMAR #define DESC_TXSTS_TXPADDIS (1 << 26) 1345b1b1883SVipin KUMAR #define DESC_TXSTS_TXCHECKINSCTRL (3 << 22) 1355b1b1883SVipin KUMAR #define DESC_TXSTS_TXRINGEND (1 << 21) 1365b1b1883SVipin KUMAR #define DESC_TXSTS_TXCHAIN (1 << 20) 1375b1b1883SVipin KUMAR #define DESC_TXSTS_MSK (0x1FFFF << 0) 1385b1b1883SVipin KUMAR 1395b1b1883SVipin KUMAR #else 1405b1b1883SVipin KUMAR 1415b1b1883SVipin KUMAR #define DESC_TXSTS_OWNBYDMA (1 << 31) 1425b1b1883SVipin KUMAR #define DESC_TXSTS_MSK (0x1FFFF << 0) 1435b1b1883SVipin KUMAR 1445b1b1883SVipin KUMAR #endif 1455b1b1883SVipin KUMAR 1465b1b1883SVipin KUMAR /* rx status bits definitions */ 1475b1b1883SVipin KUMAR #define DESC_RXSTS_OWNBYDMA (1 << 31) 1485b1b1883SVipin KUMAR #define DESC_RXSTS_DAFILTERFAIL (1 << 30) 1495b1b1883SVipin KUMAR #define DESC_RXSTS_FRMLENMSK (0x3FFF << 16) 1505b1b1883SVipin KUMAR #define DESC_RXSTS_FRMLENSHFT (16) 1515b1b1883SVipin KUMAR 1525b1b1883SVipin KUMAR #define DESC_RXSTS_ERROR (1 << 15) 1535b1b1883SVipin KUMAR #define DESC_RXSTS_RXTRUNCATED (1 << 14) 1545b1b1883SVipin KUMAR #define DESC_RXSTS_SAFILTERFAIL (1 << 13) 1555b1b1883SVipin KUMAR #define DESC_RXSTS_RXIPC_GIANTFRAME (1 << 12) 1565b1b1883SVipin KUMAR #define DESC_RXSTS_RXDAMAGED (1 << 11) 1575b1b1883SVipin KUMAR #define DESC_RXSTS_RXVLANTAG (1 << 10) 1585b1b1883SVipin KUMAR #define DESC_RXSTS_RXFIRST (1 << 9) 1595b1b1883SVipin KUMAR #define DESC_RXSTS_RXLAST (1 << 8) 1605b1b1883SVipin KUMAR #define DESC_RXSTS_RXIPC_GIANT (1 << 7) 1615b1b1883SVipin KUMAR #define DESC_RXSTS_RXCOLLISION (1 << 6) 1625b1b1883SVipin KUMAR #define DESC_RXSTS_RXFRAMEETHER (1 << 5) 1635b1b1883SVipin KUMAR #define DESC_RXSTS_RXWATCHDOG (1 << 4) 1645b1b1883SVipin KUMAR #define DESC_RXSTS_RXMIIERROR (1 << 3) 1655b1b1883SVipin KUMAR #define DESC_RXSTS_RXDRIBBLING (1 << 2) 1665b1b1883SVipin KUMAR #define DESC_RXSTS_RXCRC (1 << 1) 1675b1b1883SVipin KUMAR 1685b1b1883SVipin KUMAR /* 1695b1b1883SVipin KUMAR * dmamac_cntl definitions 1705b1b1883SVipin KUMAR */ 1715b1b1883SVipin KUMAR 1725b1b1883SVipin KUMAR /* tx control bits definitions */ 1735b1b1883SVipin KUMAR #if defined(CONFIG_DW_ALTDESCRIPTOR) 1745b1b1883SVipin KUMAR 1755b1b1883SVipin KUMAR #define DESC_TXCTRL_SIZE1MASK (0x1FFF << 0) 1765b1b1883SVipin KUMAR #define DESC_TXCTRL_SIZE1SHFT (0) 1775b1b1883SVipin KUMAR #define DESC_TXCTRL_SIZE2MASK (0x1FFF << 16) 1785b1b1883SVipin KUMAR #define DESC_TXCTRL_SIZE2SHFT (16) 1795b1b1883SVipin KUMAR 1805b1b1883SVipin KUMAR #else 1815b1b1883SVipin KUMAR 1825b1b1883SVipin KUMAR #define DESC_TXCTRL_TXINT (1 << 31) 1835b1b1883SVipin KUMAR #define DESC_TXCTRL_TXLAST (1 << 30) 1845b1b1883SVipin KUMAR #define DESC_TXCTRL_TXFIRST (1 << 29) 1855b1b1883SVipin KUMAR #define DESC_TXCTRL_TXCHECKINSCTRL (3 << 27) 1865b1b1883SVipin KUMAR #define DESC_TXCTRL_TXCRCDIS (1 << 26) 1875b1b1883SVipin KUMAR #define DESC_TXCTRL_TXRINGEND (1 << 25) 1885b1b1883SVipin KUMAR #define DESC_TXCTRL_TXCHAIN (1 << 24) 1895b1b1883SVipin KUMAR 1905b1b1883SVipin KUMAR #define DESC_TXCTRL_SIZE1MASK (0x7FF << 0) 1915b1b1883SVipin KUMAR #define DESC_TXCTRL_SIZE1SHFT (0) 1925b1b1883SVipin KUMAR #define DESC_TXCTRL_SIZE2MASK (0x7FF << 11) 1935b1b1883SVipin KUMAR #define DESC_TXCTRL_SIZE2SHFT (11) 1945b1b1883SVipin KUMAR 1955b1b1883SVipin KUMAR #endif 1965b1b1883SVipin KUMAR 1975b1b1883SVipin KUMAR /* rx control bits definitions */ 1985b1b1883SVipin KUMAR #if defined(CONFIG_DW_ALTDESCRIPTOR) 1995b1b1883SVipin KUMAR 2005b1b1883SVipin KUMAR #define DESC_RXCTRL_RXINTDIS (1 << 31) 2015b1b1883SVipin KUMAR #define DESC_RXCTRL_RXRINGEND (1 << 15) 2025b1b1883SVipin KUMAR #define DESC_RXCTRL_RXCHAIN (1 << 14) 2035b1b1883SVipin KUMAR 2045b1b1883SVipin KUMAR #define DESC_RXCTRL_SIZE1MASK (0x1FFF << 0) 2055b1b1883SVipin KUMAR #define DESC_RXCTRL_SIZE1SHFT (0) 2065b1b1883SVipin KUMAR #define DESC_RXCTRL_SIZE2MASK (0x1FFF << 16) 2075b1b1883SVipin KUMAR #define DESC_RXCTRL_SIZE2SHFT (16) 2085b1b1883SVipin KUMAR 2095b1b1883SVipin KUMAR #else 2105b1b1883SVipin KUMAR 2115b1b1883SVipin KUMAR #define DESC_RXCTRL_RXINTDIS (1 << 31) 2125b1b1883SVipin KUMAR #define DESC_RXCTRL_RXRINGEND (1 << 25) 2135b1b1883SVipin KUMAR #define DESC_RXCTRL_RXCHAIN (1 << 24) 2145b1b1883SVipin KUMAR 2155b1b1883SVipin KUMAR #define DESC_RXCTRL_SIZE1MASK (0x7FF << 0) 2165b1b1883SVipin KUMAR #define DESC_RXCTRL_SIZE1SHFT (0) 2175b1b1883SVipin KUMAR #define DESC_RXCTRL_SIZE2MASK (0x7FF << 11) 2185b1b1883SVipin KUMAR #define DESC_RXCTRL_SIZE2SHFT (11) 2195b1b1883SVipin KUMAR 2205b1b1883SVipin KUMAR #endif 2215b1b1883SVipin KUMAR 2225b1b1883SVipin KUMAR struct dw_eth_dev { 2231857075aSIan Campbell struct dmamacdescr tx_mac_descrtable[CONFIG_TX_DESCR_NUM]; 2241857075aSIan Campbell struct dmamacdescr rx_mac_descrtable[CONFIG_RX_DESCR_NUM]; 2251857075aSIan Campbell char txbuffs[TX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN); 2261857075aSIan Campbell char rxbuffs[RX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN); 2271857075aSIan Campbell 2289afc1af0SVipin Kumar u32 interface; 2296968ec92SAlexey Brodkin u32 max_speed; 2305b1b1883SVipin KUMAR u32 tx_currdescnum; 2315b1b1883SVipin KUMAR u32 rx_currdescnum; 2325b1b1883SVipin KUMAR 2335b1b1883SVipin KUMAR struct eth_mac_regs *mac_regs_p; 2345b1b1883SVipin KUMAR struct eth_dma_regs *dma_regs_p; 23575577ba4SSimon Glass #ifndef CONFIG_DM_ETH 2365b1b1883SVipin KUMAR struct eth_device *dev; 23775577ba4SSimon Glass #endif 23866d027e2SAlexey Brodkin #ifdef CONFIG_DM_GPIO 23990b7fc92SSjoerd Simons struct gpio_desc reset_gpio; 24066d027e2SAlexey Brodkin #endif 241ba1f9667SPatrice Chotard #ifdef CONFIG_CLK 242ba1f9667SPatrice Chotard struct clk *clocks; /* clock list */ 243ba1f9667SPatrice Chotard int clock_count; /* number of clock in clock list */ 244ba1f9667SPatrice Chotard #endif 24566d027e2SAlexey Brodkin 24692a190aaSAlexey Brodkin struct phy_device *phydev; 24792a190aaSAlexey Brodkin struct mii_dev *bus; 248ed102be7SAlexey Brodkin }; 2495b1b1883SVipin KUMAR 25090b7fc92SSjoerd Simons #ifdef CONFIG_DM_ETH 251b9e08d0eSSjoerd Simons int designware_eth_ofdata_to_platdata(struct udevice *dev); 252b9e08d0eSSjoerd Simons int designware_eth_probe(struct udevice *dev); 253b9e08d0eSSjoerd Simons extern const struct eth_ops designware_eth_ops; 254b9e08d0eSSjoerd Simons 25590b7fc92SSjoerd Simons struct dw_eth_pdata { 25690b7fc92SSjoerd Simons struct eth_pdata eth_pdata; 25790b7fc92SSjoerd Simons u32 reset_delays[3]; 25890b7fc92SSjoerd Simons }; 259e72ced23SSimon Glass 260e72ced23SSimon Glass int designware_eth_init(struct dw_eth_dev *priv, u8 *enetaddr); 261e72ced23SSimon Glass int designware_eth_enable(struct dw_eth_dev *priv); 262e72ced23SSimon Glass int designware_eth_send(struct udevice *dev, void *packet, int length); 263e72ced23SSimon Glass int designware_eth_recv(struct udevice *dev, int flags, uchar **packetp); 264e72ced23SSimon Glass int designware_eth_free_pkt(struct udevice *dev, uchar *packet, 265e72ced23SSimon Glass int length); 266e72ced23SSimon Glass void designware_eth_stop(struct udevice *dev); 267e72ced23SSimon Glass int designware_eth_write_hwaddr(struct udevice *dev); 26890b7fc92SSjoerd Simons #endif 26990b7fc92SSjoerd Simons 2705b1b1883SVipin KUMAR #endif 271