1 /* 2 * (C) Copyright 2010 3 * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 /* 9 * Designware ethernet IP driver for U-Boot 10 */ 11 12 #include <common.h> 13 #include <dm.h> 14 #include <errno.h> 15 #include <miiphy.h> 16 #include <malloc.h> 17 #include <pci.h> 18 #include <linux/compiler.h> 19 #include <linux/err.h> 20 #include <asm/io.h> 21 #include <power/regulator.h> 22 #include "designware.h" 23 24 DECLARE_GLOBAL_DATA_PTR; 25 26 static int dw_mdio_read(struct mii_dev *bus, int addr, int devad, int reg) 27 { 28 #ifdef CONFIG_DM_ETH 29 struct dw_eth_dev *priv = dev_get_priv((struct udevice *)bus->priv); 30 struct eth_mac_regs *mac_p = priv->mac_regs_p; 31 #else 32 struct eth_mac_regs *mac_p = bus->priv; 33 #endif 34 ulong start; 35 u16 miiaddr; 36 int timeout = CONFIG_MDIO_TIMEOUT; 37 38 miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) | 39 ((reg << MIIREGSHIFT) & MII_REGMSK); 40 41 writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr); 42 43 start = get_timer(0); 44 while (get_timer(start) < timeout) { 45 if (!(readl(&mac_p->miiaddr) & MII_BUSY)) 46 return readl(&mac_p->miidata); 47 udelay(10); 48 }; 49 50 return -ETIMEDOUT; 51 } 52 53 static int dw_mdio_write(struct mii_dev *bus, int addr, int devad, int reg, 54 u16 val) 55 { 56 #ifdef CONFIG_DM_ETH 57 struct dw_eth_dev *priv = dev_get_priv((struct udevice *)bus->priv); 58 struct eth_mac_regs *mac_p = priv->mac_regs_p; 59 #else 60 struct eth_mac_regs *mac_p = bus->priv; 61 #endif 62 ulong start; 63 u16 miiaddr; 64 int ret = -ETIMEDOUT, timeout = CONFIG_MDIO_TIMEOUT; 65 66 writel(val, &mac_p->miidata); 67 miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) | 68 ((reg << MIIREGSHIFT) & MII_REGMSK) | MII_WRITE; 69 70 writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr); 71 72 start = get_timer(0); 73 while (get_timer(start) < timeout) { 74 if (!(readl(&mac_p->miiaddr) & MII_BUSY)) { 75 ret = 0; 76 break; 77 } 78 udelay(10); 79 }; 80 81 return ret; 82 } 83 84 #if defined(CONFIG_DM_ETH) && defined(CONFIG_DM_GPIO) 85 static int dw_mdio_reset(struct mii_dev *bus) 86 { 87 struct udevice *dev = bus->priv; 88 struct dw_eth_dev *priv = dev_get_priv(dev); 89 struct dw_eth_pdata *pdata = dev_get_platdata(dev); 90 int ret; 91 92 if (!dm_gpio_is_valid(&priv->reset_gpio)) 93 return 0; 94 95 /* reset the phy */ 96 ret = dm_gpio_set_value(&priv->reset_gpio, 0); 97 if (ret) 98 return ret; 99 100 udelay(pdata->reset_delays[0]); 101 102 ret = dm_gpio_set_value(&priv->reset_gpio, 1); 103 if (ret) 104 return ret; 105 106 udelay(pdata->reset_delays[1]); 107 108 ret = dm_gpio_set_value(&priv->reset_gpio, 0); 109 if (ret) 110 return ret; 111 112 udelay(pdata->reset_delays[2]); 113 114 return 0; 115 } 116 #endif 117 118 static int dw_mdio_init(const char *name, void *priv) 119 { 120 struct mii_dev *bus = mdio_alloc(); 121 122 if (!bus) { 123 printf("Failed to allocate MDIO bus\n"); 124 return -ENOMEM; 125 } 126 127 bus->read = dw_mdio_read; 128 bus->write = dw_mdio_write; 129 snprintf(bus->name, sizeof(bus->name), "%s", name); 130 #if defined(CONFIG_DM_ETH) && defined(CONFIG_DM_GPIO) 131 bus->reset = dw_mdio_reset; 132 #endif 133 134 bus->priv = priv; 135 136 return mdio_register(bus); 137 } 138 139 static void tx_descs_init(struct dw_eth_dev *priv) 140 { 141 struct eth_dma_regs *dma_p = priv->dma_regs_p; 142 struct dmamacdescr *desc_table_p = &priv->tx_mac_descrtable[0]; 143 char *txbuffs = &priv->txbuffs[0]; 144 struct dmamacdescr *desc_p; 145 u32 idx; 146 147 for (idx = 0; idx < CONFIG_TX_DESCR_NUM; idx++) { 148 desc_p = &desc_table_p[idx]; 149 desc_p->dmamac_addr = (ulong)&txbuffs[idx * CONFIG_ETH_BUFSIZE]; 150 desc_p->dmamac_next = (ulong)&desc_table_p[idx + 1]; 151 152 #if defined(CONFIG_DW_ALTDESCRIPTOR) 153 desc_p->txrx_status &= ~(DESC_TXSTS_TXINT | DESC_TXSTS_TXLAST | 154 DESC_TXSTS_TXFIRST | DESC_TXSTS_TXCRCDIS | 155 DESC_TXSTS_TXCHECKINSCTRL | 156 DESC_TXSTS_TXRINGEND | DESC_TXSTS_TXPADDIS); 157 158 desc_p->txrx_status |= DESC_TXSTS_TXCHAIN; 159 desc_p->dmamac_cntl = 0; 160 desc_p->txrx_status &= ~(DESC_TXSTS_MSK | DESC_TXSTS_OWNBYDMA); 161 #else 162 desc_p->dmamac_cntl = DESC_TXCTRL_TXCHAIN; 163 desc_p->txrx_status = 0; 164 #endif 165 } 166 167 /* Correcting the last pointer of the chain */ 168 desc_p->dmamac_next = (ulong)&desc_table_p[0]; 169 170 /* Flush all Tx buffer descriptors at once */ 171 flush_dcache_range((ulong)priv->tx_mac_descrtable, 172 (ulong)priv->tx_mac_descrtable + 173 sizeof(priv->tx_mac_descrtable)); 174 175 writel((ulong)&desc_table_p[0], &dma_p->txdesclistaddr); 176 priv->tx_currdescnum = 0; 177 } 178 179 static void rx_descs_init(struct dw_eth_dev *priv) 180 { 181 struct eth_dma_regs *dma_p = priv->dma_regs_p; 182 struct dmamacdescr *desc_table_p = &priv->rx_mac_descrtable[0]; 183 char *rxbuffs = &priv->rxbuffs[0]; 184 struct dmamacdescr *desc_p; 185 u32 idx; 186 187 /* Before passing buffers to GMAC we need to make sure zeros 188 * written there right after "priv" structure allocation were 189 * flushed into RAM. 190 * Otherwise there's a chance to get some of them flushed in RAM when 191 * GMAC is already pushing data to RAM via DMA. This way incoming from 192 * GMAC data will be corrupted. */ 193 flush_dcache_range((ulong)rxbuffs, (ulong)rxbuffs + RX_TOTAL_BUFSIZE); 194 195 for (idx = 0; idx < CONFIG_RX_DESCR_NUM; idx++) { 196 desc_p = &desc_table_p[idx]; 197 desc_p->dmamac_addr = (ulong)&rxbuffs[idx * CONFIG_ETH_BUFSIZE]; 198 desc_p->dmamac_next = (ulong)&desc_table_p[idx + 1]; 199 200 desc_p->dmamac_cntl = 201 (MAC_MAX_FRAME_SZ & DESC_RXCTRL_SIZE1MASK) | 202 DESC_RXCTRL_RXCHAIN; 203 204 desc_p->txrx_status = DESC_RXSTS_OWNBYDMA; 205 } 206 207 /* Correcting the last pointer of the chain */ 208 desc_p->dmamac_next = (ulong)&desc_table_p[0]; 209 210 /* Flush all Rx buffer descriptors at once */ 211 flush_dcache_range((ulong)priv->rx_mac_descrtable, 212 (ulong)priv->rx_mac_descrtable + 213 sizeof(priv->rx_mac_descrtable)); 214 215 writel((ulong)&desc_table_p[0], &dma_p->rxdesclistaddr); 216 priv->rx_currdescnum = 0; 217 } 218 219 static int _dw_write_hwaddr(struct dw_eth_dev *priv, u8 *mac_id) 220 { 221 struct eth_mac_regs *mac_p = priv->mac_regs_p; 222 u32 macid_lo, macid_hi; 223 224 macid_lo = mac_id[0] + (mac_id[1] << 8) + (mac_id[2] << 16) + 225 (mac_id[3] << 24); 226 macid_hi = mac_id[4] + (mac_id[5] << 8); 227 228 writel(macid_hi, &mac_p->macaddr0hi); 229 writel(macid_lo, &mac_p->macaddr0lo); 230 231 return 0; 232 } 233 234 static int dw_adjust_link(struct dw_eth_dev *priv, struct eth_mac_regs *mac_p, 235 struct phy_device *phydev) 236 { 237 u32 conf = readl(&mac_p->conf) | FRAMEBURSTENABLE | DISABLERXOWN; 238 239 if (!phydev->link) { 240 printf("%s: No link.\n", phydev->dev->name); 241 return 0; 242 } 243 244 if (phydev->speed != 1000) 245 conf |= MII_PORTSELECT; 246 else 247 conf &= ~MII_PORTSELECT; 248 249 if (phydev->speed == 100) 250 conf |= FES_100; 251 252 if (phydev->duplex) 253 conf |= FULLDPLXMODE; 254 255 writel(conf, &mac_p->conf); 256 257 printf("Speed: %d, %s duplex%s\n", phydev->speed, 258 (phydev->duplex) ? "full" : "half", 259 (phydev->port == PORT_FIBRE) ? ", fiber mode" : ""); 260 261 return 0; 262 } 263 264 static void _dw_eth_halt(struct dw_eth_dev *priv) 265 { 266 struct eth_mac_regs *mac_p = priv->mac_regs_p; 267 struct eth_dma_regs *dma_p = priv->dma_regs_p; 268 269 writel(readl(&mac_p->conf) & ~(RXENABLE | TXENABLE), &mac_p->conf); 270 writel(readl(&dma_p->opmode) & ~(RXSTART | TXSTART), &dma_p->opmode); 271 272 phy_shutdown(priv->phydev); 273 } 274 275 int designware_eth_init(struct dw_eth_dev *priv, u8 *enetaddr) 276 { 277 struct eth_mac_regs *mac_p = priv->mac_regs_p; 278 struct eth_dma_regs *dma_p = priv->dma_regs_p; 279 unsigned int start; 280 int ret; 281 282 writel(readl(&dma_p->busmode) | DMAMAC_SRST, &dma_p->busmode); 283 284 start = get_timer(0); 285 while (readl(&dma_p->busmode) & DMAMAC_SRST) { 286 if (get_timer(start) >= CONFIG_MACRESET_TIMEOUT) { 287 printf("DMA reset timeout\n"); 288 return -ETIMEDOUT; 289 } 290 291 mdelay(100); 292 }; 293 294 /* 295 * Soft reset above clears HW address registers. 296 * So we have to set it here once again. 297 */ 298 _dw_write_hwaddr(priv, enetaddr); 299 300 rx_descs_init(priv); 301 tx_descs_init(priv); 302 303 writel(FIXEDBURST | PRIORXTX_41 | DMA_PBL, &dma_p->busmode); 304 305 #ifndef CONFIG_DW_MAC_FORCE_THRESHOLD_MODE 306 writel(readl(&dma_p->opmode) | FLUSHTXFIFO | STOREFORWARD, 307 &dma_p->opmode); 308 #else 309 writel(readl(&dma_p->opmode) | FLUSHTXFIFO, 310 &dma_p->opmode); 311 #endif 312 313 writel(readl(&dma_p->opmode) | RXSTART | TXSTART, &dma_p->opmode); 314 315 #ifdef CONFIG_DW_AXI_BURST_LEN 316 writel((CONFIG_DW_AXI_BURST_LEN & 0x1FF >> 1), &dma_p->axibus); 317 #endif 318 319 /* Start up the PHY */ 320 ret = phy_startup(priv->phydev); 321 if (ret) { 322 printf("Could not initialize PHY %s\n", 323 priv->phydev->dev->name); 324 return ret; 325 } 326 327 ret = dw_adjust_link(priv, mac_p, priv->phydev); 328 if (ret) 329 return ret; 330 331 return 0; 332 } 333 334 int designware_eth_enable(struct dw_eth_dev *priv) 335 { 336 struct eth_mac_regs *mac_p = priv->mac_regs_p; 337 338 if (!priv->phydev->link) 339 return -EIO; 340 341 writel(readl(&mac_p->conf) | RXENABLE | TXENABLE, &mac_p->conf); 342 343 return 0; 344 } 345 346 static int _dw_eth_send(struct dw_eth_dev *priv, void *packet, int length) 347 { 348 struct eth_dma_regs *dma_p = priv->dma_regs_p; 349 u32 desc_num = priv->tx_currdescnum; 350 struct dmamacdescr *desc_p = &priv->tx_mac_descrtable[desc_num]; 351 ulong desc_start = (ulong)desc_p; 352 ulong desc_end = desc_start + 353 roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN); 354 ulong data_start = desc_p->dmamac_addr; 355 ulong data_end = data_start + roundup(length, ARCH_DMA_MINALIGN); 356 /* 357 * Strictly we only need to invalidate the "txrx_status" field 358 * for the following check, but on some platforms we cannot 359 * invalidate only 4 bytes, so we flush the entire descriptor, 360 * which is 16 bytes in total. This is safe because the 361 * individual descriptors in the array are each aligned to 362 * ARCH_DMA_MINALIGN and padded appropriately. 363 */ 364 invalidate_dcache_range(desc_start, desc_end); 365 366 /* Check if the descriptor is owned by CPU */ 367 if (desc_p->txrx_status & DESC_TXSTS_OWNBYDMA) { 368 printf("CPU not owner of tx frame\n"); 369 return -EPERM; 370 } 371 372 memcpy((void *)data_start, packet, length); 373 374 /* Flush data to be sent */ 375 flush_dcache_range(data_start, data_end); 376 377 #if defined(CONFIG_DW_ALTDESCRIPTOR) 378 desc_p->txrx_status |= DESC_TXSTS_TXFIRST | DESC_TXSTS_TXLAST; 379 desc_p->dmamac_cntl |= (length << DESC_TXCTRL_SIZE1SHFT) & 380 DESC_TXCTRL_SIZE1MASK; 381 382 desc_p->txrx_status &= ~(DESC_TXSTS_MSK); 383 desc_p->txrx_status |= DESC_TXSTS_OWNBYDMA; 384 #else 385 desc_p->dmamac_cntl |= ((length << DESC_TXCTRL_SIZE1SHFT) & 386 DESC_TXCTRL_SIZE1MASK) | DESC_TXCTRL_TXLAST | 387 DESC_TXCTRL_TXFIRST; 388 389 desc_p->txrx_status = DESC_TXSTS_OWNBYDMA; 390 #endif 391 392 /* Flush modified buffer descriptor */ 393 flush_dcache_range(desc_start, desc_end); 394 395 /* Test the wrap-around condition. */ 396 if (++desc_num >= CONFIG_TX_DESCR_NUM) 397 desc_num = 0; 398 399 priv->tx_currdescnum = desc_num; 400 401 /* Start the transmission */ 402 writel(POLL_DATA, &dma_p->txpolldemand); 403 404 return 0; 405 } 406 407 static int _dw_eth_recv(struct dw_eth_dev *priv, uchar **packetp) 408 { 409 u32 status, desc_num = priv->rx_currdescnum; 410 struct dmamacdescr *desc_p = &priv->rx_mac_descrtable[desc_num]; 411 int length = -EAGAIN; 412 ulong desc_start = (ulong)desc_p; 413 ulong desc_end = desc_start + 414 roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN); 415 ulong data_start = desc_p->dmamac_addr; 416 ulong data_end; 417 418 /* Invalidate entire buffer descriptor */ 419 invalidate_dcache_range(desc_start, desc_end); 420 421 status = desc_p->txrx_status; 422 423 /* Check if the owner is the CPU */ 424 if (!(status & DESC_RXSTS_OWNBYDMA)) { 425 426 length = (status & DESC_RXSTS_FRMLENMSK) >> 427 DESC_RXSTS_FRMLENSHFT; 428 429 /* Invalidate received data */ 430 data_end = data_start + roundup(length, ARCH_DMA_MINALIGN); 431 invalidate_dcache_range(data_start, data_end); 432 *packetp = (uchar *)(ulong)desc_p->dmamac_addr; 433 } 434 435 return length; 436 } 437 438 static int _dw_free_pkt(struct dw_eth_dev *priv) 439 { 440 u32 desc_num = priv->rx_currdescnum; 441 struct dmamacdescr *desc_p = &priv->rx_mac_descrtable[desc_num]; 442 ulong desc_start = (ulong)desc_p; 443 ulong desc_end = desc_start + 444 roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN); 445 446 /* 447 * Make the current descriptor valid again and go to 448 * the next one 449 */ 450 desc_p->txrx_status |= DESC_RXSTS_OWNBYDMA; 451 452 /* Flush only status field - others weren't changed */ 453 flush_dcache_range(desc_start, desc_end); 454 455 /* Test the wrap-around condition. */ 456 if (++desc_num >= CONFIG_RX_DESCR_NUM) 457 desc_num = 0; 458 priv->rx_currdescnum = desc_num; 459 460 return 0; 461 } 462 463 static int dw_phy_init(struct dw_eth_dev *priv, void *dev) 464 { 465 struct phy_device *phydev; 466 int mask = 0xffffffff, ret; 467 468 #ifdef CONFIG_PHY_ADDR 469 mask = 1 << CONFIG_PHY_ADDR; 470 #endif 471 472 phydev = phy_find_by_mask(priv->bus, mask, priv->interface); 473 if (!phydev) 474 return -ENODEV; 475 476 phy_connect_dev(phydev, dev); 477 478 phydev->supported &= PHY_GBIT_FEATURES; 479 if (priv->max_speed) { 480 ret = phy_set_supported(phydev, priv->max_speed); 481 if (ret) 482 return ret; 483 } 484 phydev->advertising = phydev->supported; 485 486 priv->phydev = phydev; 487 phy_config(phydev); 488 489 return 0; 490 } 491 492 #ifndef CONFIG_DM_ETH 493 static int dw_eth_init(struct eth_device *dev, bd_t *bis) 494 { 495 int ret; 496 497 ret = designware_eth_init(dev->priv, dev->enetaddr); 498 if (!ret) 499 ret = designware_eth_enable(dev->priv); 500 501 return ret; 502 } 503 504 static int dw_eth_send(struct eth_device *dev, void *packet, int length) 505 { 506 return _dw_eth_send(dev->priv, packet, length); 507 } 508 509 static int dw_eth_recv(struct eth_device *dev) 510 { 511 uchar *packet; 512 int length; 513 514 length = _dw_eth_recv(dev->priv, &packet); 515 if (length == -EAGAIN) 516 return 0; 517 net_process_received_packet(packet, length); 518 519 _dw_free_pkt(dev->priv); 520 521 return 0; 522 } 523 524 static void dw_eth_halt(struct eth_device *dev) 525 { 526 return _dw_eth_halt(dev->priv); 527 } 528 529 static int dw_write_hwaddr(struct eth_device *dev) 530 { 531 return _dw_write_hwaddr(dev->priv, dev->enetaddr); 532 } 533 534 int designware_initialize(ulong base_addr, u32 interface) 535 { 536 struct eth_device *dev; 537 struct dw_eth_dev *priv; 538 539 dev = (struct eth_device *) malloc(sizeof(struct eth_device)); 540 if (!dev) 541 return -ENOMEM; 542 543 /* 544 * Since the priv structure contains the descriptors which need a strict 545 * buswidth alignment, memalign is used to allocate memory 546 */ 547 priv = (struct dw_eth_dev *) memalign(ARCH_DMA_MINALIGN, 548 sizeof(struct dw_eth_dev)); 549 if (!priv) { 550 free(dev); 551 return -ENOMEM; 552 } 553 554 if ((phys_addr_t)priv + sizeof(*priv) > (1ULL << 32)) { 555 printf("designware: buffers are outside DMA memory\n"); 556 return -EINVAL; 557 } 558 559 memset(dev, 0, sizeof(struct eth_device)); 560 memset(priv, 0, sizeof(struct dw_eth_dev)); 561 562 sprintf(dev->name, "dwmac.%lx", base_addr); 563 dev->iobase = (int)base_addr; 564 dev->priv = priv; 565 566 priv->dev = dev; 567 priv->mac_regs_p = (struct eth_mac_regs *)base_addr; 568 priv->dma_regs_p = (struct eth_dma_regs *)(base_addr + 569 DW_DMA_BASE_OFFSET); 570 571 dev->init = dw_eth_init; 572 dev->send = dw_eth_send; 573 dev->recv = dw_eth_recv; 574 dev->halt = dw_eth_halt; 575 dev->write_hwaddr = dw_write_hwaddr; 576 577 eth_register(dev); 578 579 priv->interface = interface; 580 581 dw_mdio_init(dev->name, priv->mac_regs_p); 582 priv->bus = miiphy_get_dev_by_name(dev->name); 583 584 return dw_phy_init(priv, dev); 585 } 586 #endif 587 588 #ifdef CONFIG_DM_ETH 589 static int designware_eth_start(struct udevice *dev) 590 { 591 struct eth_pdata *pdata = dev_get_platdata(dev); 592 struct dw_eth_dev *priv = dev_get_priv(dev); 593 int ret; 594 595 ret = designware_eth_init(priv, pdata->enetaddr); 596 if (ret) 597 return ret; 598 ret = designware_eth_enable(priv); 599 if (ret) 600 return ret; 601 602 return 0; 603 } 604 605 int designware_eth_send(struct udevice *dev, void *packet, int length) 606 { 607 struct dw_eth_dev *priv = dev_get_priv(dev); 608 609 return _dw_eth_send(priv, packet, length); 610 } 611 612 int designware_eth_recv(struct udevice *dev, int flags, uchar **packetp) 613 { 614 struct dw_eth_dev *priv = dev_get_priv(dev); 615 616 return _dw_eth_recv(priv, packetp); 617 } 618 619 int designware_eth_free_pkt(struct udevice *dev, uchar *packet, int length) 620 { 621 struct dw_eth_dev *priv = dev_get_priv(dev); 622 623 return _dw_free_pkt(priv); 624 } 625 626 void designware_eth_stop(struct udevice *dev) 627 { 628 struct dw_eth_dev *priv = dev_get_priv(dev); 629 630 return _dw_eth_halt(priv); 631 } 632 633 int designware_eth_write_hwaddr(struct udevice *dev) 634 { 635 struct eth_pdata *pdata = dev_get_platdata(dev); 636 struct dw_eth_dev *priv = dev_get_priv(dev); 637 638 return _dw_write_hwaddr(priv, pdata->enetaddr); 639 } 640 641 static int designware_eth_bind(struct udevice *dev) 642 { 643 #ifdef CONFIG_DM_PCI 644 static int num_cards; 645 char name[20]; 646 647 /* Create a unique device name for PCI type devices */ 648 if (device_is_on_pci_bus(dev)) { 649 sprintf(name, "eth_designware#%u", num_cards++); 650 device_set_name(dev, name); 651 } 652 #endif 653 654 return 0; 655 } 656 657 int designware_eth_probe(struct udevice *dev) 658 { 659 struct eth_pdata *pdata = dev_get_platdata(dev); 660 struct dw_eth_dev *priv = dev_get_priv(dev); 661 u32 iobase = pdata->iobase; 662 ulong ioaddr; 663 int ret; 664 665 #if defined(CONFIG_DM_REGULATOR) 666 struct udevice *phy_supply; 667 668 ret = device_get_supply_regulator(dev, "phy-supply", 669 &phy_supply); 670 if (ret) { 671 debug("%s: No phy supply\n", dev->name); 672 } else { 673 ret = regulator_set_enable(phy_supply, true); 674 if (ret) { 675 puts("Error enabling phy supply\n"); 676 return ret; 677 } 678 } 679 #endif 680 681 #ifdef CONFIG_DM_PCI 682 /* 683 * If we are on PCI bus, either directly attached to a PCI root port, 684 * or via a PCI bridge, fill in platdata before we probe the hardware. 685 */ 686 if (device_is_on_pci_bus(dev)) { 687 dm_pci_read_config32(dev, PCI_BASE_ADDRESS_0, &iobase); 688 iobase &= PCI_BASE_ADDRESS_MEM_MASK; 689 iobase = dm_pci_mem_to_phys(dev, iobase); 690 691 pdata->iobase = iobase; 692 pdata->phy_interface = PHY_INTERFACE_MODE_RMII; 693 } 694 #endif 695 696 debug("%s, iobase=%x, priv=%p\n", __func__, iobase, priv); 697 ioaddr = iobase; 698 priv->mac_regs_p = (struct eth_mac_regs *)ioaddr; 699 priv->dma_regs_p = (struct eth_dma_regs *)(ioaddr + DW_DMA_BASE_OFFSET); 700 priv->interface = pdata->phy_interface; 701 priv->max_speed = pdata->max_speed; 702 703 dw_mdio_init(dev->name, dev); 704 priv->bus = miiphy_get_dev_by_name(dev->name); 705 706 ret = dw_phy_init(priv, dev); 707 debug("%s, ret=%d\n", __func__, ret); 708 709 return ret; 710 } 711 712 static int designware_eth_remove(struct udevice *dev) 713 { 714 struct dw_eth_dev *priv = dev_get_priv(dev); 715 716 free(priv->phydev); 717 mdio_unregister(priv->bus); 718 mdio_free(priv->bus); 719 720 return 0; 721 } 722 723 const struct eth_ops designware_eth_ops = { 724 .start = designware_eth_start, 725 .send = designware_eth_send, 726 .recv = designware_eth_recv, 727 .free_pkt = designware_eth_free_pkt, 728 .stop = designware_eth_stop, 729 .write_hwaddr = designware_eth_write_hwaddr, 730 }; 731 732 int designware_eth_ofdata_to_platdata(struct udevice *dev) 733 { 734 struct dw_eth_pdata *dw_pdata = dev_get_platdata(dev); 735 #ifdef CONFIG_DM_GPIO 736 struct dw_eth_dev *priv = dev_get_priv(dev); 737 #endif 738 struct eth_pdata *pdata = &dw_pdata->eth_pdata; 739 const char *phy_mode; 740 const fdt32_t *cell; 741 #ifdef CONFIG_DM_GPIO 742 int reset_flags = GPIOD_IS_OUT; 743 #endif 744 int ret = 0; 745 746 pdata->iobase = devfdt_get_addr(dev); 747 pdata->phy_interface = -1; 748 phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode", 749 NULL); 750 if (phy_mode) 751 pdata->phy_interface = phy_get_interface_by_name(phy_mode); 752 if (pdata->phy_interface == -1) { 753 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode); 754 return -EINVAL; 755 } 756 757 pdata->max_speed = 0; 758 cell = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "max-speed", NULL); 759 if (cell) 760 pdata->max_speed = fdt32_to_cpu(*cell); 761 762 #ifdef CONFIG_DM_GPIO 763 if (dev_read_bool(dev, "snps,reset-active-low")) 764 reset_flags |= GPIOD_ACTIVE_LOW; 765 766 ret = gpio_request_by_name(dev, "snps,reset-gpio", 0, 767 &priv->reset_gpio, reset_flags); 768 if (ret == 0) { 769 ret = dev_read_u32_array(dev, "snps,reset-delays-us", 770 dw_pdata->reset_delays, 3); 771 } else if (ret == -ENOENT) { 772 ret = 0; 773 } 774 #endif 775 776 return ret; 777 } 778 779 static const struct udevice_id designware_eth_ids[] = { 780 { .compatible = "allwinner,sun7i-a20-gmac" }, 781 { .compatible = "altr,socfpga-stmmac" }, 782 { .compatible = "amlogic,meson6-dwmac" }, 783 { .compatible = "amlogic,meson-gx-dwmac" }, 784 { .compatible = "st,stm32-dwmac" }, 785 { } 786 }; 787 788 U_BOOT_DRIVER(eth_designware) = { 789 .name = "eth_designware", 790 .id = UCLASS_ETH, 791 .of_match = designware_eth_ids, 792 .ofdata_to_platdata = designware_eth_ofdata_to_platdata, 793 .bind = designware_eth_bind, 794 .probe = designware_eth_probe, 795 .remove = designware_eth_remove, 796 .ops = &designware_eth_ops, 797 .priv_auto_alloc_size = sizeof(struct dw_eth_dev), 798 .platdata_auto_alloc_size = sizeof(struct dw_eth_pdata), 799 .flags = DM_FLAG_ALLOC_PRIV_DMA, 800 }; 801 802 static struct pci_device_id supported[] = { 803 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QRK_EMAC) }, 804 { } 805 }; 806 807 U_BOOT_PCI_DEVICE(eth_designware, supported); 808 #endif 809