1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * (C) Copyright 2010 4 * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. 5 */ 6 7 /* 8 * Designware ethernet IP driver for U-Boot 9 */ 10 11 #include <common.h> 12 #include <clk.h> 13 #include <dm.h> 14 #include <errno.h> 15 #include <miiphy.h> 16 #include <malloc.h> 17 #include <pci.h> 18 #include <linux/compiler.h> 19 #include <linux/err.h> 20 #include <linux/kernel.h> 21 #include <asm/io.h> 22 #include <power/regulator.h> 23 #include "designware.h" 24 25 static int dw_mdio_read(struct mii_dev *bus, int addr, int devad, int reg) 26 { 27 #ifdef CONFIG_DM_ETH 28 struct dw_eth_dev *priv = dev_get_priv((struct udevice *)bus->priv); 29 struct eth_mac_regs *mac_p = priv->mac_regs_p; 30 #else 31 struct eth_mac_regs *mac_p = bus->priv; 32 #endif 33 ulong start; 34 u16 miiaddr; 35 int timeout = CONFIG_MDIO_TIMEOUT; 36 37 miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) | 38 ((reg << MIIREGSHIFT) & MII_REGMSK); 39 40 writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr); 41 42 start = get_timer(0); 43 while (get_timer(start) < timeout) { 44 if (!(readl(&mac_p->miiaddr) & MII_BUSY)) 45 return readl(&mac_p->miidata); 46 udelay(10); 47 }; 48 49 return -ETIMEDOUT; 50 } 51 52 static int dw_mdio_write(struct mii_dev *bus, int addr, int devad, int reg, 53 u16 val) 54 { 55 #ifdef CONFIG_DM_ETH 56 struct dw_eth_dev *priv = dev_get_priv((struct udevice *)bus->priv); 57 struct eth_mac_regs *mac_p = priv->mac_regs_p; 58 #else 59 struct eth_mac_regs *mac_p = bus->priv; 60 #endif 61 ulong start; 62 u16 miiaddr; 63 int ret = -ETIMEDOUT, timeout = CONFIG_MDIO_TIMEOUT; 64 65 writel(val, &mac_p->miidata); 66 miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) | 67 ((reg << MIIREGSHIFT) & MII_REGMSK) | MII_WRITE; 68 69 writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr); 70 71 start = get_timer(0); 72 while (get_timer(start) < timeout) { 73 if (!(readl(&mac_p->miiaddr) & MII_BUSY)) { 74 ret = 0; 75 break; 76 } 77 udelay(10); 78 }; 79 80 return ret; 81 } 82 83 #if defined(CONFIG_DM_ETH) && defined(CONFIG_DM_GPIO) 84 static int dw_mdio_reset(struct mii_dev *bus) 85 { 86 struct udevice *dev = bus->priv; 87 struct dw_eth_dev *priv = dev_get_priv(dev); 88 struct dw_eth_pdata *pdata = dev_get_platdata(dev); 89 int ret; 90 91 if (!dm_gpio_is_valid(&priv->reset_gpio)) 92 return 0; 93 94 /* reset the phy */ 95 ret = dm_gpio_set_value(&priv->reset_gpio, 0); 96 if (ret) 97 return ret; 98 99 udelay(pdata->reset_delays[0]); 100 101 ret = dm_gpio_set_value(&priv->reset_gpio, 1); 102 if (ret) 103 return ret; 104 105 udelay(pdata->reset_delays[1]); 106 107 ret = dm_gpio_set_value(&priv->reset_gpio, 0); 108 if (ret) 109 return ret; 110 111 udelay(pdata->reset_delays[2]); 112 113 return 0; 114 } 115 #endif 116 117 static int dw_mdio_init(const char *name, void *priv) 118 { 119 struct mii_dev *bus = mdio_alloc(); 120 121 if (!bus) { 122 printf("Failed to allocate MDIO bus\n"); 123 return -ENOMEM; 124 } 125 126 bus->read = dw_mdio_read; 127 bus->write = dw_mdio_write; 128 snprintf(bus->name, sizeof(bus->name), "%s", name); 129 #if defined(CONFIG_DM_ETH) && defined(CONFIG_DM_GPIO) 130 bus->reset = dw_mdio_reset; 131 #endif 132 133 bus->priv = priv; 134 135 return mdio_register(bus); 136 } 137 138 static void tx_descs_init(struct dw_eth_dev *priv) 139 { 140 struct eth_dma_regs *dma_p = priv->dma_regs_p; 141 struct dmamacdescr *desc_table_p = &priv->tx_mac_descrtable[0]; 142 char *txbuffs = &priv->txbuffs[0]; 143 struct dmamacdescr *desc_p; 144 u32 idx; 145 146 for (idx = 0; idx < CONFIG_TX_DESCR_NUM; idx++) { 147 desc_p = &desc_table_p[idx]; 148 desc_p->dmamac_addr = (ulong)&txbuffs[idx * CONFIG_ETH_BUFSIZE]; 149 desc_p->dmamac_next = (ulong)&desc_table_p[idx + 1]; 150 151 #if defined(CONFIG_DW_ALTDESCRIPTOR) 152 desc_p->txrx_status &= ~(DESC_TXSTS_TXINT | DESC_TXSTS_TXLAST | 153 DESC_TXSTS_TXFIRST | DESC_TXSTS_TXCRCDIS | 154 DESC_TXSTS_TXCHECKINSCTRL | 155 DESC_TXSTS_TXRINGEND | DESC_TXSTS_TXPADDIS); 156 157 desc_p->txrx_status |= DESC_TXSTS_TXCHAIN; 158 desc_p->dmamac_cntl = 0; 159 desc_p->txrx_status &= ~(DESC_TXSTS_MSK | DESC_TXSTS_OWNBYDMA); 160 #else 161 desc_p->dmamac_cntl = DESC_TXCTRL_TXCHAIN; 162 desc_p->txrx_status = 0; 163 #endif 164 } 165 166 /* Correcting the last pointer of the chain */ 167 desc_p->dmamac_next = (ulong)&desc_table_p[0]; 168 169 /* Flush all Tx buffer descriptors at once */ 170 flush_dcache_range((ulong)priv->tx_mac_descrtable, 171 (ulong)priv->tx_mac_descrtable + 172 sizeof(priv->tx_mac_descrtable)); 173 174 writel((ulong)&desc_table_p[0], &dma_p->txdesclistaddr); 175 priv->tx_currdescnum = 0; 176 } 177 178 static void rx_descs_init(struct dw_eth_dev *priv) 179 { 180 struct eth_dma_regs *dma_p = priv->dma_regs_p; 181 struct dmamacdescr *desc_table_p = &priv->rx_mac_descrtable[0]; 182 char *rxbuffs = &priv->rxbuffs[0]; 183 struct dmamacdescr *desc_p; 184 u32 idx; 185 186 /* Before passing buffers to GMAC we need to make sure zeros 187 * written there right after "priv" structure allocation were 188 * flushed into RAM. 189 * Otherwise there's a chance to get some of them flushed in RAM when 190 * GMAC is already pushing data to RAM via DMA. This way incoming from 191 * GMAC data will be corrupted. */ 192 flush_dcache_range((ulong)rxbuffs, (ulong)rxbuffs + RX_TOTAL_BUFSIZE); 193 194 for (idx = 0; idx < CONFIG_RX_DESCR_NUM; idx++) { 195 desc_p = &desc_table_p[idx]; 196 desc_p->dmamac_addr = (ulong)&rxbuffs[idx * CONFIG_ETH_BUFSIZE]; 197 desc_p->dmamac_next = (ulong)&desc_table_p[idx + 1]; 198 199 desc_p->dmamac_cntl = 200 (MAC_MAX_FRAME_SZ & DESC_RXCTRL_SIZE1MASK) | 201 DESC_RXCTRL_RXCHAIN; 202 203 desc_p->txrx_status = DESC_RXSTS_OWNBYDMA; 204 } 205 206 /* Correcting the last pointer of the chain */ 207 desc_p->dmamac_next = (ulong)&desc_table_p[0]; 208 209 /* Flush all Rx buffer descriptors at once */ 210 flush_dcache_range((ulong)priv->rx_mac_descrtable, 211 (ulong)priv->rx_mac_descrtable + 212 sizeof(priv->rx_mac_descrtable)); 213 214 writel((ulong)&desc_table_p[0], &dma_p->rxdesclistaddr); 215 priv->rx_currdescnum = 0; 216 } 217 218 static int _dw_write_hwaddr(struct dw_eth_dev *priv, u8 *mac_id) 219 { 220 struct eth_mac_regs *mac_p = priv->mac_regs_p; 221 u32 macid_lo, macid_hi; 222 223 macid_lo = mac_id[0] + (mac_id[1] << 8) + (mac_id[2] << 16) + 224 (mac_id[3] << 24); 225 macid_hi = mac_id[4] + (mac_id[5] << 8); 226 227 writel(macid_hi, &mac_p->macaddr0hi); 228 writel(macid_lo, &mac_p->macaddr0lo); 229 230 return 0; 231 } 232 233 static int dw_adjust_link(struct dw_eth_dev *priv, struct eth_mac_regs *mac_p, 234 struct phy_device *phydev) 235 { 236 u32 conf = readl(&mac_p->conf) | FRAMEBURSTENABLE | DISABLERXOWN; 237 238 if (!phydev->link) { 239 printf("%s: No link.\n", phydev->dev->name); 240 return 0; 241 } 242 243 if (phydev->speed != 1000) 244 conf |= MII_PORTSELECT; 245 else 246 conf &= ~MII_PORTSELECT; 247 248 if (phydev->speed == 100) 249 conf |= FES_100; 250 251 if (phydev->duplex) 252 conf |= FULLDPLXMODE; 253 254 writel(conf, &mac_p->conf); 255 256 printf("Speed: %d, %s duplex%s\n", phydev->speed, 257 (phydev->duplex) ? "full" : "half", 258 (phydev->port == PORT_FIBRE) ? ", fiber mode" : ""); 259 260 return 0; 261 } 262 263 static void _dw_eth_halt(struct dw_eth_dev *priv) 264 { 265 struct eth_mac_regs *mac_p = priv->mac_regs_p; 266 struct eth_dma_regs *dma_p = priv->dma_regs_p; 267 268 writel(readl(&mac_p->conf) & ~(RXENABLE | TXENABLE), &mac_p->conf); 269 writel(readl(&dma_p->opmode) & ~(RXSTART | TXSTART), &dma_p->opmode); 270 271 phy_shutdown(priv->phydev); 272 } 273 274 int designware_eth_init(struct dw_eth_dev *priv, u8 *enetaddr) 275 { 276 struct eth_mac_regs *mac_p = priv->mac_regs_p; 277 struct eth_dma_regs *dma_p = priv->dma_regs_p; 278 unsigned int start; 279 int ret; 280 281 writel(readl(&dma_p->busmode) | DMAMAC_SRST, &dma_p->busmode); 282 283 start = get_timer(0); 284 while (readl(&dma_p->busmode) & DMAMAC_SRST) { 285 if (get_timer(start) >= CONFIG_MACRESET_TIMEOUT) { 286 printf("DMA reset timeout\n"); 287 return -ETIMEDOUT; 288 } 289 290 mdelay(100); 291 }; 292 293 /* 294 * Soft reset above clears HW address registers. 295 * So we have to set it here once again. 296 */ 297 _dw_write_hwaddr(priv, enetaddr); 298 299 rx_descs_init(priv); 300 tx_descs_init(priv); 301 302 writel(FIXEDBURST | PRIORXTX_41 | DMA_PBL, &dma_p->busmode); 303 304 #ifndef CONFIG_DW_MAC_FORCE_THRESHOLD_MODE 305 writel(readl(&dma_p->opmode) | FLUSHTXFIFO | STOREFORWARD, 306 &dma_p->opmode); 307 #else 308 writel(readl(&dma_p->opmode) | FLUSHTXFIFO, 309 &dma_p->opmode); 310 #endif 311 312 writel(readl(&dma_p->opmode) | RXSTART | TXSTART, &dma_p->opmode); 313 314 #ifdef CONFIG_DW_AXI_BURST_LEN 315 writel((CONFIG_DW_AXI_BURST_LEN & 0x1FF >> 1), &dma_p->axibus); 316 #endif 317 318 /* Start up the PHY */ 319 ret = phy_startup(priv->phydev); 320 if (ret) { 321 printf("Could not initialize PHY %s\n", 322 priv->phydev->dev->name); 323 return ret; 324 } 325 326 ret = dw_adjust_link(priv, mac_p, priv->phydev); 327 if (ret) 328 return ret; 329 330 return 0; 331 } 332 333 int designware_eth_enable(struct dw_eth_dev *priv) 334 { 335 struct eth_mac_regs *mac_p = priv->mac_regs_p; 336 337 if (!priv->phydev->link) 338 return -EIO; 339 340 writel(readl(&mac_p->conf) | RXENABLE | TXENABLE, &mac_p->conf); 341 342 return 0; 343 } 344 345 #define ETH_ZLEN 60 346 347 static int _dw_eth_send(struct dw_eth_dev *priv, void *packet, int length) 348 { 349 struct eth_dma_regs *dma_p = priv->dma_regs_p; 350 u32 desc_num = priv->tx_currdescnum; 351 struct dmamacdescr *desc_p = &priv->tx_mac_descrtable[desc_num]; 352 ulong desc_start = (ulong)desc_p; 353 ulong desc_end = desc_start + 354 roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN); 355 ulong data_start = desc_p->dmamac_addr; 356 ulong data_end = data_start + roundup(length, ARCH_DMA_MINALIGN); 357 /* 358 * Strictly we only need to invalidate the "txrx_status" field 359 * for the following check, but on some platforms we cannot 360 * invalidate only 4 bytes, so we flush the entire descriptor, 361 * which is 16 bytes in total. This is safe because the 362 * individual descriptors in the array are each aligned to 363 * ARCH_DMA_MINALIGN and padded appropriately. 364 */ 365 invalidate_dcache_range(desc_start, desc_end); 366 367 /* Check if the descriptor is owned by CPU */ 368 if (desc_p->txrx_status & DESC_TXSTS_OWNBYDMA) { 369 printf("CPU not owner of tx frame\n"); 370 return -EPERM; 371 } 372 373 length = max(length, ETH_ZLEN); 374 375 memcpy((void *)data_start, packet, length); 376 377 /* Flush data to be sent */ 378 flush_dcache_range(data_start, data_end); 379 380 #if defined(CONFIG_DW_ALTDESCRIPTOR) 381 desc_p->txrx_status |= DESC_TXSTS_TXFIRST | DESC_TXSTS_TXLAST; 382 desc_p->dmamac_cntl |= (length << DESC_TXCTRL_SIZE1SHFT) & 383 DESC_TXCTRL_SIZE1MASK; 384 385 desc_p->txrx_status &= ~(DESC_TXSTS_MSK); 386 desc_p->txrx_status |= DESC_TXSTS_OWNBYDMA; 387 #else 388 desc_p->dmamac_cntl |= ((length << DESC_TXCTRL_SIZE1SHFT) & 389 DESC_TXCTRL_SIZE1MASK) | DESC_TXCTRL_TXLAST | 390 DESC_TXCTRL_TXFIRST; 391 392 desc_p->txrx_status = DESC_TXSTS_OWNBYDMA; 393 #endif 394 395 /* Flush modified buffer descriptor */ 396 flush_dcache_range(desc_start, desc_end); 397 398 /* Test the wrap-around condition. */ 399 if (++desc_num >= CONFIG_TX_DESCR_NUM) 400 desc_num = 0; 401 402 priv->tx_currdescnum = desc_num; 403 404 /* Start the transmission */ 405 writel(POLL_DATA, &dma_p->txpolldemand); 406 407 return 0; 408 } 409 410 static int _dw_eth_recv(struct dw_eth_dev *priv, uchar **packetp) 411 { 412 u32 status, desc_num = priv->rx_currdescnum; 413 struct dmamacdescr *desc_p = &priv->rx_mac_descrtable[desc_num]; 414 int length = -EAGAIN; 415 ulong desc_start = (ulong)desc_p; 416 ulong desc_end = desc_start + 417 roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN); 418 ulong data_start = desc_p->dmamac_addr; 419 ulong data_end; 420 421 /* Invalidate entire buffer descriptor */ 422 invalidate_dcache_range(desc_start, desc_end); 423 424 status = desc_p->txrx_status; 425 426 /* Check if the owner is the CPU */ 427 if (!(status & DESC_RXSTS_OWNBYDMA)) { 428 429 length = (status & DESC_RXSTS_FRMLENMSK) >> 430 DESC_RXSTS_FRMLENSHFT; 431 432 /* Invalidate received data */ 433 data_end = data_start + roundup(length, ARCH_DMA_MINALIGN); 434 invalidate_dcache_range(data_start, data_end); 435 *packetp = (uchar *)(ulong)desc_p->dmamac_addr; 436 } 437 438 return length; 439 } 440 441 static int _dw_free_pkt(struct dw_eth_dev *priv) 442 { 443 u32 desc_num = priv->rx_currdescnum; 444 struct dmamacdescr *desc_p = &priv->rx_mac_descrtable[desc_num]; 445 ulong desc_start = (ulong)desc_p; 446 ulong desc_end = desc_start + 447 roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN); 448 449 /* 450 * Make the current descriptor valid again and go to 451 * the next one 452 */ 453 desc_p->txrx_status |= DESC_RXSTS_OWNBYDMA; 454 455 /* Flush only status field - others weren't changed */ 456 flush_dcache_range(desc_start, desc_end); 457 458 /* Test the wrap-around condition. */ 459 if (++desc_num >= CONFIG_RX_DESCR_NUM) 460 desc_num = 0; 461 priv->rx_currdescnum = desc_num; 462 463 return 0; 464 } 465 466 static int dw_phy_init(struct dw_eth_dev *priv, void *dev) 467 { 468 struct phy_device *phydev; 469 int mask = 0xffffffff, ret; 470 471 #ifdef CONFIG_PHY_ADDR 472 mask = 1 << CONFIG_PHY_ADDR; 473 #endif 474 475 phydev = phy_find_by_mask(priv->bus, mask, priv->interface); 476 if (!phydev) 477 return -ENODEV; 478 479 phy_connect_dev(phydev, dev); 480 481 phydev->supported &= PHY_GBIT_FEATURES; 482 if (priv->max_speed) { 483 ret = phy_set_supported(phydev, priv->max_speed); 484 if (ret) 485 return ret; 486 } 487 phydev->advertising = phydev->supported; 488 489 priv->phydev = phydev; 490 phy_config(phydev); 491 492 return 0; 493 } 494 495 #ifndef CONFIG_DM_ETH 496 static int dw_eth_init(struct eth_device *dev, bd_t *bis) 497 { 498 int ret; 499 500 ret = designware_eth_init(dev->priv, dev->enetaddr); 501 if (!ret) 502 ret = designware_eth_enable(dev->priv); 503 504 return ret; 505 } 506 507 static int dw_eth_send(struct eth_device *dev, void *packet, int length) 508 { 509 return _dw_eth_send(dev->priv, packet, length); 510 } 511 512 static int dw_eth_recv(struct eth_device *dev) 513 { 514 uchar *packet; 515 int length; 516 517 length = _dw_eth_recv(dev->priv, &packet); 518 if (length == -EAGAIN) 519 return 0; 520 net_process_received_packet(packet, length); 521 522 _dw_free_pkt(dev->priv); 523 524 return 0; 525 } 526 527 static void dw_eth_halt(struct eth_device *dev) 528 { 529 return _dw_eth_halt(dev->priv); 530 } 531 532 static int dw_write_hwaddr(struct eth_device *dev) 533 { 534 return _dw_write_hwaddr(dev->priv, dev->enetaddr); 535 } 536 537 int designware_initialize(ulong base_addr, u32 interface) 538 { 539 struct eth_device *dev; 540 struct dw_eth_dev *priv; 541 542 dev = (struct eth_device *) malloc(sizeof(struct eth_device)); 543 if (!dev) 544 return -ENOMEM; 545 546 /* 547 * Since the priv structure contains the descriptors which need a strict 548 * buswidth alignment, memalign is used to allocate memory 549 */ 550 priv = (struct dw_eth_dev *) memalign(ARCH_DMA_MINALIGN, 551 sizeof(struct dw_eth_dev)); 552 if (!priv) { 553 free(dev); 554 return -ENOMEM; 555 } 556 557 if ((phys_addr_t)priv + sizeof(*priv) > (1ULL << 32)) { 558 printf("designware: buffers are outside DMA memory\n"); 559 return -EINVAL; 560 } 561 562 memset(dev, 0, sizeof(struct eth_device)); 563 memset(priv, 0, sizeof(struct dw_eth_dev)); 564 565 sprintf(dev->name, "dwmac.%lx", base_addr); 566 dev->iobase = (int)base_addr; 567 dev->priv = priv; 568 569 priv->dev = dev; 570 priv->mac_regs_p = (struct eth_mac_regs *)base_addr; 571 priv->dma_regs_p = (struct eth_dma_regs *)(base_addr + 572 DW_DMA_BASE_OFFSET); 573 574 dev->init = dw_eth_init; 575 dev->send = dw_eth_send; 576 dev->recv = dw_eth_recv; 577 dev->halt = dw_eth_halt; 578 dev->write_hwaddr = dw_write_hwaddr; 579 580 eth_register(dev); 581 582 priv->interface = interface; 583 584 dw_mdio_init(dev->name, priv->mac_regs_p); 585 priv->bus = miiphy_get_dev_by_name(dev->name); 586 587 return dw_phy_init(priv, dev); 588 } 589 #endif 590 591 #ifdef CONFIG_DM_ETH 592 static int designware_eth_start(struct udevice *dev) 593 { 594 struct eth_pdata *pdata = dev_get_platdata(dev); 595 struct dw_eth_dev *priv = dev_get_priv(dev); 596 int ret; 597 598 ret = designware_eth_init(priv, pdata->enetaddr); 599 if (ret) 600 return ret; 601 ret = designware_eth_enable(priv); 602 if (ret) 603 return ret; 604 605 return 0; 606 } 607 608 int designware_eth_send(struct udevice *dev, void *packet, int length) 609 { 610 struct dw_eth_dev *priv = dev_get_priv(dev); 611 612 return _dw_eth_send(priv, packet, length); 613 } 614 615 int designware_eth_recv(struct udevice *dev, int flags, uchar **packetp) 616 { 617 struct dw_eth_dev *priv = dev_get_priv(dev); 618 619 return _dw_eth_recv(priv, packetp); 620 } 621 622 int designware_eth_free_pkt(struct udevice *dev, uchar *packet, int length) 623 { 624 struct dw_eth_dev *priv = dev_get_priv(dev); 625 626 return _dw_free_pkt(priv); 627 } 628 629 void designware_eth_stop(struct udevice *dev) 630 { 631 struct dw_eth_dev *priv = dev_get_priv(dev); 632 633 return _dw_eth_halt(priv); 634 } 635 636 int designware_eth_write_hwaddr(struct udevice *dev) 637 { 638 struct eth_pdata *pdata = dev_get_platdata(dev); 639 struct dw_eth_dev *priv = dev_get_priv(dev); 640 641 return _dw_write_hwaddr(priv, pdata->enetaddr); 642 } 643 644 static int designware_eth_bind(struct udevice *dev) 645 { 646 #ifdef CONFIG_DM_PCI 647 static int num_cards; 648 char name[20]; 649 650 /* Create a unique device name for PCI type devices */ 651 if (device_is_on_pci_bus(dev)) { 652 sprintf(name, "eth_designware#%u", num_cards++); 653 device_set_name(dev, name); 654 } 655 #endif 656 657 return 0; 658 } 659 660 int designware_eth_probe(struct udevice *dev) 661 { 662 struct eth_pdata *pdata = dev_get_platdata(dev); 663 struct dw_eth_dev *priv = dev_get_priv(dev); 664 u32 iobase = pdata->iobase; 665 ulong ioaddr; 666 int ret; 667 #ifdef CONFIG_CLK 668 int i, err, clock_nb; 669 670 priv->clock_count = 0; 671 clock_nb = dev_count_phandle_with_args(dev, "clocks", "#clock-cells"); 672 if (clock_nb > 0) { 673 priv->clocks = devm_kcalloc(dev, clock_nb, sizeof(struct clk), 674 GFP_KERNEL); 675 if (!priv->clocks) 676 return -ENOMEM; 677 678 for (i = 0; i < clock_nb; i++) { 679 err = clk_get_by_index(dev, i, &priv->clocks[i]); 680 if (err < 0) 681 break; 682 683 err = clk_enable(&priv->clocks[i]); 684 if (err && err != -ENOSYS && err != -ENOTSUPP) { 685 pr_err("failed to enable clock %d\n", i); 686 clk_free(&priv->clocks[i]); 687 goto clk_err; 688 } 689 priv->clock_count++; 690 } 691 } else if (clock_nb != -ENOENT) { 692 pr_err("failed to get clock phandle(%d)\n", clock_nb); 693 return clock_nb; 694 } 695 #endif 696 697 #if defined(CONFIG_DM_REGULATOR) 698 struct udevice *phy_supply; 699 700 ret = device_get_supply_regulator(dev, "phy-supply", 701 &phy_supply); 702 if (ret) { 703 debug("%s: No phy supply\n", dev->name); 704 } else { 705 ret = regulator_set_enable(phy_supply, true); 706 if (ret) { 707 puts("Error enabling phy supply\n"); 708 return ret; 709 } 710 } 711 #endif 712 713 #ifdef CONFIG_DM_PCI 714 /* 715 * If we are on PCI bus, either directly attached to a PCI root port, 716 * or via a PCI bridge, fill in platdata before we probe the hardware. 717 */ 718 if (device_is_on_pci_bus(dev)) { 719 dm_pci_read_config32(dev, PCI_BASE_ADDRESS_0, &iobase); 720 iobase &= PCI_BASE_ADDRESS_MEM_MASK; 721 iobase = dm_pci_mem_to_phys(dev, iobase); 722 723 pdata->iobase = iobase; 724 pdata->phy_interface = PHY_INTERFACE_MODE_RMII; 725 } 726 #endif 727 728 debug("%s, iobase=%x, priv=%p\n", __func__, iobase, priv); 729 ioaddr = iobase; 730 priv->mac_regs_p = (struct eth_mac_regs *)ioaddr; 731 priv->dma_regs_p = (struct eth_dma_regs *)(ioaddr + DW_DMA_BASE_OFFSET); 732 priv->interface = pdata->phy_interface; 733 priv->max_speed = pdata->max_speed; 734 735 dw_mdio_init(dev->name, dev); 736 priv->bus = miiphy_get_dev_by_name(dev->name); 737 738 ret = dw_phy_init(priv, dev); 739 debug("%s, ret=%d\n", __func__, ret); 740 741 return ret; 742 743 #ifdef CONFIG_CLK 744 clk_err: 745 ret = clk_release_all(priv->clocks, priv->clock_count); 746 if (ret) 747 pr_err("failed to disable all clocks\n"); 748 749 return err; 750 #endif 751 } 752 753 static int designware_eth_remove(struct udevice *dev) 754 { 755 struct dw_eth_dev *priv = dev_get_priv(dev); 756 757 free(priv->phydev); 758 mdio_unregister(priv->bus); 759 mdio_free(priv->bus); 760 761 #ifdef CONFIG_CLK 762 return clk_release_all(priv->clocks, priv->clock_count); 763 #else 764 return 0; 765 #endif 766 } 767 768 const struct eth_ops designware_eth_ops = { 769 .start = designware_eth_start, 770 .send = designware_eth_send, 771 .recv = designware_eth_recv, 772 .free_pkt = designware_eth_free_pkt, 773 .stop = designware_eth_stop, 774 .write_hwaddr = designware_eth_write_hwaddr, 775 }; 776 777 int designware_eth_ofdata_to_platdata(struct udevice *dev) 778 { 779 struct dw_eth_pdata *dw_pdata = dev_get_platdata(dev); 780 #ifdef CONFIG_DM_GPIO 781 struct dw_eth_dev *priv = dev_get_priv(dev); 782 #endif 783 struct eth_pdata *pdata = &dw_pdata->eth_pdata; 784 const char *phy_mode; 785 #ifdef CONFIG_DM_GPIO 786 int reset_flags = GPIOD_IS_OUT; 787 #endif 788 int ret = 0; 789 790 pdata->iobase = dev_read_addr(dev); 791 pdata->phy_interface = -1; 792 phy_mode = dev_read_string(dev, "phy-mode"); 793 if (phy_mode) 794 pdata->phy_interface = phy_get_interface_by_name(phy_mode); 795 if (pdata->phy_interface == -1) { 796 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode); 797 return -EINVAL; 798 } 799 800 pdata->max_speed = dev_read_u32_default(dev, "max-speed", 0); 801 802 #ifdef CONFIG_DM_GPIO 803 if (dev_read_bool(dev, "snps,reset-active-low")) 804 reset_flags |= GPIOD_ACTIVE_LOW; 805 806 ret = gpio_request_by_name(dev, "snps,reset-gpio", 0, 807 &priv->reset_gpio, reset_flags); 808 if (ret == 0) { 809 ret = dev_read_u32_array(dev, "snps,reset-delays-us", 810 dw_pdata->reset_delays, 3); 811 } else if (ret == -ENOENT) { 812 ret = 0; 813 } 814 #endif 815 816 return ret; 817 } 818 819 static const struct udevice_id designware_eth_ids[] = { 820 { .compatible = "allwinner,sun7i-a20-gmac" }, 821 { .compatible = "altr,socfpga-stmmac" }, 822 { .compatible = "amlogic,meson6-dwmac" }, 823 { .compatible = "amlogic,meson-gx-dwmac" }, 824 { .compatible = "st,stm32-dwmac" }, 825 { } 826 }; 827 828 U_BOOT_DRIVER(eth_designware) = { 829 .name = "eth_designware", 830 .id = UCLASS_ETH, 831 .of_match = designware_eth_ids, 832 .ofdata_to_platdata = designware_eth_ofdata_to_platdata, 833 .bind = designware_eth_bind, 834 .probe = designware_eth_probe, 835 .remove = designware_eth_remove, 836 .ops = &designware_eth_ops, 837 .priv_auto_alloc_size = sizeof(struct dw_eth_dev), 838 .platdata_auto_alloc_size = sizeof(struct dw_eth_pdata), 839 .flags = DM_FLAG_ALLOC_PRIV_DMA, 840 }; 841 842 static struct pci_device_id supported[] = { 843 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QRK_EMAC) }, 844 { } 845 }; 846 847 U_BOOT_PCI_DEVICE(eth_designware, supported); 848 #endif 849