1 /* 2 * (C) Copyright 2010 3 * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 /* 9 * Designware ethernet IP driver for U-Boot 10 */ 11 12 #include <common.h> 13 #include <dm.h> 14 #include <errno.h> 15 #include <miiphy.h> 16 #include <malloc.h> 17 #include <linux/compiler.h> 18 #include <linux/err.h> 19 #include <asm/io.h> 20 #include "designware.h" 21 22 DECLARE_GLOBAL_DATA_PTR; 23 24 #if !defined(CONFIG_PHYLIB) 25 # error "DesignWare Ether MAC requires PHYLIB - missing CONFIG_PHYLIB" 26 #endif 27 28 static int dw_mdio_read(struct mii_dev *bus, int addr, int devad, int reg) 29 { 30 struct eth_mac_regs *mac_p = bus->priv; 31 ulong start; 32 u16 miiaddr; 33 int timeout = CONFIG_MDIO_TIMEOUT; 34 35 miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) | 36 ((reg << MIIREGSHIFT) & MII_REGMSK); 37 38 writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr); 39 40 start = get_timer(0); 41 while (get_timer(start) < timeout) { 42 if (!(readl(&mac_p->miiaddr) & MII_BUSY)) 43 return readl(&mac_p->miidata); 44 udelay(10); 45 }; 46 47 return -ETIMEDOUT; 48 } 49 50 static int dw_mdio_write(struct mii_dev *bus, int addr, int devad, int reg, 51 u16 val) 52 { 53 struct eth_mac_regs *mac_p = bus->priv; 54 ulong start; 55 u16 miiaddr; 56 int ret = -ETIMEDOUT, timeout = CONFIG_MDIO_TIMEOUT; 57 58 writel(val, &mac_p->miidata); 59 miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) | 60 ((reg << MIIREGSHIFT) & MII_REGMSK) | MII_WRITE; 61 62 writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr); 63 64 start = get_timer(0); 65 while (get_timer(start) < timeout) { 66 if (!(readl(&mac_p->miiaddr) & MII_BUSY)) { 67 ret = 0; 68 break; 69 } 70 udelay(10); 71 }; 72 73 return ret; 74 } 75 76 static int dw_mdio_init(const char *name, struct eth_mac_regs *mac_regs_p) 77 { 78 struct mii_dev *bus = mdio_alloc(); 79 80 if (!bus) { 81 printf("Failed to allocate MDIO bus\n"); 82 return -ENOMEM; 83 } 84 85 bus->read = dw_mdio_read; 86 bus->write = dw_mdio_write; 87 snprintf(bus->name, sizeof(bus->name), name); 88 89 bus->priv = (void *)mac_regs_p; 90 91 return mdio_register(bus); 92 } 93 94 static void tx_descs_init(struct dw_eth_dev *priv) 95 { 96 struct eth_dma_regs *dma_p = priv->dma_regs_p; 97 struct dmamacdescr *desc_table_p = &priv->tx_mac_descrtable[0]; 98 char *txbuffs = &priv->txbuffs[0]; 99 struct dmamacdescr *desc_p; 100 u32 idx; 101 102 for (idx = 0; idx < CONFIG_TX_DESCR_NUM; idx++) { 103 desc_p = &desc_table_p[idx]; 104 desc_p->dmamac_addr = &txbuffs[idx * CONFIG_ETH_BUFSIZE]; 105 desc_p->dmamac_next = &desc_table_p[idx + 1]; 106 107 #if defined(CONFIG_DW_ALTDESCRIPTOR) 108 desc_p->txrx_status &= ~(DESC_TXSTS_TXINT | DESC_TXSTS_TXLAST | 109 DESC_TXSTS_TXFIRST | DESC_TXSTS_TXCRCDIS | \ 110 DESC_TXSTS_TXCHECKINSCTRL | \ 111 DESC_TXSTS_TXRINGEND | DESC_TXSTS_TXPADDIS); 112 113 desc_p->txrx_status |= DESC_TXSTS_TXCHAIN; 114 desc_p->dmamac_cntl = 0; 115 desc_p->txrx_status &= ~(DESC_TXSTS_MSK | DESC_TXSTS_OWNBYDMA); 116 #else 117 desc_p->dmamac_cntl = DESC_TXCTRL_TXCHAIN; 118 desc_p->txrx_status = 0; 119 #endif 120 } 121 122 /* Correcting the last pointer of the chain */ 123 desc_p->dmamac_next = &desc_table_p[0]; 124 125 /* Flush all Tx buffer descriptors at once */ 126 flush_dcache_range((unsigned int)priv->tx_mac_descrtable, 127 (unsigned int)priv->tx_mac_descrtable + 128 sizeof(priv->tx_mac_descrtable)); 129 130 writel((ulong)&desc_table_p[0], &dma_p->txdesclistaddr); 131 priv->tx_currdescnum = 0; 132 } 133 134 static void rx_descs_init(struct dw_eth_dev *priv) 135 { 136 struct eth_dma_regs *dma_p = priv->dma_regs_p; 137 struct dmamacdescr *desc_table_p = &priv->rx_mac_descrtable[0]; 138 char *rxbuffs = &priv->rxbuffs[0]; 139 struct dmamacdescr *desc_p; 140 u32 idx; 141 142 /* Before passing buffers to GMAC we need to make sure zeros 143 * written there right after "priv" structure allocation were 144 * flushed into RAM. 145 * Otherwise there's a chance to get some of them flushed in RAM when 146 * GMAC is already pushing data to RAM via DMA. This way incoming from 147 * GMAC data will be corrupted. */ 148 flush_dcache_range((unsigned int)rxbuffs, (unsigned int)rxbuffs + 149 RX_TOTAL_BUFSIZE); 150 151 for (idx = 0; idx < CONFIG_RX_DESCR_NUM; idx++) { 152 desc_p = &desc_table_p[idx]; 153 desc_p->dmamac_addr = &rxbuffs[idx * CONFIG_ETH_BUFSIZE]; 154 desc_p->dmamac_next = &desc_table_p[idx + 1]; 155 156 desc_p->dmamac_cntl = 157 (MAC_MAX_FRAME_SZ & DESC_RXCTRL_SIZE1MASK) | \ 158 DESC_RXCTRL_RXCHAIN; 159 160 desc_p->txrx_status = DESC_RXSTS_OWNBYDMA; 161 } 162 163 /* Correcting the last pointer of the chain */ 164 desc_p->dmamac_next = &desc_table_p[0]; 165 166 /* Flush all Rx buffer descriptors at once */ 167 flush_dcache_range((unsigned int)priv->rx_mac_descrtable, 168 (unsigned int)priv->rx_mac_descrtable + 169 sizeof(priv->rx_mac_descrtable)); 170 171 writel((ulong)&desc_table_p[0], &dma_p->rxdesclistaddr); 172 priv->rx_currdescnum = 0; 173 } 174 175 static int _dw_write_hwaddr(struct dw_eth_dev *priv, u8 *mac_id) 176 { 177 struct eth_mac_regs *mac_p = priv->mac_regs_p; 178 u32 macid_lo, macid_hi; 179 180 macid_lo = mac_id[0] + (mac_id[1] << 8) + (mac_id[2] << 16) + 181 (mac_id[3] << 24); 182 macid_hi = mac_id[4] + (mac_id[5] << 8); 183 184 writel(macid_hi, &mac_p->macaddr0hi); 185 writel(macid_lo, &mac_p->macaddr0lo); 186 187 return 0; 188 } 189 190 static void dw_adjust_link(struct eth_mac_regs *mac_p, 191 struct phy_device *phydev) 192 { 193 u32 conf = readl(&mac_p->conf) | FRAMEBURSTENABLE | DISABLERXOWN; 194 195 if (!phydev->link) { 196 printf("%s: No link.\n", phydev->dev->name); 197 return; 198 } 199 200 if (phydev->speed != 1000) 201 conf |= MII_PORTSELECT; 202 203 if (phydev->speed == 100) 204 conf |= FES_100; 205 206 if (phydev->duplex) 207 conf |= FULLDPLXMODE; 208 209 writel(conf, &mac_p->conf); 210 211 printf("Speed: %d, %s duplex%s\n", phydev->speed, 212 (phydev->duplex) ? "full" : "half", 213 (phydev->port == PORT_FIBRE) ? ", fiber mode" : ""); 214 } 215 216 static void _dw_eth_halt(struct dw_eth_dev *priv) 217 { 218 struct eth_mac_regs *mac_p = priv->mac_regs_p; 219 struct eth_dma_regs *dma_p = priv->dma_regs_p; 220 221 writel(readl(&mac_p->conf) & ~(RXENABLE | TXENABLE), &mac_p->conf); 222 writel(readl(&dma_p->opmode) & ~(RXSTART | TXSTART), &dma_p->opmode); 223 224 phy_shutdown(priv->phydev); 225 } 226 227 static int _dw_eth_init(struct dw_eth_dev *priv, u8 *enetaddr) 228 { 229 struct eth_mac_regs *mac_p = priv->mac_regs_p; 230 struct eth_dma_regs *dma_p = priv->dma_regs_p; 231 unsigned int start; 232 int ret; 233 234 writel(readl(&dma_p->busmode) | DMAMAC_SRST, &dma_p->busmode); 235 236 start = get_timer(0); 237 while (readl(&dma_p->busmode) & DMAMAC_SRST) { 238 if (get_timer(start) >= CONFIG_MACRESET_TIMEOUT) { 239 printf("DMA reset timeout\n"); 240 return -ETIMEDOUT; 241 } 242 243 mdelay(100); 244 }; 245 246 rx_descs_init(priv); 247 tx_descs_init(priv); 248 249 writel(FIXEDBURST | PRIORXTX_41 | DMA_PBL, &dma_p->busmode); 250 251 #ifndef CONFIG_DW_MAC_FORCE_THRESHOLD_MODE 252 writel(readl(&dma_p->opmode) | FLUSHTXFIFO | STOREFORWARD, 253 &dma_p->opmode); 254 #else 255 writel(readl(&dma_p->opmode) | FLUSHTXFIFO, 256 &dma_p->opmode); 257 #endif 258 259 writel(readl(&dma_p->opmode) | RXSTART | TXSTART, &dma_p->opmode); 260 261 #ifdef CONFIG_DW_AXI_BURST_LEN 262 writel((CONFIG_DW_AXI_BURST_LEN & 0x1FF >> 1), &dma_p->axibus); 263 #endif 264 265 /* Start up the PHY */ 266 ret = phy_startup(priv->phydev); 267 if (ret) { 268 printf("Could not initialize PHY %s\n", 269 priv->phydev->dev->name); 270 return ret; 271 } 272 273 dw_adjust_link(mac_p, priv->phydev); 274 275 if (!priv->phydev->link) 276 return -EIO; 277 278 writel(readl(&mac_p->conf) | RXENABLE | TXENABLE, &mac_p->conf); 279 280 return 0; 281 } 282 283 static int _dw_eth_send(struct dw_eth_dev *priv, void *packet, int length) 284 { 285 struct eth_dma_regs *dma_p = priv->dma_regs_p; 286 u32 desc_num = priv->tx_currdescnum; 287 struct dmamacdescr *desc_p = &priv->tx_mac_descrtable[desc_num]; 288 uint32_t desc_start = (uint32_t)desc_p; 289 uint32_t desc_end = desc_start + 290 roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN); 291 uint32_t data_start = (uint32_t)desc_p->dmamac_addr; 292 uint32_t data_end = data_start + 293 roundup(length, ARCH_DMA_MINALIGN); 294 /* 295 * Strictly we only need to invalidate the "txrx_status" field 296 * for the following check, but on some platforms we cannot 297 * invalidate only 4 bytes, so we flush the entire descriptor, 298 * which is 16 bytes in total. This is safe because the 299 * individual descriptors in the array are each aligned to 300 * ARCH_DMA_MINALIGN and padded appropriately. 301 */ 302 invalidate_dcache_range(desc_start, desc_end); 303 304 /* Check if the descriptor is owned by CPU */ 305 if (desc_p->txrx_status & DESC_TXSTS_OWNBYDMA) { 306 printf("CPU not owner of tx frame\n"); 307 return -EPERM; 308 } 309 310 memcpy(desc_p->dmamac_addr, packet, length); 311 312 /* Flush data to be sent */ 313 flush_dcache_range(data_start, data_end); 314 315 #if defined(CONFIG_DW_ALTDESCRIPTOR) 316 desc_p->txrx_status |= DESC_TXSTS_TXFIRST | DESC_TXSTS_TXLAST; 317 desc_p->dmamac_cntl |= (length << DESC_TXCTRL_SIZE1SHFT) & \ 318 DESC_TXCTRL_SIZE1MASK; 319 320 desc_p->txrx_status &= ~(DESC_TXSTS_MSK); 321 desc_p->txrx_status |= DESC_TXSTS_OWNBYDMA; 322 #else 323 desc_p->dmamac_cntl |= ((length << DESC_TXCTRL_SIZE1SHFT) & \ 324 DESC_TXCTRL_SIZE1MASK) | DESC_TXCTRL_TXLAST | \ 325 DESC_TXCTRL_TXFIRST; 326 327 desc_p->txrx_status = DESC_TXSTS_OWNBYDMA; 328 #endif 329 330 /* Flush modified buffer descriptor */ 331 flush_dcache_range(desc_start, desc_end); 332 333 /* Test the wrap-around condition. */ 334 if (++desc_num >= CONFIG_TX_DESCR_NUM) 335 desc_num = 0; 336 337 priv->tx_currdescnum = desc_num; 338 339 /* Start the transmission */ 340 writel(POLL_DATA, &dma_p->txpolldemand); 341 342 return 0; 343 } 344 345 static int _dw_eth_recv(struct dw_eth_dev *priv, uchar **packetp) 346 { 347 u32 status, desc_num = priv->rx_currdescnum; 348 struct dmamacdescr *desc_p = &priv->rx_mac_descrtable[desc_num]; 349 int length = -EAGAIN; 350 uint32_t desc_start = (uint32_t)desc_p; 351 uint32_t desc_end = desc_start + 352 roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN); 353 uint32_t data_start = (uint32_t)desc_p->dmamac_addr; 354 uint32_t data_end; 355 356 /* Invalidate entire buffer descriptor */ 357 invalidate_dcache_range(desc_start, desc_end); 358 359 status = desc_p->txrx_status; 360 361 /* Check if the owner is the CPU */ 362 if (!(status & DESC_RXSTS_OWNBYDMA)) { 363 364 length = (status & DESC_RXSTS_FRMLENMSK) >> \ 365 DESC_RXSTS_FRMLENSHFT; 366 367 /* Invalidate received data */ 368 data_end = data_start + roundup(length, ARCH_DMA_MINALIGN); 369 invalidate_dcache_range(data_start, data_end); 370 *packetp = desc_p->dmamac_addr; 371 } 372 373 return length; 374 } 375 376 static int _dw_free_pkt(struct dw_eth_dev *priv) 377 { 378 u32 desc_num = priv->rx_currdescnum; 379 struct dmamacdescr *desc_p = &priv->rx_mac_descrtable[desc_num]; 380 uint32_t desc_start = (uint32_t)desc_p; 381 uint32_t desc_end = desc_start + 382 roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN); 383 384 /* 385 * Make the current descriptor valid again and go to 386 * the next one 387 */ 388 desc_p->txrx_status |= DESC_RXSTS_OWNBYDMA; 389 390 /* Flush only status field - others weren't changed */ 391 flush_dcache_range(desc_start, desc_end); 392 393 /* Test the wrap-around condition. */ 394 if (++desc_num >= CONFIG_RX_DESCR_NUM) 395 desc_num = 0; 396 priv->rx_currdescnum = desc_num; 397 398 return 0; 399 } 400 401 static int dw_phy_init(struct dw_eth_dev *priv, void *dev) 402 { 403 struct phy_device *phydev; 404 int mask = 0xffffffff; 405 406 #ifdef CONFIG_PHY_ADDR 407 mask = 1 << CONFIG_PHY_ADDR; 408 #endif 409 410 phydev = phy_find_by_mask(priv->bus, mask, priv->interface); 411 if (!phydev) 412 return -ENODEV; 413 414 phy_connect_dev(phydev, dev); 415 416 phydev->supported &= PHY_GBIT_FEATURES; 417 phydev->advertising = phydev->supported; 418 419 priv->phydev = phydev; 420 phy_config(phydev); 421 422 return 0; 423 } 424 425 #ifndef CONFIG_DM_ETH 426 static int dw_eth_init(struct eth_device *dev, bd_t *bis) 427 { 428 return _dw_eth_init(dev->priv, dev->enetaddr); 429 } 430 431 static int dw_eth_send(struct eth_device *dev, void *packet, int length) 432 { 433 return _dw_eth_send(dev->priv, packet, length); 434 } 435 436 static int dw_eth_recv(struct eth_device *dev) 437 { 438 uchar *packet; 439 int length; 440 441 length = _dw_eth_recv(dev->priv, &packet); 442 if (length == -EAGAIN) 443 return 0; 444 net_process_received_packet(packet, length); 445 446 _dw_free_pkt(dev->priv); 447 448 return 0; 449 } 450 451 static void dw_eth_halt(struct eth_device *dev) 452 { 453 return _dw_eth_halt(dev->priv); 454 } 455 456 static int dw_write_hwaddr(struct eth_device *dev) 457 { 458 return _dw_write_hwaddr(dev->priv, dev->enetaddr); 459 } 460 461 int designware_initialize(ulong base_addr, u32 interface) 462 { 463 struct eth_device *dev; 464 struct dw_eth_dev *priv; 465 466 dev = (struct eth_device *) malloc(sizeof(struct eth_device)); 467 if (!dev) 468 return -ENOMEM; 469 470 /* 471 * Since the priv structure contains the descriptors which need a strict 472 * buswidth alignment, memalign is used to allocate memory 473 */ 474 priv = (struct dw_eth_dev *) memalign(ARCH_DMA_MINALIGN, 475 sizeof(struct dw_eth_dev)); 476 if (!priv) { 477 free(dev); 478 return -ENOMEM; 479 } 480 481 memset(dev, 0, sizeof(struct eth_device)); 482 memset(priv, 0, sizeof(struct dw_eth_dev)); 483 484 sprintf(dev->name, "dwmac.%lx", base_addr); 485 dev->iobase = (int)base_addr; 486 dev->priv = priv; 487 488 priv->dev = dev; 489 priv->mac_regs_p = (struct eth_mac_regs *)base_addr; 490 priv->dma_regs_p = (struct eth_dma_regs *)(base_addr + 491 DW_DMA_BASE_OFFSET); 492 493 dev->init = dw_eth_init; 494 dev->send = dw_eth_send; 495 dev->recv = dw_eth_recv; 496 dev->halt = dw_eth_halt; 497 dev->write_hwaddr = dw_write_hwaddr; 498 499 eth_register(dev); 500 501 priv->interface = interface; 502 503 dw_mdio_init(dev->name, priv->mac_regs_p); 504 priv->bus = miiphy_get_dev_by_name(dev->name); 505 506 return dw_phy_init(priv, dev); 507 } 508 #endif 509 510 #ifdef CONFIG_DM_ETH 511 static int designware_eth_start(struct udevice *dev) 512 { 513 struct eth_pdata *pdata = dev_get_platdata(dev); 514 515 return _dw_eth_init(dev->priv, pdata->enetaddr); 516 } 517 518 static int designware_eth_send(struct udevice *dev, void *packet, int length) 519 { 520 struct dw_eth_dev *priv = dev_get_priv(dev); 521 522 return _dw_eth_send(priv, packet, length); 523 } 524 525 static int designware_eth_recv(struct udevice *dev, uchar **packetp) 526 { 527 struct dw_eth_dev *priv = dev_get_priv(dev); 528 529 return _dw_eth_recv(priv, packetp); 530 } 531 532 static int designware_eth_free_pkt(struct udevice *dev, uchar *packet, 533 int length) 534 { 535 struct dw_eth_dev *priv = dev_get_priv(dev); 536 537 return _dw_free_pkt(priv); 538 } 539 540 static void designware_eth_stop(struct udevice *dev) 541 { 542 struct dw_eth_dev *priv = dev_get_priv(dev); 543 544 return _dw_eth_halt(priv); 545 } 546 547 static int designware_eth_write_hwaddr(struct udevice *dev) 548 { 549 struct eth_pdata *pdata = dev_get_platdata(dev); 550 struct dw_eth_dev *priv = dev_get_priv(dev); 551 552 return _dw_write_hwaddr(priv, pdata->enetaddr); 553 } 554 555 static int designware_eth_probe(struct udevice *dev) 556 { 557 struct eth_pdata *pdata = dev_get_platdata(dev); 558 struct dw_eth_dev *priv = dev_get_priv(dev); 559 int ret; 560 561 debug("%s, iobase=%lx, priv=%p\n", __func__, pdata->iobase, priv); 562 priv->mac_regs_p = (struct eth_mac_regs *)pdata->iobase; 563 priv->dma_regs_p = (struct eth_dma_regs *)(pdata->iobase + 564 DW_DMA_BASE_OFFSET); 565 priv->interface = pdata->phy_interface; 566 567 dw_mdio_init(dev->name, priv->mac_regs_p); 568 priv->bus = miiphy_get_dev_by_name(dev->name); 569 570 ret = dw_phy_init(priv, dev); 571 debug("%s, ret=%d\n", __func__, ret); 572 573 return ret; 574 } 575 576 static const struct eth_ops designware_eth_ops = { 577 .start = designware_eth_start, 578 .send = designware_eth_send, 579 .recv = designware_eth_recv, 580 .free_pkt = designware_eth_free_pkt, 581 .stop = designware_eth_stop, 582 .write_hwaddr = designware_eth_write_hwaddr, 583 }; 584 585 static int designware_eth_ofdata_to_platdata(struct udevice *dev) 586 { 587 struct eth_pdata *pdata = dev_get_platdata(dev); 588 const char *phy_mode; 589 590 pdata->iobase = dev_get_addr(dev); 591 pdata->phy_interface = -1; 592 phy_mode = fdt_getprop(gd->fdt_blob, dev->of_offset, "phy-mode", NULL); 593 if (phy_mode) 594 pdata->phy_interface = phy_get_interface_by_name(phy_mode); 595 if (pdata->phy_interface == -1) { 596 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode); 597 return -EINVAL; 598 } 599 600 return 0; 601 } 602 603 static const struct udevice_id designware_eth_ids[] = { 604 { .compatible = "allwinner,sun7i-a20-gmac" }, 605 { } 606 }; 607 608 U_BOOT_DRIVER(eth_sandbox) = { 609 .name = "eth_designware", 610 .id = UCLASS_ETH, 611 .of_match = designware_eth_ids, 612 .ofdata_to_platdata = designware_eth_ofdata_to_platdata, 613 .probe = designware_eth_probe, 614 .ops = &designware_eth_ops, 615 .priv_auto_alloc_size = sizeof(struct dw_eth_dev), 616 .platdata_auto_alloc_size = sizeof(struct eth_pdata), 617 .flags = DM_FLAG_ALLOC_PRIV_DMA, 618 }; 619 #endif 620