1 /* 2 * (C) Copyright 2010 3 * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 /* 9 * Designware ethernet IP driver for U-Boot 10 */ 11 12 #include <common.h> 13 #include <dm.h> 14 #include <errno.h> 15 #include <miiphy.h> 16 #include <malloc.h> 17 #include <linux/compiler.h> 18 #include <linux/err.h> 19 #include <asm/io.h> 20 #include "designware.h" 21 22 DECLARE_GLOBAL_DATA_PTR; 23 24 #if !defined(CONFIG_PHYLIB) 25 # error "DesignWare Ether MAC requires PHYLIB - missing CONFIG_PHYLIB" 26 #endif 27 28 static int dw_mdio_read(struct mii_dev *bus, int addr, int devad, int reg) 29 { 30 struct eth_mac_regs *mac_p = bus->priv; 31 ulong start; 32 u16 miiaddr; 33 int timeout = CONFIG_MDIO_TIMEOUT; 34 35 miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) | 36 ((reg << MIIREGSHIFT) & MII_REGMSK); 37 38 writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr); 39 40 start = get_timer(0); 41 while (get_timer(start) < timeout) { 42 if (!(readl(&mac_p->miiaddr) & MII_BUSY)) 43 return readl(&mac_p->miidata); 44 udelay(10); 45 }; 46 47 return -ETIMEDOUT; 48 } 49 50 static int dw_mdio_write(struct mii_dev *bus, int addr, int devad, int reg, 51 u16 val) 52 { 53 struct eth_mac_regs *mac_p = bus->priv; 54 ulong start; 55 u16 miiaddr; 56 int ret = -ETIMEDOUT, timeout = CONFIG_MDIO_TIMEOUT; 57 58 writel(val, &mac_p->miidata); 59 miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) | 60 ((reg << MIIREGSHIFT) & MII_REGMSK) | MII_WRITE; 61 62 writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr); 63 64 start = get_timer(0); 65 while (get_timer(start) < timeout) { 66 if (!(readl(&mac_p->miiaddr) & MII_BUSY)) { 67 ret = 0; 68 break; 69 } 70 udelay(10); 71 }; 72 73 return ret; 74 } 75 76 static int dw_mdio_init(const char *name, struct eth_mac_regs *mac_regs_p) 77 { 78 struct mii_dev *bus = mdio_alloc(); 79 80 if (!bus) { 81 printf("Failed to allocate MDIO bus\n"); 82 return -ENOMEM; 83 } 84 85 bus->read = dw_mdio_read; 86 bus->write = dw_mdio_write; 87 snprintf(bus->name, sizeof(bus->name), name); 88 89 bus->priv = (void *)mac_regs_p; 90 91 return mdio_register(bus); 92 } 93 94 static void tx_descs_init(struct dw_eth_dev *priv) 95 { 96 struct eth_dma_regs *dma_p = priv->dma_regs_p; 97 struct dmamacdescr *desc_table_p = &priv->tx_mac_descrtable[0]; 98 char *txbuffs = &priv->txbuffs[0]; 99 struct dmamacdescr *desc_p; 100 u32 idx; 101 102 for (idx = 0; idx < CONFIG_TX_DESCR_NUM; idx++) { 103 desc_p = &desc_table_p[idx]; 104 desc_p->dmamac_addr = &txbuffs[idx * CONFIG_ETH_BUFSIZE]; 105 desc_p->dmamac_next = &desc_table_p[idx + 1]; 106 107 #if defined(CONFIG_DW_ALTDESCRIPTOR) 108 desc_p->txrx_status &= ~(DESC_TXSTS_TXINT | DESC_TXSTS_TXLAST | 109 DESC_TXSTS_TXFIRST | DESC_TXSTS_TXCRCDIS | \ 110 DESC_TXSTS_TXCHECKINSCTRL | \ 111 DESC_TXSTS_TXRINGEND | DESC_TXSTS_TXPADDIS); 112 113 desc_p->txrx_status |= DESC_TXSTS_TXCHAIN; 114 desc_p->dmamac_cntl = 0; 115 desc_p->txrx_status &= ~(DESC_TXSTS_MSK | DESC_TXSTS_OWNBYDMA); 116 #else 117 desc_p->dmamac_cntl = DESC_TXCTRL_TXCHAIN; 118 desc_p->txrx_status = 0; 119 #endif 120 } 121 122 /* Correcting the last pointer of the chain */ 123 desc_p->dmamac_next = &desc_table_p[0]; 124 125 /* Flush all Tx buffer descriptors at once */ 126 flush_dcache_range((unsigned int)priv->tx_mac_descrtable, 127 (unsigned int)priv->tx_mac_descrtable + 128 sizeof(priv->tx_mac_descrtable)); 129 130 writel((ulong)&desc_table_p[0], &dma_p->txdesclistaddr); 131 priv->tx_currdescnum = 0; 132 } 133 134 static void rx_descs_init(struct dw_eth_dev *priv) 135 { 136 struct eth_dma_regs *dma_p = priv->dma_regs_p; 137 struct dmamacdescr *desc_table_p = &priv->rx_mac_descrtable[0]; 138 char *rxbuffs = &priv->rxbuffs[0]; 139 struct dmamacdescr *desc_p; 140 u32 idx; 141 142 /* Before passing buffers to GMAC we need to make sure zeros 143 * written there right after "priv" structure allocation were 144 * flushed into RAM. 145 * Otherwise there's a chance to get some of them flushed in RAM when 146 * GMAC is already pushing data to RAM via DMA. This way incoming from 147 * GMAC data will be corrupted. */ 148 flush_dcache_range((unsigned int)rxbuffs, (unsigned int)rxbuffs + 149 RX_TOTAL_BUFSIZE); 150 151 for (idx = 0; idx < CONFIG_RX_DESCR_NUM; idx++) { 152 desc_p = &desc_table_p[idx]; 153 desc_p->dmamac_addr = &rxbuffs[idx * CONFIG_ETH_BUFSIZE]; 154 desc_p->dmamac_next = &desc_table_p[idx + 1]; 155 156 desc_p->dmamac_cntl = 157 (MAC_MAX_FRAME_SZ & DESC_RXCTRL_SIZE1MASK) | \ 158 DESC_RXCTRL_RXCHAIN; 159 160 desc_p->txrx_status = DESC_RXSTS_OWNBYDMA; 161 } 162 163 /* Correcting the last pointer of the chain */ 164 desc_p->dmamac_next = &desc_table_p[0]; 165 166 /* Flush all Rx buffer descriptors at once */ 167 flush_dcache_range((unsigned int)priv->rx_mac_descrtable, 168 (unsigned int)priv->rx_mac_descrtable + 169 sizeof(priv->rx_mac_descrtable)); 170 171 writel((ulong)&desc_table_p[0], &dma_p->rxdesclistaddr); 172 priv->rx_currdescnum = 0; 173 } 174 175 static int _dw_write_hwaddr(struct dw_eth_dev *priv, u8 *mac_id) 176 { 177 struct eth_mac_regs *mac_p = priv->mac_regs_p; 178 u32 macid_lo, macid_hi; 179 180 macid_lo = mac_id[0] + (mac_id[1] << 8) + (mac_id[2] << 16) + 181 (mac_id[3] << 24); 182 macid_hi = mac_id[4] + (mac_id[5] << 8); 183 184 writel(macid_hi, &mac_p->macaddr0hi); 185 writel(macid_lo, &mac_p->macaddr0lo); 186 187 return 0; 188 } 189 190 static void dw_adjust_link(struct eth_mac_regs *mac_p, 191 struct phy_device *phydev) 192 { 193 u32 conf = readl(&mac_p->conf) | FRAMEBURSTENABLE | DISABLERXOWN; 194 195 if (!phydev->link) { 196 printf("%s: No link.\n", phydev->dev->name); 197 return; 198 } 199 200 if (phydev->speed != 1000) 201 conf |= MII_PORTSELECT; 202 203 if (phydev->speed == 100) 204 conf |= FES_100; 205 206 if (phydev->duplex) 207 conf |= FULLDPLXMODE; 208 209 writel(conf, &mac_p->conf); 210 211 printf("Speed: %d, %s duplex%s\n", phydev->speed, 212 (phydev->duplex) ? "full" : "half", 213 (phydev->port == PORT_FIBRE) ? ", fiber mode" : ""); 214 } 215 216 static void _dw_eth_halt(struct dw_eth_dev *priv) 217 { 218 struct eth_mac_regs *mac_p = priv->mac_regs_p; 219 struct eth_dma_regs *dma_p = priv->dma_regs_p; 220 221 writel(readl(&mac_p->conf) & ~(RXENABLE | TXENABLE), &mac_p->conf); 222 writel(readl(&dma_p->opmode) & ~(RXSTART | TXSTART), &dma_p->opmode); 223 224 phy_shutdown(priv->phydev); 225 } 226 227 static int _dw_eth_init(struct dw_eth_dev *priv, u8 *enetaddr) 228 { 229 struct eth_mac_regs *mac_p = priv->mac_regs_p; 230 struct eth_dma_regs *dma_p = priv->dma_regs_p; 231 unsigned int start; 232 int ret; 233 234 writel(readl(&dma_p->busmode) | DMAMAC_SRST, &dma_p->busmode); 235 236 start = get_timer(0); 237 while (readl(&dma_p->busmode) & DMAMAC_SRST) { 238 if (get_timer(start) >= CONFIG_MACRESET_TIMEOUT) { 239 printf("DMA reset timeout\n"); 240 return -ETIMEDOUT; 241 } 242 243 mdelay(100); 244 }; 245 246 /* 247 * Soft reset above clears HW address registers. 248 * So we have to set it here once again. 249 */ 250 _dw_write_hwaddr(priv, enetaddr); 251 252 rx_descs_init(priv); 253 tx_descs_init(priv); 254 255 writel(FIXEDBURST | PRIORXTX_41 | DMA_PBL, &dma_p->busmode); 256 257 #ifndef CONFIG_DW_MAC_FORCE_THRESHOLD_MODE 258 writel(readl(&dma_p->opmode) | FLUSHTXFIFO | STOREFORWARD, 259 &dma_p->opmode); 260 #else 261 writel(readl(&dma_p->opmode) | FLUSHTXFIFO, 262 &dma_p->opmode); 263 #endif 264 265 writel(readl(&dma_p->opmode) | RXSTART | TXSTART, &dma_p->opmode); 266 267 #ifdef CONFIG_DW_AXI_BURST_LEN 268 writel((CONFIG_DW_AXI_BURST_LEN & 0x1FF >> 1), &dma_p->axibus); 269 #endif 270 271 /* Start up the PHY */ 272 ret = phy_startup(priv->phydev); 273 if (ret) { 274 printf("Could not initialize PHY %s\n", 275 priv->phydev->dev->name); 276 return ret; 277 } 278 279 dw_adjust_link(mac_p, priv->phydev); 280 281 if (!priv->phydev->link) 282 return -EIO; 283 284 writel(readl(&mac_p->conf) | RXENABLE | TXENABLE, &mac_p->conf); 285 286 return 0; 287 } 288 289 static int _dw_eth_send(struct dw_eth_dev *priv, void *packet, int length) 290 { 291 struct eth_dma_regs *dma_p = priv->dma_regs_p; 292 u32 desc_num = priv->tx_currdescnum; 293 struct dmamacdescr *desc_p = &priv->tx_mac_descrtable[desc_num]; 294 uint32_t desc_start = (uint32_t)desc_p; 295 uint32_t desc_end = desc_start + 296 roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN); 297 uint32_t data_start = (uint32_t)desc_p->dmamac_addr; 298 uint32_t data_end = data_start + 299 roundup(length, ARCH_DMA_MINALIGN); 300 /* 301 * Strictly we only need to invalidate the "txrx_status" field 302 * for the following check, but on some platforms we cannot 303 * invalidate only 4 bytes, so we flush the entire descriptor, 304 * which is 16 bytes in total. This is safe because the 305 * individual descriptors in the array are each aligned to 306 * ARCH_DMA_MINALIGN and padded appropriately. 307 */ 308 invalidate_dcache_range(desc_start, desc_end); 309 310 /* Check if the descriptor is owned by CPU */ 311 if (desc_p->txrx_status & DESC_TXSTS_OWNBYDMA) { 312 printf("CPU not owner of tx frame\n"); 313 return -EPERM; 314 } 315 316 memcpy(desc_p->dmamac_addr, packet, length); 317 318 /* Flush data to be sent */ 319 flush_dcache_range(data_start, data_end); 320 321 #if defined(CONFIG_DW_ALTDESCRIPTOR) 322 desc_p->txrx_status |= DESC_TXSTS_TXFIRST | DESC_TXSTS_TXLAST; 323 desc_p->dmamac_cntl |= (length << DESC_TXCTRL_SIZE1SHFT) & \ 324 DESC_TXCTRL_SIZE1MASK; 325 326 desc_p->txrx_status &= ~(DESC_TXSTS_MSK); 327 desc_p->txrx_status |= DESC_TXSTS_OWNBYDMA; 328 #else 329 desc_p->dmamac_cntl |= ((length << DESC_TXCTRL_SIZE1SHFT) & \ 330 DESC_TXCTRL_SIZE1MASK) | DESC_TXCTRL_TXLAST | \ 331 DESC_TXCTRL_TXFIRST; 332 333 desc_p->txrx_status = DESC_TXSTS_OWNBYDMA; 334 #endif 335 336 /* Flush modified buffer descriptor */ 337 flush_dcache_range(desc_start, desc_end); 338 339 /* Test the wrap-around condition. */ 340 if (++desc_num >= CONFIG_TX_DESCR_NUM) 341 desc_num = 0; 342 343 priv->tx_currdescnum = desc_num; 344 345 /* Start the transmission */ 346 writel(POLL_DATA, &dma_p->txpolldemand); 347 348 return 0; 349 } 350 351 static int _dw_eth_recv(struct dw_eth_dev *priv, uchar **packetp) 352 { 353 u32 status, desc_num = priv->rx_currdescnum; 354 struct dmamacdescr *desc_p = &priv->rx_mac_descrtable[desc_num]; 355 int length = -EAGAIN; 356 uint32_t desc_start = (uint32_t)desc_p; 357 uint32_t desc_end = desc_start + 358 roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN); 359 uint32_t data_start = (uint32_t)desc_p->dmamac_addr; 360 uint32_t data_end; 361 362 /* Invalidate entire buffer descriptor */ 363 invalidate_dcache_range(desc_start, desc_end); 364 365 status = desc_p->txrx_status; 366 367 /* Check if the owner is the CPU */ 368 if (!(status & DESC_RXSTS_OWNBYDMA)) { 369 370 length = (status & DESC_RXSTS_FRMLENMSK) >> \ 371 DESC_RXSTS_FRMLENSHFT; 372 373 /* Invalidate received data */ 374 data_end = data_start + roundup(length, ARCH_DMA_MINALIGN); 375 invalidate_dcache_range(data_start, data_end); 376 *packetp = desc_p->dmamac_addr; 377 } 378 379 return length; 380 } 381 382 static int _dw_free_pkt(struct dw_eth_dev *priv) 383 { 384 u32 desc_num = priv->rx_currdescnum; 385 struct dmamacdescr *desc_p = &priv->rx_mac_descrtable[desc_num]; 386 uint32_t desc_start = (uint32_t)desc_p; 387 uint32_t desc_end = desc_start + 388 roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN); 389 390 /* 391 * Make the current descriptor valid again and go to 392 * the next one 393 */ 394 desc_p->txrx_status |= DESC_RXSTS_OWNBYDMA; 395 396 /* Flush only status field - others weren't changed */ 397 flush_dcache_range(desc_start, desc_end); 398 399 /* Test the wrap-around condition. */ 400 if (++desc_num >= CONFIG_RX_DESCR_NUM) 401 desc_num = 0; 402 priv->rx_currdescnum = desc_num; 403 404 return 0; 405 } 406 407 static int dw_phy_init(struct dw_eth_dev *priv, void *dev) 408 { 409 struct phy_device *phydev; 410 int mask = 0xffffffff; 411 412 #ifdef CONFIG_PHY_ADDR 413 mask = 1 << CONFIG_PHY_ADDR; 414 #endif 415 416 phydev = phy_find_by_mask(priv->bus, mask, priv->interface); 417 if (!phydev) 418 return -ENODEV; 419 420 phy_connect_dev(phydev, dev); 421 422 phydev->supported &= PHY_GBIT_FEATURES; 423 phydev->advertising = phydev->supported; 424 425 priv->phydev = phydev; 426 phy_config(phydev); 427 428 return 0; 429 } 430 431 #ifndef CONFIG_DM_ETH 432 static int dw_eth_init(struct eth_device *dev, bd_t *bis) 433 { 434 return _dw_eth_init(dev->priv, dev->enetaddr); 435 } 436 437 static int dw_eth_send(struct eth_device *dev, void *packet, int length) 438 { 439 return _dw_eth_send(dev->priv, packet, length); 440 } 441 442 static int dw_eth_recv(struct eth_device *dev) 443 { 444 uchar *packet; 445 int length; 446 447 length = _dw_eth_recv(dev->priv, &packet); 448 if (length == -EAGAIN) 449 return 0; 450 net_process_received_packet(packet, length); 451 452 _dw_free_pkt(dev->priv); 453 454 return 0; 455 } 456 457 static void dw_eth_halt(struct eth_device *dev) 458 { 459 return _dw_eth_halt(dev->priv); 460 } 461 462 static int dw_write_hwaddr(struct eth_device *dev) 463 { 464 return _dw_write_hwaddr(dev->priv, dev->enetaddr); 465 } 466 467 int designware_initialize(ulong base_addr, u32 interface) 468 { 469 struct eth_device *dev; 470 struct dw_eth_dev *priv; 471 472 dev = (struct eth_device *) malloc(sizeof(struct eth_device)); 473 if (!dev) 474 return -ENOMEM; 475 476 /* 477 * Since the priv structure contains the descriptors which need a strict 478 * buswidth alignment, memalign is used to allocate memory 479 */ 480 priv = (struct dw_eth_dev *) memalign(ARCH_DMA_MINALIGN, 481 sizeof(struct dw_eth_dev)); 482 if (!priv) { 483 free(dev); 484 return -ENOMEM; 485 } 486 487 memset(dev, 0, sizeof(struct eth_device)); 488 memset(priv, 0, sizeof(struct dw_eth_dev)); 489 490 sprintf(dev->name, "dwmac.%lx", base_addr); 491 dev->iobase = (int)base_addr; 492 dev->priv = priv; 493 494 priv->dev = dev; 495 priv->mac_regs_p = (struct eth_mac_regs *)base_addr; 496 priv->dma_regs_p = (struct eth_dma_regs *)(base_addr + 497 DW_DMA_BASE_OFFSET); 498 499 dev->init = dw_eth_init; 500 dev->send = dw_eth_send; 501 dev->recv = dw_eth_recv; 502 dev->halt = dw_eth_halt; 503 dev->write_hwaddr = dw_write_hwaddr; 504 505 eth_register(dev); 506 507 priv->interface = interface; 508 509 dw_mdio_init(dev->name, priv->mac_regs_p); 510 priv->bus = miiphy_get_dev_by_name(dev->name); 511 512 return dw_phy_init(priv, dev); 513 } 514 #endif 515 516 #ifdef CONFIG_DM_ETH 517 static int designware_eth_start(struct udevice *dev) 518 { 519 struct eth_pdata *pdata = dev_get_platdata(dev); 520 521 return _dw_eth_init(dev->priv, pdata->enetaddr); 522 } 523 524 static int designware_eth_send(struct udevice *dev, void *packet, int length) 525 { 526 struct dw_eth_dev *priv = dev_get_priv(dev); 527 528 return _dw_eth_send(priv, packet, length); 529 } 530 531 static int designware_eth_recv(struct udevice *dev, int flags, uchar **packetp) 532 { 533 struct dw_eth_dev *priv = dev_get_priv(dev); 534 535 return _dw_eth_recv(priv, packetp); 536 } 537 538 static int designware_eth_free_pkt(struct udevice *dev, uchar *packet, 539 int length) 540 { 541 struct dw_eth_dev *priv = dev_get_priv(dev); 542 543 return _dw_free_pkt(priv); 544 } 545 546 static void designware_eth_stop(struct udevice *dev) 547 { 548 struct dw_eth_dev *priv = dev_get_priv(dev); 549 550 return _dw_eth_halt(priv); 551 } 552 553 static int designware_eth_write_hwaddr(struct udevice *dev) 554 { 555 struct eth_pdata *pdata = dev_get_platdata(dev); 556 struct dw_eth_dev *priv = dev_get_priv(dev); 557 558 return _dw_write_hwaddr(priv, pdata->enetaddr); 559 } 560 561 static int designware_eth_probe(struct udevice *dev) 562 { 563 struct eth_pdata *pdata = dev_get_platdata(dev); 564 struct dw_eth_dev *priv = dev_get_priv(dev); 565 u32 iobase = pdata->iobase; 566 int ret; 567 568 debug("%s, iobase=%x, priv=%p\n", __func__, iobase, priv); 569 priv->mac_regs_p = (struct eth_mac_regs *)iobase; 570 priv->dma_regs_p = (struct eth_dma_regs *)(iobase + DW_DMA_BASE_OFFSET); 571 priv->interface = pdata->phy_interface; 572 573 dw_mdio_init(dev->name, priv->mac_regs_p); 574 priv->bus = miiphy_get_dev_by_name(dev->name); 575 576 ret = dw_phy_init(priv, dev); 577 debug("%s, ret=%d\n", __func__, ret); 578 579 return ret; 580 } 581 582 static const struct eth_ops designware_eth_ops = { 583 .start = designware_eth_start, 584 .send = designware_eth_send, 585 .recv = designware_eth_recv, 586 .free_pkt = designware_eth_free_pkt, 587 .stop = designware_eth_stop, 588 .write_hwaddr = designware_eth_write_hwaddr, 589 }; 590 591 static int designware_eth_ofdata_to_platdata(struct udevice *dev) 592 { 593 struct eth_pdata *pdata = dev_get_platdata(dev); 594 const char *phy_mode; 595 596 pdata->iobase = dev_get_addr(dev); 597 pdata->phy_interface = -1; 598 phy_mode = fdt_getprop(gd->fdt_blob, dev->of_offset, "phy-mode", NULL); 599 if (phy_mode) 600 pdata->phy_interface = phy_get_interface_by_name(phy_mode); 601 if (pdata->phy_interface == -1) { 602 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode); 603 return -EINVAL; 604 } 605 606 return 0; 607 } 608 609 static const struct udevice_id designware_eth_ids[] = { 610 { .compatible = "allwinner,sun7i-a20-gmac" }, 611 { .compatible = "altr,socfpga-stmmac" }, 612 { } 613 }; 614 615 U_BOOT_DRIVER(eth_designware) = { 616 .name = "eth_designware", 617 .id = UCLASS_ETH, 618 .of_match = designware_eth_ids, 619 .ofdata_to_platdata = designware_eth_ofdata_to_platdata, 620 .probe = designware_eth_probe, 621 .ops = &designware_eth_ops, 622 .priv_auto_alloc_size = sizeof(struct dw_eth_dev), 623 .platdata_auto_alloc_size = sizeof(struct eth_pdata), 624 .flags = DM_FLAG_ALLOC_PRIV_DMA, 625 }; 626 #endif 627