1 /* 2 * (C) Copyright 2010 3 * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24 /* 25 * Designware ethernet IP driver for u-boot 26 */ 27 28 #include <common.h> 29 #include <miiphy.h> 30 #include <malloc.h> 31 #include <linux/err.h> 32 #include <asm/io.h> 33 #include "designware.h" 34 35 static int configure_phy(struct eth_device *dev); 36 37 static void tx_descs_init(struct eth_device *dev) 38 { 39 struct dw_eth_dev *priv = dev->priv; 40 struct eth_dma_regs *dma_p = priv->dma_regs_p; 41 struct dmamacdescr *desc_table_p = &priv->tx_mac_descrtable[0]; 42 char *txbuffs = &priv->txbuffs[0]; 43 struct dmamacdescr *desc_p; 44 u32 idx; 45 46 for (idx = 0; idx < CONFIG_TX_DESCR_NUM; idx++) { 47 desc_p = &desc_table_p[idx]; 48 desc_p->dmamac_addr = &txbuffs[idx * CONFIG_ETH_BUFSIZE]; 49 desc_p->dmamac_next = &desc_table_p[idx + 1]; 50 51 #if defined(CONFIG_DW_ALTDESCRIPTOR) 52 desc_p->txrx_status &= ~(DESC_TXSTS_TXINT | DESC_TXSTS_TXLAST | 53 DESC_TXSTS_TXFIRST | DESC_TXSTS_TXCRCDIS | \ 54 DESC_TXSTS_TXCHECKINSCTRL | \ 55 DESC_TXSTS_TXRINGEND | DESC_TXSTS_TXPADDIS); 56 57 desc_p->txrx_status |= DESC_TXSTS_TXCHAIN; 58 desc_p->dmamac_cntl = 0; 59 desc_p->txrx_status &= ~(DESC_TXSTS_MSK | DESC_TXSTS_OWNBYDMA); 60 #else 61 desc_p->dmamac_cntl = DESC_TXCTRL_TXCHAIN; 62 desc_p->txrx_status = 0; 63 #endif 64 } 65 66 /* Correcting the last pointer of the chain */ 67 desc_p->dmamac_next = &desc_table_p[0]; 68 69 writel((ulong)&desc_table_p[0], &dma_p->txdesclistaddr); 70 } 71 72 static void rx_descs_init(struct eth_device *dev) 73 { 74 struct dw_eth_dev *priv = dev->priv; 75 struct eth_dma_regs *dma_p = priv->dma_regs_p; 76 struct dmamacdescr *desc_table_p = &priv->rx_mac_descrtable[0]; 77 char *rxbuffs = &priv->rxbuffs[0]; 78 struct dmamacdescr *desc_p; 79 u32 idx; 80 81 for (idx = 0; idx < CONFIG_RX_DESCR_NUM; idx++) { 82 desc_p = &desc_table_p[idx]; 83 desc_p->dmamac_addr = &rxbuffs[idx * CONFIG_ETH_BUFSIZE]; 84 desc_p->dmamac_next = &desc_table_p[idx + 1]; 85 86 desc_p->dmamac_cntl = 87 (MAC_MAX_FRAME_SZ & DESC_RXCTRL_SIZE1MASK) | \ 88 DESC_RXCTRL_RXCHAIN; 89 90 desc_p->txrx_status = DESC_RXSTS_OWNBYDMA; 91 } 92 93 /* Correcting the last pointer of the chain */ 94 desc_p->dmamac_next = &desc_table_p[0]; 95 96 writel((ulong)&desc_table_p[0], &dma_p->rxdesclistaddr); 97 } 98 99 static void descs_init(struct eth_device *dev) 100 { 101 tx_descs_init(dev); 102 rx_descs_init(dev); 103 } 104 105 static int mac_reset(struct eth_device *dev) 106 { 107 struct dw_eth_dev *priv = dev->priv; 108 struct eth_mac_regs *mac_p = priv->mac_regs_p; 109 struct eth_dma_regs *dma_p = priv->dma_regs_p; 110 111 ulong start; 112 int timeout = CONFIG_MACRESET_TIMEOUT; 113 114 writel(DMAMAC_SRST, &dma_p->busmode); 115 writel(MII_PORTSELECT, &mac_p->conf); 116 117 start = get_timer(0); 118 while (get_timer(start) < timeout) { 119 if (!(readl(&dma_p->busmode) & DMAMAC_SRST)) 120 return 0; 121 122 /* Try again after 10usec */ 123 udelay(10); 124 }; 125 126 return -1; 127 } 128 129 static int dw_write_hwaddr(struct eth_device *dev) 130 { 131 struct dw_eth_dev *priv = dev->priv; 132 struct eth_mac_regs *mac_p = priv->mac_regs_p; 133 u32 macid_lo, macid_hi; 134 u8 *mac_id = &dev->enetaddr[0]; 135 136 macid_lo = mac_id[0] + (mac_id[1] << 8) + \ 137 (mac_id[2] << 16) + (mac_id[3] << 24); 138 macid_hi = mac_id[4] + (mac_id[5] << 8); 139 140 writel(macid_hi, &mac_p->macaddr0hi); 141 writel(macid_lo, &mac_p->macaddr0lo); 142 143 return 0; 144 } 145 146 static int dw_eth_init(struct eth_device *dev, bd_t *bis) 147 { 148 struct dw_eth_dev *priv = dev->priv; 149 struct eth_mac_regs *mac_p = priv->mac_regs_p; 150 struct eth_dma_regs *dma_p = priv->dma_regs_p; 151 u32 conf; 152 153 if (priv->phy_configured != 1) 154 configure_phy(dev); 155 156 /* Reset ethernet hardware */ 157 if (mac_reset(dev) < 0) 158 return -1; 159 160 /* Resore the HW MAC address as it has been lost during MAC reset */ 161 dw_write_hwaddr(dev); 162 163 writel(FIXEDBURST | PRIORXTX_41 | BURST_16, 164 &dma_p->busmode); 165 166 writel(FLUSHTXFIFO | readl(&dma_p->opmode), &dma_p->opmode); 167 writel(STOREFORWARD | TXSECONDFRAME, &dma_p->opmode); 168 169 conf = FRAMEBURSTENABLE | DISABLERXOWN; 170 171 if (priv->speed != SPEED_1000M) 172 conf |= MII_PORTSELECT; 173 174 if (priv->duplex == FULL_DUPLEX) 175 conf |= FULLDPLXMODE; 176 177 writel(conf, &mac_p->conf); 178 179 descs_init(dev); 180 181 /* 182 * Start/Enable xfer at dma as well as mac level 183 */ 184 writel(readl(&dma_p->opmode) | RXSTART, &dma_p->opmode); 185 writel(readl(&dma_p->opmode) | TXSTART, &dma_p->opmode); 186 187 writel(readl(&mac_p->conf) | RXENABLE | TXENABLE, &mac_p->conf); 188 189 return 0; 190 } 191 192 static int dw_eth_send(struct eth_device *dev, void *packet, int length) 193 { 194 struct dw_eth_dev *priv = dev->priv; 195 struct eth_dma_regs *dma_p = priv->dma_regs_p; 196 u32 desc_num = priv->tx_currdescnum; 197 struct dmamacdescr *desc_p = &priv->tx_mac_descrtable[desc_num]; 198 199 /* Check if the descriptor is owned by CPU */ 200 if (desc_p->txrx_status & DESC_TXSTS_OWNBYDMA) { 201 printf("CPU not owner of tx frame\n"); 202 return -1; 203 } 204 205 memcpy((void *)desc_p->dmamac_addr, packet, length); 206 207 #if defined(CONFIG_DW_ALTDESCRIPTOR) 208 desc_p->txrx_status |= DESC_TXSTS_TXFIRST | DESC_TXSTS_TXLAST; 209 desc_p->dmamac_cntl |= (length << DESC_TXCTRL_SIZE1SHFT) & \ 210 DESC_TXCTRL_SIZE1MASK; 211 212 desc_p->txrx_status &= ~(DESC_TXSTS_MSK); 213 desc_p->txrx_status |= DESC_TXSTS_OWNBYDMA; 214 #else 215 desc_p->dmamac_cntl |= ((length << DESC_TXCTRL_SIZE1SHFT) & \ 216 DESC_TXCTRL_SIZE1MASK) | DESC_TXCTRL_TXLAST | \ 217 DESC_TXCTRL_TXFIRST; 218 219 desc_p->txrx_status = DESC_TXSTS_OWNBYDMA; 220 #endif 221 222 /* Test the wrap-around condition. */ 223 if (++desc_num >= CONFIG_TX_DESCR_NUM) 224 desc_num = 0; 225 226 priv->tx_currdescnum = desc_num; 227 228 /* Start the transmission */ 229 writel(POLL_DATA, &dma_p->txpolldemand); 230 231 return 0; 232 } 233 234 static int dw_eth_recv(struct eth_device *dev) 235 { 236 struct dw_eth_dev *priv = dev->priv; 237 u32 desc_num = priv->rx_currdescnum; 238 struct dmamacdescr *desc_p = &priv->rx_mac_descrtable[desc_num]; 239 240 u32 status = desc_p->txrx_status; 241 int length = 0; 242 243 /* Check if the owner is the CPU */ 244 if (!(status & DESC_RXSTS_OWNBYDMA)) { 245 246 length = (status & DESC_RXSTS_FRMLENMSK) >> \ 247 DESC_RXSTS_FRMLENSHFT; 248 249 NetReceive(desc_p->dmamac_addr, length); 250 251 /* 252 * Make the current descriptor valid again and go to 253 * the next one 254 */ 255 desc_p->txrx_status |= DESC_RXSTS_OWNBYDMA; 256 257 /* Test the wrap-around condition. */ 258 if (++desc_num >= CONFIG_RX_DESCR_NUM) 259 desc_num = 0; 260 } 261 262 priv->rx_currdescnum = desc_num; 263 264 return length; 265 } 266 267 static void dw_eth_halt(struct eth_device *dev) 268 { 269 struct dw_eth_dev *priv = dev->priv; 270 271 mac_reset(dev); 272 priv->tx_currdescnum = priv->rx_currdescnum = 0; 273 } 274 275 static int eth_mdio_read(struct eth_device *dev, u8 addr, u8 reg, u16 *val) 276 { 277 struct dw_eth_dev *priv = dev->priv; 278 struct eth_mac_regs *mac_p = priv->mac_regs_p; 279 ulong start; 280 u32 miiaddr; 281 int timeout = CONFIG_MDIO_TIMEOUT; 282 283 miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) | \ 284 ((reg << MIIREGSHIFT) & MII_REGMSK); 285 286 writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr); 287 288 start = get_timer(0); 289 while (get_timer(start) < timeout) { 290 if (!(readl(&mac_p->miiaddr) & MII_BUSY)) { 291 *val = readl(&mac_p->miidata); 292 return 0; 293 } 294 295 /* Try again after 10usec */ 296 udelay(10); 297 }; 298 299 return -1; 300 } 301 302 static int eth_mdio_write(struct eth_device *dev, u8 addr, u8 reg, u16 val) 303 { 304 struct dw_eth_dev *priv = dev->priv; 305 struct eth_mac_regs *mac_p = priv->mac_regs_p; 306 ulong start; 307 u32 miiaddr; 308 int ret = -1, timeout = CONFIG_MDIO_TIMEOUT; 309 u16 value; 310 311 writel(val, &mac_p->miidata); 312 miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) | \ 313 ((reg << MIIREGSHIFT) & MII_REGMSK) | MII_WRITE; 314 315 writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr); 316 317 start = get_timer(0); 318 while (get_timer(start) < timeout) { 319 if (!(readl(&mac_p->miiaddr) & MII_BUSY)) { 320 ret = 0; 321 break; 322 } 323 324 /* Try again after 10usec */ 325 udelay(10); 326 }; 327 328 /* Needed as a fix for ST-Phy */ 329 eth_mdio_read(dev, addr, reg, &value); 330 331 return ret; 332 } 333 334 #if defined(CONFIG_DW_SEARCH_PHY) 335 static int find_phy(struct eth_device *dev) 336 { 337 int phy_addr = 0; 338 u16 ctrl, oldctrl; 339 340 do { 341 eth_mdio_read(dev, phy_addr, MII_BMCR, &ctrl); 342 oldctrl = ctrl & BMCR_ANENABLE; 343 344 ctrl ^= BMCR_ANENABLE; 345 eth_mdio_write(dev, phy_addr, MII_BMCR, ctrl); 346 eth_mdio_read(dev, phy_addr, MII_BMCR, &ctrl); 347 ctrl &= BMCR_ANENABLE; 348 349 if (ctrl == oldctrl) { 350 phy_addr++; 351 } else { 352 ctrl ^= BMCR_ANENABLE; 353 eth_mdio_write(dev, phy_addr, MII_BMCR, ctrl); 354 355 return phy_addr; 356 } 357 } while (phy_addr < 32); 358 359 return -1; 360 } 361 #endif 362 363 static int dw_reset_phy(struct eth_device *dev) 364 { 365 struct dw_eth_dev *priv = dev->priv; 366 u16 ctrl; 367 ulong start; 368 int timeout = CONFIG_PHYRESET_TIMEOUT; 369 u32 phy_addr = priv->address; 370 371 eth_mdio_write(dev, phy_addr, MII_BMCR, BMCR_RESET); 372 373 start = get_timer(0); 374 while (get_timer(start) < timeout) { 375 eth_mdio_read(dev, phy_addr, MII_BMCR, &ctrl); 376 if (!(ctrl & BMCR_RESET)) 377 break; 378 379 /* Try again after 10usec */ 380 udelay(10); 381 }; 382 383 if (get_timer(start) >= CONFIG_PHYRESET_TIMEOUT) 384 return -1; 385 386 #ifdef CONFIG_PHY_RESET_DELAY 387 udelay(CONFIG_PHY_RESET_DELAY); 388 #endif 389 return 0; 390 } 391 392 static int configure_phy(struct eth_device *dev) 393 { 394 struct dw_eth_dev *priv = dev->priv; 395 int phy_addr; 396 u16 bmcr; 397 #if defined(CONFIG_DW_AUTONEG) 398 u16 bmsr; 399 u32 timeout; 400 ulong start; 401 u16 anlpar, btsr; 402 #else 403 u16 ctrl; 404 #endif 405 406 #if defined(CONFIG_DW_SEARCH_PHY) 407 phy_addr = find_phy(dev); 408 if (phy_addr >= 0) 409 priv->address = phy_addr; 410 else 411 return -1; 412 #else 413 phy_addr = priv->address; 414 #endif 415 if (dw_reset_phy(dev) < 0) 416 return -1; 417 418 #if defined(CONFIG_DW_AUTONEG) 419 /* Set Auto-Neg Advertisement capabilities to 10/100 half/full */ 420 eth_mdio_write(dev, phy_addr, MII_ADVERTISE, 0x1E1); 421 422 bmcr = BMCR_ANENABLE | BMCR_ANRESTART; 423 #else 424 bmcr = BMCR_SPEED100 | BMCR_FULLDPLX; 425 426 #if defined(CONFIG_DW_SPEED10M) 427 bmcr &= ~BMCR_SPEED100; 428 #endif 429 #if defined(CONFIG_DW_DUPLEXHALF) 430 bmcr &= ~BMCR_FULLDPLX; 431 #endif 432 #endif 433 if (eth_mdio_write(dev, phy_addr, MII_BMCR, bmcr) < 0) 434 return -1; 435 436 /* Read the phy status register and populate priv structure */ 437 #if defined(CONFIG_DW_AUTONEG) 438 timeout = CONFIG_AUTONEG_TIMEOUT; 439 start = get_timer(0); 440 441 while (get_timer(start) < timeout) { 442 eth_mdio_read(dev, phy_addr, MII_BMSR, &bmsr); 443 if (bmsr & BMSR_ANEGCOMPLETE) 444 break; 445 446 /* Try again after 10usec */ 447 udelay(10); 448 }; 449 450 eth_mdio_read(dev, phy_addr, MII_LPA, &anlpar); 451 eth_mdio_read(dev, phy_addr, MII_STAT1000, &btsr); 452 453 if (bmsr & BMSR_ANEGCOMPLETE) { 454 if (btsr & PHY_1000BTSR_1000FD) { 455 priv->speed = SPEED_1000M; 456 bmcr |= BMCR_SPEED1000; 457 priv->duplex = FULL_DUPLEX; 458 bmcr |= BMCR_FULLDPLX; 459 } else if (btsr & PHY_1000BTSR_1000HD) { 460 priv->speed = SPEED_1000M; 461 bmcr |= BMCR_SPEED1000; 462 priv->duplex = HALF_DUPLEX; 463 bmcr &= ~BMCR_FULLDPLX; 464 } else if (anlpar & LPA_100FULL) { 465 priv->speed = SPEED_100M; 466 bmcr |= BMCR_SPEED100; 467 priv->duplex = FULL_DUPLEX; 468 bmcr |= BMCR_FULLDPLX; 469 } else if (anlpar & LPA_100HALF) { 470 priv->speed = SPEED_100M; 471 bmcr |= BMCR_SPEED100; 472 priv->duplex = HALF_DUPLEX; 473 bmcr &= ~BMCR_FULLDPLX; 474 } else if (anlpar & LPA_10FULL) { 475 priv->speed = SPEED_10M; 476 bmcr &= ~BMCR_SPEED100; 477 priv->duplex = FULL_DUPLEX; 478 bmcr |= BMCR_FULLDPLX; 479 } else { 480 priv->speed = SPEED_10M; 481 bmcr &= ~BMCR_SPEED100; 482 priv->duplex = HALF_DUPLEX; 483 bmcr &= ~BMCR_FULLDPLX; 484 } 485 if (eth_mdio_write(dev, phy_addr, MII_BMCR, bmcr) < 0) 486 return -1; 487 } else 488 return -1; 489 #else 490 if (eth_mdio_read(dev, phy_addr, MII_BMCR, &ctrl) < 0) 491 return -1; 492 493 if (ctrl & BMCR_FULLDPLX) 494 priv->duplex = FULL_DUPLEX; 495 else 496 priv->duplex = HALF_DUPLEX; 497 498 if (ctrl & BMCR_SPEED1000) 499 priv->speed = SPEED_1000M; 500 else if (ctrl & BMCR_SPEED100) 501 priv->speed = SPEED_100M; 502 else 503 priv->speed = SPEED_10M; 504 #endif 505 priv->phy_configured = 1; 506 507 return 0; 508 } 509 510 #if defined(CONFIG_MII) 511 static int dw_mii_read(const char *devname, u8 addr, u8 reg, u16 *val) 512 { 513 struct eth_device *dev; 514 515 dev = eth_get_dev_by_name(devname); 516 if (dev) 517 eth_mdio_read(dev, addr, reg, val); 518 519 return 0; 520 } 521 522 static int dw_mii_write(const char *devname, u8 addr, u8 reg, u16 val) 523 { 524 struct eth_device *dev; 525 526 dev = eth_get_dev_by_name(devname); 527 if (dev) 528 eth_mdio_write(dev, addr, reg, val); 529 530 return 0; 531 } 532 #endif 533 534 int designware_initialize(u32 id, ulong base_addr, u32 phy_addr) 535 { 536 struct eth_device *dev; 537 struct dw_eth_dev *priv; 538 539 dev = (struct eth_device *) malloc(sizeof(struct eth_device)); 540 if (!dev) 541 return -ENOMEM; 542 543 /* 544 * Since the priv structure contains the descriptors which need a strict 545 * buswidth alignment, memalign is used to allocate memory 546 */ 547 priv = (struct dw_eth_dev *) memalign(16, sizeof(struct dw_eth_dev)); 548 if (!priv) { 549 free(dev); 550 return -ENOMEM; 551 } 552 553 memset(dev, 0, sizeof(struct eth_device)); 554 memset(priv, 0, sizeof(struct dw_eth_dev)); 555 556 sprintf(dev->name, "mii%d", id); 557 dev->iobase = (int)base_addr; 558 dev->priv = priv; 559 560 eth_getenv_enetaddr_by_index("eth", id, &dev->enetaddr[0]); 561 562 priv->dev = dev; 563 priv->mac_regs_p = (struct eth_mac_regs *)base_addr; 564 priv->dma_regs_p = (struct eth_dma_regs *)(base_addr + 565 DW_DMA_BASE_OFFSET); 566 priv->address = phy_addr; 567 priv->phy_configured = 0; 568 569 if (mac_reset(dev) < 0) 570 return -1; 571 572 configure_phy(dev); 573 574 dev->init = dw_eth_init; 575 dev->send = dw_eth_send; 576 dev->recv = dw_eth_recv; 577 dev->halt = dw_eth_halt; 578 dev->write_hwaddr = dw_write_hwaddr; 579 580 eth_register(dev); 581 582 #if defined(CONFIG_MII) 583 miiphy_register(dev->name, dw_mii_read, dw_mii_write); 584 #endif 585 return 1; 586 } 587