1 /* 2 * (C) Copyright 2010 3 * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 /* 9 * Designware ethernet IP driver for U-Boot 10 */ 11 12 #include <common.h> 13 #include <dm.h> 14 #include <errno.h> 15 #include <miiphy.h> 16 #include <malloc.h> 17 #include <pci.h> 18 #include <linux/compiler.h> 19 #include <linux/err.h> 20 #include <asm/io.h> 21 #include "designware.h" 22 23 DECLARE_GLOBAL_DATA_PTR; 24 25 static int dw_mdio_read(struct mii_dev *bus, int addr, int devad, int reg) 26 { 27 struct eth_mac_regs *mac_p = bus->priv; 28 ulong start; 29 u16 miiaddr; 30 int timeout = CONFIG_MDIO_TIMEOUT; 31 32 miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) | 33 ((reg << MIIREGSHIFT) & MII_REGMSK); 34 35 writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr); 36 37 start = get_timer(0); 38 while (get_timer(start) < timeout) { 39 if (!(readl(&mac_p->miiaddr) & MII_BUSY)) 40 return readl(&mac_p->miidata); 41 udelay(10); 42 }; 43 44 return -ETIMEDOUT; 45 } 46 47 static int dw_mdio_write(struct mii_dev *bus, int addr, int devad, int reg, 48 u16 val) 49 { 50 struct eth_mac_regs *mac_p = bus->priv; 51 ulong start; 52 u16 miiaddr; 53 int ret = -ETIMEDOUT, timeout = CONFIG_MDIO_TIMEOUT; 54 55 writel(val, &mac_p->miidata); 56 miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) | 57 ((reg << MIIREGSHIFT) & MII_REGMSK) | MII_WRITE; 58 59 writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr); 60 61 start = get_timer(0); 62 while (get_timer(start) < timeout) { 63 if (!(readl(&mac_p->miiaddr) & MII_BUSY)) { 64 ret = 0; 65 break; 66 } 67 udelay(10); 68 }; 69 70 return ret; 71 } 72 73 static int dw_mdio_init(const char *name, struct eth_mac_regs *mac_regs_p) 74 { 75 struct mii_dev *bus = mdio_alloc(); 76 77 if (!bus) { 78 printf("Failed to allocate MDIO bus\n"); 79 return -ENOMEM; 80 } 81 82 bus->read = dw_mdio_read; 83 bus->write = dw_mdio_write; 84 snprintf(bus->name, sizeof(bus->name), "%s", name); 85 86 bus->priv = (void *)mac_regs_p; 87 88 return mdio_register(bus); 89 } 90 91 static void tx_descs_init(struct dw_eth_dev *priv) 92 { 93 struct eth_dma_regs *dma_p = priv->dma_regs_p; 94 struct dmamacdescr *desc_table_p = &priv->tx_mac_descrtable[0]; 95 char *txbuffs = &priv->txbuffs[0]; 96 struct dmamacdescr *desc_p; 97 u32 idx; 98 99 for (idx = 0; idx < CONFIG_TX_DESCR_NUM; idx++) { 100 desc_p = &desc_table_p[idx]; 101 desc_p->dmamac_addr = &txbuffs[idx * CONFIG_ETH_BUFSIZE]; 102 desc_p->dmamac_next = &desc_table_p[idx + 1]; 103 104 #if defined(CONFIG_DW_ALTDESCRIPTOR) 105 desc_p->txrx_status &= ~(DESC_TXSTS_TXINT | DESC_TXSTS_TXLAST | 106 DESC_TXSTS_TXFIRST | DESC_TXSTS_TXCRCDIS | 107 DESC_TXSTS_TXCHECKINSCTRL | 108 DESC_TXSTS_TXRINGEND | DESC_TXSTS_TXPADDIS); 109 110 desc_p->txrx_status |= DESC_TXSTS_TXCHAIN; 111 desc_p->dmamac_cntl = 0; 112 desc_p->txrx_status &= ~(DESC_TXSTS_MSK | DESC_TXSTS_OWNBYDMA); 113 #else 114 desc_p->dmamac_cntl = DESC_TXCTRL_TXCHAIN; 115 desc_p->txrx_status = 0; 116 #endif 117 } 118 119 /* Correcting the last pointer of the chain */ 120 desc_p->dmamac_next = &desc_table_p[0]; 121 122 /* Flush all Tx buffer descriptors at once */ 123 flush_dcache_range((unsigned int)priv->tx_mac_descrtable, 124 (unsigned int)priv->tx_mac_descrtable + 125 sizeof(priv->tx_mac_descrtable)); 126 127 writel((ulong)&desc_table_p[0], &dma_p->txdesclistaddr); 128 priv->tx_currdescnum = 0; 129 } 130 131 static void rx_descs_init(struct dw_eth_dev *priv) 132 { 133 struct eth_dma_regs *dma_p = priv->dma_regs_p; 134 struct dmamacdescr *desc_table_p = &priv->rx_mac_descrtable[0]; 135 char *rxbuffs = &priv->rxbuffs[0]; 136 struct dmamacdescr *desc_p; 137 u32 idx; 138 139 /* Before passing buffers to GMAC we need to make sure zeros 140 * written there right after "priv" structure allocation were 141 * flushed into RAM. 142 * Otherwise there's a chance to get some of them flushed in RAM when 143 * GMAC is already pushing data to RAM via DMA. This way incoming from 144 * GMAC data will be corrupted. */ 145 flush_dcache_range((unsigned int)rxbuffs, (unsigned int)rxbuffs + 146 RX_TOTAL_BUFSIZE); 147 148 for (idx = 0; idx < CONFIG_RX_DESCR_NUM; idx++) { 149 desc_p = &desc_table_p[idx]; 150 desc_p->dmamac_addr = &rxbuffs[idx * CONFIG_ETH_BUFSIZE]; 151 desc_p->dmamac_next = &desc_table_p[idx + 1]; 152 153 desc_p->dmamac_cntl = 154 (MAC_MAX_FRAME_SZ & DESC_RXCTRL_SIZE1MASK) | 155 DESC_RXCTRL_RXCHAIN; 156 157 desc_p->txrx_status = DESC_RXSTS_OWNBYDMA; 158 } 159 160 /* Correcting the last pointer of the chain */ 161 desc_p->dmamac_next = &desc_table_p[0]; 162 163 /* Flush all Rx buffer descriptors at once */ 164 flush_dcache_range((unsigned int)priv->rx_mac_descrtable, 165 (unsigned int)priv->rx_mac_descrtable + 166 sizeof(priv->rx_mac_descrtable)); 167 168 writel((ulong)&desc_table_p[0], &dma_p->rxdesclistaddr); 169 priv->rx_currdescnum = 0; 170 } 171 172 static int _dw_write_hwaddr(struct dw_eth_dev *priv, u8 *mac_id) 173 { 174 struct eth_mac_regs *mac_p = priv->mac_regs_p; 175 u32 macid_lo, macid_hi; 176 177 macid_lo = mac_id[0] + (mac_id[1] << 8) + (mac_id[2] << 16) + 178 (mac_id[3] << 24); 179 macid_hi = mac_id[4] + (mac_id[5] << 8); 180 181 writel(macid_hi, &mac_p->macaddr0hi); 182 writel(macid_lo, &mac_p->macaddr0lo); 183 184 return 0; 185 } 186 187 static void dw_adjust_link(struct eth_mac_regs *mac_p, 188 struct phy_device *phydev) 189 { 190 u32 conf = readl(&mac_p->conf) | FRAMEBURSTENABLE | DISABLERXOWN; 191 192 if (!phydev->link) { 193 printf("%s: No link.\n", phydev->dev->name); 194 return; 195 } 196 197 if (phydev->speed != 1000) 198 conf |= MII_PORTSELECT; 199 else 200 conf &= ~MII_PORTSELECT; 201 202 if (phydev->speed == 100) 203 conf |= FES_100; 204 205 if (phydev->duplex) 206 conf |= FULLDPLXMODE; 207 208 writel(conf, &mac_p->conf); 209 210 printf("Speed: %d, %s duplex%s\n", phydev->speed, 211 (phydev->duplex) ? "full" : "half", 212 (phydev->port == PORT_FIBRE) ? ", fiber mode" : ""); 213 } 214 215 static void _dw_eth_halt(struct dw_eth_dev *priv) 216 { 217 struct eth_mac_regs *mac_p = priv->mac_regs_p; 218 struct eth_dma_regs *dma_p = priv->dma_regs_p; 219 220 writel(readl(&mac_p->conf) & ~(RXENABLE | TXENABLE), &mac_p->conf); 221 writel(readl(&dma_p->opmode) & ~(RXSTART | TXSTART), &dma_p->opmode); 222 223 phy_shutdown(priv->phydev); 224 } 225 226 static int _dw_eth_init(struct dw_eth_dev *priv, u8 *enetaddr) 227 { 228 struct eth_mac_regs *mac_p = priv->mac_regs_p; 229 struct eth_dma_regs *dma_p = priv->dma_regs_p; 230 unsigned int start; 231 int ret; 232 233 writel(readl(&dma_p->busmode) | DMAMAC_SRST, &dma_p->busmode); 234 235 start = get_timer(0); 236 while (readl(&dma_p->busmode) & DMAMAC_SRST) { 237 if (get_timer(start) >= CONFIG_MACRESET_TIMEOUT) { 238 printf("DMA reset timeout\n"); 239 return -ETIMEDOUT; 240 } 241 242 mdelay(100); 243 }; 244 245 /* 246 * Soft reset above clears HW address registers. 247 * So we have to set it here once again. 248 */ 249 _dw_write_hwaddr(priv, enetaddr); 250 251 rx_descs_init(priv); 252 tx_descs_init(priv); 253 254 writel(FIXEDBURST | PRIORXTX_41 | DMA_PBL, &dma_p->busmode); 255 256 #ifndef CONFIG_DW_MAC_FORCE_THRESHOLD_MODE 257 writel(readl(&dma_p->opmode) | FLUSHTXFIFO | STOREFORWARD, 258 &dma_p->opmode); 259 #else 260 writel(readl(&dma_p->opmode) | FLUSHTXFIFO, 261 &dma_p->opmode); 262 #endif 263 264 writel(readl(&dma_p->opmode) | RXSTART | TXSTART, &dma_p->opmode); 265 266 #ifdef CONFIG_DW_AXI_BURST_LEN 267 writel((CONFIG_DW_AXI_BURST_LEN & 0x1FF >> 1), &dma_p->axibus); 268 #endif 269 270 /* Start up the PHY */ 271 ret = phy_startup(priv->phydev); 272 if (ret) { 273 printf("Could not initialize PHY %s\n", 274 priv->phydev->dev->name); 275 return ret; 276 } 277 278 dw_adjust_link(mac_p, priv->phydev); 279 280 if (!priv->phydev->link) 281 return -EIO; 282 283 writel(readl(&mac_p->conf) | RXENABLE | TXENABLE, &mac_p->conf); 284 285 return 0; 286 } 287 288 static int _dw_eth_send(struct dw_eth_dev *priv, void *packet, int length) 289 { 290 struct eth_dma_regs *dma_p = priv->dma_regs_p; 291 u32 desc_num = priv->tx_currdescnum; 292 struct dmamacdescr *desc_p = &priv->tx_mac_descrtable[desc_num]; 293 uint32_t desc_start = (uint32_t)desc_p; 294 uint32_t desc_end = desc_start + 295 roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN); 296 uint32_t data_start = (uint32_t)desc_p->dmamac_addr; 297 uint32_t data_end = data_start + 298 roundup(length, ARCH_DMA_MINALIGN); 299 /* 300 * Strictly we only need to invalidate the "txrx_status" field 301 * for the following check, but on some platforms we cannot 302 * invalidate only 4 bytes, so we flush the entire descriptor, 303 * which is 16 bytes in total. This is safe because the 304 * individual descriptors in the array are each aligned to 305 * ARCH_DMA_MINALIGN and padded appropriately. 306 */ 307 invalidate_dcache_range(desc_start, desc_end); 308 309 /* Check if the descriptor is owned by CPU */ 310 if (desc_p->txrx_status & DESC_TXSTS_OWNBYDMA) { 311 printf("CPU not owner of tx frame\n"); 312 return -EPERM; 313 } 314 315 memcpy(desc_p->dmamac_addr, packet, length); 316 317 /* Flush data to be sent */ 318 flush_dcache_range(data_start, data_end); 319 320 #if defined(CONFIG_DW_ALTDESCRIPTOR) 321 desc_p->txrx_status |= DESC_TXSTS_TXFIRST | DESC_TXSTS_TXLAST; 322 desc_p->dmamac_cntl |= (length << DESC_TXCTRL_SIZE1SHFT) & 323 DESC_TXCTRL_SIZE1MASK; 324 325 desc_p->txrx_status &= ~(DESC_TXSTS_MSK); 326 desc_p->txrx_status |= DESC_TXSTS_OWNBYDMA; 327 #else 328 desc_p->dmamac_cntl |= ((length << DESC_TXCTRL_SIZE1SHFT) & 329 DESC_TXCTRL_SIZE1MASK) | DESC_TXCTRL_TXLAST | 330 DESC_TXCTRL_TXFIRST; 331 332 desc_p->txrx_status = DESC_TXSTS_OWNBYDMA; 333 #endif 334 335 /* Flush modified buffer descriptor */ 336 flush_dcache_range(desc_start, desc_end); 337 338 /* Test the wrap-around condition. */ 339 if (++desc_num >= CONFIG_TX_DESCR_NUM) 340 desc_num = 0; 341 342 priv->tx_currdescnum = desc_num; 343 344 /* Start the transmission */ 345 writel(POLL_DATA, &dma_p->txpolldemand); 346 347 return 0; 348 } 349 350 static int _dw_eth_recv(struct dw_eth_dev *priv, uchar **packetp) 351 { 352 u32 status, desc_num = priv->rx_currdescnum; 353 struct dmamacdescr *desc_p = &priv->rx_mac_descrtable[desc_num]; 354 int length = -EAGAIN; 355 uint32_t desc_start = (uint32_t)desc_p; 356 uint32_t desc_end = desc_start + 357 roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN); 358 uint32_t data_start = (uint32_t)desc_p->dmamac_addr; 359 uint32_t data_end; 360 361 /* Invalidate entire buffer descriptor */ 362 invalidate_dcache_range(desc_start, desc_end); 363 364 status = desc_p->txrx_status; 365 366 /* Check if the owner is the CPU */ 367 if (!(status & DESC_RXSTS_OWNBYDMA)) { 368 369 length = (status & DESC_RXSTS_FRMLENMSK) >> 370 DESC_RXSTS_FRMLENSHFT; 371 372 /* Invalidate received data */ 373 data_end = data_start + roundup(length, ARCH_DMA_MINALIGN); 374 invalidate_dcache_range(data_start, data_end); 375 *packetp = desc_p->dmamac_addr; 376 } 377 378 return length; 379 } 380 381 static int _dw_free_pkt(struct dw_eth_dev *priv) 382 { 383 u32 desc_num = priv->rx_currdescnum; 384 struct dmamacdescr *desc_p = &priv->rx_mac_descrtable[desc_num]; 385 uint32_t desc_start = (uint32_t)desc_p; 386 uint32_t desc_end = desc_start + 387 roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN); 388 389 /* 390 * Make the current descriptor valid again and go to 391 * the next one 392 */ 393 desc_p->txrx_status |= DESC_RXSTS_OWNBYDMA; 394 395 /* Flush only status field - others weren't changed */ 396 flush_dcache_range(desc_start, desc_end); 397 398 /* Test the wrap-around condition. */ 399 if (++desc_num >= CONFIG_RX_DESCR_NUM) 400 desc_num = 0; 401 priv->rx_currdescnum = desc_num; 402 403 return 0; 404 } 405 406 static int dw_phy_init(struct dw_eth_dev *priv, void *dev) 407 { 408 struct phy_device *phydev; 409 int mask = 0xffffffff, ret; 410 411 #ifdef CONFIG_PHY_ADDR 412 mask = 1 << CONFIG_PHY_ADDR; 413 #endif 414 415 phydev = phy_find_by_mask(priv->bus, mask, priv->interface); 416 if (!phydev) 417 return -ENODEV; 418 419 phy_connect_dev(phydev, dev); 420 421 phydev->supported &= PHY_GBIT_FEATURES; 422 if (priv->max_speed) { 423 ret = phy_set_supported(phydev, priv->max_speed); 424 if (ret) 425 return ret; 426 } 427 phydev->advertising = phydev->supported; 428 429 priv->phydev = phydev; 430 phy_config(phydev); 431 432 return 0; 433 } 434 435 #ifndef CONFIG_DM_ETH 436 static int dw_eth_init(struct eth_device *dev, bd_t *bis) 437 { 438 return _dw_eth_init(dev->priv, dev->enetaddr); 439 } 440 441 static int dw_eth_send(struct eth_device *dev, void *packet, int length) 442 { 443 return _dw_eth_send(dev->priv, packet, length); 444 } 445 446 static int dw_eth_recv(struct eth_device *dev) 447 { 448 uchar *packet; 449 int length; 450 451 length = _dw_eth_recv(dev->priv, &packet); 452 if (length == -EAGAIN) 453 return 0; 454 net_process_received_packet(packet, length); 455 456 _dw_free_pkt(dev->priv); 457 458 return 0; 459 } 460 461 static void dw_eth_halt(struct eth_device *dev) 462 { 463 return _dw_eth_halt(dev->priv); 464 } 465 466 static int dw_write_hwaddr(struct eth_device *dev) 467 { 468 return _dw_write_hwaddr(dev->priv, dev->enetaddr); 469 } 470 471 int designware_initialize(ulong base_addr, u32 interface) 472 { 473 struct eth_device *dev; 474 struct dw_eth_dev *priv; 475 476 dev = (struct eth_device *) malloc(sizeof(struct eth_device)); 477 if (!dev) 478 return -ENOMEM; 479 480 /* 481 * Since the priv structure contains the descriptors which need a strict 482 * buswidth alignment, memalign is used to allocate memory 483 */ 484 priv = (struct dw_eth_dev *) memalign(ARCH_DMA_MINALIGN, 485 sizeof(struct dw_eth_dev)); 486 if (!priv) { 487 free(dev); 488 return -ENOMEM; 489 } 490 491 memset(dev, 0, sizeof(struct eth_device)); 492 memset(priv, 0, sizeof(struct dw_eth_dev)); 493 494 sprintf(dev->name, "dwmac.%lx", base_addr); 495 dev->iobase = (int)base_addr; 496 dev->priv = priv; 497 498 priv->dev = dev; 499 priv->mac_regs_p = (struct eth_mac_regs *)base_addr; 500 priv->dma_regs_p = (struct eth_dma_regs *)(base_addr + 501 DW_DMA_BASE_OFFSET); 502 503 dev->init = dw_eth_init; 504 dev->send = dw_eth_send; 505 dev->recv = dw_eth_recv; 506 dev->halt = dw_eth_halt; 507 dev->write_hwaddr = dw_write_hwaddr; 508 509 eth_register(dev); 510 511 priv->interface = interface; 512 513 dw_mdio_init(dev->name, priv->mac_regs_p); 514 priv->bus = miiphy_get_dev_by_name(dev->name); 515 516 return dw_phy_init(priv, dev); 517 } 518 #endif 519 520 #ifdef CONFIG_DM_ETH 521 static int designware_eth_start(struct udevice *dev) 522 { 523 struct eth_pdata *pdata = dev_get_platdata(dev); 524 525 return _dw_eth_init(dev->priv, pdata->enetaddr); 526 } 527 528 static int designware_eth_send(struct udevice *dev, void *packet, int length) 529 { 530 struct dw_eth_dev *priv = dev_get_priv(dev); 531 532 return _dw_eth_send(priv, packet, length); 533 } 534 535 static int designware_eth_recv(struct udevice *dev, int flags, uchar **packetp) 536 { 537 struct dw_eth_dev *priv = dev_get_priv(dev); 538 539 return _dw_eth_recv(priv, packetp); 540 } 541 542 static int designware_eth_free_pkt(struct udevice *dev, uchar *packet, 543 int length) 544 { 545 struct dw_eth_dev *priv = dev_get_priv(dev); 546 547 return _dw_free_pkt(priv); 548 } 549 550 static void designware_eth_stop(struct udevice *dev) 551 { 552 struct dw_eth_dev *priv = dev_get_priv(dev); 553 554 return _dw_eth_halt(priv); 555 } 556 557 static int designware_eth_write_hwaddr(struct udevice *dev) 558 { 559 struct eth_pdata *pdata = dev_get_platdata(dev); 560 struct dw_eth_dev *priv = dev_get_priv(dev); 561 562 return _dw_write_hwaddr(priv, pdata->enetaddr); 563 } 564 565 static int designware_eth_bind(struct udevice *dev) 566 { 567 #ifdef CONFIG_DM_PCI 568 static int num_cards; 569 char name[20]; 570 571 /* Create a unique device name for PCI type devices */ 572 if (device_is_on_pci_bus(dev)) { 573 sprintf(name, "eth_designware#%u", num_cards++); 574 device_set_name(dev, name); 575 } 576 #endif 577 578 return 0; 579 } 580 581 static int designware_eth_probe(struct udevice *dev) 582 { 583 struct eth_pdata *pdata = dev_get_platdata(dev); 584 struct dw_eth_dev *priv = dev_get_priv(dev); 585 u32 iobase = pdata->iobase; 586 int ret; 587 588 #ifdef CONFIG_DM_PCI 589 /* 590 * If we are on PCI bus, either directly attached to a PCI root port, 591 * or via a PCI bridge, fill in platdata before we probe the hardware. 592 */ 593 if (device_is_on_pci_bus(dev)) { 594 pci_dev_t bdf = dm_pci_get_bdf(dev); 595 596 dm_pci_read_config32(dev, PCI_BASE_ADDRESS_0, &iobase); 597 iobase &= PCI_BASE_ADDRESS_MEM_MASK; 598 iobase = pci_mem_to_phys(bdf, iobase); 599 600 pdata->iobase = iobase; 601 pdata->phy_interface = PHY_INTERFACE_MODE_RMII; 602 } 603 #endif 604 605 debug("%s, iobase=%x, priv=%p\n", __func__, iobase, priv); 606 priv->mac_regs_p = (struct eth_mac_regs *)iobase; 607 priv->dma_regs_p = (struct eth_dma_regs *)(iobase + DW_DMA_BASE_OFFSET); 608 priv->interface = pdata->phy_interface; 609 priv->max_speed = pdata->max_speed; 610 611 dw_mdio_init(dev->name, priv->mac_regs_p); 612 priv->bus = miiphy_get_dev_by_name(dev->name); 613 614 ret = dw_phy_init(priv, dev); 615 debug("%s, ret=%d\n", __func__, ret); 616 617 return ret; 618 } 619 620 static int designware_eth_remove(struct udevice *dev) 621 { 622 struct dw_eth_dev *priv = dev_get_priv(dev); 623 624 free(priv->phydev); 625 mdio_unregister(priv->bus); 626 mdio_free(priv->bus); 627 628 return 0; 629 } 630 631 static const struct eth_ops designware_eth_ops = { 632 .start = designware_eth_start, 633 .send = designware_eth_send, 634 .recv = designware_eth_recv, 635 .free_pkt = designware_eth_free_pkt, 636 .stop = designware_eth_stop, 637 .write_hwaddr = designware_eth_write_hwaddr, 638 }; 639 640 static int designware_eth_ofdata_to_platdata(struct udevice *dev) 641 { 642 struct eth_pdata *pdata = dev_get_platdata(dev); 643 const char *phy_mode; 644 const fdt32_t *cell; 645 646 pdata->iobase = dev_get_addr(dev); 647 pdata->phy_interface = -1; 648 phy_mode = fdt_getprop(gd->fdt_blob, dev->of_offset, "phy-mode", NULL); 649 if (phy_mode) 650 pdata->phy_interface = phy_get_interface_by_name(phy_mode); 651 if (pdata->phy_interface == -1) { 652 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode); 653 return -EINVAL; 654 } 655 656 pdata->max_speed = 0; 657 cell = fdt_getprop(gd->fdt_blob, dev->of_offset, "max-speed", NULL); 658 if (cell) 659 pdata->max_speed = fdt32_to_cpu(*cell); 660 661 return 0; 662 } 663 664 static const struct udevice_id designware_eth_ids[] = { 665 { .compatible = "allwinner,sun7i-a20-gmac" }, 666 { .compatible = "altr,socfpga-stmmac" }, 667 { } 668 }; 669 670 U_BOOT_DRIVER(eth_designware) = { 671 .name = "eth_designware", 672 .id = UCLASS_ETH, 673 .of_match = designware_eth_ids, 674 .ofdata_to_platdata = designware_eth_ofdata_to_platdata, 675 .bind = designware_eth_bind, 676 .probe = designware_eth_probe, 677 .remove = designware_eth_remove, 678 .ops = &designware_eth_ops, 679 .priv_auto_alloc_size = sizeof(struct dw_eth_dev), 680 .platdata_auto_alloc_size = sizeof(struct eth_pdata), 681 .flags = DM_FLAG_ALLOC_PRIV_DMA, 682 }; 683 684 static struct pci_device_id supported[] = { 685 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QRK_EMAC) }, 686 { } 687 }; 688 689 U_BOOT_PCI_DEVICE(eth_designware, supported); 690 #endif 691