1 /* 2 * (C) Copyright 2010 3 * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 /* 9 * Designware ethernet IP driver for U-Boot 10 */ 11 12 #include <common.h> 13 #include <dm.h> 14 #include <errno.h> 15 #include <miiphy.h> 16 #include <malloc.h> 17 #include <pci.h> 18 #include <linux/compiler.h> 19 #include <linux/err.h> 20 #include <asm/io.h> 21 #include "designware.h" 22 23 DECLARE_GLOBAL_DATA_PTR; 24 25 static int dw_mdio_read(struct mii_dev *bus, int addr, int devad, int reg) 26 { 27 struct eth_mac_regs *mac_p = bus->priv; 28 ulong start; 29 u16 miiaddr; 30 int timeout = CONFIG_MDIO_TIMEOUT; 31 32 miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) | 33 ((reg << MIIREGSHIFT) & MII_REGMSK); 34 35 writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr); 36 37 start = get_timer(0); 38 while (get_timer(start) < timeout) { 39 if (!(readl(&mac_p->miiaddr) & MII_BUSY)) 40 return readl(&mac_p->miidata); 41 udelay(10); 42 }; 43 44 return -ETIMEDOUT; 45 } 46 47 static int dw_mdio_write(struct mii_dev *bus, int addr, int devad, int reg, 48 u16 val) 49 { 50 struct eth_mac_regs *mac_p = bus->priv; 51 ulong start; 52 u16 miiaddr; 53 int ret = -ETIMEDOUT, timeout = CONFIG_MDIO_TIMEOUT; 54 55 writel(val, &mac_p->miidata); 56 miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) | 57 ((reg << MIIREGSHIFT) & MII_REGMSK) | MII_WRITE; 58 59 writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr); 60 61 start = get_timer(0); 62 while (get_timer(start) < timeout) { 63 if (!(readl(&mac_p->miiaddr) & MII_BUSY)) { 64 ret = 0; 65 break; 66 } 67 udelay(10); 68 }; 69 70 return ret; 71 } 72 73 static int dw_mdio_init(const char *name, struct eth_mac_regs *mac_regs_p) 74 { 75 struct mii_dev *bus = mdio_alloc(); 76 77 if (!bus) { 78 printf("Failed to allocate MDIO bus\n"); 79 return -ENOMEM; 80 } 81 82 bus->read = dw_mdio_read; 83 bus->write = dw_mdio_write; 84 snprintf(bus->name, sizeof(bus->name), "%s", name); 85 86 bus->priv = (void *)mac_regs_p; 87 88 return mdio_register(bus); 89 } 90 91 static void tx_descs_init(struct dw_eth_dev *priv) 92 { 93 struct eth_dma_regs *dma_p = priv->dma_regs_p; 94 struct dmamacdescr *desc_table_p = &priv->tx_mac_descrtable[0]; 95 char *txbuffs = &priv->txbuffs[0]; 96 struct dmamacdescr *desc_p; 97 u32 idx; 98 99 for (idx = 0; idx < CONFIG_TX_DESCR_NUM; idx++) { 100 desc_p = &desc_table_p[idx]; 101 desc_p->dmamac_addr = &txbuffs[idx * CONFIG_ETH_BUFSIZE]; 102 desc_p->dmamac_next = &desc_table_p[idx + 1]; 103 104 #if defined(CONFIG_DW_ALTDESCRIPTOR) 105 desc_p->txrx_status &= ~(DESC_TXSTS_TXINT | DESC_TXSTS_TXLAST | 106 DESC_TXSTS_TXFIRST | DESC_TXSTS_TXCRCDIS | 107 DESC_TXSTS_TXCHECKINSCTRL | 108 DESC_TXSTS_TXRINGEND | DESC_TXSTS_TXPADDIS); 109 110 desc_p->txrx_status |= DESC_TXSTS_TXCHAIN; 111 desc_p->dmamac_cntl = 0; 112 desc_p->txrx_status &= ~(DESC_TXSTS_MSK | DESC_TXSTS_OWNBYDMA); 113 #else 114 desc_p->dmamac_cntl = DESC_TXCTRL_TXCHAIN; 115 desc_p->txrx_status = 0; 116 #endif 117 } 118 119 /* Correcting the last pointer of the chain */ 120 desc_p->dmamac_next = &desc_table_p[0]; 121 122 /* Flush all Tx buffer descriptors at once */ 123 flush_dcache_range((unsigned int)priv->tx_mac_descrtable, 124 (unsigned int)priv->tx_mac_descrtable + 125 sizeof(priv->tx_mac_descrtable)); 126 127 writel((ulong)&desc_table_p[0], &dma_p->txdesclistaddr); 128 priv->tx_currdescnum = 0; 129 } 130 131 static void rx_descs_init(struct dw_eth_dev *priv) 132 { 133 struct eth_dma_regs *dma_p = priv->dma_regs_p; 134 struct dmamacdescr *desc_table_p = &priv->rx_mac_descrtable[0]; 135 char *rxbuffs = &priv->rxbuffs[0]; 136 struct dmamacdescr *desc_p; 137 u32 idx; 138 139 /* Before passing buffers to GMAC we need to make sure zeros 140 * written there right after "priv" structure allocation were 141 * flushed into RAM. 142 * Otherwise there's a chance to get some of them flushed in RAM when 143 * GMAC is already pushing data to RAM via DMA. This way incoming from 144 * GMAC data will be corrupted. */ 145 flush_dcache_range((unsigned int)rxbuffs, (unsigned int)rxbuffs + 146 RX_TOTAL_BUFSIZE); 147 148 for (idx = 0; idx < CONFIG_RX_DESCR_NUM; idx++) { 149 desc_p = &desc_table_p[idx]; 150 desc_p->dmamac_addr = &rxbuffs[idx * CONFIG_ETH_BUFSIZE]; 151 desc_p->dmamac_next = &desc_table_p[idx + 1]; 152 153 desc_p->dmamac_cntl = 154 (MAC_MAX_FRAME_SZ & DESC_RXCTRL_SIZE1MASK) | 155 DESC_RXCTRL_RXCHAIN; 156 157 desc_p->txrx_status = DESC_RXSTS_OWNBYDMA; 158 } 159 160 /* Correcting the last pointer of the chain */ 161 desc_p->dmamac_next = &desc_table_p[0]; 162 163 /* Flush all Rx buffer descriptors at once */ 164 flush_dcache_range((unsigned int)priv->rx_mac_descrtable, 165 (unsigned int)priv->rx_mac_descrtable + 166 sizeof(priv->rx_mac_descrtable)); 167 168 writel((ulong)&desc_table_p[0], &dma_p->rxdesclistaddr); 169 priv->rx_currdescnum = 0; 170 } 171 172 static int _dw_write_hwaddr(struct dw_eth_dev *priv, u8 *mac_id) 173 { 174 struct eth_mac_regs *mac_p = priv->mac_regs_p; 175 u32 macid_lo, macid_hi; 176 177 macid_lo = mac_id[0] + (mac_id[1] << 8) + (mac_id[2] << 16) + 178 (mac_id[3] << 24); 179 macid_hi = mac_id[4] + (mac_id[5] << 8); 180 181 writel(macid_hi, &mac_p->macaddr0hi); 182 writel(macid_lo, &mac_p->macaddr0lo); 183 184 return 0; 185 } 186 187 static void dw_adjust_link(struct eth_mac_regs *mac_p, 188 struct phy_device *phydev) 189 { 190 u32 conf = readl(&mac_p->conf) | FRAMEBURSTENABLE | DISABLERXOWN; 191 192 if (!phydev->link) { 193 printf("%s: No link.\n", phydev->dev->name); 194 return; 195 } 196 197 if (phydev->speed != 1000) 198 conf |= MII_PORTSELECT; 199 200 if (phydev->speed == 100) 201 conf |= FES_100; 202 203 if (phydev->duplex) 204 conf |= FULLDPLXMODE; 205 206 writel(conf, &mac_p->conf); 207 208 printf("Speed: %d, %s duplex%s\n", phydev->speed, 209 (phydev->duplex) ? "full" : "half", 210 (phydev->port == PORT_FIBRE) ? ", fiber mode" : ""); 211 } 212 213 static void _dw_eth_halt(struct dw_eth_dev *priv) 214 { 215 struct eth_mac_regs *mac_p = priv->mac_regs_p; 216 struct eth_dma_regs *dma_p = priv->dma_regs_p; 217 218 writel(readl(&mac_p->conf) & ~(RXENABLE | TXENABLE), &mac_p->conf); 219 writel(readl(&dma_p->opmode) & ~(RXSTART | TXSTART), &dma_p->opmode); 220 221 phy_shutdown(priv->phydev); 222 } 223 224 static int _dw_eth_init(struct dw_eth_dev *priv, u8 *enetaddr) 225 { 226 struct eth_mac_regs *mac_p = priv->mac_regs_p; 227 struct eth_dma_regs *dma_p = priv->dma_regs_p; 228 unsigned int start; 229 int ret; 230 231 writel(readl(&dma_p->busmode) | DMAMAC_SRST, &dma_p->busmode); 232 233 start = get_timer(0); 234 while (readl(&dma_p->busmode) & DMAMAC_SRST) { 235 if (get_timer(start) >= CONFIG_MACRESET_TIMEOUT) { 236 printf("DMA reset timeout\n"); 237 return -ETIMEDOUT; 238 } 239 240 mdelay(100); 241 }; 242 243 /* 244 * Soft reset above clears HW address registers. 245 * So we have to set it here once again. 246 */ 247 _dw_write_hwaddr(priv, enetaddr); 248 249 rx_descs_init(priv); 250 tx_descs_init(priv); 251 252 writel(FIXEDBURST | PRIORXTX_41 | DMA_PBL, &dma_p->busmode); 253 254 #ifndef CONFIG_DW_MAC_FORCE_THRESHOLD_MODE 255 writel(readl(&dma_p->opmode) | FLUSHTXFIFO | STOREFORWARD, 256 &dma_p->opmode); 257 #else 258 writel(readl(&dma_p->opmode) | FLUSHTXFIFO, 259 &dma_p->opmode); 260 #endif 261 262 writel(readl(&dma_p->opmode) | RXSTART | TXSTART, &dma_p->opmode); 263 264 #ifdef CONFIG_DW_AXI_BURST_LEN 265 writel((CONFIG_DW_AXI_BURST_LEN & 0x1FF >> 1), &dma_p->axibus); 266 #endif 267 268 /* Start up the PHY */ 269 ret = phy_startup(priv->phydev); 270 if (ret) { 271 printf("Could not initialize PHY %s\n", 272 priv->phydev->dev->name); 273 return ret; 274 } 275 276 dw_adjust_link(mac_p, priv->phydev); 277 278 if (!priv->phydev->link) 279 return -EIO; 280 281 writel(readl(&mac_p->conf) | RXENABLE | TXENABLE, &mac_p->conf); 282 283 return 0; 284 } 285 286 static int _dw_eth_send(struct dw_eth_dev *priv, void *packet, int length) 287 { 288 struct eth_dma_regs *dma_p = priv->dma_regs_p; 289 u32 desc_num = priv->tx_currdescnum; 290 struct dmamacdescr *desc_p = &priv->tx_mac_descrtable[desc_num]; 291 uint32_t desc_start = (uint32_t)desc_p; 292 uint32_t desc_end = desc_start + 293 roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN); 294 uint32_t data_start = (uint32_t)desc_p->dmamac_addr; 295 uint32_t data_end = data_start + 296 roundup(length, ARCH_DMA_MINALIGN); 297 /* 298 * Strictly we only need to invalidate the "txrx_status" field 299 * for the following check, but on some platforms we cannot 300 * invalidate only 4 bytes, so we flush the entire descriptor, 301 * which is 16 bytes in total. This is safe because the 302 * individual descriptors in the array are each aligned to 303 * ARCH_DMA_MINALIGN and padded appropriately. 304 */ 305 invalidate_dcache_range(desc_start, desc_end); 306 307 /* Check if the descriptor is owned by CPU */ 308 if (desc_p->txrx_status & DESC_TXSTS_OWNBYDMA) { 309 printf("CPU not owner of tx frame\n"); 310 return -EPERM; 311 } 312 313 memcpy(desc_p->dmamac_addr, packet, length); 314 315 /* Flush data to be sent */ 316 flush_dcache_range(data_start, data_end); 317 318 #if defined(CONFIG_DW_ALTDESCRIPTOR) 319 desc_p->txrx_status |= DESC_TXSTS_TXFIRST | DESC_TXSTS_TXLAST; 320 desc_p->dmamac_cntl |= (length << DESC_TXCTRL_SIZE1SHFT) & 321 DESC_TXCTRL_SIZE1MASK; 322 323 desc_p->txrx_status &= ~(DESC_TXSTS_MSK); 324 desc_p->txrx_status |= DESC_TXSTS_OWNBYDMA; 325 #else 326 desc_p->dmamac_cntl |= ((length << DESC_TXCTRL_SIZE1SHFT) & 327 DESC_TXCTRL_SIZE1MASK) | DESC_TXCTRL_TXLAST | 328 DESC_TXCTRL_TXFIRST; 329 330 desc_p->txrx_status = DESC_TXSTS_OWNBYDMA; 331 #endif 332 333 /* Flush modified buffer descriptor */ 334 flush_dcache_range(desc_start, desc_end); 335 336 /* Test the wrap-around condition. */ 337 if (++desc_num >= CONFIG_TX_DESCR_NUM) 338 desc_num = 0; 339 340 priv->tx_currdescnum = desc_num; 341 342 /* Start the transmission */ 343 writel(POLL_DATA, &dma_p->txpolldemand); 344 345 return 0; 346 } 347 348 static int _dw_eth_recv(struct dw_eth_dev *priv, uchar **packetp) 349 { 350 u32 status, desc_num = priv->rx_currdescnum; 351 struct dmamacdescr *desc_p = &priv->rx_mac_descrtable[desc_num]; 352 int length = -EAGAIN; 353 uint32_t desc_start = (uint32_t)desc_p; 354 uint32_t desc_end = desc_start + 355 roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN); 356 uint32_t data_start = (uint32_t)desc_p->dmamac_addr; 357 uint32_t data_end; 358 359 /* Invalidate entire buffer descriptor */ 360 invalidate_dcache_range(desc_start, desc_end); 361 362 status = desc_p->txrx_status; 363 364 /* Check if the owner is the CPU */ 365 if (!(status & DESC_RXSTS_OWNBYDMA)) { 366 367 length = (status & DESC_RXSTS_FRMLENMSK) >> 368 DESC_RXSTS_FRMLENSHFT; 369 370 /* Invalidate received data */ 371 data_end = data_start + roundup(length, ARCH_DMA_MINALIGN); 372 invalidate_dcache_range(data_start, data_end); 373 *packetp = desc_p->dmamac_addr; 374 } 375 376 return length; 377 } 378 379 static int _dw_free_pkt(struct dw_eth_dev *priv) 380 { 381 u32 desc_num = priv->rx_currdescnum; 382 struct dmamacdescr *desc_p = &priv->rx_mac_descrtable[desc_num]; 383 uint32_t desc_start = (uint32_t)desc_p; 384 uint32_t desc_end = desc_start + 385 roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN); 386 387 /* 388 * Make the current descriptor valid again and go to 389 * the next one 390 */ 391 desc_p->txrx_status |= DESC_RXSTS_OWNBYDMA; 392 393 /* Flush only status field - others weren't changed */ 394 flush_dcache_range(desc_start, desc_end); 395 396 /* Test the wrap-around condition. */ 397 if (++desc_num >= CONFIG_RX_DESCR_NUM) 398 desc_num = 0; 399 priv->rx_currdescnum = desc_num; 400 401 return 0; 402 } 403 404 static int dw_phy_init(struct dw_eth_dev *priv, void *dev) 405 { 406 struct phy_device *phydev; 407 int mask = 0xffffffff; 408 409 #ifdef CONFIG_PHY_ADDR 410 mask = 1 << CONFIG_PHY_ADDR; 411 #endif 412 413 phydev = phy_find_by_mask(priv->bus, mask, priv->interface); 414 if (!phydev) 415 return -ENODEV; 416 417 phy_connect_dev(phydev, dev); 418 419 phydev->supported &= PHY_GBIT_FEATURES; 420 phydev->advertising = phydev->supported; 421 422 priv->phydev = phydev; 423 phy_config(phydev); 424 425 return 0; 426 } 427 428 #ifndef CONFIG_DM_ETH 429 static int dw_eth_init(struct eth_device *dev, bd_t *bis) 430 { 431 return _dw_eth_init(dev->priv, dev->enetaddr); 432 } 433 434 static int dw_eth_send(struct eth_device *dev, void *packet, int length) 435 { 436 return _dw_eth_send(dev->priv, packet, length); 437 } 438 439 static int dw_eth_recv(struct eth_device *dev) 440 { 441 uchar *packet; 442 int length; 443 444 length = _dw_eth_recv(dev->priv, &packet); 445 if (length == -EAGAIN) 446 return 0; 447 net_process_received_packet(packet, length); 448 449 _dw_free_pkt(dev->priv); 450 451 return 0; 452 } 453 454 static void dw_eth_halt(struct eth_device *dev) 455 { 456 return _dw_eth_halt(dev->priv); 457 } 458 459 static int dw_write_hwaddr(struct eth_device *dev) 460 { 461 return _dw_write_hwaddr(dev->priv, dev->enetaddr); 462 } 463 464 int designware_initialize(ulong base_addr, u32 interface) 465 { 466 struct eth_device *dev; 467 struct dw_eth_dev *priv; 468 469 dev = (struct eth_device *) malloc(sizeof(struct eth_device)); 470 if (!dev) 471 return -ENOMEM; 472 473 /* 474 * Since the priv structure contains the descriptors which need a strict 475 * buswidth alignment, memalign is used to allocate memory 476 */ 477 priv = (struct dw_eth_dev *) memalign(ARCH_DMA_MINALIGN, 478 sizeof(struct dw_eth_dev)); 479 if (!priv) { 480 free(dev); 481 return -ENOMEM; 482 } 483 484 memset(dev, 0, sizeof(struct eth_device)); 485 memset(priv, 0, sizeof(struct dw_eth_dev)); 486 487 sprintf(dev->name, "dwmac.%lx", base_addr); 488 dev->iobase = (int)base_addr; 489 dev->priv = priv; 490 491 priv->dev = dev; 492 priv->mac_regs_p = (struct eth_mac_regs *)base_addr; 493 priv->dma_regs_p = (struct eth_dma_regs *)(base_addr + 494 DW_DMA_BASE_OFFSET); 495 496 dev->init = dw_eth_init; 497 dev->send = dw_eth_send; 498 dev->recv = dw_eth_recv; 499 dev->halt = dw_eth_halt; 500 dev->write_hwaddr = dw_write_hwaddr; 501 502 eth_register(dev); 503 504 priv->interface = interface; 505 506 dw_mdio_init(dev->name, priv->mac_regs_p); 507 priv->bus = miiphy_get_dev_by_name(dev->name); 508 509 return dw_phy_init(priv, dev); 510 } 511 #endif 512 513 #ifdef CONFIG_DM_ETH 514 static int designware_eth_start(struct udevice *dev) 515 { 516 struct eth_pdata *pdata = dev_get_platdata(dev); 517 518 return _dw_eth_init(dev->priv, pdata->enetaddr); 519 } 520 521 static int designware_eth_send(struct udevice *dev, void *packet, int length) 522 { 523 struct dw_eth_dev *priv = dev_get_priv(dev); 524 525 return _dw_eth_send(priv, packet, length); 526 } 527 528 static int designware_eth_recv(struct udevice *dev, int flags, uchar **packetp) 529 { 530 struct dw_eth_dev *priv = dev_get_priv(dev); 531 532 return _dw_eth_recv(priv, packetp); 533 } 534 535 static int designware_eth_free_pkt(struct udevice *dev, uchar *packet, 536 int length) 537 { 538 struct dw_eth_dev *priv = dev_get_priv(dev); 539 540 return _dw_free_pkt(priv); 541 } 542 543 static void designware_eth_stop(struct udevice *dev) 544 { 545 struct dw_eth_dev *priv = dev_get_priv(dev); 546 547 return _dw_eth_halt(priv); 548 } 549 550 static int designware_eth_write_hwaddr(struct udevice *dev) 551 { 552 struct eth_pdata *pdata = dev_get_platdata(dev); 553 struct dw_eth_dev *priv = dev_get_priv(dev); 554 555 return _dw_write_hwaddr(priv, pdata->enetaddr); 556 } 557 558 static int designware_eth_bind(struct udevice *dev) 559 { 560 #ifdef CONFIG_DM_PCI 561 static int num_cards; 562 char name[20]; 563 564 /* Create a unique device name for PCI type devices */ 565 if (device_is_on_pci_bus(dev)) { 566 sprintf(name, "eth_designware#%u", num_cards++); 567 device_set_name(dev, name); 568 } 569 #endif 570 571 return 0; 572 } 573 574 static int designware_eth_probe(struct udevice *dev) 575 { 576 struct eth_pdata *pdata = dev_get_platdata(dev); 577 struct dw_eth_dev *priv = dev_get_priv(dev); 578 u32 iobase = pdata->iobase; 579 int ret; 580 581 #ifdef CONFIG_DM_PCI 582 /* 583 * If we are on PCI bus, either directly attached to a PCI root port, 584 * or via a PCI bridge, fill in platdata before we probe the hardware. 585 */ 586 if (device_is_on_pci_bus(dev)) { 587 pci_dev_t bdf = dm_pci_get_bdf(dev); 588 589 dm_pci_read_config32(dev, PCI_BASE_ADDRESS_0, &iobase); 590 iobase &= PCI_BASE_ADDRESS_MEM_MASK; 591 iobase = pci_mem_to_phys(bdf, iobase); 592 593 pdata->iobase = iobase; 594 pdata->phy_interface = PHY_INTERFACE_MODE_RMII; 595 } 596 #endif 597 598 debug("%s, iobase=%x, priv=%p\n", __func__, iobase, priv); 599 priv->mac_regs_p = (struct eth_mac_regs *)iobase; 600 priv->dma_regs_p = (struct eth_dma_regs *)(iobase + DW_DMA_BASE_OFFSET); 601 priv->interface = pdata->phy_interface; 602 603 dw_mdio_init(dev->name, priv->mac_regs_p); 604 priv->bus = miiphy_get_dev_by_name(dev->name); 605 606 ret = dw_phy_init(priv, dev); 607 debug("%s, ret=%d\n", __func__, ret); 608 609 return ret; 610 } 611 612 static int designware_eth_remove(struct udevice *dev) 613 { 614 struct dw_eth_dev *priv = dev_get_priv(dev); 615 616 free(priv->phydev); 617 mdio_unregister(priv->bus); 618 mdio_free(priv->bus); 619 620 return 0; 621 } 622 623 static const struct eth_ops designware_eth_ops = { 624 .start = designware_eth_start, 625 .send = designware_eth_send, 626 .recv = designware_eth_recv, 627 .free_pkt = designware_eth_free_pkt, 628 .stop = designware_eth_stop, 629 .write_hwaddr = designware_eth_write_hwaddr, 630 }; 631 632 static int designware_eth_ofdata_to_platdata(struct udevice *dev) 633 { 634 struct eth_pdata *pdata = dev_get_platdata(dev); 635 const char *phy_mode; 636 637 pdata->iobase = dev_get_addr(dev); 638 pdata->phy_interface = -1; 639 phy_mode = fdt_getprop(gd->fdt_blob, dev->of_offset, "phy-mode", NULL); 640 if (phy_mode) 641 pdata->phy_interface = phy_get_interface_by_name(phy_mode); 642 if (pdata->phy_interface == -1) { 643 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode); 644 return -EINVAL; 645 } 646 647 return 0; 648 } 649 650 static const struct udevice_id designware_eth_ids[] = { 651 { .compatible = "allwinner,sun7i-a20-gmac" }, 652 { .compatible = "altr,socfpga-stmmac" }, 653 { } 654 }; 655 656 U_BOOT_DRIVER(eth_designware) = { 657 .name = "eth_designware", 658 .id = UCLASS_ETH, 659 .of_match = designware_eth_ids, 660 .ofdata_to_platdata = designware_eth_ofdata_to_platdata, 661 .bind = designware_eth_bind, 662 .probe = designware_eth_probe, 663 .remove = designware_eth_remove, 664 .ops = &designware_eth_ops, 665 .priv_auto_alloc_size = sizeof(struct dw_eth_dev), 666 .platdata_auto_alloc_size = sizeof(struct eth_pdata), 667 .flags = DM_FLAG_ALLOC_PRIV_DMA, 668 }; 669 670 static struct pci_device_id supported[] = { 671 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QRK_EMAC) }, 672 { } 673 }; 674 675 U_BOOT_PCI_DEVICE(eth_designware, supported); 676 #endif 677