1 /* 2 * (C) Copyright 2010 3 * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 /* 9 * Designware ethernet IP driver for U-Boot 10 */ 11 12 #include <common.h> 13 #include <clk.h> 14 #include <dm.h> 15 #include <errno.h> 16 #include <miiphy.h> 17 #include <malloc.h> 18 #include <pci.h> 19 #include <linux/compiler.h> 20 #include <linux/err.h> 21 #include <linux/kernel.h> 22 #include <asm/io.h> 23 #include <power/regulator.h> 24 #include "designware.h" 25 26 DECLARE_GLOBAL_DATA_PTR; 27 28 static int dw_mdio_read(struct mii_dev *bus, int addr, int devad, int reg) 29 { 30 #ifdef CONFIG_DM_ETH 31 struct dw_eth_dev *priv = dev_get_priv((struct udevice *)bus->priv); 32 struct eth_mac_regs *mac_p = priv->mac_regs_p; 33 #else 34 struct eth_mac_regs *mac_p = bus->priv; 35 #endif 36 ulong start; 37 u16 miiaddr; 38 int timeout = CONFIG_MDIO_TIMEOUT; 39 40 miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) | 41 ((reg << MIIREGSHIFT) & MII_REGMSK); 42 43 writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr); 44 45 start = get_timer(0); 46 while (get_timer(start) < timeout) { 47 if (!(readl(&mac_p->miiaddr) & MII_BUSY)) 48 return readl(&mac_p->miidata); 49 udelay(10); 50 }; 51 52 return -ETIMEDOUT; 53 } 54 55 static int dw_mdio_write(struct mii_dev *bus, int addr, int devad, int reg, 56 u16 val) 57 { 58 #ifdef CONFIG_DM_ETH 59 struct dw_eth_dev *priv = dev_get_priv((struct udevice *)bus->priv); 60 struct eth_mac_regs *mac_p = priv->mac_regs_p; 61 #else 62 struct eth_mac_regs *mac_p = bus->priv; 63 #endif 64 ulong start; 65 u16 miiaddr; 66 int ret = -ETIMEDOUT, timeout = CONFIG_MDIO_TIMEOUT; 67 68 writel(val, &mac_p->miidata); 69 miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) | 70 ((reg << MIIREGSHIFT) & MII_REGMSK) | MII_WRITE; 71 72 writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr); 73 74 start = get_timer(0); 75 while (get_timer(start) < timeout) { 76 if (!(readl(&mac_p->miiaddr) & MII_BUSY)) { 77 ret = 0; 78 break; 79 } 80 udelay(10); 81 }; 82 83 return ret; 84 } 85 86 #if defined(CONFIG_DM_ETH) && defined(CONFIG_DM_GPIO) 87 static int dw_mdio_reset(struct mii_dev *bus) 88 { 89 struct udevice *dev = bus->priv; 90 struct dw_eth_dev *priv = dev_get_priv(dev); 91 struct dw_eth_pdata *pdata = dev_get_platdata(dev); 92 int ret; 93 94 if (!dm_gpio_is_valid(&priv->reset_gpio)) 95 return 0; 96 97 /* reset the phy */ 98 ret = dm_gpio_set_value(&priv->reset_gpio, 0); 99 if (ret) 100 return ret; 101 102 udelay(pdata->reset_delays[0]); 103 104 ret = dm_gpio_set_value(&priv->reset_gpio, 1); 105 if (ret) 106 return ret; 107 108 udelay(pdata->reset_delays[1]); 109 110 ret = dm_gpio_set_value(&priv->reset_gpio, 0); 111 if (ret) 112 return ret; 113 114 udelay(pdata->reset_delays[2]); 115 116 return 0; 117 } 118 #endif 119 120 static int dw_mdio_init(const char *name, void *priv) 121 { 122 struct mii_dev *bus = mdio_alloc(); 123 124 if (!bus) { 125 printf("Failed to allocate MDIO bus\n"); 126 return -ENOMEM; 127 } 128 129 bus->read = dw_mdio_read; 130 bus->write = dw_mdio_write; 131 snprintf(bus->name, sizeof(bus->name), "%s", name); 132 #if defined(CONFIG_DM_ETH) && defined(CONFIG_DM_GPIO) 133 bus->reset = dw_mdio_reset; 134 #endif 135 136 bus->priv = priv; 137 138 return mdio_register(bus); 139 } 140 141 static void tx_descs_init(struct dw_eth_dev *priv) 142 { 143 struct eth_dma_regs *dma_p = priv->dma_regs_p; 144 struct dmamacdescr *desc_table_p = &priv->tx_mac_descrtable[0]; 145 char *txbuffs = &priv->txbuffs[0]; 146 struct dmamacdescr *desc_p; 147 u32 idx; 148 149 for (idx = 0; idx < CONFIG_TX_DESCR_NUM; idx++) { 150 desc_p = &desc_table_p[idx]; 151 desc_p->dmamac_addr = (ulong)&txbuffs[idx * CONFIG_ETH_BUFSIZE]; 152 desc_p->dmamac_next = (ulong)&desc_table_p[idx + 1]; 153 154 #if defined(CONFIG_DW_ALTDESCRIPTOR) 155 desc_p->txrx_status &= ~(DESC_TXSTS_TXINT | DESC_TXSTS_TXLAST | 156 DESC_TXSTS_TXFIRST | DESC_TXSTS_TXCRCDIS | 157 DESC_TXSTS_TXCHECKINSCTRL | 158 DESC_TXSTS_TXRINGEND | DESC_TXSTS_TXPADDIS); 159 160 desc_p->txrx_status |= DESC_TXSTS_TXCHAIN; 161 desc_p->dmamac_cntl = 0; 162 desc_p->txrx_status &= ~(DESC_TXSTS_MSK | DESC_TXSTS_OWNBYDMA); 163 #else 164 desc_p->dmamac_cntl = DESC_TXCTRL_TXCHAIN; 165 desc_p->txrx_status = 0; 166 #endif 167 } 168 169 /* Correcting the last pointer of the chain */ 170 desc_p->dmamac_next = (ulong)&desc_table_p[0]; 171 172 /* Flush all Tx buffer descriptors at once */ 173 flush_dcache_range((ulong)priv->tx_mac_descrtable, 174 (ulong)priv->tx_mac_descrtable + 175 sizeof(priv->tx_mac_descrtable)); 176 177 writel((ulong)&desc_table_p[0], &dma_p->txdesclistaddr); 178 priv->tx_currdescnum = 0; 179 } 180 181 static void rx_descs_init(struct dw_eth_dev *priv) 182 { 183 struct eth_dma_regs *dma_p = priv->dma_regs_p; 184 struct dmamacdescr *desc_table_p = &priv->rx_mac_descrtable[0]; 185 char *rxbuffs = &priv->rxbuffs[0]; 186 struct dmamacdescr *desc_p; 187 u32 idx; 188 189 /* Before passing buffers to GMAC we need to make sure zeros 190 * written there right after "priv" structure allocation were 191 * flushed into RAM. 192 * Otherwise there's a chance to get some of them flushed in RAM when 193 * GMAC is already pushing data to RAM via DMA. This way incoming from 194 * GMAC data will be corrupted. */ 195 flush_dcache_range((ulong)rxbuffs, (ulong)rxbuffs + RX_TOTAL_BUFSIZE); 196 197 for (idx = 0; idx < CONFIG_RX_DESCR_NUM; idx++) { 198 desc_p = &desc_table_p[idx]; 199 desc_p->dmamac_addr = (ulong)&rxbuffs[idx * CONFIG_ETH_BUFSIZE]; 200 desc_p->dmamac_next = (ulong)&desc_table_p[idx + 1]; 201 202 desc_p->dmamac_cntl = 203 (MAC_MAX_FRAME_SZ & DESC_RXCTRL_SIZE1MASK) | 204 DESC_RXCTRL_RXCHAIN; 205 206 desc_p->txrx_status = DESC_RXSTS_OWNBYDMA; 207 } 208 209 /* Correcting the last pointer of the chain */ 210 desc_p->dmamac_next = (ulong)&desc_table_p[0]; 211 212 /* Flush all Rx buffer descriptors at once */ 213 flush_dcache_range((ulong)priv->rx_mac_descrtable, 214 (ulong)priv->rx_mac_descrtable + 215 sizeof(priv->rx_mac_descrtable)); 216 217 writel((ulong)&desc_table_p[0], &dma_p->rxdesclistaddr); 218 priv->rx_currdescnum = 0; 219 } 220 221 static int _dw_write_hwaddr(struct dw_eth_dev *priv, u8 *mac_id) 222 { 223 struct eth_mac_regs *mac_p = priv->mac_regs_p; 224 u32 macid_lo, macid_hi; 225 226 macid_lo = mac_id[0] + (mac_id[1] << 8) + (mac_id[2] << 16) + 227 (mac_id[3] << 24); 228 macid_hi = mac_id[4] + (mac_id[5] << 8); 229 230 writel(macid_hi, &mac_p->macaddr0hi); 231 writel(macid_lo, &mac_p->macaddr0lo); 232 233 return 0; 234 } 235 236 static int dw_adjust_link(struct dw_eth_dev *priv, struct eth_mac_regs *mac_p, 237 struct phy_device *phydev) 238 { 239 u32 conf = readl(&mac_p->conf) | FRAMEBURSTENABLE | DISABLERXOWN; 240 241 if (!phydev->link) { 242 printf("%s: No link.\n", phydev->dev->name); 243 return 0; 244 } 245 246 if (phydev->speed != 1000) 247 conf |= MII_PORTSELECT; 248 else 249 conf &= ~MII_PORTSELECT; 250 251 if (phydev->speed == 100) 252 conf |= FES_100; 253 254 if (phydev->duplex) 255 conf |= FULLDPLXMODE; 256 257 writel(conf, &mac_p->conf); 258 259 printf("Speed: %d, %s duplex%s\n", phydev->speed, 260 (phydev->duplex) ? "full" : "half", 261 (phydev->port == PORT_FIBRE) ? ", fiber mode" : ""); 262 263 return 0; 264 } 265 266 static void _dw_eth_halt(struct dw_eth_dev *priv) 267 { 268 struct eth_mac_regs *mac_p = priv->mac_regs_p; 269 struct eth_dma_regs *dma_p = priv->dma_regs_p; 270 271 writel(readl(&mac_p->conf) & ~(RXENABLE | TXENABLE), &mac_p->conf); 272 writel(readl(&dma_p->opmode) & ~(RXSTART | TXSTART), &dma_p->opmode); 273 274 phy_shutdown(priv->phydev); 275 } 276 277 int designware_eth_init(struct dw_eth_dev *priv, u8 *enetaddr) 278 { 279 struct eth_mac_regs *mac_p = priv->mac_regs_p; 280 struct eth_dma_regs *dma_p = priv->dma_regs_p; 281 unsigned int start; 282 int ret; 283 284 writel(readl(&dma_p->busmode) | DMAMAC_SRST, &dma_p->busmode); 285 286 start = get_timer(0); 287 while (readl(&dma_p->busmode) & DMAMAC_SRST) { 288 if (get_timer(start) >= CONFIG_MACRESET_TIMEOUT) { 289 printf("DMA reset timeout\n"); 290 return -ETIMEDOUT; 291 } 292 293 mdelay(100); 294 }; 295 296 /* 297 * Soft reset above clears HW address registers. 298 * So we have to set it here once again. 299 */ 300 _dw_write_hwaddr(priv, enetaddr); 301 302 rx_descs_init(priv); 303 tx_descs_init(priv); 304 305 writel(FIXEDBURST | PRIORXTX_41 | DMA_PBL, &dma_p->busmode); 306 307 #ifndef CONFIG_DW_MAC_FORCE_THRESHOLD_MODE 308 writel(readl(&dma_p->opmode) | FLUSHTXFIFO | STOREFORWARD, 309 &dma_p->opmode); 310 #else 311 writel(readl(&dma_p->opmode) | FLUSHTXFIFO, 312 &dma_p->opmode); 313 #endif 314 315 writel(readl(&dma_p->opmode) | RXSTART | TXSTART, &dma_p->opmode); 316 317 #ifdef CONFIG_DW_AXI_BURST_LEN 318 writel((CONFIG_DW_AXI_BURST_LEN & 0x1FF >> 1), &dma_p->axibus); 319 #endif 320 321 /* Start up the PHY */ 322 ret = phy_startup(priv->phydev); 323 if (ret) { 324 printf("Could not initialize PHY %s\n", 325 priv->phydev->dev->name); 326 return ret; 327 } 328 329 ret = dw_adjust_link(priv, mac_p, priv->phydev); 330 if (ret) 331 return ret; 332 333 return 0; 334 } 335 336 int designware_eth_enable(struct dw_eth_dev *priv) 337 { 338 struct eth_mac_regs *mac_p = priv->mac_regs_p; 339 340 if (!priv->phydev->link) 341 return -EIO; 342 343 writel(readl(&mac_p->conf) | RXENABLE | TXENABLE, &mac_p->conf); 344 345 return 0; 346 } 347 348 #define ETH_ZLEN 60 349 350 static int _dw_eth_send(struct dw_eth_dev *priv, void *packet, int length) 351 { 352 struct eth_dma_regs *dma_p = priv->dma_regs_p; 353 u32 desc_num = priv->tx_currdescnum; 354 struct dmamacdescr *desc_p = &priv->tx_mac_descrtable[desc_num]; 355 ulong desc_start = (ulong)desc_p; 356 ulong desc_end = desc_start + 357 roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN); 358 ulong data_start = desc_p->dmamac_addr; 359 ulong data_end = data_start + roundup(length, ARCH_DMA_MINALIGN); 360 /* 361 * Strictly we only need to invalidate the "txrx_status" field 362 * for the following check, but on some platforms we cannot 363 * invalidate only 4 bytes, so we flush the entire descriptor, 364 * which is 16 bytes in total. This is safe because the 365 * individual descriptors in the array are each aligned to 366 * ARCH_DMA_MINALIGN and padded appropriately. 367 */ 368 invalidate_dcache_range(desc_start, desc_end); 369 370 /* Check if the descriptor is owned by CPU */ 371 if (desc_p->txrx_status & DESC_TXSTS_OWNBYDMA) { 372 printf("CPU not owner of tx frame\n"); 373 return -EPERM; 374 } 375 376 length = max(length, ETH_ZLEN); 377 378 memcpy((void *)data_start, packet, length); 379 380 /* Flush data to be sent */ 381 flush_dcache_range(data_start, data_end); 382 383 #if defined(CONFIG_DW_ALTDESCRIPTOR) 384 desc_p->txrx_status |= DESC_TXSTS_TXFIRST | DESC_TXSTS_TXLAST; 385 desc_p->dmamac_cntl |= (length << DESC_TXCTRL_SIZE1SHFT) & 386 DESC_TXCTRL_SIZE1MASK; 387 388 desc_p->txrx_status &= ~(DESC_TXSTS_MSK); 389 desc_p->txrx_status |= DESC_TXSTS_OWNBYDMA; 390 #else 391 desc_p->dmamac_cntl |= ((length << DESC_TXCTRL_SIZE1SHFT) & 392 DESC_TXCTRL_SIZE1MASK) | DESC_TXCTRL_TXLAST | 393 DESC_TXCTRL_TXFIRST; 394 395 desc_p->txrx_status = DESC_TXSTS_OWNBYDMA; 396 #endif 397 398 /* Flush modified buffer descriptor */ 399 flush_dcache_range(desc_start, desc_end); 400 401 /* Test the wrap-around condition. */ 402 if (++desc_num >= CONFIG_TX_DESCR_NUM) 403 desc_num = 0; 404 405 priv->tx_currdescnum = desc_num; 406 407 /* Start the transmission */ 408 writel(POLL_DATA, &dma_p->txpolldemand); 409 410 return 0; 411 } 412 413 static int _dw_eth_recv(struct dw_eth_dev *priv, uchar **packetp) 414 { 415 u32 status, desc_num = priv->rx_currdescnum; 416 struct dmamacdescr *desc_p = &priv->rx_mac_descrtable[desc_num]; 417 int length = -EAGAIN; 418 ulong desc_start = (ulong)desc_p; 419 ulong desc_end = desc_start + 420 roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN); 421 ulong data_start = desc_p->dmamac_addr; 422 ulong data_end; 423 424 /* Invalidate entire buffer descriptor */ 425 invalidate_dcache_range(desc_start, desc_end); 426 427 status = desc_p->txrx_status; 428 429 /* Check if the owner is the CPU */ 430 if (!(status & DESC_RXSTS_OWNBYDMA)) { 431 432 length = (status & DESC_RXSTS_FRMLENMSK) >> 433 DESC_RXSTS_FRMLENSHFT; 434 435 /* Invalidate received data */ 436 data_end = data_start + roundup(length, ARCH_DMA_MINALIGN); 437 invalidate_dcache_range(data_start, data_end); 438 *packetp = (uchar *)(ulong)desc_p->dmamac_addr; 439 } 440 441 return length; 442 } 443 444 static int _dw_free_pkt(struct dw_eth_dev *priv) 445 { 446 u32 desc_num = priv->rx_currdescnum; 447 struct dmamacdescr *desc_p = &priv->rx_mac_descrtable[desc_num]; 448 ulong desc_start = (ulong)desc_p; 449 ulong desc_end = desc_start + 450 roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN); 451 452 /* 453 * Make the current descriptor valid again and go to 454 * the next one 455 */ 456 desc_p->txrx_status |= DESC_RXSTS_OWNBYDMA; 457 458 /* Flush only status field - others weren't changed */ 459 flush_dcache_range(desc_start, desc_end); 460 461 /* Test the wrap-around condition. */ 462 if (++desc_num >= CONFIG_RX_DESCR_NUM) 463 desc_num = 0; 464 priv->rx_currdescnum = desc_num; 465 466 return 0; 467 } 468 469 static int dw_phy_init(struct dw_eth_dev *priv, void *dev) 470 { 471 struct phy_device *phydev; 472 int mask = 0xffffffff, ret; 473 474 #ifdef CONFIG_PHY_ADDR 475 mask = 1 << CONFIG_PHY_ADDR; 476 #endif 477 478 phydev = phy_find_by_mask(priv->bus, mask, priv->interface); 479 if (!phydev) 480 return -ENODEV; 481 482 phy_connect_dev(phydev, dev); 483 484 phydev->supported &= PHY_GBIT_FEATURES; 485 if (priv->max_speed) { 486 ret = phy_set_supported(phydev, priv->max_speed); 487 if (ret) 488 return ret; 489 } 490 phydev->advertising = phydev->supported; 491 492 priv->phydev = phydev; 493 phy_config(phydev); 494 495 return 0; 496 } 497 498 #ifndef CONFIG_DM_ETH 499 static int dw_eth_init(struct eth_device *dev, bd_t *bis) 500 { 501 int ret; 502 503 ret = designware_eth_init(dev->priv, dev->enetaddr); 504 if (!ret) 505 ret = designware_eth_enable(dev->priv); 506 507 return ret; 508 } 509 510 static int dw_eth_send(struct eth_device *dev, void *packet, int length) 511 { 512 return _dw_eth_send(dev->priv, packet, length); 513 } 514 515 static int dw_eth_recv(struct eth_device *dev) 516 { 517 uchar *packet; 518 int length; 519 520 length = _dw_eth_recv(dev->priv, &packet); 521 if (length == -EAGAIN) 522 return 0; 523 net_process_received_packet(packet, length); 524 525 _dw_free_pkt(dev->priv); 526 527 return 0; 528 } 529 530 static void dw_eth_halt(struct eth_device *dev) 531 { 532 return _dw_eth_halt(dev->priv); 533 } 534 535 static int dw_write_hwaddr(struct eth_device *dev) 536 { 537 return _dw_write_hwaddr(dev->priv, dev->enetaddr); 538 } 539 540 int designware_initialize(ulong base_addr, u32 interface) 541 { 542 struct eth_device *dev; 543 struct dw_eth_dev *priv; 544 545 dev = (struct eth_device *) malloc(sizeof(struct eth_device)); 546 if (!dev) 547 return -ENOMEM; 548 549 /* 550 * Since the priv structure contains the descriptors which need a strict 551 * buswidth alignment, memalign is used to allocate memory 552 */ 553 priv = (struct dw_eth_dev *) memalign(ARCH_DMA_MINALIGN, 554 sizeof(struct dw_eth_dev)); 555 if (!priv) { 556 free(dev); 557 return -ENOMEM; 558 } 559 560 if ((phys_addr_t)priv + sizeof(*priv) > (1ULL << 32)) { 561 printf("designware: buffers are outside DMA memory\n"); 562 return -EINVAL; 563 } 564 565 memset(dev, 0, sizeof(struct eth_device)); 566 memset(priv, 0, sizeof(struct dw_eth_dev)); 567 568 sprintf(dev->name, "dwmac.%lx", base_addr); 569 dev->iobase = (int)base_addr; 570 dev->priv = priv; 571 572 priv->dev = dev; 573 priv->mac_regs_p = (struct eth_mac_regs *)base_addr; 574 priv->dma_regs_p = (struct eth_dma_regs *)(base_addr + 575 DW_DMA_BASE_OFFSET); 576 577 dev->init = dw_eth_init; 578 dev->send = dw_eth_send; 579 dev->recv = dw_eth_recv; 580 dev->halt = dw_eth_halt; 581 dev->write_hwaddr = dw_write_hwaddr; 582 583 eth_register(dev); 584 585 priv->interface = interface; 586 587 dw_mdio_init(dev->name, priv->mac_regs_p); 588 priv->bus = miiphy_get_dev_by_name(dev->name); 589 590 return dw_phy_init(priv, dev); 591 } 592 #endif 593 594 #ifdef CONFIG_DM_ETH 595 static int designware_eth_start(struct udevice *dev) 596 { 597 struct eth_pdata *pdata = dev_get_platdata(dev); 598 struct dw_eth_dev *priv = dev_get_priv(dev); 599 int ret; 600 601 ret = designware_eth_init(priv, pdata->enetaddr); 602 if (ret) 603 return ret; 604 ret = designware_eth_enable(priv); 605 if (ret) 606 return ret; 607 608 return 0; 609 } 610 611 int designware_eth_send(struct udevice *dev, void *packet, int length) 612 { 613 struct dw_eth_dev *priv = dev_get_priv(dev); 614 615 return _dw_eth_send(priv, packet, length); 616 } 617 618 int designware_eth_recv(struct udevice *dev, int flags, uchar **packetp) 619 { 620 struct dw_eth_dev *priv = dev_get_priv(dev); 621 622 return _dw_eth_recv(priv, packetp); 623 } 624 625 int designware_eth_free_pkt(struct udevice *dev, uchar *packet, int length) 626 { 627 struct dw_eth_dev *priv = dev_get_priv(dev); 628 629 return _dw_free_pkt(priv); 630 } 631 632 void designware_eth_stop(struct udevice *dev) 633 { 634 struct dw_eth_dev *priv = dev_get_priv(dev); 635 636 return _dw_eth_halt(priv); 637 } 638 639 int designware_eth_write_hwaddr(struct udevice *dev) 640 { 641 struct eth_pdata *pdata = dev_get_platdata(dev); 642 struct dw_eth_dev *priv = dev_get_priv(dev); 643 644 return _dw_write_hwaddr(priv, pdata->enetaddr); 645 } 646 647 static int designware_eth_bind(struct udevice *dev) 648 { 649 #ifdef CONFIG_DM_PCI 650 static int num_cards; 651 char name[20]; 652 653 /* Create a unique device name for PCI type devices */ 654 if (device_is_on_pci_bus(dev)) { 655 sprintf(name, "eth_designware#%u", num_cards++); 656 device_set_name(dev, name); 657 } 658 #endif 659 660 return 0; 661 } 662 663 int designware_eth_probe(struct udevice *dev) 664 { 665 struct eth_pdata *pdata = dev_get_platdata(dev); 666 struct dw_eth_dev *priv = dev_get_priv(dev); 667 u32 iobase = pdata->iobase; 668 ulong ioaddr; 669 int ret; 670 #ifdef CONFIG_CLK 671 int i, err, clock_nb; 672 673 priv->clock_count = 0; 674 clock_nb = dev_count_phandle_with_args(dev, "clocks", "#clock-cells"); 675 if (clock_nb > 0) { 676 priv->clocks = devm_kcalloc(dev, clock_nb, sizeof(struct clk), 677 GFP_KERNEL); 678 if (!priv->clocks) 679 return -ENOMEM; 680 681 for (i = 0; i < clock_nb; i++) { 682 err = clk_get_by_index(dev, i, &priv->clocks[i]); 683 if (err < 0) 684 break; 685 686 err = clk_enable(&priv->clocks[i]); 687 if (err) { 688 pr_err("failed to enable clock %d\n", i); 689 clk_free(&priv->clocks[i]); 690 goto clk_err; 691 } 692 priv->clock_count++; 693 } 694 } else if (clock_nb != -ENOENT) { 695 pr_err("failed to get clock phandle(%d)\n", clock_nb); 696 return clock_nb; 697 } 698 #endif 699 700 #if defined(CONFIG_DM_REGULATOR) 701 struct udevice *phy_supply; 702 703 ret = device_get_supply_regulator(dev, "phy-supply", 704 &phy_supply); 705 if (ret) { 706 debug("%s: No phy supply\n", dev->name); 707 } else { 708 ret = regulator_set_enable(phy_supply, true); 709 if (ret) { 710 puts("Error enabling phy supply\n"); 711 return ret; 712 } 713 } 714 #endif 715 716 #ifdef CONFIG_DM_PCI 717 /* 718 * If we are on PCI bus, either directly attached to a PCI root port, 719 * or via a PCI bridge, fill in platdata before we probe the hardware. 720 */ 721 if (device_is_on_pci_bus(dev)) { 722 dm_pci_read_config32(dev, PCI_BASE_ADDRESS_0, &iobase); 723 iobase &= PCI_BASE_ADDRESS_MEM_MASK; 724 iobase = dm_pci_mem_to_phys(dev, iobase); 725 726 pdata->iobase = iobase; 727 pdata->phy_interface = PHY_INTERFACE_MODE_RMII; 728 } 729 #endif 730 731 debug("%s, iobase=%x, priv=%p\n", __func__, iobase, priv); 732 ioaddr = iobase; 733 priv->mac_regs_p = (struct eth_mac_regs *)ioaddr; 734 priv->dma_regs_p = (struct eth_dma_regs *)(ioaddr + DW_DMA_BASE_OFFSET); 735 priv->interface = pdata->phy_interface; 736 priv->max_speed = pdata->max_speed; 737 738 dw_mdio_init(dev->name, dev); 739 priv->bus = miiphy_get_dev_by_name(dev->name); 740 741 ret = dw_phy_init(priv, dev); 742 debug("%s, ret=%d\n", __func__, ret); 743 744 return ret; 745 746 #ifdef CONFIG_CLK 747 clk_err: 748 ret = clk_release_all(priv->clocks, priv->clock_count); 749 if (ret) 750 pr_err("failed to disable all clocks\n"); 751 752 return err; 753 #endif 754 } 755 756 static int designware_eth_remove(struct udevice *dev) 757 { 758 struct dw_eth_dev *priv = dev_get_priv(dev); 759 760 free(priv->phydev); 761 mdio_unregister(priv->bus); 762 mdio_free(priv->bus); 763 764 #ifdef CONFIG_CLK 765 return clk_release_all(priv->clocks, priv->clock_count); 766 #else 767 return 0; 768 #endif 769 } 770 771 const struct eth_ops designware_eth_ops = { 772 .start = designware_eth_start, 773 .send = designware_eth_send, 774 .recv = designware_eth_recv, 775 .free_pkt = designware_eth_free_pkt, 776 .stop = designware_eth_stop, 777 .write_hwaddr = designware_eth_write_hwaddr, 778 }; 779 780 int designware_eth_ofdata_to_platdata(struct udevice *dev) 781 { 782 struct dw_eth_pdata *dw_pdata = dev_get_platdata(dev); 783 #ifdef CONFIG_DM_GPIO 784 struct dw_eth_dev *priv = dev_get_priv(dev); 785 #endif 786 struct eth_pdata *pdata = &dw_pdata->eth_pdata; 787 const char *phy_mode; 788 #ifdef CONFIG_DM_GPIO 789 int reset_flags = GPIOD_IS_OUT; 790 #endif 791 int ret = 0; 792 793 pdata->iobase = dev_read_addr(dev); 794 pdata->phy_interface = -1; 795 phy_mode = dev_read_string(dev, "phy-mode"); 796 if (phy_mode) 797 pdata->phy_interface = phy_get_interface_by_name(phy_mode); 798 if (pdata->phy_interface == -1) { 799 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode); 800 return -EINVAL; 801 } 802 803 pdata->max_speed = dev_read_u32_default(dev, "max-speed", 0); 804 805 #ifdef CONFIG_DM_GPIO 806 if (dev_read_bool(dev, "snps,reset-active-low")) 807 reset_flags |= GPIOD_ACTIVE_LOW; 808 809 ret = gpio_request_by_name(dev, "snps,reset-gpio", 0, 810 &priv->reset_gpio, reset_flags); 811 if (ret == 0) { 812 ret = dev_read_u32_array(dev, "snps,reset-delays-us", 813 dw_pdata->reset_delays, 3); 814 } else if (ret == -ENOENT) { 815 ret = 0; 816 } 817 #endif 818 819 return ret; 820 } 821 822 static const struct udevice_id designware_eth_ids[] = { 823 { .compatible = "allwinner,sun7i-a20-gmac" }, 824 { .compatible = "altr,socfpga-stmmac" }, 825 { .compatible = "amlogic,meson6-dwmac" }, 826 { .compatible = "amlogic,meson-gx-dwmac" }, 827 { .compatible = "st,stm32-dwmac" }, 828 { } 829 }; 830 831 U_BOOT_DRIVER(eth_designware) = { 832 .name = "eth_designware", 833 .id = UCLASS_ETH, 834 .of_match = designware_eth_ids, 835 .ofdata_to_platdata = designware_eth_ofdata_to_platdata, 836 .bind = designware_eth_bind, 837 .probe = designware_eth_probe, 838 .remove = designware_eth_remove, 839 .ops = &designware_eth_ops, 840 .priv_auto_alloc_size = sizeof(struct dw_eth_dev), 841 .platdata_auto_alloc_size = sizeof(struct dw_eth_pdata), 842 .flags = DM_FLAG_ALLOC_PRIV_DMA, 843 }; 844 845 static struct pci_device_id supported[] = { 846 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QRK_EMAC) }, 847 { } 848 }; 849 850 U_BOOT_PCI_DEVICE(eth_designware, supported); 851 #endif 852