1 /* 2 * See file CREDITS for list of people who contributed to this 3 * project. 4 * 5 * This program is free software; you can redistribute it and/or 6 * modify it under the terms of the GNU General Public License as 7 * published by the Free Software Foundation; either version 2 of 8 * the License, or (at your option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, write to the Free Software 17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 18 * MA 02111-1307 USA 19 */ 20 21 #include <common.h> 22 23 #if defined(CONFIG_CMD_NET) \ 24 && defined(CONFIG_NET_MULTI) && defined(CONFIG_TULIP) 25 26 #include <malloc.h> 27 #include <net.h> 28 #include <pci.h> 29 30 #undef DEBUG_SROM 31 #undef DEBUG_SROM2 32 33 #undef UPDATE_SROM 34 35 /* PCI Registers. 36 */ 37 #define PCI_CFDA_PSM 0x43 38 39 #define CFRV_RN 0x000000f0 /* Revision Number */ 40 41 #define WAKEUP 0x00 /* Power Saving Wakeup */ 42 #define SLEEP 0x80 /* Power Saving Sleep Mode */ 43 44 #define DC2114x_BRK 0x0020 /* CFRV break between DC21142 & DC21143 */ 45 46 /* Ethernet chip registers. 47 */ 48 #define DE4X5_BMR 0x000 /* Bus Mode Register */ 49 #define DE4X5_TPD 0x008 /* Transmit Poll Demand Reg */ 50 #define DE4X5_RRBA 0x018 /* RX Ring Base Address Reg */ 51 #define DE4X5_TRBA 0x020 /* TX Ring Base Address Reg */ 52 #define DE4X5_STS 0x028 /* Status Register */ 53 #define DE4X5_OMR 0x030 /* Operation Mode Register */ 54 #define DE4X5_SICR 0x068 /* SIA Connectivity Register */ 55 #define DE4X5_APROM 0x048 /* Ethernet Address PROM */ 56 57 /* Register bits. 58 */ 59 #define BMR_SWR 0x00000001 /* Software Reset */ 60 #define STS_TS 0x00700000 /* Transmit Process State */ 61 #define STS_RS 0x000e0000 /* Receive Process State */ 62 #define OMR_ST 0x00002000 /* Start/Stop Transmission Command */ 63 #define OMR_SR 0x00000002 /* Start/Stop Receive */ 64 #define OMR_PS 0x00040000 /* Port Select */ 65 #define OMR_SDP 0x02000000 /* SD Polarity - MUST BE ASSERTED */ 66 #define OMR_PM 0x00000080 /* Pass All Multicast */ 67 68 /* Descriptor bits. 69 */ 70 #define R_OWN 0x80000000 /* Own Bit */ 71 #define RD_RER 0x02000000 /* Receive End Of Ring */ 72 #define RD_LS 0x00000100 /* Last Descriptor */ 73 #define RD_ES 0x00008000 /* Error Summary */ 74 #define TD_TER 0x02000000 /* Transmit End Of Ring */ 75 #define T_OWN 0x80000000 /* Own Bit */ 76 #define TD_LS 0x40000000 /* Last Segment */ 77 #define TD_FS 0x20000000 /* First Segment */ 78 #define TD_ES 0x00008000 /* Error Summary */ 79 #define TD_SET 0x08000000 /* Setup Packet */ 80 81 /* The EEPROM commands include the alway-set leading bit. */ 82 #define SROM_WRITE_CMD 5 83 #define SROM_READ_CMD 6 84 #define SROM_ERASE_CMD 7 85 86 #define SROM_HWADD 0x0014 /* Hardware Address offset in SROM */ 87 #define SROM_RD 0x00004000 /* Read from Boot ROM */ 88 #define EE_DATA_WRITE 0x04 /* EEPROM chip data in. */ 89 #define EE_WRITE_0 0x4801 90 #define EE_WRITE_1 0x4805 91 #define EE_DATA_READ 0x08 /* EEPROM chip data out. */ 92 #define SROM_SR 0x00000800 /* Select Serial ROM when set */ 93 94 #define DT_IN 0x00000004 /* Serial Data In */ 95 #define DT_CLK 0x00000002 /* Serial ROM Clock */ 96 #define DT_CS 0x00000001 /* Serial ROM Chip Select */ 97 98 #define POLL_DEMAND 1 99 100 #ifdef CONFIG_TULIP_FIX_DAVICOM 101 #define RESET_DM9102(dev) {\ 102 unsigned long i;\ 103 i=INL(dev, 0x0);\ 104 udelay(1000);\ 105 OUTL(dev, i | BMR_SWR, DE4X5_BMR);\ 106 udelay(1000);\ 107 } 108 #else 109 #define RESET_DE4X5(dev) {\ 110 int i;\ 111 i=INL(dev, DE4X5_BMR);\ 112 udelay(1000);\ 113 OUTL(dev, i | BMR_SWR, DE4X5_BMR);\ 114 udelay(1000);\ 115 OUTL(dev, i, DE4X5_BMR);\ 116 udelay(1000);\ 117 for (i=0;i<5;i++) {INL(dev, DE4X5_BMR); udelay(10000);}\ 118 udelay(1000);\ 119 } 120 #endif 121 122 #define START_DE4X5(dev) {\ 123 s32 omr; \ 124 omr = INL(dev, DE4X5_OMR);\ 125 omr |= OMR_ST | OMR_SR;\ 126 OUTL(dev, omr, DE4X5_OMR); /* Enable the TX and/or RX */\ 127 } 128 129 #define STOP_DE4X5(dev) {\ 130 s32 omr; \ 131 omr = INL(dev, DE4X5_OMR);\ 132 omr &= ~(OMR_ST|OMR_SR);\ 133 OUTL(dev, omr, DE4X5_OMR); /* Disable the TX and/or RX */ \ 134 } 135 136 #define NUM_RX_DESC PKTBUFSRX 137 #ifndef CONFIG_TULIP_FIX_DAVICOM 138 #define NUM_TX_DESC 1 /* Number of TX descriptors */ 139 #else 140 #define NUM_TX_DESC 4 141 #endif 142 #define RX_BUFF_SZ PKTSIZE_ALIGN 143 144 #define TOUT_LOOP 1000000 145 146 #define SETUP_FRAME_LEN 192 147 #define ETH_ALEN 6 148 149 struct de4x5_desc { 150 volatile s32 status; 151 u32 des1; 152 u32 buf; 153 u32 next; 154 }; 155 156 static struct de4x5_desc rx_ring[NUM_RX_DESC] __attribute__ ((aligned(32))); /* RX descriptor ring */ 157 static struct de4x5_desc tx_ring[NUM_TX_DESC] __attribute__ ((aligned(32))); /* TX descriptor ring */ 158 static int rx_new; /* RX descriptor ring pointer */ 159 static int tx_new; /* TX descriptor ring pointer */ 160 161 static char rxRingSize; 162 static char txRingSize; 163 164 #if defined(UPDATE_SROM) || !defined(CONFIG_TULIP_FIX_DAVICOM) 165 static void sendto_srom(struct eth_device* dev, u_int command, u_long addr); 166 static int getfrom_srom(struct eth_device* dev, u_long addr); 167 static int do_eeprom_cmd(struct eth_device *dev, u_long ioaddr,int cmd,int cmd_len); 168 static int do_read_eeprom(struct eth_device *dev,u_long ioaddr,int location,int addr_len); 169 #endif /* UPDATE_SROM || !CONFIG_TULIP_FIX_DAVICOM */ 170 #ifdef UPDATE_SROM 171 static int write_srom(struct eth_device *dev, u_long ioaddr, int index, int new_value); 172 static void update_srom(struct eth_device *dev, bd_t *bis); 173 #endif 174 #ifndef CONFIG_TULIP_FIX_DAVICOM 175 static int read_srom(struct eth_device *dev, u_long ioaddr, int index); 176 static void read_hw_addr(struct eth_device* dev, bd_t * bis); 177 #endif /* CONFIG_TULIP_FIX_DAVICOM */ 178 static void send_setup_frame(struct eth_device* dev, bd_t * bis); 179 180 static int dc21x4x_init(struct eth_device* dev, bd_t* bis); 181 static int dc21x4x_send(struct eth_device* dev, volatile void *packet, int length); 182 static int dc21x4x_recv(struct eth_device* dev); 183 static void dc21x4x_halt(struct eth_device* dev); 184 #ifdef CONFIG_TULIP_SELECT_MEDIA 185 extern void dc21x4x_select_media(struct eth_device* dev); 186 #endif 187 188 #if defined(CONFIG_E500) 189 #define phys_to_bus(a) (a) 190 #else 191 #define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)dev->priv, a) 192 #endif 193 194 static int INL(struct eth_device* dev, u_long addr) 195 { 196 return le32_to_cpu(*(volatile u_long *)(addr + dev->iobase)); 197 } 198 199 static void OUTL(struct eth_device* dev, int command, u_long addr) 200 { 201 *(volatile u_long *)(addr + dev->iobase) = cpu_to_le32(command); 202 } 203 204 static struct pci_device_id supported[] = { 205 { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TULIP_FAST }, 206 { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21142 }, 207 #ifdef CONFIG_TULIP_FIX_DAVICOM 208 { PCI_VENDOR_ID_DAVICOM, PCI_DEVICE_ID_DAVICOM_DM9102A }, 209 #endif 210 { } 211 }; 212 213 int dc21x4x_initialize(bd_t *bis) 214 { 215 int idx=0; 216 int card_number = 0; 217 unsigned int cfrv; 218 unsigned char timer; 219 pci_dev_t devbusfn; 220 unsigned int iobase; 221 unsigned short status; 222 struct eth_device* dev; 223 224 while(1) { 225 devbusfn = pci_find_devices(supported, idx++); 226 if (devbusfn == -1) { 227 break; 228 } 229 230 /* Get the chip configuration revision register. */ 231 pci_read_config_dword(devbusfn, PCI_REVISION_ID, &cfrv); 232 233 #ifndef CONFIG_TULIP_FIX_DAVICOM 234 if ((cfrv & CFRV_RN) < DC2114x_BRK ) { 235 printf("Error: The chip is not DC21143.\n"); 236 continue; 237 } 238 #endif 239 240 pci_read_config_word(devbusfn, PCI_COMMAND, &status); 241 status |= 242 #ifdef CONFIG_TULIP_USE_IO 243 PCI_COMMAND_IO | 244 #else 245 PCI_COMMAND_MEMORY | 246 #endif 247 PCI_COMMAND_MASTER; 248 pci_write_config_word(devbusfn, PCI_COMMAND, status); 249 250 pci_read_config_word(devbusfn, PCI_COMMAND, &status); 251 if (!(status & PCI_COMMAND_IO)) { 252 printf("Error: Can not enable I/O access.\n"); 253 continue; 254 } 255 256 if (!(status & PCI_COMMAND_IO)) { 257 printf("Error: Can not enable I/O access.\n"); 258 continue; 259 } 260 261 if (!(status & PCI_COMMAND_MASTER)) { 262 printf("Error: Can not enable Bus Mastering.\n"); 263 continue; 264 } 265 266 /* Check the latency timer for values >= 0x60. */ 267 pci_read_config_byte(devbusfn, PCI_LATENCY_TIMER, &timer); 268 269 if (timer < 0x60) { 270 pci_write_config_byte(devbusfn, PCI_LATENCY_TIMER, 0x60); 271 } 272 273 #ifdef CONFIG_TULIP_USE_IO 274 /* read BAR for memory space access */ 275 pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, &iobase); 276 iobase &= PCI_BASE_ADDRESS_IO_MASK; 277 #else 278 /* read BAR for memory space access */ 279 pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_1, &iobase); 280 iobase &= PCI_BASE_ADDRESS_MEM_MASK; 281 #endif 282 debug ("dc21x4x: DEC 21142 PCI Device @0x%x\n", iobase); 283 284 dev = (struct eth_device*) malloc(sizeof *dev); 285 286 #ifdef CONFIG_TULIP_FIX_DAVICOM 287 sprintf(dev->name, "Davicom#%d", card_number); 288 #else 289 sprintf(dev->name, "dc21x4x#%d", card_number); 290 #endif 291 292 #ifdef CONFIG_TULIP_USE_IO 293 dev->iobase = pci_io_to_phys(devbusfn, iobase); 294 #else 295 dev->iobase = pci_mem_to_phys(devbusfn, iobase); 296 #endif 297 dev->priv = (void*) devbusfn; 298 dev->init = dc21x4x_init; 299 dev->halt = dc21x4x_halt; 300 dev->send = dc21x4x_send; 301 dev->recv = dc21x4x_recv; 302 303 /* Ensure we're not sleeping. */ 304 pci_write_config_byte(devbusfn, PCI_CFDA_PSM, WAKEUP); 305 306 udelay(10 * 1000); 307 308 #ifndef CONFIG_TULIP_FIX_DAVICOM 309 read_hw_addr(dev, bis); 310 #endif 311 eth_register(dev); 312 313 card_number++; 314 } 315 316 return card_number; 317 } 318 319 static int dc21x4x_init(struct eth_device* dev, bd_t* bis) 320 { 321 int i; 322 int devbusfn = (int) dev->priv; 323 324 /* Ensure we're not sleeping. */ 325 pci_write_config_byte(devbusfn, PCI_CFDA_PSM, WAKEUP); 326 327 #ifdef CONFIG_TULIP_FIX_DAVICOM 328 RESET_DM9102(dev); 329 #else 330 RESET_DE4X5(dev); 331 #endif 332 333 if ((INL(dev, DE4X5_STS) & (STS_TS | STS_RS)) != 0) { 334 printf("Error: Cannot reset ethernet controller.\n"); 335 return -1; 336 } 337 338 #ifdef CONFIG_TULIP_SELECT_MEDIA 339 dc21x4x_select_media(dev); 340 #else 341 OUTL(dev, OMR_SDP | OMR_PS | OMR_PM, DE4X5_OMR); 342 #endif 343 344 for (i = 0; i < NUM_RX_DESC; i++) { 345 rx_ring[i].status = cpu_to_le32(R_OWN); 346 rx_ring[i].des1 = cpu_to_le32(RX_BUFF_SZ); 347 rx_ring[i].buf = cpu_to_le32(phys_to_bus((u32) NetRxPackets[i])); 348 #ifdef CONFIG_TULIP_FIX_DAVICOM 349 rx_ring[i].next = cpu_to_le32(phys_to_bus((u32) &rx_ring[(i+1) % NUM_RX_DESC])); 350 #else 351 rx_ring[i].next = 0; 352 #endif 353 } 354 355 for (i=0; i < NUM_TX_DESC; i++) { 356 tx_ring[i].status = 0; 357 tx_ring[i].des1 = 0; 358 tx_ring[i].buf = 0; 359 360 #ifdef CONFIG_TULIP_FIX_DAVICOM 361 tx_ring[i].next = cpu_to_le32(phys_to_bus((u32) &tx_ring[(i+1) % NUM_TX_DESC])); 362 #else 363 tx_ring[i].next = 0; 364 #endif 365 } 366 367 rxRingSize = NUM_RX_DESC; 368 txRingSize = NUM_TX_DESC; 369 370 /* Write the end of list marker to the descriptor lists. */ 371 rx_ring[rxRingSize - 1].des1 |= cpu_to_le32(RD_RER); 372 tx_ring[txRingSize - 1].des1 |= cpu_to_le32(TD_TER); 373 374 /* Tell the adapter where the TX/RX rings are located. */ 375 OUTL(dev, phys_to_bus((u32) &rx_ring), DE4X5_RRBA); 376 OUTL(dev, phys_to_bus((u32) &tx_ring), DE4X5_TRBA); 377 378 START_DE4X5(dev); 379 380 tx_new = 0; 381 rx_new = 0; 382 383 send_setup_frame(dev, bis); 384 385 return 0; 386 } 387 388 static int dc21x4x_send(struct eth_device* dev, volatile void *packet, int length) 389 { 390 int status = -1; 391 int i; 392 393 if (length <= 0) { 394 printf("%s: bad packet size: %d\n", dev->name, length); 395 goto Done; 396 } 397 398 for(i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) { 399 if (i >= TOUT_LOOP) { 400 printf("%s: tx error buffer not ready\n", dev->name); 401 goto Done; 402 } 403 } 404 405 tx_ring[tx_new].buf = cpu_to_le32(phys_to_bus((u32) packet)); 406 tx_ring[tx_new].des1 = cpu_to_le32(TD_TER | TD_LS | TD_FS | length); 407 tx_ring[tx_new].status = cpu_to_le32(T_OWN); 408 409 OUTL(dev, POLL_DEMAND, DE4X5_TPD); 410 411 for(i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) { 412 if (i >= TOUT_LOOP) { 413 printf(".%s: tx buffer not ready\n", dev->name); 414 goto Done; 415 } 416 } 417 418 if (le32_to_cpu(tx_ring[tx_new].status) & TD_ES) { 419 #if 0 /* test-only */ 420 printf("TX error status = 0x%08X\n", 421 le32_to_cpu(tx_ring[tx_new].status)); 422 #endif 423 tx_ring[tx_new].status = 0x0; 424 goto Done; 425 } 426 427 status = length; 428 429 Done: 430 tx_new = (tx_new+1) % NUM_TX_DESC; 431 return status; 432 } 433 434 static int dc21x4x_recv(struct eth_device* dev) 435 { 436 s32 status; 437 int length = 0; 438 439 for ( ; ; ) { 440 status = (s32)le32_to_cpu(rx_ring[rx_new].status); 441 442 if (status & R_OWN) { 443 break; 444 } 445 446 if (status & RD_LS) { 447 /* Valid frame status. 448 */ 449 if (status & RD_ES) { 450 451 /* There was an error. 452 */ 453 printf("RX error status = 0x%08X\n", status); 454 } else { 455 /* A valid frame received. 456 */ 457 length = (le32_to_cpu(rx_ring[rx_new].status) >> 16); 458 459 /* Pass the packet up to the protocol 460 * layers. 461 */ 462 NetReceive(NetRxPackets[rx_new], length - 4); 463 } 464 465 /* Change buffer ownership for this frame, back 466 * to the adapter. 467 */ 468 rx_ring[rx_new].status = cpu_to_le32(R_OWN); 469 } 470 471 /* Update entry information. 472 */ 473 rx_new = (rx_new + 1) % rxRingSize; 474 } 475 476 return length; 477 } 478 479 static void dc21x4x_halt(struct eth_device* dev) 480 { 481 int devbusfn = (int) dev->priv; 482 483 STOP_DE4X5(dev); 484 OUTL(dev, 0, DE4X5_SICR); 485 486 pci_write_config_byte(devbusfn, PCI_CFDA_PSM, SLEEP); 487 } 488 489 static void send_setup_frame(struct eth_device* dev, bd_t *bis) 490 { 491 int i; 492 char setup_frame[SETUP_FRAME_LEN]; 493 char *pa = &setup_frame[0]; 494 495 memset(pa, 0xff, SETUP_FRAME_LEN); 496 497 for (i = 0; i < ETH_ALEN; i++) { 498 *(pa + (i & 1)) = dev->enetaddr[i]; 499 if (i & 0x01) { 500 pa += 4; 501 } 502 } 503 504 for(i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) { 505 if (i >= TOUT_LOOP) { 506 printf("%s: tx error buffer not ready\n", dev->name); 507 goto Done; 508 } 509 } 510 511 tx_ring[tx_new].buf = cpu_to_le32(phys_to_bus((u32) &setup_frame[0])); 512 tx_ring[tx_new].des1 = cpu_to_le32(TD_TER | TD_SET| SETUP_FRAME_LEN); 513 tx_ring[tx_new].status = cpu_to_le32(T_OWN); 514 515 OUTL(dev, POLL_DEMAND, DE4X5_TPD); 516 517 for(i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) { 518 if (i >= TOUT_LOOP) { 519 printf("%s: tx buffer not ready\n", dev->name); 520 goto Done; 521 } 522 } 523 524 if (le32_to_cpu(tx_ring[tx_new].status) != 0x7FFFFFFF) { 525 printf("TX error status2 = 0x%08X\n", le32_to_cpu(tx_ring[tx_new].status)); 526 } 527 tx_new = (tx_new+1) % NUM_TX_DESC; 528 529 Done: 530 return; 531 } 532 533 #if defined(UPDATE_SROM) || !defined(CONFIG_TULIP_FIX_DAVICOM) 534 /* SROM Read and write routines. 535 */ 536 static void 537 sendto_srom(struct eth_device* dev, u_int command, u_long addr) 538 { 539 OUTL(dev, command, addr); 540 udelay(1); 541 } 542 543 static int 544 getfrom_srom(struct eth_device* dev, u_long addr) 545 { 546 s32 tmp; 547 548 tmp = INL(dev, addr); 549 udelay(1); 550 551 return tmp; 552 } 553 554 /* Note: this routine returns extra data bits for size detection. */ 555 static int do_read_eeprom(struct eth_device *dev, u_long ioaddr, int location, int addr_len) 556 { 557 int i; 558 unsigned retval = 0; 559 int read_cmd = location | (SROM_READ_CMD << addr_len); 560 561 sendto_srom(dev, SROM_RD | SROM_SR, ioaddr); 562 sendto_srom(dev, SROM_RD | SROM_SR | DT_CS, ioaddr); 563 564 #ifdef DEBUG_SROM 565 printf(" EEPROM read at %d ", location); 566 #endif 567 568 /* Shift the read command bits out. */ 569 for (i = 4 + addr_len; i >= 0; i--) { 570 short dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0; 571 sendto_srom(dev, SROM_RD | SROM_SR | DT_CS | dataval, ioaddr); 572 udelay(10); 573 sendto_srom(dev, SROM_RD | SROM_SR | DT_CS | dataval | DT_CLK, ioaddr); 574 udelay(10); 575 #ifdef DEBUG_SROM2 576 printf("%X", getfrom_srom(dev, ioaddr) & 15); 577 #endif 578 retval = (retval << 1) | ((getfrom_srom(dev, ioaddr) & EE_DATA_READ) ? 1 : 0); 579 } 580 581 sendto_srom(dev, SROM_RD | SROM_SR | DT_CS, ioaddr); 582 583 #ifdef DEBUG_SROM2 584 printf(" :%X:", getfrom_srom(dev, ioaddr) & 15); 585 #endif 586 587 for (i = 16; i > 0; i--) { 588 sendto_srom(dev, SROM_RD | SROM_SR | DT_CS | DT_CLK, ioaddr); 589 udelay(10); 590 #ifdef DEBUG_SROM2 591 printf("%X", getfrom_srom(dev, ioaddr) & 15); 592 #endif 593 retval = (retval << 1) | ((getfrom_srom(dev, ioaddr) & EE_DATA_READ) ? 1 : 0); 594 sendto_srom(dev, SROM_RD | SROM_SR | DT_CS, ioaddr); 595 udelay(10); 596 } 597 598 /* Terminate the EEPROM access. */ 599 sendto_srom(dev, SROM_RD | SROM_SR, ioaddr); 600 601 #ifdef DEBUG_SROM2 602 printf(" EEPROM value at %d is %5.5x.\n", location, retval); 603 #endif 604 605 return retval; 606 } 607 #endif /* UPDATE_SROM || !CONFIG_TULIP_FIX_DAVICOM */ 608 609 /* This executes a generic EEPROM command, typically a write or write 610 * enable. It returns the data output from the EEPROM, and thus may 611 * also be used for reads. 612 */ 613 #if defined(UPDATE_SROM) || !defined(CONFIG_TULIP_FIX_DAVICOM) 614 static int do_eeprom_cmd(struct eth_device *dev, u_long ioaddr, int cmd, int cmd_len) 615 { 616 unsigned retval = 0; 617 618 #ifdef DEBUG_SROM 619 printf(" EEPROM op 0x%x: ", cmd); 620 #endif 621 622 sendto_srom(dev,SROM_RD | SROM_SR | DT_CS | DT_CLK, ioaddr); 623 624 /* Shift the command bits out. */ 625 do { 626 short dataval = (cmd & (1 << cmd_len)) ? EE_WRITE_1 : EE_WRITE_0; 627 sendto_srom(dev,dataval, ioaddr); 628 udelay(10); 629 630 #ifdef DEBUG_SROM2 631 printf("%X", getfrom_srom(dev,ioaddr) & 15); 632 #endif 633 634 sendto_srom(dev,dataval | DT_CLK, ioaddr); 635 udelay(10); 636 retval = (retval << 1) | ((getfrom_srom(dev,ioaddr) & EE_DATA_READ) ? 1 : 0); 637 } while (--cmd_len >= 0); 638 sendto_srom(dev,SROM_RD | SROM_SR | DT_CS, ioaddr); 639 640 /* Terminate the EEPROM access. */ 641 sendto_srom(dev,SROM_RD | SROM_SR, ioaddr); 642 643 #ifdef DEBUG_SROM 644 printf(" EEPROM result is 0x%5.5x.\n", retval); 645 #endif 646 647 return retval; 648 } 649 #endif /* UPDATE_SROM || !CONFIG_TULIP_FIX_DAVICOM */ 650 651 #ifndef CONFIG_TULIP_FIX_DAVICOM 652 static int read_srom(struct eth_device *dev, u_long ioaddr, int index) 653 { 654 int ee_addr_size = do_read_eeprom(dev, ioaddr, 0xff, 8) & 0x40000 ? 8 : 6; 655 656 return do_eeprom_cmd(dev, ioaddr, 657 (((SROM_READ_CMD << ee_addr_size) | index) << 16) 658 | 0xffff, 3 + ee_addr_size + 16); 659 } 660 #endif /* CONFIG_TULIP_FIX_DAVICOM */ 661 662 #ifdef UPDATE_SROM 663 static int write_srom(struct eth_device *dev, u_long ioaddr, int index, int new_value) 664 { 665 int ee_addr_size = do_read_eeprom(dev, ioaddr, 0xff, 8) & 0x40000 ? 8 : 6; 666 int i; 667 unsigned short newval; 668 669 udelay(10*1000); /* test-only */ 670 671 #ifdef DEBUG_SROM 672 printf("ee_addr_size=%d.\n", ee_addr_size); 673 printf("Writing new entry 0x%4.4x to offset %d.\n", new_value, index); 674 #endif 675 676 /* Enable programming modes. */ 677 do_eeprom_cmd(dev, ioaddr, (0x4f << (ee_addr_size-4)), 3+ee_addr_size); 678 679 /* Do the actual write. */ 680 do_eeprom_cmd(dev, ioaddr, 681 (((SROM_WRITE_CMD<<ee_addr_size)|index) << 16) | new_value, 682 3 + ee_addr_size + 16); 683 684 /* Poll for write finished. */ 685 sendto_srom(dev, SROM_RD | SROM_SR | DT_CS, ioaddr); 686 for (i = 0; i < 10000; i++) /* Typical 2000 ticks */ 687 if (getfrom_srom(dev, ioaddr) & EE_DATA_READ) 688 break; 689 690 #ifdef DEBUG_SROM 691 printf(" Write finished after %d ticks.\n", i); 692 #endif 693 694 /* Disable programming. */ 695 do_eeprom_cmd(dev, ioaddr, (0x40 << (ee_addr_size-4)), 3 + ee_addr_size); 696 697 /* And read the result. */ 698 newval = do_eeprom_cmd(dev, ioaddr, 699 (((SROM_READ_CMD<<ee_addr_size)|index) << 16) 700 | 0xffff, 3 + ee_addr_size + 16); 701 #ifdef DEBUG_SROM 702 printf(" New value at offset %d is %4.4x.\n", index, newval); 703 #endif 704 return 1; 705 } 706 #endif 707 708 #ifndef CONFIG_TULIP_FIX_DAVICOM 709 static void read_hw_addr(struct eth_device *dev, bd_t *bis) 710 { 711 u_short tmp, *p = (u_short *)(&dev->enetaddr[0]); 712 int i, j = 0; 713 714 for (i = 0; i < (ETH_ALEN >> 1); i++) { 715 tmp = read_srom(dev, DE4X5_APROM, ((SROM_HWADD >> 1) + i)); 716 *p = le16_to_cpu(tmp); 717 j += *p++; 718 } 719 720 if ((j == 0) || (j == 0x2fffd)) { 721 memset (dev->enetaddr, 0, ETH_ALEN); 722 debug ("Warning: can't read HW address from SROM.\n"); 723 goto Done; 724 } 725 726 return; 727 728 Done: 729 #ifdef UPDATE_SROM 730 update_srom(dev, bis); 731 #endif 732 return; 733 } 734 #endif /* CONFIG_TULIP_FIX_DAVICOM */ 735 736 #ifdef UPDATE_SROM 737 static void update_srom(struct eth_device *dev, bd_t *bis) 738 { 739 int i; 740 static unsigned short eeprom[0x40] = { 741 0x140b, 0x6610, 0x0000, 0x0000, /* 00 */ 742 0x0000, 0x0000, 0x0000, 0x0000, /* 04 */ 743 0x00a3, 0x0103, 0x0000, 0x0000, /* 08 */ 744 0x0000, 0x1f00, 0x0000, 0x0000, /* 0c */ 745 0x0108, 0x038d, 0x0000, 0x0000, /* 10 */ 746 0xe078, 0x0001, 0x0040, 0x0018, /* 14 */ 747 0x0000, 0x0000, 0x0000, 0x0000, /* 18 */ 748 0x0000, 0x0000, 0x0000, 0x0000, /* 1c */ 749 0x0000, 0x0000, 0x0000, 0x0000, /* 20 */ 750 0x0000, 0x0000, 0x0000, 0x0000, /* 24 */ 751 0x0000, 0x0000, 0x0000, 0x0000, /* 28 */ 752 0x0000, 0x0000, 0x0000, 0x0000, /* 2c */ 753 0x0000, 0x0000, 0x0000, 0x0000, /* 30 */ 754 0x0000, 0x0000, 0x0000, 0x0000, /* 34 */ 755 0x0000, 0x0000, 0x0000, 0x0000, /* 38 */ 756 0x0000, 0x0000, 0x0000, 0x4e07, /* 3c */ 757 }; 758 759 /* Ethernet Addr... */ 760 eeprom[0x0a] = ((bis->bi_enetaddr[1] & 0xff) << 8) | (bis->bi_enetaddr[0] & 0xff); 761 eeprom[0x0b] = ((bis->bi_enetaddr[3] & 0xff) << 8) | (bis->bi_enetaddr[2] & 0xff); 762 eeprom[0x0c] = ((bis->bi_enetaddr[5] & 0xff) << 8) | (bis->bi_enetaddr[4] & 0xff); 763 764 for (i=0; i<0x40; i++) { 765 write_srom(dev, DE4X5_APROM, i, eeprom[i]); 766 } 767 } 768 #endif /* UPDATE_SROM */ 769 770 #endif 771