1 /* 2 * See file CREDITS for list of people who contributed to this 3 * project. 4 * 5 * This program is free software; you can redistribute it and/or 6 * modify it under the terms of the GNU General Public License as 7 * published by the Free Software Foundation; either version 2 of 8 * the License, or (at your option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, write to the Free Software 17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 18 * MA 02111-1307 USA 19 */ 20 21 #include <common.h> 22 #include <malloc.h> 23 #include <net.h> 24 #include <netdev.h> 25 #include <pci.h> 26 27 #undef DEBUG_SROM 28 #undef DEBUG_SROM2 29 30 #undef UPDATE_SROM 31 32 /* PCI Registers. 33 */ 34 #define PCI_CFDA_PSM 0x43 35 36 #define CFRV_RN 0x000000f0 /* Revision Number */ 37 38 #define WAKEUP 0x00 /* Power Saving Wakeup */ 39 #define SLEEP 0x80 /* Power Saving Sleep Mode */ 40 41 #define DC2114x_BRK 0x0020 /* CFRV break between DC21142 & DC21143 */ 42 43 /* Ethernet chip registers. 44 */ 45 #define DE4X5_BMR 0x000 /* Bus Mode Register */ 46 #define DE4X5_TPD 0x008 /* Transmit Poll Demand Reg */ 47 #define DE4X5_RRBA 0x018 /* RX Ring Base Address Reg */ 48 #define DE4X5_TRBA 0x020 /* TX Ring Base Address Reg */ 49 #define DE4X5_STS 0x028 /* Status Register */ 50 #define DE4X5_OMR 0x030 /* Operation Mode Register */ 51 #define DE4X5_SICR 0x068 /* SIA Connectivity Register */ 52 #define DE4X5_APROM 0x048 /* Ethernet Address PROM */ 53 54 /* Register bits. 55 */ 56 #define BMR_SWR 0x00000001 /* Software Reset */ 57 #define STS_TS 0x00700000 /* Transmit Process State */ 58 #define STS_RS 0x000e0000 /* Receive Process State */ 59 #define OMR_ST 0x00002000 /* Start/Stop Transmission Command */ 60 #define OMR_SR 0x00000002 /* Start/Stop Receive */ 61 #define OMR_PS 0x00040000 /* Port Select */ 62 #define OMR_SDP 0x02000000 /* SD Polarity - MUST BE ASSERTED */ 63 #define OMR_PM 0x00000080 /* Pass All Multicast */ 64 65 /* Descriptor bits. 66 */ 67 #define R_OWN 0x80000000 /* Own Bit */ 68 #define RD_RER 0x02000000 /* Receive End Of Ring */ 69 #define RD_LS 0x00000100 /* Last Descriptor */ 70 #define RD_ES 0x00008000 /* Error Summary */ 71 #define TD_TER 0x02000000 /* Transmit End Of Ring */ 72 #define T_OWN 0x80000000 /* Own Bit */ 73 #define TD_LS 0x40000000 /* Last Segment */ 74 #define TD_FS 0x20000000 /* First Segment */ 75 #define TD_ES 0x00008000 /* Error Summary */ 76 #define TD_SET 0x08000000 /* Setup Packet */ 77 78 /* The EEPROM commands include the alway-set leading bit. */ 79 #define SROM_WRITE_CMD 5 80 #define SROM_READ_CMD 6 81 #define SROM_ERASE_CMD 7 82 83 #define SROM_HWADD 0x0014 /* Hardware Address offset in SROM */ 84 #define SROM_RD 0x00004000 /* Read from Boot ROM */ 85 #define EE_DATA_WRITE 0x04 /* EEPROM chip data in. */ 86 #define EE_WRITE_0 0x4801 87 #define EE_WRITE_1 0x4805 88 #define EE_DATA_READ 0x08 /* EEPROM chip data out. */ 89 #define SROM_SR 0x00000800 /* Select Serial ROM when set */ 90 91 #define DT_IN 0x00000004 /* Serial Data In */ 92 #define DT_CLK 0x00000002 /* Serial ROM Clock */ 93 #define DT_CS 0x00000001 /* Serial ROM Chip Select */ 94 95 #define POLL_DEMAND 1 96 97 #ifdef CONFIG_TULIP_FIX_DAVICOM 98 #define RESET_DM9102(dev) {\ 99 unsigned long i;\ 100 i=INL(dev, 0x0);\ 101 udelay(1000);\ 102 OUTL(dev, i | BMR_SWR, DE4X5_BMR);\ 103 udelay(1000);\ 104 } 105 #else 106 #define RESET_DE4X5(dev) {\ 107 int i;\ 108 i=INL(dev, DE4X5_BMR);\ 109 udelay(1000);\ 110 OUTL(dev, i | BMR_SWR, DE4X5_BMR);\ 111 udelay(1000);\ 112 OUTL(dev, i, DE4X5_BMR);\ 113 udelay(1000);\ 114 for (i=0;i<5;i++) {INL(dev, DE4X5_BMR); udelay(10000);}\ 115 udelay(1000);\ 116 } 117 #endif 118 119 #define START_DE4X5(dev) {\ 120 s32 omr; \ 121 omr = INL(dev, DE4X5_OMR);\ 122 omr |= OMR_ST | OMR_SR;\ 123 OUTL(dev, omr, DE4X5_OMR); /* Enable the TX and/or RX */\ 124 } 125 126 #define STOP_DE4X5(dev) {\ 127 s32 omr; \ 128 omr = INL(dev, DE4X5_OMR);\ 129 omr &= ~(OMR_ST|OMR_SR);\ 130 OUTL(dev, omr, DE4X5_OMR); /* Disable the TX and/or RX */ \ 131 } 132 133 #define NUM_RX_DESC PKTBUFSRX 134 #ifndef CONFIG_TULIP_FIX_DAVICOM 135 #define NUM_TX_DESC 1 /* Number of TX descriptors */ 136 #else 137 #define NUM_TX_DESC 4 138 #endif 139 #define RX_BUFF_SZ PKTSIZE_ALIGN 140 141 #define TOUT_LOOP 1000000 142 143 #define SETUP_FRAME_LEN 192 144 #define ETH_ALEN 6 145 146 struct de4x5_desc { 147 volatile s32 status; 148 u32 des1; 149 u32 buf; 150 u32 next; 151 }; 152 153 static struct de4x5_desc rx_ring[NUM_RX_DESC] __attribute__ ((aligned(32))); /* RX descriptor ring */ 154 static struct de4x5_desc tx_ring[NUM_TX_DESC] __attribute__ ((aligned(32))); /* TX descriptor ring */ 155 static int rx_new; /* RX descriptor ring pointer */ 156 static int tx_new; /* TX descriptor ring pointer */ 157 158 static char rxRingSize; 159 static char txRingSize; 160 161 #if defined(UPDATE_SROM) || !defined(CONFIG_TULIP_FIX_DAVICOM) 162 static void sendto_srom(struct eth_device* dev, u_int command, u_long addr); 163 static int getfrom_srom(struct eth_device* dev, u_long addr); 164 static int do_eeprom_cmd(struct eth_device *dev, u_long ioaddr,int cmd,int cmd_len); 165 static int do_read_eeprom(struct eth_device *dev,u_long ioaddr,int location,int addr_len); 166 #endif /* UPDATE_SROM || !CONFIG_TULIP_FIX_DAVICOM */ 167 #ifdef UPDATE_SROM 168 static int write_srom(struct eth_device *dev, u_long ioaddr, int index, int new_value); 169 static void update_srom(struct eth_device *dev, bd_t *bis); 170 #endif 171 #ifndef CONFIG_TULIP_FIX_DAVICOM 172 static int read_srom(struct eth_device *dev, u_long ioaddr, int index); 173 static void read_hw_addr(struct eth_device* dev, bd_t * bis); 174 #endif /* CONFIG_TULIP_FIX_DAVICOM */ 175 static void send_setup_frame(struct eth_device* dev, bd_t * bis); 176 177 static int dc21x4x_init(struct eth_device* dev, bd_t* bis); 178 static int dc21x4x_send(struct eth_device* dev, volatile void *packet, int length); 179 static int dc21x4x_recv(struct eth_device* dev); 180 static void dc21x4x_halt(struct eth_device* dev); 181 #ifdef CONFIG_TULIP_SELECT_MEDIA 182 extern void dc21x4x_select_media(struct eth_device* dev); 183 #endif 184 185 #if defined(CONFIG_E500) 186 #define phys_to_bus(a) (a) 187 #else 188 #define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)dev->priv, a) 189 #endif 190 191 static int INL(struct eth_device* dev, u_long addr) 192 { 193 return le32_to_cpu(*(volatile u_long *)(addr + dev->iobase)); 194 } 195 196 static void OUTL(struct eth_device* dev, int command, u_long addr) 197 { 198 *(volatile u_long *)(addr + dev->iobase) = cpu_to_le32(command); 199 } 200 201 static struct pci_device_id supported[] = { 202 { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TULIP_FAST }, 203 { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21142 }, 204 #ifdef CONFIG_TULIP_FIX_DAVICOM 205 { PCI_VENDOR_ID_DAVICOM, PCI_DEVICE_ID_DAVICOM_DM9102A }, 206 #endif 207 { } 208 }; 209 210 int dc21x4x_initialize(bd_t *bis) 211 { 212 int idx=0; 213 int card_number = 0; 214 unsigned int cfrv; 215 unsigned char timer; 216 pci_dev_t devbusfn; 217 unsigned int iobase; 218 unsigned short status; 219 struct eth_device* dev; 220 221 while(1) { 222 devbusfn = pci_find_devices(supported, idx++); 223 if (devbusfn == -1) { 224 break; 225 } 226 227 /* Get the chip configuration revision register. */ 228 pci_read_config_dword(devbusfn, PCI_REVISION_ID, &cfrv); 229 230 #ifndef CONFIG_TULIP_FIX_DAVICOM 231 if ((cfrv & CFRV_RN) < DC2114x_BRK ) { 232 printf("Error: The chip is not DC21143.\n"); 233 continue; 234 } 235 #endif 236 237 pci_read_config_word(devbusfn, PCI_COMMAND, &status); 238 status |= 239 #ifdef CONFIG_TULIP_USE_IO 240 PCI_COMMAND_IO | 241 #else 242 PCI_COMMAND_MEMORY | 243 #endif 244 PCI_COMMAND_MASTER; 245 pci_write_config_word(devbusfn, PCI_COMMAND, status); 246 247 pci_read_config_word(devbusfn, PCI_COMMAND, &status); 248 if (!(status & PCI_COMMAND_IO)) { 249 printf("Error: Can not enable I/O access.\n"); 250 continue; 251 } 252 253 if (!(status & PCI_COMMAND_IO)) { 254 printf("Error: Can not enable I/O access.\n"); 255 continue; 256 } 257 258 if (!(status & PCI_COMMAND_MASTER)) { 259 printf("Error: Can not enable Bus Mastering.\n"); 260 continue; 261 } 262 263 /* Check the latency timer for values >= 0x60. */ 264 pci_read_config_byte(devbusfn, PCI_LATENCY_TIMER, &timer); 265 266 if (timer < 0x60) { 267 pci_write_config_byte(devbusfn, PCI_LATENCY_TIMER, 0x60); 268 } 269 270 #ifdef CONFIG_TULIP_USE_IO 271 /* read BAR for memory space access */ 272 pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, &iobase); 273 iobase &= PCI_BASE_ADDRESS_IO_MASK; 274 #else 275 /* read BAR for memory space access */ 276 pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_1, &iobase); 277 iobase &= PCI_BASE_ADDRESS_MEM_MASK; 278 #endif 279 debug ("dc21x4x: DEC 21142 PCI Device @0x%x\n", iobase); 280 281 dev = (struct eth_device*) malloc(sizeof *dev); 282 283 if (!dev) { 284 printf("Can not allocalte memory of dc21x4x\n"); 285 break; 286 } 287 memset(dev, 0, sizeof(*dev)); 288 289 #ifdef CONFIG_TULIP_FIX_DAVICOM 290 sprintf(dev->name, "Davicom#%d", card_number); 291 #else 292 sprintf(dev->name, "dc21x4x#%d", card_number); 293 #endif 294 295 #ifdef CONFIG_TULIP_USE_IO 296 dev->iobase = pci_io_to_phys(devbusfn, iobase); 297 #else 298 dev->iobase = pci_mem_to_phys(devbusfn, iobase); 299 #endif 300 dev->priv = (void*) devbusfn; 301 dev->init = dc21x4x_init; 302 dev->halt = dc21x4x_halt; 303 dev->send = dc21x4x_send; 304 dev->recv = dc21x4x_recv; 305 306 /* Ensure we're not sleeping. */ 307 pci_write_config_byte(devbusfn, PCI_CFDA_PSM, WAKEUP); 308 309 udelay(10 * 1000); 310 311 #ifndef CONFIG_TULIP_FIX_DAVICOM 312 read_hw_addr(dev, bis); 313 #endif 314 eth_register(dev); 315 316 card_number++; 317 } 318 319 return card_number; 320 } 321 322 static int dc21x4x_init(struct eth_device* dev, bd_t* bis) 323 { 324 int i; 325 int devbusfn = (int) dev->priv; 326 327 /* Ensure we're not sleeping. */ 328 pci_write_config_byte(devbusfn, PCI_CFDA_PSM, WAKEUP); 329 330 #ifdef CONFIG_TULIP_FIX_DAVICOM 331 RESET_DM9102(dev); 332 #else 333 RESET_DE4X5(dev); 334 #endif 335 336 if ((INL(dev, DE4X5_STS) & (STS_TS | STS_RS)) != 0) { 337 printf("Error: Cannot reset ethernet controller.\n"); 338 return -1; 339 } 340 341 #ifdef CONFIG_TULIP_SELECT_MEDIA 342 dc21x4x_select_media(dev); 343 #else 344 OUTL(dev, OMR_SDP | OMR_PS | OMR_PM, DE4X5_OMR); 345 #endif 346 347 for (i = 0; i < NUM_RX_DESC; i++) { 348 rx_ring[i].status = cpu_to_le32(R_OWN); 349 rx_ring[i].des1 = cpu_to_le32(RX_BUFF_SZ); 350 rx_ring[i].buf = cpu_to_le32(phys_to_bus((u32) NetRxPackets[i])); 351 #ifdef CONFIG_TULIP_FIX_DAVICOM 352 rx_ring[i].next = cpu_to_le32(phys_to_bus((u32) &rx_ring[(i+1) % NUM_RX_DESC])); 353 #else 354 rx_ring[i].next = 0; 355 #endif 356 } 357 358 for (i=0; i < NUM_TX_DESC; i++) { 359 tx_ring[i].status = 0; 360 tx_ring[i].des1 = 0; 361 tx_ring[i].buf = 0; 362 363 #ifdef CONFIG_TULIP_FIX_DAVICOM 364 tx_ring[i].next = cpu_to_le32(phys_to_bus((u32) &tx_ring[(i+1) % NUM_TX_DESC])); 365 #else 366 tx_ring[i].next = 0; 367 #endif 368 } 369 370 rxRingSize = NUM_RX_DESC; 371 txRingSize = NUM_TX_DESC; 372 373 /* Write the end of list marker to the descriptor lists. */ 374 rx_ring[rxRingSize - 1].des1 |= cpu_to_le32(RD_RER); 375 tx_ring[txRingSize - 1].des1 |= cpu_to_le32(TD_TER); 376 377 /* Tell the adapter where the TX/RX rings are located. */ 378 OUTL(dev, phys_to_bus((u32) &rx_ring), DE4X5_RRBA); 379 OUTL(dev, phys_to_bus((u32) &tx_ring), DE4X5_TRBA); 380 381 START_DE4X5(dev); 382 383 tx_new = 0; 384 rx_new = 0; 385 386 send_setup_frame(dev, bis); 387 388 return 0; 389 } 390 391 static int dc21x4x_send(struct eth_device* dev, volatile void *packet, int length) 392 { 393 int status = -1; 394 int i; 395 396 if (length <= 0) { 397 printf("%s: bad packet size: %d\n", dev->name, length); 398 goto Done; 399 } 400 401 for(i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) { 402 if (i >= TOUT_LOOP) { 403 printf("%s: tx error buffer not ready\n", dev->name); 404 goto Done; 405 } 406 } 407 408 tx_ring[tx_new].buf = cpu_to_le32(phys_to_bus((u32) packet)); 409 tx_ring[tx_new].des1 = cpu_to_le32(TD_TER | TD_LS | TD_FS | length); 410 tx_ring[tx_new].status = cpu_to_le32(T_OWN); 411 412 OUTL(dev, POLL_DEMAND, DE4X5_TPD); 413 414 for(i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) { 415 if (i >= TOUT_LOOP) { 416 printf(".%s: tx buffer not ready\n", dev->name); 417 goto Done; 418 } 419 } 420 421 if (le32_to_cpu(tx_ring[tx_new].status) & TD_ES) { 422 #if 0 /* test-only */ 423 printf("TX error status = 0x%08X\n", 424 le32_to_cpu(tx_ring[tx_new].status)); 425 #endif 426 tx_ring[tx_new].status = 0x0; 427 goto Done; 428 } 429 430 status = length; 431 432 Done: 433 tx_new = (tx_new+1) % NUM_TX_DESC; 434 return status; 435 } 436 437 static int dc21x4x_recv(struct eth_device* dev) 438 { 439 s32 status; 440 int length = 0; 441 442 for ( ; ; ) { 443 status = (s32)le32_to_cpu(rx_ring[rx_new].status); 444 445 if (status & R_OWN) { 446 break; 447 } 448 449 if (status & RD_LS) { 450 /* Valid frame status. 451 */ 452 if (status & RD_ES) { 453 454 /* There was an error. 455 */ 456 printf("RX error status = 0x%08X\n", status); 457 } else { 458 /* A valid frame received. 459 */ 460 length = (le32_to_cpu(rx_ring[rx_new].status) >> 16); 461 462 /* Pass the packet up to the protocol 463 * layers. 464 */ 465 NetReceive(NetRxPackets[rx_new], length - 4); 466 } 467 468 /* Change buffer ownership for this frame, back 469 * to the adapter. 470 */ 471 rx_ring[rx_new].status = cpu_to_le32(R_OWN); 472 } 473 474 /* Update entry information. 475 */ 476 rx_new = (rx_new + 1) % rxRingSize; 477 } 478 479 return length; 480 } 481 482 static void dc21x4x_halt(struct eth_device* dev) 483 { 484 int devbusfn = (int) dev->priv; 485 486 STOP_DE4X5(dev); 487 OUTL(dev, 0, DE4X5_SICR); 488 489 pci_write_config_byte(devbusfn, PCI_CFDA_PSM, SLEEP); 490 } 491 492 static void send_setup_frame(struct eth_device* dev, bd_t *bis) 493 { 494 int i; 495 char setup_frame[SETUP_FRAME_LEN]; 496 char *pa = &setup_frame[0]; 497 498 memset(pa, 0xff, SETUP_FRAME_LEN); 499 500 for (i = 0; i < ETH_ALEN; i++) { 501 *(pa + (i & 1)) = dev->enetaddr[i]; 502 if (i & 0x01) { 503 pa += 4; 504 } 505 } 506 507 for(i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) { 508 if (i >= TOUT_LOOP) { 509 printf("%s: tx error buffer not ready\n", dev->name); 510 goto Done; 511 } 512 } 513 514 tx_ring[tx_new].buf = cpu_to_le32(phys_to_bus((u32) &setup_frame[0])); 515 tx_ring[tx_new].des1 = cpu_to_le32(TD_TER | TD_SET| SETUP_FRAME_LEN); 516 tx_ring[tx_new].status = cpu_to_le32(T_OWN); 517 518 OUTL(dev, POLL_DEMAND, DE4X5_TPD); 519 520 for(i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) { 521 if (i >= TOUT_LOOP) { 522 printf("%s: tx buffer not ready\n", dev->name); 523 goto Done; 524 } 525 } 526 527 if (le32_to_cpu(tx_ring[tx_new].status) != 0x7FFFFFFF) { 528 printf("TX error status2 = 0x%08X\n", le32_to_cpu(tx_ring[tx_new].status)); 529 } 530 tx_new = (tx_new+1) % NUM_TX_DESC; 531 532 Done: 533 return; 534 } 535 536 #if defined(UPDATE_SROM) || !defined(CONFIG_TULIP_FIX_DAVICOM) 537 /* SROM Read and write routines. 538 */ 539 static void 540 sendto_srom(struct eth_device* dev, u_int command, u_long addr) 541 { 542 OUTL(dev, command, addr); 543 udelay(1); 544 } 545 546 static int 547 getfrom_srom(struct eth_device* dev, u_long addr) 548 { 549 s32 tmp; 550 551 tmp = INL(dev, addr); 552 udelay(1); 553 554 return tmp; 555 } 556 557 /* Note: this routine returns extra data bits for size detection. */ 558 static int do_read_eeprom(struct eth_device *dev, u_long ioaddr, int location, int addr_len) 559 { 560 int i; 561 unsigned retval = 0; 562 int read_cmd = location | (SROM_READ_CMD << addr_len); 563 564 sendto_srom(dev, SROM_RD | SROM_SR, ioaddr); 565 sendto_srom(dev, SROM_RD | SROM_SR | DT_CS, ioaddr); 566 567 #ifdef DEBUG_SROM 568 printf(" EEPROM read at %d ", location); 569 #endif 570 571 /* Shift the read command bits out. */ 572 for (i = 4 + addr_len; i >= 0; i--) { 573 short dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0; 574 sendto_srom(dev, SROM_RD | SROM_SR | DT_CS | dataval, ioaddr); 575 udelay(10); 576 sendto_srom(dev, SROM_RD | SROM_SR | DT_CS | dataval | DT_CLK, ioaddr); 577 udelay(10); 578 #ifdef DEBUG_SROM2 579 printf("%X", getfrom_srom(dev, ioaddr) & 15); 580 #endif 581 retval = (retval << 1) | ((getfrom_srom(dev, ioaddr) & EE_DATA_READ) ? 1 : 0); 582 } 583 584 sendto_srom(dev, SROM_RD | SROM_SR | DT_CS, ioaddr); 585 586 #ifdef DEBUG_SROM2 587 printf(" :%X:", getfrom_srom(dev, ioaddr) & 15); 588 #endif 589 590 for (i = 16; i > 0; i--) { 591 sendto_srom(dev, SROM_RD | SROM_SR | DT_CS | DT_CLK, ioaddr); 592 udelay(10); 593 #ifdef DEBUG_SROM2 594 printf("%X", getfrom_srom(dev, ioaddr) & 15); 595 #endif 596 retval = (retval << 1) | ((getfrom_srom(dev, ioaddr) & EE_DATA_READ) ? 1 : 0); 597 sendto_srom(dev, SROM_RD | SROM_SR | DT_CS, ioaddr); 598 udelay(10); 599 } 600 601 /* Terminate the EEPROM access. */ 602 sendto_srom(dev, SROM_RD | SROM_SR, ioaddr); 603 604 #ifdef DEBUG_SROM2 605 printf(" EEPROM value at %d is %5.5x.\n", location, retval); 606 #endif 607 608 return retval; 609 } 610 #endif /* UPDATE_SROM || !CONFIG_TULIP_FIX_DAVICOM */ 611 612 /* This executes a generic EEPROM command, typically a write or write 613 * enable. It returns the data output from the EEPROM, and thus may 614 * also be used for reads. 615 */ 616 #if defined(UPDATE_SROM) || !defined(CONFIG_TULIP_FIX_DAVICOM) 617 static int do_eeprom_cmd(struct eth_device *dev, u_long ioaddr, int cmd, int cmd_len) 618 { 619 unsigned retval = 0; 620 621 #ifdef DEBUG_SROM 622 printf(" EEPROM op 0x%x: ", cmd); 623 #endif 624 625 sendto_srom(dev,SROM_RD | SROM_SR | DT_CS | DT_CLK, ioaddr); 626 627 /* Shift the command bits out. */ 628 do { 629 short dataval = (cmd & (1 << cmd_len)) ? EE_WRITE_1 : EE_WRITE_0; 630 sendto_srom(dev,dataval, ioaddr); 631 udelay(10); 632 633 #ifdef DEBUG_SROM2 634 printf("%X", getfrom_srom(dev,ioaddr) & 15); 635 #endif 636 637 sendto_srom(dev,dataval | DT_CLK, ioaddr); 638 udelay(10); 639 retval = (retval << 1) | ((getfrom_srom(dev,ioaddr) & EE_DATA_READ) ? 1 : 0); 640 } while (--cmd_len >= 0); 641 sendto_srom(dev,SROM_RD | SROM_SR | DT_CS, ioaddr); 642 643 /* Terminate the EEPROM access. */ 644 sendto_srom(dev,SROM_RD | SROM_SR, ioaddr); 645 646 #ifdef DEBUG_SROM 647 printf(" EEPROM result is 0x%5.5x.\n", retval); 648 #endif 649 650 return retval; 651 } 652 #endif /* UPDATE_SROM || !CONFIG_TULIP_FIX_DAVICOM */ 653 654 #ifndef CONFIG_TULIP_FIX_DAVICOM 655 static int read_srom(struct eth_device *dev, u_long ioaddr, int index) 656 { 657 int ee_addr_size = do_read_eeprom(dev, ioaddr, 0xff, 8) & 0x40000 ? 8 : 6; 658 659 return do_eeprom_cmd(dev, ioaddr, 660 (((SROM_READ_CMD << ee_addr_size) | index) << 16) 661 | 0xffff, 3 + ee_addr_size + 16); 662 } 663 #endif /* CONFIG_TULIP_FIX_DAVICOM */ 664 665 #ifdef UPDATE_SROM 666 static int write_srom(struct eth_device *dev, u_long ioaddr, int index, int new_value) 667 { 668 int ee_addr_size = do_read_eeprom(dev, ioaddr, 0xff, 8) & 0x40000 ? 8 : 6; 669 int i; 670 unsigned short newval; 671 672 udelay(10*1000); /* test-only */ 673 674 #ifdef DEBUG_SROM 675 printf("ee_addr_size=%d.\n", ee_addr_size); 676 printf("Writing new entry 0x%4.4x to offset %d.\n", new_value, index); 677 #endif 678 679 /* Enable programming modes. */ 680 do_eeprom_cmd(dev, ioaddr, (0x4f << (ee_addr_size-4)), 3+ee_addr_size); 681 682 /* Do the actual write. */ 683 do_eeprom_cmd(dev, ioaddr, 684 (((SROM_WRITE_CMD<<ee_addr_size)|index) << 16) | new_value, 685 3 + ee_addr_size + 16); 686 687 /* Poll for write finished. */ 688 sendto_srom(dev, SROM_RD | SROM_SR | DT_CS, ioaddr); 689 for (i = 0; i < 10000; i++) /* Typical 2000 ticks */ 690 if (getfrom_srom(dev, ioaddr) & EE_DATA_READ) 691 break; 692 693 #ifdef DEBUG_SROM 694 printf(" Write finished after %d ticks.\n", i); 695 #endif 696 697 /* Disable programming. */ 698 do_eeprom_cmd(dev, ioaddr, (0x40 << (ee_addr_size-4)), 3 + ee_addr_size); 699 700 /* And read the result. */ 701 newval = do_eeprom_cmd(dev, ioaddr, 702 (((SROM_READ_CMD<<ee_addr_size)|index) << 16) 703 | 0xffff, 3 + ee_addr_size + 16); 704 #ifdef DEBUG_SROM 705 printf(" New value at offset %d is %4.4x.\n", index, newval); 706 #endif 707 return 1; 708 } 709 #endif 710 711 #ifndef CONFIG_TULIP_FIX_DAVICOM 712 static void read_hw_addr(struct eth_device *dev, bd_t *bis) 713 { 714 u_short tmp, *p = (u_short *)(&dev->enetaddr[0]); 715 int i, j = 0; 716 717 for (i = 0; i < (ETH_ALEN >> 1); i++) { 718 tmp = read_srom(dev, DE4X5_APROM, ((SROM_HWADD >> 1) + i)); 719 *p = le16_to_cpu(tmp); 720 j += *p++; 721 } 722 723 if ((j == 0) || (j == 0x2fffd)) { 724 memset (dev->enetaddr, 0, ETH_ALEN); 725 debug ("Warning: can't read HW address from SROM.\n"); 726 goto Done; 727 } 728 729 return; 730 731 Done: 732 #ifdef UPDATE_SROM 733 update_srom(dev, bis); 734 #endif 735 return; 736 } 737 #endif /* CONFIG_TULIP_FIX_DAVICOM */ 738 739 #ifdef UPDATE_SROM 740 static void update_srom(struct eth_device *dev, bd_t *bis) 741 { 742 int i; 743 static unsigned short eeprom[0x40] = { 744 0x140b, 0x6610, 0x0000, 0x0000, /* 00 */ 745 0x0000, 0x0000, 0x0000, 0x0000, /* 04 */ 746 0x00a3, 0x0103, 0x0000, 0x0000, /* 08 */ 747 0x0000, 0x1f00, 0x0000, 0x0000, /* 0c */ 748 0x0108, 0x038d, 0x0000, 0x0000, /* 10 */ 749 0xe078, 0x0001, 0x0040, 0x0018, /* 14 */ 750 0x0000, 0x0000, 0x0000, 0x0000, /* 18 */ 751 0x0000, 0x0000, 0x0000, 0x0000, /* 1c */ 752 0x0000, 0x0000, 0x0000, 0x0000, /* 20 */ 753 0x0000, 0x0000, 0x0000, 0x0000, /* 24 */ 754 0x0000, 0x0000, 0x0000, 0x0000, /* 28 */ 755 0x0000, 0x0000, 0x0000, 0x0000, /* 2c */ 756 0x0000, 0x0000, 0x0000, 0x0000, /* 30 */ 757 0x0000, 0x0000, 0x0000, 0x0000, /* 34 */ 758 0x0000, 0x0000, 0x0000, 0x0000, /* 38 */ 759 0x0000, 0x0000, 0x0000, 0x4e07, /* 3c */ 760 }; 761 uchar enetaddr[6]; 762 763 /* Ethernet Addr... */ 764 if (!eth_getenv_enetaddr("ethaddr", enetaddr)) 765 return; 766 eeprom[0x0a] = (enetaddr[1] << 8) | enetaddr[0]; 767 eeprom[0x0b] = (enetaddr[3] << 8) | enetaddr[2]; 768 eeprom[0x0c] = (enetaddr[5] << 8) | enetaddr[4]; 769 770 for (i=0; i<0x40; i++) { 771 write_srom(dev, DE4X5_APROM, i, eeprom[i]); 772 } 773 } 774 #endif /* UPDATE_SROM */ 775