1 /* 2 * See file CREDITS for list of people who contributed to this 3 * project. 4 * 5 * This program is free software; you can redistribute it and/or 6 * modify it under the terms of the GNU General Public License as 7 * published by the Free Software Foundation; either version 2 of 8 * the License, or (at your option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, write to the Free Software 17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 18 * MA 02111-1307 USA 19 */ 20 21 #include <common.h> 22 #include <malloc.h> 23 #include <net.h> 24 #include <pci.h> 25 26 #undef DEBUG_SROM 27 #undef DEBUG_SROM2 28 29 #undef UPDATE_SROM 30 31 /* PCI Registers. 32 */ 33 #define PCI_CFDA_PSM 0x43 34 35 #define CFRV_RN 0x000000f0 /* Revision Number */ 36 37 #define WAKEUP 0x00 /* Power Saving Wakeup */ 38 #define SLEEP 0x80 /* Power Saving Sleep Mode */ 39 40 #define DC2114x_BRK 0x0020 /* CFRV break between DC21142 & DC21143 */ 41 42 /* Ethernet chip registers. 43 */ 44 #define DE4X5_BMR 0x000 /* Bus Mode Register */ 45 #define DE4X5_TPD 0x008 /* Transmit Poll Demand Reg */ 46 #define DE4X5_RRBA 0x018 /* RX Ring Base Address Reg */ 47 #define DE4X5_TRBA 0x020 /* TX Ring Base Address Reg */ 48 #define DE4X5_STS 0x028 /* Status Register */ 49 #define DE4X5_OMR 0x030 /* Operation Mode Register */ 50 #define DE4X5_SICR 0x068 /* SIA Connectivity Register */ 51 #define DE4X5_APROM 0x048 /* Ethernet Address PROM */ 52 53 /* Register bits. 54 */ 55 #define BMR_SWR 0x00000001 /* Software Reset */ 56 #define STS_TS 0x00700000 /* Transmit Process State */ 57 #define STS_RS 0x000e0000 /* Receive Process State */ 58 #define OMR_ST 0x00002000 /* Start/Stop Transmission Command */ 59 #define OMR_SR 0x00000002 /* Start/Stop Receive */ 60 #define OMR_PS 0x00040000 /* Port Select */ 61 #define OMR_SDP 0x02000000 /* SD Polarity - MUST BE ASSERTED */ 62 #define OMR_PM 0x00000080 /* Pass All Multicast */ 63 64 /* Descriptor bits. 65 */ 66 #define R_OWN 0x80000000 /* Own Bit */ 67 #define RD_RER 0x02000000 /* Receive End Of Ring */ 68 #define RD_LS 0x00000100 /* Last Descriptor */ 69 #define RD_ES 0x00008000 /* Error Summary */ 70 #define TD_TER 0x02000000 /* Transmit End Of Ring */ 71 #define T_OWN 0x80000000 /* Own Bit */ 72 #define TD_LS 0x40000000 /* Last Segment */ 73 #define TD_FS 0x20000000 /* First Segment */ 74 #define TD_ES 0x00008000 /* Error Summary */ 75 #define TD_SET 0x08000000 /* Setup Packet */ 76 77 /* The EEPROM commands include the alway-set leading bit. */ 78 #define SROM_WRITE_CMD 5 79 #define SROM_READ_CMD 6 80 #define SROM_ERASE_CMD 7 81 82 #define SROM_HWADD 0x0014 /* Hardware Address offset in SROM */ 83 #define SROM_RD 0x00004000 /* Read from Boot ROM */ 84 #define EE_DATA_WRITE 0x04 /* EEPROM chip data in. */ 85 #define EE_WRITE_0 0x4801 86 #define EE_WRITE_1 0x4805 87 #define EE_DATA_READ 0x08 /* EEPROM chip data out. */ 88 #define SROM_SR 0x00000800 /* Select Serial ROM when set */ 89 90 #define DT_IN 0x00000004 /* Serial Data In */ 91 #define DT_CLK 0x00000002 /* Serial ROM Clock */ 92 #define DT_CS 0x00000001 /* Serial ROM Chip Select */ 93 94 #define POLL_DEMAND 1 95 96 #ifdef CONFIG_TULIP_FIX_DAVICOM 97 #define RESET_DM9102(dev) {\ 98 unsigned long i;\ 99 i=INL(dev, 0x0);\ 100 udelay(1000);\ 101 OUTL(dev, i | BMR_SWR, DE4X5_BMR);\ 102 udelay(1000);\ 103 } 104 #else 105 #define RESET_DE4X5(dev) {\ 106 int i;\ 107 i=INL(dev, DE4X5_BMR);\ 108 udelay(1000);\ 109 OUTL(dev, i | BMR_SWR, DE4X5_BMR);\ 110 udelay(1000);\ 111 OUTL(dev, i, DE4X5_BMR);\ 112 udelay(1000);\ 113 for (i=0;i<5;i++) {INL(dev, DE4X5_BMR); udelay(10000);}\ 114 udelay(1000);\ 115 } 116 #endif 117 118 #define START_DE4X5(dev) {\ 119 s32 omr; \ 120 omr = INL(dev, DE4X5_OMR);\ 121 omr |= OMR_ST | OMR_SR;\ 122 OUTL(dev, omr, DE4X5_OMR); /* Enable the TX and/or RX */\ 123 } 124 125 #define STOP_DE4X5(dev) {\ 126 s32 omr; \ 127 omr = INL(dev, DE4X5_OMR);\ 128 omr &= ~(OMR_ST|OMR_SR);\ 129 OUTL(dev, omr, DE4X5_OMR); /* Disable the TX and/or RX */ \ 130 } 131 132 #define NUM_RX_DESC PKTBUFSRX 133 #ifndef CONFIG_TULIP_FIX_DAVICOM 134 #define NUM_TX_DESC 1 /* Number of TX descriptors */ 135 #else 136 #define NUM_TX_DESC 4 137 #endif 138 #define RX_BUFF_SZ PKTSIZE_ALIGN 139 140 #define TOUT_LOOP 1000000 141 142 #define SETUP_FRAME_LEN 192 143 #define ETH_ALEN 6 144 145 struct de4x5_desc { 146 volatile s32 status; 147 u32 des1; 148 u32 buf; 149 u32 next; 150 }; 151 152 static struct de4x5_desc rx_ring[NUM_RX_DESC] __attribute__ ((aligned(32))); /* RX descriptor ring */ 153 static struct de4x5_desc tx_ring[NUM_TX_DESC] __attribute__ ((aligned(32))); /* TX descriptor ring */ 154 static int rx_new; /* RX descriptor ring pointer */ 155 static int tx_new; /* TX descriptor ring pointer */ 156 157 static char rxRingSize; 158 static char txRingSize; 159 160 #if defined(UPDATE_SROM) || !defined(CONFIG_TULIP_FIX_DAVICOM) 161 static void sendto_srom(struct eth_device* dev, u_int command, u_long addr); 162 static int getfrom_srom(struct eth_device* dev, u_long addr); 163 static int do_eeprom_cmd(struct eth_device *dev, u_long ioaddr,int cmd,int cmd_len); 164 static int do_read_eeprom(struct eth_device *dev,u_long ioaddr,int location,int addr_len); 165 #endif /* UPDATE_SROM || !CONFIG_TULIP_FIX_DAVICOM */ 166 #ifdef UPDATE_SROM 167 static int write_srom(struct eth_device *dev, u_long ioaddr, int index, int new_value); 168 static void update_srom(struct eth_device *dev, bd_t *bis); 169 #endif 170 #ifndef CONFIG_TULIP_FIX_DAVICOM 171 static int read_srom(struct eth_device *dev, u_long ioaddr, int index); 172 static void read_hw_addr(struct eth_device* dev, bd_t * bis); 173 #endif /* CONFIG_TULIP_FIX_DAVICOM */ 174 static void send_setup_frame(struct eth_device* dev, bd_t * bis); 175 176 static int dc21x4x_init(struct eth_device* dev, bd_t* bis); 177 static int dc21x4x_send(struct eth_device* dev, volatile void *packet, int length); 178 static int dc21x4x_recv(struct eth_device* dev); 179 static void dc21x4x_halt(struct eth_device* dev); 180 #ifdef CONFIG_TULIP_SELECT_MEDIA 181 extern void dc21x4x_select_media(struct eth_device* dev); 182 #endif 183 184 #if defined(CONFIG_E500) 185 #define phys_to_bus(a) (a) 186 #else 187 #define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)dev->priv, a) 188 #endif 189 190 static int INL(struct eth_device* dev, u_long addr) 191 { 192 return le32_to_cpu(*(volatile u_long *)(addr + dev->iobase)); 193 } 194 195 static void OUTL(struct eth_device* dev, int command, u_long addr) 196 { 197 *(volatile u_long *)(addr + dev->iobase) = cpu_to_le32(command); 198 } 199 200 static struct pci_device_id supported[] = { 201 { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TULIP_FAST }, 202 { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21142 }, 203 #ifdef CONFIG_TULIP_FIX_DAVICOM 204 { PCI_VENDOR_ID_DAVICOM, PCI_DEVICE_ID_DAVICOM_DM9102A }, 205 #endif 206 { } 207 }; 208 209 int dc21x4x_initialize(bd_t *bis) 210 { 211 int idx=0; 212 int card_number = 0; 213 unsigned int cfrv; 214 unsigned char timer; 215 pci_dev_t devbusfn; 216 unsigned int iobase; 217 unsigned short status; 218 struct eth_device* dev; 219 220 while(1) { 221 devbusfn = pci_find_devices(supported, idx++); 222 if (devbusfn == -1) { 223 break; 224 } 225 226 /* Get the chip configuration revision register. */ 227 pci_read_config_dword(devbusfn, PCI_REVISION_ID, &cfrv); 228 229 #ifndef CONFIG_TULIP_FIX_DAVICOM 230 if ((cfrv & CFRV_RN) < DC2114x_BRK ) { 231 printf("Error: The chip is not DC21143.\n"); 232 continue; 233 } 234 #endif 235 236 pci_read_config_word(devbusfn, PCI_COMMAND, &status); 237 status |= 238 #ifdef CONFIG_TULIP_USE_IO 239 PCI_COMMAND_IO | 240 #else 241 PCI_COMMAND_MEMORY | 242 #endif 243 PCI_COMMAND_MASTER; 244 pci_write_config_word(devbusfn, PCI_COMMAND, status); 245 246 pci_read_config_word(devbusfn, PCI_COMMAND, &status); 247 if (!(status & PCI_COMMAND_IO)) { 248 printf("Error: Can not enable I/O access.\n"); 249 continue; 250 } 251 252 if (!(status & PCI_COMMAND_IO)) { 253 printf("Error: Can not enable I/O access.\n"); 254 continue; 255 } 256 257 if (!(status & PCI_COMMAND_MASTER)) { 258 printf("Error: Can not enable Bus Mastering.\n"); 259 continue; 260 } 261 262 /* Check the latency timer for values >= 0x60. */ 263 pci_read_config_byte(devbusfn, PCI_LATENCY_TIMER, &timer); 264 265 if (timer < 0x60) { 266 pci_write_config_byte(devbusfn, PCI_LATENCY_TIMER, 0x60); 267 } 268 269 #ifdef CONFIG_TULIP_USE_IO 270 /* read BAR for memory space access */ 271 pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, &iobase); 272 iobase &= PCI_BASE_ADDRESS_IO_MASK; 273 #else 274 /* read BAR for memory space access */ 275 pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_1, &iobase); 276 iobase &= PCI_BASE_ADDRESS_MEM_MASK; 277 #endif 278 debug ("dc21x4x: DEC 21142 PCI Device @0x%x\n", iobase); 279 280 dev = (struct eth_device*) malloc(sizeof *dev); 281 282 #ifdef CONFIG_TULIP_FIX_DAVICOM 283 sprintf(dev->name, "Davicom#%d", card_number); 284 #else 285 sprintf(dev->name, "dc21x4x#%d", card_number); 286 #endif 287 288 #ifdef CONFIG_TULIP_USE_IO 289 dev->iobase = pci_io_to_phys(devbusfn, iobase); 290 #else 291 dev->iobase = pci_mem_to_phys(devbusfn, iobase); 292 #endif 293 dev->priv = (void*) devbusfn; 294 dev->init = dc21x4x_init; 295 dev->halt = dc21x4x_halt; 296 dev->send = dc21x4x_send; 297 dev->recv = dc21x4x_recv; 298 299 /* Ensure we're not sleeping. */ 300 pci_write_config_byte(devbusfn, PCI_CFDA_PSM, WAKEUP); 301 302 udelay(10 * 1000); 303 304 #ifndef CONFIG_TULIP_FIX_DAVICOM 305 read_hw_addr(dev, bis); 306 #endif 307 eth_register(dev); 308 309 card_number++; 310 } 311 312 return card_number; 313 } 314 315 static int dc21x4x_init(struct eth_device* dev, bd_t* bis) 316 { 317 int i; 318 int devbusfn = (int) dev->priv; 319 320 /* Ensure we're not sleeping. */ 321 pci_write_config_byte(devbusfn, PCI_CFDA_PSM, WAKEUP); 322 323 #ifdef CONFIG_TULIP_FIX_DAVICOM 324 RESET_DM9102(dev); 325 #else 326 RESET_DE4X5(dev); 327 #endif 328 329 if ((INL(dev, DE4X5_STS) & (STS_TS | STS_RS)) != 0) { 330 printf("Error: Cannot reset ethernet controller.\n"); 331 return -1; 332 } 333 334 #ifdef CONFIG_TULIP_SELECT_MEDIA 335 dc21x4x_select_media(dev); 336 #else 337 OUTL(dev, OMR_SDP | OMR_PS | OMR_PM, DE4X5_OMR); 338 #endif 339 340 for (i = 0; i < NUM_RX_DESC; i++) { 341 rx_ring[i].status = cpu_to_le32(R_OWN); 342 rx_ring[i].des1 = cpu_to_le32(RX_BUFF_SZ); 343 rx_ring[i].buf = cpu_to_le32(phys_to_bus((u32) NetRxPackets[i])); 344 #ifdef CONFIG_TULIP_FIX_DAVICOM 345 rx_ring[i].next = cpu_to_le32(phys_to_bus((u32) &rx_ring[(i+1) % NUM_RX_DESC])); 346 #else 347 rx_ring[i].next = 0; 348 #endif 349 } 350 351 for (i=0; i < NUM_TX_DESC; i++) { 352 tx_ring[i].status = 0; 353 tx_ring[i].des1 = 0; 354 tx_ring[i].buf = 0; 355 356 #ifdef CONFIG_TULIP_FIX_DAVICOM 357 tx_ring[i].next = cpu_to_le32(phys_to_bus((u32) &tx_ring[(i+1) % NUM_TX_DESC])); 358 #else 359 tx_ring[i].next = 0; 360 #endif 361 } 362 363 rxRingSize = NUM_RX_DESC; 364 txRingSize = NUM_TX_DESC; 365 366 /* Write the end of list marker to the descriptor lists. */ 367 rx_ring[rxRingSize - 1].des1 |= cpu_to_le32(RD_RER); 368 tx_ring[txRingSize - 1].des1 |= cpu_to_le32(TD_TER); 369 370 /* Tell the adapter where the TX/RX rings are located. */ 371 OUTL(dev, phys_to_bus((u32) &rx_ring), DE4X5_RRBA); 372 OUTL(dev, phys_to_bus((u32) &tx_ring), DE4X5_TRBA); 373 374 START_DE4X5(dev); 375 376 tx_new = 0; 377 rx_new = 0; 378 379 send_setup_frame(dev, bis); 380 381 return 0; 382 } 383 384 static int dc21x4x_send(struct eth_device* dev, volatile void *packet, int length) 385 { 386 int status = -1; 387 int i; 388 389 if (length <= 0) { 390 printf("%s: bad packet size: %d\n", dev->name, length); 391 goto Done; 392 } 393 394 for(i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) { 395 if (i >= TOUT_LOOP) { 396 printf("%s: tx error buffer not ready\n", dev->name); 397 goto Done; 398 } 399 } 400 401 tx_ring[tx_new].buf = cpu_to_le32(phys_to_bus((u32) packet)); 402 tx_ring[tx_new].des1 = cpu_to_le32(TD_TER | TD_LS | TD_FS | length); 403 tx_ring[tx_new].status = cpu_to_le32(T_OWN); 404 405 OUTL(dev, POLL_DEMAND, DE4X5_TPD); 406 407 for(i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) { 408 if (i >= TOUT_LOOP) { 409 printf(".%s: tx buffer not ready\n", dev->name); 410 goto Done; 411 } 412 } 413 414 if (le32_to_cpu(tx_ring[tx_new].status) & TD_ES) { 415 #if 0 /* test-only */ 416 printf("TX error status = 0x%08X\n", 417 le32_to_cpu(tx_ring[tx_new].status)); 418 #endif 419 tx_ring[tx_new].status = 0x0; 420 goto Done; 421 } 422 423 status = length; 424 425 Done: 426 tx_new = (tx_new+1) % NUM_TX_DESC; 427 return status; 428 } 429 430 static int dc21x4x_recv(struct eth_device* dev) 431 { 432 s32 status; 433 int length = 0; 434 435 for ( ; ; ) { 436 status = (s32)le32_to_cpu(rx_ring[rx_new].status); 437 438 if (status & R_OWN) { 439 break; 440 } 441 442 if (status & RD_LS) { 443 /* Valid frame status. 444 */ 445 if (status & RD_ES) { 446 447 /* There was an error. 448 */ 449 printf("RX error status = 0x%08X\n", status); 450 } else { 451 /* A valid frame received. 452 */ 453 length = (le32_to_cpu(rx_ring[rx_new].status) >> 16); 454 455 /* Pass the packet up to the protocol 456 * layers. 457 */ 458 NetReceive(NetRxPackets[rx_new], length - 4); 459 } 460 461 /* Change buffer ownership for this frame, back 462 * to the adapter. 463 */ 464 rx_ring[rx_new].status = cpu_to_le32(R_OWN); 465 } 466 467 /* Update entry information. 468 */ 469 rx_new = (rx_new + 1) % rxRingSize; 470 } 471 472 return length; 473 } 474 475 static void dc21x4x_halt(struct eth_device* dev) 476 { 477 int devbusfn = (int) dev->priv; 478 479 STOP_DE4X5(dev); 480 OUTL(dev, 0, DE4X5_SICR); 481 482 pci_write_config_byte(devbusfn, PCI_CFDA_PSM, SLEEP); 483 } 484 485 static void send_setup_frame(struct eth_device* dev, bd_t *bis) 486 { 487 int i; 488 char setup_frame[SETUP_FRAME_LEN]; 489 char *pa = &setup_frame[0]; 490 491 memset(pa, 0xff, SETUP_FRAME_LEN); 492 493 for (i = 0; i < ETH_ALEN; i++) { 494 *(pa + (i & 1)) = dev->enetaddr[i]; 495 if (i & 0x01) { 496 pa += 4; 497 } 498 } 499 500 for(i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) { 501 if (i >= TOUT_LOOP) { 502 printf("%s: tx error buffer not ready\n", dev->name); 503 goto Done; 504 } 505 } 506 507 tx_ring[tx_new].buf = cpu_to_le32(phys_to_bus((u32) &setup_frame[0])); 508 tx_ring[tx_new].des1 = cpu_to_le32(TD_TER | TD_SET| SETUP_FRAME_LEN); 509 tx_ring[tx_new].status = cpu_to_le32(T_OWN); 510 511 OUTL(dev, POLL_DEMAND, DE4X5_TPD); 512 513 for(i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) { 514 if (i >= TOUT_LOOP) { 515 printf("%s: tx buffer not ready\n", dev->name); 516 goto Done; 517 } 518 } 519 520 if (le32_to_cpu(tx_ring[tx_new].status) != 0x7FFFFFFF) { 521 printf("TX error status2 = 0x%08X\n", le32_to_cpu(tx_ring[tx_new].status)); 522 } 523 tx_new = (tx_new+1) % NUM_TX_DESC; 524 525 Done: 526 return; 527 } 528 529 #if defined(UPDATE_SROM) || !defined(CONFIG_TULIP_FIX_DAVICOM) 530 /* SROM Read and write routines. 531 */ 532 static void 533 sendto_srom(struct eth_device* dev, u_int command, u_long addr) 534 { 535 OUTL(dev, command, addr); 536 udelay(1); 537 } 538 539 static int 540 getfrom_srom(struct eth_device* dev, u_long addr) 541 { 542 s32 tmp; 543 544 tmp = INL(dev, addr); 545 udelay(1); 546 547 return tmp; 548 } 549 550 /* Note: this routine returns extra data bits for size detection. */ 551 static int do_read_eeprom(struct eth_device *dev, u_long ioaddr, int location, int addr_len) 552 { 553 int i; 554 unsigned retval = 0; 555 int read_cmd = location | (SROM_READ_CMD << addr_len); 556 557 sendto_srom(dev, SROM_RD | SROM_SR, ioaddr); 558 sendto_srom(dev, SROM_RD | SROM_SR | DT_CS, ioaddr); 559 560 #ifdef DEBUG_SROM 561 printf(" EEPROM read at %d ", location); 562 #endif 563 564 /* Shift the read command bits out. */ 565 for (i = 4 + addr_len; i >= 0; i--) { 566 short dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0; 567 sendto_srom(dev, SROM_RD | SROM_SR | DT_CS | dataval, ioaddr); 568 udelay(10); 569 sendto_srom(dev, SROM_RD | SROM_SR | DT_CS | dataval | DT_CLK, ioaddr); 570 udelay(10); 571 #ifdef DEBUG_SROM2 572 printf("%X", getfrom_srom(dev, ioaddr) & 15); 573 #endif 574 retval = (retval << 1) | ((getfrom_srom(dev, ioaddr) & EE_DATA_READ) ? 1 : 0); 575 } 576 577 sendto_srom(dev, SROM_RD | SROM_SR | DT_CS, ioaddr); 578 579 #ifdef DEBUG_SROM2 580 printf(" :%X:", getfrom_srom(dev, ioaddr) & 15); 581 #endif 582 583 for (i = 16; i > 0; i--) { 584 sendto_srom(dev, SROM_RD | SROM_SR | DT_CS | DT_CLK, ioaddr); 585 udelay(10); 586 #ifdef DEBUG_SROM2 587 printf("%X", getfrom_srom(dev, ioaddr) & 15); 588 #endif 589 retval = (retval << 1) | ((getfrom_srom(dev, ioaddr) & EE_DATA_READ) ? 1 : 0); 590 sendto_srom(dev, SROM_RD | SROM_SR | DT_CS, ioaddr); 591 udelay(10); 592 } 593 594 /* Terminate the EEPROM access. */ 595 sendto_srom(dev, SROM_RD | SROM_SR, ioaddr); 596 597 #ifdef DEBUG_SROM2 598 printf(" EEPROM value at %d is %5.5x.\n", location, retval); 599 #endif 600 601 return retval; 602 } 603 #endif /* UPDATE_SROM || !CONFIG_TULIP_FIX_DAVICOM */ 604 605 /* This executes a generic EEPROM command, typically a write or write 606 * enable. It returns the data output from the EEPROM, and thus may 607 * also be used for reads. 608 */ 609 #if defined(UPDATE_SROM) || !defined(CONFIG_TULIP_FIX_DAVICOM) 610 static int do_eeprom_cmd(struct eth_device *dev, u_long ioaddr, int cmd, int cmd_len) 611 { 612 unsigned retval = 0; 613 614 #ifdef DEBUG_SROM 615 printf(" EEPROM op 0x%x: ", cmd); 616 #endif 617 618 sendto_srom(dev,SROM_RD | SROM_SR | DT_CS | DT_CLK, ioaddr); 619 620 /* Shift the command bits out. */ 621 do { 622 short dataval = (cmd & (1 << cmd_len)) ? EE_WRITE_1 : EE_WRITE_0; 623 sendto_srom(dev,dataval, ioaddr); 624 udelay(10); 625 626 #ifdef DEBUG_SROM2 627 printf("%X", getfrom_srom(dev,ioaddr) & 15); 628 #endif 629 630 sendto_srom(dev,dataval | DT_CLK, ioaddr); 631 udelay(10); 632 retval = (retval << 1) | ((getfrom_srom(dev,ioaddr) & EE_DATA_READ) ? 1 : 0); 633 } while (--cmd_len >= 0); 634 sendto_srom(dev,SROM_RD | SROM_SR | DT_CS, ioaddr); 635 636 /* Terminate the EEPROM access. */ 637 sendto_srom(dev,SROM_RD | SROM_SR, ioaddr); 638 639 #ifdef DEBUG_SROM 640 printf(" EEPROM result is 0x%5.5x.\n", retval); 641 #endif 642 643 return retval; 644 } 645 #endif /* UPDATE_SROM || !CONFIG_TULIP_FIX_DAVICOM */ 646 647 #ifndef CONFIG_TULIP_FIX_DAVICOM 648 static int read_srom(struct eth_device *dev, u_long ioaddr, int index) 649 { 650 int ee_addr_size = do_read_eeprom(dev, ioaddr, 0xff, 8) & 0x40000 ? 8 : 6; 651 652 return do_eeprom_cmd(dev, ioaddr, 653 (((SROM_READ_CMD << ee_addr_size) | index) << 16) 654 | 0xffff, 3 + ee_addr_size + 16); 655 } 656 #endif /* CONFIG_TULIP_FIX_DAVICOM */ 657 658 #ifdef UPDATE_SROM 659 static int write_srom(struct eth_device *dev, u_long ioaddr, int index, int new_value) 660 { 661 int ee_addr_size = do_read_eeprom(dev, ioaddr, 0xff, 8) & 0x40000 ? 8 : 6; 662 int i; 663 unsigned short newval; 664 665 udelay(10*1000); /* test-only */ 666 667 #ifdef DEBUG_SROM 668 printf("ee_addr_size=%d.\n", ee_addr_size); 669 printf("Writing new entry 0x%4.4x to offset %d.\n", new_value, index); 670 #endif 671 672 /* Enable programming modes. */ 673 do_eeprom_cmd(dev, ioaddr, (0x4f << (ee_addr_size-4)), 3+ee_addr_size); 674 675 /* Do the actual write. */ 676 do_eeprom_cmd(dev, ioaddr, 677 (((SROM_WRITE_CMD<<ee_addr_size)|index) << 16) | new_value, 678 3 + ee_addr_size + 16); 679 680 /* Poll for write finished. */ 681 sendto_srom(dev, SROM_RD | SROM_SR | DT_CS, ioaddr); 682 for (i = 0; i < 10000; i++) /* Typical 2000 ticks */ 683 if (getfrom_srom(dev, ioaddr) & EE_DATA_READ) 684 break; 685 686 #ifdef DEBUG_SROM 687 printf(" Write finished after %d ticks.\n", i); 688 #endif 689 690 /* Disable programming. */ 691 do_eeprom_cmd(dev, ioaddr, (0x40 << (ee_addr_size-4)), 3 + ee_addr_size); 692 693 /* And read the result. */ 694 newval = do_eeprom_cmd(dev, ioaddr, 695 (((SROM_READ_CMD<<ee_addr_size)|index) << 16) 696 | 0xffff, 3 + ee_addr_size + 16); 697 #ifdef DEBUG_SROM 698 printf(" New value at offset %d is %4.4x.\n", index, newval); 699 #endif 700 return 1; 701 } 702 #endif 703 704 #ifndef CONFIG_TULIP_FIX_DAVICOM 705 static void read_hw_addr(struct eth_device *dev, bd_t *bis) 706 { 707 u_short tmp, *p = (u_short *)(&dev->enetaddr[0]); 708 int i, j = 0; 709 710 for (i = 0; i < (ETH_ALEN >> 1); i++) { 711 tmp = read_srom(dev, DE4X5_APROM, ((SROM_HWADD >> 1) + i)); 712 *p = le16_to_cpu(tmp); 713 j += *p++; 714 } 715 716 if ((j == 0) || (j == 0x2fffd)) { 717 memset (dev->enetaddr, 0, ETH_ALEN); 718 debug ("Warning: can't read HW address from SROM.\n"); 719 goto Done; 720 } 721 722 return; 723 724 Done: 725 #ifdef UPDATE_SROM 726 update_srom(dev, bis); 727 #endif 728 return; 729 } 730 #endif /* CONFIG_TULIP_FIX_DAVICOM */ 731 732 #ifdef UPDATE_SROM 733 static void update_srom(struct eth_device *dev, bd_t *bis) 734 { 735 int i; 736 static unsigned short eeprom[0x40] = { 737 0x140b, 0x6610, 0x0000, 0x0000, /* 00 */ 738 0x0000, 0x0000, 0x0000, 0x0000, /* 04 */ 739 0x00a3, 0x0103, 0x0000, 0x0000, /* 08 */ 740 0x0000, 0x1f00, 0x0000, 0x0000, /* 0c */ 741 0x0108, 0x038d, 0x0000, 0x0000, /* 10 */ 742 0xe078, 0x0001, 0x0040, 0x0018, /* 14 */ 743 0x0000, 0x0000, 0x0000, 0x0000, /* 18 */ 744 0x0000, 0x0000, 0x0000, 0x0000, /* 1c */ 745 0x0000, 0x0000, 0x0000, 0x0000, /* 20 */ 746 0x0000, 0x0000, 0x0000, 0x0000, /* 24 */ 747 0x0000, 0x0000, 0x0000, 0x0000, /* 28 */ 748 0x0000, 0x0000, 0x0000, 0x0000, /* 2c */ 749 0x0000, 0x0000, 0x0000, 0x0000, /* 30 */ 750 0x0000, 0x0000, 0x0000, 0x0000, /* 34 */ 751 0x0000, 0x0000, 0x0000, 0x0000, /* 38 */ 752 0x0000, 0x0000, 0x0000, 0x4e07, /* 3c */ 753 }; 754 755 /* Ethernet Addr... */ 756 eeprom[0x0a] = ((bis->bi_enetaddr[1] & 0xff) << 8) | (bis->bi_enetaddr[0] & 0xff); 757 eeprom[0x0b] = ((bis->bi_enetaddr[3] & 0xff) << 8) | (bis->bi_enetaddr[2] & 0xff); 758 eeprom[0x0c] = ((bis->bi_enetaddr[5] & 0xff) << 8) | (bis->bi_enetaddr[4] & 0xff); 759 760 for (i=0; i<0x40; i++) { 761 write_srom(dev, DE4X5_APROM, i, eeprom[i]); 762 } 763 } 764 #endif /* UPDATE_SROM */ 765