1 /* 2 * See file CREDITS for list of people who contributed to this 3 * project. 4 * 5 * This program is free software; you can redistribute it and/or 6 * modify it under the terms of the GNU General Public License as 7 * published by the Free Software Foundation; either version 2 of 8 * the License, or (at your option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, write to the Free Software 17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 18 * MA 02111-1307 USA 19 */ 20 21 #include <common.h> 22 #include <malloc.h> 23 #include <net.h> 24 #include <netdev.h> 25 #include <pci.h> 26 27 #undef DEBUG_SROM 28 #undef DEBUG_SROM2 29 30 #undef UPDATE_SROM 31 32 /* PCI Registers. 33 */ 34 #define PCI_CFDA_PSM 0x43 35 36 #define CFRV_RN 0x000000f0 /* Revision Number */ 37 38 #define WAKEUP 0x00 /* Power Saving Wakeup */ 39 #define SLEEP 0x80 /* Power Saving Sleep Mode */ 40 41 #define DC2114x_BRK 0x0020 /* CFRV break between DC21142 & DC21143 */ 42 43 /* Ethernet chip registers. 44 */ 45 #define DE4X5_BMR 0x000 /* Bus Mode Register */ 46 #define DE4X5_TPD 0x008 /* Transmit Poll Demand Reg */ 47 #define DE4X5_RRBA 0x018 /* RX Ring Base Address Reg */ 48 #define DE4X5_TRBA 0x020 /* TX Ring Base Address Reg */ 49 #define DE4X5_STS 0x028 /* Status Register */ 50 #define DE4X5_OMR 0x030 /* Operation Mode Register */ 51 #define DE4X5_SICR 0x068 /* SIA Connectivity Register */ 52 #define DE4X5_APROM 0x048 /* Ethernet Address PROM */ 53 54 /* Register bits. 55 */ 56 #define BMR_SWR 0x00000001 /* Software Reset */ 57 #define STS_TS 0x00700000 /* Transmit Process State */ 58 #define STS_RS 0x000e0000 /* Receive Process State */ 59 #define OMR_ST 0x00002000 /* Start/Stop Transmission Command */ 60 #define OMR_SR 0x00000002 /* Start/Stop Receive */ 61 #define OMR_PS 0x00040000 /* Port Select */ 62 #define OMR_SDP 0x02000000 /* SD Polarity - MUST BE ASSERTED */ 63 #define OMR_PM 0x00000080 /* Pass All Multicast */ 64 65 /* Descriptor bits. 66 */ 67 #define R_OWN 0x80000000 /* Own Bit */ 68 #define RD_RER 0x02000000 /* Receive End Of Ring */ 69 #define RD_LS 0x00000100 /* Last Descriptor */ 70 #define RD_ES 0x00008000 /* Error Summary */ 71 #define TD_TER 0x02000000 /* Transmit End Of Ring */ 72 #define T_OWN 0x80000000 /* Own Bit */ 73 #define TD_LS 0x40000000 /* Last Segment */ 74 #define TD_FS 0x20000000 /* First Segment */ 75 #define TD_ES 0x00008000 /* Error Summary */ 76 #define TD_SET 0x08000000 /* Setup Packet */ 77 78 /* The EEPROM commands include the alway-set leading bit. */ 79 #define SROM_WRITE_CMD 5 80 #define SROM_READ_CMD 6 81 #define SROM_ERASE_CMD 7 82 83 #define SROM_HWADD 0x0014 /* Hardware Address offset in SROM */ 84 #define SROM_RD 0x00004000 /* Read from Boot ROM */ 85 #define EE_DATA_WRITE 0x04 /* EEPROM chip data in. */ 86 #define EE_WRITE_0 0x4801 87 #define EE_WRITE_1 0x4805 88 #define EE_DATA_READ 0x08 /* EEPROM chip data out. */ 89 #define SROM_SR 0x00000800 /* Select Serial ROM when set */ 90 91 #define DT_IN 0x00000004 /* Serial Data In */ 92 #define DT_CLK 0x00000002 /* Serial ROM Clock */ 93 #define DT_CS 0x00000001 /* Serial ROM Chip Select */ 94 95 #define POLL_DEMAND 1 96 97 #ifdef CONFIG_TULIP_FIX_DAVICOM 98 #define RESET_DM9102(dev) {\ 99 unsigned long i;\ 100 i=INL(dev, 0x0);\ 101 udelay(1000);\ 102 OUTL(dev, i | BMR_SWR, DE4X5_BMR);\ 103 udelay(1000);\ 104 } 105 #else 106 #define RESET_DE4X5(dev) {\ 107 int i;\ 108 i=INL(dev, DE4X5_BMR);\ 109 udelay(1000);\ 110 OUTL(dev, i | BMR_SWR, DE4X5_BMR);\ 111 udelay(1000);\ 112 OUTL(dev, i, DE4X5_BMR);\ 113 udelay(1000);\ 114 for (i=0;i<5;i++) {INL(dev, DE4X5_BMR); udelay(10000);}\ 115 udelay(1000);\ 116 } 117 #endif 118 119 #define START_DE4X5(dev) {\ 120 s32 omr; \ 121 omr = INL(dev, DE4X5_OMR);\ 122 omr |= OMR_ST | OMR_SR;\ 123 OUTL(dev, omr, DE4X5_OMR); /* Enable the TX and/or RX */\ 124 } 125 126 #define STOP_DE4X5(dev) {\ 127 s32 omr; \ 128 omr = INL(dev, DE4X5_OMR);\ 129 omr &= ~(OMR_ST|OMR_SR);\ 130 OUTL(dev, omr, DE4X5_OMR); /* Disable the TX and/or RX */ \ 131 } 132 133 #define NUM_RX_DESC PKTBUFSRX 134 #ifndef CONFIG_TULIP_FIX_DAVICOM 135 #define NUM_TX_DESC 1 /* Number of TX descriptors */ 136 #else 137 #define NUM_TX_DESC 4 138 #endif 139 #define RX_BUFF_SZ PKTSIZE_ALIGN 140 141 #define TOUT_LOOP 1000000 142 143 #define SETUP_FRAME_LEN 192 144 #define ETH_ALEN 6 145 146 struct de4x5_desc { 147 volatile s32 status; 148 u32 des1; 149 u32 buf; 150 u32 next; 151 }; 152 153 static struct de4x5_desc rx_ring[NUM_RX_DESC] __attribute__ ((aligned(32))); /* RX descriptor ring */ 154 static struct de4x5_desc tx_ring[NUM_TX_DESC] __attribute__ ((aligned(32))); /* TX descriptor ring */ 155 static int rx_new; /* RX descriptor ring pointer */ 156 static int tx_new; /* TX descriptor ring pointer */ 157 158 static char rxRingSize; 159 static char txRingSize; 160 161 #if defined(UPDATE_SROM) || !defined(CONFIG_TULIP_FIX_DAVICOM) 162 static void sendto_srom(struct eth_device* dev, u_int command, u_long addr); 163 static int getfrom_srom(struct eth_device* dev, u_long addr); 164 static int do_eeprom_cmd(struct eth_device *dev, u_long ioaddr,int cmd,int cmd_len); 165 static int do_read_eeprom(struct eth_device *dev,u_long ioaddr,int location,int addr_len); 166 #endif /* UPDATE_SROM || !CONFIG_TULIP_FIX_DAVICOM */ 167 #ifdef UPDATE_SROM 168 static int write_srom(struct eth_device *dev, u_long ioaddr, int index, int new_value); 169 static void update_srom(struct eth_device *dev, bd_t *bis); 170 #endif 171 #ifndef CONFIG_TULIP_FIX_DAVICOM 172 static int read_srom(struct eth_device *dev, u_long ioaddr, int index); 173 static void read_hw_addr(struct eth_device* dev, bd_t * bis); 174 #endif /* CONFIG_TULIP_FIX_DAVICOM */ 175 static void send_setup_frame(struct eth_device* dev, bd_t * bis); 176 177 static int dc21x4x_init(struct eth_device* dev, bd_t* bis); 178 static int dc21x4x_send(struct eth_device* dev, volatile void *packet, int length); 179 static int dc21x4x_recv(struct eth_device* dev); 180 static void dc21x4x_halt(struct eth_device* dev); 181 #ifdef CONFIG_TULIP_SELECT_MEDIA 182 extern void dc21x4x_select_media(struct eth_device* dev); 183 #endif 184 185 #if defined(CONFIG_E500) 186 #define phys_to_bus(a) (a) 187 #else 188 #define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)dev->priv, a) 189 #endif 190 191 static int INL(struct eth_device* dev, u_long addr) 192 { 193 return le32_to_cpu(*(volatile u_long *)(addr + dev->iobase)); 194 } 195 196 static void OUTL(struct eth_device* dev, int command, u_long addr) 197 { 198 *(volatile u_long *)(addr + dev->iobase) = cpu_to_le32(command); 199 } 200 201 static struct pci_device_id supported[] = { 202 { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TULIP_FAST }, 203 { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21142 }, 204 #ifdef CONFIG_TULIP_FIX_DAVICOM 205 { PCI_VENDOR_ID_DAVICOM, PCI_DEVICE_ID_DAVICOM_DM9102A }, 206 #endif 207 { } 208 }; 209 210 int dc21x4x_initialize(bd_t *bis) 211 { 212 int idx=0; 213 int card_number = 0; 214 unsigned int cfrv; 215 unsigned char timer; 216 pci_dev_t devbusfn; 217 unsigned int iobase; 218 unsigned short status; 219 struct eth_device* dev; 220 221 while(1) { 222 devbusfn = pci_find_devices(supported, idx++); 223 if (devbusfn == -1) { 224 break; 225 } 226 227 /* Get the chip configuration revision register. */ 228 pci_read_config_dword(devbusfn, PCI_REVISION_ID, &cfrv); 229 230 #ifndef CONFIG_TULIP_FIX_DAVICOM 231 if ((cfrv & CFRV_RN) < DC2114x_BRK ) { 232 printf("Error: The chip is not DC21143.\n"); 233 continue; 234 } 235 #endif 236 237 pci_read_config_word(devbusfn, PCI_COMMAND, &status); 238 status |= 239 #ifdef CONFIG_TULIP_USE_IO 240 PCI_COMMAND_IO | 241 #else 242 PCI_COMMAND_MEMORY | 243 #endif 244 PCI_COMMAND_MASTER; 245 pci_write_config_word(devbusfn, PCI_COMMAND, status); 246 247 pci_read_config_word(devbusfn, PCI_COMMAND, &status); 248 if (!(status & PCI_COMMAND_IO)) { 249 printf("Error: Can not enable I/O access.\n"); 250 continue; 251 } 252 253 if (!(status & PCI_COMMAND_IO)) { 254 printf("Error: Can not enable I/O access.\n"); 255 continue; 256 } 257 258 if (!(status & PCI_COMMAND_MASTER)) { 259 printf("Error: Can not enable Bus Mastering.\n"); 260 continue; 261 } 262 263 /* Check the latency timer for values >= 0x60. */ 264 pci_read_config_byte(devbusfn, PCI_LATENCY_TIMER, &timer); 265 266 if (timer < 0x60) { 267 pci_write_config_byte(devbusfn, PCI_LATENCY_TIMER, 0x60); 268 } 269 270 #ifdef CONFIG_TULIP_USE_IO 271 /* read BAR for memory space access */ 272 pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, &iobase); 273 iobase &= PCI_BASE_ADDRESS_IO_MASK; 274 #else 275 /* read BAR for memory space access */ 276 pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_1, &iobase); 277 iobase &= PCI_BASE_ADDRESS_MEM_MASK; 278 #endif 279 debug ("dc21x4x: DEC 21142 PCI Device @0x%x\n", iobase); 280 281 dev = (struct eth_device*) malloc(sizeof *dev); 282 283 #ifdef CONFIG_TULIP_FIX_DAVICOM 284 sprintf(dev->name, "Davicom#%d", card_number); 285 #else 286 sprintf(dev->name, "dc21x4x#%d", card_number); 287 #endif 288 289 #ifdef CONFIG_TULIP_USE_IO 290 dev->iobase = pci_io_to_phys(devbusfn, iobase); 291 #else 292 dev->iobase = pci_mem_to_phys(devbusfn, iobase); 293 #endif 294 dev->priv = (void*) devbusfn; 295 dev->init = dc21x4x_init; 296 dev->halt = dc21x4x_halt; 297 dev->send = dc21x4x_send; 298 dev->recv = dc21x4x_recv; 299 300 /* Ensure we're not sleeping. */ 301 pci_write_config_byte(devbusfn, PCI_CFDA_PSM, WAKEUP); 302 303 udelay(10 * 1000); 304 305 #ifndef CONFIG_TULIP_FIX_DAVICOM 306 read_hw_addr(dev, bis); 307 #endif 308 eth_register(dev); 309 310 card_number++; 311 } 312 313 return card_number; 314 } 315 316 static int dc21x4x_init(struct eth_device* dev, bd_t* bis) 317 { 318 int i; 319 int devbusfn = (int) dev->priv; 320 321 /* Ensure we're not sleeping. */ 322 pci_write_config_byte(devbusfn, PCI_CFDA_PSM, WAKEUP); 323 324 #ifdef CONFIG_TULIP_FIX_DAVICOM 325 RESET_DM9102(dev); 326 #else 327 RESET_DE4X5(dev); 328 #endif 329 330 if ((INL(dev, DE4X5_STS) & (STS_TS | STS_RS)) != 0) { 331 printf("Error: Cannot reset ethernet controller.\n"); 332 return -1; 333 } 334 335 #ifdef CONFIG_TULIP_SELECT_MEDIA 336 dc21x4x_select_media(dev); 337 #else 338 OUTL(dev, OMR_SDP | OMR_PS | OMR_PM, DE4X5_OMR); 339 #endif 340 341 for (i = 0; i < NUM_RX_DESC; i++) { 342 rx_ring[i].status = cpu_to_le32(R_OWN); 343 rx_ring[i].des1 = cpu_to_le32(RX_BUFF_SZ); 344 rx_ring[i].buf = cpu_to_le32(phys_to_bus((u32) NetRxPackets[i])); 345 #ifdef CONFIG_TULIP_FIX_DAVICOM 346 rx_ring[i].next = cpu_to_le32(phys_to_bus((u32) &rx_ring[(i+1) % NUM_RX_DESC])); 347 #else 348 rx_ring[i].next = 0; 349 #endif 350 } 351 352 for (i=0; i < NUM_TX_DESC; i++) { 353 tx_ring[i].status = 0; 354 tx_ring[i].des1 = 0; 355 tx_ring[i].buf = 0; 356 357 #ifdef CONFIG_TULIP_FIX_DAVICOM 358 tx_ring[i].next = cpu_to_le32(phys_to_bus((u32) &tx_ring[(i+1) % NUM_TX_DESC])); 359 #else 360 tx_ring[i].next = 0; 361 #endif 362 } 363 364 rxRingSize = NUM_RX_DESC; 365 txRingSize = NUM_TX_DESC; 366 367 /* Write the end of list marker to the descriptor lists. */ 368 rx_ring[rxRingSize - 1].des1 |= cpu_to_le32(RD_RER); 369 tx_ring[txRingSize - 1].des1 |= cpu_to_le32(TD_TER); 370 371 /* Tell the adapter where the TX/RX rings are located. */ 372 OUTL(dev, phys_to_bus((u32) &rx_ring), DE4X5_RRBA); 373 OUTL(dev, phys_to_bus((u32) &tx_ring), DE4X5_TRBA); 374 375 START_DE4X5(dev); 376 377 tx_new = 0; 378 rx_new = 0; 379 380 send_setup_frame(dev, bis); 381 382 return 0; 383 } 384 385 static int dc21x4x_send(struct eth_device* dev, volatile void *packet, int length) 386 { 387 int status = -1; 388 int i; 389 390 if (length <= 0) { 391 printf("%s: bad packet size: %d\n", dev->name, length); 392 goto Done; 393 } 394 395 for(i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) { 396 if (i >= TOUT_LOOP) { 397 printf("%s: tx error buffer not ready\n", dev->name); 398 goto Done; 399 } 400 } 401 402 tx_ring[tx_new].buf = cpu_to_le32(phys_to_bus((u32) packet)); 403 tx_ring[tx_new].des1 = cpu_to_le32(TD_TER | TD_LS | TD_FS | length); 404 tx_ring[tx_new].status = cpu_to_le32(T_OWN); 405 406 OUTL(dev, POLL_DEMAND, DE4X5_TPD); 407 408 for(i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) { 409 if (i >= TOUT_LOOP) { 410 printf(".%s: tx buffer not ready\n", dev->name); 411 goto Done; 412 } 413 } 414 415 if (le32_to_cpu(tx_ring[tx_new].status) & TD_ES) { 416 #if 0 /* test-only */ 417 printf("TX error status = 0x%08X\n", 418 le32_to_cpu(tx_ring[tx_new].status)); 419 #endif 420 tx_ring[tx_new].status = 0x0; 421 goto Done; 422 } 423 424 status = length; 425 426 Done: 427 tx_new = (tx_new+1) % NUM_TX_DESC; 428 return status; 429 } 430 431 static int dc21x4x_recv(struct eth_device* dev) 432 { 433 s32 status; 434 int length = 0; 435 436 for ( ; ; ) { 437 status = (s32)le32_to_cpu(rx_ring[rx_new].status); 438 439 if (status & R_OWN) { 440 break; 441 } 442 443 if (status & RD_LS) { 444 /* Valid frame status. 445 */ 446 if (status & RD_ES) { 447 448 /* There was an error. 449 */ 450 printf("RX error status = 0x%08X\n", status); 451 } else { 452 /* A valid frame received. 453 */ 454 length = (le32_to_cpu(rx_ring[rx_new].status) >> 16); 455 456 /* Pass the packet up to the protocol 457 * layers. 458 */ 459 NetReceive(NetRxPackets[rx_new], length - 4); 460 } 461 462 /* Change buffer ownership for this frame, back 463 * to the adapter. 464 */ 465 rx_ring[rx_new].status = cpu_to_le32(R_OWN); 466 } 467 468 /* Update entry information. 469 */ 470 rx_new = (rx_new + 1) % rxRingSize; 471 } 472 473 return length; 474 } 475 476 static void dc21x4x_halt(struct eth_device* dev) 477 { 478 int devbusfn = (int) dev->priv; 479 480 STOP_DE4X5(dev); 481 OUTL(dev, 0, DE4X5_SICR); 482 483 pci_write_config_byte(devbusfn, PCI_CFDA_PSM, SLEEP); 484 } 485 486 static void send_setup_frame(struct eth_device* dev, bd_t *bis) 487 { 488 int i; 489 char setup_frame[SETUP_FRAME_LEN]; 490 char *pa = &setup_frame[0]; 491 492 memset(pa, 0xff, SETUP_FRAME_LEN); 493 494 for (i = 0; i < ETH_ALEN; i++) { 495 *(pa + (i & 1)) = dev->enetaddr[i]; 496 if (i & 0x01) { 497 pa += 4; 498 } 499 } 500 501 for(i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) { 502 if (i >= TOUT_LOOP) { 503 printf("%s: tx error buffer not ready\n", dev->name); 504 goto Done; 505 } 506 } 507 508 tx_ring[tx_new].buf = cpu_to_le32(phys_to_bus((u32) &setup_frame[0])); 509 tx_ring[tx_new].des1 = cpu_to_le32(TD_TER | TD_SET| SETUP_FRAME_LEN); 510 tx_ring[tx_new].status = cpu_to_le32(T_OWN); 511 512 OUTL(dev, POLL_DEMAND, DE4X5_TPD); 513 514 for(i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) { 515 if (i >= TOUT_LOOP) { 516 printf("%s: tx buffer not ready\n", dev->name); 517 goto Done; 518 } 519 } 520 521 if (le32_to_cpu(tx_ring[tx_new].status) != 0x7FFFFFFF) { 522 printf("TX error status2 = 0x%08X\n", le32_to_cpu(tx_ring[tx_new].status)); 523 } 524 tx_new = (tx_new+1) % NUM_TX_DESC; 525 526 Done: 527 return; 528 } 529 530 #if defined(UPDATE_SROM) || !defined(CONFIG_TULIP_FIX_DAVICOM) 531 /* SROM Read and write routines. 532 */ 533 static void 534 sendto_srom(struct eth_device* dev, u_int command, u_long addr) 535 { 536 OUTL(dev, command, addr); 537 udelay(1); 538 } 539 540 static int 541 getfrom_srom(struct eth_device* dev, u_long addr) 542 { 543 s32 tmp; 544 545 tmp = INL(dev, addr); 546 udelay(1); 547 548 return tmp; 549 } 550 551 /* Note: this routine returns extra data bits for size detection. */ 552 static int do_read_eeprom(struct eth_device *dev, u_long ioaddr, int location, int addr_len) 553 { 554 int i; 555 unsigned retval = 0; 556 int read_cmd = location | (SROM_READ_CMD << addr_len); 557 558 sendto_srom(dev, SROM_RD | SROM_SR, ioaddr); 559 sendto_srom(dev, SROM_RD | SROM_SR | DT_CS, ioaddr); 560 561 #ifdef DEBUG_SROM 562 printf(" EEPROM read at %d ", location); 563 #endif 564 565 /* Shift the read command bits out. */ 566 for (i = 4 + addr_len; i >= 0; i--) { 567 short dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0; 568 sendto_srom(dev, SROM_RD | SROM_SR | DT_CS | dataval, ioaddr); 569 udelay(10); 570 sendto_srom(dev, SROM_RD | SROM_SR | DT_CS | dataval | DT_CLK, ioaddr); 571 udelay(10); 572 #ifdef DEBUG_SROM2 573 printf("%X", getfrom_srom(dev, ioaddr) & 15); 574 #endif 575 retval = (retval << 1) | ((getfrom_srom(dev, ioaddr) & EE_DATA_READ) ? 1 : 0); 576 } 577 578 sendto_srom(dev, SROM_RD | SROM_SR | DT_CS, ioaddr); 579 580 #ifdef DEBUG_SROM2 581 printf(" :%X:", getfrom_srom(dev, ioaddr) & 15); 582 #endif 583 584 for (i = 16; i > 0; i--) { 585 sendto_srom(dev, SROM_RD | SROM_SR | DT_CS | DT_CLK, ioaddr); 586 udelay(10); 587 #ifdef DEBUG_SROM2 588 printf("%X", getfrom_srom(dev, ioaddr) & 15); 589 #endif 590 retval = (retval << 1) | ((getfrom_srom(dev, ioaddr) & EE_DATA_READ) ? 1 : 0); 591 sendto_srom(dev, SROM_RD | SROM_SR | DT_CS, ioaddr); 592 udelay(10); 593 } 594 595 /* Terminate the EEPROM access. */ 596 sendto_srom(dev, SROM_RD | SROM_SR, ioaddr); 597 598 #ifdef DEBUG_SROM2 599 printf(" EEPROM value at %d is %5.5x.\n", location, retval); 600 #endif 601 602 return retval; 603 } 604 #endif /* UPDATE_SROM || !CONFIG_TULIP_FIX_DAVICOM */ 605 606 /* This executes a generic EEPROM command, typically a write or write 607 * enable. It returns the data output from the EEPROM, and thus may 608 * also be used for reads. 609 */ 610 #if defined(UPDATE_SROM) || !defined(CONFIG_TULIP_FIX_DAVICOM) 611 static int do_eeprom_cmd(struct eth_device *dev, u_long ioaddr, int cmd, int cmd_len) 612 { 613 unsigned retval = 0; 614 615 #ifdef DEBUG_SROM 616 printf(" EEPROM op 0x%x: ", cmd); 617 #endif 618 619 sendto_srom(dev,SROM_RD | SROM_SR | DT_CS | DT_CLK, ioaddr); 620 621 /* Shift the command bits out. */ 622 do { 623 short dataval = (cmd & (1 << cmd_len)) ? EE_WRITE_1 : EE_WRITE_0; 624 sendto_srom(dev,dataval, ioaddr); 625 udelay(10); 626 627 #ifdef DEBUG_SROM2 628 printf("%X", getfrom_srom(dev,ioaddr) & 15); 629 #endif 630 631 sendto_srom(dev,dataval | DT_CLK, ioaddr); 632 udelay(10); 633 retval = (retval << 1) | ((getfrom_srom(dev,ioaddr) & EE_DATA_READ) ? 1 : 0); 634 } while (--cmd_len >= 0); 635 sendto_srom(dev,SROM_RD | SROM_SR | DT_CS, ioaddr); 636 637 /* Terminate the EEPROM access. */ 638 sendto_srom(dev,SROM_RD | SROM_SR, ioaddr); 639 640 #ifdef DEBUG_SROM 641 printf(" EEPROM result is 0x%5.5x.\n", retval); 642 #endif 643 644 return retval; 645 } 646 #endif /* UPDATE_SROM || !CONFIG_TULIP_FIX_DAVICOM */ 647 648 #ifndef CONFIG_TULIP_FIX_DAVICOM 649 static int read_srom(struct eth_device *dev, u_long ioaddr, int index) 650 { 651 int ee_addr_size = do_read_eeprom(dev, ioaddr, 0xff, 8) & 0x40000 ? 8 : 6; 652 653 return do_eeprom_cmd(dev, ioaddr, 654 (((SROM_READ_CMD << ee_addr_size) | index) << 16) 655 | 0xffff, 3 + ee_addr_size + 16); 656 } 657 #endif /* CONFIG_TULIP_FIX_DAVICOM */ 658 659 #ifdef UPDATE_SROM 660 static int write_srom(struct eth_device *dev, u_long ioaddr, int index, int new_value) 661 { 662 int ee_addr_size = do_read_eeprom(dev, ioaddr, 0xff, 8) & 0x40000 ? 8 : 6; 663 int i; 664 unsigned short newval; 665 666 udelay(10*1000); /* test-only */ 667 668 #ifdef DEBUG_SROM 669 printf("ee_addr_size=%d.\n", ee_addr_size); 670 printf("Writing new entry 0x%4.4x to offset %d.\n", new_value, index); 671 #endif 672 673 /* Enable programming modes. */ 674 do_eeprom_cmd(dev, ioaddr, (0x4f << (ee_addr_size-4)), 3+ee_addr_size); 675 676 /* Do the actual write. */ 677 do_eeprom_cmd(dev, ioaddr, 678 (((SROM_WRITE_CMD<<ee_addr_size)|index) << 16) | new_value, 679 3 + ee_addr_size + 16); 680 681 /* Poll for write finished. */ 682 sendto_srom(dev, SROM_RD | SROM_SR | DT_CS, ioaddr); 683 for (i = 0; i < 10000; i++) /* Typical 2000 ticks */ 684 if (getfrom_srom(dev, ioaddr) & EE_DATA_READ) 685 break; 686 687 #ifdef DEBUG_SROM 688 printf(" Write finished after %d ticks.\n", i); 689 #endif 690 691 /* Disable programming. */ 692 do_eeprom_cmd(dev, ioaddr, (0x40 << (ee_addr_size-4)), 3 + ee_addr_size); 693 694 /* And read the result. */ 695 newval = do_eeprom_cmd(dev, ioaddr, 696 (((SROM_READ_CMD<<ee_addr_size)|index) << 16) 697 | 0xffff, 3 + ee_addr_size + 16); 698 #ifdef DEBUG_SROM 699 printf(" New value at offset %d is %4.4x.\n", index, newval); 700 #endif 701 return 1; 702 } 703 #endif 704 705 #ifndef CONFIG_TULIP_FIX_DAVICOM 706 static void read_hw_addr(struct eth_device *dev, bd_t *bis) 707 { 708 u_short tmp, *p = (u_short *)(&dev->enetaddr[0]); 709 int i, j = 0; 710 711 for (i = 0; i < (ETH_ALEN >> 1); i++) { 712 tmp = read_srom(dev, DE4X5_APROM, ((SROM_HWADD >> 1) + i)); 713 *p = le16_to_cpu(tmp); 714 j += *p++; 715 } 716 717 if ((j == 0) || (j == 0x2fffd)) { 718 memset (dev->enetaddr, 0, ETH_ALEN); 719 debug ("Warning: can't read HW address from SROM.\n"); 720 goto Done; 721 } 722 723 return; 724 725 Done: 726 #ifdef UPDATE_SROM 727 update_srom(dev, bis); 728 #endif 729 return; 730 } 731 #endif /* CONFIG_TULIP_FIX_DAVICOM */ 732 733 #ifdef UPDATE_SROM 734 static void update_srom(struct eth_device *dev, bd_t *bis) 735 { 736 int i; 737 static unsigned short eeprom[0x40] = { 738 0x140b, 0x6610, 0x0000, 0x0000, /* 00 */ 739 0x0000, 0x0000, 0x0000, 0x0000, /* 04 */ 740 0x00a3, 0x0103, 0x0000, 0x0000, /* 08 */ 741 0x0000, 0x1f00, 0x0000, 0x0000, /* 0c */ 742 0x0108, 0x038d, 0x0000, 0x0000, /* 10 */ 743 0xe078, 0x0001, 0x0040, 0x0018, /* 14 */ 744 0x0000, 0x0000, 0x0000, 0x0000, /* 18 */ 745 0x0000, 0x0000, 0x0000, 0x0000, /* 1c */ 746 0x0000, 0x0000, 0x0000, 0x0000, /* 20 */ 747 0x0000, 0x0000, 0x0000, 0x0000, /* 24 */ 748 0x0000, 0x0000, 0x0000, 0x0000, /* 28 */ 749 0x0000, 0x0000, 0x0000, 0x0000, /* 2c */ 750 0x0000, 0x0000, 0x0000, 0x0000, /* 30 */ 751 0x0000, 0x0000, 0x0000, 0x0000, /* 34 */ 752 0x0000, 0x0000, 0x0000, 0x0000, /* 38 */ 753 0x0000, 0x0000, 0x0000, 0x4e07, /* 3c */ 754 }; 755 uchar enetaddr[6]; 756 757 /* Ethernet Addr... */ 758 if (!eth_getenv_enetaddr("ethaddr", enetaddr)) 759 return; 760 eeprom[0x0a] = (enetaddr[1] << 8) | enetaddr[0]; 761 eeprom[0x0b] = (enetaddr[3] << 8) | enetaddr[2]; 762 eeprom[0x0c] = (enetaddr[5] << 8) | enetaddr[4]; 763 764 for (i=0; i<0x40; i++) { 765 write_srom(dev, DE4X5_APROM, i, eeprom[i]); 766 } 767 } 768 #endif /* UPDATE_SROM */ 769