1 #ifndef CS8900_H 2 #define CS8900_H 3 /* 4 * Cirrus Logic CS8900A Ethernet 5 * 6 * (C) 2009 Ben Warren , biggerbadderben@gmail.com 7 * Converted to use CONFIG_NET_MULTI API 8 * 9 * (C) Copyright 2002 10 * Sysgo Real-Time Solutions, GmbH <www.elinos.com> 11 * Marius Groeger <mgroeger@sysgo.de> 12 * 13 * Copyright (C) 1999 Ben Williamson <benw@pobox.com> 14 * 15 * See file CREDITS for list of people who contributed to this 16 * project. 17 * 18 * This program is loaded into SRAM in bootstrap mode, where it waits 19 * for commands on UART1 to read and write memory, jump to code etc. 20 * A design goal for this program is to be entirely independent of the 21 * target board. Anything with a CL-PS7111 or EP7211 should be able to run 22 * this code in bootstrap mode. All the board specifics can be handled on 23 * the host. 24 * 25 * This program is free software; you can redistribute it and/or modify 26 * it under the terms of the GNU General Public License as published by 27 * the Free Software Foundation; either version 2 of the License, or 28 * (at your option) any later version. 29 * 30 * This program is distributed in the hope that it will be useful, 31 * but WITHOUT ANY WARRANTY; without even the implied warranty of 32 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 33 * GNU General Public License for more details. 34 * 35 * You should have received a copy of the GNU General Public License 36 * along with this program; if not, write to the Free Software 37 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 38 */ 39 40 #include <asm/types.h> 41 #include <config.h> 42 43 #define CS8900_DRIVERNAME "CS8900" 44 /* although the registers are 16 bit, they are 32-bit aligned on the 45 EDB7111. so we have to read them as 32-bit registers and ignore the 46 upper 16-bits. i'm not sure if this holds for the EDB7211. */ 47 48 #ifdef CONFIG_CS8900_BUS16 49 /* 16 bit aligned registers, 16 bit wide */ 50 #define CS8900_REG u16 51 #elif defined(CONFIG_CS8900_BUS32) 52 /* 32 bit aligned registers, 16 bit wide (we ignore upper 16 bits) */ 53 #define CS8900_REG u32 54 #else 55 #error unknown bussize ... 56 #endif 57 58 struct cs8900_regs { 59 CS8900_REG rtdata; 60 CS8900_REG pad0; 61 CS8900_REG txcmd; 62 CS8900_REG txlen; 63 CS8900_REG isq; 64 CS8900_REG pptr; 65 CS8900_REG pdata; 66 }; 67 68 struct cs8900_priv { 69 struct cs8900_regs *regs; 70 }; 71 72 #define ISQ_RxEvent 0x04 73 #define ISQ_TxEvent 0x08 74 #define ISQ_BufEvent 0x0C 75 #define ISQ_RxMissEvent 0x10 76 #define ISQ_TxColEvent 0x12 77 #define ISQ_EventMask 0x3F 78 79 /* packet page register offsets */ 80 81 /* bus interface registers */ 82 #define PP_ChipID 0x0000 /* Chip identifier - must be 0x630E */ 83 #define PP_ChipRev 0x0002 /* Chip revision, model codes */ 84 85 #define PP_IntReg 0x0022 /* Interrupt configuration */ 86 #define PP_IntReg_IRQ0 0x0000 /* Use INTR0 pin */ 87 #define PP_IntReg_IRQ1 0x0001 /* Use INTR1 pin */ 88 #define PP_IntReg_IRQ2 0x0002 /* Use INTR2 pin */ 89 #define PP_IntReg_IRQ3 0x0003 /* Use INTR3 pin */ 90 91 /* status and control registers */ 92 93 #define PP_RxCFG 0x0102 /* Receiver configuration */ 94 #define PP_RxCFG_Skip1 0x0040 /* Skip (i.e. discard) current frame */ 95 #define PP_RxCFG_Stream 0x0080 /* Enable streaming mode */ 96 #define PP_RxCFG_RxOK 0x0100 /* RxOK interrupt enable */ 97 #define PP_RxCFG_RxDMAonly 0x0200 /* Use RxDMA for all frames */ 98 #define PP_RxCFG_AutoRxDMA 0x0400 /* Select RxDMA automatically */ 99 #define PP_RxCFG_BufferCRC 0x0800 /* Include CRC characters in frame */ 100 #define PP_RxCFG_CRC 0x1000 /* Enable interrupt on CRC error */ 101 #define PP_RxCFG_RUNT 0x2000 /* Enable interrupt on RUNT frames */ 102 #define PP_RxCFG_EXTRA 0x4000 /* Enable interrupt on frames with extra data */ 103 104 #define PP_RxCTL 0x0104 /* Receiver control */ 105 #define PP_RxCTL_IAHash 0x0040 /* Accept frames that match hash */ 106 #define PP_RxCTL_Promiscuous 0x0080 /* Accept any frame */ 107 #define PP_RxCTL_RxOK 0x0100 /* Accept well formed frames */ 108 #define PP_RxCTL_Multicast 0x0200 /* Accept multicast frames */ 109 #define PP_RxCTL_IA 0x0400 /* Accept frame that matches IA */ 110 #define PP_RxCTL_Broadcast 0x0800 /* Accept broadcast frames */ 111 #define PP_RxCTL_CRC 0x1000 /* Accept frames with bad CRC */ 112 #define PP_RxCTL_RUNT 0x2000 /* Accept runt frames */ 113 #define PP_RxCTL_EXTRA 0x4000 /* Accept frames that are too long */ 114 115 #define PP_TxCFG 0x0106 /* Transmit configuration */ 116 #define PP_TxCFG_CRS 0x0040 /* Enable interrupt on loss of carrier */ 117 #define PP_TxCFG_SQE 0x0080 /* Enable interrupt on Signal Quality Error */ 118 #define PP_TxCFG_TxOK 0x0100 /* Enable interrupt on successful xmits */ 119 #define PP_TxCFG_Late 0x0200 /* Enable interrupt on "out of window" */ 120 #define PP_TxCFG_Jabber 0x0400 /* Enable interrupt on jabber detect */ 121 #define PP_TxCFG_Collision 0x0800 /* Enable interrupt if collision */ 122 #define PP_TxCFG_16Collisions 0x8000 /* Enable interrupt if > 16 collisions */ 123 124 #define PP_TxCmd 0x0108 /* Transmit command status */ 125 #define PP_TxCmd_TxStart_5 0x0000 /* Start after 5 bytes in buffer */ 126 #define PP_TxCmd_TxStart_381 0x0040 /* Start after 381 bytes in buffer */ 127 #define PP_TxCmd_TxStart_1021 0x0080 /* Start after 1021 bytes in buffer */ 128 #define PP_TxCmd_TxStart_Full 0x00C0 /* Start after all bytes loaded */ 129 #define PP_TxCmd_Force 0x0100 /* Discard any pending packets */ 130 #define PP_TxCmd_OneCollision 0x0200 /* Abort after a single collision */ 131 #define PP_TxCmd_NoCRC 0x1000 /* Do not add CRC */ 132 #define PP_TxCmd_NoPad 0x2000 /* Do not pad short packets */ 133 134 #define PP_BufCFG 0x010A /* Buffer configuration */ 135 #define PP_BufCFG_SWI 0x0040 /* Force interrupt via software */ 136 #define PP_BufCFG_RxDMA 0x0080 /* Enable interrupt on Rx DMA */ 137 #define PP_BufCFG_TxRDY 0x0100 /* Enable interrupt when ready for Tx */ 138 #define PP_BufCFG_TxUE 0x0200 /* Enable interrupt in Tx underrun */ 139 #define PP_BufCFG_RxMiss 0x0400 /* Enable interrupt on missed Rx packets */ 140 #define PP_BufCFG_Rx128 0x0800 /* Enable Rx interrupt after 128 bytes */ 141 #define PP_BufCFG_TxCol 0x1000 /* Enable int on Tx collision ctr overflow */ 142 #define PP_BufCFG_Miss 0x2000 /* Enable int on Rx miss ctr overflow */ 143 #define PP_BufCFG_RxDest 0x8000 /* Enable int on Rx dest addr match */ 144 145 #define PP_LineCTL 0x0112 /* Line control */ 146 #define PP_LineCTL_Rx 0x0040 /* Enable receiver */ 147 #define PP_LineCTL_Tx 0x0080 /* Enable transmitter */ 148 #define PP_LineCTL_AUIonly 0x0100 /* AUI interface only */ 149 #define PP_LineCTL_AutoAUI10BT 0x0200 /* Autodetect AUI or 10BaseT interface */ 150 #define PP_LineCTL_ModBackoffE 0x0800 /* Enable modified backoff algorithm */ 151 #define PP_LineCTL_PolarityDis 0x1000 /* Disable Rx polarity autodetect */ 152 #define PP_LineCTL_2partDefDis 0x2000 /* Disable two-part defferal */ 153 #define PP_LineCTL_LoRxSquelch 0x4000 /* Reduce receiver squelch threshold */ 154 155 #define PP_SelfCTL 0x0114 /* Chip self control */ 156 #define PP_SelfCTL_Reset 0x0040 /* Self-clearing reset */ 157 #define PP_SelfCTL_SWSuspend 0x0100 /* Initiate suspend mode */ 158 #define PP_SelfCTL_HWSleepE 0x0200 /* Enable SLEEP input */ 159 #define PP_SelfCTL_HWStandbyE 0x0400 /* Enable standby mode */ 160 #define PP_SelfCTL_HC0E 0x1000 /* use HCB0 for LINK LED */ 161 #define PP_SelfCTL_HC1E 0x2000 /* use HCB1 for BSTATUS LED */ 162 #define PP_SelfCTL_HCB0 0x4000 /* control LINK LED if HC0E set */ 163 #define PP_SelfCTL_HCB1 0x8000 /* control BSTATUS LED if HC1E set */ 164 165 #define PP_BusCTL 0x0116 /* Bus control */ 166 #define PP_BusCTL_ResetRxDMA 0x0040 /* Reset RxDMA pointer */ 167 #define PP_BusCTL_DMAextend 0x0100 /* Extend DMA cycle */ 168 #define PP_BusCTL_UseSA 0x0200 /* Assert MEMCS16 on address decode */ 169 #define PP_BusCTL_MemoryE 0x0400 /* Enable memory mode */ 170 #define PP_BusCTL_DMAburst 0x0800 /* Limit DMA access burst */ 171 #define PP_BusCTL_IOCHRDYE 0x1000 /* Set IOCHRDY high impedence */ 172 #define PP_BusCTL_RxDMAsize 0x2000 /* Set DMA buffer size 64KB */ 173 #define PP_BusCTL_EnableIRQ 0x8000 /* Generate interrupt on interrupt event */ 174 175 #define PP_TestCTL 0x0118 /* Test control */ 176 #define PP_TestCTL_DisableLT 0x0080 /* Disable link status */ 177 #define PP_TestCTL_ENDECloop 0x0200 /* Internal loopback */ 178 #define PP_TestCTL_AUIloop 0x0400 /* AUI loopback */ 179 #define PP_TestCTL_DisBackoff 0x0800 /* Disable backoff algorithm */ 180 #define PP_TestCTL_FDX 0x4000 /* Enable full duplex mode */ 181 182 #define PP_ISQ 0x0120 /* Interrupt Status Queue */ 183 184 #define PP_RER 0x0124 /* Receive event */ 185 #define PP_RER_IAHash 0x0040 /* Frame hash match */ 186 #define PP_RER_Dribble 0x0080 /* Frame had 1-7 extra bits after last byte */ 187 #define PP_RER_RxOK 0x0100 /* Frame received with no errors */ 188 #define PP_RER_Hashed 0x0200 /* Frame address hashed OK */ 189 #define PP_RER_IA 0x0400 /* Frame address matched IA */ 190 #define PP_RER_Broadcast 0x0800 /* Broadcast frame */ 191 #define PP_RER_CRC 0x1000 /* Frame had CRC error */ 192 #define PP_RER_RUNT 0x2000 /* Runt frame */ 193 #define PP_RER_EXTRA 0x4000 /* Frame was too long */ 194 195 #define PP_TER 0x0128 /* Transmit event */ 196 #define PP_TER_CRS 0x0040 /* Carrier lost */ 197 #define PP_TER_SQE 0x0080 /* Signal Quality Error */ 198 #define PP_TER_TxOK 0x0100 /* Packet sent without error */ 199 #define PP_TER_Late 0x0200 /* Out of window */ 200 #define PP_TER_Jabber 0x0400 /* Stuck transmit? */ 201 #define PP_TER_NumCollisions 0x7800 /* Number of collisions */ 202 #define PP_TER_16Collisions 0x8000 /* > 16 collisions */ 203 204 #define PP_BER 0x012C /* Buffer event */ 205 #define PP_BER_SWint 0x0040 /* Software interrupt */ 206 #define PP_BER_RxDMAFrame 0x0080 /* Received framed DMAed */ 207 #define PP_BER_Rdy4Tx 0x0100 /* Ready for transmission */ 208 #define PP_BER_TxUnderrun 0x0200 /* Transmit underrun */ 209 #define PP_BER_RxMiss 0x0400 /* Received frame missed */ 210 #define PP_BER_Rx128 0x0800 /* 128 bytes received */ 211 #define PP_BER_RxDest 0x8000 /* Received framed passed address filter */ 212 213 #define PP_RxMiss 0x0130 /* Receiver miss counter */ 214 215 #define PP_TxCol 0x0132 /* Transmit collision counter */ 216 217 #define PP_LineSTAT 0x0134 /* Line status */ 218 #define PP_LineSTAT_LinkOK 0x0080 /* Line is connected and working */ 219 #define PP_LineSTAT_AUI 0x0100 /* Connected via AUI */ 220 #define PP_LineSTAT_10BT 0x0200 /* Connected via twisted pair */ 221 #define PP_LineSTAT_Polarity 0x1000 /* Line polarity OK (10BT only) */ 222 #define PP_LineSTAT_CRS 0x4000 /* Frame being received */ 223 224 #define PP_SelfSTAT 0x0136 /* Chip self status */ 225 #define PP_SelfSTAT_33VActive 0x0040 /* supply voltage is 3.3V */ 226 #define PP_SelfSTAT_InitD 0x0080 /* Chip initialization complete */ 227 #define PP_SelfSTAT_SIBSY 0x0100 /* EEPROM is busy */ 228 #define PP_SelfSTAT_EEPROM 0x0200 /* EEPROM present */ 229 #define PP_SelfSTAT_EEPROM_OK 0x0400 /* EEPROM checks out */ 230 #define PP_SelfSTAT_ELPresent 0x0800 /* External address latch logic available */ 231 #define PP_SelfSTAT_EEsize 0x1000 /* Size of EEPROM */ 232 233 #define PP_BusSTAT 0x0138 /* Bus status */ 234 #define PP_BusSTAT_TxBid 0x0080 /* Tx error */ 235 #define PP_BusSTAT_TxRDY 0x0100 /* Ready for Tx data */ 236 237 #define PP_TDR 0x013C /* AUI Time Domain Reflectometer */ 238 239 /* initiate transmit registers */ 240 241 #define PP_TxCommand 0x0144 /* Tx Command */ 242 #define PP_TxLength 0x0146 /* Tx Length */ 243 244 245 /* address filter registers */ 246 247 #define PP_LAF 0x0150 /* Logical address filter (6 bytes) */ 248 #define PP_IA 0x0158 /* Individual address (MAC) */ 249 250 /* EEPROM Kram */ 251 #define SI_BUSY 0x0100 252 #define PP_EECMD 0x0040 /* NVR Interface Command register */ 253 #define PP_EEData 0x0042 /* NVR Interface Data Register */ 254 #define EEPROM_WRITE_EN 0x00F0 255 #define EEPROM_WRITE_DIS 0x0000 256 #define EEPROM_WRITE_CMD 0x0100 257 #define EEPROM_READ_CMD 0x0200 258 #define EEPROM_ERASE_CMD 0x0300 259 260 /* Exported functions */ 261 int cs8900_e2prom_read(struct eth_device *dev, uchar, ushort *); 262 int cs8900_e2prom_write(struct eth_device *dev, uchar, ushort); 263 264 #endif /* CS8900_H */ 265