xref: /openbmc/u-boot/drivers/net/cs8900.c (revision 53193a4f)
1 /*
2  * Cirrus Logic CS8900A Ethernet
3  *
4  * (C) 2009 Ben Warren , biggerbadderben@gmail.com
5  *     Converted to use CONFIG_NET_MULTI API
6  *
7  * (C) 2003 Wolfgang Denk, wd@denx.de
8  *     Extension to synchronize ethaddr environment variable
9  *     against value in EEPROM
10  *
11  * (C) Copyright 2002
12  * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
13  * Marius Groeger <mgroeger@sysgo.de>
14  *
15  * Copyright (C) 1999 Ben Williamson <benw@pobox.com>
16  *
17  * This program is loaded into SRAM in bootstrap mode, where it waits
18  * for commands on UART1 to read and write memory, jump to code etc.
19  * A design goal for this program is to be entirely independent of the
20  * target board.  Anything with a CL-PS7111 or EP7211 should be able to run
21  * this code in bootstrap mode.  All the board specifics can be handled on
22  * the host.
23  *
24  * SPDX-License-Identifier:	GPL-2.0+
25  */
26 
27 #include <common.h>
28 #include <command.h>
29 #include <asm/io.h>
30 #include <net.h>
31 #include <malloc.h>
32 #include "cs8900.h"
33 
34 #undef DEBUG
35 
36 /* packet page register access functions */
37 
38 #ifdef CONFIG_CS8900_BUS32
39 
40 #define REG_WRITE(v, a) writel((v),(a))
41 #define REG_READ(a) readl((a))
42 
43 /* we don't need 16 bit initialisation on 32 bit bus */
44 #define get_reg_init_bus(r,d) get_reg((r),(d))
45 
46 #else
47 
48 #define REG_WRITE(v, a) writew((v),(a))
49 #define REG_READ(a) readw((a))
50 
51 static u16 get_reg_init_bus(struct eth_device *dev, int regno)
52 {
53 	/* force 16 bit busmode */
54 	struct cs8900_priv *priv = (struct cs8900_priv *)(dev->priv);
55 	uint8_t volatile * const iob = (uint8_t volatile * const)dev->iobase;
56 
57 	readb(iob);
58 	readb(iob + 1);
59 	readb(iob);
60 	readb(iob + 1);
61 	readb(iob);
62 
63 	REG_WRITE(regno, &priv->regs->pptr);
64 	return REG_READ(&priv->regs->pdata);
65 }
66 #endif
67 
68 static u16 get_reg(struct eth_device *dev, int regno)
69 {
70 	struct cs8900_priv *priv = (struct cs8900_priv *)(dev->priv);
71 	REG_WRITE(regno, &priv->regs->pptr);
72 	return REG_READ(&priv->regs->pdata);
73 }
74 
75 
76 static void put_reg(struct eth_device *dev, int regno, u16 val)
77 {
78 	struct cs8900_priv *priv = (struct cs8900_priv *)(dev->priv);
79 	REG_WRITE(regno, &priv->regs->pptr);
80 	REG_WRITE(val, &priv->regs->pdata);
81 }
82 
83 static void cs8900_reset(struct eth_device *dev)
84 {
85 	int tmo;
86 	u16 us;
87 
88 	/* reset NIC */
89 	put_reg(dev, PP_SelfCTL, get_reg(dev, PP_SelfCTL) | PP_SelfCTL_Reset);
90 
91 	/* wait for 200ms */
92 	udelay(200000);
93 	/* Wait until the chip is reset */
94 
95 	tmo = get_timer(0) + 1 * CONFIG_SYS_HZ;
96 	while ((((us = get_reg_init_bus(dev, PP_SelfSTAT)) &
97 		PP_SelfSTAT_InitD) == 0) && tmo < get_timer(0))
98 		/*NOP*/;
99 }
100 
101 static void cs8900_reginit(struct eth_device *dev)
102 {
103 	/* receive only error free packets addressed to this card */
104 	put_reg(dev, PP_RxCTL,
105 		PP_RxCTL_IA | PP_RxCTL_Broadcast | PP_RxCTL_RxOK);
106 	/* do not generate any interrupts on receive operations */
107 	put_reg(dev, PP_RxCFG, 0);
108 	/* do not generate any interrupts on transmit operations */
109 	put_reg(dev, PP_TxCFG, 0);
110 	/* do not generate any interrupts on buffer operations */
111 	put_reg(dev, PP_BufCFG, 0);
112 	/* enable transmitter/receiver mode */
113 	put_reg(dev, PP_LineCTL, PP_LineCTL_Rx | PP_LineCTL_Tx);
114 }
115 
116 void cs8900_get_enetaddr(struct eth_device *dev)
117 {
118 	int i;
119 
120 	/* verify chip id */
121 	if (get_reg_init_bus(dev, PP_ChipID) != 0x630e)
122 		return;
123 	cs8900_reset(dev);
124 	if ((get_reg(dev, PP_SelfSTAT) &
125 		(PP_SelfSTAT_EEPROM | PP_SelfSTAT_EEPROM_OK)) ==
126 		(PP_SelfSTAT_EEPROM | PP_SelfSTAT_EEPROM_OK)) {
127 
128 		/* Load the MAC from EEPROM */
129 		for (i = 0; i < 3; i++) {
130 			u32 Addr;
131 
132 			Addr = get_reg(dev, PP_IA + i * 2);
133 			dev->enetaddr[i * 2] = Addr & 0xFF;
134 			dev->enetaddr[i * 2 + 1] = Addr >> 8;
135 		}
136 	}
137 }
138 
139 void cs8900_halt(struct eth_device *dev)
140 {
141 	/* disable transmitter/receiver mode */
142 	put_reg(dev, PP_LineCTL, 0);
143 
144 	/* "shutdown" to show ChipID or kernel wouldn't find he cs8900 ... */
145 	get_reg_init_bus(dev, PP_ChipID);
146 }
147 
148 static int cs8900_init(struct eth_device *dev, bd_t * bd)
149 {
150 	uchar *enetaddr = dev->enetaddr;
151 	u16 id;
152 
153 	/* verify chip id */
154 	id = get_reg_init_bus(dev, PP_ChipID);
155 	if (id != 0x630e) {
156 		printf ("CS8900 Ethernet chip not found: "
157 			"ID=0x%04x instead 0x%04x\n", id, 0x630e);
158 		return 1;
159 	}
160 
161 	cs8900_reset (dev);
162 	/* set the ethernet address */
163 	put_reg(dev, PP_IA + 0, enetaddr[0] | (enetaddr[1] << 8));
164 	put_reg(dev, PP_IA + 2, enetaddr[2] | (enetaddr[3] << 8));
165 	put_reg(dev, PP_IA + 4, enetaddr[4] | (enetaddr[5] << 8));
166 
167 	cs8900_reginit(dev);
168 	return 0;
169 }
170 
171 /* Get a data block via Ethernet */
172 static int cs8900_recv(struct eth_device *dev)
173 {
174 	int i;
175 	u16 rxlen;
176 	u16 *addr;
177 	u16 status;
178 
179 	struct cs8900_priv *priv = (struct cs8900_priv *)(dev->priv);
180 
181 	status = get_reg(dev, PP_RER);
182 
183 	if ((status & PP_RER_RxOK) == 0)
184 		return 0;
185 
186 	status = REG_READ(&priv->regs->rtdata);
187 	rxlen = REG_READ(&priv->regs->rtdata);
188 
189 	if (rxlen > PKTSIZE_ALIGN + PKTALIGN)
190 		debug("packet too big!\n");
191 	for (addr = (u16 *)net_rx_packets[0], i = rxlen >> 1; i > 0; i--)
192 		*addr++ = REG_READ(&priv->regs->rtdata);
193 	if (rxlen & 1)
194 		*addr++ = REG_READ(&priv->regs->rtdata);
195 
196 	/* Pass the packet up to the protocol layers. */
197 	net_process_received_packet(net_rx_packets[0], rxlen);
198 	return rxlen;
199 }
200 
201 /* Send a data block via Ethernet. */
202 static int cs8900_send(struct eth_device *dev, void *packet, int length)
203 {
204 	volatile u16 *addr;
205 	int tmo;
206 	u16 s;
207 	struct cs8900_priv *priv = (struct cs8900_priv *)(dev->priv);
208 
209 retry:
210 	/* initiate a transmit sequence */
211 	REG_WRITE(PP_TxCmd_TxStart_Full, &priv->regs->txcmd);
212 	REG_WRITE(length, &priv->regs->txlen);
213 
214 	/* Test to see if the chip has allocated memory for the packet */
215 	if ((get_reg(dev, PP_BusSTAT) & PP_BusSTAT_TxRDY) == 0) {
216 		/* Oops... this should not happen! */
217 		debug("cs: unable to send packet; retrying...\n");
218 		for (tmo = get_timer(0) + 5 * CONFIG_SYS_HZ;
219 			get_timer(0) < tmo;)
220 			/*NOP*/;
221 		cs8900_reset(dev);
222 		cs8900_reginit(dev);
223 		goto retry;
224 	}
225 
226 	/* Write the contents of the packet */
227 	/* assume even number of bytes */
228 	for (addr = packet; length > 0; length -= 2)
229 		REG_WRITE(*addr++, &priv->regs->rtdata);
230 
231 	/* wait for transfer to succeed */
232 	tmo = get_timer(0) + 5 * CONFIG_SYS_HZ;
233 	while ((s = get_reg(dev, PP_TER) & ~0x1F) == 0) {
234 		if (get_timer(0) >= tmo)
235 			break;
236 	}
237 
238 	/* nothing */ ;
239 	if((s & (PP_TER_CRS | PP_TER_TxOK)) != PP_TER_TxOK) {
240 		debug("\ntransmission error %#x\n", s);
241 	}
242 
243 	return 0;
244 }
245 
246 static void cs8900_e2prom_ready(struct eth_device *dev)
247 {
248 	while (get_reg(dev, PP_SelfSTAT) & SI_BUSY)
249 		;
250 }
251 
252 /***********************************************************/
253 /* read a 16-bit word out of the EEPROM                    */
254 /***********************************************************/
255 
256 int cs8900_e2prom_read(struct eth_device *dev,
257 			u8 addr, u16 *value)
258 {
259 	cs8900_e2prom_ready(dev);
260 	put_reg(dev, PP_EECMD, EEPROM_READ_CMD | addr);
261 	cs8900_e2prom_ready(dev);
262 	*value = get_reg(dev, PP_EEData);
263 
264 	return 0;
265 }
266 
267 
268 /***********************************************************/
269 /* write a 16-bit word into the EEPROM                     */
270 /***********************************************************/
271 
272 int cs8900_e2prom_write(struct eth_device *dev, u8 addr, u16 value)
273 {
274 	cs8900_e2prom_ready(dev);
275 	put_reg(dev, PP_EECMD, EEPROM_WRITE_EN);
276 	cs8900_e2prom_ready(dev);
277 	put_reg(dev, PP_EEData, value);
278 	put_reg(dev, PP_EECMD, EEPROM_WRITE_CMD | addr);
279 	cs8900_e2prom_ready(dev);
280 	put_reg(dev, PP_EECMD, EEPROM_WRITE_DIS);
281 	cs8900_e2prom_ready(dev);
282 
283 	return 0;
284 }
285 
286 int cs8900_initialize(u8 dev_num, int base_addr)
287 {
288 	struct eth_device *dev;
289 	struct cs8900_priv *priv;
290 
291 	dev = malloc(sizeof(*dev));
292 	if (!dev) {
293 		return 0;
294 	}
295 	memset(dev, 0, sizeof(*dev));
296 
297 	priv = malloc(sizeof(*priv));
298 	if (!priv) {
299 		free(dev);
300 		return 0;
301 	}
302 	memset(priv, 0, sizeof(*priv));
303 	priv->regs = (struct cs8900_regs *)base_addr;
304 
305 	dev->iobase = base_addr;
306 	dev->priv = priv;
307 	dev->init = cs8900_init;
308 	dev->halt = cs8900_halt;
309 	dev->send = cs8900_send;
310 	dev->recv = cs8900_recv;
311 
312 	/* Load MAC address from EEPROM */
313 	cs8900_get_enetaddr(dev);
314 
315 	sprintf(dev->name, "%s-%hu", CS8900_DRIVERNAME, dev_num);
316 
317 	eth_register(dev);
318 	return 0;
319 }
320