1 /* 2 * Cirrus Logic CS8900A Ethernet 3 * 4 * (C) 2009 Ben Warren , biggerbadderben@gmail.com 5 * Converted to use CONFIG_NET_MULTI API 6 * 7 * (C) 2003 Wolfgang Denk, wd@denx.de 8 * Extension to synchronize ethaddr environment variable 9 * against value in EEPROM 10 * 11 * (C) Copyright 2002 12 * Sysgo Real-Time Solutions, GmbH <www.elinos.com> 13 * Marius Groeger <mgroeger@sysgo.de> 14 * 15 * Copyright (C) 1999 Ben Williamson <benw@pobox.com> 16 * 17 * See file CREDITS for list of people who contributed to this 18 * project. 19 * 20 * This program is loaded into SRAM in bootstrap mode, where it waits 21 * for commands on UART1 to read and write memory, jump to code etc. 22 * A design goal for this program is to be entirely independent of the 23 * target board. Anything with a CL-PS7111 or EP7211 should be able to run 24 * this code in bootstrap mode. All the board specifics can be handled on 25 * the host. 26 * 27 * This program is free software; you can redistribute it and/or modify 28 * it under the terms of the GNU General Public License as published by 29 * the Free Software Foundation; either version 2 of the License, or 30 * (at your option) any later version. 31 * 32 * This program is distributed in the hope that it will be useful, 33 * but WITHOUT ANY WARRANTY; without even the implied warranty of 34 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 35 * GNU General Public License for more details. 36 * 37 * You should have received a copy of the GNU General Public License 38 * along with this program; if not, write to the Free Software 39 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 40 */ 41 42 #include <common.h> 43 #include <command.h> 44 #include <asm/io.h> 45 #include <net.h> 46 #include <malloc.h> 47 #include "cs8900.h" 48 49 #undef DEBUG 50 51 /* packet page register access functions */ 52 53 #ifdef CONFIG_CS8900_BUS32 54 55 #define REG_WRITE(v, a) writel((v),(a)) 56 #define REG_READ(a) readl((a)) 57 58 /* we don't need 16 bit initialisation on 32 bit bus */ 59 #define get_reg_init_bus(r,d) get_reg((r),(d)) 60 61 #else 62 63 #define REG_WRITE(v, a) writew((v),(a)) 64 #define REG_READ(a) readw((a)) 65 66 static u16 get_reg_init_bus(struct eth_device *dev, int regno) 67 { 68 /* force 16 bit busmode */ 69 struct cs8900_priv *priv = (struct cs8900_priv *)(dev->priv); 70 uint8_t volatile * const iob = (uint8_t volatile * const)dev->iobase; 71 72 readb(iob); 73 readb(iob + 1); 74 readb(iob); 75 readb(iob + 1); 76 readb(iob); 77 78 REG_WRITE(regno, &priv->regs->pptr); 79 return REG_READ(&priv->regs->pdata); 80 } 81 #endif 82 83 static u16 get_reg(struct eth_device *dev, int regno) 84 { 85 struct cs8900_priv *priv = (struct cs8900_priv *)(dev->priv); 86 REG_WRITE(regno, &priv->regs->pptr); 87 return REG_READ(&priv->regs->pdata); 88 } 89 90 91 static void put_reg(struct eth_device *dev, int regno, u16 val) 92 { 93 struct cs8900_priv *priv = (struct cs8900_priv *)(dev->priv); 94 REG_WRITE(regno, &priv->regs->pptr); 95 REG_WRITE(val, &priv->regs->pdata); 96 } 97 98 static void cs8900_reset(struct eth_device *dev) 99 { 100 int tmo; 101 u16 us; 102 103 /* reset NIC */ 104 put_reg(dev, PP_SelfCTL, get_reg(dev, PP_SelfCTL) | PP_SelfCTL_Reset); 105 106 /* wait for 200ms */ 107 udelay(200000); 108 /* Wait until the chip is reset */ 109 110 tmo = get_timer(0) + 1 * CONFIG_SYS_HZ; 111 while ((((us = get_reg_init_bus(dev, PP_SelfSTAT)) & 112 PP_SelfSTAT_InitD) == 0) && tmo < get_timer(0)) 113 /*NOP*/; 114 } 115 116 static void cs8900_reginit(struct eth_device *dev) 117 { 118 /* receive only error free packets addressed to this card */ 119 put_reg(dev, PP_RxCTL, 120 PP_RxCTL_IA | PP_RxCTL_Broadcast | PP_RxCTL_RxOK); 121 /* do not generate any interrupts on receive operations */ 122 put_reg(dev, PP_RxCFG, 0); 123 /* do not generate any interrupts on transmit operations */ 124 put_reg(dev, PP_TxCFG, 0); 125 /* do not generate any interrupts on buffer operations */ 126 put_reg(dev, PP_BufCFG, 0); 127 /* enable transmitter/receiver mode */ 128 put_reg(dev, PP_LineCTL, PP_LineCTL_Rx | PP_LineCTL_Tx); 129 } 130 131 void cs8900_get_enetaddr(struct eth_device *dev) 132 { 133 int i; 134 135 /* verify chip id */ 136 if (get_reg_init_bus(dev, PP_ChipID) != 0x630e) 137 return; 138 cs8900_reset(dev); 139 if ((get_reg(dev, PP_SelfSTAT) & 140 (PP_SelfSTAT_EEPROM | PP_SelfSTAT_EEPROM_OK)) == 141 (PP_SelfSTAT_EEPROM | PP_SelfSTAT_EEPROM_OK)) { 142 143 /* Load the MAC from EEPROM */ 144 for (i = 0; i < 3; i++) { 145 u32 Addr; 146 147 Addr = get_reg(dev, PP_IA + i * 2); 148 dev->enetaddr[i * 2] = Addr & 0xFF; 149 dev->enetaddr[i * 2 + 1] = Addr >> 8; 150 } 151 } 152 } 153 154 void cs8900_halt(struct eth_device *dev) 155 { 156 /* disable transmitter/receiver mode */ 157 put_reg(dev, PP_LineCTL, 0); 158 159 /* "shutdown" to show ChipID or kernel wouldn't find he cs8900 ... */ 160 get_reg_init_bus(dev, PP_ChipID); 161 } 162 163 static int cs8900_init(struct eth_device *dev, bd_t * bd) 164 { 165 uchar *enetaddr = dev->enetaddr; 166 u16 id; 167 168 /* verify chip id */ 169 id = get_reg_init_bus(dev, PP_ChipID); 170 if (id != 0x630e) { 171 printf ("CS8900 Ethernet chip not found: " 172 "ID=0x%04x instead 0x%04x\n", id, 0x630e); 173 return 1; 174 } 175 176 cs8900_reset (dev); 177 /* set the ethernet address */ 178 put_reg(dev, PP_IA + 0, enetaddr[0] | (enetaddr[1] << 8)); 179 put_reg(dev, PP_IA + 2, enetaddr[2] | (enetaddr[3] << 8)); 180 put_reg(dev, PP_IA + 4, enetaddr[4] | (enetaddr[5] << 8)); 181 182 cs8900_reginit(dev); 183 return 0; 184 } 185 186 /* Get a data block via Ethernet */ 187 static int cs8900_recv(struct eth_device *dev) 188 { 189 int i; 190 u16 rxlen; 191 u16 *addr; 192 u16 status; 193 194 struct cs8900_priv *priv = (struct cs8900_priv *)(dev->priv); 195 196 status = get_reg(dev, PP_RER); 197 198 if ((status & PP_RER_RxOK) == 0) 199 return 0; 200 201 status = REG_READ(&priv->regs->rtdata); 202 rxlen = REG_READ(&priv->regs->rtdata); 203 204 if (rxlen > PKTSIZE_ALIGN + PKTALIGN) 205 debug("packet too big!\n"); 206 for (addr = (u16 *) NetRxPackets[0], i = rxlen >> 1; i > 0; 207 i--) 208 *addr++ = REG_READ(&priv->regs->rtdata); 209 if (rxlen & 1) 210 *addr++ = REG_READ(&priv->regs->rtdata); 211 212 /* Pass the packet up to the protocol layers. */ 213 NetReceive (NetRxPackets[0], rxlen); 214 return rxlen; 215 } 216 217 /* Send a data block via Ethernet. */ 218 static int cs8900_send(struct eth_device *dev, 219 volatile void *packet, int length) 220 { 221 volatile u16 *addr; 222 int tmo; 223 u16 s; 224 struct cs8900_priv *priv = (struct cs8900_priv *)(dev->priv); 225 226 retry: 227 /* initiate a transmit sequence */ 228 REG_WRITE(PP_TxCmd_TxStart_Full, &priv->regs->txcmd); 229 REG_WRITE(length, &priv->regs->txlen); 230 231 /* Test to see if the chip has allocated memory for the packet */ 232 if ((get_reg(dev, PP_BusSTAT) & PP_BusSTAT_TxRDY) == 0) { 233 /* Oops... this should not happen! */ 234 debug("cs: unable to send packet; retrying...\n"); 235 for (tmo = get_timer(0) + 5 * CONFIG_SYS_HZ; 236 get_timer(0) < tmo;) 237 /*NOP*/; 238 cs8900_reset(dev); 239 cs8900_reginit(dev); 240 goto retry; 241 } 242 243 /* Write the contents of the packet */ 244 /* assume even number of bytes */ 245 for (addr = packet; length > 0; length -= 2) 246 REG_WRITE(*addr++, &priv->regs->rtdata); 247 248 /* wait for transfer to succeed */ 249 tmo = get_timer(0) + 5 * CONFIG_SYS_HZ; 250 while ((s = get_reg(dev, PP_TER) & ~0x1F) == 0) { 251 if (get_timer(0) >= tmo) 252 break; 253 } 254 255 /* nothing */ ; 256 if((s & (PP_TER_CRS | PP_TER_TxOK)) != PP_TER_TxOK) { 257 debug("\ntransmission error %#x\n", s); 258 } 259 260 return 0; 261 } 262 263 static void cs8900_e2prom_ready(struct eth_device *dev) 264 { 265 while (get_reg(dev, PP_SelfSTAT) & SI_BUSY) 266 ; 267 } 268 269 /***********************************************************/ 270 /* read a 16-bit word out of the EEPROM */ 271 /***********************************************************/ 272 273 int cs8900_e2prom_read(struct eth_device *dev, 274 u8 addr, u16 *value) 275 { 276 cs8900_e2prom_ready(dev); 277 put_reg(dev, PP_EECMD, EEPROM_READ_CMD | addr); 278 cs8900_e2prom_ready(dev); 279 *value = get_reg(dev, PP_EEData); 280 281 return 0; 282 } 283 284 285 /***********************************************************/ 286 /* write a 16-bit word into the EEPROM */ 287 /***********************************************************/ 288 289 int cs8900_e2prom_write(struct eth_device *dev, u8 addr, u16 value) 290 { 291 cs8900_e2prom_ready(dev); 292 put_reg(dev, PP_EECMD, EEPROM_WRITE_EN); 293 cs8900_e2prom_ready(dev); 294 put_reg(dev, PP_EEData, value); 295 put_reg(dev, PP_EECMD, EEPROM_WRITE_CMD | addr); 296 cs8900_e2prom_ready(dev); 297 put_reg(dev, PP_EECMD, EEPROM_WRITE_DIS); 298 cs8900_e2prom_ready(dev); 299 300 return 0; 301 } 302 303 int cs8900_initialize(u8 dev_num, int base_addr) 304 { 305 struct eth_device *dev; 306 struct cs8900_priv *priv; 307 308 dev = malloc(sizeof(*dev)); 309 if (!dev) { 310 return 0; 311 } 312 memset(dev, 0, sizeof(*dev)); 313 314 priv = malloc(sizeof(*priv)); 315 if (!priv) { 316 free(dev); 317 return 0; 318 } 319 memset(priv, 0, sizeof(*priv)); 320 priv->regs = (struct cs8900_regs *)base_addr; 321 322 dev->iobase = base_addr; 323 dev->priv = priv; 324 dev->init = cs8900_init; 325 dev->halt = cs8900_halt; 326 dev->send = cs8900_send; 327 dev->recv = cs8900_recv; 328 329 /* Load MAC address from EEPROM */ 330 cs8900_get_enetaddr(dev); 331 332 sprintf(dev->name, "%s-%hu", CS8900_DRIVERNAME, dev_num); 333 334 eth_register(dev); 335 return 0; 336 } 337