1 /* 2 * Copyright 2010-2011 Calxeda, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <malloc.h> 9 #include <linux/compiler.h> 10 #include <linux/err.h> 11 #include <asm/io.h> 12 13 #define TX_NUM_DESC 1 14 #define RX_NUM_DESC 32 15 16 #define MAC_TIMEOUT (5*CONFIG_SYS_HZ) 17 18 #define ETH_BUF_SZ 2048 19 #define TX_BUF_SZ (ETH_BUF_SZ * TX_NUM_DESC) 20 #define RX_BUF_SZ (ETH_BUF_SZ * RX_NUM_DESC) 21 22 #define RXSTART 0x00000002 23 #define TXSTART 0x00002000 24 25 #define RXENABLE 0x00000004 26 #define TXENABLE 0x00000008 27 28 #define XGMAC_CONTROL_SPD 0x40000000 29 #define XGMAC_CONTROL_SPD_MASK 0x60000000 30 #define XGMAC_CONTROL_SARC 0x10000000 31 #define XGMAC_CONTROL_SARK_MASK 0x18000000 32 #define XGMAC_CONTROL_CAR 0x04000000 33 #define XGMAC_CONTROL_CAR_MASK 0x06000000 34 #define XGMAC_CONTROL_CAR_SHIFT 25 35 #define XGMAC_CONTROL_DP 0x01000000 36 #define XGMAC_CONTROL_WD 0x00800000 37 #define XGMAC_CONTROL_JD 0x00400000 38 #define XGMAC_CONTROL_JE 0x00100000 39 #define XGMAC_CONTROL_LM 0x00001000 40 #define XGMAC_CONTROL_IPC 0x00000400 41 #define XGMAC_CONTROL_ACS 0x00000080 42 #define XGMAC_CONTROL_DDIC 0x00000010 43 #define XGMAC_CONTROL_TE 0x00000008 44 #define XGMAC_CONTROL_RE 0x00000004 45 46 #define XGMAC_DMA_BUSMODE_RESET 0x00000001 47 #define XGMAC_DMA_BUSMODE_DSL 0x00000004 48 #define XGMAC_DMA_BUSMODE_DSL_MASK 0x0000007c 49 #define XGMAC_DMA_BUSMODE_DSL_SHIFT 2 50 #define XGMAC_DMA_BUSMODE_ATDS 0x00000080 51 #define XGMAC_DMA_BUSMODE_PBL_MASK 0x00003f00 52 #define XGMAC_DMA_BUSMODE_PBL_SHIFT 8 53 #define XGMAC_DMA_BUSMODE_FB 0x00010000 54 #define XGMAC_DMA_BUSMODE_USP 0x00800000 55 #define XGMAC_DMA_BUSMODE_8PBL 0x01000000 56 #define XGMAC_DMA_BUSMODE_AAL 0x02000000 57 58 #define XGMAC_DMA_AXIMODE_ENLPI 0x80000000 59 #define XGMAC_DMA_AXIMODE_MGK 0x40000000 60 #define XGMAC_DMA_AXIMODE_WROSR 0x00100000 61 #define XGMAC_DMA_AXIMODE_WROSR_MASK 0x00F00000 62 #define XGMAC_DMA_AXIMODE_WROSR_SHIFT 20 63 #define XGMAC_DMA_AXIMODE_RDOSR 0x00010000 64 #define XGMAC_DMA_AXIMODE_RDOSR_MASK 0x000F0000 65 #define XGMAC_DMA_AXIMODE_RDOSR_SHIFT 16 66 #define XGMAC_DMA_AXIMODE_AAL 0x00001000 67 #define XGMAC_DMA_AXIMODE_BLEN256 0x00000080 68 #define XGMAC_DMA_AXIMODE_BLEN128 0x00000040 69 #define XGMAC_DMA_AXIMODE_BLEN64 0x00000020 70 #define XGMAC_DMA_AXIMODE_BLEN32 0x00000010 71 #define XGMAC_DMA_AXIMODE_BLEN16 0x00000008 72 #define XGMAC_DMA_AXIMODE_BLEN8 0x00000004 73 #define XGMAC_DMA_AXIMODE_BLEN4 0x00000002 74 #define XGMAC_DMA_AXIMODE_UNDEF 0x00000001 75 76 #define XGMAC_CORE_OMR_RTC_SHIFT 3 77 #define XGMAC_CORE_OMR_RTC_MASK 0x00000018 78 #define XGMAC_CORE_OMR_RTC 0x00000010 79 #define XGMAC_CORE_OMR_RSF 0x00000020 80 #define XGMAC_CORE_OMR_DT 0x00000040 81 #define XGMAC_CORE_OMR_FEF 0x00000080 82 #define XGMAC_CORE_OMR_EFC 0x00000100 83 #define XGMAC_CORE_OMR_RFA_SHIFT 9 84 #define XGMAC_CORE_OMR_RFA_MASK 0x00000E00 85 #define XGMAC_CORE_OMR_RFD_SHIFT 12 86 #define XGMAC_CORE_OMR_RFD_MASK 0x00007000 87 #define XGMAC_CORE_OMR_TTC_SHIFT 16 88 #define XGMAC_CORE_OMR_TTC_MASK 0x00030000 89 #define XGMAC_CORE_OMR_TTC 0x00020000 90 #define XGMAC_CORE_OMR_FTF 0x00100000 91 #define XGMAC_CORE_OMR_TSF 0x00200000 92 93 #define FIFO_MINUS_1K 0x0 94 #define FIFO_MINUS_2K 0x1 95 #define FIFO_MINUS_3K 0x2 96 #define FIFO_MINUS_4K 0x3 97 #define FIFO_MINUS_6K 0x4 98 #define FIFO_MINUS_8K 0x5 99 #define FIFO_MINUS_12K 0x6 100 #define FIFO_MINUS_16K 0x7 101 102 #define XGMAC_CORE_FLOW_PT_SHIFT 16 103 #define XGMAC_CORE_FLOW_PT_MASK 0xFFFF0000 104 #define XGMAC_CORE_FLOW_PT 0x00010000 105 #define XGMAC_CORE_FLOW_DZQP 0x00000080 106 #define XGMAC_CORE_FLOW_PLT_SHIFT 4 107 #define XGMAC_CORE_FLOW_PLT_MASK 0x00000030 108 #define XGMAC_CORE_FLOW_PLT 0x00000010 109 #define XGMAC_CORE_FLOW_UP 0x00000008 110 #define XGMAC_CORE_FLOW_RFE 0x00000004 111 #define XGMAC_CORE_FLOW_TFE 0x00000002 112 #define XGMAC_CORE_FLOW_FCB 0x00000001 113 114 /* XGMAC Descriptor Defines */ 115 #define MAX_DESC_BUF_SZ (0x2000 - 8) 116 117 #define RXDESC_EXT_STATUS 0x00000001 118 #define RXDESC_CRC_ERR 0x00000002 119 #define RXDESC_RX_ERR 0x00000008 120 #define RXDESC_RX_WDOG 0x00000010 121 #define RXDESC_FRAME_TYPE 0x00000020 122 #define RXDESC_GIANT_FRAME 0x00000080 123 #define RXDESC_LAST_SEG 0x00000100 124 #define RXDESC_FIRST_SEG 0x00000200 125 #define RXDESC_VLAN_FRAME 0x00000400 126 #define RXDESC_OVERFLOW_ERR 0x00000800 127 #define RXDESC_LENGTH_ERR 0x00001000 128 #define RXDESC_SA_FILTER_FAIL 0x00002000 129 #define RXDESC_DESCRIPTOR_ERR 0x00004000 130 #define RXDESC_ERROR_SUMMARY 0x00008000 131 #define RXDESC_FRAME_LEN_OFFSET 16 132 #define RXDESC_FRAME_LEN_MASK 0x3fff0000 133 #define RXDESC_DA_FILTER_FAIL 0x40000000 134 135 #define RXDESC1_END_RING 0x00008000 136 137 #define RXDESC_IP_PAYLOAD_MASK 0x00000003 138 #define RXDESC_IP_PAYLOAD_UDP 0x00000001 139 #define RXDESC_IP_PAYLOAD_TCP 0x00000002 140 #define RXDESC_IP_PAYLOAD_ICMP 0x00000003 141 #define RXDESC_IP_HEADER_ERR 0x00000008 142 #define RXDESC_IP_PAYLOAD_ERR 0x00000010 143 #define RXDESC_IPV4_PACKET 0x00000040 144 #define RXDESC_IPV6_PACKET 0x00000080 145 #define TXDESC_UNDERFLOW_ERR 0x00000001 146 #define TXDESC_JABBER_TIMEOUT 0x00000002 147 #define TXDESC_LOCAL_FAULT 0x00000004 148 #define TXDESC_REMOTE_FAULT 0x00000008 149 #define TXDESC_VLAN_FRAME 0x00000010 150 #define TXDESC_FRAME_FLUSHED 0x00000020 151 #define TXDESC_IP_HEADER_ERR 0x00000040 152 #define TXDESC_PAYLOAD_CSUM_ERR 0x00000080 153 #define TXDESC_ERROR_SUMMARY 0x00008000 154 #define TXDESC_SA_CTRL_INSERT 0x00040000 155 #define TXDESC_SA_CTRL_REPLACE 0x00080000 156 #define TXDESC_2ND_ADDR_CHAINED 0x00100000 157 #define TXDESC_END_RING 0x00200000 158 #define TXDESC_CSUM_IP 0x00400000 159 #define TXDESC_CSUM_IP_PAYLD 0x00800000 160 #define TXDESC_CSUM_ALL 0x00C00000 161 #define TXDESC_CRC_EN_REPLACE 0x01000000 162 #define TXDESC_CRC_EN_APPEND 0x02000000 163 #define TXDESC_DISABLE_PAD 0x04000000 164 #define TXDESC_FIRST_SEG 0x10000000 165 #define TXDESC_LAST_SEG 0x20000000 166 #define TXDESC_INTERRUPT 0x40000000 167 168 #define DESC_OWN 0x80000000 169 #define DESC_BUFFER1_SZ_MASK 0x00001fff 170 #define DESC_BUFFER2_SZ_MASK 0x1fff0000 171 #define DESC_BUFFER2_SZ_OFFSET 16 172 173 struct xgmac_regs { 174 u32 config; 175 u32 framefilter; 176 u32 resv_1[4]; 177 u32 flow_control; 178 u32 vlantag; 179 u32 version; 180 u32 vlaninclude; 181 u32 resv_2[2]; 182 u32 pacestretch; 183 u32 vlanhash; 184 u32 resv_3; 185 u32 intreg; 186 struct { 187 u32 hi; /* 0x40 */ 188 u32 lo; /* 0x44 */ 189 } macaddr[16]; 190 u32 resv_4[0xd0]; 191 u32 core_opmode; /* 0x400 */ 192 u32 resv_5[0x2bf]; 193 u32 busmode; /* 0xf00 */ 194 u32 txpoll; 195 u32 rxpoll; 196 u32 rxdesclist; 197 u32 txdesclist; 198 u32 dma_status; 199 u32 dma_opmode; 200 u32 intenable; 201 u32 resv_6[2]; 202 u32 axi_mode; /* 0xf28 */ 203 }; 204 205 struct xgmac_dma_desc { 206 __le32 flags; 207 __le32 buf_size; 208 __le32 buf1_addr; /* Buffer 1 Address Pointer */ 209 __le32 buf2_addr; /* Buffer 2 Address Pointer */ 210 __le32 ext_status; 211 __le32 res[3]; 212 }; 213 214 /* XGMAC Descriptor Access Helpers */ 215 static inline void desc_set_buf_len(struct xgmac_dma_desc *p, u32 buf_sz) 216 { 217 if (buf_sz > MAX_DESC_BUF_SZ) 218 p->buf_size = cpu_to_le32(MAX_DESC_BUF_SZ | 219 (buf_sz - MAX_DESC_BUF_SZ) << DESC_BUFFER2_SZ_OFFSET); 220 else 221 p->buf_size = cpu_to_le32(buf_sz); 222 } 223 224 static inline int desc_get_buf_len(struct xgmac_dma_desc *p) 225 { 226 u32 len = le32_to_cpu(p->buf_size); 227 return (len & DESC_BUFFER1_SZ_MASK) + 228 ((len & DESC_BUFFER2_SZ_MASK) >> DESC_BUFFER2_SZ_OFFSET); 229 } 230 231 static inline void desc_init_rx_desc(struct xgmac_dma_desc *p, int ring_size, 232 int buf_sz) 233 { 234 struct xgmac_dma_desc *end = p + ring_size - 1; 235 236 memset(p, 0, sizeof(*p) * ring_size); 237 238 for (; p <= end; p++) 239 desc_set_buf_len(p, buf_sz); 240 241 end->buf_size |= cpu_to_le32(RXDESC1_END_RING); 242 } 243 244 static inline void desc_init_tx_desc(struct xgmac_dma_desc *p, u32 ring_size) 245 { 246 memset(p, 0, sizeof(*p) * ring_size); 247 p[ring_size - 1].flags = cpu_to_le32(TXDESC_END_RING); 248 } 249 250 static inline int desc_get_owner(struct xgmac_dma_desc *p) 251 { 252 return le32_to_cpu(p->flags) & DESC_OWN; 253 } 254 255 static inline void desc_set_rx_owner(struct xgmac_dma_desc *p) 256 { 257 /* Clear all fields and set the owner */ 258 p->flags = cpu_to_le32(DESC_OWN); 259 } 260 261 static inline void desc_set_tx_owner(struct xgmac_dma_desc *p, u32 flags) 262 { 263 u32 tmpflags = le32_to_cpu(p->flags); 264 tmpflags &= TXDESC_END_RING; 265 tmpflags |= flags | DESC_OWN; 266 p->flags = cpu_to_le32(tmpflags); 267 } 268 269 static inline void *desc_get_buf_addr(struct xgmac_dma_desc *p) 270 { 271 return (void *)le32_to_cpu(p->buf1_addr); 272 } 273 274 static inline void desc_set_buf_addr(struct xgmac_dma_desc *p, 275 void *paddr, int len) 276 { 277 p->buf1_addr = cpu_to_le32(paddr); 278 if (len > MAX_DESC_BUF_SZ) 279 p->buf2_addr = cpu_to_le32(paddr + MAX_DESC_BUF_SZ); 280 } 281 282 static inline void desc_set_buf_addr_and_size(struct xgmac_dma_desc *p, 283 void *paddr, int len) 284 { 285 desc_set_buf_len(p, len); 286 desc_set_buf_addr(p, paddr, len); 287 } 288 289 static inline int desc_get_rx_frame_len(struct xgmac_dma_desc *p) 290 { 291 u32 data = le32_to_cpu(p->flags); 292 u32 len = (data & RXDESC_FRAME_LEN_MASK) >> RXDESC_FRAME_LEN_OFFSET; 293 if (data & RXDESC_FRAME_TYPE) 294 len -= 4; 295 296 return len; 297 } 298 299 struct calxeda_eth_dev { 300 struct xgmac_dma_desc rx_chain[RX_NUM_DESC]; 301 struct xgmac_dma_desc tx_chain[TX_NUM_DESC]; 302 char rxbuffer[RX_BUF_SZ]; 303 304 u32 tx_currdesc; 305 u32 rx_currdesc; 306 307 struct eth_device *dev; 308 } __aligned(32); 309 310 /* 311 * Initialize a descriptor ring. Calxeda XGMAC is configured to use 312 * advanced descriptors. 313 */ 314 315 static void init_rx_desc(struct calxeda_eth_dev *priv) 316 { 317 struct xgmac_dma_desc *rxdesc = priv->rx_chain; 318 struct xgmac_regs *regs = (struct xgmac_regs *)priv->dev->iobase; 319 void *rxbuffer = priv->rxbuffer; 320 int i; 321 322 desc_init_rx_desc(rxdesc, RX_NUM_DESC, ETH_BUF_SZ); 323 writel((ulong)rxdesc, ®s->rxdesclist); 324 325 for (i = 0; i < RX_NUM_DESC; i++) { 326 desc_set_buf_addr(rxdesc + i, rxbuffer + (i * ETH_BUF_SZ), 327 ETH_BUF_SZ); 328 desc_set_rx_owner(rxdesc + i); 329 } 330 } 331 332 static void init_tx_desc(struct calxeda_eth_dev *priv) 333 { 334 struct xgmac_regs *regs = (struct xgmac_regs *)priv->dev->iobase; 335 336 desc_init_tx_desc(priv->tx_chain, TX_NUM_DESC); 337 writel((ulong)priv->tx_chain, ®s->txdesclist); 338 } 339 340 static int xgmac_reset(struct eth_device *dev) 341 { 342 struct xgmac_regs *regs = (struct xgmac_regs *)dev->iobase; 343 int timeout = MAC_TIMEOUT; 344 u32 value; 345 346 value = readl(®s->config) & XGMAC_CONTROL_SPD_MASK; 347 348 writel(XGMAC_DMA_BUSMODE_RESET, ®s->busmode); 349 while ((timeout-- >= 0) && 350 (readl(®s->busmode) & XGMAC_DMA_BUSMODE_RESET)) 351 udelay(1); 352 353 writel(value, ®s->config); 354 355 return timeout; 356 } 357 358 static void xgmac_hwmacaddr(struct eth_device *dev) 359 { 360 struct xgmac_regs *regs = (struct xgmac_regs *)dev->iobase; 361 u32 macaddr[2]; 362 363 memcpy(macaddr, dev->enetaddr, 6); 364 writel(macaddr[1], ®s->macaddr[0].hi); 365 writel(macaddr[0], ®s->macaddr[0].lo); 366 } 367 368 static int xgmac_init(struct eth_device *dev, bd_t * bis) 369 { 370 struct xgmac_regs *regs = (struct xgmac_regs *)dev->iobase; 371 struct calxeda_eth_dev *priv = dev->priv; 372 int value; 373 374 if (xgmac_reset(dev) < 0) 375 return -1; 376 377 /* set the hardware MAC address */ 378 xgmac_hwmacaddr(dev); 379 380 /* set the AXI bus modes */ 381 value = XGMAC_DMA_BUSMODE_ATDS | 382 (16 << XGMAC_DMA_BUSMODE_PBL_SHIFT) | 383 XGMAC_DMA_BUSMODE_FB | XGMAC_DMA_BUSMODE_AAL; 384 writel(value, ®s->busmode); 385 386 value = XGMAC_DMA_AXIMODE_AAL | XGMAC_DMA_AXIMODE_BLEN16 | 387 XGMAC_DMA_AXIMODE_BLEN8 | XGMAC_DMA_AXIMODE_BLEN4; 388 writel(value, ®s->axi_mode); 389 390 /* set flow control parameters and store and forward mode */ 391 value = (FIFO_MINUS_12K << XGMAC_CORE_OMR_RFD_SHIFT) | 392 (FIFO_MINUS_4K << XGMAC_CORE_OMR_RFA_SHIFT) | 393 XGMAC_CORE_OMR_EFC | XGMAC_CORE_OMR_TSF; 394 writel(value, ®s->core_opmode); 395 396 /* enable pause frames */ 397 value = (1024 << XGMAC_CORE_FLOW_PT_SHIFT) | 398 (1 << XGMAC_CORE_FLOW_PLT_SHIFT) | 399 XGMAC_CORE_FLOW_UP | XGMAC_CORE_FLOW_RFE | XGMAC_CORE_FLOW_TFE; 400 writel(value, ®s->flow_control); 401 402 /* Initialize the descriptor chains */ 403 init_rx_desc(priv); 404 init_tx_desc(priv); 405 406 /* must set to 0, or when started up will cause issues */ 407 priv->tx_currdesc = 0; 408 priv->rx_currdesc = 0; 409 410 /* set default core values */ 411 value = readl(®s->config); 412 value &= XGMAC_CONTROL_SPD_MASK; 413 value |= XGMAC_CONTROL_DDIC | XGMAC_CONTROL_ACS | 414 XGMAC_CONTROL_IPC | XGMAC_CONTROL_CAR; 415 416 /* Everything is ready enable both mac and DMA */ 417 value |= RXENABLE | TXENABLE; 418 writel(value, ®s->config); 419 420 value = readl(®s->dma_opmode); 421 value |= RXSTART | TXSTART; 422 writel(value, ®s->dma_opmode); 423 424 return 0; 425 } 426 427 static int xgmac_tx(struct eth_device *dev, void *packet, int length) 428 { 429 struct xgmac_regs *regs = (struct xgmac_regs *)dev->iobase; 430 struct calxeda_eth_dev *priv = dev->priv; 431 u32 currdesc = priv->tx_currdesc; 432 struct xgmac_dma_desc *txdesc = &priv->tx_chain[currdesc]; 433 int timeout; 434 435 desc_set_buf_addr_and_size(txdesc, packet, length); 436 desc_set_tx_owner(txdesc, TXDESC_FIRST_SEG | 437 TXDESC_LAST_SEG | TXDESC_CRC_EN_APPEND); 438 439 /* write poll demand */ 440 writel(1, ®s->txpoll); 441 442 timeout = 1000000; 443 while (desc_get_owner(txdesc)) { 444 if (timeout-- < 0) { 445 printf("xgmac: TX timeout\n"); 446 return -ETIMEDOUT; 447 } 448 udelay(1); 449 } 450 451 priv->tx_currdesc = (currdesc + 1) & (TX_NUM_DESC - 1); 452 return 0; 453 } 454 455 static int xgmac_rx(struct eth_device *dev) 456 { 457 struct xgmac_regs *regs = (struct xgmac_regs *)dev->iobase; 458 struct calxeda_eth_dev *priv = dev->priv; 459 u32 currdesc = priv->rx_currdesc; 460 struct xgmac_dma_desc *rxdesc = &priv->rx_chain[currdesc]; 461 int length = 0; 462 463 /* check if the host has the desc */ 464 if (desc_get_owner(rxdesc)) 465 return -1; /* something bad happened */ 466 467 length = desc_get_rx_frame_len(rxdesc); 468 469 NetReceive(desc_get_buf_addr(rxdesc), length); 470 471 /* set descriptor back to owned by XGMAC */ 472 desc_set_rx_owner(rxdesc); 473 writel(1, ®s->rxpoll); 474 475 priv->rx_currdesc = (currdesc + 1) & (RX_NUM_DESC - 1); 476 477 return length; 478 } 479 480 static void xgmac_halt(struct eth_device *dev) 481 { 482 struct xgmac_regs *regs = (struct xgmac_regs *)dev->iobase; 483 struct calxeda_eth_dev *priv = dev->priv; 484 int value; 485 486 /* Disable TX/RX */ 487 value = readl(®s->config); 488 value &= ~(RXENABLE | TXENABLE); 489 writel(value, ®s->config); 490 491 /* Disable DMA */ 492 value = readl(®s->dma_opmode); 493 value &= ~(RXSTART | TXSTART); 494 writel(value, ®s->dma_opmode); 495 496 /* must set to 0, or when started up will cause issues */ 497 priv->tx_currdesc = 0; 498 priv->rx_currdesc = 0; 499 } 500 501 int calxedaxgmac_initialize(u32 id, ulong base_addr) 502 { 503 struct eth_device *dev; 504 struct calxeda_eth_dev *priv; 505 struct xgmac_regs *regs; 506 u32 macaddr[2]; 507 508 regs = (struct xgmac_regs *)base_addr; 509 510 /* check hardware version */ 511 if (readl(®s->version) != 0x1012) 512 return -1; 513 514 dev = malloc(sizeof(*dev)); 515 if (!dev) 516 return 0; 517 memset(dev, 0, sizeof(*dev)); 518 519 /* Structure must be aligned, because it contains the descriptors */ 520 priv = memalign(32, sizeof(*priv)); 521 if (!priv) { 522 free(dev); 523 return 0; 524 } 525 526 dev->iobase = (int)base_addr; 527 dev->priv = priv; 528 priv->dev = dev; 529 sprintf(dev->name, "xgmac%d", id); 530 531 /* The MAC address is already configured, so read it from registers. */ 532 macaddr[1] = readl(®s->macaddr[0].hi); 533 macaddr[0] = readl(®s->macaddr[0].lo); 534 memcpy(dev->enetaddr, macaddr, 6); 535 536 dev->init = xgmac_init; 537 dev->send = xgmac_tx; 538 dev->recv = xgmac_rx; 539 dev->halt = xgmac_halt; 540 541 eth_register(dev); 542 543 return 1; 544 } 545