1 /* 2 * Copyright 2014 Broadcom Corporation. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef _BCM_SF2_ETH_GMAC_H_ 8 #define _BCM_SF2_ETH_GMAC_H_ 9 10 #define BCM_SF2_ETH_MAC_NAME "gmac" 11 12 #ifndef ETHHW_PORT_INT 13 #define ETHHW_PORT_INT 8 14 #endif 15 16 #define GMAC0_REG_BASE 0x18042000 17 #define GMAC0_DEV_CTRL_ADDR GMAC0_REG_BASE 18 #define GMAC0_INT_STATUS_ADDR (GMAC0_REG_BASE + 0x020) 19 #define GMAC0_INTR_RECV_LAZY_ADDR (GMAC0_REG_BASE + 0x100) 20 #define GMAC0_PHY_CTRL_ADDR (GMAC0_REG_BASE + 0x188) 21 22 23 #define GMAC_DMA_PTR_OFFSET 0x04 24 #define GMAC_DMA_ADDR_LOW_OFFSET 0x08 25 #define GMAC_DMA_ADDR_HIGH_OFFSET 0x0c 26 #define GMAC_DMA_STATUS0_OFFSET 0x10 27 #define GMAC_DMA_STATUS1_OFFSET 0x14 28 29 #define GMAC0_DMA_TX_CTRL_ADDR (GMAC0_REG_BASE + 0x200) 30 #define GMAC0_DMA_TX_PTR_ADDR \ 31 (GMAC0_DMA_TX_CTRL_ADDR + GMAC_DMA_PTR_OFFSET) 32 #define GMAC0_DMA_TX_ADDR_LOW_ADDR \ 33 (GMAC0_DMA_TX_CTRL_ADDR + GMAC_DMA_ADDR_LOW_OFFSET) 34 #define GMAC0_DMA_TX_ADDR_HIGH_ADDR \ 35 (GMAC0_DMA_TX_CTRL_ADDR + GMAC_DMA_ADDR_HIGH_OFFSET) 36 #define GMAC0_DMA_TX_STATUS0_ADDR \ 37 (GMAC0_DMA_TX_CTRL_ADDR + GMAC_DMA_STATUS0_OFFSET) 38 #define GMAC0_DMA_TX_STATUS1_ADDR \ 39 (GMAC0_DMA_TX_CTRL_ADDR + GMAC_DMA_STATUS1_OFFSET) 40 41 #define GMAC0_DMA_RX_CTRL_ADDR (GMAC0_REG_BASE + 0x220) 42 #define GMAC0_DMA_RX_PTR_ADDR \ 43 (GMAC0_DMA_RX_CTRL_ADDR + GMAC_DMA_PTR_OFFSET) 44 #define GMAC0_DMA_RX_ADDR_LOW_ADDR \ 45 (GMAC0_DMA_RX_CTRL_ADDR + GMAC_DMA_ADDR_LOW_OFFSET) 46 #define GMAC0_DMA_RX_ADDR_HIGH_ADDR \ 47 (GMAC0_DMA_RX_CTRL_ADDR + GMAC_DMA_ADDR_HIGH_OFFSET) 48 #define GMAC0_DMA_RX_STATUS0_ADDR \ 49 (GMAC0_DMA_RX_CTRL_ADDR + GMAC_DMA_STATUS0_OFFSET) 50 #define GMAC0_DMA_RX_STATUS1_ADDR \ 51 (GMAC0_DMA_RX_CTRL_ADDR + GMAC_DMA_STATUS1_OFFSET) 52 53 #define UNIMAC0_CMD_CFG_ADDR (GMAC0_REG_BASE + 0x808) 54 #define UNIMAC0_MAC_MSB_ADDR (GMAC0_REG_BASE + 0x80c) 55 #define UNIMAC0_MAC_LSB_ADDR (GMAC0_REG_BASE + 0x810) 56 #define UNIMAC0_FRM_LENGTH_ADDR (GMAC0_REG_BASE + 0x814) 57 58 #define GMAC0_IRL_FRAMECOUNT_SHIFT 24 59 60 /* transmit channel control */ 61 /* transmit enable */ 62 #define D64_XC_XE 0x00000001 63 /* transmit suspend request */ 64 #define D64_XC_SE 0x00000002 65 /* parity check disable */ 66 #define D64_XC_PD 0x00000800 67 /* BurstLen bits */ 68 #define D64_XC_BL_MASK 0x001C0000 69 #define D64_XC_BL_SHIFT 18 70 71 /* transmit descriptor table pointer */ 72 /* last valid descriptor */ 73 #define D64_XP_LD_MASK 0x00001fff 74 75 /* transmit channel status */ 76 /* transmit state */ 77 #define D64_XS0_XS_MASK 0xf0000000 78 #define D64_XS0_XS_SHIFT 28 79 #define D64_XS0_XS_DISABLED 0x00000000 80 #define D64_XS0_XS_ACTIVE 0x10000000 81 #define D64_XS0_XS_IDLE 0x20000000 82 #define D64_XS0_XS_STOPPED 0x30000000 83 #define D64_XS0_XS_SUSP 0x40000000 84 85 /* receive channel control */ 86 /* receive enable */ 87 #define D64_RC_RE 0x00000001 88 /* address extension bits */ 89 #define D64_RC_AE 0x00030000 90 /* overflow continue */ 91 #define D64_RC_OC 0x00000400 92 /* parity check disable */ 93 #define D64_RC_PD 0x00000800 94 /* receive frame offset */ 95 #define D64_RC_RO_MASK 0x000000fe 96 #define D64_RC_RO_SHIFT 1 97 /* BurstLen bits */ 98 #define D64_RC_BL_MASK 0x001C0000 99 #define D64_RC_BL_SHIFT 18 100 101 /* flags for dma controller */ 102 /* partity enable */ 103 #define DMA_CTRL_PEN (1 << 0) 104 /* rx overflow continue */ 105 #define DMA_CTRL_ROC (1 << 1) 106 107 /* receive descriptor table pointer */ 108 /* last valid descriptor */ 109 #define D64_RP_LD_MASK 0x00001fff 110 111 /* receive channel status */ 112 /* current descriptor pointer */ 113 #define D64_RS0_CD_MASK 0x00001fff 114 /* receive state */ 115 #define D64_RS0_RS_MASK 0xf0000000 116 #define D64_RS0_RS_SHIFT 28 117 #define D64_RS0_RS_DISABLED 0x00000000 118 #define D64_RS0_RS_ACTIVE 0x10000000 119 #define D64_RS0_RS_IDLE 0x20000000 120 #define D64_RS0_RS_STOPPED 0x30000000 121 #define D64_RS0_RS_SUSP 0x40000000 122 123 /* descriptor control flags 1 */ 124 /* core specific flags */ 125 #define D64_CTRL_COREFLAGS 0x0ff00000 126 /* end of descriptor table */ 127 #define D64_CTRL1_EOT ((uint32_t)1 << 28) 128 /* interrupt on completion */ 129 #define D64_CTRL1_IOC ((uint32_t)1 << 29) 130 /* end of frame */ 131 #define D64_CTRL1_EOF ((uint32_t)1 << 30) 132 /* start of frame */ 133 #define D64_CTRL1_SOF ((uint32_t)1 << 31) 134 135 /* descriptor control flags 2 */ 136 /* buffer byte count. real data len must <= 16KB */ 137 #define D64_CTRL2_BC_MASK 0x00007fff 138 /* address extension bits */ 139 #define D64_CTRL2_AE 0x00030000 140 #define D64_CTRL2_AE_SHIFT 16 141 /* parity bit */ 142 #define D64_CTRL2_PARITY 0x00040000 143 /* control flags in the range [27:20] are core-specific and not defined here */ 144 #define D64_CTRL_CORE_MASK 0x0ff00000 145 146 #define DC_MROR 0x00000010 147 #define PC_MTE 0x00800000 148 149 /* command config */ 150 #define CC_TE 0x00000001 151 #define CC_RE 0x00000002 152 #define CC_ES_MASK 0x0000000c 153 #define CC_ES_SHIFT 2 154 #define CC_PROM 0x00000010 155 #define CC_PAD_EN 0x00000020 156 #define CC_CF 0x00000040 157 #define CC_PF 0x00000080 158 #define CC_RPI 0x00000100 159 #define CC_TAI 0x00000200 160 #define CC_HD 0x00000400 161 #define CC_HD_SHIFT 10 162 #define CC_SR 0x00002000 163 #define CC_ML 0x00008000 164 #define CC_AE 0x00400000 165 #define CC_CFE 0x00800000 166 #define CC_NLC 0x01000000 167 #define CC_RL 0x02000000 168 #define CC_RED 0x04000000 169 #define CC_PE 0x08000000 170 #define CC_TPI 0x10000000 171 #define CC_AT 0x20000000 172 173 #define I_PDEE 0x00000400 174 #define I_PDE 0x00000800 175 #define I_DE 0x00001000 176 #define I_RDU 0x00002000 177 #define I_RFO 0x00004000 178 #define I_XFU 0x00008000 179 #define I_RI 0x00010000 180 #define I_XI0 0x01000000 181 #define I_XI1 0x02000000 182 #define I_XI2 0x04000000 183 #define I_XI3 0x08000000 184 #define I_ERRORS (I_PDEE | I_PDE | I_DE | I_RDU | I_RFO | I_XFU) 185 #define DEF_INTMASK (I_XI0 | I_XI1 | I_XI2 | I_XI3 | I_RI | I_ERRORS) 186 187 #define I_INTMASK 0x0f01fcff 188 189 #define CHIP_DRU_BASE 0x0301d000 190 #define CRMU_CHIP_IO_PAD_CONTROL_ADDR (CHIP_DRU_BASE + 0x0bc) 191 #define SWITCH_GLOBAL_CONFIG_ADDR (CHIP_DRU_BASE + 0x194) 192 193 #define CDRU_IOMUX_FORCE_PAD_IN_SHIFT 0 194 #define CDRU_SWITCH_BYPASS_SWITCH_SHIFT 13 195 196 #define AMAC0_IDM_RESET_ADDR 0x18110800 197 #define AMAC0_IO_CTRL_DIRECT_ADDR 0x18110408 198 #define AMAC0_IO_CTRL_CLK_250_SEL_SHIFT 6 199 #define AMAC0_IO_CTRL_GMII_MODE_SHIFT 5 200 #define AMAC0_IO_CTRL_DEST_SYNC_MODE_EN_SHIFT 3 201 202 #define CHIPA_CHIP_ID_ADDR 0x18000000 203 #define CHIPID (readl(CHIPA_CHIP_ID_ADDR) & 0xFFFF) 204 #define CHIPREV (((readl(CHIPA_CHIP_ID_ADDR) >> 16) & 0xF) 205 #define CHIPSKU (((readl(CHIPA_CHIP_ID_ADDR) >> 20) & 0xF) 206 207 #define GMAC_MII_CTRL_ADDR 0x18002000 208 #define GMAC_MII_CTRL_BYP_SHIFT 10 209 #define GMAC_MII_CTRL_EXT_SHIFT 9 210 #define GMAC_MII_DATA_ADDR 0x18002004 211 #define GMAC_MII_DATA_READ_CMD 0x60020000 212 #define GMAC_MII_DATA_WRITE_CMD 0x50020000 213 #define GMAC_MII_BUSY_SHIFT 8 214 #define GMAC_MII_PHY_ADDR_SHIFT 23 215 #define GMAC_MII_PHY_REG_SHIFT 18 216 217 #define GMAC_RESET_DELAY 2 218 #define HWRXOFF 30 219 #define MAXNAMEL 8 220 #define NUMTXQ 4 221 222 int gmac_add(struct eth_device *dev); 223 224 #endif /* _BCM_SF2_ETH_GMAC_H_ */ 225