1 /* ax88180.h: ASIX AX88180 Non-PCI Gigabit Ethernet u-boot driver */ 2 /* 3 * 4 * This program is free software; you can distribute it and/or modify it 5 * under the terms of the GNU General Public License (Version 2) as 6 * published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 11 * for more details. 12 * 13 * You should have received a copy of the GNU General Public License along 14 * with this program; if not, write to the Free Software Foundation, Inc., 15 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. 16 * 17 */ 18 19 #ifndef _AX88180_H_ 20 #define _AX88180_H_ 21 22 #include <asm/types.h> 23 #include <config.h> 24 25 typedef enum _ax88180_link_state { 26 INS_LINK_DOWN, 27 INS_LINK_UP, 28 INS_LINK_UNKNOWN 29 } ax88180_link_state; 30 31 struct ax88180_private { 32 unsigned char BusWidth; 33 unsigned char PadSize; 34 unsigned short PhyAddr; 35 unsigned short PhyID0; 36 unsigned short FirstTxDesc; 37 unsigned short NextTxDesc; 38 ax88180_link_state LinkState; 39 }; 40 41 #define BUS_WIDTH_16 1 42 #define BUS_WIDTH_32 2 43 44 #define ENABLE_JUMBO 1 45 #define DISABLE_JUMBO 0 46 47 #define ENABLE_BURST 1 48 #define DISABLE_BURST 0 49 50 #define NORMAL_RX_MODE 0 51 #define RX_LOOPBACK_MODE 1 52 #define RX_INIFINIT_LOOP_MODE 2 53 #define TX_INIFINIT_LOOP_MODE 3 54 55 #define DEFAULT_ETH_MTU 1500 56 57 /* Jumbo packet size 4086 bytes included 4 bytes CRC*/ 58 #define MAX_JUMBO_MTU 4072 59 60 /* Max Tx Jumbo size 4086 bytes included 4 bytes CRC */ 61 #define MAX_TX_JUMBO_SIZE 4086 62 63 /* Max Rx Jumbo size is 15K Bytes */ 64 #define MAX_RX_SIZE 0x3C00 65 66 #define MARVELL_88E1111_PHYSID0 0x0141 67 68 #define CICADA_CIS8201_PHYSID0 0x000F 69 70 #define MEDIA_AUTO 0 71 #define MEDIA_1000FULL 1 72 #define MEDIA_1000HALF 2 73 #define MEDIA_100FULL 3 74 #define MEDIA_100HALF 4 75 #define MEDIA_10FULL 5 76 #define MEDIA_10HALF 6 77 #define MEDIA_UNKNOWN 7 78 79 #define AUTO_MEDIA 0 80 #define FORCE_MEDIA 1 81 82 #define TXDP_MASK 3 83 #define TXDP0 0 84 #define TXDP1 1 85 #define TXDP2 2 86 #define TXDP3 3 87 88 #define CMD_MAP_SIZE 0x100 89 90 #if defined (CONFIG_DRIVER_AX88180_16BIT) 91 #define AX88180_MEMORY_SIZE 0x00004000 92 #define START_BASE 0x1000 93 94 #define RX_BUF_SIZE 0x1000 95 #define TX_BUF_SIZE 0x0F00 96 97 #define TX_BASE START_BASE 98 #define CMD_BASE (TX_BASE + TX_BUF_SIZE) 99 #define RX_BASE (CMD_BASE + CMD_MAP_SIZE) 100 #else 101 #define AX88180_MEMORY_SIZE 0x00010000 102 103 #define RX_BUF_SIZE 0x8000 104 #define TX_BUF_SIZE 0x7C00 105 106 #define RX_BASE 0x0000 107 #define TX_BASE (RX_BASE + RX_BUF_SIZE) 108 #define CMD_BASE (TX_BASE + TX_BUF_SIZE) 109 #endif 110 111 /* AX88180 Memory Mapping Definition */ 112 #define RXBUFFER_START RX_BASE 113 #define RX_PACKET_LEN_OFFSET 0 114 #define RX_PAGE_NUM_MASK 0x7FF /* RX pages 0~7FFh */ 115 #define TXBUFFER_START TX_BASE 116 117 /* AX88180 MAC Register Definition */ 118 #define DECODE (0) 119 #define DECODE_EN 0x00000001 120 #define BASE (6) 121 #define CMD (CMD_BASE + 0x0000) 122 #define WAKEMOD 0x00000001 123 #define TXEN 0x00000100 124 #define RXEN 0x00000200 125 #define DEFAULT_CMD WAKEMOD 126 #define IMR (CMD_BASE + 0x0004) 127 #define IMR_RXBUFFOVR 0x00000001 128 #define IMR_WATCHDOG 0x00000002 129 #define IMR_TX 0x00000008 130 #define IMR_RX 0x00000010 131 #define IMR_PHY 0x00000020 132 #define CLEAR_IMR 0x00000000 133 #define DEFAULT_IMR (IMR_PHY | IMR_RX | IMR_TX |\ 134 IMR_RXBUFFOVR | IMR_WATCHDOG) 135 #define ISR (CMD_BASE + 0x0008) 136 #define ISR_RXBUFFOVR 0x00000001 137 #define ISR_WATCHDOG 0x00000002 138 #define ISR_TX 0x00000008 139 #define ISR_RX 0x00000010 140 #define ISR_PHY 0x00000020 141 #define TXCFG (CMD_BASE + 0x0010) 142 #define AUTOPAD_CRC 0x00000050 143 #define DEFAULT_TXCFG AUTOPAD_CRC 144 #define TXCMD (CMD_BASE + 0x0014) 145 #define TXCMD_TXDP_MASK 0x00006000 146 #define TXCMD_TXDP0 0x00000000 147 #define TXCMD_TXDP1 0x00002000 148 #define TXCMD_TXDP2 0x00004000 149 #define TXCMD_TXDP3 0x00006000 150 #define TX_START_WRITE 0x00008000 151 #define TX_STOP_WRITE 0x00000000 152 #define DEFAULT_TXCMD 0x00000000 153 #define TXBS (CMD_BASE + 0x0018) 154 #define TXDP0_USED 0x00000001 155 #define TXDP1_USED 0x00000002 156 #define TXDP2_USED 0x00000004 157 #define TXDP3_USED 0x00000008 158 #define DEFAULT_TXBS 0x00000000 159 #define TXDES0 (CMD_BASE + 0x0020) 160 #define TXDPx_ENABLE 0x00008000 161 #define TXDPx_LEN_MASK 0x00001FFF 162 #define DEFAULT_TXDES0 0x00000000 163 #define TXDES1 (CMD_BASE + 0x0024) 164 #define TXDPx_ENABLE 0x00008000 165 #define TXDPx_LEN_MASK 0x00001FFF 166 #define DEFAULT_TXDES1 0x00000000 167 #define TXDES2 (CMD_BASE + 0x0028) 168 #define TXDPx_ENABLE 0x00008000 169 #define TXDPx_LEN_MASK 0x00001FFF 170 #define DEFAULT_TXDES2 0x00000000 171 #define TXDES3 (CMD_BASE + 0x002C) 172 #define TXDPx_ENABLE 0x00008000 173 #define TXDPx_LEN_MASK 0x00001FFF 174 #define DEFAULT_TXDES3 0x00000000 175 #define RXCFG (CMD_BASE + 0x0030) 176 #define RXBUFF_PROTECT 0x00000001 177 #define RXTCPCRC_CHECK 0x00000010 178 #define RXFLOW_ENABLE 0x00000100 179 #define DEFAULT_RXCFG RXBUFF_PROTECT 180 #define RXCURT (CMD_BASE + 0x0034) 181 #define DEFAULT_RXCURT 0x00000000 182 #define RXBOUND (CMD_BASE + 0x0038) 183 #define DEFAULT_RXBOUND 0x7FF /* RX pages 0~7FFh */ 184 #define MACCFG0 (CMD_BASE + 0x0040) 185 #define MACCFG0_BIT3_0 0x00000007 186 #define IPGT_VAL 0x00000150 187 #define TXFLOW_ENABLE 0x00001000 188 #define SPEED100 0x00008000 189 #define DEFAULT_MACCFG0 (IPGT_VAL | MACCFG0_BIT3_0) 190 #define MACCFG1 (CMD_BASE + 0x0044) 191 #define RGMII_EN 0x00000002 192 #define RXFLOW_EN 0x00000020 193 #define FULLDUPLEX 0x00000040 194 #define MAX_JUMBO_LEN 0x00000780 195 #define RXJUMBO_EN 0x00000800 196 #define GIGA_MODE_EN 0x00001000 197 #define RXCRC_CHECK 0x00002000 198 #define RXPAUSE_DA_CHECK 0x00004000 199 200 #define JUMBO_LEN_4K 0x00000200 201 #define JUMBO_LEN_15K 0x00000780 202 #define DEFAULT_MACCFG1 (RXCRC_CHECK | RXPAUSE_DA_CHECK | \ 203 RGMII_EN) 204 #define CICADA_DEFAULT_MACCFG1 (RXCRC_CHECK | RXPAUSE_DA_CHECK) 205 #define MACCFG2 (CMD_BASE + 0x0048) 206 #define MACCFG2_BIT15_8 0x00000100 207 #define JAM_LIMIT_MASK 0x000000FC 208 #define DEFAULT_JAM_LIMIT 0x00000064 209 #define DEFAULT_MACCFG2 MACCFG2_BIT15_8 210 #define MACCFG3 (CMD_BASE + 0x004C) 211 #define IPGR2_VAL 0x0000000E 212 #define IPGR1_VAL 0x00000600 213 #define NOABORT 0x00008000 214 #define DEFAULT_MACCFG3 (IPGR1_VAL | IPGR2_VAL) 215 #define TXPAUT (CMD_BASE + 0x0054) 216 #define DEFAULT_TXPAUT 0x001FE000 217 #define RXBTHD0 (CMD_BASE + 0x0058) 218 #define DEFAULT_RXBTHD0 0x00000300 219 #define RXBTHD1 (CMD_BASE + 0x005C) 220 #define DEFAULT_RXBTHD1 0x00000600 221 #define RXFULTHD (CMD_BASE + 0x0060) 222 #define DEFAULT_RXFULTHD 0x00000100 223 #define MISC (CMD_BASE + 0x0068) 224 /* Normal operation mode */ 225 #define MISC_NORMAL 0x00000003 226 /* Clear bit 0 to reset MAC */ 227 #define MISC_RESET_MAC 0x00000002 228 /* Clear bit 1 to reset PHY */ 229 #define MISC_RESET_PHY 0x00000001 230 /* Clear bit 0 and 1 to reset MAC and PHY */ 231 #define MISC_RESET_MAC_PHY 0x00000000 232 #define DEFAULT_MISC MISC_NORMAL 233 #define MACID0 (CMD_BASE + 0x0070) 234 #define MACID1 (CMD_BASE + 0x0074) 235 #define MACID2 (CMD_BASE + 0x0078) 236 #define TXLEN (CMD_BASE + 0x007C) 237 #define DEFAULT_TXLEN 0x000005FC 238 #define RXFILTER (CMD_BASE + 0x0080) 239 #define RX_RXANY 0x00000001 240 #define RX_MULTICAST 0x00000002 241 #define RX_UNICAST 0x00000004 242 #define RX_BROADCAST 0x00000008 243 #define RX_MULTI_HASH 0x00000010 244 #define DISABLE_RXFILTER 0x00000000 245 #define DEFAULT_RXFILTER (RX_BROADCAST + RX_UNICAST) 246 #define MDIOCTRL (CMD_BASE + 0x0084) 247 #define PHY_ADDR_MASK 0x0000001F 248 #define REG_ADDR_MASK 0x00001F00 249 #define READ_PHY 0x00004000 250 #define WRITE_PHY 0x00008000 251 #define MDIODP (CMD_BASE + 0x0088) 252 #define GPIOCTRL (CMD_BASE + 0x008C) 253 #define RXINDICATOR (CMD_BASE + 0x0090) 254 #define RX_START_READ 0x00000001 255 #define RX_STOP_READ 0x00000000 256 #define DEFAULT_RXINDICATOR RX_STOP_READ 257 #define TXST (CMD_BASE + 0x0094) 258 #define MDCCLKPAT (CMD_BASE + 0x00A0) 259 #define RXIPCRCCNT (CMD_BASE + 0x00A4) 260 #define RXCRCCNT (CMD_BASE + 0x00A8) 261 #define TXFAILCNT (CMD_BASE + 0x00AC) 262 #define PROMDP (CMD_BASE + 0x00B0) 263 #define PROMCTRL (CMD_BASE + 0x00B4) 264 #define RELOAD_EEPROM 0x00000200 265 #define MAXRXLEN (CMD_BASE + 0x00B8) 266 #define HASHTAB0 (CMD_BASE + 0x00C0) 267 #define HASHTAB1 (CMD_BASE + 0x00C4) 268 #define HASHTAB2 (CMD_BASE + 0x00C8) 269 #define HASHTAB3 (CMD_BASE + 0x00CC) 270 #define DOGTHD0 (CMD_BASE + 0x00E0) 271 #define DEFAULT_DOGTHD0 0x0000FFFF 272 #define DOGTHD1 (CMD_BASE + 0x00E4) 273 #define START_WATCHDOG_TIMER 0x00008000 274 #define DEFAULT_DOGTHD1 0x00000FFF 275 #define SOFTRST (CMD_BASE + 0x00EC) 276 #define SOFTRST_NORMAL 0x00000003 277 #define SOFTRST_RESET_MAC 0x00000002 278 279 /* Marvell 88E1111 Gigabit PHY Register Definition */ 280 #define M88_SSR 0x0011 281 #define SSR_SPEED_MASK 0xC000 282 #define SSR_SPEED_1000 0x8000 283 #define SSR_SPEED_100 0x4000 284 #define SSR_SPEED_10 0x0000 285 #define SSR_DUPLEX 0x2000 286 #define SSR_MEDIA_RESOLVED_OK 0x0800 287 288 #define SSR_MEDIA_MASK (SSR_SPEED_MASK | SSR_DUPLEX) 289 #define SSR_1000FULL (SSR_SPEED_1000 | SSR_DUPLEX) 290 #define SSR_1000HALF SSR_SPEED_1000 291 #define SSR_100FULL (SSR_SPEED_100 | SSR_DUPLEX) 292 #define SSR_100HALF SSR_SPEED_100 293 #define SSR_10FULL (SSR_SPEED_10 | SSR_DUPLEX) 294 #define SSR_10HALF SSR_SPEED_10 295 #define M88_IER 0x0012 296 #define LINK_CHANGE_INT 0x0400 297 #define M88_ISR 0x0013 298 #define LINK_CHANGE_STATUS 0x0400 299 #define M88_EXT_SCR 0x0014 300 #define RGMII_RXCLK_DELAY 0x0080 301 #define RGMII_TXCLK_DELAY 0x0002 302 #define DEFAULT_EXT_SCR (RGMII_TXCLK_DELAY | RGMII_RXCLK_DELAY) 303 #define M88_EXT_SSR 0x001B 304 #define HWCFG_MODE_MASK 0x000F 305 #define RGMII_COPPER_MODE 0x000B 306 307 /* CICADA CIS8201 Gigabit PHY Register Definition */ 308 #define CIS_IMR 0x0019 309 #define CIS_INT_ENABLE 0x8000 310 #define CIS_LINK_CHANGE_INT 0x2000 311 #define CIS_ISR 0x001A 312 #define CIS_INT_PENDING 0x8000 313 #define CIS_LINK_CHANGE_STATUS 0x2000 314 #define CIS_AUX_CTRL_STATUS 0x001C 315 #define CIS_AUTONEG_COMPLETE 0x8000 316 #define CIS_SPEED_MASK 0x0018 317 #define CIS_SPEED_1000 0x0010 318 #define CIS_SPEED_100 0x0008 319 #define CIS_SPEED_10 0x0000 320 #define CIS_DUPLEX 0x0020 321 322 #define CIS_MEDIA_MASK (CIS_SPEED_MASK | CIS_DUPLEX) 323 #define CIS_1000FULL (CIS_SPEED_1000 | CIS_DUPLEX) 324 #define CIS_1000HALF CIS_SPEED_1000 325 #define CIS_100FULL (CIS_SPEED_100 | CIS_DUPLEX) 326 #define CIS_100HALF CIS_SPEED_100 327 #define CIS_10FULL (CIS_SPEED_10 | CIS_DUPLEX) 328 #define CIS_10HALF CIS_SPEED_10 329 #define CIS_SMI_PRIORITY 0x0004 330 331 static inline unsigned short INW (struct eth_device *dev, unsigned long addr) 332 { 333 return le16_to_cpu (*(volatile unsigned short *) (addr + dev->iobase)); 334 } 335 336 static inline void OUTW (struct eth_device *dev, unsigned short command, unsigned long addr) 337 { 338 *(volatile unsigned short *) ((addr + dev->iobase)) = cpu_to_le16 (command); 339 } 340 341 /* 342 Access RXBUFFER_START/TXBUFFER_START to read RX buffer/write TX buffer 343 */ 344 #if defined (CONFIG_DRIVER_AX88180_16BIT) 345 static inline unsigned short READ_RXBUF (struct eth_device *dev) 346 { 347 return le16_to_cpu (*(volatile unsigned short *) (RXBUFFER_START + dev->iobase)); 348 } 349 350 static inline void WRITE_TXBUF (struct eth_device *dev, unsigned short data) 351 { 352 *(volatile unsigned short *) ((TXBUFFER_START + dev->iobase)) = cpu_to_le16 (data); 353 } 354 #else 355 static inline unsigned long READ_RXBUF (struct eth_device *dev) 356 { 357 return le32_to_cpu (*(volatile unsigned long *) (RXBUFFER_START + dev->iobase)); 358 } 359 360 static inline void WRITE_TXBUF (struct eth_device *dev, unsigned long data) 361 { 362 *(volatile unsigned long *) ((TXBUFFER_START + dev->iobase)) = cpu_to_le32 (data); 363 } 364 #endif 365 366 #endif /* _AX88180_H_ */ 367