1*30f57471SLouis Su /* ax88180.h: ASIX AX88180 Non-PCI Gigabit Ethernet u-boot driver */ 2*30f57471SLouis Su /* 3*30f57471SLouis Su * 4*30f57471SLouis Su * This program is free software; you can distribute it and/or modify it 5*30f57471SLouis Su * under the terms of the GNU General Public License (Version 2) as 6*30f57471SLouis Su * published by the Free Software Foundation. 7*30f57471SLouis Su * 8*30f57471SLouis Su * This program is distributed in the hope it will be useful, but WITHOUT 9*30f57471SLouis Su * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10*30f57471SLouis Su * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 11*30f57471SLouis Su * for more details. 12*30f57471SLouis Su * 13*30f57471SLouis Su * You should have received a copy of the GNU General Public License along 14*30f57471SLouis Su * with this program; if not, write to the Free Software Foundation, Inc., 15*30f57471SLouis Su * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. 16*30f57471SLouis Su * 17*30f57471SLouis Su */ 18*30f57471SLouis Su 19*30f57471SLouis Su #ifndef _AX88180_H_ 20*30f57471SLouis Su #define _AX88180_H_ 21*30f57471SLouis Su 22*30f57471SLouis Su #include <asm/types.h> 23*30f57471SLouis Su #include <config.h> 24*30f57471SLouis Su 25*30f57471SLouis Su typedef enum _ax88180_link_state { 26*30f57471SLouis Su INS_LINK_DOWN, 27*30f57471SLouis Su INS_LINK_UP, 28*30f57471SLouis Su INS_LINK_UNKNOWN 29*30f57471SLouis Su } ax88180_link_state; 30*30f57471SLouis Su 31*30f57471SLouis Su struct ax88180_private { 32*30f57471SLouis Su unsigned char BusWidth; 33*30f57471SLouis Su unsigned char PadSize; 34*30f57471SLouis Su unsigned short PhyAddr; 35*30f57471SLouis Su unsigned short PhyID0; 36*30f57471SLouis Su unsigned short FirstTxDesc; 37*30f57471SLouis Su unsigned short NextTxDesc; 38*30f57471SLouis Su ax88180_link_state LinkState; 39*30f57471SLouis Su }; 40*30f57471SLouis Su 41*30f57471SLouis Su #define BUS_WIDTH_16 1 42*30f57471SLouis Su #define BUS_WIDTH_32 2 43*30f57471SLouis Su 44*30f57471SLouis Su #define ENABLE_JUMBO 1 45*30f57471SLouis Su #define DISABLE_JUMBO 0 46*30f57471SLouis Su 47*30f57471SLouis Su #define ENABLE_BURST 1 48*30f57471SLouis Su #define DISABLE_BURST 0 49*30f57471SLouis Su 50*30f57471SLouis Su #define NORMAL_RX_MODE 0 51*30f57471SLouis Su #define RX_LOOPBACK_MODE 1 52*30f57471SLouis Su #define RX_INIFINIT_LOOP_MODE 2 53*30f57471SLouis Su #define TX_INIFINIT_LOOP_MODE 3 54*30f57471SLouis Su 55*30f57471SLouis Su #define DEFAULT_ETH_MTU 1500 56*30f57471SLouis Su 57*30f57471SLouis Su /* Jumbo packet size 4086 bytes included 4 bytes CRC*/ 58*30f57471SLouis Su #define MAX_JUMBO_MTU 4072 59*30f57471SLouis Su 60*30f57471SLouis Su /* Max Tx Jumbo size 4086 bytes included 4 bytes CRC */ 61*30f57471SLouis Su #define MAX_TX_JUMBO_SIZE 4086 62*30f57471SLouis Su 63*30f57471SLouis Su /* Max Rx Jumbo size is 15K Bytes */ 64*30f57471SLouis Su #define MAX_RX_SIZE 0x3C00 65*30f57471SLouis Su 66*30f57471SLouis Su #define MARVELL_88E1111_PHYADDR 0x18 67*30f57471SLouis Su #define MARVELL_88E1111_PHYIDR0 0x0141 68*30f57471SLouis Su 69*30f57471SLouis Su #define CICADA_CIS8201_PHYADDR 0x01 70*30f57471SLouis Su #define CICADA_CIS8201_PHYIDR0 0x000F 71*30f57471SLouis Su 72*30f57471SLouis Su #define MEDIA_AUTO 0 73*30f57471SLouis Su #define MEDIA_1000FULL 1 74*30f57471SLouis Su #define MEDIA_1000HALF 2 75*30f57471SLouis Su #define MEDIA_100FULL 3 76*30f57471SLouis Su #define MEDIA_100HALF 4 77*30f57471SLouis Su #define MEDIA_10FULL 5 78*30f57471SLouis Su #define MEDIA_10HALF 6 79*30f57471SLouis Su #define MEDIA_UNKNOWN 7 80*30f57471SLouis Su 81*30f57471SLouis Su #define AUTO_MEDIA 0 82*30f57471SLouis Su #define FORCE_MEDIA 1 83*30f57471SLouis Su 84*30f57471SLouis Su #define TXDP_MASK 3 85*30f57471SLouis Su #define TXDP0 0 86*30f57471SLouis Su #define TXDP1 1 87*30f57471SLouis Su #define TXDP2 2 88*30f57471SLouis Su #define TXDP3 3 89*30f57471SLouis Su 90*30f57471SLouis Su #define CMD_MAP_SIZE 0x100 91*30f57471SLouis Su 92*30f57471SLouis Su #if defined (CONFIG_DRIVER_AX88180_16BIT) 93*30f57471SLouis Su #define AX88180_MEMORY_SIZE 0x00004000 94*30f57471SLouis Su #define START_BASE 0x1000 95*30f57471SLouis Su 96*30f57471SLouis Su #define RX_BUF_SIZE 0x1000 97*30f57471SLouis Su #define TX_BUF_SIZE 0x0F00 98*30f57471SLouis Su 99*30f57471SLouis Su #define TX_BASE START_BASE 100*30f57471SLouis Su #define CMD_BASE (TX_BASE + TX_BUF_SIZE) 101*30f57471SLouis Su #define RX_BASE (CMD_BASE + CMD_MAP_SIZE) 102*30f57471SLouis Su #else 103*30f57471SLouis Su #define AX88180_MEMORY_SIZE 0x00010000 104*30f57471SLouis Su 105*30f57471SLouis Su #define RX_BUF_SIZE 0x8000 106*30f57471SLouis Su #define TX_BUF_SIZE 0x7C00 107*30f57471SLouis Su 108*30f57471SLouis Su #define RX_BASE 0x0000 109*30f57471SLouis Su #define TX_BASE (RX_BASE + RX_BUF_SIZE) 110*30f57471SLouis Su #define CMD_BASE (TX_BASE + TX_BUF_SIZE) 111*30f57471SLouis Su #endif 112*30f57471SLouis Su 113*30f57471SLouis Su /* AX88180 Memory Mapping Definition */ 114*30f57471SLouis Su #define RXBUFFER_START RX_BASE 115*30f57471SLouis Su #define RX_PACKET_LEN_OFFSET 0 116*30f57471SLouis Su #define RX_PAGE_NUM_MASK 0x7FF /* RX pages 0~7FFh */ 117*30f57471SLouis Su #define TXBUFFER_START TX_BASE 118*30f57471SLouis Su 119*30f57471SLouis Su /* AX88180 MAC Register Definition */ 120*30f57471SLouis Su #define DECODE (0) 121*30f57471SLouis Su #define DECODE_EN 0x00000001 122*30f57471SLouis Su #define BASE (6) 123*30f57471SLouis Su #define CMD (CMD_BASE + 0x0000) 124*30f57471SLouis Su #define WAKEMOD 0x00000001 125*30f57471SLouis Su #define TXEN 0x00000100 126*30f57471SLouis Su #define RXEN 0x00000200 127*30f57471SLouis Su #define DEFAULT_CMD WAKEMOD 128*30f57471SLouis Su #define IMR (CMD_BASE + 0x0004) 129*30f57471SLouis Su #define IMR_RXBUFFOVR 0x00000001 130*30f57471SLouis Su #define IMR_WATCHDOG 0x00000002 131*30f57471SLouis Su #define IMR_TX 0x00000008 132*30f57471SLouis Su #define IMR_RX 0x00000010 133*30f57471SLouis Su #define IMR_PHY 0x00000020 134*30f57471SLouis Su #define CLEAR_IMR 0x00000000 135*30f57471SLouis Su #define DEFAULT_IMR (IMR_PHY | IMR_RX | IMR_TX |\ 136*30f57471SLouis Su IMR_RXBUFFOVR | IMR_WATCHDOG) 137*30f57471SLouis Su #define ISR (CMD_BASE + 0x0008) 138*30f57471SLouis Su #define ISR_RXBUFFOVR 0x00000001 139*30f57471SLouis Su #define ISR_WATCHDOG 0x00000002 140*30f57471SLouis Su #define ISR_TX 0x00000008 141*30f57471SLouis Su #define ISR_RX 0x00000010 142*30f57471SLouis Su #define ISR_PHY 0x00000020 143*30f57471SLouis Su #define TXCFG (CMD_BASE + 0x0010) 144*30f57471SLouis Su #define AUTOPAD_CRC 0x00000050 145*30f57471SLouis Su #define DEFAULT_TXCFG AUTOPAD_CRC 146*30f57471SLouis Su #define TXCMD (CMD_BASE + 0x0014) 147*30f57471SLouis Su #define TXCMD_TXDP_MASK 0x00006000 148*30f57471SLouis Su #define TXCMD_TXDP0 0x00000000 149*30f57471SLouis Su #define TXCMD_TXDP1 0x00002000 150*30f57471SLouis Su #define TXCMD_TXDP2 0x00004000 151*30f57471SLouis Su #define TXCMD_TXDP3 0x00006000 152*30f57471SLouis Su #define TX_START_WRITE 0x00008000 153*30f57471SLouis Su #define TX_STOP_WRITE 0x00000000 154*30f57471SLouis Su #define DEFAULT_TXCMD 0x00000000 155*30f57471SLouis Su #define TXBS (CMD_BASE + 0x0018) 156*30f57471SLouis Su #define TXDP0_USED 0x00000001 157*30f57471SLouis Su #define TXDP1_USED 0x00000002 158*30f57471SLouis Su #define TXDP2_USED 0x00000004 159*30f57471SLouis Su #define TXDP3_USED 0x00000008 160*30f57471SLouis Su #define DEFAULT_TXBS 0x00000000 161*30f57471SLouis Su #define TXDES0 (CMD_BASE + 0x0020) 162*30f57471SLouis Su #define TXDPx_ENABLE 0x00008000 163*30f57471SLouis Su #define TXDPx_LEN_MASK 0x00001FFF 164*30f57471SLouis Su #define DEFAULT_TXDES0 0x00000000 165*30f57471SLouis Su #define TXDES1 (CMD_BASE + 0x0024) 166*30f57471SLouis Su #define TXDPx_ENABLE 0x00008000 167*30f57471SLouis Su #define TXDPx_LEN_MASK 0x00001FFF 168*30f57471SLouis Su #define DEFAULT_TXDES1 0x00000000 169*30f57471SLouis Su #define TXDES2 (CMD_BASE + 0x0028) 170*30f57471SLouis Su #define TXDPx_ENABLE 0x00008000 171*30f57471SLouis Su #define TXDPx_LEN_MASK 0x00001FFF 172*30f57471SLouis Su #define DEFAULT_TXDES2 0x00000000 173*30f57471SLouis Su #define TXDES3 (CMD_BASE + 0x002C) 174*30f57471SLouis Su #define TXDPx_ENABLE 0x00008000 175*30f57471SLouis Su #define TXDPx_LEN_MASK 0x00001FFF 176*30f57471SLouis Su #define DEFAULT_TXDES3 0x00000000 177*30f57471SLouis Su #define RXCFG (CMD_BASE + 0x0030) 178*30f57471SLouis Su #define RXBUFF_PROTECT 0x00000001 179*30f57471SLouis Su #define RXTCPCRC_CHECK 0x00000010 180*30f57471SLouis Su #define RXFLOW_ENABLE 0x00000100 181*30f57471SLouis Su #define DEFAULT_RXCFG RXBUFF_PROTECT 182*30f57471SLouis Su #define RXCURT (CMD_BASE + 0x0034) 183*30f57471SLouis Su #define DEFAULT_RXCURT 0x00000000 184*30f57471SLouis Su #define RXBOUND (CMD_BASE + 0x0038) 185*30f57471SLouis Su #define DEFAULT_RXBOUND 0x7FF //RX pages 0~7FFh 186*30f57471SLouis Su #define MACCFG0 (CMD_BASE + 0x0040) 187*30f57471SLouis Su #define MACCFG0_BIT3_0 0x00000007 188*30f57471SLouis Su #define IPGT_VAL 0x00000150 189*30f57471SLouis Su #define TXFLOW_ENABLE 0x00001000 190*30f57471SLouis Su #define SPEED100 0x00008000 191*30f57471SLouis Su #define DEFAULT_MACCFG0 (IPGT_VAL | MACCFG0_BIT3_0) 192*30f57471SLouis Su #define MACCFG1 (CMD_BASE + 0x0044) 193*30f57471SLouis Su #define RGMII_EN 0x00000002 194*30f57471SLouis Su #define RXFLOW_EN 0x00000020 195*30f57471SLouis Su #define FULLDUPLEX 0x00000040 196*30f57471SLouis Su #define MAX_JUMBO_LEN 0x00000780 197*30f57471SLouis Su #define RXJUMBO_EN 0x00000800 198*30f57471SLouis Su #define GIGA_MODE_EN 0x00001000 199*30f57471SLouis Su #define RXCRC_CHECK 0x00002000 200*30f57471SLouis Su #define RXPAUSE_DA_CHECK 0x00004000 201*30f57471SLouis Su 202*30f57471SLouis Su #define JUMBO_LEN_4K 0x00000200 203*30f57471SLouis Su #define JUMBO_LEN_15K 0x00000780 204*30f57471SLouis Su #define DEFAULT_MACCFG1 (RXCRC_CHECK | RXPAUSE_DA_CHECK | \ 205*30f57471SLouis Su RGMII_EN) 206*30f57471SLouis Su #define CICADA_DEFAULT_MACCFG1 (RXCRC_CHECK | RXPAUSE_DA_CHECK) 207*30f57471SLouis Su #define MACCFG2 (CMD_BASE + 0x0048) 208*30f57471SLouis Su #define MACCFG2_BIT15_8 0x00000100 209*30f57471SLouis Su #define JAM_LIMIT_MASK 0x000000FC 210*30f57471SLouis Su #define DEFAULT_JAM_LIMIT 0x00000064 211*30f57471SLouis Su #define DEFAULT_MACCFG2 MACCFG2_BIT15_8 212*30f57471SLouis Su #define MACCFG3 (CMD_BASE + 0x004C) 213*30f57471SLouis Su #define IPGR2_VAL 0x0000000E 214*30f57471SLouis Su #define IPGR1_VAL 0x00000600 215*30f57471SLouis Su #define NOABORT 0x00008000 216*30f57471SLouis Su #define DEFAULT_MACCFG3 (IPGR1_VAL | IPGR2_VAL) 217*30f57471SLouis Su #define TXPAUT (CMD_BASE + 0x0054) 218*30f57471SLouis Su #define DEFAULT_TXPAUT 0x001FE000 219*30f57471SLouis Su #define RXBTHD0 (CMD_BASE + 0x0058) 220*30f57471SLouis Su #define DEFAULT_RXBTHD0 0x00000300 221*30f57471SLouis Su #define RXBTHD1 (CMD_BASE + 0x005C) 222*30f57471SLouis Su #define DEFAULT_RXBTHD1 0x00000600 223*30f57471SLouis Su #define RXFULTHD (CMD_BASE + 0x0060) 224*30f57471SLouis Su #define DEFAULT_RXFULTHD 0x00000100 225*30f57471SLouis Su #define MISC (CMD_BASE + 0x0068) 226*30f57471SLouis Su /* Normal operation mode */ 227*30f57471SLouis Su #define MISC_NORMAL 0x00000003 228*30f57471SLouis Su /* Clear bit 0 to reset MAC */ 229*30f57471SLouis Su #define MISC_RESET_MAC 0x00000002 230*30f57471SLouis Su /* Clear bit 1 to reset PHY */ 231*30f57471SLouis Su #define MISC_RESET_PHY 0x00000001 232*30f57471SLouis Su /* Clear bit 0 and 1 to reset MAC and PHY */ 233*30f57471SLouis Su #define MISC_RESET_MAC_PHY 0x00000000 234*30f57471SLouis Su #define DEFAULT_MISC MISC_NORMAL 235*30f57471SLouis Su #define MACID0 (CMD_BASE + 0x0070) 236*30f57471SLouis Su #define MACID1 (CMD_BASE + 0x0074) 237*30f57471SLouis Su #define MACID2 (CMD_BASE + 0x0078) 238*30f57471SLouis Su #define TXLEN (CMD_BASE + 0x007C) 239*30f57471SLouis Su #define DEFAULT_TXLEN 0x000005FC 240*30f57471SLouis Su #define RXFILTER (CMD_BASE + 0x0080) 241*30f57471SLouis Su #define RX_RXANY 0x00000001 242*30f57471SLouis Su #define RX_MULTICAST 0x00000002 243*30f57471SLouis Su #define RX_UNICAST 0x00000004 244*30f57471SLouis Su #define RX_BROADCAST 0x00000008 245*30f57471SLouis Su #define RX_MULTI_HASH 0x00000010 246*30f57471SLouis Su #define DISABLE_RXFILTER 0x00000000 247*30f57471SLouis Su #define DEFAULT_RXFILTER (RX_BROADCAST + RX_UNICAST) 248*30f57471SLouis Su #define MDIOCTRL (CMD_BASE + 0x0084) 249*30f57471SLouis Su #define PHY_ADDR_MASK 0x0000001F 250*30f57471SLouis Su #define REG_ADDR_MASK 0x00001F00 251*30f57471SLouis Su #define READ_PHY 0x00004000 252*30f57471SLouis Su #define WRITE_PHY 0x00008000 253*30f57471SLouis Su #define MDIODP (CMD_BASE + 0x0088) 254*30f57471SLouis Su #define GPIOCTRL (CMD_BASE + 0x008C) 255*30f57471SLouis Su #define RXINDICATOR (CMD_BASE + 0x0090) 256*30f57471SLouis Su #define RX_START_READ 0x00000001 257*30f57471SLouis Su #define RX_STOP_READ 0x00000000 258*30f57471SLouis Su #define DEFAULT_RXINDICATOR RX_STOP_READ 259*30f57471SLouis Su #define TXST (CMD_BASE + 0x0094) 260*30f57471SLouis Su #define MDCCLKPAT (CMD_BASE + 0x00A0) 261*30f57471SLouis Su #define RXIPCRCCNT (CMD_BASE + 0x00A4) 262*30f57471SLouis Su #define RXCRCCNT (CMD_BASE + 0x00A8) 263*30f57471SLouis Su #define TXFAILCNT (CMD_BASE + 0x00AC) 264*30f57471SLouis Su #define PROMDP (CMD_BASE + 0x00B0) 265*30f57471SLouis Su #define PROMCTRL (CMD_BASE + 0x00B4) 266*30f57471SLouis Su #define RELOAD_EEPROM 0x00000200 267*30f57471SLouis Su #define MAXRXLEN (CMD_BASE + 0x00B8) 268*30f57471SLouis Su #define HASHTAB0 (CMD_BASE + 0x00C0) 269*30f57471SLouis Su #define HASHTAB1 (CMD_BASE + 0x00C4) 270*30f57471SLouis Su #define HASHTAB2 (CMD_BASE + 0x00C8) 271*30f57471SLouis Su #define HASHTAB3 (CMD_BASE + 0x00CC) 272*30f57471SLouis Su #define DOGTHD0 (CMD_BASE + 0x00E0) 273*30f57471SLouis Su #define DEFAULT_DOGTHD0 0x0000FFFF 274*30f57471SLouis Su #define DOGTHD1 (CMD_BASE + 0x00E4) 275*30f57471SLouis Su #define START_WATCHDOG_TIMER 0x00008000 276*30f57471SLouis Su #define DEFAULT_DOGTHD1 0x00000FFF 277*30f57471SLouis Su #define SOFTRST (CMD_BASE + 0x00EC) 278*30f57471SLouis Su #define SOFTRST_NORMAL 0x00000003 279*30f57471SLouis Su #define SOFTRST_RESET_MAC 0x00000002 280*30f57471SLouis Su 281*30f57471SLouis Su /* External PHY Register Definition */ 282*30f57471SLouis Su #define BMCR 0x0000 283*30f57471SLouis Su #define LINE_SPEED_MSB 0x0040 284*30f57471SLouis Su #define DUPLEX_MODE 0x0100 285*30f57471SLouis Su #define RESTART_AUTONEG 0x0200 286*30f57471SLouis Su #define POWER_DOWN 0x0800 287*30f57471SLouis Su #define AUTONEG_EN 0x1000 288*30f57471SLouis Su #define LINE_SPEED_LSB 0x2000 289*30f57471SLouis Su #define PHY_RESET 0x8000 290*30f57471SLouis Su 291*30f57471SLouis Su #define MEDIAMODE_MASK (LINE_SPEED_MSB | LINE_SPEED_LSB |\ 292*30f57471SLouis Su DUPLEX_MODE) 293*30f57471SLouis Su #define BMCR_SPEED_1000 LINE_SPEED_MSB 294*30f57471SLouis Su #define BMCR_SPEED_100 LINE_SPEED_LSB 295*30f57471SLouis Su #define BMCR_SPEED_10 0x0000 296*30f57471SLouis Su 297*30f57471SLouis Su #define BMCR_1000FULL (BMCR_SPEED_1000 | DUPLEX_MODE) 298*30f57471SLouis Su #define BMCR_100FULL (BMCR_SPEED_100 | DUPLEX_MODE) 299*30f57471SLouis Su #define BMCR_100HALF BMCR_SPEED_100 300*30f57471SLouis Su #define BMCR_10FULL DUPLEX_MODE 301*30f57471SLouis Su #define BMCR_10HALF 0x0000 302*30f57471SLouis Su #define BMSR 0x0001 303*30f57471SLouis Su #define LINKOK 0x0004 304*30f57471SLouis Su #define AUTONEG_ENABLE_STS 0x0008 305*30f57471SLouis Su #define AUTONEG_COMPLETE 0x0020 306*30f57471SLouis Su #define PHYIDR0 0x0002 307*30f57471SLouis Su #define PHYIDR1 0x0003 308*30f57471SLouis Su #define ANAR 0x0004 309*30f57471SLouis Su #define ANAR_PAUSE 0x0400 310*30f57471SLouis Su #define ANAR_100FULL 0x0100 311*30f57471SLouis Su #define ANAR_100HALF 0x0080 312*30f57471SLouis Su #define ANAR_10FULL 0x0040 313*30f57471SLouis Su #define ANAR_10HALF 0x0020 314*30f57471SLouis Su #define ANAR_8023BIT 0x0001 315*30f57471SLouis Su #define ANLPAR 0x0005 316*30f57471SLouis Su #define ANER 0x0006 317*30f57471SLouis Su #define AUX_1000_CTRL 0x0009 318*30f57471SLouis Su #define ENABLE_1000HALF 0x0100 319*30f57471SLouis Su #define ENABLE_1000FULL 0x0200 320*30f57471SLouis Su #define DEFAULT_AUX_1000_CTRL (ENABLE_1000HALF | ENABLE_1000FULL) 321*30f57471SLouis Su #define AUX_1000_STATUS 0x000A 322*30f57471SLouis Su #define LP_1000HALF 0x0400 323*30f57471SLouis Su #define LP_1000FULL 0x0800 324*30f57471SLouis Su 325*30f57471SLouis Su /* Marvell 88E1111 Gigabit PHY Register Definition */ 326*30f57471SLouis Su #define M88_SSR 0x0011 327*30f57471SLouis Su #define SSR_SPEED_MASK 0xC000 328*30f57471SLouis Su #define SSR_SPEED_1000 0x8000 329*30f57471SLouis Su #define SSR_SPEED_100 0x4000 330*30f57471SLouis Su #define SSR_SPEED_10 0x0000 331*30f57471SLouis Su #define SSR_DUPLEX 0x2000 332*30f57471SLouis Su #define SSR_MEDIA_RESOLVED_OK 0x0800 333*30f57471SLouis Su 334*30f57471SLouis Su #define SSR_MEDIA_MASK (SSR_SPEED_MASK | SSR_DUPLEX) 335*30f57471SLouis Su #define SSR_1000FULL (SSR_SPEED_1000 | SSR_DUPLEX) 336*30f57471SLouis Su #define SSR_1000HALF SSR_SPEED_1000 337*30f57471SLouis Su #define SSR_100FULL (SSR_SPEED_100 | SSR_DUPLEX) 338*30f57471SLouis Su #define SSR_100HALF SSR_SPEED_100 339*30f57471SLouis Su #define SSR_10FULL (SSR_SPEED_10 | SSR_DUPLEX) 340*30f57471SLouis Su #define SSR_10HALF SSR_SPEED_10 341*30f57471SLouis Su #define M88_IER 0x0012 342*30f57471SLouis Su #define LINK_CHANGE_INT 0x0400 343*30f57471SLouis Su #define M88_ISR 0x0013 344*30f57471SLouis Su #define LINK_CHANGE_STATUS 0x0400 345*30f57471SLouis Su #define M88_EXT_SCR 0x0014 346*30f57471SLouis Su #define RGMII_RXCLK_DELAY 0x0080 347*30f57471SLouis Su #define RGMII_TXCLK_DELAY 0x0002 348*30f57471SLouis Su #define DEFAULT_EXT_SCR (RGMII_TXCLK_DELAY | RGMII_RXCLK_DELAY) 349*30f57471SLouis Su #define M88_EXT_SSR 0x001B 350*30f57471SLouis Su #define HWCFG_MODE_MASK 0x000F 351*30f57471SLouis Su #define RGMII_COPPER_MODE 0x000B 352*30f57471SLouis Su 353*30f57471SLouis Su /* CICADA CIS8201 Gigabit PHY Register Definition */ 354*30f57471SLouis Su #define CIS_IMR 0x0019 355*30f57471SLouis Su #define CIS_INT_ENABLE 0x8000 356*30f57471SLouis Su #define CIS_LINK_CHANGE_INT 0x2000 357*30f57471SLouis Su #define CIS_ISR 0x001A 358*30f57471SLouis Su #define CIS_INT_PENDING 0x8000 359*30f57471SLouis Su #define CIS_LINK_CHANGE_STATUS 0x2000 360*30f57471SLouis Su #define CIS_AUX_CTRL_STATUS 0x001C 361*30f57471SLouis Su #define CIS_AUTONEG_COMPLETE 0x8000 362*30f57471SLouis Su #define CIS_SPEED_MASK 0x0018 363*30f57471SLouis Su #define CIS_SPEED_1000 0x0010 364*30f57471SLouis Su #define CIS_SPEED_100 0x0008 365*30f57471SLouis Su #define CIS_SPEED_10 0x0000 366*30f57471SLouis Su #define CIS_DUPLEX 0x0020 367*30f57471SLouis Su 368*30f57471SLouis Su #define CIS_MEDIA_MASK (CIS_SPEED_MASK | CIS_DUPLEX) 369*30f57471SLouis Su #define CIS_1000FULL (CIS_SPEED_1000 | CIS_DUPLEX) 370*30f57471SLouis Su #define CIS_1000HALF CIS_SPEED_1000 371*30f57471SLouis Su #define CIS_100FULL (CIS_SPEED_100 | CIS_DUPLEX) 372*30f57471SLouis Su #define CIS_100HALF CIS_SPEED_100 373*30f57471SLouis Su #define CIS_10FULL (CIS_SPEED_10 | CIS_DUPLEX) 374*30f57471SLouis Su #define CIS_10HALF CIS_SPEED_10 375*30f57471SLouis Su #define CIS_SMI_PRIORITY 0x0004 376*30f57471SLouis Su 377*30f57471SLouis Su static inline unsigned short INW (struct eth_device *dev, unsigned long addr) 378*30f57471SLouis Su { 379*30f57471SLouis Su return le16_to_cpu (*(volatile unsigned short *) (addr + dev->iobase)); 380*30f57471SLouis Su } 381*30f57471SLouis Su 382*30f57471SLouis Su static inline void OUTW (struct eth_device *dev, unsigned short command, unsigned long addr) 383*30f57471SLouis Su { 384*30f57471SLouis Su *(volatile unsigned short *) ((addr + dev->iobase)) = cpu_to_le16 (command); 385*30f57471SLouis Su } 386*30f57471SLouis Su 387*30f57471SLouis Su /* 388*30f57471SLouis Su Access RXBUFFER_START/TXBUFFER_START to read RX buffer/write TX buffer 389*30f57471SLouis Su */ 390*30f57471SLouis Su #if defined (CONFIG_DRIVER_AX88180_16BIT) 391*30f57471SLouis Su static inline unsigned short READ_RXBUF (struct eth_device *dev) 392*30f57471SLouis Su { 393*30f57471SLouis Su return le16_to_cpu (*(volatile unsigned short *) (RXBUFFER_START + dev->iobase)); 394*30f57471SLouis Su } 395*30f57471SLouis Su 396*30f57471SLouis Su static inline void WRITE_TXBUF (struct eth_device *dev, unsigned short data) 397*30f57471SLouis Su { 398*30f57471SLouis Su *(volatile unsigned short *) ((TXBUFFER_START + dev->iobase)) = cpu_to_le16 (data); 399*30f57471SLouis Su } 400*30f57471SLouis Su #else 401*30f57471SLouis Su static inline unsigned long READ_RXBUF (struct eth_device *dev) 402*30f57471SLouis Su { 403*30f57471SLouis Su return le32_to_cpu (*(volatile unsigned long *) (RXBUFFER_START + dev->iobase)); 404*30f57471SLouis Su } 405*30f57471SLouis Su 406*30f57471SLouis Su static inline void WRITE_TXBUF (struct eth_device *dev, unsigned long data) 407*30f57471SLouis Su { 408*30f57471SLouis Su *(volatile unsigned long *) ((TXBUFFER_START + dev->iobase)) = cpu_to_le32 (data); 409*30f57471SLouis Su } 410*30f57471SLouis Su #endif 411*30f57471SLouis Su 412*30f57471SLouis Su #endif /* _AX88180_H_ */ 413