1 /* 2 * Copyright (C) 2009 BuS Elektronik GmbH & Co. KG 3 * Jens Scharsig (esw@bus-elektronik.de) 4 * 5 * (C) Copyright 2003 6 * Author : Hamid Ikdoumi (Atmel) 7 8 * See file CREDITS for list of people who contributed to this 9 * project. 10 * 11 * This program is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License as 13 * published by the Free Software Foundation; either version 2 of 14 * the License, or (at your option) any later version. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program; if not, write to the Free Software 23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 24 * MA 02111-1307 USA 25 */ 26 27 #include <common.h> 28 #include <asm/io.h> 29 #ifndef CONFIG_AT91_LEGACY 30 #include <asm/arch/hardware.h> 31 #include <asm/arch/at91_emac.h> 32 #include <asm/arch/at91_pmc.h> 33 #include <asm/arch/at91_pio.h> 34 #else 35 /* remove next 5 lines, if all RM9200 boards convert to at91 arch */ 36 #include <asm/arch-at91/at91rm9200.h> 37 #include <asm/arch-at91/hardware.h> 38 #include <asm/arch-at91/at91_emac.h> 39 #include <asm/arch-at91/at91_pmc.h> 40 #include <asm/arch-at91/at91_pio.h> 41 #endif 42 #include <net.h> 43 #include <netdev.h> 44 #include <malloc.h> 45 #include <miiphy.h> 46 #include <linux/mii.h> 47 48 #undef MII_DEBUG 49 #undef ET_DEBUG 50 51 #if (CONFIG_SYS_RX_ETH_BUFFER > 1024) 52 #error AT91 EMAC supports max 1024 RX buffers. \ 53 Please decrease the CONFIG_SYS_RX_ETH_BUFFER value 54 #endif 55 56 #ifndef CONFIG_DRIVER_AT91EMAC_PHYADDR 57 #define CONFIG_DRIVER_AT91EMAC_PHYADDR 0 58 #endif 59 60 /* MDIO clock must not exceed 2.5 MHz, so enable MCK divider */ 61 #if (AT91C_MASTER_CLOCK > 80000000) 62 #define HCLK_DIV AT91_EMAC_CFG_MCLK_64 63 #elif (AT91C_MASTER_CLOCK > 40000000) 64 #define HCLK_DIV AT91_EMAC_CFG_MCLK_32 65 #elif (AT91C_MASTER_CLOCK > 20000000) 66 #define HCLK_DIV AT91_EMAC_CFG_MCLK_16 67 #else 68 #define HCLK_DIV AT91_EMAC_CFG_MCLK_8 69 #endif 70 71 #ifdef ET_DEBUG 72 #define DEBUG_AT91EMAC(...) printf(__VA_ARGS__); 73 #else 74 #define DEBUG_AT91EMAC(...) 75 #endif 76 77 #ifdef MII_DEBUG 78 #define DEBUG_AT91PHY(...) printf(__VA_ARGS__); 79 #else 80 #define DEBUG_AT91PHY(...) 81 #endif 82 83 #ifndef CONFIG_DRIVER_AT91EMAC_QUIET 84 #define VERBOSEP(...) printf(__VA_ARGS__); 85 #else 86 #define VERBOSEP(...) 87 #endif 88 89 #define RBF_ADDR 0xfffffffc 90 #define RBF_OWNER (1<<0) 91 #define RBF_WRAP (1<<1) 92 #define RBF_BROADCAST (1<<31) 93 #define RBF_MULTICAST (1<<30) 94 #define RBF_UNICAST (1<<29) 95 #define RBF_EXTERNAL (1<<28) 96 #define RBF_UNKNOWN (1<<27) 97 #define RBF_SIZE 0x07ff 98 #define RBF_LOCAL4 (1<<26) 99 #define RBF_LOCAL3 (1<<25) 100 #define RBF_LOCAL2 (1<<24) 101 #define RBF_LOCAL1 (1<<23) 102 103 #define RBF_FRAMEMAX CONFIG_SYS_RX_ETH_BUFFER 104 #define RBF_FRAMELEN 0x600 105 106 typedef struct { 107 unsigned long addr, size; 108 } rbf_t; 109 110 typedef struct { 111 rbf_t rbfdt[RBF_FRAMEMAX]; 112 unsigned long rbindex; 113 } emac_device; 114 115 void at91emac_EnableMDIO(at91_emac_t *at91mac) 116 { 117 /* Mac CTRL reg set for MDIO enable */ 118 writel(readl(&at91mac->ctl) | AT91_EMAC_CTL_MPE, &at91mac->ctl); 119 } 120 121 void at91emac_DisableMDIO(at91_emac_t *at91mac) 122 { 123 /* Mac CTRL reg set for MDIO disable */ 124 writel(readl(&at91mac->ctl) & ~AT91_EMAC_CTL_MPE, &at91mac->ctl); 125 } 126 127 int at91emac_read(at91_emac_t *at91mac, unsigned char addr, 128 unsigned char reg, unsigned short *value) 129 { 130 unsigned long netstat; 131 at91emac_EnableMDIO(at91mac); 132 133 writel(AT91_EMAC_MAN_HIGH | AT91_EMAC_MAN_RW_R | 134 AT91_EMAC_MAN_REGA(reg) | AT91_EMAC_MAN_CODE_802_3 | 135 AT91_EMAC_MAN_PHYA(addr), 136 &at91mac->man); 137 138 do { 139 netstat = readl(&at91mac->sr); 140 DEBUG_AT91PHY("poll SR %08lx\n", netstat); 141 } while (!(netstat & AT91_EMAC_SR_IDLE)); 142 143 *value = readl(&at91mac->man) & AT91_EMAC_MAN_DATA_MASK; 144 145 at91emac_DisableMDIO(at91mac); 146 147 DEBUG_AT91PHY("AT91PHY read %x REG(%d)=%x\n", at91mac, reg, *value) 148 149 return 0; 150 } 151 152 int at91emac_write(at91_emac_t *at91mac, unsigned char addr, 153 unsigned char reg, unsigned short value) 154 { 155 unsigned long netstat; 156 DEBUG_AT91PHY("AT91PHY write %x REG(%d)=%x\n", at91mac, reg, &value) 157 158 at91emac_EnableMDIO(at91mac); 159 160 writel(AT91_EMAC_MAN_HIGH | AT91_EMAC_MAN_RW_W | 161 AT91_EMAC_MAN_REGA(reg) | AT91_EMAC_MAN_CODE_802_3 | 162 AT91_EMAC_MAN_PHYA(addr) | (value & AT91_EMAC_MAN_DATA_MASK), 163 &at91mac->man); 164 165 do { 166 netstat = readl(&at91mac->sr); 167 DEBUG_AT91PHY("poll SR %08lx\n", netstat); 168 } while (!(netstat & AT91_EMAC_SR_IDLE)); 169 170 at91emac_DisableMDIO(at91mac); 171 172 return 0; 173 } 174 175 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) 176 177 at91_emac_t *get_emacbase_by_name(const char *devname) 178 { 179 struct eth_device *netdev; 180 181 netdev = eth_get_dev_by_name(devname); 182 return (at91_emac_t *) netdev->iobase; 183 } 184 185 int at91emac_mii_read(const char *devname, unsigned char addr, 186 unsigned char reg, unsigned short *value) 187 { 188 at91_emac_t *emac; 189 190 emac = get_emacbase_by_name(devname); 191 at91emac_read(emac , addr, reg, value); 192 return 0; 193 } 194 195 196 int at91emac_mii_write(const char *devname, unsigned char addr, 197 unsigned char reg, unsigned short value) 198 { 199 at91_emac_t *emac; 200 201 emac = get_emacbase_by_name(devname); 202 at91emac_write(emac, addr, reg, value); 203 return 0; 204 } 205 206 #endif 207 208 static int at91emac_phy_reset(struct eth_device *netdev) 209 { 210 int i; 211 u16 status, adv; 212 at91_emac_t *emac; 213 214 emac = (at91_emac_t *) netdev->iobase; 215 216 adv = ADVERTISE_CSMA | ADVERTISE_ALL; 217 at91emac_write(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR, 218 MII_ADVERTISE, adv); 219 VERBOSEP("%s: Starting autonegotiation...\n", netdev->name); 220 at91emac_write(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR, MII_BMCR, 221 (BMCR_ANENABLE | BMCR_ANRESTART)); 222 223 for (i = 0; i < 30000; i++) { 224 at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR, 225 MII_BMSR, &status); 226 if (status & BMSR_ANEGCOMPLETE) 227 break; 228 udelay(100); 229 } 230 231 if (status & BMSR_ANEGCOMPLETE) { 232 VERBOSEP("%s: Autonegotiation complete\n", netdev->name); 233 } else { 234 printf("%s: Autonegotiation timed out (status=0x%04x)\n", 235 netdev->name, status); 236 return -1; 237 } 238 return 0; 239 } 240 241 static int at91emac_phy_init(struct eth_device *netdev) 242 { 243 u16 phy_id, status, adv, lpa; 244 int media, speed, duplex; 245 int i; 246 at91_emac_t *emac; 247 248 emac = (at91_emac_t *) netdev->iobase; 249 250 /* Check if the PHY is up to snuff... */ 251 at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR, 252 MII_PHYSID1, &phy_id); 253 if (phy_id == 0xffff) { 254 printf("%s: No PHY present\n", netdev->name); 255 return -1; 256 } 257 258 at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR, 259 MII_BMSR, &status); 260 261 if (!(status & BMSR_LSTATUS)) { 262 /* Try to re-negotiate if we don't have link already. */ 263 if (at91emac_phy_reset(netdev)) 264 return -2; 265 266 for (i = 0; i < 100000 / 100; i++) { 267 at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR, 268 MII_BMSR, &status); 269 if (status & BMSR_LSTATUS) 270 break; 271 udelay(100); 272 } 273 } 274 if (!(status & BMSR_LSTATUS)) { 275 VERBOSEP("%s: link down\n", netdev->name); 276 return -3; 277 } else { 278 at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR, 279 MII_ADVERTISE, &adv); 280 at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR, 281 MII_LPA, &lpa); 282 media = mii_nway_result(lpa & adv); 283 speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF) 284 ? 1 : 0); 285 duplex = (media & ADVERTISE_FULL) ? 1 : 0; 286 VERBOSEP("%s: link up, %sMbps %s-duplex\n", 287 netdev->name, 288 speed ? "100" : "10", 289 duplex ? "full" : "half"); 290 } 291 return 0; 292 } 293 294 int at91emac_UpdateLinkSpeed(at91_emac_t *emac) 295 { 296 unsigned short stat1; 297 298 at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR, MII_BMSR, &stat1); 299 300 if (!(stat1 & BMSR_LSTATUS)) /* link status up? */ 301 return -1; 302 303 if (stat1 & BMSR_100FULL) { 304 /*set Emac for 100BaseTX and Full Duplex */ 305 writel(readl(&emac->cfg) | 306 AT91_EMAC_CFG_SPD | AT91_EMAC_CFG_FD, 307 &emac->cfg); 308 return 0; 309 } 310 311 if (stat1 & BMSR_10FULL) { 312 /*set MII for 10BaseT and Full Duplex */ 313 writel((readl(&emac->cfg) & 314 ~(AT91_EMAC_CFG_SPD | AT91_EMAC_CFG_FD) 315 ) | AT91_EMAC_CFG_FD, 316 &emac->cfg); 317 return 0; 318 } 319 320 if (stat1 & BMSR_100HALF) { 321 /*set MII for 100BaseTX and Half Duplex */ 322 writel((readl(&emac->cfg) & 323 ~(AT91_EMAC_CFG_SPD | AT91_EMAC_CFG_FD) 324 ) | AT91_EMAC_CFG_SPD, 325 &emac->cfg); 326 return 0; 327 } 328 329 if (stat1 & BMSR_10HALF) { 330 /*set MII for 10BaseT and Half Duplex */ 331 writel((readl(&emac->cfg) & 332 ~(AT91_EMAC_CFG_SPD | AT91_EMAC_CFG_FD)), 333 &emac->cfg); 334 return 0; 335 } 336 return 0; 337 } 338 339 static int at91emac_init(struct eth_device *netdev, bd_t *bd) 340 { 341 int i; 342 u32 value; 343 emac_device *dev; 344 at91_emac_t *emac; 345 at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO; 346 at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; 347 348 emac = (at91_emac_t *) netdev->iobase; 349 dev = (emac_device *) netdev->priv; 350 351 /* PIO Disable Register */ 352 value = ATMEL_PMX_AA_EMDIO | ATMEL_PMX_AA_EMDC | 353 ATMEL_PMX_AA_ERXER | ATMEL_PMX_AA_ERX1 | 354 ATMEL_PMX_AA_ERX0 | ATMEL_PMX_AA_ECRS | 355 ATMEL_PMX_AA_ETX1 | ATMEL_PMX_AA_ETX0 | 356 ATMEL_PMX_AA_ETXEN | ATMEL_PMX_AA_EREFCK; 357 358 writel(value, &pio->pioa.pdr); 359 writel(value, &pio->pioa.asr); 360 361 #ifdef CONFIG_RMII 362 value = ATMEL_PMX_BA_ERXCK; 363 #else 364 value = ATMEL_PMX_BA_ERXCK | ATMEL_PMX_BA_ECOL | 365 ATMEL_PMX_BA_ERXDV | ATMEL_PMX_BA_ERX3 | 366 ATMEL_PMX_BA_ERX2 | ATMEL_PMX_BA_ETXER | 367 ATMEL_PMX_BA_ETX3 | ATMEL_PMX_BA_ETX2; 368 #endif 369 writel(value, &pio->piob.pdr); 370 writel(value, &pio->piob.bsr); 371 372 writel(1 << ATMEL_ID_EMAC, &pmc->pcer); 373 writel(readl(&emac->ctl) | AT91_EMAC_CTL_CSR, &emac->ctl); 374 375 /* Init Ethernet buffers */ 376 for (i = 0; i < RBF_FRAMEMAX; i++) { 377 dev->rbfdt[i].addr = (unsigned long) NetRxPackets[i]; 378 dev->rbfdt[i].size = 0; 379 } 380 dev->rbfdt[RBF_FRAMEMAX - 1].addr |= RBF_WRAP; 381 dev->rbindex = 0; 382 writel((u32) &(dev->rbfdt[0]), &emac->rbqp); 383 384 writel(readl(&emac->rsr) & 385 ~(AT91_EMAC_RSR_OVR | AT91_EMAC_RSR_REC | AT91_EMAC_RSR_BNA), 386 &emac->rsr); 387 388 value = AT91_EMAC_CFG_CAF | AT91_EMAC_CFG_NBC | 389 HCLK_DIV; 390 #ifdef CONFIG_RMII 391 value |= AT91_EMAC_CFG_RMII; 392 #endif 393 writel(value, &emac->cfg); 394 395 writel(readl(&emac->ctl) | AT91_EMAC_CTL_TE | AT91_EMAC_CTL_RE, 396 &emac->ctl); 397 398 if (!at91emac_phy_init(netdev)) { 399 at91emac_UpdateLinkSpeed(emac); 400 return 0; 401 } 402 return -1; 403 } 404 405 static void at91emac_halt(struct eth_device *netdev) 406 { 407 at91_emac_t *emac; 408 409 emac = (at91_emac_t *) netdev->iobase; 410 writel(readl(&emac->ctl) & ~(AT91_EMAC_CTL_TE | AT91_EMAC_CTL_RE), 411 &emac->ctl); 412 DEBUG_AT91EMAC("halt MAC\n"); 413 } 414 415 static int at91emac_send(struct eth_device *netdev, volatile void *packet, 416 int length) 417 { 418 at91_emac_t *emac; 419 420 emac = (at91_emac_t *) netdev->iobase; 421 422 while (!(readl(&emac->tsr) & AT91_EMAC_TSR_BNQ)) 423 ; 424 writel((u32) packet, &emac->tar); 425 writel(AT91_EMAC_TCR_LEN(length), &emac->tcr); 426 while (AT91_EMAC_TCR_LEN(readl(&emac->tcr))) 427 ; 428 DEBUG_AT91EMAC("Send %d \n", length); 429 writel(readl(&emac->tsr) | AT91_EMAC_TSR_COMP, &emac->tsr); 430 return 0; 431 } 432 433 static int at91emac_recv(struct eth_device *netdev) 434 { 435 emac_device *dev; 436 at91_emac_t *emac; 437 rbf_t *rbfp; 438 int size; 439 440 emac = (at91_emac_t *) netdev->iobase; 441 dev = (emac_device *) netdev->priv; 442 443 rbfp = &dev->rbfdt[dev->rbindex]; 444 while (rbfp->addr & RBF_OWNER) { 445 size = rbfp->size & RBF_SIZE; 446 NetReceive(NetRxPackets[dev->rbindex], size); 447 448 DEBUG_AT91EMAC("Recv[%d]: %d bytes @ %x \n", 449 dev->rbindex, size, rbfp->addr); 450 451 rbfp->addr &= ~RBF_OWNER; 452 rbfp->size = 0; 453 if (dev->rbindex < (RBF_FRAMEMAX-1)) 454 dev->rbindex++; 455 else 456 dev->rbindex = 0; 457 458 rbfp = &(dev->rbfdt[dev->rbindex]); 459 if (!(rbfp->addr & RBF_OWNER)) 460 writel(readl(&emac->rsr) | AT91_EMAC_RSR_REC, 461 &emac->rsr); 462 } 463 464 if (readl(&emac->isr) & AT91_EMAC_IxR_RBNA) { 465 /* EMAC silicon bug 41.3.1 workaround 1 */ 466 writel(readl(&emac->ctl) & ~AT91_EMAC_CTL_RE, &emac->ctl); 467 writel(readl(&emac->ctl) | AT91_EMAC_CTL_RE, &emac->ctl); 468 dev->rbindex = 0; 469 printf("%s: reset receiver (EMAC dead lock bug)\n", 470 netdev->name); 471 } 472 return 0; 473 } 474 475 static int at91emac_write_hwaddr(struct eth_device *netdev) 476 { 477 emac_device *dev; 478 at91_emac_t *emac; 479 at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; 480 emac = (at91_emac_t *) netdev->iobase; 481 dev = (emac_device *) netdev->priv; 482 483 writel(1 << ATMEL_ID_EMAC, &pmc->pcer); 484 DEBUG_AT91EMAC("init MAC-ADDR %02x:%02x:%02x:%02x:%02x:%02x\n", 485 netdev->enetaddr[5], netdev->enetaddr[4], netdev->enetaddr[3], 486 netdev->enetaddr[2], netdev->enetaddr[1], netdev->enetaddr[0]); 487 writel( (netdev->enetaddr[0] | netdev->enetaddr[1] << 8 | 488 netdev->enetaddr[2] << 16 | netdev->enetaddr[3] << 24), 489 &emac->sa2l); 490 writel((netdev->enetaddr[4] | netdev->enetaddr[5] << 8), &emac->sa2h); 491 DEBUG_AT91EMAC("init MAC-ADDR %x%x \n", 492 readl(&emac->sa2h), readl(&emac->sa2l)); 493 return 0; 494 } 495 496 int at91emac_register(bd_t *bis, unsigned long iobase) 497 { 498 emac_device *emac; 499 emac_device *emacfix; 500 struct eth_device *dev; 501 502 if (iobase == 0) 503 iobase = ATMEL_BASE_EMAC; 504 emac = malloc(sizeof(*emac)+512); 505 if (emac == NULL) 506 return -1; 507 dev = malloc(sizeof(*dev)); 508 if (dev == NULL) { 509 free(emac); 510 return -1; 511 } 512 /* alignment as per Errata (64 bytes) is insufficient! */ 513 emacfix = (emac_device *) (((unsigned long) emac + 0x1ff) & 0xFFFFFE00); 514 memset(emacfix, 0, sizeof(emac_device)); 515 516 memset(dev, 0, sizeof(*dev)); 517 sprintf(dev->name, "emac"); 518 dev->iobase = iobase; 519 dev->priv = emacfix; 520 dev->init = at91emac_init; 521 dev->halt = at91emac_halt; 522 dev->send = at91emac_send; 523 dev->recv = at91emac_recv; 524 dev->write_hwaddr = at91emac_write_hwaddr; 525 526 eth_register(dev); 527 528 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) 529 miiphy_register(dev->name, at91emac_mii_read, at91emac_mii_write); 530 #endif 531 return 1; 532 } 533