1 /* 2 * Copyright (C) 2009 BuS Elektronik GmbH & Co. KG 3 * Jens Scharsig (esw@bus-elektronik.de) 4 * 5 * (C) Copyright 2003 6 * Author : Hamid Ikdoumi (Atmel) 7 8 * See file CREDITS for list of people who contributed to this 9 * project. 10 * 11 * This program is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License as 13 * published by the Free Software Foundation; either version 2 of 14 * the License, or (at your option) any later version. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program; if not, write to the Free Software 23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 24 * MA 02111-1307 USA 25 */ 26 27 #include <common.h> 28 #include <asm/io.h> 29 #ifndef CONFIG_AT91_LEGACY 30 #include <asm/arch/hardware.h> 31 #include <asm/arch/at91_emac.h> 32 #include <asm/arch/at91_pmc.h> 33 #include <asm/arch/at91_pio.h> 34 #else 35 /* remove next 5 lines, if all RM9200 boards convert to at91 arch */ 36 #include <asm/arch-at91/at91rm9200.h> 37 #include <asm/arch-at91/hardware.h> 38 #include <asm/arch-at91/at91_emac.h> 39 #include <asm/arch-at91/at91_pmc.h> 40 #include <asm/arch-at91/at91_pio.h> 41 #endif 42 #include <net.h> 43 #include <netdev.h> 44 #include <malloc.h> 45 #include <miiphy.h> 46 #include <linux/mii.h> 47 48 #undef MII_DEBUG 49 #undef ET_DEBUG 50 51 #if (CONFIG_SYS_RX_ETH_BUFFER > 1024) 52 #error AT91 EMAC supports max 1024 RX buffers. \ 53 Please decrease the CONFIG_SYS_RX_ETH_BUFFER value 54 #endif 55 56 #ifndef CONFIG_DRIVER_AT91EMAC_PHYADDR 57 #define CONFIG_DRIVER_AT91EMAC_PHYADDR 0 58 #endif 59 60 /* MDIO clock must not exceed 2.5 MHz, so enable MCK divider */ 61 #if (AT91C_MASTER_CLOCK > 80000000) 62 #define HCLK_DIV AT91_EMAC_CFG_MCLK_64 63 #elif (AT91C_MASTER_CLOCK > 40000000) 64 #define HCLK_DIV AT91_EMAC_CFG_MCLK_32 65 #elif (AT91C_MASTER_CLOCK > 20000000) 66 #define HCLK_DIV AT91_EMAC_CFG_MCLK_16 67 #else 68 #define HCLK_DIV AT91_EMAC_CFG_MCLK_8 69 #endif 70 71 #ifdef ET_DEBUG 72 #define DEBUG_AT91EMAC(...) printf(__VA_ARGS__); 73 #else 74 #define DEBUG_AT91EMAC(...) 75 #endif 76 77 #ifdef MII_DEBUG 78 #define DEBUG_AT91PHY(...) printf(__VA_ARGS__); 79 #else 80 #define DEBUG_AT91PHY(...) 81 #endif 82 83 #ifndef CONFIG_DRIVER_AT91EMAC_QUIET 84 #define VERBOSEP(...) printf(__VA_ARGS__); 85 #else 86 #define VERBOSEP(...) 87 #endif 88 89 #define RBF_ADDR 0xfffffffc 90 #define RBF_OWNER (1<<0) 91 #define RBF_WRAP (1<<1) 92 #define RBF_BROADCAST (1<<31) 93 #define RBF_MULTICAST (1<<30) 94 #define RBF_UNICAST (1<<29) 95 #define RBF_EXTERNAL (1<<28) 96 #define RBF_UNKOWN (1<<27) 97 #define RBF_SIZE 0x07ff 98 #define RBF_LOCAL4 (1<<26) 99 #define RBF_LOCAL3 (1<<25) 100 #define RBF_LOCAL2 (1<<24) 101 #define RBF_LOCAL1 (1<<23) 102 103 #define RBF_FRAMEMAX CONFIG_SYS_RX_ETH_BUFFER 104 #define RBF_FRAMELEN 0x600 105 106 typedef struct { 107 unsigned long addr, size; 108 } rbf_t; 109 110 typedef struct { 111 rbf_t rbfdt[RBF_FRAMEMAX]; 112 unsigned long rbindex; 113 } emac_device; 114 115 void at91emac_EnableMDIO(at91_emac_t *at91mac) 116 { 117 /* Mac CTRL reg set for MDIO enable */ 118 writel(readl(&at91mac->ctl) | AT91_EMAC_CTL_MPE, &at91mac->ctl); 119 } 120 121 void at91emac_DisableMDIO(at91_emac_t *at91mac) 122 { 123 /* Mac CTRL reg set for MDIO disable */ 124 writel(readl(&at91mac->ctl) & ~AT91_EMAC_CTL_MPE, &at91mac->ctl); 125 } 126 127 int at91emac_read(at91_emac_t *at91mac, unsigned char addr, 128 unsigned char reg, unsigned short *value) 129 { 130 at91emac_EnableMDIO(at91mac); 131 132 writel(AT91_EMAC_MAN_HIGH | AT91_EMAC_MAN_RW_R | 133 AT91_EMAC_MAN_REGA(reg) | AT91_EMAC_MAN_CODE_802_3 | 134 AT91_EMAC_MAN_PHYA(addr), 135 &at91mac->man); 136 udelay(10000); 137 *value = readl(&at91mac->man) & AT91_EMAC_MAN_DATA_MASK; 138 139 at91emac_DisableMDIO(at91mac); 140 141 DEBUG_AT91PHY("AT91PHY read %x REG(%d)=%x\n", at91mac, reg, *value) 142 143 return 0; 144 } 145 146 int at91emac_write(at91_emac_t *at91mac, unsigned char addr, 147 unsigned char reg, unsigned short value) 148 { 149 DEBUG_AT91PHY("AT91PHY write %x REG(%d)=%x\n", at91mac, reg, &value) 150 151 at91emac_EnableMDIO(at91mac); 152 153 writel(AT91_EMAC_MAN_HIGH | AT91_EMAC_MAN_RW_W | 154 AT91_EMAC_MAN_REGA(reg) | AT91_EMAC_MAN_CODE_802_3 | 155 AT91_EMAC_MAN_PHYA(addr) | (value & AT91_EMAC_MAN_DATA_MASK), 156 &at91mac->man); 157 udelay(10000); 158 159 at91emac_DisableMDIO(at91mac); 160 return 0; 161 } 162 163 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) 164 165 at91_emac_t *get_emacbase_by_name(const char *devname) 166 { 167 struct eth_device *netdev; 168 169 netdev = eth_get_dev_by_name(devname); 170 return (at91_emac_t *) netdev->iobase; 171 } 172 173 int at91emac_mii_read(const char *devname, unsigned char addr, 174 unsigned char reg, unsigned short *value) 175 { 176 at91_emac_t *emac; 177 178 emac = get_emacbase_by_name(devname); 179 at91emac_read(emac , addr, reg, value); 180 return 0; 181 } 182 183 184 int at91emac_mii_write(const char *devname, unsigned char addr, 185 unsigned char reg, unsigned short value) 186 { 187 at91_emac_t *emac; 188 189 emac = get_emacbase_by_name(devname); 190 at91emac_write(emac, addr, reg, value); 191 return 0; 192 } 193 194 #endif 195 196 static int at91emac_phy_reset(struct eth_device *netdev) 197 { 198 int i; 199 u16 status, adv; 200 at91_emac_t *emac; 201 202 emac = (at91_emac_t *) netdev->iobase; 203 204 adv = ADVERTISE_CSMA | ADVERTISE_ALL; 205 at91emac_write(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR, 206 MII_ADVERTISE, adv); 207 VERBOSEP("%s: Starting autonegotiation...\n", netdev->name); 208 at91emac_write(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR, MII_BMCR, 209 (BMCR_ANENABLE | BMCR_ANRESTART)); 210 211 for (i = 0; i < 100000 / 100; i++) { 212 at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR, 213 MII_BMSR, &status); 214 if (status & BMSR_ANEGCOMPLETE) 215 break; 216 udelay(100); 217 } 218 219 if (status & BMSR_ANEGCOMPLETE) { 220 VERBOSEP("%s: Autonegotiation complete\n", netdev->name); 221 } else { 222 printf("%s: Autonegotiation timed out (status=0x%04x)\n", 223 netdev->name, status); 224 return 1; 225 } 226 return 0; 227 } 228 229 static int at91emac_phy_init(struct eth_device *netdev) 230 { 231 u16 phy_id, status, adv, lpa; 232 int media, speed, duplex; 233 int i; 234 at91_emac_t *emac; 235 236 emac = (at91_emac_t *) netdev->iobase; 237 238 /* Check if the PHY is up to snuff... */ 239 at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR, 240 MII_PHYSID1, &phy_id); 241 if (phy_id == 0xffff) { 242 printf("%s: No PHY present\n", netdev->name); 243 return 1; 244 } 245 246 at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR, 247 MII_BMSR, &status); 248 249 if (!(status & BMSR_LSTATUS)) { 250 /* Try to re-negotiate if we don't have link already. */ 251 if (at91emac_phy_reset(netdev)) 252 return 2; 253 254 for (i = 0; i < 100000 / 100; i++) { 255 at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR, 256 MII_BMSR, &status); 257 if (status & BMSR_LSTATUS) 258 break; 259 udelay(100); 260 } 261 } 262 if (!(status & BMSR_LSTATUS)) { 263 VERBOSEP("%s: link down\n", netdev->name); 264 return 3; 265 } else { 266 at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR, 267 MII_ADVERTISE, &adv); 268 at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR, 269 MII_LPA, &lpa); 270 media = mii_nway_result(lpa & adv); 271 speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF) 272 ? 1 : 0); 273 duplex = (media & ADVERTISE_FULL) ? 1 : 0; 274 VERBOSEP("%s: link up, %sMbps %s-duplex\n", 275 netdev->name, 276 speed ? "100" : "10", 277 duplex ? "full" : "half"); 278 } 279 return 0; 280 } 281 282 int at91emac_UpdateLinkSpeed(at91_emac_t *emac) 283 { 284 unsigned short stat1; 285 286 at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR, MII_BMSR, &stat1); 287 288 if (!(stat1 & BMSR_LSTATUS)) /* link status up? */ 289 return 1; 290 291 if (stat1 & BMSR_100FULL) { 292 /*set Emac for 100BaseTX and Full Duplex */ 293 writel(readl(&emac->cfg) | 294 AT91_EMAC_CFG_SPD | AT91_EMAC_CFG_FD, 295 &emac->cfg); 296 return 0; 297 } 298 299 if (stat1 & BMSR_10FULL) { 300 /*set MII for 10BaseT and Full Duplex */ 301 writel((readl(&emac->cfg) & 302 ~(AT91_EMAC_CFG_SPD | AT91_EMAC_CFG_FD) 303 ) | AT91_EMAC_CFG_FD, 304 &emac->cfg); 305 return 0; 306 } 307 308 if (stat1 & BMSR_100HALF) { 309 /*set MII for 100BaseTX and Half Duplex */ 310 writel((readl(&emac->cfg) & 311 ~(AT91_EMAC_CFG_SPD | AT91_EMAC_CFG_FD) 312 ) | AT91_EMAC_CFG_SPD, 313 &emac->cfg); 314 return 0; 315 } 316 317 if (stat1 & BMSR_10HALF) { 318 /*set MII for 10BaseT and Half Duplex */ 319 writel((readl(&emac->cfg) & 320 ~(AT91_EMAC_CFG_SPD | AT91_EMAC_CFG_FD)), 321 &emac->cfg); 322 return 0; 323 } 324 return 1; 325 } 326 327 static int at91emac_init(struct eth_device *netdev, bd_t *bd) 328 { 329 int i; 330 u32 value; 331 emac_device *dev; 332 at91_emac_t *emac; 333 at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE; 334 at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; 335 336 emac = (at91_emac_t *) netdev->iobase; 337 dev = (emac_device *) netdev->priv; 338 339 /* PIO Disable Register */ 340 value = AT91_PMX_AA_EMDIO | AT91_PMX_AA_EMDC | 341 AT91_PMX_AA_ERXER | AT91_PMX_AA_ERX1 | 342 AT91_PMX_AA_ERX0 | AT91_PMX_AA_ECRS | 343 AT91_PMX_AA_ETX1 | AT91_PMX_AA_ETX0 | 344 AT91_PMX_AA_ETXEN | AT91_PMX_AA_EREFCK; 345 346 writel(value, &pio->pioa.pdr); 347 writel(value, &pio->pioa.asr); 348 349 #ifdef CONFIG_RMII 350 value = AT91_PMX_BA_ERXCK; 351 #else 352 value = AT91_PMX_BA_ERXCK | AT91_PMX_BA_ECOL | 353 AT91_PMX_BA_ERXDV | AT91_PMX_BA_ERX3 | 354 AT91_PMX_BA_ERX2 | AT91_PMX_BA_ETXER | 355 AT91_PMX_BA_ETX3 | AT91_PMX_BA_ETX2; 356 #endif 357 writel(value, &pio->piob.pdr); 358 writel(value, &pio->piob.bsr); 359 360 writel(1 << AT91_ID_EMAC, &pmc->pcer); 361 writel(readl(&emac->ctl) | AT91_EMAC_CTL_CSR, &emac->ctl); 362 363 /* Init Ethernet buffers */ 364 for (i = 0; i < RBF_FRAMEMAX; i++) { 365 dev->rbfdt[i].addr = (unsigned long) NetRxPackets[i]; 366 dev->rbfdt[i].size = 0; 367 } 368 dev->rbfdt[RBF_FRAMEMAX - 1].addr |= RBF_WRAP; 369 dev->rbindex = 0; 370 writel((u32) &(dev->rbfdt[0]), &emac->rbqp); 371 372 writel(readl(&emac->rsr) & 373 ~(AT91_EMAC_RSR_OVR | AT91_EMAC_RSR_REC | AT91_EMAC_RSR_BNA), 374 &emac->rsr); 375 376 value = AT91_EMAC_CFG_CAF | AT91_EMAC_CFG_NBC | 377 HCLK_DIV; 378 #ifdef CONFIG_RMII 379 value |= AT91_EMAC_CFG_RMII; 380 #endif 381 writel(value, &emac->cfg); 382 383 writel(readl(&emac->ctl) | AT91_EMAC_CTL_TE | AT91_EMAC_CTL_RE, 384 &emac->ctl); 385 386 if (!at91emac_phy_init(netdev)) { 387 at91emac_UpdateLinkSpeed(emac); 388 return 0; 389 } 390 return 1; 391 } 392 393 static void at91emac_halt(struct eth_device *netdev) 394 { 395 at91_emac_t *emac; 396 397 emac = (at91_emac_t *) netdev->iobase; 398 writel(readl(&emac->ctl) & ~(AT91_EMAC_CTL_TE | AT91_EMAC_CTL_RE), 399 &emac->ctl); 400 DEBUG_AT91EMAC("halt MAC\n"); 401 } 402 403 static int at91emac_send(struct eth_device *netdev, volatile void *packet, 404 int length) 405 { 406 at91_emac_t *emac; 407 408 emac = (at91_emac_t *) netdev->iobase; 409 410 while (!(readl(&emac->tsr) & AT91_EMAC_TSR_BNQ)) 411 ; 412 writel((u32) packet, &emac->tar); 413 writel(AT91_EMAC_TCR_LEN(length), &emac->tcr); 414 while (AT91_EMAC_TCR_LEN(readl(&emac->tcr))) 415 ; 416 DEBUG_AT91EMAC("Send %d \n", length); 417 writel(readl(&emac->tsr) | AT91_EMAC_TSR_COMP, &emac->tsr); 418 return 0; 419 } 420 421 static int at91emac_recv(struct eth_device *netdev) 422 { 423 emac_device *dev; 424 at91_emac_t *emac; 425 rbf_t *rbfp; 426 int size; 427 428 emac = (at91_emac_t *) netdev->iobase; 429 dev = (emac_device *) netdev->priv; 430 431 rbfp = &dev->rbfdt[dev->rbindex]; 432 while (rbfp->addr & RBF_OWNER) { 433 size = rbfp->size & RBF_SIZE; 434 NetReceive(NetRxPackets[dev->rbindex], size); 435 436 DEBUG_AT91EMAC("Recv[%d]: %d bytes @ %x \n", 437 dev->rbindex, size, rbfp->addr); 438 439 rbfp->addr &= ~RBF_OWNER; 440 rbfp->size = 0; 441 if (dev->rbindex < (RBF_FRAMEMAX-1)) 442 dev->rbindex++; 443 else 444 dev->rbindex = 0; 445 446 rbfp = &(dev->rbfdt[dev->rbindex]); 447 if (!(rbfp->addr & RBF_OWNER)) 448 writel(readl(&emac->rsr) | AT91_EMAC_RSR_REC, 449 &emac->rsr); 450 } 451 452 if (readl(&emac->isr) & AT91_EMAC_IxR_RBNA) { 453 /* EMAC silicon bug 41.3.1 workaround 1 */ 454 writel(readl(&emac->ctl) & ~AT91_EMAC_CTL_RE, &emac->ctl); 455 writel(readl(&emac->ctl) | AT91_EMAC_CTL_RE, &emac->ctl); 456 dev->rbindex = 0; 457 printf("%s: reset receiver (EMAC dead lock bug)\n", 458 netdev->name); 459 } 460 return 0; 461 } 462 463 static int at91emac_write_hwaddr(struct eth_device *netdev) 464 { 465 emac_device *dev; 466 at91_emac_t *emac; 467 at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; 468 emac = (at91_emac_t *) netdev->iobase; 469 dev = (emac_device *) netdev->priv; 470 471 writel(1 << AT91_ID_EMAC, &pmc->pcer); 472 DEBUG_AT91EMAC("init MAC-ADDR %x%x \n", 473 cpu_to_le16(*((u16 *)(netdev->enetaddr + 4))), 474 cpu_to_le32(*((u32 *)netdev->enetaddr))); 475 writel(cpu_to_le32(*((u32 *)netdev->enetaddr)), &emac->sa2l); 476 writel(cpu_to_le16(*((u16 *)(netdev->enetaddr + 4))), &emac->sa2h); 477 DEBUG_AT91EMAC("init MAC-ADDR %x%x \n", 478 readl(&emac->sa2h), readl(&emac->sa2l)); 479 return 0; 480 } 481 482 int at91emac_register(bd_t *bis, unsigned long iobase) 483 { 484 emac_device *emac; 485 emac_device *emacfix; 486 struct eth_device *dev; 487 488 if (iobase == 0) 489 iobase = AT91_EMAC_BASE; 490 emac = malloc(sizeof(*emac)+512); 491 if (emac == NULL) 492 return 1; 493 dev = malloc(sizeof(*dev)); 494 if (dev == NULL) { 495 free(emac); 496 return 1; 497 } 498 /* alignment as per Errata (64 bytes) is insufficient! */ 499 emacfix = (emac_device *) (((unsigned long) emac + 0x1ff) & 0xFFFFFE00); 500 memset(emacfix, 0, sizeof(emac_device)); 501 502 memset(dev, 0, sizeof(*dev)); 503 #ifndef CONFIG_RMII 504 sprintf(dev->name, "AT91 EMAC"); 505 #else 506 sprintf(dev->name, "AT91 EMAC RMII"); 507 #endif 508 dev->iobase = iobase; 509 dev->priv = emacfix; 510 dev->init = at91emac_init; 511 dev->halt = at91emac_halt; 512 dev->send = at91emac_send; 513 dev->recv = at91emac_recv; 514 dev->write_hwaddr = at91emac_write_hwaddr; 515 516 eth_register(dev); 517 518 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) 519 miiphy_register(dev->name, at91emac_mii_read, at91emac_mii_write); 520 #endif 521 return 1; 522 } 523