xref: /openbmc/u-boot/drivers/net/at91_emac.c (revision 1e52fea3)
1 /*
2  * Copyright (C) 2009 BuS Elektronik GmbH & Co. KG
3  * Jens Scharsig (esw@bus-elektronik.de)
4  *
5  * (C) Copyright 2003
6  * Author : Hamid Ikdoumi (Atmel)
7 
8  * See file CREDITS for list of people who contributed to this
9  * project.
10  *
11  * This program is free software; you can redistribute it and/or
12  * modify it under the terms of the GNU General Public License as
13  * published by the Free Software Foundation; either version 2 of
14  * the License, or (at your option) any later version.
15  *
16  * This program is distributed in the hope that it will be useful,
17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
19  * GNU General Public License for more details.
20  *
21  * You should have received a copy of the GNU General Public License
22  * along with this program; if not, write to the Free Software
23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24  * MA 02111-1307 USA
25  */
26 
27 #include <common.h>
28 #include <asm/io.h>
29 #ifndef CONFIG_AT91_LEGACY
30 #include <asm/arch/hardware.h>
31 #include <asm/arch/at91_emac.h>
32 #include <asm/arch/at91_pmc.h>
33 #include <asm/arch/at91_pio.h>
34 #else
35 /* remove next 5 lines, if all RM9200 boards convert to at91 arch */
36 #include <asm/arch-at91/at91rm9200.h>
37 #include <asm/arch-at91/hardware.h>
38 #include <asm/arch-at91/at91_emac.h>
39 #include <asm/arch-at91/at91_pmc.h>
40 #include <asm/arch-at91/at91_pio.h>
41 #endif
42 #include <net.h>
43 #include <netdev.h>
44 #include <malloc.h>
45 #include <miiphy.h>
46 #include <linux/mii.h>
47 
48 #undef MII_DEBUG
49 #undef ET_DEBUG
50 
51 #if (CONFIG_SYS_RX_ETH_BUFFER > 1024)
52 #error AT91 EMAC supports max 1024 RX buffers. \
53 	Please decrease the CONFIG_SYS_RX_ETH_BUFFER value
54 #endif
55 
56 #ifndef CONFIG_DRIVER_AT91EMAC_PHYADDR
57 #define CONFIG_DRIVER_AT91EMAC_PHYADDR	0
58 #endif
59 
60 /* MDIO clock must not exceed 2.5 MHz, so enable MCK divider */
61 #if (AT91C_MASTER_CLOCK > 80000000)
62 	#define HCLK_DIV	AT91_EMAC_CFG_MCLK_64
63 #elif (AT91C_MASTER_CLOCK > 40000000)
64 	#define HCLK_DIV	AT91_EMAC_CFG_MCLK_32
65 #elif (AT91C_MASTER_CLOCK > 20000000)
66 	#define HCLK_DIV	AT91_EMAC_CFG_MCLK_16
67 #else
68 	#define HCLK_DIV	AT91_EMAC_CFG_MCLK_8
69 #endif
70 
71 #ifdef ET_DEBUG
72 #define DEBUG_AT91EMAC	1
73 #else
74 #define DEBUG_AT91EMAC	0
75 #endif
76 
77 #ifdef MII_DEBUG
78 #define DEBUG_AT91PHY	1
79 #else
80 #define DEBUG_AT91PHY	0
81 #endif
82 
83 #ifndef CONFIG_DRIVER_AT91EMAC_QUIET
84 #define VERBOSEP	1
85 #else
86 #define VERBOSEP	0
87 #endif
88 
89 #define RBF_ADDR      0xfffffffc
90 #define RBF_OWNER     (1<<0)
91 #define RBF_WRAP      (1<<1)
92 #define RBF_BROADCAST (1<<31)
93 #define RBF_MULTICAST (1<<30)
94 #define RBF_UNICAST   (1<<29)
95 #define RBF_EXTERNAL  (1<<28)
96 #define RBF_UNKNOWN   (1<<27)
97 #define RBF_SIZE      0x07ff
98 #define RBF_LOCAL4    (1<<26)
99 #define RBF_LOCAL3    (1<<25)
100 #define RBF_LOCAL2    (1<<24)
101 #define RBF_LOCAL1    (1<<23)
102 
103 #define RBF_FRAMEMAX CONFIG_SYS_RX_ETH_BUFFER
104 #define RBF_FRAMELEN 0x600
105 
106 typedef struct {
107 	unsigned long addr, size;
108 } rbf_t;
109 
110 typedef struct {
111 	rbf_t 		rbfdt[RBF_FRAMEMAX];
112 	unsigned long	rbindex;
113 } emac_device;
114 
115 void at91emac_EnableMDIO(at91_emac_t *at91mac)
116 {
117 	/* Mac CTRL reg set for MDIO enable */
118 	writel(readl(&at91mac->ctl) | AT91_EMAC_CTL_MPE, &at91mac->ctl);
119 }
120 
121 void at91emac_DisableMDIO(at91_emac_t *at91mac)
122 {
123 	/* Mac CTRL reg set for MDIO disable */
124 	writel(readl(&at91mac->ctl) & ~AT91_EMAC_CTL_MPE, &at91mac->ctl);
125 }
126 
127 int  at91emac_read(at91_emac_t *at91mac, unsigned char addr,
128 		unsigned char reg, unsigned short *value)
129 {
130 	unsigned long netstat;
131 	at91emac_EnableMDIO(at91mac);
132 
133 	writel(AT91_EMAC_MAN_HIGH | AT91_EMAC_MAN_RW_R |
134 		AT91_EMAC_MAN_REGA(reg) | AT91_EMAC_MAN_CODE_802_3 |
135 		AT91_EMAC_MAN_PHYA(addr),
136 		&at91mac->man);
137 
138 	do {
139 		netstat = readl(&at91mac->sr);
140 		debug_cond(DEBUG_AT91PHY, "poll SR %08lx\n", netstat);
141 	} while (!(netstat & AT91_EMAC_SR_IDLE));
142 
143 	*value = readl(&at91mac->man) & AT91_EMAC_MAN_DATA_MASK;
144 
145 	at91emac_DisableMDIO(at91mac);
146 
147 	debug_cond(DEBUG_AT91PHY,
148 		"AT91PHY read %p REG(%d)=%x\n", at91mac, reg, *value);
149 
150 	return 0;
151 }
152 
153 int  at91emac_write(at91_emac_t *at91mac, unsigned char addr,
154 		unsigned char reg, unsigned short value)
155 {
156 	unsigned long netstat;
157 	debug_cond(DEBUG_AT91PHY,
158 		"AT91PHY write %p REG(%d)=%p\n", at91mac, reg, &value);
159 
160 	at91emac_EnableMDIO(at91mac);
161 
162 	writel(AT91_EMAC_MAN_HIGH | AT91_EMAC_MAN_RW_W |
163 		AT91_EMAC_MAN_REGA(reg) | AT91_EMAC_MAN_CODE_802_3 |
164 		AT91_EMAC_MAN_PHYA(addr) | (value & AT91_EMAC_MAN_DATA_MASK),
165 		&at91mac->man);
166 
167 	do {
168 		netstat = readl(&at91mac->sr);
169 		debug_cond(DEBUG_AT91PHY, "poll SR %08lx\n", netstat);
170 	} while (!(netstat & AT91_EMAC_SR_IDLE));
171 
172 	at91emac_DisableMDIO(at91mac);
173 
174 	return 0;
175 }
176 
177 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
178 
179 at91_emac_t *get_emacbase_by_name(const char *devname)
180 {
181 	struct eth_device *netdev;
182 
183 	netdev = eth_get_dev_by_name(devname);
184 	return (at91_emac_t *) netdev->iobase;
185 }
186 
187 int  at91emac_mii_read(const char *devname, unsigned char addr,
188 		unsigned char reg, unsigned short *value)
189 {
190 	at91_emac_t *emac;
191 
192 	emac = get_emacbase_by_name(devname);
193 	at91emac_read(emac , addr, reg, value);
194 	return 0;
195 }
196 
197 
198 int  at91emac_mii_write(const char *devname, unsigned char addr,
199 		unsigned char reg, unsigned short value)
200 {
201 	at91_emac_t *emac;
202 
203 	emac = get_emacbase_by_name(devname);
204 	at91emac_write(emac, addr, reg, value);
205 	return 0;
206 }
207 
208 #endif
209 
210 static int at91emac_phy_reset(struct eth_device *netdev)
211 {
212 	int i;
213 	u16 status, adv;
214 	at91_emac_t *emac;
215 
216 	emac = (at91_emac_t *) netdev->iobase;
217 
218 	adv = ADVERTISE_CSMA | ADVERTISE_ALL;
219 	at91emac_write(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR,
220 		MII_ADVERTISE, adv);
221 	debug_cond(VERBOSEP, "%s: Starting autonegotiation...\n", netdev->name);
222 	at91emac_write(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR, MII_BMCR,
223 		(BMCR_ANENABLE | BMCR_ANRESTART));
224 
225 	for (i = 0; i < 30000; i++) {
226 		at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR,
227 			MII_BMSR, &status);
228 		if (status & BMSR_ANEGCOMPLETE)
229 			break;
230 		udelay(100);
231 	}
232 
233 	if (status & BMSR_ANEGCOMPLETE) {
234 		debug_cond(VERBOSEP,
235 			"%s: Autonegotiation complete\n", netdev->name);
236 	} else {
237 		printf("%s: Autonegotiation timed out (status=0x%04x)\n",
238 		       netdev->name, status);
239 		return -1;
240 	}
241 	return 0;
242 }
243 
244 static int at91emac_phy_init(struct eth_device *netdev)
245 {
246 	u16 phy_id, status, adv, lpa;
247 	int media, speed, duplex;
248 	int i;
249 	at91_emac_t *emac;
250 
251 	emac = (at91_emac_t *) netdev->iobase;
252 
253 	/* Check if the PHY is up to snuff... */
254 	at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR,
255 		MII_PHYSID1, &phy_id);
256 	if (phy_id == 0xffff) {
257 		printf("%s: No PHY present\n", netdev->name);
258 		return -1;
259 	}
260 
261 	at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR,
262 		MII_BMSR, &status);
263 
264 	if (!(status & BMSR_LSTATUS)) {
265 		/* Try to re-negotiate if we don't have link already. */
266 		if (at91emac_phy_reset(netdev))
267 			return -2;
268 
269 		for (i = 0; i < 100000 / 100; i++) {
270 			at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR,
271 				MII_BMSR, &status);
272 			if (status & BMSR_LSTATUS)
273 				break;
274 			udelay(100);
275 		}
276 	}
277 	if (!(status & BMSR_LSTATUS)) {
278 		debug_cond(VERBOSEP, "%s: link down\n", netdev->name);
279 		return -3;
280 	} else {
281 		at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR,
282 			MII_ADVERTISE, &adv);
283 		at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR,
284 			MII_LPA, &lpa);
285 		media = mii_nway_result(lpa & adv);
286 		speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF)
287 			 ? 1 : 0);
288 		duplex = (media & ADVERTISE_FULL) ? 1 : 0;
289 		debug_cond(VERBOSEP, "%s: link up, %sMbps %s-duplex\n",
290 		       netdev->name,
291 		       speed ? "100" : "10",
292 		       duplex ? "full" : "half");
293 	}
294 	return 0;
295 }
296 
297 int at91emac_UpdateLinkSpeed(at91_emac_t *emac)
298 {
299 	unsigned short stat1;
300 
301 	at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR, MII_BMSR, &stat1);
302 
303 	if (!(stat1 & BMSR_LSTATUS))	/* link status up? */
304 		return -1;
305 
306 	if (stat1 & BMSR_100FULL) {
307 		/*set Emac for 100BaseTX and Full Duplex  */
308 		writel(readl(&emac->cfg) |
309 			AT91_EMAC_CFG_SPD | AT91_EMAC_CFG_FD,
310 			&emac->cfg);
311 		return 0;
312 	}
313 
314 	if (stat1 & BMSR_10FULL) {
315 		/*set MII for 10BaseT and Full Duplex  */
316 		writel((readl(&emac->cfg) &
317 			~(AT91_EMAC_CFG_SPD | AT91_EMAC_CFG_FD)
318 			) | AT91_EMAC_CFG_FD,
319 			&emac->cfg);
320 		return 0;
321 	}
322 
323 	if (stat1 & BMSR_100HALF) {
324 		/*set MII for 100BaseTX and Half Duplex  */
325 		writel((readl(&emac->cfg) &
326 			~(AT91_EMAC_CFG_SPD | AT91_EMAC_CFG_FD)
327 			) | AT91_EMAC_CFG_SPD,
328 			&emac->cfg);
329 		return 0;
330 	}
331 
332 	if (stat1 & BMSR_10HALF) {
333 		/*set MII for 10BaseT and Half Duplex  */
334 		writel((readl(&emac->cfg) &
335 			~(AT91_EMAC_CFG_SPD | AT91_EMAC_CFG_FD)),
336 			&emac->cfg);
337 		return 0;
338 	}
339 	return 0;
340 }
341 
342 static int at91emac_init(struct eth_device *netdev, bd_t *bd)
343 {
344 	int i;
345 	u32 value;
346 	emac_device *dev;
347 	at91_emac_t *emac;
348 	at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO;
349 	at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
350 
351 	emac = (at91_emac_t *) netdev->iobase;
352 	dev = (emac_device *) netdev->priv;
353 
354 	/* PIO Disable Register */
355 	value =	ATMEL_PMX_AA_EMDIO |	ATMEL_PMX_AA_EMDC |
356 		ATMEL_PMX_AA_ERXER |	ATMEL_PMX_AA_ERX1 |
357 		ATMEL_PMX_AA_ERX0 |	ATMEL_PMX_AA_ECRS |
358 		ATMEL_PMX_AA_ETX1 |	ATMEL_PMX_AA_ETX0 |
359 		ATMEL_PMX_AA_ETXEN |	ATMEL_PMX_AA_EREFCK;
360 
361 	writel(value, &pio->pioa.pdr);
362 	writel(value, &pio->pioa.asr);
363 
364 #ifdef CONFIG_RMII
365 	value = ATMEL_PMX_BA_ERXCK;
366 #else
367 	value = ATMEL_PMX_BA_ERXCK |	ATMEL_PMX_BA_ECOL |
368 		ATMEL_PMX_BA_ERXDV |	ATMEL_PMX_BA_ERX3 |
369 		ATMEL_PMX_BA_ERX2 |	ATMEL_PMX_BA_ETXER |
370 		ATMEL_PMX_BA_ETX3 |	ATMEL_PMX_BA_ETX2;
371 #endif
372 	writel(value, &pio->piob.pdr);
373 	writel(value, &pio->piob.bsr);
374 
375 	writel(1 << ATMEL_ID_EMAC, &pmc->pcer);
376 	writel(readl(&emac->ctl) | AT91_EMAC_CTL_CSR, &emac->ctl);
377 
378 	/* Init Ethernet buffers */
379 	for (i = 0; i < RBF_FRAMEMAX; i++) {
380 		dev->rbfdt[i].addr = (unsigned long) NetRxPackets[i];
381 		dev->rbfdt[i].size = 0;
382 	}
383 	dev->rbfdt[RBF_FRAMEMAX - 1].addr |= RBF_WRAP;
384 	dev->rbindex = 0;
385 	writel((u32) &(dev->rbfdt[0]), &emac->rbqp);
386 
387 	writel(readl(&emac->rsr) &
388 		~(AT91_EMAC_RSR_OVR | AT91_EMAC_RSR_REC | AT91_EMAC_RSR_BNA),
389 		&emac->rsr);
390 
391 	value = AT91_EMAC_CFG_CAF |	AT91_EMAC_CFG_NBC |
392 		HCLK_DIV;
393 #ifdef CONFIG_RMII
394 	value |= AT91_EMAC_CFG_RMII;
395 #endif
396 	writel(value, &emac->cfg);
397 
398 	writel(readl(&emac->ctl) | AT91_EMAC_CTL_TE | AT91_EMAC_CTL_RE,
399 		&emac->ctl);
400 
401 	if (!at91emac_phy_init(netdev)) {
402 		at91emac_UpdateLinkSpeed(emac);
403 		return 0;
404 	}
405 	return -1;
406 }
407 
408 static void at91emac_halt(struct eth_device *netdev)
409 {
410 	at91_emac_t *emac;
411 
412 	emac = (at91_emac_t *) netdev->iobase;
413 	writel(readl(&emac->ctl) & ~(AT91_EMAC_CTL_TE | AT91_EMAC_CTL_RE),
414 		&emac->ctl);
415 	debug_cond(DEBUG_AT91EMAC, "halt MAC\n");
416 }
417 
418 static int at91emac_send(struct eth_device *netdev, volatile void *packet,
419 		     int length)
420 {
421 	at91_emac_t *emac;
422 
423 	emac = (at91_emac_t *) netdev->iobase;
424 
425 	while (!(readl(&emac->tsr) & AT91_EMAC_TSR_BNQ))
426 		;
427 	writel((u32) packet, &emac->tar);
428 	writel(AT91_EMAC_TCR_LEN(length), &emac->tcr);
429 	while (AT91_EMAC_TCR_LEN(readl(&emac->tcr)))
430 		;
431 	debug_cond(DEBUG_AT91EMAC, "Send %d\n", length);
432 	writel(readl(&emac->tsr) | AT91_EMAC_TSR_COMP, &emac->tsr);
433 	return 0;
434 }
435 
436 static int at91emac_recv(struct eth_device *netdev)
437 {
438 	emac_device *dev;
439 	at91_emac_t *emac;
440 	rbf_t *rbfp;
441 	int size;
442 
443 	emac = (at91_emac_t *) netdev->iobase;
444 	dev = (emac_device *) netdev->priv;
445 
446 	rbfp = &dev->rbfdt[dev->rbindex];
447 	while (rbfp->addr & RBF_OWNER)	{
448 		size = rbfp->size & RBF_SIZE;
449 		NetReceive(NetRxPackets[dev->rbindex], size);
450 
451 		debug_cond(DEBUG_AT91EMAC, "Recv[%ld]: %d bytes @ %lx\n",
452 			dev->rbindex, size, rbfp->addr);
453 
454 		rbfp->addr &= ~RBF_OWNER;
455 		rbfp->size = 0;
456 		if (dev->rbindex < (RBF_FRAMEMAX-1))
457 			dev->rbindex++;
458 		else
459 			dev->rbindex = 0;
460 
461 		rbfp = &(dev->rbfdt[dev->rbindex]);
462 		if (!(rbfp->addr & RBF_OWNER))
463 			writel(readl(&emac->rsr) | AT91_EMAC_RSR_REC,
464 				&emac->rsr);
465 	}
466 
467 	if (readl(&emac->isr) & AT91_EMAC_IxR_RBNA) {
468 		/* EMAC silicon bug 41.3.1 workaround 1 */
469 		writel(readl(&emac->ctl) & ~AT91_EMAC_CTL_RE, &emac->ctl);
470 		writel(readl(&emac->ctl) | AT91_EMAC_CTL_RE, &emac->ctl);
471 		dev->rbindex = 0;
472 		printf("%s: reset receiver (EMAC dead lock bug)\n",
473 			netdev->name);
474 	}
475 	return 0;
476 }
477 
478 static int at91emac_write_hwaddr(struct eth_device *netdev)
479 {
480 	at91_emac_t *emac;
481 	at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
482 	emac = (at91_emac_t *) netdev->iobase;
483 
484 	writel(1 << ATMEL_ID_EMAC, &pmc->pcer);
485 	debug_cond(DEBUG_AT91EMAC,
486 		"init MAC-ADDR %02x:%02x:%02x:%02x:%02x:%02x\n",
487 		netdev->enetaddr[5], netdev->enetaddr[4], netdev->enetaddr[3],
488 		netdev->enetaddr[2], netdev->enetaddr[1], netdev->enetaddr[0]);
489 	writel( (netdev->enetaddr[0] | netdev->enetaddr[1] << 8 |
490 			netdev->enetaddr[2] << 16 | netdev->enetaddr[3] << 24),
491 			&emac->sa2l);
492 	writel((netdev->enetaddr[4] | netdev->enetaddr[5] << 8), &emac->sa2h);
493 	debug_cond(DEBUG_AT91EMAC, "init MAC-ADDR %x%x\n",
494 		readl(&emac->sa2h), readl(&emac->sa2l));
495 	return 0;
496 }
497 
498 int at91emac_register(bd_t *bis, unsigned long iobase)
499 {
500 	emac_device *emac;
501 	emac_device *emacfix;
502 	struct eth_device *dev;
503 
504 	if (iobase == 0)
505 		iobase = ATMEL_BASE_EMAC;
506 	emac = malloc(sizeof(*emac)+512);
507 	if (emac == NULL)
508 		return -1;
509 	dev = malloc(sizeof(*dev));
510 	if (dev == NULL) {
511 		free(emac);
512 		return -1;
513 	}
514 	/* alignment as per Errata (64 bytes) is insufficient! */
515 	emacfix = (emac_device *) (((unsigned long) emac + 0x1ff) & 0xFFFFFE00);
516 	memset(emacfix, 0, sizeof(emac_device));
517 
518 	memset(dev, 0, sizeof(*dev));
519 	sprintf(dev->name, "emac");
520 	dev->iobase = iobase;
521 	dev->priv = emacfix;
522 	dev->init = at91emac_init;
523 	dev->halt = at91emac_halt;
524 	dev->send = at91emac_send;
525 	dev->recv = at91emac_recv;
526 	dev->write_hwaddr = at91emac_write_hwaddr;
527 
528 	eth_register(dev);
529 
530 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
531 	miiphy_register(dev->name, at91emac_mii_read, at91emac_mii_write);
532 #endif
533 	return 1;
534 }
535