1 /* 2 * Altera 10/100/1000 triple speed ethernet mac 3 * 4 * Copyright (C) 2008 Altera Corporation. 5 * Copyright (C) 2010 Thomas Chou <thomas@wytron.com.tw> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11 #ifndef _ALTERA_TSE_H_ 12 #define _ALTERA_TSE_H_ 13 14 #define __packed_1_ __attribute__ ((packed, aligned(1))) 15 16 /* PHY Stuff */ 17 #define miim_end -2 18 #define miim_read -1 19 20 #define PHY_AUTONEGOTIATE_TIMEOUT 5000 /* in ms */ 21 22 #ifndef CONFIG_SYS_TBIPA_VALUE 23 #define CONFIG_SYS_TBIPA_VALUE 0x1f 24 #endif 25 #define MIIMCFG_INIT_VALUE 0x00000003 26 #define MIIMCFG_RESET 0x80000000 27 28 #define MIIMIND_BUSY 0x00000001 29 #define MIIMIND_NOTVALID 0x00000004 30 31 #define MIIM_CONTROL 0x00 32 #define MIIM_CONTROL_RESET 0x00009140 33 #define MIIM_CONTROL_INIT 0x00001140 34 #define MIIM_CONTROL_RESTART 0x00001340 35 #define MIIM_ANEN 0x00001000 36 37 #define MIIM_CR 0x00 38 #define MIIM_CR_RST 0x00008000 39 #define MIIM_CR_INIT 0x00001000 40 41 #define MIIM_STATUS 0x1 42 #define MIIM_STATUS_AN_DONE 0x00000020 43 #define MIIM_STATUS_LINK 0x0004 44 #define PHY_BMSR_AUTN_ABLE 0x0008 45 #define PHY_BMSR_AUTN_COMP 0x0020 46 47 #define MIIM_PHYIR1 0x2 48 #define MIIM_PHYIR2 0x3 49 50 #define MIIM_ANAR 0x4 51 #define MIIM_ANAR_INIT 0x1e1 52 53 #define MIIM_TBI_ANLPBPA 0x5 54 #define MIIM_TBI_ANLPBPA_HALF 0x00000040 55 #define MIIM_TBI_ANLPBPA_FULL 0x00000020 56 57 #define MIIM_TBI_ANEX 0x6 58 #define MIIM_TBI_ANEX_NP 0x00000004 59 #define MIIM_TBI_ANEX_PRX 0x00000002 60 61 #define MIIM_GBIT_CONTROL 0x9 62 #define MIIM_GBIT_CONTROL_INIT 0xe00 63 64 #define MIIM_EXT_PAGE_ACCESS 0x1f 65 66 /* 88E1011 PHY Status Register */ 67 #define MIIM_88E1011_PHY_STATUS 0x11 68 #define MIIM_88E1011_PHYSTAT_SPEED 0xc000 69 #define MIIM_88E1011_PHYSTAT_GBIT 0x8000 70 #define MIIM_88E1011_PHYSTAT_100 0x4000 71 #define MIIM_88E1011_PHYSTAT_DUPLEX 0x2000 72 #define MIIM_88E1011_PHYSTAT_SPDDONE 0x0800 73 #define MIIM_88E1011_PHYSTAT_LINK 0x0400 74 75 #define MIIM_88E1011_PHY_SCR 0x10 76 #define MIIM_88E1011_PHY_MDI_X_AUTO 0x0060 77 78 #define MIIM_88E1111_PHY_EXT_CR 0x14 79 #define MIIM_88E1111_PHY_EXT_SR 0x1b 80 81 /* 88E1111 PHY LED Control Register */ 82 #define MIIM_88E1111_PHY_LED_CONTROL 24 83 #define MIIM_88E1111_PHY_LED_DIRECT 0x4100 84 #define MIIM_88E1111_PHY_LED_COMBINE 0x411C 85 86 #define MIIM_READ_COMMAND 0x00000001 87 88 /* struct phy_info: a structure which defines attributes for a PHY 89 * id will contain a number which represents the PHY. During 90 * startup, the driver will poll the PHY to find out what its 91 * UID--as defined by registers 2 and 3--is. The 32-bit result 92 * gotten from the PHY will be shifted right by "shift" bits to 93 * discard any bits which may change based on revision numbers 94 * unimportant to functionality 95 * 96 * The struct phy_cmd entries represent pointers to an arrays of 97 * commands which tell the driver what to do to the PHY. 98 */ 99 struct phy_info { 100 uint id; 101 char *name; 102 uint shift; 103 /* Called to configure the PHY, and modify the controller 104 * based on the results */ 105 struct phy_cmd *config; 106 107 /* Called when starting up the controller */ 108 struct phy_cmd *startup; 109 110 /* Called when bringing down the controller */ 111 struct phy_cmd *shutdown; 112 }; 113 114 /* SGDMA Stuff */ 115 #define ALT_SGDMA_STATUS_ERROR_MSK (0x00000001) 116 #define ALT_SGDMA_STATUS_EOP_ENCOUNTERED_MSK (0x00000002) 117 #define ALT_SGDMA_STATUS_DESC_COMPLETED_MSK (0x00000004) 118 #define ALT_SGDMA_STATUS_CHAIN_COMPLETED_MSK (0x00000008) 119 #define ALT_SGDMA_STATUS_BUSY_MSK (0x00000010) 120 121 #define ALT_SGDMA_CONTROL_IE_ERROR_MSK (0x00000001) 122 #define ALT_SGDMA_CONTROL_IE_EOP_ENCOUNTERED_MSK (0x00000002) 123 #define ALT_SGDMA_CONTROL_IE_DESC_COMPLETED_MSK (0x00000004) 124 #define ALT_SGDMA_CONTROL_IE_CHAIN_COMPLETED_MSK (0x00000008) 125 #define ALT_SGDMA_CONTROL_IE_GLOBAL_MSK (0x00000010) 126 #define ALT_SGDMA_CONTROL_RUN_MSK (0x00000020) 127 #define ALT_SGDMA_CONTROL_STOP_DMA_ER_MSK (0x00000040) 128 #define ALT_SGDMA_CONTROL_IE_MAX_DESC_PROCESSED_MSK (0x00000080) 129 #define ALT_SGDMA_CONTROL_MAX_DESC_PROCESSED_MSK (0x0000FF00) 130 #define ALT_SGDMA_CONTROL_SOFTWARERESET_MSK (0x00010000) 131 #define ALT_SGDMA_CONTROL_PARK_MSK (0x00020000) 132 #define ALT_SGDMA_CONTROL_CLEAR_INTERRUPT_MSK (0x80000000) 133 134 #define ALTERA_TSE_SGDMA_INTR_MASK (ALT_SGDMA_CONTROL_IE_CHAIN_COMPLETED_MSK \ 135 | ALT_SGDMA_STATUS_DESC_COMPLETED_MSK \ 136 | ALT_SGDMA_CONTROL_IE_GLOBAL_MSK) 137 138 /* 139 * Descriptor control bit masks & offsets 140 * 141 * Note: The control byte physically occupies bits [31:24] in memory. 142 * The following bit-offsets are expressed relative to the LSB of 143 * the control register bitfield. 144 */ 145 #define ALT_SGDMA_DESCRIPTOR_CONTROL_GENERATE_EOP_MSK (0x00000001) 146 #define ALT_SGDMA_DESCRIPTOR_CONTROL_READ_FIXED_ADDRESS_MSK (0x00000002) 147 #define ALT_SGDMA_DESCRIPTOR_CONTROL_WRITE_FIXED_ADDRESS_MSK (0x00000004) 148 #define ALT_SGDMA_DESCRIPTOR_CONTROL_ATLANTIC_CHANNEL_MSK (0x00000008) 149 #define ALT_SGDMA_DESCRIPTOR_CONTROL_OWNED_BY_HW_MSK (0x00000080) 150 151 /* 152 * Descriptor status bit masks & offsets 153 * 154 * Note: The status byte physically occupies bits [23:16] in memory. 155 * The following bit-offsets are expressed relative to the LSB of 156 * the status register bitfield. 157 */ 158 #define ALT_SGDMA_DESCRIPTOR_STATUS_E_CRC_MSK (0x00000001) 159 #define ALT_SGDMA_DESCRIPTOR_STATUS_E_PARITY_MSK (0x00000002) 160 #define ALT_SGDMA_DESCRIPTOR_STATUS_E_OVERFLOW_MSK (0x00000004) 161 #define ALT_SGDMA_DESCRIPTOR_STATUS_E_SYNC_MSK (0x00000008) 162 #define ALT_SGDMA_DESCRIPTOR_STATUS_E_UEOP_MSK (0x00000010) 163 #define ALT_SGDMA_DESCRIPTOR_STATUS_E_MEOP_MSK (0x00000020) 164 #define ALT_SGDMA_DESCRIPTOR_STATUS_E_MSOP_MSK (0x00000040) 165 #define ALT_SGDMA_DESCRIPTOR_STATUS_TERMINATED_BY_EOP_MSK (0x00000080) 166 #define ALT_SGDMA_DESCRIPTOR_STATUS_ERROR_MSK (0x0000007F) 167 168 /* 169 * The SGDMA controller buffer descriptor allocates 170 * 64 bits for each address. To support ANSI C, the 171 * struct implementing a descriptor places 32-bits 172 * of padding directly above each address; each pad must 173 * be cleared when initializing a descriptor. 174 */ 175 176 /* 177 * Buffer Descriptor data structure 178 * 179 */ 180 struct alt_sgdma_descriptor { 181 unsigned int *source; /* the address of data to be read. */ 182 unsigned int source_pad; 183 184 unsigned int *destination; /* the address to write data */ 185 unsigned int destination_pad; 186 187 unsigned int *next; /* the next descriptor in the list. */ 188 unsigned int next_pad; 189 190 unsigned short bytes_to_transfer; /* the number of bytes to transfer */ 191 unsigned char read_burst; 192 unsigned char write_burst; 193 194 unsigned short actual_bytes_transferred;/* bytes transferred by DMA */ 195 unsigned char descriptor_status; 196 unsigned char descriptor_control; 197 198 } __packed_1_; 199 200 /* SG-DMA Control/Status Slave registers map */ 201 202 struct alt_sgdma_registers { 203 unsigned int status; 204 unsigned int status_pad[3]; 205 unsigned int control; 206 unsigned int control_pad[3]; 207 unsigned int next_descriptor_pointer; 208 unsigned int descriptor_pad[3]; 209 }; 210 211 /* TSE Stuff */ 212 #define ALTERA_TSE_CMD_TX_ENA_MSK (0x00000001) 213 #define ALTERA_TSE_CMD_RX_ENA_MSK (0x00000002) 214 #define ALTERA_TSE_CMD_XON_GEN_MSK (0x00000004) 215 #define ALTERA_TSE_CMD_ETH_SPEED_MSK (0x00000008) 216 #define ALTERA_TSE_CMD_PROMIS_EN_MSK (0x00000010) 217 #define ALTERA_TSE_CMD_PAD_EN_MSK (0x00000020) 218 #define ALTERA_TSE_CMD_CRC_FWD_MSK (0x00000040) 219 #define ALTERA_TSE_CMD_PAUSE_FWD_MSK (0x00000080) 220 #define ALTERA_TSE_CMD_PAUSE_IGNORE_MSK (0x00000100) 221 #define ALTERA_TSE_CMD_TX_ADDR_INS_MSK (0x00000200) 222 #define ALTERA_TSE_CMD_HD_ENA_MSK (0x00000400) 223 #define ALTERA_TSE_CMD_EXCESS_COL_MSK (0x00000800) 224 #define ALTERA_TSE_CMD_LATE_COL_MSK (0x00001000) 225 #define ALTERA_TSE_CMD_SW_RESET_MSK (0x00002000) 226 #define ALTERA_TSE_CMD_MHASH_SEL_MSK (0x00004000) 227 #define ALTERA_TSE_CMD_LOOPBACK_MSK (0x00008000) 228 /* Bits (18:16) = address select */ 229 #define ALTERA_TSE_CMD_TX_ADDR_SEL_MSK (0x00070000) 230 #define ALTERA_TSE_CMD_MAGIC_ENA_MSK (0x00080000) 231 #define ALTERA_TSE_CMD_SLEEP_MSK (0x00100000) 232 #define ALTERA_TSE_CMD_WAKEUP_MSK (0x00200000) 233 #define ALTERA_TSE_CMD_XOFF_GEN_MSK (0x00400000) 234 #define ALTERA_TSE_CMD_CNTL_FRM_ENA_MSK (0x00800000) 235 #define ALTERA_TSE_CMD_NO_LENGTH_CHECK_MSK (0x01000000) 236 #define ALTERA_TSE_CMD_ENA_10_MSK (0x02000000) 237 #define ALTERA_TSE_CMD_RX_ERR_DISC_MSK (0x04000000) 238 /* Bits (30..27) reserved */ 239 #define ALTERA_TSE_CMD_CNT_RESET_MSK (0x80000000) 240 241 #define ALTERA_TSE_TX_CMD_STAT_TX_SHIFT16 (0x00040000) 242 #define ALTERA_TSE_TX_CMD_STAT_OMIT_CRC (0x00020000) 243 244 #define ALTERA_TSE_RX_CMD_STAT_RX_SHIFT16 (0x02000000) 245 246 #define ALT_TSE_SW_RESET_WATCHDOG_CNTR 10000 247 #define ALT_TSE_SGDMA_BUSY_WATCHDOG_CNTR 90000000 248 249 /* Command_Config Register Bit Definitions */ 250 251 typedef volatile union __alt_tse_command_config { 252 unsigned int image; 253 struct { 254 unsigned int 255 transmit_enable:1, /* bit 0 */ 256 receive_enable:1, /* bit 1 */ 257 pause_frame_xon_gen:1, /* bit 2 */ 258 ethernet_speed:1, /* bit 3 */ 259 promiscuous_enable:1, /* bit 4 */ 260 pad_enable:1, /* bit 5 */ 261 crc_forward:1, /* bit 6 */ 262 pause_frame_forward:1, /* bit 7 */ 263 pause_frame_ignore:1, /* bit 8 */ 264 set_mac_address_on_tx:1, /* bit 9 */ 265 halfduplex_enable:1, /* bit 10 */ 266 excessive_collision:1, /* bit 11 */ 267 late_collision:1, /* bit 12 */ 268 software_reset:1, /* bit 13 */ 269 multicast_hash_mode_sel:1, /* bit 14 */ 270 loopback_enable:1, /* bit 15 */ 271 src_mac_addr_sel_on_tx:3, /* bit 18:16 */ 272 magic_packet_detect:1, /* bit 19 */ 273 sleep_mode_enable:1, /* bit 20 */ 274 wake_up_request:1, /* bit 21 */ 275 pause_frame_xoff_gen:1, /* bit 22 */ 276 control_frame_enable:1, /* bit 23 */ 277 payload_len_chk_disable:1, /* bit 24 */ 278 enable_10mbps_intf:1, /* bit 25 */ 279 rx_error_discard_enable:1, /* bit 26 */ 280 reserved_bits:4, /* bit 30:27 */ 281 self_clear_counter_reset:1; /* bit 31 */ 282 } __packed_1_ bits; 283 } __packed_1_ alt_tse_command_config; 284 285 /* Tx_Cmd_Stat Register Bit Definitions */ 286 287 typedef volatile union __alt_tse_tx_cmd_stat { 288 unsigned int image; 289 struct { 290 unsigned int reserved_lsbs:17, /* bit 16:0 */ 291 omit_crc:1, /* bit 17 */ 292 tx_shift16:1, /* bit 18 */ 293 reserved_msbs:13; /* bit 31:19 */ 294 295 } __packed_1_ bits; 296 } alt_tse_tx_cmd_stat; 297 298 /* Rx_Cmd_Stat Register Bit Definitions */ 299 300 typedef volatile union __alt_tse_rx_cmd_stat { 301 unsigned int image; 302 struct { 303 unsigned int reserved_lsbs:25, /* bit 24:0 */ 304 rx_shift16:1, /* bit 25 */ 305 reserved_msbs:6; /* bit 31:26 */ 306 307 } __packed_1_ bits; 308 } alt_tse_rx_cmd_stat; 309 310 struct alt_tse_mdio { 311 unsigned int control; /*PHY device operation control register */ 312 unsigned int status; /*PHY device operation status register */ 313 unsigned int phy_id1; /*Bits 31:16 of PHY identifier. */ 314 unsigned int phy_id2; /*Bits 15:0 of PHY identifier. */ 315 unsigned int auto_negotiation_advertisement; 316 unsigned int remote_partner_base_page_ability; 317 318 unsigned int reg6; 319 unsigned int reg7; 320 unsigned int reg8; 321 unsigned int reg9; 322 unsigned int rega; 323 unsigned int regb; 324 unsigned int regc; 325 unsigned int regd; 326 unsigned int rege; 327 unsigned int regf; 328 unsigned int reg10; 329 unsigned int reg11; 330 unsigned int reg12; 331 unsigned int reg13; 332 unsigned int reg14; 333 unsigned int reg15; 334 unsigned int reg16; 335 unsigned int reg17; 336 unsigned int reg18; 337 unsigned int reg19; 338 unsigned int reg1a; 339 unsigned int reg1b; 340 unsigned int reg1c; 341 unsigned int reg1d; 342 unsigned int reg1e; 343 unsigned int reg1f; 344 }; 345 346 /* MAC register Space */ 347 348 struct alt_tse_mac { 349 unsigned int megacore_revision; 350 unsigned int scratch_pad; 351 alt_tse_command_config command_config; 352 unsigned int mac_addr_0; 353 unsigned int mac_addr_1; 354 unsigned int max_frame_length; 355 unsigned int pause_quanta; 356 unsigned int rx_sel_empty_threshold; 357 unsigned int rx_sel_full_threshold; 358 unsigned int tx_sel_empty_threshold; 359 unsigned int tx_sel_full_threshold; 360 unsigned int rx_almost_empty_threshold; 361 unsigned int rx_almost_full_threshold; 362 unsigned int tx_almost_empty_threshold; 363 unsigned int tx_almost_full_threshold; 364 unsigned int mdio_phy0_addr; 365 unsigned int mdio_phy1_addr; 366 367 /* only if 100/1000 BaseX PCS, reserved otherwise */ 368 unsigned int reservedx44[5]; 369 370 unsigned int reg_read_access_status; 371 unsigned int min_tx_ipg_length; 372 373 /* IEEE 802.3 oEntity Managed Object Support */ 374 unsigned int aMACID_1; /*The MAC addresses */ 375 unsigned int aMACID_2; 376 unsigned int aFramesTransmittedOK; 377 unsigned int aFramesReceivedOK; 378 unsigned int aFramesCheckSequenceErrors; 379 unsigned int aAlignmentErrors; 380 unsigned int aOctetsTransmittedOK; 381 unsigned int aOctetsReceivedOK; 382 383 /* IEEE 802.3 oPausedEntity Managed Object Support */ 384 unsigned int aTxPAUSEMACCtrlFrames; 385 unsigned int aRxPAUSEMACCtrlFrames; 386 387 /* IETF MIB (MIB-II) Object Support */ 388 unsigned int ifInErrors; 389 unsigned int ifOutErrors; 390 unsigned int ifInUcastPkts; 391 unsigned int ifInMulticastPkts; 392 unsigned int ifInBroadcastPkts; 393 unsigned int ifOutDiscards; 394 unsigned int ifOutUcastPkts; 395 unsigned int ifOutMulticastPkts; 396 unsigned int ifOutBroadcastPkts; 397 398 /* IETF RMON MIB Object Support */ 399 unsigned int etherStatsDropEvent; 400 unsigned int etherStatsOctets; 401 unsigned int etherStatsPkts; 402 unsigned int etherStatsUndersizePkts; 403 unsigned int etherStatsOversizePkts; 404 unsigned int etherStatsPkts64Octets; 405 unsigned int etherStatsPkts65to127Octets; 406 unsigned int etherStatsPkts128to255Octets; 407 unsigned int etherStatsPkts256to511Octets; 408 unsigned int etherStatsPkts512to1023Octets; 409 unsigned int etherStatsPkts1024to1518Octets; 410 411 unsigned int etherStatsPkts1519toXOctets; 412 unsigned int etherStatsJabbers; 413 unsigned int etherStatsFragments; 414 415 unsigned int reservedxE4; 416 417 /*FIFO control register. */ 418 alt_tse_tx_cmd_stat tx_cmd_stat; 419 alt_tse_rx_cmd_stat rx_cmd_stat; 420 421 unsigned int ipaccTxConf; 422 unsigned int ipaccRxConf; 423 unsigned int ipaccRxStat; 424 unsigned int ipaccRxStatSum; 425 426 /*Multicast address resolution table */ 427 unsigned int hash_table[64]; 428 429 /*Registers 0 to 31 within PHY device 0/1 */ 430 struct alt_tse_mdio mdio_phy0; 431 struct alt_tse_mdio mdio_phy1; 432 433 /*4 Supplemental MAC Addresses */ 434 unsigned int supp_mac_addr_0_0; 435 unsigned int supp_mac_addr_0_1; 436 unsigned int supp_mac_addr_1_0; 437 unsigned int supp_mac_addr_1_1; 438 unsigned int supp_mac_addr_2_0; 439 unsigned int supp_mac_addr_2_1; 440 unsigned int supp_mac_addr_3_0; 441 unsigned int supp_mac_addr_3_1; 442 443 unsigned int reservedx320[56]; 444 }; 445 446 /* flags: TSE MII modes */ 447 /* GMII/MII = 0 */ 448 /* RGMII = 1 */ 449 /* RGMII_ID = 2 */ 450 /* RGMII_TXID = 3 */ 451 /* RGMII_RXID = 4 */ 452 /* SGMII = 5 */ 453 struct altera_tse_priv { 454 char devname[16]; 455 volatile struct alt_tse_mac *mac_dev; 456 volatile struct alt_sgdma_registers *sgdma_rx; 457 volatile struct alt_sgdma_registers *sgdma_tx; 458 unsigned int rx_sgdma_irq; 459 unsigned int tx_sgdma_irq; 460 unsigned int has_descriptor_mem; 461 unsigned int descriptor_mem_base; 462 unsigned int descriptor_mem_size; 463 volatile struct alt_sgdma_descriptor *rx_desc; 464 volatile struct alt_sgdma_descriptor *tx_desc; 465 volatile unsigned char *rx_buf; 466 struct phy_info *phyinfo; 467 unsigned int phyaddr; 468 unsigned int flags; 469 unsigned int link; 470 unsigned int duplexity; 471 unsigned int speed; 472 }; 473 474 /* Phy stuff continued */ 475 /* 476 * struct phy_cmd: A command for reading or writing a PHY register 477 * 478 * mii_reg: The register to read or write 479 * 480 * mii_data: For writes, the value to put in the register. 481 * A value of -1 indicates this is a read. 482 * 483 * funct: A function pointer which is invoked for each command. 484 * For reads, this function will be passed the value read 485 * from the PHY, and process it. 486 * For writes, the result of this function will be written 487 * to the PHY register 488 */ 489 struct phy_cmd { 490 uint mii_reg; 491 uint mii_data; 492 uint(*funct) (uint mii_reg, struct altera_tse_priv *priv); 493 }; 494 #endif /* _ALTERA_TSE_H_ */ 495