1 /* 2 * Altera 10/100/1000 triple speed ethernet mac 3 * 4 * Copyright (C) 2008 Altera Corporation. 5 * Copyright (C) 2010 Thomas Chou <thomas@wytron.com.tw> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11 #ifndef _ALTERA_TSE_H_ 12 #define _ALTERA_TSE_H_ 13 14 #define __packed_1_ __attribute__ ((packed, aligned(1))) 15 16 /* PHY Stuff */ 17 #define miim_end -2 18 #define miim_read -1 19 20 #define PHY_AUTONEGOTIATE_TIMEOUT 5000 /* in ms */ 21 22 #ifndef CONFIG_SYS_TBIPA_VALUE 23 #define CONFIG_SYS_TBIPA_VALUE 0x1f 24 #endif 25 #define MIIMCFG_INIT_VALUE 0x00000003 26 #define MIIMCFG_RESET 0x80000000 27 28 #define MIIMIND_BUSY 0x00000001 29 #define MIIMIND_NOTVALID 0x00000004 30 31 #define MIIM_CONTROL 0x00 32 #define MIIM_CONTROL_RESET 0x00009140 33 #define MIIM_CONTROL_INIT 0x00001140 34 #define MIIM_CONTROL_RESTART 0x00001340 35 #define MIIM_ANEN 0x00001000 36 37 #define MIIM_CR 0x00 38 #define MIIM_CR_RST 0x00008000 39 #define MIIM_CR_INIT 0x00001000 40 41 #define MIIM_STATUS 0x1 42 #define MIIM_STATUS_AN_DONE 0x00000020 43 #define MIIM_STATUS_LINK 0x0004 44 45 #define MIIM_PHYIR1 0x2 46 #define MIIM_PHYIR2 0x3 47 48 #define MIIM_ANAR 0x4 49 #define MIIM_ANAR_INIT 0x1e1 50 51 #define MIIM_TBI_ANLPBPA 0x5 52 #define MIIM_TBI_ANLPBPA_HALF 0x00000040 53 #define MIIM_TBI_ANLPBPA_FULL 0x00000020 54 55 #define MIIM_TBI_ANEX 0x6 56 #define MIIM_TBI_ANEX_NP 0x00000004 57 #define MIIM_TBI_ANEX_PRX 0x00000002 58 59 #define MIIM_GBIT_CONTROL 0x9 60 #define MIIM_GBIT_CONTROL_INIT 0xe00 61 62 #define MIIM_EXT_PAGE_ACCESS 0x1f 63 64 /* 88E1011 PHY Status Register */ 65 #define MIIM_88E1011_PHY_STATUS 0x11 66 #define MIIM_88E1011_PHYSTAT_SPEED 0xc000 67 #define MIIM_88E1011_PHYSTAT_GBIT 0x8000 68 #define MIIM_88E1011_PHYSTAT_100 0x4000 69 #define MIIM_88E1011_PHYSTAT_DUPLEX 0x2000 70 #define MIIM_88E1011_PHYSTAT_SPDDONE 0x0800 71 #define MIIM_88E1011_PHYSTAT_LINK 0x0400 72 73 #define MIIM_88E1011_PHY_SCR 0x10 74 #define MIIM_88E1011_PHY_MDI_X_AUTO 0x0060 75 76 #define MIIM_88E1111_PHY_EXT_CR 0x14 77 #define MIIM_88E1111_PHY_EXT_SR 0x1b 78 79 /* 88E1111 PHY LED Control Register */ 80 #define MIIM_88E1111_PHY_LED_CONTROL 24 81 #define MIIM_88E1111_PHY_LED_DIRECT 0x4100 82 #define MIIM_88E1111_PHY_LED_COMBINE 0x411C 83 84 #define MIIM_READ_COMMAND 0x00000001 85 86 /* struct phy_info: a structure which defines attributes for a PHY 87 * id will contain a number which represents the PHY. During 88 * startup, the driver will poll the PHY to find out what its 89 * UID--as defined by registers 2 and 3--is. The 32-bit result 90 * gotten from the PHY will be shifted right by "shift" bits to 91 * discard any bits which may change based on revision numbers 92 * unimportant to functionality 93 * 94 * The struct phy_cmd entries represent pointers to an arrays of 95 * commands which tell the driver what to do to the PHY. 96 */ 97 struct phy_info { 98 uint id; 99 char *name; 100 uint shift; 101 /* Called to configure the PHY, and modify the controller 102 * based on the results */ 103 struct phy_cmd *config; 104 105 /* Called when starting up the controller */ 106 struct phy_cmd *startup; 107 108 /* Called when bringing down the controller */ 109 struct phy_cmd *shutdown; 110 }; 111 112 /* SGDMA Stuff */ 113 #define ALT_SGDMA_STATUS_ERROR_MSK (0x00000001) 114 #define ALT_SGDMA_STATUS_EOP_ENCOUNTERED_MSK (0x00000002) 115 #define ALT_SGDMA_STATUS_DESC_COMPLETED_MSK (0x00000004) 116 #define ALT_SGDMA_STATUS_CHAIN_COMPLETED_MSK (0x00000008) 117 #define ALT_SGDMA_STATUS_BUSY_MSK (0x00000010) 118 119 #define ALT_SGDMA_CONTROL_IE_ERROR_MSK (0x00000001) 120 #define ALT_SGDMA_CONTROL_IE_EOP_ENCOUNTERED_MSK (0x00000002) 121 #define ALT_SGDMA_CONTROL_IE_DESC_COMPLETED_MSK (0x00000004) 122 #define ALT_SGDMA_CONTROL_IE_CHAIN_COMPLETED_MSK (0x00000008) 123 #define ALT_SGDMA_CONTROL_IE_GLOBAL_MSK (0x00000010) 124 #define ALT_SGDMA_CONTROL_RUN_MSK (0x00000020) 125 #define ALT_SGDMA_CONTROL_STOP_DMA_ER_MSK (0x00000040) 126 #define ALT_SGDMA_CONTROL_IE_MAX_DESC_PROCESSED_MSK (0x00000080) 127 #define ALT_SGDMA_CONTROL_MAX_DESC_PROCESSED_MSK (0x0000FF00) 128 #define ALT_SGDMA_CONTROL_SOFTWARERESET_MSK (0x00010000) 129 #define ALT_SGDMA_CONTROL_PARK_MSK (0x00020000) 130 #define ALT_SGDMA_CONTROL_CLEAR_INTERRUPT_MSK (0x80000000) 131 132 #define ALTERA_TSE_SGDMA_INTR_MASK (ALT_SGDMA_CONTROL_IE_CHAIN_COMPLETED_MSK \ 133 | ALT_SGDMA_STATUS_DESC_COMPLETED_MSK \ 134 | ALT_SGDMA_CONTROL_IE_GLOBAL_MSK) 135 136 /* 137 * Descriptor control bit masks & offsets 138 * 139 * Note: The control byte physically occupies bits [31:24] in memory. 140 * The following bit-offsets are expressed relative to the LSB of 141 * the control register bitfield. 142 */ 143 #define ALT_SGDMA_DESCRIPTOR_CONTROL_GENERATE_EOP_MSK (0x00000001) 144 #define ALT_SGDMA_DESCRIPTOR_CONTROL_READ_FIXED_ADDRESS_MSK (0x00000002) 145 #define ALT_SGDMA_DESCRIPTOR_CONTROL_WRITE_FIXED_ADDRESS_MSK (0x00000004) 146 #define ALT_SGDMA_DESCRIPTOR_CONTROL_ATLANTIC_CHANNEL_MSK (0x00000008) 147 #define ALT_SGDMA_DESCRIPTOR_CONTROL_OWNED_BY_HW_MSK (0x00000080) 148 149 /* 150 * Descriptor status bit masks & offsets 151 * 152 * Note: The status byte physically occupies bits [23:16] in memory. 153 * The following bit-offsets are expressed relative to the LSB of 154 * the status register bitfield. 155 */ 156 #define ALT_SGDMA_DESCRIPTOR_STATUS_E_CRC_MSK (0x00000001) 157 #define ALT_SGDMA_DESCRIPTOR_STATUS_E_PARITY_MSK (0x00000002) 158 #define ALT_SGDMA_DESCRIPTOR_STATUS_E_OVERFLOW_MSK (0x00000004) 159 #define ALT_SGDMA_DESCRIPTOR_STATUS_E_SYNC_MSK (0x00000008) 160 #define ALT_SGDMA_DESCRIPTOR_STATUS_E_UEOP_MSK (0x00000010) 161 #define ALT_SGDMA_DESCRIPTOR_STATUS_E_MEOP_MSK (0x00000020) 162 #define ALT_SGDMA_DESCRIPTOR_STATUS_E_MSOP_MSK (0x00000040) 163 #define ALT_SGDMA_DESCRIPTOR_STATUS_TERMINATED_BY_EOP_MSK (0x00000080) 164 #define ALT_SGDMA_DESCRIPTOR_STATUS_ERROR_MSK (0x0000007F) 165 166 /* 167 * The SGDMA controller buffer descriptor allocates 168 * 64 bits for each address. To support ANSI C, the 169 * struct implementing a descriptor places 32-bits 170 * of padding directly above each address; each pad must 171 * be cleared when initializing a descriptor. 172 */ 173 174 /* 175 * Buffer Descriptor data structure 176 * 177 */ 178 struct alt_sgdma_descriptor { 179 unsigned int *source; /* the address of data to be read. */ 180 unsigned int source_pad; 181 182 unsigned int *destination; /* the address to write data */ 183 unsigned int destination_pad; 184 185 unsigned int *next; /* the next descriptor in the list. */ 186 unsigned int next_pad; 187 188 unsigned short bytes_to_transfer; /* the number of bytes to transfer */ 189 unsigned char read_burst; 190 unsigned char write_burst; 191 192 unsigned short actual_bytes_transferred;/* bytes transferred by DMA */ 193 unsigned char descriptor_status; 194 unsigned char descriptor_control; 195 196 } __packed_1_; 197 198 /* SG-DMA Control/Status Slave registers map */ 199 200 struct alt_sgdma_registers { 201 unsigned int status; 202 unsigned int status_pad[3]; 203 unsigned int control; 204 unsigned int control_pad[3]; 205 unsigned int next_descriptor_pointer; 206 unsigned int descriptor_pad[3]; 207 }; 208 209 /* TSE Stuff */ 210 #define ALTERA_TSE_CMD_TX_ENA_MSK (0x00000001) 211 #define ALTERA_TSE_CMD_RX_ENA_MSK (0x00000002) 212 #define ALTERA_TSE_CMD_XON_GEN_MSK (0x00000004) 213 #define ALTERA_TSE_CMD_ETH_SPEED_MSK (0x00000008) 214 #define ALTERA_TSE_CMD_PROMIS_EN_MSK (0x00000010) 215 #define ALTERA_TSE_CMD_PAD_EN_MSK (0x00000020) 216 #define ALTERA_TSE_CMD_CRC_FWD_MSK (0x00000040) 217 #define ALTERA_TSE_CMD_PAUSE_FWD_MSK (0x00000080) 218 #define ALTERA_TSE_CMD_PAUSE_IGNORE_MSK (0x00000100) 219 #define ALTERA_TSE_CMD_TX_ADDR_INS_MSK (0x00000200) 220 #define ALTERA_TSE_CMD_HD_ENA_MSK (0x00000400) 221 #define ALTERA_TSE_CMD_EXCESS_COL_MSK (0x00000800) 222 #define ALTERA_TSE_CMD_LATE_COL_MSK (0x00001000) 223 #define ALTERA_TSE_CMD_SW_RESET_MSK (0x00002000) 224 #define ALTERA_TSE_CMD_MHASH_SEL_MSK (0x00004000) 225 #define ALTERA_TSE_CMD_LOOPBACK_MSK (0x00008000) 226 /* Bits (18:16) = address select */ 227 #define ALTERA_TSE_CMD_TX_ADDR_SEL_MSK (0x00070000) 228 #define ALTERA_TSE_CMD_MAGIC_ENA_MSK (0x00080000) 229 #define ALTERA_TSE_CMD_SLEEP_MSK (0x00100000) 230 #define ALTERA_TSE_CMD_WAKEUP_MSK (0x00200000) 231 #define ALTERA_TSE_CMD_XOFF_GEN_MSK (0x00400000) 232 #define ALTERA_TSE_CMD_CNTL_FRM_ENA_MSK (0x00800000) 233 #define ALTERA_TSE_CMD_NO_LENGTH_CHECK_MSK (0x01000000) 234 #define ALTERA_TSE_CMD_ENA_10_MSK (0x02000000) 235 #define ALTERA_TSE_CMD_RX_ERR_DISC_MSK (0x04000000) 236 /* Bits (30..27) reserved */ 237 #define ALTERA_TSE_CMD_CNT_RESET_MSK (0x80000000) 238 239 #define ALTERA_TSE_TX_CMD_STAT_TX_SHIFT16 (0x00040000) 240 #define ALTERA_TSE_TX_CMD_STAT_OMIT_CRC (0x00020000) 241 242 #define ALTERA_TSE_RX_CMD_STAT_RX_SHIFT16 (0x02000000) 243 244 #define ALT_TSE_SW_RESET_WATCHDOG_CNTR 10000 245 #define ALT_TSE_SGDMA_BUSY_WATCHDOG_CNTR 90000000 246 247 /* Command_Config Register Bit Definitions */ 248 249 typedef volatile union __alt_tse_command_config { 250 unsigned int image; 251 struct { 252 unsigned int 253 transmit_enable:1, /* bit 0 */ 254 receive_enable:1, /* bit 1 */ 255 pause_frame_xon_gen:1, /* bit 2 */ 256 ethernet_speed:1, /* bit 3 */ 257 promiscuous_enable:1, /* bit 4 */ 258 pad_enable:1, /* bit 5 */ 259 crc_forward:1, /* bit 6 */ 260 pause_frame_forward:1, /* bit 7 */ 261 pause_frame_ignore:1, /* bit 8 */ 262 set_mac_address_on_tx:1, /* bit 9 */ 263 halfduplex_enable:1, /* bit 10 */ 264 excessive_collision:1, /* bit 11 */ 265 late_collision:1, /* bit 12 */ 266 software_reset:1, /* bit 13 */ 267 multicast_hash_mode_sel:1, /* bit 14 */ 268 loopback_enable:1, /* bit 15 */ 269 src_mac_addr_sel_on_tx:3, /* bit 18:16 */ 270 magic_packet_detect:1, /* bit 19 */ 271 sleep_mode_enable:1, /* bit 20 */ 272 wake_up_request:1, /* bit 21 */ 273 pause_frame_xoff_gen:1, /* bit 22 */ 274 control_frame_enable:1, /* bit 23 */ 275 payload_len_chk_disable:1, /* bit 24 */ 276 enable_10mbps_intf:1, /* bit 25 */ 277 rx_error_discard_enable:1, /* bit 26 */ 278 reserved_bits:4, /* bit 30:27 */ 279 self_clear_counter_reset:1; /* bit 31 */ 280 } __packed_1_ bits; 281 } __packed_1_ alt_tse_command_config; 282 283 /* Tx_Cmd_Stat Register Bit Definitions */ 284 285 typedef volatile union __alt_tse_tx_cmd_stat { 286 unsigned int image; 287 struct { 288 unsigned int reserved_lsbs:17, /* bit 16:0 */ 289 omit_crc:1, /* bit 17 */ 290 tx_shift16:1, /* bit 18 */ 291 reserved_msbs:13; /* bit 31:19 */ 292 293 } __packed_1_ bits; 294 } alt_tse_tx_cmd_stat; 295 296 /* Rx_Cmd_Stat Register Bit Definitions */ 297 298 typedef volatile union __alt_tse_rx_cmd_stat { 299 unsigned int image; 300 struct { 301 unsigned int reserved_lsbs:25, /* bit 24:0 */ 302 rx_shift16:1, /* bit 25 */ 303 reserved_msbs:6; /* bit 31:26 */ 304 305 } __packed_1_ bits; 306 } alt_tse_rx_cmd_stat; 307 308 struct alt_tse_mdio { 309 unsigned int control; /*PHY device operation control register */ 310 unsigned int status; /*PHY device operation status register */ 311 unsigned int phy_id1; /*Bits 31:16 of PHY identifier. */ 312 unsigned int phy_id2; /*Bits 15:0 of PHY identifier. */ 313 unsigned int auto_negotiation_advertisement; 314 unsigned int remote_partner_base_page_ability; 315 316 unsigned int reg6; 317 unsigned int reg7; 318 unsigned int reg8; 319 unsigned int reg9; 320 unsigned int rega; 321 unsigned int regb; 322 unsigned int regc; 323 unsigned int regd; 324 unsigned int rege; 325 unsigned int regf; 326 unsigned int reg10; 327 unsigned int reg11; 328 unsigned int reg12; 329 unsigned int reg13; 330 unsigned int reg14; 331 unsigned int reg15; 332 unsigned int reg16; 333 unsigned int reg17; 334 unsigned int reg18; 335 unsigned int reg19; 336 unsigned int reg1a; 337 unsigned int reg1b; 338 unsigned int reg1c; 339 unsigned int reg1d; 340 unsigned int reg1e; 341 unsigned int reg1f; 342 }; 343 344 /* MAC register Space */ 345 346 struct alt_tse_mac { 347 unsigned int megacore_revision; 348 unsigned int scratch_pad; 349 alt_tse_command_config command_config; 350 unsigned int mac_addr_0; 351 unsigned int mac_addr_1; 352 unsigned int max_frame_length; 353 unsigned int pause_quanta; 354 unsigned int rx_sel_empty_threshold; 355 unsigned int rx_sel_full_threshold; 356 unsigned int tx_sel_empty_threshold; 357 unsigned int tx_sel_full_threshold; 358 unsigned int rx_almost_empty_threshold; 359 unsigned int rx_almost_full_threshold; 360 unsigned int tx_almost_empty_threshold; 361 unsigned int tx_almost_full_threshold; 362 unsigned int mdio_phy0_addr; 363 unsigned int mdio_phy1_addr; 364 365 /* only if 100/1000 BaseX PCS, reserved otherwise */ 366 unsigned int reservedx44[5]; 367 368 unsigned int reg_read_access_status; 369 unsigned int min_tx_ipg_length; 370 371 /* IEEE 802.3 oEntity Managed Object Support */ 372 unsigned int aMACID_1; /*The MAC addresses */ 373 unsigned int aMACID_2; 374 unsigned int aFramesTransmittedOK; 375 unsigned int aFramesReceivedOK; 376 unsigned int aFramesCheckSequenceErrors; 377 unsigned int aAlignmentErrors; 378 unsigned int aOctetsTransmittedOK; 379 unsigned int aOctetsReceivedOK; 380 381 /* IEEE 802.3 oPausedEntity Managed Object Support */ 382 unsigned int aTxPAUSEMACCtrlFrames; 383 unsigned int aRxPAUSEMACCtrlFrames; 384 385 /* IETF MIB (MIB-II) Object Support */ 386 unsigned int ifInErrors; 387 unsigned int ifOutErrors; 388 unsigned int ifInUcastPkts; 389 unsigned int ifInMulticastPkts; 390 unsigned int ifInBroadcastPkts; 391 unsigned int ifOutDiscards; 392 unsigned int ifOutUcastPkts; 393 unsigned int ifOutMulticastPkts; 394 unsigned int ifOutBroadcastPkts; 395 396 /* IETF RMON MIB Object Support */ 397 unsigned int etherStatsDropEvent; 398 unsigned int etherStatsOctets; 399 unsigned int etherStatsPkts; 400 unsigned int etherStatsUndersizePkts; 401 unsigned int etherStatsOversizePkts; 402 unsigned int etherStatsPkts64Octets; 403 unsigned int etherStatsPkts65to127Octets; 404 unsigned int etherStatsPkts128to255Octets; 405 unsigned int etherStatsPkts256to511Octets; 406 unsigned int etherStatsPkts512to1023Octets; 407 unsigned int etherStatsPkts1024to1518Octets; 408 409 unsigned int etherStatsPkts1519toXOctets; 410 unsigned int etherStatsJabbers; 411 unsigned int etherStatsFragments; 412 413 unsigned int reservedxE4; 414 415 /*FIFO control register. */ 416 alt_tse_tx_cmd_stat tx_cmd_stat; 417 alt_tse_rx_cmd_stat rx_cmd_stat; 418 419 unsigned int ipaccTxConf; 420 unsigned int ipaccRxConf; 421 unsigned int ipaccRxStat; 422 unsigned int ipaccRxStatSum; 423 424 /*Multicast address resolution table */ 425 unsigned int hash_table[64]; 426 427 /*Registers 0 to 31 within PHY device 0/1 */ 428 struct alt_tse_mdio mdio_phy0; 429 struct alt_tse_mdio mdio_phy1; 430 431 /*4 Supplemental MAC Addresses */ 432 unsigned int supp_mac_addr_0_0; 433 unsigned int supp_mac_addr_0_1; 434 unsigned int supp_mac_addr_1_0; 435 unsigned int supp_mac_addr_1_1; 436 unsigned int supp_mac_addr_2_0; 437 unsigned int supp_mac_addr_2_1; 438 unsigned int supp_mac_addr_3_0; 439 unsigned int supp_mac_addr_3_1; 440 441 unsigned int reservedx320[56]; 442 }; 443 444 /* flags: TSE MII modes */ 445 /* GMII/MII = 0 */ 446 /* RGMII = 1 */ 447 /* RGMII_ID = 2 */ 448 /* RGMII_TXID = 3 */ 449 /* RGMII_RXID = 4 */ 450 /* SGMII = 5 */ 451 struct altera_tse_priv { 452 char devname[16]; 453 volatile struct alt_tse_mac *mac_dev; 454 volatile struct alt_sgdma_registers *sgdma_rx; 455 volatile struct alt_sgdma_registers *sgdma_tx; 456 unsigned int rx_sgdma_irq; 457 unsigned int tx_sgdma_irq; 458 unsigned int has_descriptor_mem; 459 unsigned int descriptor_mem_base; 460 unsigned int descriptor_mem_size; 461 volatile struct alt_sgdma_descriptor *rx_desc; 462 volatile struct alt_sgdma_descriptor *tx_desc; 463 volatile unsigned char *rx_buf; 464 struct phy_info *phyinfo; 465 unsigned int phyaddr; 466 unsigned int flags; 467 unsigned int link; 468 unsigned int duplexity; 469 unsigned int speed; 470 }; 471 472 /* Phy stuff continued */ 473 /* 474 * struct phy_cmd: A command for reading or writing a PHY register 475 * 476 * mii_reg: The register to read or write 477 * 478 * mii_data: For writes, the value to put in the register. 479 * A value of -1 indicates this is a read. 480 * 481 * funct: A function pointer which is invoked for each command. 482 * For reads, this function will be passed the value read 483 * from the PHY, and process it. 484 * For writes, the result of this function will be written 485 * to the PHY register 486 */ 487 struct phy_cmd { 488 uint mii_reg; 489 uint mii_data; 490 uint(*funct) (uint mii_reg, struct altera_tse_priv *priv); 491 }; 492 #endif /* _ALTERA_TSE_H_ */ 493