1c960b13eSThomas Chou /* 2c960b13eSThomas Chou * Altera 10/100/1000 triple speed ethernet mac 3c960b13eSThomas Chou * 4c960b13eSThomas Chou * Copyright (C) 2008 Altera Corporation. 5c960b13eSThomas Chou * Copyright (C) 2010 Thomas Chou <thomas@wytron.com.tw> 6c960b13eSThomas Chou * 7c960b13eSThomas Chou * This program is free software; you can redistribute it and/or modify 8c960b13eSThomas Chou * it under the terms of the GNU General Public License version 2 as 9c960b13eSThomas Chou * published by the Free Software Foundation. 10c960b13eSThomas Chou */ 11c960b13eSThomas Chou #ifndef _ALTERA_TSE_H_ 12c960b13eSThomas Chou #define _ALTERA_TSE_H_ 13c960b13eSThomas Chou 14c960b13eSThomas Chou #define __packed_1_ __attribute__ ((packed, aligned(1))) 15c960b13eSThomas Chou 16c960b13eSThomas Chou /* SGDMA Stuff */ 17c960b13eSThomas Chou #define ALT_SGDMA_STATUS_ERROR_MSK (0x00000001) 18c960b13eSThomas Chou #define ALT_SGDMA_STATUS_EOP_ENCOUNTERED_MSK (0x00000002) 19c960b13eSThomas Chou #define ALT_SGDMA_STATUS_DESC_COMPLETED_MSK (0x00000004) 20c960b13eSThomas Chou #define ALT_SGDMA_STATUS_CHAIN_COMPLETED_MSK (0x00000008) 21c960b13eSThomas Chou #define ALT_SGDMA_STATUS_BUSY_MSK (0x00000010) 22c960b13eSThomas Chou 23c960b13eSThomas Chou #define ALT_SGDMA_CONTROL_RUN_MSK (0x00000020) 24c960b13eSThomas Chou #define ALT_SGDMA_CONTROL_STOP_DMA_ER_MSK (0x00000040) 25c960b13eSThomas Chou #define ALT_SGDMA_CONTROL_SOFTWARERESET_MSK (0x00010000) 26c960b13eSThomas Chou 27c960b13eSThomas Chou #define ALTERA_TSE_SGDMA_INTR_MASK (ALT_SGDMA_CONTROL_IE_CHAIN_COMPLETED_MSK \ 28c960b13eSThomas Chou | ALT_SGDMA_STATUS_DESC_COMPLETED_MSK \ 29c960b13eSThomas Chou | ALT_SGDMA_CONTROL_IE_GLOBAL_MSK) 30c960b13eSThomas Chou 31c960b13eSThomas Chou /* 32c960b13eSThomas Chou * Descriptor control bit masks & offsets 33c960b13eSThomas Chou * 34c960b13eSThomas Chou * Note: The control byte physically occupies bits [31:24] in memory. 35c960b13eSThomas Chou * The following bit-offsets are expressed relative to the LSB of 36c960b13eSThomas Chou * the control register bitfield. 37c960b13eSThomas Chou */ 38c960b13eSThomas Chou #define ALT_SGDMA_DESCRIPTOR_CONTROL_GENERATE_EOP_MSK (0x00000001) 39c960b13eSThomas Chou #define ALT_SGDMA_DESCRIPTOR_CONTROL_READ_FIXED_ADDRESS_MSK (0x00000002) 40c960b13eSThomas Chou #define ALT_SGDMA_DESCRIPTOR_CONTROL_WRITE_FIXED_ADDRESS_MSK (0x00000004) 41c960b13eSThomas Chou #define ALT_SGDMA_DESCRIPTOR_CONTROL_ATLANTIC_CHANNEL_MSK (0x00000008) 42c960b13eSThomas Chou #define ALT_SGDMA_DESCRIPTOR_CONTROL_OWNED_BY_HW_MSK (0x00000080) 43c960b13eSThomas Chou 44c960b13eSThomas Chou /* 45c960b13eSThomas Chou * Descriptor status bit masks & offsets 46c960b13eSThomas Chou * 47c960b13eSThomas Chou * Note: The status byte physically occupies bits [23:16] in memory. 48c960b13eSThomas Chou * The following bit-offsets are expressed relative to the LSB of 49c960b13eSThomas Chou * the status register bitfield. 50c960b13eSThomas Chou */ 51c960b13eSThomas Chou #define ALT_SGDMA_DESCRIPTOR_STATUS_E_CRC_MSK (0x00000001) 52c960b13eSThomas Chou #define ALT_SGDMA_DESCRIPTOR_STATUS_E_PARITY_MSK (0x00000002) 53c960b13eSThomas Chou #define ALT_SGDMA_DESCRIPTOR_STATUS_E_OVERFLOW_MSK (0x00000004) 54c960b13eSThomas Chou #define ALT_SGDMA_DESCRIPTOR_STATUS_E_SYNC_MSK (0x00000008) 55c960b13eSThomas Chou #define ALT_SGDMA_DESCRIPTOR_STATUS_E_UEOP_MSK (0x00000010) 56c960b13eSThomas Chou #define ALT_SGDMA_DESCRIPTOR_STATUS_E_MEOP_MSK (0x00000020) 57c960b13eSThomas Chou #define ALT_SGDMA_DESCRIPTOR_STATUS_E_MSOP_MSK (0x00000040) 58c960b13eSThomas Chou #define ALT_SGDMA_DESCRIPTOR_STATUS_TERMINATED_BY_EOP_MSK (0x00000080) 59c960b13eSThomas Chou #define ALT_SGDMA_DESCRIPTOR_STATUS_ERROR_MSK (0x0000007F) 60c960b13eSThomas Chou 61c960b13eSThomas Chou /* 62c960b13eSThomas Chou * The SGDMA controller buffer descriptor allocates 63c960b13eSThomas Chou * 64 bits for each address. To support ANSI C, the 64c960b13eSThomas Chou * struct implementing a descriptor places 32-bits 65c960b13eSThomas Chou * of padding directly above each address; each pad must 66c960b13eSThomas Chou * be cleared when initializing a descriptor. 67c960b13eSThomas Chou */ 68c960b13eSThomas Chou 69c960b13eSThomas Chou /* 70c960b13eSThomas Chou * Buffer Descriptor data structure 71c960b13eSThomas Chou * 72c960b13eSThomas Chou */ 73c960b13eSThomas Chou struct alt_sgdma_descriptor { 74*96fa1e43SThomas Chou unsigned int source; /* the address of data to be read. */ 75c960b13eSThomas Chou unsigned int source_pad; 76c960b13eSThomas Chou 77*96fa1e43SThomas Chou unsigned int destination; /* the address to write data */ 78c960b13eSThomas Chou unsigned int destination_pad; 79c960b13eSThomas Chou 80*96fa1e43SThomas Chou unsigned int next; /* the next descriptor in the list. */ 81c960b13eSThomas Chou unsigned int next_pad; 82c960b13eSThomas Chou 83c960b13eSThomas Chou unsigned short bytes_to_transfer; /* the number of bytes to transfer */ 84c960b13eSThomas Chou unsigned char read_burst; 85c960b13eSThomas Chou unsigned char write_burst; 86c960b13eSThomas Chou 87c960b13eSThomas Chou unsigned short actual_bytes_transferred;/* bytes transferred by DMA */ 88c960b13eSThomas Chou unsigned char descriptor_status; 89c960b13eSThomas Chou unsigned char descriptor_control; 90c960b13eSThomas Chou 91c960b13eSThomas Chou } __packed_1_; 92c960b13eSThomas Chou 93c960b13eSThomas Chou /* SG-DMA Control/Status Slave registers map */ 94c960b13eSThomas Chou 95c960b13eSThomas Chou struct alt_sgdma_registers { 96c960b13eSThomas Chou unsigned int status; 97c960b13eSThomas Chou unsigned int status_pad[3]; 98c960b13eSThomas Chou unsigned int control; 99c960b13eSThomas Chou unsigned int control_pad[3]; 100c960b13eSThomas Chou unsigned int next_descriptor_pointer; 101c960b13eSThomas Chou unsigned int descriptor_pad[3]; 102c960b13eSThomas Chou }; 103c960b13eSThomas Chou 104c960b13eSThomas Chou /* TSE Stuff */ 105c960b13eSThomas Chou #define ALTERA_TSE_CMD_TX_ENA_MSK (0x00000001) 106c960b13eSThomas Chou #define ALTERA_TSE_CMD_RX_ENA_MSK (0x00000002) 107c960b13eSThomas Chou #define ALTERA_TSE_CMD_XON_GEN_MSK (0x00000004) 108c960b13eSThomas Chou #define ALTERA_TSE_CMD_ETH_SPEED_MSK (0x00000008) 109c960b13eSThomas Chou #define ALTERA_TSE_CMD_PROMIS_EN_MSK (0x00000010) 110c960b13eSThomas Chou #define ALTERA_TSE_CMD_PAD_EN_MSK (0x00000020) 111c960b13eSThomas Chou #define ALTERA_TSE_CMD_CRC_FWD_MSK (0x00000040) 112c960b13eSThomas Chou #define ALTERA_TSE_CMD_PAUSE_FWD_MSK (0x00000080) 113c960b13eSThomas Chou #define ALTERA_TSE_CMD_PAUSE_IGNORE_MSK (0x00000100) 114c960b13eSThomas Chou #define ALTERA_TSE_CMD_TX_ADDR_INS_MSK (0x00000200) 115c960b13eSThomas Chou #define ALTERA_TSE_CMD_HD_ENA_MSK (0x00000400) 116c960b13eSThomas Chou #define ALTERA_TSE_CMD_EXCESS_COL_MSK (0x00000800) 117c960b13eSThomas Chou #define ALTERA_TSE_CMD_LATE_COL_MSK (0x00001000) 118c960b13eSThomas Chou #define ALTERA_TSE_CMD_SW_RESET_MSK (0x00002000) 119c960b13eSThomas Chou #define ALTERA_TSE_CMD_MHASH_SEL_MSK (0x00004000) 120c960b13eSThomas Chou #define ALTERA_TSE_CMD_LOOPBACK_MSK (0x00008000) 121c960b13eSThomas Chou /* Bits (18:16) = address select */ 122c960b13eSThomas Chou #define ALTERA_TSE_CMD_TX_ADDR_SEL_MSK (0x00070000) 123c960b13eSThomas Chou #define ALTERA_TSE_CMD_MAGIC_ENA_MSK (0x00080000) 124c960b13eSThomas Chou #define ALTERA_TSE_CMD_SLEEP_MSK (0x00100000) 125c960b13eSThomas Chou #define ALTERA_TSE_CMD_WAKEUP_MSK (0x00200000) 126c960b13eSThomas Chou #define ALTERA_TSE_CMD_XOFF_GEN_MSK (0x00400000) 127c960b13eSThomas Chou #define ALTERA_TSE_CMD_CNTL_FRM_ENA_MSK (0x00800000) 128c960b13eSThomas Chou #define ALTERA_TSE_CMD_NO_LENGTH_CHECK_MSK (0x01000000) 129c960b13eSThomas Chou #define ALTERA_TSE_CMD_ENA_10_MSK (0x02000000) 130c960b13eSThomas Chou #define ALTERA_TSE_CMD_RX_ERR_DISC_MSK (0x04000000) 131c960b13eSThomas Chou /* Bits (30..27) reserved */ 132c960b13eSThomas Chou #define ALTERA_TSE_CMD_CNT_RESET_MSK (0x80000000) 133c960b13eSThomas Chou 134c960b13eSThomas Chou #define ALTERA_TSE_TX_CMD_STAT_TX_SHIFT16 (0x00040000) 135c960b13eSThomas Chou #define ALTERA_TSE_TX_CMD_STAT_OMIT_CRC (0x00020000) 136c960b13eSThomas Chou 137c960b13eSThomas Chou #define ALTERA_TSE_RX_CMD_STAT_RX_SHIFT16 (0x02000000) 138c960b13eSThomas Chou 139*96fa1e43SThomas Chou #define ALT_TSE_SW_RESET_TIMEOUT (3 * CONFIG_SYS_HZ) 140*96fa1e43SThomas Chou #define ALT_TSE_SGDMA_BUSY_TIMEOUT (3 * CONFIG_SYS_HZ) 141c960b13eSThomas Chou 142c960b13eSThomas Chou /* MAC register Space */ 143c960b13eSThomas Chou 144c960b13eSThomas Chou struct alt_tse_mac { 145c960b13eSThomas Chou unsigned int megacore_revision; 146c960b13eSThomas Chou unsigned int scratch_pad; 147*96fa1e43SThomas Chou unsigned int command_config; 148c960b13eSThomas Chou unsigned int mac_addr_0; 149c960b13eSThomas Chou unsigned int mac_addr_1; 150c960b13eSThomas Chou unsigned int max_frame_length; 151c960b13eSThomas Chou unsigned int pause_quanta; 152c960b13eSThomas Chou unsigned int rx_sel_empty_threshold; 153c960b13eSThomas Chou unsigned int rx_sel_full_threshold; 154c960b13eSThomas Chou unsigned int tx_sel_empty_threshold; 155c960b13eSThomas Chou unsigned int tx_sel_full_threshold; 156c960b13eSThomas Chou unsigned int rx_almost_empty_threshold; 157c960b13eSThomas Chou unsigned int rx_almost_full_threshold; 158c960b13eSThomas Chou unsigned int tx_almost_empty_threshold; 159c960b13eSThomas Chou unsigned int tx_almost_full_threshold; 160c960b13eSThomas Chou unsigned int mdio_phy0_addr; 161c960b13eSThomas Chou unsigned int mdio_phy1_addr; 162c960b13eSThomas Chou 163c960b13eSThomas Chou /* only if 100/1000 BaseX PCS, reserved otherwise */ 164c960b13eSThomas Chou unsigned int reservedx44[5]; 165c960b13eSThomas Chou 166c960b13eSThomas Chou unsigned int reg_read_access_status; 167c960b13eSThomas Chou unsigned int min_tx_ipg_length; 168c960b13eSThomas Chou 169c960b13eSThomas Chou /* IEEE 802.3 oEntity Managed Object Support */ 170c960b13eSThomas Chou unsigned int aMACID_1; /*The MAC addresses */ 171c960b13eSThomas Chou unsigned int aMACID_2; 172c960b13eSThomas Chou unsigned int aFramesTransmittedOK; 173c960b13eSThomas Chou unsigned int aFramesReceivedOK; 174c960b13eSThomas Chou unsigned int aFramesCheckSequenceErrors; 175c960b13eSThomas Chou unsigned int aAlignmentErrors; 176c960b13eSThomas Chou unsigned int aOctetsTransmittedOK; 177c960b13eSThomas Chou unsigned int aOctetsReceivedOK; 178c960b13eSThomas Chou 179c960b13eSThomas Chou /* IEEE 802.3 oPausedEntity Managed Object Support */ 180c960b13eSThomas Chou unsigned int aTxPAUSEMACCtrlFrames; 181c960b13eSThomas Chou unsigned int aRxPAUSEMACCtrlFrames; 182c960b13eSThomas Chou 183c960b13eSThomas Chou /* IETF MIB (MIB-II) Object Support */ 184c960b13eSThomas Chou unsigned int ifInErrors; 185c960b13eSThomas Chou unsigned int ifOutErrors; 186c960b13eSThomas Chou unsigned int ifInUcastPkts; 187c960b13eSThomas Chou unsigned int ifInMulticastPkts; 188c960b13eSThomas Chou unsigned int ifInBroadcastPkts; 189c960b13eSThomas Chou unsigned int ifOutDiscards; 190c960b13eSThomas Chou unsigned int ifOutUcastPkts; 191c960b13eSThomas Chou unsigned int ifOutMulticastPkts; 192c960b13eSThomas Chou unsigned int ifOutBroadcastPkts; 193c960b13eSThomas Chou 194c960b13eSThomas Chou /* IETF RMON MIB Object Support */ 195c960b13eSThomas Chou unsigned int etherStatsDropEvent; 196c960b13eSThomas Chou unsigned int etherStatsOctets; 197c960b13eSThomas Chou unsigned int etherStatsPkts; 198c960b13eSThomas Chou unsigned int etherStatsUndersizePkts; 199c960b13eSThomas Chou unsigned int etherStatsOversizePkts; 200c960b13eSThomas Chou unsigned int etherStatsPkts64Octets; 201c960b13eSThomas Chou unsigned int etherStatsPkts65to127Octets; 202c960b13eSThomas Chou unsigned int etherStatsPkts128to255Octets; 203c960b13eSThomas Chou unsigned int etherStatsPkts256to511Octets; 204c960b13eSThomas Chou unsigned int etherStatsPkts512to1023Octets; 205c960b13eSThomas Chou unsigned int etherStatsPkts1024to1518Octets; 206c960b13eSThomas Chou 207c960b13eSThomas Chou unsigned int etherStatsPkts1519toXOctets; 208c960b13eSThomas Chou unsigned int etherStatsJabbers; 209c960b13eSThomas Chou unsigned int etherStatsFragments; 210c960b13eSThomas Chou 211c960b13eSThomas Chou unsigned int reservedxE4; 212c960b13eSThomas Chou 213c960b13eSThomas Chou /*FIFO control register. */ 214*96fa1e43SThomas Chou unsigned int tx_cmd_stat; 215*96fa1e43SThomas Chou unsigned int rx_cmd_stat; 216c960b13eSThomas Chou 217c960b13eSThomas Chou unsigned int ipaccTxConf; 218c960b13eSThomas Chou unsigned int ipaccRxConf; 219c960b13eSThomas Chou unsigned int ipaccRxStat; 220c960b13eSThomas Chou unsigned int ipaccRxStatSum; 221c960b13eSThomas Chou 222c960b13eSThomas Chou /*Multicast address resolution table */ 223c960b13eSThomas Chou unsigned int hash_table[64]; 224c960b13eSThomas Chou 225c960b13eSThomas Chou /*Registers 0 to 31 within PHY device 0/1 */ 226*96fa1e43SThomas Chou unsigned int mdio_phy0[0x20]; 227*96fa1e43SThomas Chou unsigned int mdio_phy1[0x20]; 228c960b13eSThomas Chou 229c960b13eSThomas Chou /*4 Supplemental MAC Addresses */ 230c960b13eSThomas Chou unsigned int supp_mac_addr_0_0; 231c960b13eSThomas Chou unsigned int supp_mac_addr_0_1; 232c960b13eSThomas Chou unsigned int supp_mac_addr_1_0; 233c960b13eSThomas Chou unsigned int supp_mac_addr_1_1; 234c960b13eSThomas Chou unsigned int supp_mac_addr_2_0; 235c960b13eSThomas Chou unsigned int supp_mac_addr_2_1; 236c960b13eSThomas Chou unsigned int supp_mac_addr_3_0; 237c960b13eSThomas Chou unsigned int supp_mac_addr_3_1; 238c960b13eSThomas Chou 239c960b13eSThomas Chou unsigned int reservedx320[56]; 240c960b13eSThomas Chou }; 241c960b13eSThomas Chou 242c960b13eSThomas Chou struct altera_tse_priv { 243*96fa1e43SThomas Chou struct alt_tse_mac *mac_dev; 244*96fa1e43SThomas Chou struct alt_sgdma_registers *sgdma_rx; 245*96fa1e43SThomas Chou struct alt_sgdma_registers *sgdma_tx; 246*96fa1e43SThomas Chou unsigned int rx_fifo_depth; 247*96fa1e43SThomas Chou unsigned int tx_fifo_depth; 248*96fa1e43SThomas Chou struct alt_sgdma_descriptor *rx_desc; 249*96fa1e43SThomas Chou struct alt_sgdma_descriptor *tx_desc; 250*96fa1e43SThomas Chou unsigned char *rx_buf; 251c960b13eSThomas Chou unsigned int phyaddr; 252*96fa1e43SThomas Chou unsigned int interface; 253*96fa1e43SThomas Chou struct phy_device *phydev; 254*96fa1e43SThomas Chou struct mii_dev *bus; 255c960b13eSThomas Chou }; 256c960b13eSThomas Chou 257c960b13eSThomas Chou #endif /* _ALTERA_TSE_H_ */ 258